VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66935

Last change on this file since 66935 was 66935, checked in by vboxsync, 8 years ago

IEM: Implemented vmovlpd Vq,Hq,Mq (VEX.66.0F 12 mod!=3).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 19.1 KB
Line 
1/* $Id: bs3-cpu-generated-1.h 66935 2017-05-17 12:09:30Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, common header file.
4 */
5
6/*
7 * Copyright (C) 2007-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28#ifndef ___bs3_cpu_generated_1_h___
29#define ___bs3_cpu_generated_1_h___
30
31#include <bs3kit.h>
32#include <iprt/assert.h>
33
34
35/**
36 * Operand details.
37 *
38 * Currently simply using the encoding from the reference manuals.
39 */
40typedef enum BS3CG1OP
41{
42 BS3CG1OP_INVALID = 0,
43
44 BS3CG1OP_Eb,
45 BS3CG1OP_Ev,
46 BS3CG1OP_Wss,
47 BS3CG1OP_Wss_WO,
48 BS3CG1OP_Wsd,
49 BS3CG1OP_Wsd_WO,
50 BS3CG1OP_Wps,
51 BS3CG1OP_Wps_WO,
52 BS3CG1OP_Wpd,
53 BS3CG1OP_Wpd_WO,
54 BS3CG1OP_Wdq,
55 BS3CG1OP_Wdq_WO,
56 BS3CG1OP_Wq,
57 BS3CG1OP_Wq_WO,
58 BS3CG1OP_WqZxReg_WO,
59
60 BS3CG1OP_Gb,
61 BS3CG1OP_Gv,
62 BS3CG1OP_Gv_RO,
63 BS3CG1OP_HdqCss,
64 BS3CG1OP_HdqCsd,
65 BS3CG1OP_HdqCq,
66 BS3CG1OP_HqHi,
67 BS3CG1OP_Nq,
68 BS3CG1OP_Pq_WO,
69 BS3CG1OP_Uq,
70 BS3CG1OP_UqHi,
71 BS3CG1OP_Uss,
72 BS3CG1OP_Uss_WO,
73 BS3CG1OP_Usd,
74 BS3CG1OP_Usd_WO,
75 BS3CG1OP_Vss,
76 BS3CG1OP_Vss_WO,
77 BS3CG1OP_VssZx_WO,
78 BS3CG1OP_Vsd,
79 BS3CG1OP_Vsd_WO,
80 BS3CG1OP_VsdZx_WO,
81 BS3CG1OP_Vps,
82 BS3CG1OP_Vps_WO,
83 BS3CG1OP_Vpd,
84 BS3CG1OP_Vpd_WO,
85 BS3CG1OP_Vq,
86 BS3CG1OP_Vq_WO,
87 BS3CG1OP_Vdq,
88 BS3CG1OP_Vdq_WO,
89 BS3CG1OP_VqHi,
90 BS3CG1OP_VqHi_WO,
91 BS3CG1OP_VqZx_WO,
92
93 BS3CG1OP_Ib,
94 BS3CG1OP_Iz,
95
96 BS3CG1OP_AL,
97 BS3CG1OP_rAX,
98
99 BS3CG1OP_Ma,
100 BS3CG1OP_Mb_RO,
101 BS3CG1OP_Md,
102 BS3CG1OP_Md_RO,
103 BS3CG1OP_Md_WO,
104 BS3CG1OP_Mq,
105 BS3CG1OP_Mq_WO,
106
107 BS3CG1OP_END
108} BS3CG1OP;
109/** Pointer to a const operand enum. */
110typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
111
112
113/**
114 * Instruction encoding format.
115 *
116 * This duplicates some of the info in the operand array, however it makes it
117 * easier to figure out encoding variations.
118 */
119typedef enum BS3CG1ENC
120{
121 BS3CG1ENC_INVALID = 0,
122
123 BS3CG1ENC_MODRM_Eb_Gb,
124 BS3CG1ENC_MODRM_Ev_Gv,
125 BS3CG1ENC_MODRM_Wss_WO_Vss,
126 BS3CG1ENC_MODRM_Wsd_WO_Vsd,
127 BS3CG1ENC_MODRM_Wps_WO_Vps,
128 BS3CG1ENC_MODRM_Wpd_WO_Vpd,
129 BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
130
131 BS3CG1ENC_MODRM_Gb_Eb,
132 BS3CG1ENC_MODRM_Gv_Ev,
133 BS3CG1ENC_MODRM_Gv_RO_Ma, /**< bound instruction */
134 BS3CG1ENC_MODRM_Pq_WO_Uq,
135 BS3CG1ENC_MODRM_Vq_WO_UqHi,
136 BS3CG1ENC_MODRM_Vq_WO_Mq,
137 BS3CG1ENC_MODRM_VqHi_WO_Uq,
138 BS3CG1ENC_MODRM_VqHi_WO_Mq,
139 BS3CG1ENC_MODRM_Vdq_WO_Wdq,
140 BS3CG1ENC_MODRM_Vpd_WO_Wpd,
141 BS3CG1ENC_MODRM_Vps_WO_Wps,
142 BS3CG1ENC_MODRM_VssZx_WO_Wss,
143 BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
144 BS3CG1ENC_MODRM_VqZx_WO_Wq,
145 BS3CG1ENC_MODRM_VqZx_WO_Nq,
146 BS3CG1ENC_MODRM_Mb_RO,
147 BS3CG1ENC_MODRM_Md_RO,
148 BS3CG1ENC_MODRM_Md_WO,
149 BS3CG1ENC_MODRM_Mq_WO_Vq,
150 BS3CG1ENC_MODRM_Mq_WO_VqHi,
151
152 BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
153 BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
154 BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss,
155 BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd,
156 BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_UqHi,
157 BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_Mq,
158 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq,
159 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
160 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
161 BS3CG1ENC_VEX_MODRM_Md_WO,
162 BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
163 BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd,
164 BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss,
165 BS3CG1ENC_VEX_MODRM_Usd_WO_HdqCsd_Vsd,
166 BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
167 BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
168
169 BS3CG1ENC_FIXED,
170 BS3CG1ENC_FIXED_AL_Ib,
171 BS3CG1ENC_FIXED_rAX_Iz,
172
173
174 BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
175 BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
176 BS3CG1ENC_VEX_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
177 BS3CG1ENC_VEX_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
178
179 BS3CG1ENC_END
180} BS3CG1ENC;
181
182
183/**
184 * Prefix sensitivitiy kind.
185 */
186typedef enum BS3CG1PFXKIND
187{
188 BS3CG1PFXKIND_INVALID = 0,
189
190 BS3CG1PFXKIND_NO_F2_F3_66, /**< No 66, F2 or F3 prefixes allowed as that would alter the meaning. */
191 BS3CG1PFXKIND_REQ_F2, /**< Requires F2 (REPNE) prefix as part of the instr encoding. */
192 BS3CG1PFXKIND_REQ_F3, /**< Requires F3 (REPE) prefix as part of the instr encoding. */
193 BS3CG1PFXKIND_REQ_66, /**< Requires 66 (OP SIZE) prefix as part of the instr encoding. */
194
195 /** @todo more work to be done here... */
196 BS3CG1PFXKIND_MODRM,
197 BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
198
199 BS3CG1PFXKIND_END
200} BS3CG1PFXKIND;
201
202/**
203 * CPU selection or CPU ID.
204 */
205typedef enum BS3CG1CPU
206{
207 /** Works with an CPU. */
208 BS3CG1CPU_ANY = 0,
209 BS3CG1CPU_GE_80186,
210 BS3CG1CPU_GE_80286,
211 BS3CG1CPU_GE_80386,
212 BS3CG1CPU_GE_80486,
213 BS3CG1CPU_GE_Pentium,
214
215 BS3CG1CPU_SSE,
216 BS3CG1CPU_SSE2,
217 BS3CG1CPU_SSE3,
218 BS3CG1CPU_AVX,
219 BS3CG1CPU_AVX2,
220 BS3CG1CPU_CLFSH,
221 BS3CG1CPU_CLFLUSHOPT,
222
223 BS3CG1CPU_END
224} BS3CG1CPU;
225
226
227/**
228 * SSE & AVX exception types.
229 */
230typedef enum BS3CG1XCPTTYPE
231{
232 BS3CG1XCPTTYPE_NONE = 0,
233 /* SSE: */
234 BS3CG1XCPTTYPE_1,
235 BS3CG1XCPTTYPE_2,
236 BS3CG1XCPTTYPE_3,
237 BS3CG1XCPTTYPE_4,
238 BS3CG1XCPTTYPE_4UA,
239 BS3CG1XCPTTYPE_5,
240 BS3CG1XCPTTYPE_5LZ,
241 BS3CG1XCPTTYPE_6,
242 BS3CG1XCPTTYPE_7,
243 BS3CG1XCPTTYPE_7LZ,
244 BS3CG1XCPTTYPE_8,
245 BS3CG1XCPTTYPE_11,
246 BS3CG1XCPTTYPE_12,
247 /* EVEX: */
248 BS3CG1XCPTTYPE_E1,
249 BS3CG1XCPTTYPE_E1NF,
250 BS3CG1XCPTTYPE_E2,
251 BS3CG1XCPTTYPE_E3,
252 BS3CG1XCPTTYPE_E3NF,
253 BS3CG1XCPTTYPE_E4,
254 BS3CG1XCPTTYPE_E4NF,
255 BS3CG1XCPTTYPE_E5,
256 BS3CG1XCPTTYPE_E5NF,
257 BS3CG1XCPTTYPE_E6,
258 BS3CG1XCPTTYPE_E6NF,
259 BS3CG1XCPTTYPE_E7NF,
260 BS3CG1XCPTTYPE_E9,
261 BS3CG1XCPTTYPE_E9NF,
262 BS3CG1XCPTTYPE_E10,
263 BS3CG1XCPTTYPE_E11,
264 BS3CG1XCPTTYPE_E12,
265 BS3CG1XCPTTYPE_E12NF,
266 BS3CG1XCPTTYPE_END
267} BS3CG1XCPTTYPE;
268AssertCompile(BS3CG1XCPTTYPE_END <= 32);
269
270
271/**
272 * Generated instruction info.
273 */
274typedef struct BS3CG1INSTR
275{
276 /** The opcode size. */
277 uint32_t cbOpcodes : 2;
278 /** The number of operands. */
279 uint32_t cOperands : 2;
280 /** The length of the mnemonic. */
281 uint32_t cchMnemonic : 4;
282 /** Whether to advance the mnemonic array pointer. */
283 uint32_t fAdvanceMnemonic : 1;
284 /** Offset into g_abBs3Cg1Tests of the first test. */
285 uint32_t offTests : 23;
286 /** BS3CG1ENC values. */
287 uint32_t enmEncoding : 10;
288 /** BS3CG1PFXKIND values. */
289 uint32_t enmPrefixKind : 4;
290 /** CPU test / CPU ID bit test (BS3CG1CPU). */
291 uint32_t enmCpuTest : 6;
292 /** Exception type (BS3CG1XCPTTYPE) */
293 uint32_t enmXcptType : 5;
294 /** Currently unused bits. */
295 uint32_t uUnused : 6;
296 /** BS3CG1INSTR_F_XXX. */
297 uint32_t fFlags;
298} BS3CG1INSTR;
299AssertCompileSize(BS3CG1INSTR, 12);
300/** Pointer to a const instruction. */
301typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
302
303
304/** @name BS3CG1INSTR_F_XXX
305 * @{ */
306/** Defaults to SS rather than DS. */
307#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
308/** Invalid instruction in 64-bit mode. */
309#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
310/** Unused instruction. */
311#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
312/** Invalid instruction. */
313#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
314/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
315 * Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
316#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
317/** @} */
318
319
320/**
321 * Test header.
322 */
323typedef struct BS3CG1TESTHDR
324{
325 /** The size of the selector program in bytes.
326 * This is also the offset of the input context modification program. */
327 uint32_t cbSelector : 8;
328 /** The size of the input context modification program in bytes.
329 * This immediately follows the selector program. */
330 uint32_t cbInput : 12;
331 /** The size of the output context modification program in bytes.
332 * This immediately follows the input context modification program. The
333 * program takes the result of the input program as starting point. */
334 uint32_t cbOutput : 11;
335 /** Indicates whether this is the last test or not. */
336 uint32_t fLast : 1;
337} BS3CG1TESTHDR;
338AssertCompileSize(BS3CG1TESTHDR, 4);
339/** Pointer to a const test header. */
340typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
341
342/** @name Opcode format for the BS3CG1 context modifier.
343 *
344 * Used by both the input and output context programs.
345 *
346 * The most common operations are encoded as a single byte opcode followed by
347 * one or more immediate bytes with data.
348 *
349 * @{ */
350#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
351#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
352#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
353#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
354#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
355#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
356#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
357#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
358#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /**< Separate byte encoding the value size following any destination escape byte. */
359
360#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
361#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
362#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
363#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
364#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /**< Separate byte giving the destination follows immediately. */
365
366#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /**< Whether to sign-extend (set) the immediate value. */
367
368#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
369#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /**< Simple assignment operator (=) */
370#define BS3CG1_CTXOP_OR UINT8_C(0x40) /**< OR assignment operator (|=). */
371#define BS3CG1_CTXOP_AND UINT8_C(0x80) /**< AND assignment operator (&=). */
372#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /**< AND assignment operator of the inverted value (&~=). */
373/** @} */
374
375/**
376 * Escaped destination values
377 *
378 * These are just uppercased versions of TestInOut.kdFields, where dots are
379 * replaced by underscores.
380 */
381typedef enum BS3CG1DST
382{
383 BS3CG1DST_INVALID = 0,
384 /* Operands. */
385 BS3CG1DST_OP1,
386 BS3CG1DST_OP2,
387 BS3CG1DST_OP3,
388 BS3CG1DST_OP4,
389 /* Flags. */
390 BS3CG1DST_EFL,
391 BS3CG1DST_EFL_UNDEF, /**< Special field only valid in output context modifiers: EFLAGS |= Value & Ouput.EFLAGS; */
392 /* 8-bit GPRs. */
393 BS3CG1DST_AL,
394 BS3CG1DST_CL,
395 BS3CG1DST_DL,
396 BS3CG1DST_BL,
397 BS3CG1DST_AH,
398 BS3CG1DST_CH,
399 BS3CG1DST_DH,
400 BS3CG1DST_BH,
401 BS3CG1DST_SPL,
402 BS3CG1DST_BPL,
403 BS3CG1DST_SIL,
404 BS3CG1DST_DIL,
405 BS3CG1DST_R8L,
406 BS3CG1DST_R9L,
407 BS3CG1DST_R10L,
408 BS3CG1DST_R11L,
409 BS3CG1DST_R12L,
410 BS3CG1DST_R13L,
411 BS3CG1DST_R14L,
412 BS3CG1DST_R15L,
413 /* 16-bit GPRs. */
414 BS3CG1DST_AX,
415 BS3CG1DST_CX,
416 BS3CG1DST_DX,
417 BS3CG1DST_BX,
418 BS3CG1DST_SP,
419 BS3CG1DST_BP,
420 BS3CG1DST_SI,
421 BS3CG1DST_DI,
422 BS3CG1DST_R8W,
423 BS3CG1DST_R9W,
424 BS3CG1DST_R10W,
425 BS3CG1DST_R11W,
426 BS3CG1DST_R12W,
427 BS3CG1DST_R13W,
428 BS3CG1DST_R14W,
429 BS3CG1DST_R15W,
430 /* 32-bit GPRs. */
431 BS3CG1DST_EAX,
432 BS3CG1DST_ECX,
433 BS3CG1DST_EDX,
434 BS3CG1DST_EBX,
435 BS3CG1DST_ESP,
436 BS3CG1DST_EBP,
437 BS3CG1DST_ESI,
438 BS3CG1DST_EDI,
439 BS3CG1DST_R8D,
440 BS3CG1DST_R9D,
441 BS3CG1DST_R10D,
442 BS3CG1DST_R11D,
443 BS3CG1DST_R12D,
444 BS3CG1DST_R13D,
445 BS3CG1DST_R14D,
446 BS3CG1DST_R15D,
447 /* 64-bit GPRs. */
448 BS3CG1DST_RAX,
449 BS3CG1DST_RCX,
450 BS3CG1DST_RDX,
451 BS3CG1DST_RBX,
452 BS3CG1DST_RSP,
453 BS3CG1DST_RBP,
454 BS3CG1DST_RSI,
455 BS3CG1DST_RDI,
456 BS3CG1DST_R8,
457 BS3CG1DST_R9,
458 BS3CG1DST_R10,
459 BS3CG1DST_R11,
460 BS3CG1DST_R12,
461 BS3CG1DST_R13,
462 BS3CG1DST_R14,
463 BS3CG1DST_R15,
464 /* 16-bit, 32-bit or 64-bit registers according to operand size. */
465 BS3CG1DST_OZ_RAX,
466 BS3CG1DST_OZ_RCX,
467 BS3CG1DST_OZ_RDX,
468 BS3CG1DST_OZ_RBX,
469 BS3CG1DST_OZ_RSP,
470 BS3CG1DST_OZ_RBP,
471 BS3CG1DST_OZ_RSI,
472 BS3CG1DST_OZ_RDI,
473 BS3CG1DST_OZ_R8,
474 BS3CG1DST_OZ_R9,
475 BS3CG1DST_OZ_R10,
476 BS3CG1DST_OZ_R11,
477 BS3CG1DST_OZ_R12,
478 BS3CG1DST_OZ_R13,
479 BS3CG1DST_OZ_R14,
480 BS3CG1DST_OZ_R15,
481
482 /* Control registers.*/
483 BS3CG1DST_CR0,
484 BS3CG1DST_CR4,
485 BS3CG1DST_XCR0,
486
487 /* FPU registers. */
488 BS3CG1DST_FPU_FIRST,
489 BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
490 BS3CG1DST_FSW,
491 BS3CG1DST_FTW,
492 BS3CG1DST_FOP,
493 BS3CG1DST_FPUIP,
494 BS3CG1DST_FPUCS,
495 BS3CG1DST_FPUDP,
496 BS3CG1DST_FPUDS,
497 BS3CG1DST_MXCSR,
498 BS3CG1DST_ST0,
499 BS3CG1DST_ST1,
500 BS3CG1DST_ST2,
501 BS3CG1DST_ST3,
502 BS3CG1DST_ST4,
503 BS3CG1DST_ST5,
504 BS3CG1DST_ST6,
505 BS3CG1DST_ST7,
506 /* MMX registers. */
507 BS3CG1DST_MM0,
508 BS3CG1DST_MM1,
509 BS3CG1DST_MM2,
510 BS3CG1DST_MM3,
511 BS3CG1DST_MM4,
512 BS3CG1DST_MM5,
513 BS3CG1DST_MM6,
514 BS3CG1DST_MM7,
515 /* SSE registers. */
516 BS3CG1DST_XMM0,
517 BS3CG1DST_XMM1,
518 BS3CG1DST_XMM2,
519 BS3CG1DST_XMM3,
520 BS3CG1DST_XMM4,
521 BS3CG1DST_XMM5,
522 BS3CG1DST_XMM6,
523 BS3CG1DST_XMM7,
524 BS3CG1DST_XMM8,
525 BS3CG1DST_XMM9,
526 BS3CG1DST_XMM10,
527 BS3CG1DST_XMM11,
528 BS3CG1DST_XMM12,
529 BS3CG1DST_XMM13,
530 BS3CG1DST_XMM14,
531 BS3CG1DST_XMM15,
532 BS3CG1DST_XMM0_LO,
533 BS3CG1DST_XMM1_LO,
534 BS3CG1DST_XMM2_LO,
535 BS3CG1DST_XMM3_LO,
536 BS3CG1DST_XMM4_LO,
537 BS3CG1DST_XMM5_LO,
538 BS3CG1DST_XMM6_LO,
539 BS3CG1DST_XMM7_LO,
540 BS3CG1DST_XMM8_LO,
541 BS3CG1DST_XMM9_LO,
542 BS3CG1DST_XMM10_LO,
543 BS3CG1DST_XMM11_LO,
544 BS3CG1DST_XMM12_LO,
545 BS3CG1DST_XMM13_LO,
546 BS3CG1DST_XMM14_LO,
547 BS3CG1DST_XMM15_LO,
548 BS3CG1DST_XMM0_HI,
549 BS3CG1DST_XMM1_HI,
550 BS3CG1DST_XMM2_HI,
551 BS3CG1DST_XMM3_HI,
552 BS3CG1DST_XMM4_HI,
553 BS3CG1DST_XMM5_HI,
554 BS3CG1DST_XMM6_HI,
555 BS3CG1DST_XMM7_HI,
556 BS3CG1DST_XMM8_HI,
557 BS3CG1DST_XMM9_HI,
558 BS3CG1DST_XMM10_HI,
559 BS3CG1DST_XMM11_HI,
560 BS3CG1DST_XMM12_HI,
561 BS3CG1DST_XMM13_HI,
562 BS3CG1DST_XMM14_HI,
563 BS3CG1DST_XMM15_HI,
564 BS3CG1DST_XMM0_LO_ZX,
565 BS3CG1DST_XMM1_LO_ZX,
566 BS3CG1DST_XMM2_LO_ZX,
567 BS3CG1DST_XMM3_LO_ZX,
568 BS3CG1DST_XMM4_LO_ZX,
569 BS3CG1DST_XMM5_LO_ZX,
570 BS3CG1DST_XMM6_LO_ZX,
571 BS3CG1DST_XMM7_LO_ZX,
572 BS3CG1DST_XMM8_LO_ZX,
573 BS3CG1DST_XMM9_LO_ZX,
574 BS3CG1DST_XMM10_LO_ZX,
575 BS3CG1DST_XMM11_LO_ZX,
576 BS3CG1DST_XMM12_LO_ZX,
577 BS3CG1DST_XMM13_LO_ZX,
578 BS3CG1DST_XMM14_LO_ZX,
579 BS3CG1DST_XMM15_LO_ZX,
580 BS3CG1DST_XMM0_DW0,
581 BS3CG1DST_XMM1_DW0,
582 BS3CG1DST_XMM2_DW0,
583 BS3CG1DST_XMM3_DW0,
584 BS3CG1DST_XMM4_DW0,
585 BS3CG1DST_XMM5_DW0,
586 BS3CG1DST_XMM6_DW0,
587 BS3CG1DST_XMM7_DW0,
588 BS3CG1DST_XMM8_DW0,
589 BS3CG1DST_XMM9_DW0,
590 BS3CG1DST_XMM10_DW0,
591 BS3CG1DST_XMM11_DW0,
592 BS3CG1DST_XMM12_DW0,
593 BS3CG1DST_XMM13_DW0,
594 BS3CG1DST_XMM14_DW0,
595 BS3CG1DST_XMM15_DW0,
596 BS3CG1DST_XMM0_DW0_ZX,
597 BS3CG1DST_XMM1_DW0_ZX,
598 BS3CG1DST_XMM2_DW0_ZX,
599 BS3CG1DST_XMM3_DW0_ZX,
600 BS3CG1DST_XMM4_DW0_ZX,
601 BS3CG1DST_XMM5_DW0_ZX,
602 BS3CG1DST_XMM6_DW0_ZX,
603 BS3CG1DST_XMM7_DW0_ZX,
604 BS3CG1DST_XMM8_DW0_ZX,
605 BS3CG1DST_XMM9_DW0_ZX,
606 BS3CG1DST_XMM10_DW0_ZX,
607 BS3CG1DST_XMM11_DW0_ZX,
608 BS3CG1DST_XMM12_DW0_ZX,
609 BS3CG1DST_XMM13_DW0_ZX,
610 BS3CG1DST_XMM14_DW0_ZX,
611 BS3CG1DST_XMM15_DW0_ZX,
612 /* AVX registers. */
613 BS3CG1DST_YMM0,
614 BS3CG1DST_YMM1,
615 BS3CG1DST_YMM2,
616 BS3CG1DST_YMM3,
617 BS3CG1DST_YMM4,
618 BS3CG1DST_YMM5,
619 BS3CG1DST_YMM6,
620 BS3CG1DST_YMM7,
621 BS3CG1DST_YMM8,
622 BS3CG1DST_YMM9,
623 BS3CG1DST_YMM10,
624 BS3CG1DST_YMM11,
625 BS3CG1DST_YMM12,
626 BS3CG1DST_YMM13,
627 BS3CG1DST_YMM14,
628 BS3CG1DST_YMM15,
629
630 /* Special fields: */
631 BS3CG1DST_SPECIAL_START,
632 BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /**< Expected exception based on input or result. */
633
634 BS3CG1DST_END
635} BS3CG1DST;
636AssertCompile(BS3CG1DST_END <= 256);
637
638/** @name Selector opcode definitions.
639 *
640 * Selector programs are very simple, they are zero or more predicate tests
641 * that are ANDed together. If a predicate test fails, the test is skipped.
642 *
643 * One instruction is encoded as byte, where the first bit indicates what kind
644 * of test and the 7 remaining bits indicates which predicate to check.
645 *
646 * @{ */
647#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /**< The operator part (put in lower bit to reduce switch value range). */
648#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /**< Check that the predicate is true. */
649#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /**< Check that the predicate is false. */
650#define BS3CG1SEL_OP_PRED_SHIFT 1 /**< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. */
651/** @} */
652
653/**
654 * Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
655 */
656typedef enum BS3CG1PRED
657{
658 BS3CG1PRED_INVALID = 0,
659
660 /* Operand size. */
661 BS3CG1PRED_SIZE_O16,
662 BS3CG1PRED_SIZE_O32,
663 BS3CG1PRED_SIZE_O64,
664 /* Execution ring. */
665 BS3CG1PRED_RING_0,
666 BS3CG1PRED_RING_1,
667 BS3CG1PRED_RING_2,
668 BS3CG1PRED_RING_3,
669 BS3CG1PRED_RING_0_THRU_2,
670 BS3CG1PRED_RING_1_THRU_3,
671 /* Basic code mode. */
672 BS3CG1PRED_CODE_64BIT,
673 BS3CG1PRED_CODE_32BIT,
674 BS3CG1PRED_CODE_16BIT,
675 /* CPU modes. */
676 BS3CG1PRED_MODE_REAL,
677 BS3CG1PRED_MODE_PROT,
678 BS3CG1PRED_MODE_LONG,
679 BS3CG1PRED_MODE_V86,
680 BS3CG1PRED_MODE_SMM,
681 BS3CG1PRED_MODE_VMX,
682 BS3CG1PRED_MODE_SVM,
683 /* Paging on/off */
684 BS3CG1PRED_PAGING_ON,
685 BS3CG1PRED_PAGING_OFF,
686 /* CPU Vendors. */
687 BS3CG1PRED_VENDOR_AMD,
688 BS3CG1PRED_VENDOR_INTEL,
689 BS3CG1PRED_VENDOR_VIA,
690
691 BS3CG1PRED_END
692} BS3CG1PRED;
693
694
695/** The test instructions (generated). */
696extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
697/** The number of test instructions (generated). */
698extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
699/** The mnemonics (generated).
700 * Variable length sequence of mnemonics that runs in parallel to
701 * g_aBs3Cg1Instructions. */
702extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
703/** The opcodes (generated).
704 * Variable length sequence of opcode bytes that runs in parallel to
705 * g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
706extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
707/** The operands (generated).
708 * Variable length sequence of opcode values (BS3CG1OP) that runs in
709 * parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
710extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
711/** The test data that BS3CG1INSTR.
712 * In order to simplify generating these, we use a byte array. */
713extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
714
715
716#endif
717
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette