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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 67033

Last change on this file since 67033 was 67033, checked in by vboxsync, 8 years ago

IEM: Tests+docs+adjustments for movntq Mq,Pq (0x0f 0xe7).
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1/* $Id: bs3-cpu-generated-1.h 67033 2017-05-23 10:08:01Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, common header file.
4 */
5
6/*
7 * Copyright (C) 2007-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28#ifndef ___bs3_cpu_generated_1_h___
29#define ___bs3_cpu_generated_1_h___
30
31#include <bs3kit.h>
32#include <iprt/assert.h>
33
34
35/**
36 * Operand details.
37 *
38 * Currently simply using the encoding from the reference manuals.
39 */
40typedef enum BS3CG1OP
41{
42 BS3CG1OP_INVALID = 0,
43
44 BS3CG1OP_Eb,
45 BS3CG1OP_Ed,
46 BS3CG1OP_Ed_WO,
47 BS3CG1OP_Eq,
48 BS3CG1OP_Eq_WO,
49 BS3CG1OP_Ev,
50 BS3CG1OP_Qq,
51 BS3CG1OP_Qq_WO,
52 BS3CG1OP_Wss,
53 BS3CG1OP_Wss_WO,
54 BS3CG1OP_Wsd,
55 BS3CG1OP_Wsd_WO,
56 BS3CG1OP_Wps,
57 BS3CG1OP_Wps_WO,
58 BS3CG1OP_Wpd,
59 BS3CG1OP_Wpd_WO,
60 BS3CG1OP_Wdq,
61 BS3CG1OP_Wdq_WO,
62 BS3CG1OP_Wq,
63 BS3CG1OP_Wq_WO,
64 BS3CG1OP_WqZxReg_WO,
65 BS3CG1OP_Wx,
66 BS3CG1OP_Wx_WO,
67
68 BS3CG1OP_Gb,
69 BS3CG1OP_Gv,
70 BS3CG1OP_Gv_RO,
71 BS3CG1OP_HssHi,
72 BS3CG1OP_HsdHi,
73 BS3CG1OP_HqHi,
74 BS3CG1OP_Nq,
75 BS3CG1OP_Pd,
76 BS3CG1OP_PdZx_WO,
77 BS3CG1OP_Pq,
78 BS3CG1OP_Pq_WO,
79 BS3CG1OP_Uq,
80 BS3CG1OP_UqHi,
81 BS3CG1OP_Uss,
82 BS3CG1OP_Uss_WO,
83 BS3CG1OP_Usd,
84 BS3CG1OP_Usd_WO,
85 BS3CG1OP_Vd,
86 BS3CG1OP_Vd_WO,
87 BS3CG1OP_VdZx_WO,
88 BS3CG1OP_Vss,
89 BS3CG1OP_Vss_WO,
90 BS3CG1OP_VssZx_WO,
91 BS3CG1OP_Vsd,
92 BS3CG1OP_Vsd_WO,
93 BS3CG1OP_VsdZx_WO,
94 BS3CG1OP_Vps,
95 BS3CG1OP_Vps_WO,
96 BS3CG1OP_Vpd,
97 BS3CG1OP_Vpd_WO,
98 BS3CG1OP_Vq,
99 BS3CG1OP_Vq_WO,
100 BS3CG1OP_Vdq,
101 BS3CG1OP_Vdq_WO,
102 BS3CG1OP_VqHi,
103 BS3CG1OP_VqHi_WO,
104 BS3CG1OP_VqZx_WO,
105 BS3CG1OP_Vx,
106 BS3CG1OP_Vx_WO,
107
108 BS3CG1OP_Ib,
109 BS3CG1OP_Iz,
110
111 BS3CG1OP_AL,
112 BS3CG1OP_rAX,
113
114 BS3CG1OP_Ma,
115 BS3CG1OP_Mb_RO,
116 BS3CG1OP_Md,
117 BS3CG1OP_Md_RO,
118 BS3CG1OP_Md_WO,
119 BS3CG1OP_Mq,
120 BS3CG1OP_Mq_WO,
121 BS3CG1OP_Mps_WO,
122 BS3CG1OP_Mpd_WO,
123
124 BS3CG1OP_END
125} BS3CG1OP;
126/** Pointer to a const operand enum. */
127typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
128
129
130/**
131 * Instruction encoding format.
132 *
133 * This duplicates some of the info in the operand array, however it makes it
134 * easier to figure out encoding variations.
135 */
136typedef enum BS3CG1ENC
137{
138 BS3CG1ENC_INVALID = 0,
139
140 BS3CG1ENC_MODRM_Eb_Gb,
141 BS3CG1ENC_MODRM_Ev_Gv,
142 BS3CG1ENC_MODRM_Ed_WO_Pd_WZ,
143 BS3CG1ENC_MODRM_Eq_WO_Pq_WNZ,
144 BS3CG1ENC_MODRM_Ed_WO_Vd_WZ,
145 BS3CG1ENC_MODRM_Eq_WO_Vq_WNZ,
146 BS3CG1ENC_MODRM_Pq_WO_Qq,
147 BS3CG1ENC_MODRM_Wss_WO_Vss,
148 BS3CG1ENC_MODRM_Wsd_WO_Vsd,
149 BS3CG1ENC_MODRM_Wps_WO_Vps,
150 BS3CG1ENC_MODRM_Wpd_WO_Vpd,
151 BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
152
153 BS3CG1ENC_MODRM_Gb_Eb,
154 BS3CG1ENC_MODRM_Gv_Ev,
155 BS3CG1ENC_MODRM_Gv_RO_Ma, /**< bound instruction */
156 BS3CG1ENC_MODRM_Pq_WO_Uq,
157 BS3CG1ENC_MODRM_PdZx_WO_Ed_WZ,
158 BS3CG1ENC_MODRM_Pq_WO_Eq_WNZ,
159 BS3CG1ENC_MODRM_VdZx_WO_Ed_WZ,
160 BS3CG1ENC_MODRM_Vq_WO_UqHi,
161 BS3CG1ENC_MODRM_Vq_WO_Mq,
162 BS3CG1ENC_MODRM_VqHi_WO_Uq,
163 BS3CG1ENC_MODRM_VqHi_WO_Mq,
164 BS3CG1ENC_MODRM_VqZx_WO_Eq_WNZ,
165 BS3CG1ENC_MODRM_Vdq_WO_Wdq,
166 BS3CG1ENC_MODRM_Vpd_WO_Wpd,
167 BS3CG1ENC_MODRM_Vps_WO_Wps,
168 BS3CG1ENC_MODRM_VssZx_WO_Wss,
169 BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
170 BS3CG1ENC_MODRM_VqZx_WO_Wq,
171 BS3CG1ENC_MODRM_VqZx_WO_Nq,
172 BS3CG1ENC_MODRM_Mb_RO,
173 BS3CG1ENC_MODRM_Md_RO,
174 BS3CG1ENC_MODRM_Md_WO,
175 BS3CG1ENC_MODRM_Mq_WO_Pq,
176 BS3CG1ENC_MODRM_Mq_WO_Vq,
177 BS3CG1ENC_MODRM_Mq_WO_VqHi,
178 BS3CG1ENC_MODRM_Mps_WO_Vps,
179 BS3CG1ENC_MODRM_Mpd_WO_Vpd,
180
181 BS3CG1ENC_VEX_MODRM_Vd_WO_Ed_WZ,
182 BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
183 BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
184 BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss,
185 BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd,
186 BS3CG1ENC_VEX_MODRM_Vq_WO_Eq_WNZ,
187 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi,
188 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq,
189 BS3CG1ENC_VEX_MODRM_Vq_WO_Wq,
190 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
191 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
192 BS3CG1ENC_VEX_MODRM_Vx_WO_Wx,
193 BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ,
194 BS3CG1ENC_VEX_MODRM_Eq_WO_Vq_WNZ,
195 BS3CG1ENC_VEX_MODRM_Md_WO,
196 BS3CG1ENC_VEX_MODRM_Mq_WO_Vq,
197 BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
198 BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd,
199 BS3CG1ENC_VEX_MODRM_Mps_WO_Vps,
200 BS3CG1ENC_VEX_MODRM_Mpd_WO_Vpd,
201 BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss,
202 BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd,
203 BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
204 BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
205 BS3CG1ENC_VEX_MODRM_Wq_WO_Vq,
206 BS3CG1ENC_VEX_MODRM_Wx_WO_Vx,
207
208 BS3CG1ENC_FIXED,
209 BS3CG1ENC_FIXED_AL_Ib,
210 BS3CG1ENC_FIXED_rAX_Iz,
211
212
213 BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
214 BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
215 //BS3CG1ENC_VEX_FIXED, /**< Unused or invalid instruction. */
216 BS3CG1ENC_VEX_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
217 BS3CG1ENC_VEX_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
218 BS3CG1ENC_VEX_MODRM, /**< Unused or invalid instruction. */
219
220 BS3CG1ENC_END
221} BS3CG1ENC;
222
223
224/**
225 * Prefix sensitivitiy kind.
226 */
227typedef enum BS3CG1PFXKIND
228{
229 BS3CG1PFXKIND_INVALID = 0,
230
231 BS3CG1PFXKIND_NO_F2_F3_66, /**< No 66, F2 or F3 prefixes allowed as that would alter the meaning. */
232 BS3CG1PFXKIND_REQ_F2, /**< Requires F2 (REPNE) prefix as part of the instr encoding. */
233 BS3CG1PFXKIND_REQ_F3, /**< Requires F3 (REPE) prefix as part of the instr encoding. */
234 BS3CG1PFXKIND_REQ_66, /**< Requires 66 (OP SIZE) prefix as part of the instr encoding. */
235
236 /** @todo more work to be done here... */
237 BS3CG1PFXKIND_MODRM,
238 BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
239
240 BS3CG1PFXKIND_END
241} BS3CG1PFXKIND;
242
243/**
244 * CPU selection or CPU ID.
245 */
246typedef enum BS3CG1CPU
247{
248 /** Works with an CPU. */
249 BS3CG1CPU_ANY = 0,
250 BS3CG1CPU_GE_80186,
251 BS3CG1CPU_GE_80286,
252 BS3CG1CPU_GE_80386,
253 BS3CG1CPU_GE_80486,
254 BS3CG1CPU_GE_Pentium,
255
256 BS3CG1CPU_MMX,
257 BS3CG1CPU_SSE,
258 BS3CG1CPU_SSE2,
259 BS3CG1CPU_SSE3,
260 BS3CG1CPU_AVX,
261 BS3CG1CPU_AVX2,
262 BS3CG1CPU_CLFSH,
263 BS3CG1CPU_CLFLUSHOPT,
264
265 BS3CG1CPU_END
266} BS3CG1CPU;
267
268
269/**
270 * SSE & AVX exception types.
271 */
272typedef enum BS3CG1XCPTTYPE
273{
274 BS3CG1XCPTTYPE_NONE = 0,
275 /* SSE: */
276 BS3CG1XCPTTYPE_1,
277 BS3CG1XCPTTYPE_2,
278 BS3CG1XCPTTYPE_3,
279 BS3CG1XCPTTYPE_4,
280 BS3CG1XCPTTYPE_4UA,
281 BS3CG1XCPTTYPE_5,
282 BS3CG1XCPTTYPE_5LZ,
283 BS3CG1XCPTTYPE_6,
284 BS3CG1XCPTTYPE_7,
285 BS3CG1XCPTTYPE_7LZ,
286 BS3CG1XCPTTYPE_8,
287 BS3CG1XCPTTYPE_11,
288 BS3CG1XCPTTYPE_12,
289 /* EVEX: */
290 BS3CG1XCPTTYPE_E1,
291 BS3CG1XCPTTYPE_E1NF,
292 BS3CG1XCPTTYPE_E2,
293 BS3CG1XCPTTYPE_E3,
294 BS3CG1XCPTTYPE_E3NF,
295 BS3CG1XCPTTYPE_E4,
296 BS3CG1XCPTTYPE_E4NF,
297 BS3CG1XCPTTYPE_E5,
298 BS3CG1XCPTTYPE_E5NF,
299 BS3CG1XCPTTYPE_E6,
300 BS3CG1XCPTTYPE_E6NF,
301 BS3CG1XCPTTYPE_E7NF,
302 BS3CG1XCPTTYPE_E9,
303 BS3CG1XCPTTYPE_E9NF,
304 BS3CG1XCPTTYPE_E10,
305 BS3CG1XCPTTYPE_E11,
306 BS3CG1XCPTTYPE_E12,
307 BS3CG1XCPTTYPE_E12NF,
308 BS3CG1XCPTTYPE_END
309} BS3CG1XCPTTYPE;
310AssertCompile(BS3CG1XCPTTYPE_END <= 32);
311
312
313/**
314 * Generated instruction info.
315 */
316typedef struct BS3CG1INSTR
317{
318 /** The opcode size. */
319 uint32_t cbOpcodes : 2;
320 /** The number of operands. */
321 uint32_t cOperands : 2;
322 /** The length of the mnemonic. */
323 uint32_t cchMnemonic : 4;
324 /** Whether to advance the mnemonic array pointer. */
325 uint32_t fAdvanceMnemonic : 1;
326 /** Offset into g_abBs3Cg1Tests of the first test. */
327 uint32_t offTests : 23;
328 /** BS3CG1ENC values. */
329 uint32_t enmEncoding : 10;
330 /** BS3CG1PFXKIND values. */
331 uint32_t enmPrefixKind : 4;
332 /** CPU test / CPU ID bit test (BS3CG1CPU). */
333 uint32_t enmCpuTest : 6;
334 /** Exception type (BS3CG1XCPTTYPE) */
335 uint32_t enmXcptType : 5;
336 /** Currently unused bits. */
337 uint32_t uUnused : 6;
338 /** BS3CG1INSTR_F_XXX. */
339 uint32_t fFlags;
340} BS3CG1INSTR;
341AssertCompileSize(BS3CG1INSTR, 12);
342/** Pointer to a const instruction. */
343typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
344
345
346/** @name BS3CG1INSTR_F_XXX
347 * @{ */
348/** Defaults to SS rather than DS. */
349#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
350/** Invalid instruction in 64-bit mode. */
351#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
352/** Unused instruction. */
353#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
354/** Invalid instruction. */
355#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
356/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
357 * Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
358#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
359/** VEX.L must be zero (IEMOPHINT_VEX_L_ZERO). */
360#define BS3CG1INSTR_F_VEX_L_ZERO UINT32_C(0x00000020)
361/** @} */
362
363
364/**
365 * Test header.
366 */
367typedef struct BS3CG1TESTHDR
368{
369 /** The size of the selector program in bytes.
370 * This is also the offset of the input context modification program. */
371 uint32_t cbSelector : 8;
372 /** The size of the input context modification program in bytes.
373 * This immediately follows the selector program. */
374 uint32_t cbInput : 12;
375 /** The size of the output context modification program in bytes.
376 * This immediately follows the input context modification program. The
377 * program takes the result of the input program as starting point. */
378 uint32_t cbOutput : 11;
379 /** Indicates whether this is the last test or not. */
380 uint32_t fLast : 1;
381} BS3CG1TESTHDR;
382AssertCompileSize(BS3CG1TESTHDR, 4);
383/** Pointer to a const test header. */
384typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
385
386/** @name Opcode format for the BS3CG1 context modifier.
387 *
388 * Used by both the input and output context programs.
389 *
390 * The most common operations are encoded as a single byte opcode followed by
391 * one or more immediate bytes with data.
392 *
393 * @{ */
394#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
395#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
396#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
397#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
398#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
399#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
400#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
401#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
402#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /**< Separate byte encoding the value size following any destination escape byte. */
403
404#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
405#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
406#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
407#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
408#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /**< Separate byte giving the destination follows immediately. */
409
410#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /**< Whether to sign-extend (set) the immediate value. */
411
412#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
413#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /**< Simple assignment operator (=) */
414#define BS3CG1_CTXOP_OR UINT8_C(0x40) /**< OR assignment operator (|=). */
415#define BS3CG1_CTXOP_AND UINT8_C(0x80) /**< AND assignment operator (&=). */
416#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /**< AND assignment operator of the inverted value (&~=). */
417/** @} */
418
419/**
420 * Escaped destination values
421 *
422 * These are just uppercased versions of TestInOut.kdFields, where dots are
423 * replaced by underscores.
424 */
425typedef enum BS3CG1DST
426{
427 BS3CG1DST_INVALID = 0,
428 /* Operands. */
429 BS3CG1DST_OP1,
430 BS3CG1DST_OP2,
431 BS3CG1DST_OP3,
432 BS3CG1DST_OP4,
433 /* Flags. */
434 BS3CG1DST_EFL,
435 BS3CG1DST_EFL_UNDEF, /**< Special field only valid in output context modifiers: EFLAGS |= Value & Ouput.EFLAGS; */
436 /* 8-bit GPRs. */
437 BS3CG1DST_AL,
438 BS3CG1DST_CL,
439 BS3CG1DST_DL,
440 BS3CG1DST_BL,
441 BS3CG1DST_AH,
442 BS3CG1DST_CH,
443 BS3CG1DST_DH,
444 BS3CG1DST_BH,
445 BS3CG1DST_SPL,
446 BS3CG1DST_BPL,
447 BS3CG1DST_SIL,
448 BS3CG1DST_DIL,
449 BS3CG1DST_R8L,
450 BS3CG1DST_R9L,
451 BS3CG1DST_R10L,
452 BS3CG1DST_R11L,
453 BS3CG1DST_R12L,
454 BS3CG1DST_R13L,
455 BS3CG1DST_R14L,
456 BS3CG1DST_R15L,
457 /* 16-bit GPRs. */
458 BS3CG1DST_AX,
459 BS3CG1DST_CX,
460 BS3CG1DST_DX,
461 BS3CG1DST_BX,
462 BS3CG1DST_SP,
463 BS3CG1DST_BP,
464 BS3CG1DST_SI,
465 BS3CG1DST_DI,
466 BS3CG1DST_R8W,
467 BS3CG1DST_R9W,
468 BS3CG1DST_R10W,
469 BS3CG1DST_R11W,
470 BS3CG1DST_R12W,
471 BS3CG1DST_R13W,
472 BS3CG1DST_R14W,
473 BS3CG1DST_R15W,
474 /* 32-bit GPRs. */
475 BS3CG1DST_EAX,
476 BS3CG1DST_ECX,
477 BS3CG1DST_EDX,
478 BS3CG1DST_EBX,
479 BS3CG1DST_ESP,
480 BS3CG1DST_EBP,
481 BS3CG1DST_ESI,
482 BS3CG1DST_EDI,
483 BS3CG1DST_R8D,
484 BS3CG1DST_R9D,
485 BS3CG1DST_R10D,
486 BS3CG1DST_R11D,
487 BS3CG1DST_R12D,
488 BS3CG1DST_R13D,
489 BS3CG1DST_R14D,
490 BS3CG1DST_R15D,
491 /* 64-bit GPRs. */
492 BS3CG1DST_RAX,
493 BS3CG1DST_RCX,
494 BS3CG1DST_RDX,
495 BS3CG1DST_RBX,
496 BS3CG1DST_RSP,
497 BS3CG1DST_RBP,
498 BS3CG1DST_RSI,
499 BS3CG1DST_RDI,
500 BS3CG1DST_R8,
501 BS3CG1DST_R9,
502 BS3CG1DST_R10,
503 BS3CG1DST_R11,
504 BS3CG1DST_R12,
505 BS3CG1DST_R13,
506 BS3CG1DST_R14,
507 BS3CG1DST_R15,
508 /* 16-bit, 32-bit or 64-bit registers according to operand size. */
509 BS3CG1DST_OZ_RAX,
510 BS3CG1DST_OZ_RCX,
511 BS3CG1DST_OZ_RDX,
512 BS3CG1DST_OZ_RBX,
513 BS3CG1DST_OZ_RSP,
514 BS3CG1DST_OZ_RBP,
515 BS3CG1DST_OZ_RSI,
516 BS3CG1DST_OZ_RDI,
517 BS3CG1DST_OZ_R8,
518 BS3CG1DST_OZ_R9,
519 BS3CG1DST_OZ_R10,
520 BS3CG1DST_OZ_R11,
521 BS3CG1DST_OZ_R12,
522 BS3CG1DST_OZ_R13,
523 BS3CG1DST_OZ_R14,
524 BS3CG1DST_OZ_R15,
525
526 /* Control registers.*/
527 BS3CG1DST_CR0,
528 BS3CG1DST_CR4,
529 BS3CG1DST_XCR0,
530
531 /* FPU registers. */
532 BS3CG1DST_FPU_FIRST,
533 BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
534 BS3CG1DST_FSW,
535 BS3CG1DST_FTW,
536 BS3CG1DST_FOP,
537 BS3CG1DST_FPUIP,
538 BS3CG1DST_FPUCS,
539 BS3CG1DST_FPUDP,
540 BS3CG1DST_FPUDS,
541 BS3CG1DST_MXCSR,
542 BS3CG1DST_ST0,
543 BS3CG1DST_ST1,
544 BS3CG1DST_ST2,
545 BS3CG1DST_ST3,
546 BS3CG1DST_ST4,
547 BS3CG1DST_ST5,
548 BS3CG1DST_ST6,
549 BS3CG1DST_ST7,
550 /* MMX registers. */
551 BS3CG1DST_MM0,
552 BS3CG1DST_MM1,
553 BS3CG1DST_MM2,
554 BS3CG1DST_MM3,
555 BS3CG1DST_MM4,
556 BS3CG1DST_MM5,
557 BS3CG1DST_MM6,
558 BS3CG1DST_MM7,
559 BS3CG1DST_MM0_LO_ZX,
560 BS3CG1DST_MM1_LO_ZX,
561 BS3CG1DST_MM2_LO_ZX,
562 BS3CG1DST_MM3_LO_ZX,
563 BS3CG1DST_MM4_LO_ZX,
564 BS3CG1DST_MM5_LO_ZX,
565 BS3CG1DST_MM6_LO_ZX,
566 BS3CG1DST_MM7_LO_ZX,
567 /* SSE registers. */
568 BS3CG1DST_XMM0,
569 BS3CG1DST_XMM1,
570 BS3CG1DST_XMM2,
571 BS3CG1DST_XMM3,
572 BS3CG1DST_XMM4,
573 BS3CG1DST_XMM5,
574 BS3CG1DST_XMM6,
575 BS3CG1DST_XMM7,
576 BS3CG1DST_XMM8,
577 BS3CG1DST_XMM9,
578 BS3CG1DST_XMM10,
579 BS3CG1DST_XMM11,
580 BS3CG1DST_XMM12,
581 BS3CG1DST_XMM13,
582 BS3CG1DST_XMM14,
583 BS3CG1DST_XMM15,
584 BS3CG1DST_XMM0_LO,
585 BS3CG1DST_XMM1_LO,
586 BS3CG1DST_XMM2_LO,
587 BS3CG1DST_XMM3_LO,
588 BS3CG1DST_XMM4_LO,
589 BS3CG1DST_XMM5_LO,
590 BS3CG1DST_XMM6_LO,
591 BS3CG1DST_XMM7_LO,
592 BS3CG1DST_XMM8_LO,
593 BS3CG1DST_XMM9_LO,
594 BS3CG1DST_XMM10_LO,
595 BS3CG1DST_XMM11_LO,
596 BS3CG1DST_XMM12_LO,
597 BS3CG1DST_XMM13_LO,
598 BS3CG1DST_XMM14_LO,
599 BS3CG1DST_XMM15_LO,
600 BS3CG1DST_XMM0_HI,
601 BS3CG1DST_XMM1_HI,
602 BS3CG1DST_XMM2_HI,
603 BS3CG1DST_XMM3_HI,
604 BS3CG1DST_XMM4_HI,
605 BS3CG1DST_XMM5_HI,
606 BS3CG1DST_XMM6_HI,
607 BS3CG1DST_XMM7_HI,
608 BS3CG1DST_XMM8_HI,
609 BS3CG1DST_XMM9_HI,
610 BS3CG1DST_XMM10_HI,
611 BS3CG1DST_XMM11_HI,
612 BS3CG1DST_XMM12_HI,
613 BS3CG1DST_XMM13_HI,
614 BS3CG1DST_XMM14_HI,
615 BS3CG1DST_XMM15_HI,
616 BS3CG1DST_XMM0_LO_ZX,
617 BS3CG1DST_XMM1_LO_ZX,
618 BS3CG1DST_XMM2_LO_ZX,
619 BS3CG1DST_XMM3_LO_ZX,
620 BS3CG1DST_XMM4_LO_ZX,
621 BS3CG1DST_XMM5_LO_ZX,
622 BS3CG1DST_XMM6_LO_ZX,
623 BS3CG1DST_XMM7_LO_ZX,
624 BS3CG1DST_XMM8_LO_ZX,
625 BS3CG1DST_XMM9_LO_ZX,
626 BS3CG1DST_XMM10_LO_ZX,
627 BS3CG1DST_XMM11_LO_ZX,
628 BS3CG1DST_XMM12_LO_ZX,
629 BS3CG1DST_XMM13_LO_ZX,
630 BS3CG1DST_XMM14_LO_ZX,
631 BS3CG1DST_XMM15_LO_ZX,
632 BS3CG1DST_XMM0_DW0,
633 BS3CG1DST_XMM1_DW0,
634 BS3CG1DST_XMM2_DW0,
635 BS3CG1DST_XMM3_DW0,
636 BS3CG1DST_XMM4_DW0,
637 BS3CG1DST_XMM5_DW0,
638 BS3CG1DST_XMM6_DW0,
639 BS3CG1DST_XMM7_DW0,
640 BS3CG1DST_XMM8_DW0,
641 BS3CG1DST_XMM9_DW0,
642 BS3CG1DST_XMM10_DW0,
643 BS3CG1DST_XMM11_DW0,
644 BS3CG1DST_XMM12_DW0,
645 BS3CG1DST_XMM13_DW0,
646 BS3CG1DST_XMM14_DW0,
647 BS3CG1DST_XMM15_DW0,
648 BS3CG1DST_XMM0_DW0_ZX,
649 BS3CG1DST_XMM1_DW0_ZX,
650 BS3CG1DST_XMM2_DW0_ZX,
651 BS3CG1DST_XMM3_DW0_ZX,
652 BS3CG1DST_XMM4_DW0_ZX,
653 BS3CG1DST_XMM5_DW0_ZX,
654 BS3CG1DST_XMM6_DW0_ZX,
655 BS3CG1DST_XMM7_DW0_ZX,
656 BS3CG1DST_XMM8_DW0_ZX,
657 BS3CG1DST_XMM9_DW0_ZX,
658 BS3CG1DST_XMM10_DW0_ZX,
659 BS3CG1DST_XMM11_DW0_ZX,
660 BS3CG1DST_XMM12_DW0_ZX,
661 BS3CG1DST_XMM13_DW0_ZX,
662 BS3CG1DST_XMM14_DW0_ZX,
663 BS3CG1DST_XMM15_DW0_ZX,
664 BS3CG1DST_XMM0_HI96,
665 BS3CG1DST_XMM1_HI96,
666 BS3CG1DST_XMM2_HI96,
667 BS3CG1DST_XMM3_HI96,
668 BS3CG1DST_XMM4_HI96,
669 BS3CG1DST_XMM5_HI96,
670 BS3CG1DST_XMM6_HI96,
671 BS3CG1DST_XMM7_HI96,
672 BS3CG1DST_XMM8_HI96,
673 BS3CG1DST_XMM9_HI96,
674 BS3CG1DST_XMM10_HI96,
675 BS3CG1DST_XMM11_HI96,
676 BS3CG1DST_XMM12_HI96,
677 BS3CG1DST_XMM13_HI96,
678 BS3CG1DST_XMM14_HI96,
679 BS3CG1DST_XMM15_HI96,
680 /* AVX registers. */
681 BS3CG1DST_YMM0,
682 BS3CG1DST_YMM1,
683 BS3CG1DST_YMM2,
684 BS3CG1DST_YMM3,
685 BS3CG1DST_YMM4,
686 BS3CG1DST_YMM5,
687 BS3CG1DST_YMM6,
688 BS3CG1DST_YMM7,
689 BS3CG1DST_YMM8,
690 BS3CG1DST_YMM9,
691 BS3CG1DST_YMM10,
692 BS3CG1DST_YMM11,
693 BS3CG1DST_YMM12,
694 BS3CG1DST_YMM13,
695 BS3CG1DST_YMM14,
696 BS3CG1DST_YMM15,
697
698 /* Special fields: */
699 BS3CG1DST_SPECIAL_START,
700 BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /**< Expected exception based on input or result. */
701
702 BS3CG1DST_END
703} BS3CG1DST;
704AssertCompile(BS3CG1DST_END <= 256);
705
706/** @name Selector opcode definitions.
707 *
708 * Selector programs are very simple, they are zero or more predicate tests
709 * that are ANDed together. If a predicate test fails, the test is skipped.
710 *
711 * One instruction is encoded as byte, where the first bit indicates what kind
712 * of test and the 7 remaining bits indicates which predicate to check.
713 *
714 * @{ */
715#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /**< The operator part (put in lower bit to reduce switch value range). */
716#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /**< Check that the predicate is true. */
717#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /**< Check that the predicate is false. */
718#define BS3CG1SEL_OP_PRED_SHIFT 1 /**< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. */
719/** @} */
720
721/**
722 * Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
723 */
724typedef enum BS3CG1PRED
725{
726 BS3CG1PRED_INVALID = 0,
727
728 /* Operand size. */
729 BS3CG1PRED_SIZE_O16,
730 BS3CG1PRED_SIZE_O32,
731 BS3CG1PRED_SIZE_O64,
732 /* VEX.L values. */
733 BS3CG1PRED_VEXL_0,
734 BS3CG1PRED_VEXL_1,
735 /* Execution ring. */
736 BS3CG1PRED_RING_0,
737 BS3CG1PRED_RING_1,
738 BS3CG1PRED_RING_2,
739 BS3CG1PRED_RING_3,
740 BS3CG1PRED_RING_0_THRU_2,
741 BS3CG1PRED_RING_1_THRU_3,
742 /* Basic code mode. */
743 BS3CG1PRED_CODE_64BIT,
744 BS3CG1PRED_CODE_32BIT,
745 BS3CG1PRED_CODE_16BIT,
746 /* CPU modes. */
747 BS3CG1PRED_MODE_REAL,
748 BS3CG1PRED_MODE_PROT,
749 BS3CG1PRED_MODE_LONG,
750 BS3CG1PRED_MODE_V86,
751 BS3CG1PRED_MODE_SMM,
752 BS3CG1PRED_MODE_VMX,
753 BS3CG1PRED_MODE_SVM,
754 /* Paging on/off */
755 BS3CG1PRED_PAGING_ON,
756 BS3CG1PRED_PAGING_OFF,
757 /* CPU Vendors. */
758 BS3CG1PRED_VENDOR_AMD,
759 BS3CG1PRED_VENDOR_INTEL,
760 BS3CG1PRED_VENDOR_VIA,
761
762 BS3CG1PRED_END
763} BS3CG1PRED;
764
765
766/** The test instructions (generated). */
767extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
768/** The number of test instructions (generated). */
769extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
770/** The mnemonics (generated).
771 * Variable length sequence of mnemonics that runs in parallel to
772 * g_aBs3Cg1Instructions. */
773extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
774/** The opcodes (generated).
775 * Variable length sequence of opcode bytes that runs in parallel to
776 * g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
777extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
778/** The operands (generated).
779 * Variable length sequence of opcode values (BS3CG1OP) that runs in
780 * parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
781extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
782/** The test data that BS3CG1INSTR.
783 * In order to simplify generating these, we use a byte array. */
784extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
785
786
787#endif
788
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