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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 67035

Last change on this file since 67035 was 67034, checked in by vboxsync, 8 years ago

IEM: Tests+docs for movntdq Mdq,Vdq (0x66 0x0f 0xe7).
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1/* $Id: bs3-cpu-generated-1.h 67034 2017-05-23 11:10:57Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, common header file.
4 */
5
6/*
7 * Copyright (C) 2007-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28#ifndef ___bs3_cpu_generated_1_h___
29#define ___bs3_cpu_generated_1_h___
30
31#include <bs3kit.h>
32#include <iprt/assert.h>
33
34
35/**
36 * Operand details.
37 *
38 * Currently simply using the encoding from the reference manuals.
39 */
40typedef enum BS3CG1OP
41{
42 BS3CG1OP_INVALID = 0,
43
44 BS3CG1OP_Eb,
45 BS3CG1OP_Ed,
46 BS3CG1OP_Ed_WO,
47 BS3CG1OP_Eq,
48 BS3CG1OP_Eq_WO,
49 BS3CG1OP_Ev,
50 BS3CG1OP_Qq,
51 BS3CG1OP_Qq_WO,
52 BS3CG1OP_Wss,
53 BS3CG1OP_Wss_WO,
54 BS3CG1OP_Wsd,
55 BS3CG1OP_Wsd_WO,
56 BS3CG1OP_Wps,
57 BS3CG1OP_Wps_WO,
58 BS3CG1OP_Wpd,
59 BS3CG1OP_Wpd_WO,
60 BS3CG1OP_Wdq,
61 BS3CG1OP_Wdq_WO,
62 BS3CG1OP_Wq,
63 BS3CG1OP_Wq_WO,
64 BS3CG1OP_WqZxReg_WO,
65 BS3CG1OP_Wx,
66 BS3CG1OP_Wx_WO,
67
68 BS3CG1OP_Gb,
69 BS3CG1OP_Gv,
70 BS3CG1OP_Gv_RO,
71 BS3CG1OP_HssHi,
72 BS3CG1OP_HsdHi,
73 BS3CG1OP_HqHi,
74 BS3CG1OP_Nq,
75 BS3CG1OP_Pd,
76 BS3CG1OP_PdZx_WO,
77 BS3CG1OP_Pq,
78 BS3CG1OP_Pq_WO,
79 BS3CG1OP_Uq,
80 BS3CG1OP_UqHi,
81 BS3CG1OP_Uss,
82 BS3CG1OP_Uss_WO,
83 BS3CG1OP_Usd,
84 BS3CG1OP_Usd_WO,
85 BS3CG1OP_Vd,
86 BS3CG1OP_Vd_WO,
87 BS3CG1OP_VdZx_WO,
88 BS3CG1OP_Vss,
89 BS3CG1OP_Vss_WO,
90 BS3CG1OP_VssZx_WO,
91 BS3CG1OP_Vsd,
92 BS3CG1OP_Vsd_WO,
93 BS3CG1OP_VsdZx_WO,
94 BS3CG1OP_Vps,
95 BS3CG1OP_Vps_WO,
96 BS3CG1OP_Vpd,
97 BS3CG1OP_Vpd_WO,
98 BS3CG1OP_Vq,
99 BS3CG1OP_Vq_WO,
100 BS3CG1OP_Vdq,
101 BS3CG1OP_Vdq_WO,
102 BS3CG1OP_VqHi,
103 BS3CG1OP_VqHi_WO,
104 BS3CG1OP_VqZx_WO,
105 BS3CG1OP_Vx,
106 BS3CG1OP_Vx_WO,
107
108 BS3CG1OP_Ib,
109 BS3CG1OP_Iz,
110
111 BS3CG1OP_AL,
112 BS3CG1OP_rAX,
113
114 BS3CG1OP_Ma,
115 BS3CG1OP_Mb_RO,
116 BS3CG1OP_Md,
117 BS3CG1OP_Md_RO,
118 BS3CG1OP_Md_WO,
119 BS3CG1OP_Mdq_WO,
120 BS3CG1OP_Mq,
121 BS3CG1OP_Mq_WO,
122 BS3CG1OP_Mps_WO,
123 BS3CG1OP_Mpd_WO,
124
125 BS3CG1OP_END
126} BS3CG1OP;
127/** Pointer to a const operand enum. */
128typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
129
130
131/**
132 * Instruction encoding format.
133 *
134 * This duplicates some of the info in the operand array, however it makes it
135 * easier to figure out encoding variations.
136 */
137typedef enum BS3CG1ENC
138{
139 BS3CG1ENC_INVALID = 0,
140
141 BS3CG1ENC_MODRM_Eb_Gb,
142 BS3CG1ENC_MODRM_Ev_Gv,
143 BS3CG1ENC_MODRM_Ed_WO_Pd_WZ,
144 BS3CG1ENC_MODRM_Eq_WO_Pq_WNZ,
145 BS3CG1ENC_MODRM_Ed_WO_Vd_WZ,
146 BS3CG1ENC_MODRM_Eq_WO_Vq_WNZ,
147 BS3CG1ENC_MODRM_Pq_WO_Qq,
148 BS3CG1ENC_MODRM_Wss_WO_Vss,
149 BS3CG1ENC_MODRM_Wsd_WO_Vsd,
150 BS3CG1ENC_MODRM_Wps_WO_Vps,
151 BS3CG1ENC_MODRM_Wpd_WO_Vpd,
152 BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
153
154 BS3CG1ENC_MODRM_Gb_Eb,
155 BS3CG1ENC_MODRM_Gv_Ev,
156 BS3CG1ENC_MODRM_Gv_RO_Ma, /**< bound instruction */
157 BS3CG1ENC_MODRM_Pq_WO_Uq,
158 BS3CG1ENC_MODRM_PdZx_WO_Ed_WZ,
159 BS3CG1ENC_MODRM_Pq_WO_Eq_WNZ,
160 BS3CG1ENC_MODRM_VdZx_WO_Ed_WZ,
161 BS3CG1ENC_MODRM_Vq_WO_UqHi,
162 BS3CG1ENC_MODRM_Vq_WO_Mq,
163 BS3CG1ENC_MODRM_VqHi_WO_Uq,
164 BS3CG1ENC_MODRM_VqHi_WO_Mq,
165 BS3CG1ENC_MODRM_VqZx_WO_Eq_WNZ,
166 BS3CG1ENC_MODRM_Vdq_WO_Wdq,
167 BS3CG1ENC_MODRM_Vpd_WO_Wpd,
168 BS3CG1ENC_MODRM_Vps_WO_Wps,
169 BS3CG1ENC_MODRM_VssZx_WO_Wss,
170 BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
171 BS3CG1ENC_MODRM_VqZx_WO_Wq,
172 BS3CG1ENC_MODRM_VqZx_WO_Nq,
173 BS3CG1ENC_MODRM_Mb_RO,
174 BS3CG1ENC_MODRM_Md_RO,
175 BS3CG1ENC_MODRM_Md_WO,
176 BS3CG1ENC_MODRM_Mdq_WO_Vdq,
177 BS3CG1ENC_MODRM_Mq_WO_Pq,
178 BS3CG1ENC_MODRM_Mq_WO_Vq,
179 BS3CG1ENC_MODRM_Mq_WO_VqHi,
180 BS3CG1ENC_MODRM_Mps_WO_Vps,
181 BS3CG1ENC_MODRM_Mpd_WO_Vpd,
182
183 BS3CG1ENC_VEX_MODRM_Vd_WO_Ed_WZ,
184 BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
185 BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
186 BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss,
187 BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd,
188 BS3CG1ENC_VEX_MODRM_Vq_WO_Eq_WNZ,
189 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi,
190 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq,
191 BS3CG1ENC_VEX_MODRM_Vq_WO_Wq,
192 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
193 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
194 BS3CG1ENC_VEX_MODRM_Vx_WO_Wx,
195 BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ,
196 BS3CG1ENC_VEX_MODRM_Eq_WO_Vq_WNZ,
197 BS3CG1ENC_VEX_MODRM_Md_WO,
198 BS3CG1ENC_VEX_MODRM_Mq_WO_Vq,
199 BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
200 BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd,
201 BS3CG1ENC_VEX_MODRM_Mps_WO_Vps,
202 BS3CG1ENC_VEX_MODRM_Mpd_WO_Vpd,
203 BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss,
204 BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd,
205 BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
206 BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
207 BS3CG1ENC_VEX_MODRM_Wq_WO_Vq,
208 BS3CG1ENC_VEX_MODRM_Wx_WO_Vx,
209
210 BS3CG1ENC_FIXED,
211 BS3CG1ENC_FIXED_AL_Ib,
212 BS3CG1ENC_FIXED_rAX_Iz,
213
214
215 BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
216 BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
217 //BS3CG1ENC_VEX_FIXED, /**< Unused or invalid instruction. */
218 BS3CG1ENC_VEX_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
219 BS3CG1ENC_VEX_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
220 BS3CG1ENC_VEX_MODRM, /**< Unused or invalid instruction. */
221
222 BS3CG1ENC_END
223} BS3CG1ENC;
224
225
226/**
227 * Prefix sensitivitiy kind.
228 */
229typedef enum BS3CG1PFXKIND
230{
231 BS3CG1PFXKIND_INVALID = 0,
232
233 BS3CG1PFXKIND_NO_F2_F3_66, /**< No 66, F2 or F3 prefixes allowed as that would alter the meaning. */
234 BS3CG1PFXKIND_REQ_F2, /**< Requires F2 (REPNE) prefix as part of the instr encoding. */
235 BS3CG1PFXKIND_REQ_F3, /**< Requires F3 (REPE) prefix as part of the instr encoding. */
236 BS3CG1PFXKIND_REQ_66, /**< Requires 66 (OP SIZE) prefix as part of the instr encoding. */
237
238 /** @todo more work to be done here... */
239 BS3CG1PFXKIND_MODRM,
240 BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
241
242 BS3CG1PFXKIND_END
243} BS3CG1PFXKIND;
244
245/**
246 * CPU selection or CPU ID.
247 */
248typedef enum BS3CG1CPU
249{
250 /** Works with an CPU. */
251 BS3CG1CPU_ANY = 0,
252 BS3CG1CPU_GE_80186,
253 BS3CG1CPU_GE_80286,
254 BS3CG1CPU_GE_80386,
255 BS3CG1CPU_GE_80486,
256 BS3CG1CPU_GE_Pentium,
257
258 BS3CG1CPU_MMX,
259 BS3CG1CPU_SSE,
260 BS3CG1CPU_SSE2,
261 BS3CG1CPU_SSE3,
262 BS3CG1CPU_AVX,
263 BS3CG1CPU_AVX2,
264 BS3CG1CPU_CLFSH,
265 BS3CG1CPU_CLFLUSHOPT,
266
267 BS3CG1CPU_END
268} BS3CG1CPU;
269
270
271/**
272 * SSE & AVX exception types.
273 */
274typedef enum BS3CG1XCPTTYPE
275{
276 BS3CG1XCPTTYPE_NONE = 0,
277 /* SSE: */
278 BS3CG1XCPTTYPE_1,
279 BS3CG1XCPTTYPE_2,
280 BS3CG1XCPTTYPE_3,
281 BS3CG1XCPTTYPE_4,
282 BS3CG1XCPTTYPE_4UA,
283 BS3CG1XCPTTYPE_5,
284 BS3CG1XCPTTYPE_5LZ,
285 BS3CG1XCPTTYPE_6,
286 BS3CG1XCPTTYPE_7,
287 BS3CG1XCPTTYPE_7LZ,
288 BS3CG1XCPTTYPE_8,
289 BS3CG1XCPTTYPE_11,
290 BS3CG1XCPTTYPE_12,
291 /* EVEX: */
292 BS3CG1XCPTTYPE_E1,
293 BS3CG1XCPTTYPE_E1NF,
294 BS3CG1XCPTTYPE_E2,
295 BS3CG1XCPTTYPE_E3,
296 BS3CG1XCPTTYPE_E3NF,
297 BS3CG1XCPTTYPE_E4,
298 BS3CG1XCPTTYPE_E4NF,
299 BS3CG1XCPTTYPE_E5,
300 BS3CG1XCPTTYPE_E5NF,
301 BS3CG1XCPTTYPE_E6,
302 BS3CG1XCPTTYPE_E6NF,
303 BS3CG1XCPTTYPE_E7NF,
304 BS3CG1XCPTTYPE_E9,
305 BS3CG1XCPTTYPE_E9NF,
306 BS3CG1XCPTTYPE_E10,
307 BS3CG1XCPTTYPE_E11,
308 BS3CG1XCPTTYPE_E12,
309 BS3CG1XCPTTYPE_E12NF,
310 BS3CG1XCPTTYPE_END
311} BS3CG1XCPTTYPE;
312AssertCompile(BS3CG1XCPTTYPE_END <= 32);
313
314
315/**
316 * Generated instruction info.
317 */
318typedef struct BS3CG1INSTR
319{
320 /** The opcode size. */
321 uint32_t cbOpcodes : 2;
322 /** The number of operands. */
323 uint32_t cOperands : 2;
324 /** The length of the mnemonic. */
325 uint32_t cchMnemonic : 4;
326 /** Whether to advance the mnemonic array pointer. */
327 uint32_t fAdvanceMnemonic : 1;
328 /** Offset into g_abBs3Cg1Tests of the first test. */
329 uint32_t offTests : 23;
330 /** BS3CG1ENC values. */
331 uint32_t enmEncoding : 10;
332 /** BS3CG1PFXKIND values. */
333 uint32_t enmPrefixKind : 4;
334 /** CPU test / CPU ID bit test (BS3CG1CPU). */
335 uint32_t enmCpuTest : 6;
336 /** Exception type (BS3CG1XCPTTYPE) */
337 uint32_t enmXcptType : 5;
338 /** Currently unused bits. */
339 uint32_t uUnused : 6;
340 /** BS3CG1INSTR_F_XXX. */
341 uint32_t fFlags;
342} BS3CG1INSTR;
343AssertCompileSize(BS3CG1INSTR, 12);
344/** Pointer to a const instruction. */
345typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
346
347
348/** @name BS3CG1INSTR_F_XXX
349 * @{ */
350/** Defaults to SS rather than DS. */
351#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
352/** Invalid instruction in 64-bit mode. */
353#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
354/** Unused instruction. */
355#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
356/** Invalid instruction. */
357#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
358/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
359 * Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
360#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
361/** VEX.L must be zero (IEMOPHINT_VEX_L_ZERO). */
362#define BS3CG1INSTR_F_VEX_L_ZERO UINT32_C(0x00000020)
363/** @} */
364
365
366/**
367 * Test header.
368 */
369typedef struct BS3CG1TESTHDR
370{
371 /** The size of the selector program in bytes.
372 * This is also the offset of the input context modification program. */
373 uint32_t cbSelector : 8;
374 /** The size of the input context modification program in bytes.
375 * This immediately follows the selector program. */
376 uint32_t cbInput : 12;
377 /** The size of the output context modification program in bytes.
378 * This immediately follows the input context modification program. The
379 * program takes the result of the input program as starting point. */
380 uint32_t cbOutput : 11;
381 /** Indicates whether this is the last test or not. */
382 uint32_t fLast : 1;
383} BS3CG1TESTHDR;
384AssertCompileSize(BS3CG1TESTHDR, 4);
385/** Pointer to a const test header. */
386typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
387
388/** @name Opcode format for the BS3CG1 context modifier.
389 *
390 * Used by both the input and output context programs.
391 *
392 * The most common operations are encoded as a single byte opcode followed by
393 * one or more immediate bytes with data.
394 *
395 * @{ */
396#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
397#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
398#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
399#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
400#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
401#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
402#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
403#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
404#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /**< Separate byte encoding the value size following any destination escape byte. */
405
406#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
407#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
408#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
409#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
410#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /**< Separate byte giving the destination follows immediately. */
411
412#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /**< Whether to sign-extend (set) the immediate value. */
413
414#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
415#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /**< Simple assignment operator (=) */
416#define BS3CG1_CTXOP_OR UINT8_C(0x40) /**< OR assignment operator (|=). */
417#define BS3CG1_CTXOP_AND UINT8_C(0x80) /**< AND assignment operator (&=). */
418#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /**< AND assignment operator of the inverted value (&~=). */
419/** @} */
420
421/**
422 * Escaped destination values
423 *
424 * These are just uppercased versions of TestInOut.kdFields, where dots are
425 * replaced by underscores.
426 */
427typedef enum BS3CG1DST
428{
429 BS3CG1DST_INVALID = 0,
430 /* Operands. */
431 BS3CG1DST_OP1,
432 BS3CG1DST_OP2,
433 BS3CG1DST_OP3,
434 BS3CG1DST_OP4,
435 /* Flags. */
436 BS3CG1DST_EFL,
437 BS3CG1DST_EFL_UNDEF, /**< Special field only valid in output context modifiers: EFLAGS |= Value & Ouput.EFLAGS; */
438 /* 8-bit GPRs. */
439 BS3CG1DST_AL,
440 BS3CG1DST_CL,
441 BS3CG1DST_DL,
442 BS3CG1DST_BL,
443 BS3CG1DST_AH,
444 BS3CG1DST_CH,
445 BS3CG1DST_DH,
446 BS3CG1DST_BH,
447 BS3CG1DST_SPL,
448 BS3CG1DST_BPL,
449 BS3CG1DST_SIL,
450 BS3CG1DST_DIL,
451 BS3CG1DST_R8L,
452 BS3CG1DST_R9L,
453 BS3CG1DST_R10L,
454 BS3CG1DST_R11L,
455 BS3CG1DST_R12L,
456 BS3CG1DST_R13L,
457 BS3CG1DST_R14L,
458 BS3CG1DST_R15L,
459 /* 16-bit GPRs. */
460 BS3CG1DST_AX,
461 BS3CG1DST_CX,
462 BS3CG1DST_DX,
463 BS3CG1DST_BX,
464 BS3CG1DST_SP,
465 BS3CG1DST_BP,
466 BS3CG1DST_SI,
467 BS3CG1DST_DI,
468 BS3CG1DST_R8W,
469 BS3CG1DST_R9W,
470 BS3CG1DST_R10W,
471 BS3CG1DST_R11W,
472 BS3CG1DST_R12W,
473 BS3CG1DST_R13W,
474 BS3CG1DST_R14W,
475 BS3CG1DST_R15W,
476 /* 32-bit GPRs. */
477 BS3CG1DST_EAX,
478 BS3CG1DST_ECX,
479 BS3CG1DST_EDX,
480 BS3CG1DST_EBX,
481 BS3CG1DST_ESP,
482 BS3CG1DST_EBP,
483 BS3CG1DST_ESI,
484 BS3CG1DST_EDI,
485 BS3CG1DST_R8D,
486 BS3CG1DST_R9D,
487 BS3CG1DST_R10D,
488 BS3CG1DST_R11D,
489 BS3CG1DST_R12D,
490 BS3CG1DST_R13D,
491 BS3CG1DST_R14D,
492 BS3CG1DST_R15D,
493 /* 64-bit GPRs. */
494 BS3CG1DST_RAX,
495 BS3CG1DST_RCX,
496 BS3CG1DST_RDX,
497 BS3CG1DST_RBX,
498 BS3CG1DST_RSP,
499 BS3CG1DST_RBP,
500 BS3CG1DST_RSI,
501 BS3CG1DST_RDI,
502 BS3CG1DST_R8,
503 BS3CG1DST_R9,
504 BS3CG1DST_R10,
505 BS3CG1DST_R11,
506 BS3CG1DST_R12,
507 BS3CG1DST_R13,
508 BS3CG1DST_R14,
509 BS3CG1DST_R15,
510 /* 16-bit, 32-bit or 64-bit registers according to operand size. */
511 BS3CG1DST_OZ_RAX,
512 BS3CG1DST_OZ_RCX,
513 BS3CG1DST_OZ_RDX,
514 BS3CG1DST_OZ_RBX,
515 BS3CG1DST_OZ_RSP,
516 BS3CG1DST_OZ_RBP,
517 BS3CG1DST_OZ_RSI,
518 BS3CG1DST_OZ_RDI,
519 BS3CG1DST_OZ_R8,
520 BS3CG1DST_OZ_R9,
521 BS3CG1DST_OZ_R10,
522 BS3CG1DST_OZ_R11,
523 BS3CG1DST_OZ_R12,
524 BS3CG1DST_OZ_R13,
525 BS3CG1DST_OZ_R14,
526 BS3CG1DST_OZ_R15,
527
528 /* Control registers.*/
529 BS3CG1DST_CR0,
530 BS3CG1DST_CR4,
531 BS3CG1DST_XCR0,
532
533 /* FPU registers. */
534 BS3CG1DST_FPU_FIRST,
535 BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
536 BS3CG1DST_FSW,
537 BS3CG1DST_FTW,
538 BS3CG1DST_FOP,
539 BS3CG1DST_FPUIP,
540 BS3CG1DST_FPUCS,
541 BS3CG1DST_FPUDP,
542 BS3CG1DST_FPUDS,
543 BS3CG1DST_MXCSR,
544 BS3CG1DST_ST0,
545 BS3CG1DST_ST1,
546 BS3CG1DST_ST2,
547 BS3CG1DST_ST3,
548 BS3CG1DST_ST4,
549 BS3CG1DST_ST5,
550 BS3CG1DST_ST6,
551 BS3CG1DST_ST7,
552 /* MMX registers. */
553 BS3CG1DST_MM0,
554 BS3CG1DST_MM1,
555 BS3CG1DST_MM2,
556 BS3CG1DST_MM3,
557 BS3CG1DST_MM4,
558 BS3CG1DST_MM5,
559 BS3CG1DST_MM6,
560 BS3CG1DST_MM7,
561 BS3CG1DST_MM0_LO_ZX,
562 BS3CG1DST_MM1_LO_ZX,
563 BS3CG1DST_MM2_LO_ZX,
564 BS3CG1DST_MM3_LO_ZX,
565 BS3CG1DST_MM4_LO_ZX,
566 BS3CG1DST_MM5_LO_ZX,
567 BS3CG1DST_MM6_LO_ZX,
568 BS3CG1DST_MM7_LO_ZX,
569 /* SSE registers. */
570 BS3CG1DST_XMM0,
571 BS3CG1DST_XMM1,
572 BS3CG1DST_XMM2,
573 BS3CG1DST_XMM3,
574 BS3CG1DST_XMM4,
575 BS3CG1DST_XMM5,
576 BS3CG1DST_XMM6,
577 BS3CG1DST_XMM7,
578 BS3CG1DST_XMM8,
579 BS3CG1DST_XMM9,
580 BS3CG1DST_XMM10,
581 BS3CG1DST_XMM11,
582 BS3CG1DST_XMM12,
583 BS3CG1DST_XMM13,
584 BS3CG1DST_XMM14,
585 BS3CG1DST_XMM15,
586 BS3CG1DST_XMM0_LO,
587 BS3CG1DST_XMM1_LO,
588 BS3CG1DST_XMM2_LO,
589 BS3CG1DST_XMM3_LO,
590 BS3CG1DST_XMM4_LO,
591 BS3CG1DST_XMM5_LO,
592 BS3CG1DST_XMM6_LO,
593 BS3CG1DST_XMM7_LO,
594 BS3CG1DST_XMM8_LO,
595 BS3CG1DST_XMM9_LO,
596 BS3CG1DST_XMM10_LO,
597 BS3CG1DST_XMM11_LO,
598 BS3CG1DST_XMM12_LO,
599 BS3CG1DST_XMM13_LO,
600 BS3CG1DST_XMM14_LO,
601 BS3CG1DST_XMM15_LO,
602 BS3CG1DST_XMM0_HI,
603 BS3CG1DST_XMM1_HI,
604 BS3CG1DST_XMM2_HI,
605 BS3CG1DST_XMM3_HI,
606 BS3CG1DST_XMM4_HI,
607 BS3CG1DST_XMM5_HI,
608 BS3CG1DST_XMM6_HI,
609 BS3CG1DST_XMM7_HI,
610 BS3CG1DST_XMM8_HI,
611 BS3CG1DST_XMM9_HI,
612 BS3CG1DST_XMM10_HI,
613 BS3CG1DST_XMM11_HI,
614 BS3CG1DST_XMM12_HI,
615 BS3CG1DST_XMM13_HI,
616 BS3CG1DST_XMM14_HI,
617 BS3CG1DST_XMM15_HI,
618 BS3CG1DST_XMM0_LO_ZX,
619 BS3CG1DST_XMM1_LO_ZX,
620 BS3CG1DST_XMM2_LO_ZX,
621 BS3CG1DST_XMM3_LO_ZX,
622 BS3CG1DST_XMM4_LO_ZX,
623 BS3CG1DST_XMM5_LO_ZX,
624 BS3CG1DST_XMM6_LO_ZX,
625 BS3CG1DST_XMM7_LO_ZX,
626 BS3CG1DST_XMM8_LO_ZX,
627 BS3CG1DST_XMM9_LO_ZX,
628 BS3CG1DST_XMM10_LO_ZX,
629 BS3CG1DST_XMM11_LO_ZX,
630 BS3CG1DST_XMM12_LO_ZX,
631 BS3CG1DST_XMM13_LO_ZX,
632 BS3CG1DST_XMM14_LO_ZX,
633 BS3CG1DST_XMM15_LO_ZX,
634 BS3CG1DST_XMM0_DW0,
635 BS3CG1DST_XMM1_DW0,
636 BS3CG1DST_XMM2_DW0,
637 BS3CG1DST_XMM3_DW0,
638 BS3CG1DST_XMM4_DW0,
639 BS3CG1DST_XMM5_DW0,
640 BS3CG1DST_XMM6_DW0,
641 BS3CG1DST_XMM7_DW0,
642 BS3CG1DST_XMM8_DW0,
643 BS3CG1DST_XMM9_DW0,
644 BS3CG1DST_XMM10_DW0,
645 BS3CG1DST_XMM11_DW0,
646 BS3CG1DST_XMM12_DW0,
647 BS3CG1DST_XMM13_DW0,
648 BS3CG1DST_XMM14_DW0,
649 BS3CG1DST_XMM15_DW0,
650 BS3CG1DST_XMM0_DW0_ZX,
651 BS3CG1DST_XMM1_DW0_ZX,
652 BS3CG1DST_XMM2_DW0_ZX,
653 BS3CG1DST_XMM3_DW0_ZX,
654 BS3CG1DST_XMM4_DW0_ZX,
655 BS3CG1DST_XMM5_DW0_ZX,
656 BS3CG1DST_XMM6_DW0_ZX,
657 BS3CG1DST_XMM7_DW0_ZX,
658 BS3CG1DST_XMM8_DW0_ZX,
659 BS3CG1DST_XMM9_DW0_ZX,
660 BS3CG1DST_XMM10_DW0_ZX,
661 BS3CG1DST_XMM11_DW0_ZX,
662 BS3CG1DST_XMM12_DW0_ZX,
663 BS3CG1DST_XMM13_DW0_ZX,
664 BS3CG1DST_XMM14_DW0_ZX,
665 BS3CG1DST_XMM15_DW0_ZX,
666 BS3CG1DST_XMM0_HI96,
667 BS3CG1DST_XMM1_HI96,
668 BS3CG1DST_XMM2_HI96,
669 BS3CG1DST_XMM3_HI96,
670 BS3CG1DST_XMM4_HI96,
671 BS3CG1DST_XMM5_HI96,
672 BS3CG1DST_XMM6_HI96,
673 BS3CG1DST_XMM7_HI96,
674 BS3CG1DST_XMM8_HI96,
675 BS3CG1DST_XMM9_HI96,
676 BS3CG1DST_XMM10_HI96,
677 BS3CG1DST_XMM11_HI96,
678 BS3CG1DST_XMM12_HI96,
679 BS3CG1DST_XMM13_HI96,
680 BS3CG1DST_XMM14_HI96,
681 BS3CG1DST_XMM15_HI96,
682 /* AVX registers. */
683 BS3CG1DST_YMM0,
684 BS3CG1DST_YMM1,
685 BS3CG1DST_YMM2,
686 BS3CG1DST_YMM3,
687 BS3CG1DST_YMM4,
688 BS3CG1DST_YMM5,
689 BS3CG1DST_YMM6,
690 BS3CG1DST_YMM7,
691 BS3CG1DST_YMM8,
692 BS3CG1DST_YMM9,
693 BS3CG1DST_YMM10,
694 BS3CG1DST_YMM11,
695 BS3CG1DST_YMM12,
696 BS3CG1DST_YMM13,
697 BS3CG1DST_YMM14,
698 BS3CG1DST_YMM15,
699
700 /* Special fields: */
701 BS3CG1DST_SPECIAL_START,
702 BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /**< Expected exception based on input or result. */
703
704 BS3CG1DST_END
705} BS3CG1DST;
706AssertCompile(BS3CG1DST_END <= 256);
707
708/** @name Selector opcode definitions.
709 *
710 * Selector programs are very simple, they are zero or more predicate tests
711 * that are ANDed together. If a predicate test fails, the test is skipped.
712 *
713 * One instruction is encoded as byte, where the first bit indicates what kind
714 * of test and the 7 remaining bits indicates which predicate to check.
715 *
716 * @{ */
717#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /**< The operator part (put in lower bit to reduce switch value range). */
718#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /**< Check that the predicate is true. */
719#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /**< Check that the predicate is false. */
720#define BS3CG1SEL_OP_PRED_SHIFT 1 /**< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. */
721/** @} */
722
723/**
724 * Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
725 */
726typedef enum BS3CG1PRED
727{
728 BS3CG1PRED_INVALID = 0,
729
730 /* Operand size. */
731 BS3CG1PRED_SIZE_O16,
732 BS3CG1PRED_SIZE_O32,
733 BS3CG1PRED_SIZE_O64,
734 /* VEX.L values. */
735 BS3CG1PRED_VEXL_0,
736 BS3CG1PRED_VEXL_1,
737 /* Execution ring. */
738 BS3CG1PRED_RING_0,
739 BS3CG1PRED_RING_1,
740 BS3CG1PRED_RING_2,
741 BS3CG1PRED_RING_3,
742 BS3CG1PRED_RING_0_THRU_2,
743 BS3CG1PRED_RING_1_THRU_3,
744 /* Basic code mode. */
745 BS3CG1PRED_CODE_64BIT,
746 BS3CG1PRED_CODE_32BIT,
747 BS3CG1PRED_CODE_16BIT,
748 /* CPU modes. */
749 BS3CG1PRED_MODE_REAL,
750 BS3CG1PRED_MODE_PROT,
751 BS3CG1PRED_MODE_LONG,
752 BS3CG1PRED_MODE_V86,
753 BS3CG1PRED_MODE_SMM,
754 BS3CG1PRED_MODE_VMX,
755 BS3CG1PRED_MODE_SVM,
756 /* Paging on/off */
757 BS3CG1PRED_PAGING_ON,
758 BS3CG1PRED_PAGING_OFF,
759 /* CPU Vendors. */
760 BS3CG1PRED_VENDOR_AMD,
761 BS3CG1PRED_VENDOR_INTEL,
762 BS3CG1PRED_VENDOR_VIA,
763
764 BS3CG1PRED_END
765} BS3CG1PRED;
766
767
768/** The test instructions (generated). */
769extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
770/** The number of test instructions (generated). */
771extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
772/** The mnemonics (generated).
773 * Variable length sequence of mnemonics that runs in parallel to
774 * g_aBs3Cg1Instructions. */
775extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
776/** The opcodes (generated).
777 * Variable length sequence of opcode bytes that runs in parallel to
778 * g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
779extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
780/** The operands (generated).
781 * Variable length sequence of opcode values (BS3CG1OP) that runs in
782 * parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
783extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
784/** The test data that BS3CG1INSTR.
785 * In order to simplify generating these, we use a byte array. */
786extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
787
788
789#endif
790
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