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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 76579

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1/* $Id: bs3-cpu-generated-1.h 76579 2019-01-01 06:14:44Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, common header file.
4 */
5
6/*
7 * Copyright (C) 2007-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27#ifndef VBOX_INCLUDED_SRC_bootsectors_bs3_cpu_generated_1_h
28#define VBOX_INCLUDED_SRC_bootsectors_bs3_cpu_generated_1_h
29#ifndef RT_WITHOUT_PRAGMA_ONCE
30# pragma once
31#endif
32
33#include <bs3kit.h>
34#include <iprt/assert.h>
35
36
37/**
38 * Operand details.
39 *
40 * Currently simply using the encoding from the reference manuals.
41 */
42typedef enum BS3CG1OP
43{
44 BS3CG1OP_INVALID = 0,
45
46 BS3CG1OP_Eb,
47 BS3CG1OP_Ed,
48 BS3CG1OP_Ed_WO,
49 BS3CG1OP_Eq,
50 BS3CG1OP_Eq_WO,
51 BS3CG1OP_Ev,
52 BS3CG1OP_Qq,
53 BS3CG1OP_Qq_WO,
54 BS3CG1OP_Wss,
55 BS3CG1OP_Wss_WO,
56 BS3CG1OP_Wsd,
57 BS3CG1OP_Wsd_WO,
58 BS3CG1OP_Wps,
59 BS3CG1OP_Wps_WO,
60 BS3CG1OP_Wpd,
61 BS3CG1OP_Wpd_WO,
62 BS3CG1OP_Wdq,
63 BS3CG1OP_Wdq_WO,
64 BS3CG1OP_Wq,
65 BS3CG1OP_Wq_WO,
66 BS3CG1OP_WqZxReg_WO,
67 BS3CG1OP_Wx,
68 BS3CG1OP_Wx_WO,
69
70 BS3CG1OP_Gb,
71 BS3CG1OP_Gv,
72 BS3CG1OP_Gv_RO,
73 BS3CG1OP_HssHi,
74 BS3CG1OP_HsdHi,
75 BS3CG1OP_HqHi,
76 BS3CG1OP_Nq,
77 BS3CG1OP_Pd,
78 BS3CG1OP_PdZx_WO,
79 BS3CG1OP_Pq,
80 BS3CG1OP_Pq_WO,
81 BS3CG1OP_Uq,
82 BS3CG1OP_UqHi,
83 BS3CG1OP_Uss,
84 BS3CG1OP_Uss_WO,
85 BS3CG1OP_Usd,
86 BS3CG1OP_Usd_WO,
87 BS3CG1OP_Vd,
88 BS3CG1OP_Vd_WO,
89 BS3CG1OP_VdZx_WO,
90 BS3CG1OP_Vss,
91 BS3CG1OP_Vss_WO,
92 BS3CG1OP_VssZx_WO,
93 BS3CG1OP_Vsd,
94 BS3CG1OP_Vsd_WO,
95 BS3CG1OP_VsdZx_WO,
96 BS3CG1OP_Vps,
97 BS3CG1OP_Vps_WO,
98 BS3CG1OP_Vpd,
99 BS3CG1OP_Vpd_WO,
100 BS3CG1OP_Vq,
101 BS3CG1OP_Vq_WO,
102 BS3CG1OP_Vdq,
103 BS3CG1OP_Vdq_WO,
104 BS3CG1OP_VqHi,
105 BS3CG1OP_VqHi_WO,
106 BS3CG1OP_VqZx_WO,
107 BS3CG1OP_Vx,
108 BS3CG1OP_Vx_WO,
109
110 BS3CG1OP_Ib,
111 BS3CG1OP_Iz,
112
113 BS3CG1OP_AL,
114 BS3CG1OP_rAX,
115
116 BS3CG1OP_Ma,
117 BS3CG1OP_Mb_RO,
118 BS3CG1OP_Md,
119 BS3CG1OP_Md_RO,
120 BS3CG1OP_Md_WO,
121 BS3CG1OP_Mdq,
122 BS3CG1OP_Mdq_WO,
123 BS3CG1OP_Mq,
124 BS3CG1OP_Mq_WO,
125 BS3CG1OP_Mps_WO,
126 BS3CG1OP_Mpd_WO,
127 BS3CG1OP_Mx,
128 BS3CG1OP_Mx_WO,
129
130 BS3CG1OP_END
131} BS3CG1OP;
132/** Pointer to a const operand enum. */
133typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
134
135
136/**
137 * Instruction encoding format.
138 *
139 * This duplicates some of the info in the operand array, however it makes it
140 * easier to figure out encoding variations.
141 */
142typedef enum BS3CG1ENC
143{
144 BS3CG1ENC_INVALID = 0,
145
146 BS3CG1ENC_MODRM_Eb_Gb,
147 BS3CG1ENC_MODRM_Ev_Gv,
148 BS3CG1ENC_MODRM_Ed_WO_Pd_WZ,
149 BS3CG1ENC_MODRM_Eq_WO_Pq_WNZ,
150 BS3CG1ENC_MODRM_Ed_WO_Vd_WZ,
151 BS3CG1ENC_MODRM_Eq_WO_Vq_WNZ,
152 BS3CG1ENC_MODRM_Pq_WO_Qq,
153 BS3CG1ENC_MODRM_Wss_WO_Vss,
154 BS3CG1ENC_MODRM_Wsd_WO_Vsd,
155 BS3CG1ENC_MODRM_Wps_WO_Vps,
156 BS3CG1ENC_MODRM_Wpd_WO_Vpd,
157 BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
158
159 BS3CG1ENC_MODRM_Gb_Eb,
160 BS3CG1ENC_MODRM_Gv_Ev,
161 BS3CG1ENC_MODRM_Gv_RO_Ma, /**< bound instruction */
162 BS3CG1ENC_MODRM_Pq_WO_Uq,
163 BS3CG1ENC_MODRM_PdZx_WO_Ed_WZ,
164 BS3CG1ENC_MODRM_Pq_WO_Eq_WNZ,
165 BS3CG1ENC_MODRM_VdZx_WO_Ed_WZ,
166 BS3CG1ENC_MODRM_Vq_WO_UqHi,
167 BS3CG1ENC_MODRM_Vq_WO_Mq,
168 BS3CG1ENC_MODRM_VqHi_WO_Uq,
169 BS3CG1ENC_MODRM_VqHi_WO_Mq,
170 BS3CG1ENC_MODRM_VqZx_WO_Eq_WNZ,
171 BS3CG1ENC_MODRM_Vdq_WO_Mdq,
172 BS3CG1ENC_MODRM_Vdq_WO_Wdq,
173 BS3CG1ENC_MODRM_Vpd_WO_Wpd,
174 BS3CG1ENC_MODRM_Vps_WO_Wps,
175 BS3CG1ENC_MODRM_VssZx_WO_Wss,
176 BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
177 BS3CG1ENC_MODRM_VqZx_WO_Wq,
178 BS3CG1ENC_MODRM_VqZx_WO_Nq,
179 BS3CG1ENC_MODRM_Mb_RO,
180 BS3CG1ENC_MODRM_Md_RO,
181 BS3CG1ENC_MODRM_Md_WO,
182 BS3CG1ENC_MODRM_Mdq_WO_Vdq,
183 BS3CG1ENC_MODRM_Mq_WO_Pq,
184 BS3CG1ENC_MODRM_Mq_WO_Vq,
185 BS3CG1ENC_MODRM_Mq_WO_VqHi,
186 BS3CG1ENC_MODRM_Mps_WO_Vps,
187 BS3CG1ENC_MODRM_Mpd_WO_Vpd,
188
189 BS3CG1ENC_VEX_MODRM_Vd_WO_Ed_WZ,
190 BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
191 BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
192 BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss,
193 BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd,
194 BS3CG1ENC_VEX_MODRM_Vq_WO_Eq_WNZ,
195 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi,
196 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq,
197 BS3CG1ENC_VEX_MODRM_Vq_WO_Wq,
198 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
199 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
200 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0,
201 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1,
202 BS3CG1ENC_VEX_MODRM_Vx_WO_Wx,
203 BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ,
204 BS3CG1ENC_VEX_MODRM_Eq_WO_Vq_WNZ,
205 BS3CG1ENC_VEX_MODRM_Md_WO,
206 BS3CG1ENC_VEX_MODRM_Mq_WO_Vq,
207 BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
208 BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd,
209 BS3CG1ENC_VEX_MODRM_Mps_WO_Vps,
210 BS3CG1ENC_VEX_MODRM_Mpd_WO_Vpd,
211 BS3CG1ENC_VEX_MODRM_Mx_WO_Vx,
212 BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss,
213 BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd,
214 BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
215 BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
216 BS3CG1ENC_VEX_MODRM_Wq_WO_Vq,
217 BS3CG1ENC_VEX_MODRM_Wx_WO_Vx,
218
219 BS3CG1ENC_FIXED,
220 BS3CG1ENC_FIXED_AL_Ib,
221 BS3CG1ENC_FIXED_rAX_Iz,
222
223
224 BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
225 BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
226 //BS3CG1ENC_VEX_FIXED, /**< Unused or invalid instruction. */
227 BS3CG1ENC_VEX_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
228 BS3CG1ENC_VEX_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
229 BS3CG1ENC_VEX_MODRM, /**< Unused or invalid instruction. */
230
231 BS3CG1ENC_END
232} BS3CG1ENC;
233
234
235/**
236 * Prefix sensitivitiy kind.
237 */
238typedef enum BS3CG1PFXKIND
239{
240 BS3CG1PFXKIND_INVALID = 0,
241
242 BS3CG1PFXKIND_NO_F2_F3_66, /**< No 66, F2 or F3 prefixes allowed as that would alter the meaning. */
243 BS3CG1PFXKIND_REQ_F2, /**< Requires F2 (REPNE) prefix as part of the instr encoding. */
244 BS3CG1PFXKIND_REQ_F3, /**< Requires F3 (REPE) prefix as part of the instr encoding. */
245 BS3CG1PFXKIND_REQ_66, /**< Requires 66 (OP SIZE) prefix as part of the instr encoding. */
246
247 /** @todo more work to be done here... */
248 BS3CG1PFXKIND_MODRM,
249 BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
250
251 BS3CG1PFXKIND_END
252} BS3CG1PFXKIND;
253
254/**
255 * CPU selection or CPU ID.
256 */
257typedef enum BS3CG1CPU
258{
259 /** Works with an CPU. */
260 BS3CG1CPU_ANY = 0,
261 BS3CG1CPU_GE_80186,
262 BS3CG1CPU_GE_80286,
263 BS3CG1CPU_GE_80386,
264 BS3CG1CPU_GE_80486,
265 BS3CG1CPU_GE_Pentium,
266
267 BS3CG1CPU_MMX,
268 BS3CG1CPU_SSE,
269 BS3CG1CPU_SSE2,
270 BS3CG1CPU_SSE3,
271 BS3CG1CPU_SSE4_1,
272 BS3CG1CPU_AVX,
273 BS3CG1CPU_AVX2,
274 BS3CG1CPU_CLFSH,
275 BS3CG1CPU_CLFLUSHOPT,
276
277 BS3CG1CPU_END
278} BS3CG1CPU;
279
280
281/**
282 * SSE & AVX exception types.
283 */
284typedef enum BS3CG1XCPTTYPE
285{
286 BS3CG1XCPTTYPE_NONE = 0,
287 /* SSE: */
288 BS3CG1XCPTTYPE_1,
289 BS3CG1XCPTTYPE_2,
290 BS3CG1XCPTTYPE_3,
291 BS3CG1XCPTTYPE_4,
292 BS3CG1XCPTTYPE_4UA,
293 BS3CG1XCPTTYPE_5,
294 BS3CG1XCPTTYPE_5LZ,
295 BS3CG1XCPTTYPE_6,
296 BS3CG1XCPTTYPE_7,
297 BS3CG1XCPTTYPE_7LZ,
298 BS3CG1XCPTTYPE_8,
299 BS3CG1XCPTTYPE_11,
300 BS3CG1XCPTTYPE_12,
301 /* EVEX: */
302 BS3CG1XCPTTYPE_E1,
303 BS3CG1XCPTTYPE_E1NF,
304 BS3CG1XCPTTYPE_E2,
305 BS3CG1XCPTTYPE_E3,
306 BS3CG1XCPTTYPE_E3NF,
307 BS3CG1XCPTTYPE_E4,
308 BS3CG1XCPTTYPE_E4NF,
309 BS3CG1XCPTTYPE_E5,
310 BS3CG1XCPTTYPE_E5NF,
311 BS3CG1XCPTTYPE_E6,
312 BS3CG1XCPTTYPE_E6NF,
313 BS3CG1XCPTTYPE_E7NF,
314 BS3CG1XCPTTYPE_E9,
315 BS3CG1XCPTTYPE_E9NF,
316 BS3CG1XCPTTYPE_E10,
317 BS3CG1XCPTTYPE_E11,
318 BS3CG1XCPTTYPE_E12,
319 BS3CG1XCPTTYPE_E12NF,
320 BS3CG1XCPTTYPE_END
321} BS3CG1XCPTTYPE;
322AssertCompile(BS3CG1XCPTTYPE_END <= 32);
323
324
325/**
326 * Generated instruction info.
327 */
328typedef struct BS3CG1INSTR
329{
330 /** The opcode size. */
331 uint32_t cbOpcodes : 2;
332 /** The number of operands. */
333 uint32_t cOperands : 2;
334 /** The length of the mnemonic. */
335 uint32_t cchMnemonic : 4;
336 /** Whether to advance the mnemonic array pointer. */
337 uint32_t fAdvanceMnemonic : 1;
338 /** Offset into g_abBs3Cg1Tests of the first test. */
339 uint32_t offTests : 23;
340 /** BS3CG1ENC values. */
341 uint32_t enmEncoding : 10;
342 /** The VEX, EVEX or XOP opcode map number (VEX.mmmm). */
343 uint32_t uOpcodeMap : 4;
344 /** BS3CG1PFXKIND values. */
345 uint32_t enmPrefixKind : 4;
346 /** CPU test / CPU ID bit test (BS3CG1CPU). */
347 uint32_t enmCpuTest : 6;
348 /** Exception type (BS3CG1XCPTTYPE) */
349 uint32_t enmXcptType : 5;
350 /** Currently unused bits. */
351 uint32_t uUnused : 3;
352 /** BS3CG1INSTR_F_XXX. */
353 uint32_t fFlags;
354} BS3CG1INSTR;
355AssertCompileSize(BS3CG1INSTR, 12);
356/** Pointer to a const instruction. */
357typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
358
359
360/** @name BS3CG1INSTR_F_XXX
361 * @{ */
362/** Defaults to SS rather than DS. */
363#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
364/** Invalid instruction in 64-bit mode. */
365#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
366/** Unused instruction. */
367#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
368/** Invalid instruction. */
369#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
370/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
371 * Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
372#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
373/** VEX.L must be zero (IEMOPHINT_VEX_L_ZERO). */
374#define BS3CG1INSTR_F_VEX_L_ZERO UINT32_C(0x00000020)
375/** VEX.L is ignored (IEMOPHINT_VEX_L_IGNORED). */
376#define BS3CG1INSTR_F_VEX_L_IGNORED UINT32_C(0x00000040)
377/** @} */
378
379
380/**
381 * Test header.
382 */
383typedef struct BS3CG1TESTHDR
384{
385 /** The size of the selector program in bytes.
386 * This is also the offset of the input context modification program. */
387 uint32_t cbSelector : 8;
388 /** The size of the input context modification program in bytes.
389 * This immediately follows the selector program. */
390 uint32_t cbInput : 12;
391 /** The size of the output context modification program in bytes.
392 * This immediately follows the input context modification program. The
393 * program takes the result of the input program as starting point. */
394 uint32_t cbOutput : 11;
395 /** Indicates whether this is the last test or not. */
396 uint32_t fLast : 1;
397} BS3CG1TESTHDR;
398AssertCompileSize(BS3CG1TESTHDR, 4);
399/** Pointer to a const test header. */
400typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
401
402/** @name Opcode format for the BS3CG1 context modifier.
403 *
404 * Used by both the input and output context programs.
405 *
406 * The most common operations are encoded as a single byte opcode followed by
407 * one or more immediate bytes with data.
408 *
409 * @{ */
410#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
411#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
412#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
413#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
414#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
415#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
416#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
417#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
418#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /**< Separate byte encoding the value size following any destination escape byte. */
419
420#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
421#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
422#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
423#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
424#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /**< Separate byte giving the destination follows immediately. */
425
426#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /**< Whether to sign-extend (set) the immediate value. */
427
428#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
429#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /**< Simple assignment operator (=) */
430#define BS3CG1_CTXOP_OR UINT8_C(0x40) /**< OR assignment operator (|=). */
431#define BS3CG1_CTXOP_AND UINT8_C(0x80) /**< AND assignment operator (&=). */
432#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /**< AND assignment operator of the inverted value (&~=). */
433/** @} */
434
435/**
436 * Escaped destination values
437 *
438 * These are just uppercased versions of TestInOut.kdFields, where dots are
439 * replaced by underscores.
440 */
441typedef enum BS3CG1DST
442{
443 BS3CG1DST_INVALID = 0,
444 /* Operands. */
445 BS3CG1DST_OP1,
446 BS3CG1DST_OP2,
447 BS3CG1DST_OP3,
448 BS3CG1DST_OP4,
449 /* Flags. */
450 BS3CG1DST_EFL,
451 BS3CG1DST_EFL_UNDEF, /**< Special field only valid in output context modifiers: EFLAGS |= Value & Ouput.EFLAGS; */
452 /* 8-bit GPRs. */
453 BS3CG1DST_AL,
454 BS3CG1DST_CL,
455 BS3CG1DST_DL,
456 BS3CG1DST_BL,
457 BS3CG1DST_AH,
458 BS3CG1DST_CH,
459 BS3CG1DST_DH,
460 BS3CG1DST_BH,
461 BS3CG1DST_SPL,
462 BS3CG1DST_BPL,
463 BS3CG1DST_SIL,
464 BS3CG1DST_DIL,
465 BS3CG1DST_R8L,
466 BS3CG1DST_R9L,
467 BS3CG1DST_R10L,
468 BS3CG1DST_R11L,
469 BS3CG1DST_R12L,
470 BS3CG1DST_R13L,
471 BS3CG1DST_R14L,
472 BS3CG1DST_R15L,
473 /* 16-bit GPRs. */
474 BS3CG1DST_AX,
475 BS3CG1DST_CX,
476 BS3CG1DST_DX,
477 BS3CG1DST_BX,
478 BS3CG1DST_SP,
479 BS3CG1DST_BP,
480 BS3CG1DST_SI,
481 BS3CG1DST_DI,
482 BS3CG1DST_R8W,
483 BS3CG1DST_R9W,
484 BS3CG1DST_R10W,
485 BS3CG1DST_R11W,
486 BS3CG1DST_R12W,
487 BS3CG1DST_R13W,
488 BS3CG1DST_R14W,
489 BS3CG1DST_R15W,
490 /* 32-bit GPRs. */
491 BS3CG1DST_EAX,
492 BS3CG1DST_ECX,
493 BS3CG1DST_EDX,
494 BS3CG1DST_EBX,
495 BS3CG1DST_ESP,
496 BS3CG1DST_EBP,
497 BS3CG1DST_ESI,
498 BS3CG1DST_EDI,
499 BS3CG1DST_R8D,
500 BS3CG1DST_R9D,
501 BS3CG1DST_R10D,
502 BS3CG1DST_R11D,
503 BS3CG1DST_R12D,
504 BS3CG1DST_R13D,
505 BS3CG1DST_R14D,
506 BS3CG1DST_R15D,
507 /* 64-bit GPRs. */
508 BS3CG1DST_RAX,
509 BS3CG1DST_RCX,
510 BS3CG1DST_RDX,
511 BS3CG1DST_RBX,
512 BS3CG1DST_RSP,
513 BS3CG1DST_RBP,
514 BS3CG1DST_RSI,
515 BS3CG1DST_RDI,
516 BS3CG1DST_R8,
517 BS3CG1DST_R9,
518 BS3CG1DST_R10,
519 BS3CG1DST_R11,
520 BS3CG1DST_R12,
521 BS3CG1DST_R13,
522 BS3CG1DST_R14,
523 BS3CG1DST_R15,
524 /* 16-bit, 32-bit or 64-bit registers according to operand size. */
525 BS3CG1DST_OZ_RAX,
526 BS3CG1DST_OZ_RCX,
527 BS3CG1DST_OZ_RDX,
528 BS3CG1DST_OZ_RBX,
529 BS3CG1DST_OZ_RSP,
530 BS3CG1DST_OZ_RBP,
531 BS3CG1DST_OZ_RSI,
532 BS3CG1DST_OZ_RDI,
533 BS3CG1DST_OZ_R8,
534 BS3CG1DST_OZ_R9,
535 BS3CG1DST_OZ_R10,
536 BS3CG1DST_OZ_R11,
537 BS3CG1DST_OZ_R12,
538 BS3CG1DST_OZ_R13,
539 BS3CG1DST_OZ_R14,
540 BS3CG1DST_OZ_R15,
541
542 /* Control registers.*/
543 BS3CG1DST_CR0,
544 BS3CG1DST_CR4,
545 BS3CG1DST_XCR0,
546
547 /* FPU registers. */
548 BS3CG1DST_FPU_FIRST,
549 BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
550 BS3CG1DST_FSW,
551 BS3CG1DST_FTW,
552 BS3CG1DST_FOP,
553 BS3CG1DST_FPUIP,
554 BS3CG1DST_FPUCS,
555 BS3CG1DST_FPUDP,
556 BS3CG1DST_FPUDS,
557 BS3CG1DST_MXCSR,
558 BS3CG1DST_ST0,
559 BS3CG1DST_ST1,
560 BS3CG1DST_ST2,
561 BS3CG1DST_ST3,
562 BS3CG1DST_ST4,
563 BS3CG1DST_ST5,
564 BS3CG1DST_ST6,
565 BS3CG1DST_ST7,
566 /* MMX registers. */
567 BS3CG1DST_MM0,
568 BS3CG1DST_MM1,
569 BS3CG1DST_MM2,
570 BS3CG1DST_MM3,
571 BS3CG1DST_MM4,
572 BS3CG1DST_MM5,
573 BS3CG1DST_MM6,
574 BS3CG1DST_MM7,
575 BS3CG1DST_MM0_LO_ZX,
576 BS3CG1DST_MM1_LO_ZX,
577 BS3CG1DST_MM2_LO_ZX,
578 BS3CG1DST_MM3_LO_ZX,
579 BS3CG1DST_MM4_LO_ZX,
580 BS3CG1DST_MM5_LO_ZX,
581 BS3CG1DST_MM6_LO_ZX,
582 BS3CG1DST_MM7_LO_ZX,
583 /* SSE registers. */
584 BS3CG1DST_XMM0,
585 BS3CG1DST_XMM1,
586 BS3CG1DST_XMM2,
587 BS3CG1DST_XMM3,
588 BS3CG1DST_XMM4,
589 BS3CG1DST_XMM5,
590 BS3CG1DST_XMM6,
591 BS3CG1DST_XMM7,
592 BS3CG1DST_XMM8,
593 BS3CG1DST_XMM9,
594 BS3CG1DST_XMM10,
595 BS3CG1DST_XMM11,
596 BS3CG1DST_XMM12,
597 BS3CG1DST_XMM13,
598 BS3CG1DST_XMM14,
599 BS3CG1DST_XMM15,
600 BS3CG1DST_XMM0_LO,
601 BS3CG1DST_XMM1_LO,
602 BS3CG1DST_XMM2_LO,
603 BS3CG1DST_XMM3_LO,
604 BS3CG1DST_XMM4_LO,
605 BS3CG1DST_XMM5_LO,
606 BS3CG1DST_XMM6_LO,
607 BS3CG1DST_XMM7_LO,
608 BS3CG1DST_XMM8_LO,
609 BS3CG1DST_XMM9_LO,
610 BS3CG1DST_XMM10_LO,
611 BS3CG1DST_XMM11_LO,
612 BS3CG1DST_XMM12_LO,
613 BS3CG1DST_XMM13_LO,
614 BS3CG1DST_XMM14_LO,
615 BS3CG1DST_XMM15_LO,
616 BS3CG1DST_XMM0_HI,
617 BS3CG1DST_XMM1_HI,
618 BS3CG1DST_XMM2_HI,
619 BS3CG1DST_XMM3_HI,
620 BS3CG1DST_XMM4_HI,
621 BS3CG1DST_XMM5_HI,
622 BS3CG1DST_XMM6_HI,
623 BS3CG1DST_XMM7_HI,
624 BS3CG1DST_XMM8_HI,
625 BS3CG1DST_XMM9_HI,
626 BS3CG1DST_XMM10_HI,
627 BS3CG1DST_XMM11_HI,
628 BS3CG1DST_XMM12_HI,
629 BS3CG1DST_XMM13_HI,
630 BS3CG1DST_XMM14_HI,
631 BS3CG1DST_XMM15_HI,
632 BS3CG1DST_XMM0_LO_ZX,
633 BS3CG1DST_XMM1_LO_ZX,
634 BS3CG1DST_XMM2_LO_ZX,
635 BS3CG1DST_XMM3_LO_ZX,
636 BS3CG1DST_XMM4_LO_ZX,
637 BS3CG1DST_XMM5_LO_ZX,
638 BS3CG1DST_XMM6_LO_ZX,
639 BS3CG1DST_XMM7_LO_ZX,
640 BS3CG1DST_XMM8_LO_ZX,
641 BS3CG1DST_XMM9_LO_ZX,
642 BS3CG1DST_XMM10_LO_ZX,
643 BS3CG1DST_XMM11_LO_ZX,
644 BS3CG1DST_XMM12_LO_ZX,
645 BS3CG1DST_XMM13_LO_ZX,
646 BS3CG1DST_XMM14_LO_ZX,
647 BS3CG1DST_XMM15_LO_ZX,
648 BS3CG1DST_XMM0_DW0,
649 BS3CG1DST_XMM1_DW0,
650 BS3CG1DST_XMM2_DW0,
651 BS3CG1DST_XMM3_DW0,
652 BS3CG1DST_XMM4_DW0,
653 BS3CG1DST_XMM5_DW0,
654 BS3CG1DST_XMM6_DW0,
655 BS3CG1DST_XMM7_DW0,
656 BS3CG1DST_XMM8_DW0,
657 BS3CG1DST_XMM9_DW0,
658 BS3CG1DST_XMM10_DW0,
659 BS3CG1DST_XMM11_DW0,
660 BS3CG1DST_XMM12_DW0,
661 BS3CG1DST_XMM13_DW0,
662 BS3CG1DST_XMM14_DW0,
663 BS3CG1DST_XMM15_DW0,
664 BS3CG1DST_XMM0_DW0_ZX,
665 BS3CG1DST_XMM1_DW0_ZX,
666 BS3CG1DST_XMM2_DW0_ZX,
667 BS3CG1DST_XMM3_DW0_ZX,
668 BS3CG1DST_XMM4_DW0_ZX,
669 BS3CG1DST_XMM5_DW0_ZX,
670 BS3CG1DST_XMM6_DW0_ZX,
671 BS3CG1DST_XMM7_DW0_ZX,
672 BS3CG1DST_XMM8_DW0_ZX,
673 BS3CG1DST_XMM9_DW0_ZX,
674 BS3CG1DST_XMM10_DW0_ZX,
675 BS3CG1DST_XMM11_DW0_ZX,
676 BS3CG1DST_XMM12_DW0_ZX,
677 BS3CG1DST_XMM13_DW0_ZX,
678 BS3CG1DST_XMM14_DW0_ZX,
679 BS3CG1DST_XMM15_DW0_ZX,
680 BS3CG1DST_XMM0_HI96,
681 BS3CG1DST_XMM1_HI96,
682 BS3CG1DST_XMM2_HI96,
683 BS3CG1DST_XMM3_HI96,
684 BS3CG1DST_XMM4_HI96,
685 BS3CG1DST_XMM5_HI96,
686 BS3CG1DST_XMM6_HI96,
687 BS3CG1DST_XMM7_HI96,
688 BS3CG1DST_XMM8_HI96,
689 BS3CG1DST_XMM9_HI96,
690 BS3CG1DST_XMM10_HI96,
691 BS3CG1DST_XMM11_HI96,
692 BS3CG1DST_XMM12_HI96,
693 BS3CG1DST_XMM13_HI96,
694 BS3CG1DST_XMM14_HI96,
695 BS3CG1DST_XMM15_HI96,
696 /* AVX registers. */
697 BS3CG1DST_YMM0,
698 BS3CG1DST_YMM1,
699 BS3CG1DST_YMM2,
700 BS3CG1DST_YMM3,
701 BS3CG1DST_YMM4,
702 BS3CG1DST_YMM5,
703 BS3CG1DST_YMM6,
704 BS3CG1DST_YMM7,
705 BS3CG1DST_YMM8,
706 BS3CG1DST_YMM9,
707 BS3CG1DST_YMM10,
708 BS3CG1DST_YMM11,
709 BS3CG1DST_YMM12,
710 BS3CG1DST_YMM13,
711 BS3CG1DST_YMM14,
712 BS3CG1DST_YMM15,
713
714 /* Special fields: */
715 BS3CG1DST_SPECIAL_START,
716 BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /**< Expected exception based on input or result. */
717
718 BS3CG1DST_END
719} BS3CG1DST;
720AssertCompile(BS3CG1DST_END <= 256);
721
722/** @name Selector opcode definitions.
723 *
724 * Selector programs are very simple, they are zero or more predicate tests
725 * that are ANDed together. If a predicate test fails, the test is skipped.
726 *
727 * One instruction is encoded as byte, where the first bit indicates what kind
728 * of test and the 7 remaining bits indicates which predicate to check.
729 *
730 * @{ */
731#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /**< The operator part (put in lower bit to reduce switch value range). */
732#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /**< Check that the predicate is true. */
733#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /**< Check that the predicate is false. */
734#define BS3CG1SEL_OP_PRED_SHIFT 1 /**< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. */
735/** @} */
736
737/**
738 * Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
739 */
740typedef enum BS3CG1PRED
741{
742 BS3CG1PRED_INVALID = 0,
743
744 /* Operand size. */
745 BS3CG1PRED_SIZE_O16,
746 BS3CG1PRED_SIZE_O32,
747 BS3CG1PRED_SIZE_O64,
748 /* VEX.L values. */
749 BS3CG1PRED_VEXL_0,
750 BS3CG1PRED_VEXL_1,
751 /* Execution ring. */
752 BS3CG1PRED_RING_0,
753 BS3CG1PRED_RING_1,
754 BS3CG1PRED_RING_2,
755 BS3CG1PRED_RING_3,
756 BS3CG1PRED_RING_0_THRU_2,
757 BS3CG1PRED_RING_1_THRU_3,
758 /* Basic code mode. */
759 BS3CG1PRED_CODE_64BIT,
760 BS3CG1PRED_CODE_32BIT,
761 BS3CG1PRED_CODE_16BIT,
762 /* CPU modes. */
763 BS3CG1PRED_MODE_REAL,
764 BS3CG1PRED_MODE_PROT,
765 BS3CG1PRED_MODE_LONG,
766 BS3CG1PRED_MODE_V86,
767 BS3CG1PRED_MODE_SMM,
768 BS3CG1PRED_MODE_VMX,
769 BS3CG1PRED_MODE_SVM,
770 /* Paging on/off */
771 BS3CG1PRED_PAGING_ON,
772 BS3CG1PRED_PAGING_OFF,
773 /* CPU Vendors. */
774 BS3CG1PRED_VENDOR_AMD,
775 BS3CG1PRED_VENDOR_INTEL,
776 BS3CG1PRED_VENDOR_VIA,
777
778 BS3CG1PRED_END
779} BS3CG1PRED;
780
781
782/** The test instructions (generated). */
783extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
784/** The number of test instructions (generated). */
785extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
786/** The mnemonics (generated).
787 * Variable length sequence of mnemonics that runs in parallel to
788 * g_aBs3Cg1Instructions. */
789extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
790/** The opcodes (generated).
791 * Variable length sequence of opcode bytes that runs in parallel to
792 * g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
793extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
794/** The operands (generated).
795 * Variable length sequence of opcode values (BS3CG1OP) that runs in
796 * parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
797extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
798/** The test data that BS3CG1INSTR.
799 * In order to simplify generating these, we use a byte array. */
800extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
801
802
803#endif /* !VBOX_INCLUDED_SRC_bootsectors_bs3_cpu_generated_1_h */
804
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