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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 97576

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1/* $Id: bs3-cpu-generated-1.h 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, common header file.
4 */
5
6/*
7 * Copyright (C) 2007-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37#ifndef VBOX_INCLUDED_SRC_bootsectors_bs3_cpu_generated_1_h
38#define VBOX_INCLUDED_SRC_bootsectors_bs3_cpu_generated_1_h
39#ifndef RT_WITHOUT_PRAGMA_ONCE
40# pragma once
41#endif
42
43#include <bs3kit.h>
44#include <iprt/assert.h>
45
46
47/**
48 * Operand details.
49 *
50 * Currently simply using the encoding from the reference manuals.
51 */
52typedef enum BS3CG1OP
53{
54 BS3CG1OP_INVALID = 0,
55
56 BS3CG1OP_Eb,
57 BS3CG1OP_Ed,
58 BS3CG1OP_Ed_WO,
59 BS3CG1OP_Eq,
60 BS3CG1OP_Eq_WO,
61 BS3CG1OP_Ev,
62 BS3CG1OP_Qq,
63 BS3CG1OP_Qq_WO,
64 BS3CG1OP_Wss,
65 BS3CG1OP_Wss_WO,
66 BS3CG1OP_Wsd,
67 BS3CG1OP_Wsd_WO,
68 BS3CG1OP_Wps,
69 BS3CG1OP_Wps_WO,
70 BS3CG1OP_Wpd,
71 BS3CG1OP_Wpd_WO,
72 BS3CG1OP_Wdq,
73 BS3CG1OP_Wdq_WO,
74 BS3CG1OP_Wq,
75 BS3CG1OP_Wq_WO,
76 BS3CG1OP_WqZxReg_WO,
77 BS3CG1OP_Wx,
78 BS3CG1OP_Wx_WO,
79
80 BS3CG1OP_Gb,
81 BS3CG1OP_Gv,
82 BS3CG1OP_Gv_RO,
83 BS3CG1OP_HssHi,
84 BS3CG1OP_HsdHi,
85 BS3CG1OP_HqHi,
86 BS3CG1OP_Nq,
87 BS3CG1OP_Pd,
88 BS3CG1OP_PdZx_WO,
89 BS3CG1OP_Pq,
90 BS3CG1OP_Pq_WO,
91 BS3CG1OP_Uq,
92 BS3CG1OP_UqHi,
93 BS3CG1OP_Uss,
94 BS3CG1OP_Uss_WO,
95 BS3CG1OP_Usd,
96 BS3CG1OP_Usd_WO,
97 BS3CG1OP_Vd,
98 BS3CG1OP_Vd_WO,
99 BS3CG1OP_VdZx_WO,
100 BS3CG1OP_Vss,
101 BS3CG1OP_Vss_WO,
102 BS3CG1OP_VssZx_WO,
103 BS3CG1OP_Vsd,
104 BS3CG1OP_Vsd_WO,
105 BS3CG1OP_VsdZx_WO,
106 BS3CG1OP_Vps,
107 BS3CG1OP_Vps_WO,
108 BS3CG1OP_Vpd,
109 BS3CG1OP_Vpd_WO,
110 BS3CG1OP_Vq,
111 BS3CG1OP_Vq_WO,
112 BS3CG1OP_Vdq,
113 BS3CG1OP_Vdq_WO,
114 BS3CG1OP_VqHi,
115 BS3CG1OP_VqHi_WO,
116 BS3CG1OP_VqZx_WO,
117 BS3CG1OP_Vx,
118 BS3CG1OP_Vx_WO,
119
120 BS3CG1OP_Ib,
121 BS3CG1OP_Iz,
122
123 BS3CG1OP_AL,
124 BS3CG1OP_rAX,
125
126 BS3CG1OP_Ma,
127 BS3CG1OP_Mb_RO,
128 BS3CG1OP_Md,
129 BS3CG1OP_Md_RO,
130 BS3CG1OP_Md_WO,
131 BS3CG1OP_Mdq,
132 BS3CG1OP_Mdq_WO,
133 BS3CG1OP_Mq,
134 BS3CG1OP_Mq_WO,
135 BS3CG1OP_Mps_WO,
136 BS3CG1OP_Mpd_WO,
137 BS3CG1OP_Mx,
138 BS3CG1OP_Mx_WO,
139
140 BS3CG1OP_END
141} BS3CG1OP;
142/** Pointer to a const operand enum. */
143typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
144
145
146/**
147 * Instruction encoding format.
148 *
149 * This duplicates some of the info in the operand array, however it makes it
150 * easier to figure out encoding variations.
151 */
152typedef enum BS3CG1ENC
153{
154 BS3CG1ENC_INVALID = 0,
155
156 BS3CG1ENC_MODRM_Eb_Gb,
157 BS3CG1ENC_MODRM_Ev_Gv,
158 BS3CG1ENC_MODRM_Ed_WO_Pd_WZ,
159 BS3CG1ENC_MODRM_Eq_WO_Pq_WNZ,
160 BS3CG1ENC_MODRM_Ed_WO_Vd_WZ,
161 BS3CG1ENC_MODRM_Eq_WO_Vq_WNZ,
162 BS3CG1ENC_MODRM_Pq_WO_Qq,
163 BS3CG1ENC_MODRM_Wss_WO_Vss,
164 BS3CG1ENC_MODRM_Wsd_WO_Vsd,
165 BS3CG1ENC_MODRM_Wps_WO_Vps,
166 BS3CG1ENC_MODRM_Wpd_WO_Vpd,
167 BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
168
169 BS3CG1ENC_MODRM_Gb_Eb,
170 BS3CG1ENC_MODRM_Gv_Ev,
171 BS3CG1ENC_MODRM_Gv_RO_Ma, /**< bound instruction */
172 BS3CG1ENC_MODRM_Pq_WO_Uq,
173 BS3CG1ENC_MODRM_PdZx_WO_Ed_WZ,
174 BS3CG1ENC_MODRM_Pq_WO_Eq_WNZ,
175 BS3CG1ENC_MODRM_VdZx_WO_Ed_WZ,
176 BS3CG1ENC_MODRM_Vq_Mq,
177 BS3CG1ENC_MODRM_Vq_WO_UqHi,
178 BS3CG1ENC_MODRM_Vq_WO_Mq,
179 BS3CG1ENC_MODRM_VqHi_WO_Uq,
180 BS3CG1ENC_MODRM_VqHi_WO_Mq,
181 BS3CG1ENC_MODRM_VqZx_WO_Eq_WNZ,
182 BS3CG1ENC_MODRM_Vdq_WO_Mdq,
183 BS3CG1ENC_MODRM_Vdq_WO_Wdq,
184 BS3CG1ENC_MODRM_Vpd_WO_Wpd,
185 BS3CG1ENC_MODRM_Vps_WO_Wps,
186 BS3CG1ENC_MODRM_VssZx_WO_Wss,
187 BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
188 BS3CG1ENC_MODRM_VqZx_WO_Wq,
189 BS3CG1ENC_MODRM_VqZx_WO_Nq,
190 BS3CG1ENC_MODRM_Mb_RO,
191 BS3CG1ENC_MODRM_Md_RO,
192 BS3CG1ENC_MODRM_Md_WO,
193 BS3CG1ENC_MODRM_Mdq_WO_Vdq,
194 BS3CG1ENC_MODRM_Mq_WO_Pq,
195 BS3CG1ENC_MODRM_Mq_WO_Vq,
196 BS3CG1ENC_MODRM_Mq_WO_VqHi,
197 BS3CG1ENC_MODRM_Mps_WO_Vps,
198 BS3CG1ENC_MODRM_Mpd_WO_Vpd,
199
200 BS3CG1ENC_VEX_MODRM_Vd_WO_Ed_WZ,
201 BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
202 BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
203 BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss,
204 BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd,
205 BS3CG1ENC_VEX_MODRM_Vq_WO_Eq_WNZ,
206 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi,
207 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq,
208 BS3CG1ENC_VEX_MODRM_Vq_WO_Wq,
209 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
210 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
211 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0,
212 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1,
213 BS3CG1ENC_VEX_MODRM_Vx_WO_Wx,
214 BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ,
215 BS3CG1ENC_VEX_MODRM_Eq_WO_Vq_WNZ,
216 BS3CG1ENC_VEX_MODRM_Md_WO,
217 BS3CG1ENC_VEX_MODRM_Mq_WO_Vq,
218 BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
219 BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd,
220 BS3CG1ENC_VEX_MODRM_Mps_WO_Vps,
221 BS3CG1ENC_VEX_MODRM_Mpd_WO_Vpd,
222 BS3CG1ENC_VEX_MODRM_Mx_WO_Vx,
223 BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss,
224 BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd,
225 BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
226 BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
227 BS3CG1ENC_VEX_MODRM_Wq_WO_Vq,
228 BS3CG1ENC_VEX_MODRM_Wx_WO_Vx,
229
230 BS3CG1ENC_FIXED,
231 BS3CG1ENC_FIXED_AL_Ib,
232 BS3CG1ENC_FIXED_rAX_Iz,
233
234
235 BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
236 BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
237 //BS3CG1ENC_VEX_FIXED, /**< Unused or invalid instruction. */
238 BS3CG1ENC_VEX_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
239 BS3CG1ENC_VEX_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
240 BS3CG1ENC_VEX_MODRM, /**< Unused or invalid instruction. */
241
242 BS3CG1ENC_END
243} BS3CG1ENC;
244
245
246/**
247 * Prefix sensitivitiy kind.
248 */
249typedef enum BS3CG1PFXKIND
250{
251 BS3CG1PFXKIND_INVALID = 0,
252
253 BS3CG1PFXKIND_NO_F2_F3_66, /**< No 66, F2 or F3 prefixes allowed as that would alter the meaning. */
254 BS3CG1PFXKIND_REQ_F2, /**< Requires F2 (REPNE) prefix as part of the instr encoding. */
255 BS3CG1PFXKIND_REQ_F3, /**< Requires F3 (REPE) prefix as part of the instr encoding. */
256 BS3CG1PFXKIND_REQ_66, /**< Requires 66 (OP SIZE) prefix as part of the instr encoding. */
257
258 /** @todo more work to be done here... */
259 BS3CG1PFXKIND_MODRM,
260 BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
261
262 BS3CG1PFXKIND_END
263} BS3CG1PFXKIND;
264
265/**
266 * CPU selection or CPU ID.
267 */
268typedef enum BS3CG1CPU
269{
270 /** Works with an CPU. */
271 BS3CG1CPU_ANY = 0,
272 BS3CG1CPU_GE_80186,
273 BS3CG1CPU_GE_80286,
274 BS3CG1CPU_GE_80386,
275 BS3CG1CPU_GE_80486,
276 BS3CG1CPU_GE_Pentium,
277
278 BS3CG1CPU_MMX,
279 BS3CG1CPU_SSE,
280 BS3CG1CPU_SSE2,
281 BS3CG1CPU_SSE3,
282 BS3CG1CPU_SSE4_1,
283 BS3CG1CPU_AVX,
284 BS3CG1CPU_AVX2,
285 BS3CG1CPU_CLFSH,
286 BS3CG1CPU_CLFLUSHOPT,
287
288 BS3CG1CPU_END
289} BS3CG1CPU;
290
291
292/**
293 * SSE & AVX exception types.
294 */
295typedef enum BS3CG1XCPTTYPE
296{
297 BS3CG1XCPTTYPE_NONE = 0,
298 /* SSE: */
299 BS3CG1XCPTTYPE_1,
300 BS3CG1XCPTTYPE_2,
301 BS3CG1XCPTTYPE_3,
302 BS3CG1XCPTTYPE_4,
303 BS3CG1XCPTTYPE_4UA,
304 BS3CG1XCPTTYPE_5,
305 BS3CG1XCPTTYPE_5LZ,
306 BS3CG1XCPTTYPE_6,
307 BS3CG1XCPTTYPE_7,
308 BS3CG1XCPTTYPE_7LZ,
309 BS3CG1XCPTTYPE_8,
310 BS3CG1XCPTTYPE_11,
311 BS3CG1XCPTTYPE_12,
312 /* EVEX: */
313 BS3CG1XCPTTYPE_E1,
314 BS3CG1XCPTTYPE_E1NF,
315 BS3CG1XCPTTYPE_E2,
316 BS3CG1XCPTTYPE_E3,
317 BS3CG1XCPTTYPE_E3NF,
318 BS3CG1XCPTTYPE_E4,
319 BS3CG1XCPTTYPE_E4NF,
320 BS3CG1XCPTTYPE_E5,
321 BS3CG1XCPTTYPE_E5NF,
322 BS3CG1XCPTTYPE_E6,
323 BS3CG1XCPTTYPE_E6NF,
324 BS3CG1XCPTTYPE_E7NF,
325 BS3CG1XCPTTYPE_E9,
326 BS3CG1XCPTTYPE_E9NF,
327 BS3CG1XCPTTYPE_E10,
328 BS3CG1XCPTTYPE_E11,
329 BS3CG1XCPTTYPE_E12,
330 BS3CG1XCPTTYPE_E12NF,
331 BS3CG1XCPTTYPE_END
332} BS3CG1XCPTTYPE;
333AssertCompile(BS3CG1XCPTTYPE_END <= 32);
334
335
336/**
337 * Generated instruction info.
338 */
339typedef struct BS3CG1INSTR
340{
341 /** The opcode size. */
342 uint32_t cbOpcodes : 2;
343 /** The number of operands. */
344 uint32_t cOperands : 2;
345 /** The length of the mnemonic. */
346 uint32_t cchMnemonic : 4;
347 /** Whether to advance the mnemonic array pointer. */
348 uint32_t fAdvanceMnemonic : 1;
349 /** Offset into g_abBs3Cg1Tests of the first test. */
350 uint32_t offTests : 23;
351 /** BS3CG1ENC values. */
352 uint32_t enmEncoding : 10;
353 /** The VEX, EVEX or XOP opcode map number (VEX.mmmm). */
354 uint32_t uOpcodeMap : 4;
355 /** BS3CG1PFXKIND values. */
356 uint32_t enmPrefixKind : 4;
357 /** CPU test / CPU ID bit test (BS3CG1CPU). */
358 uint32_t enmCpuTest : 6;
359 /** Exception type (BS3CG1XCPTTYPE) */
360 uint32_t enmXcptType : 5;
361 /** Currently unused bits. */
362 uint32_t uUnused : 3;
363 /** BS3CG1INSTR_F_XXX. */
364 uint32_t fFlags;
365} BS3CG1INSTR;
366AssertCompileSize(BS3CG1INSTR, 12);
367/** Pointer to a const instruction. */
368typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
369
370
371/** @name BS3CG1INSTR_F_XXX
372 * @{ */
373/** Defaults to SS rather than DS. */
374#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
375/** Invalid instruction in 64-bit mode. */
376#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
377/** Unused instruction. */
378#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
379/** Invalid instruction. */
380#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
381/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
382 * Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
383#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
384/** VEX.L must be zero (IEMOPHINT_VEX_L_ZERO). */
385#define BS3CG1INSTR_F_VEX_L_ZERO UINT32_C(0x00000020)
386/** VEX.L is ignored (IEMOPHINT_VEX_L_IGNORED). */
387#define BS3CG1INSTR_F_VEX_L_IGNORED UINT32_C(0x00000040)
388/** @} */
389
390
391/**
392 * Test header.
393 */
394typedef struct BS3CG1TESTHDR
395{
396 /** The size of the selector program in bytes.
397 * This is also the offset of the input context modification program. */
398 uint32_t cbSelector : 8;
399 /** The size of the input context modification program in bytes.
400 * This immediately follows the selector program. */
401 uint32_t cbInput : 12;
402 /** The size of the output context modification program in bytes.
403 * This immediately follows the input context modification program. The
404 * program takes the result of the input program as starting point. */
405 uint32_t cbOutput : 11;
406 /** Indicates whether this is the last test or not. */
407 uint32_t fLast : 1;
408} BS3CG1TESTHDR;
409AssertCompileSize(BS3CG1TESTHDR, 4);
410/** Pointer to a const test header. */
411typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
412
413/** @name Opcode format for the BS3CG1 context modifier.
414 *
415 * Used by both the input and output context programs.
416 *
417 * The most common operations are encoded as a single byte opcode followed by
418 * one or more immediate bytes with data.
419 *
420 * @{ */
421#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
422#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
423#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
424#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
425#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
426#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
427#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
428#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
429#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /**< Separate byte encoding the value size following any destination escape byte. */
430
431#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
432#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
433#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
434#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
435#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /**< Separate byte giving the destination follows immediately. */
436
437#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /**< Whether to sign-extend (set) the immediate value. */
438
439#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
440#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /**< Simple assignment operator (=) */
441#define BS3CG1_CTXOP_OR UINT8_C(0x40) /**< OR assignment operator (|=). */
442#define BS3CG1_CTXOP_AND UINT8_C(0x80) /**< AND assignment operator (&=). */
443#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /**< AND assignment operator of the inverted value (&~=). */
444/** @} */
445
446/**
447 * Escaped destination values
448 *
449 * These are just uppercased versions of TestInOut.kdFields, where dots are
450 * replaced by underscores.
451 */
452typedef enum BS3CG1DST
453{
454 BS3CG1DST_INVALID = 0,
455 /* Operands. */
456 BS3CG1DST_OP1,
457 BS3CG1DST_OP2,
458 BS3CG1DST_OP3,
459 BS3CG1DST_OP4,
460 /* Flags. */
461 BS3CG1DST_EFL,
462 BS3CG1DST_EFL_UNDEF, /**< Special field only valid in output context modifiers: EFLAGS |= Value & Ouput.EFLAGS; */
463 /* 8-bit GPRs. */
464 BS3CG1DST_AL,
465 BS3CG1DST_CL,
466 BS3CG1DST_DL,
467 BS3CG1DST_BL,
468 BS3CG1DST_AH,
469 BS3CG1DST_CH,
470 BS3CG1DST_DH,
471 BS3CG1DST_BH,
472 BS3CG1DST_SPL,
473 BS3CG1DST_BPL,
474 BS3CG1DST_SIL,
475 BS3CG1DST_DIL,
476 BS3CG1DST_R8L,
477 BS3CG1DST_R9L,
478 BS3CG1DST_R10L,
479 BS3CG1DST_R11L,
480 BS3CG1DST_R12L,
481 BS3CG1DST_R13L,
482 BS3CG1DST_R14L,
483 BS3CG1DST_R15L,
484 /* 16-bit GPRs. */
485 BS3CG1DST_AX,
486 BS3CG1DST_CX,
487 BS3CG1DST_DX,
488 BS3CG1DST_BX,
489 BS3CG1DST_SP,
490 BS3CG1DST_BP,
491 BS3CG1DST_SI,
492 BS3CG1DST_DI,
493 BS3CG1DST_R8W,
494 BS3CG1DST_R9W,
495 BS3CG1DST_R10W,
496 BS3CG1DST_R11W,
497 BS3CG1DST_R12W,
498 BS3CG1DST_R13W,
499 BS3CG1DST_R14W,
500 BS3CG1DST_R15W,
501 /* 32-bit GPRs. */
502 BS3CG1DST_EAX,
503 BS3CG1DST_ECX,
504 BS3CG1DST_EDX,
505 BS3CG1DST_EBX,
506 BS3CG1DST_ESP,
507 BS3CG1DST_EBP,
508 BS3CG1DST_ESI,
509 BS3CG1DST_EDI,
510 BS3CG1DST_R8D,
511 BS3CG1DST_R9D,
512 BS3CG1DST_R10D,
513 BS3CG1DST_R11D,
514 BS3CG1DST_R12D,
515 BS3CG1DST_R13D,
516 BS3CG1DST_R14D,
517 BS3CG1DST_R15D,
518 /* 64-bit GPRs. */
519 BS3CG1DST_RAX,
520 BS3CG1DST_RCX,
521 BS3CG1DST_RDX,
522 BS3CG1DST_RBX,
523 BS3CG1DST_RSP,
524 BS3CG1DST_RBP,
525 BS3CG1DST_RSI,
526 BS3CG1DST_RDI,
527 BS3CG1DST_R8,
528 BS3CG1DST_R9,
529 BS3CG1DST_R10,
530 BS3CG1DST_R11,
531 BS3CG1DST_R12,
532 BS3CG1DST_R13,
533 BS3CG1DST_R14,
534 BS3CG1DST_R15,
535 /* 16-bit, 32-bit or 64-bit registers according to operand size. */
536 BS3CG1DST_OZ_RAX,
537 BS3CG1DST_OZ_RCX,
538 BS3CG1DST_OZ_RDX,
539 BS3CG1DST_OZ_RBX,
540 BS3CG1DST_OZ_RSP,
541 BS3CG1DST_OZ_RBP,
542 BS3CG1DST_OZ_RSI,
543 BS3CG1DST_OZ_RDI,
544 BS3CG1DST_OZ_R8,
545 BS3CG1DST_OZ_R9,
546 BS3CG1DST_OZ_R10,
547 BS3CG1DST_OZ_R11,
548 BS3CG1DST_OZ_R12,
549 BS3CG1DST_OZ_R13,
550 BS3CG1DST_OZ_R14,
551 BS3CG1DST_OZ_R15,
552
553 /* Control registers.*/
554 BS3CG1DST_CR0,
555 BS3CG1DST_CR4,
556 BS3CG1DST_XCR0,
557
558 /* FPU registers. */
559 BS3CG1DST_FPU_FIRST,
560 BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
561 BS3CG1DST_FSW,
562 BS3CG1DST_FTW,
563 BS3CG1DST_FOP,
564 BS3CG1DST_FPUIP,
565 BS3CG1DST_FPUCS,
566 BS3CG1DST_FPUDP,
567 BS3CG1DST_FPUDS,
568 BS3CG1DST_MXCSR,
569 BS3CG1DST_ST0,
570 BS3CG1DST_ST1,
571 BS3CG1DST_ST2,
572 BS3CG1DST_ST3,
573 BS3CG1DST_ST4,
574 BS3CG1DST_ST5,
575 BS3CG1DST_ST6,
576 BS3CG1DST_ST7,
577 /* MMX registers. */
578 BS3CG1DST_MM0,
579 BS3CG1DST_MM1,
580 BS3CG1DST_MM2,
581 BS3CG1DST_MM3,
582 BS3CG1DST_MM4,
583 BS3CG1DST_MM5,
584 BS3CG1DST_MM6,
585 BS3CG1DST_MM7,
586 BS3CG1DST_MM0_LO_ZX,
587 BS3CG1DST_MM1_LO_ZX,
588 BS3CG1DST_MM2_LO_ZX,
589 BS3CG1DST_MM3_LO_ZX,
590 BS3CG1DST_MM4_LO_ZX,
591 BS3CG1DST_MM5_LO_ZX,
592 BS3CG1DST_MM6_LO_ZX,
593 BS3CG1DST_MM7_LO_ZX,
594 /* SSE registers. */
595 BS3CG1DST_XMM0,
596 BS3CG1DST_XMM1,
597 BS3CG1DST_XMM2,
598 BS3CG1DST_XMM3,
599 BS3CG1DST_XMM4,
600 BS3CG1DST_XMM5,
601 BS3CG1DST_XMM6,
602 BS3CG1DST_XMM7,
603 BS3CG1DST_XMM8,
604 BS3CG1DST_XMM9,
605 BS3CG1DST_XMM10,
606 BS3CG1DST_XMM11,
607 BS3CG1DST_XMM12,
608 BS3CG1DST_XMM13,
609 BS3CG1DST_XMM14,
610 BS3CG1DST_XMM15,
611 BS3CG1DST_XMM0_LO,
612 BS3CG1DST_XMM1_LO,
613 BS3CG1DST_XMM2_LO,
614 BS3CG1DST_XMM3_LO,
615 BS3CG1DST_XMM4_LO,
616 BS3CG1DST_XMM5_LO,
617 BS3CG1DST_XMM6_LO,
618 BS3CG1DST_XMM7_LO,
619 BS3CG1DST_XMM8_LO,
620 BS3CG1DST_XMM9_LO,
621 BS3CG1DST_XMM10_LO,
622 BS3CG1DST_XMM11_LO,
623 BS3CG1DST_XMM12_LO,
624 BS3CG1DST_XMM13_LO,
625 BS3CG1DST_XMM14_LO,
626 BS3CG1DST_XMM15_LO,
627 BS3CG1DST_XMM0_HI,
628 BS3CG1DST_XMM1_HI,
629 BS3CG1DST_XMM2_HI,
630 BS3CG1DST_XMM3_HI,
631 BS3CG1DST_XMM4_HI,
632 BS3CG1DST_XMM5_HI,
633 BS3CG1DST_XMM6_HI,
634 BS3CG1DST_XMM7_HI,
635 BS3CG1DST_XMM8_HI,
636 BS3CG1DST_XMM9_HI,
637 BS3CG1DST_XMM10_HI,
638 BS3CG1DST_XMM11_HI,
639 BS3CG1DST_XMM12_HI,
640 BS3CG1DST_XMM13_HI,
641 BS3CG1DST_XMM14_HI,
642 BS3CG1DST_XMM15_HI,
643 BS3CG1DST_XMM0_LO_ZX,
644 BS3CG1DST_XMM1_LO_ZX,
645 BS3CG1DST_XMM2_LO_ZX,
646 BS3CG1DST_XMM3_LO_ZX,
647 BS3CG1DST_XMM4_LO_ZX,
648 BS3CG1DST_XMM5_LO_ZX,
649 BS3CG1DST_XMM6_LO_ZX,
650 BS3CG1DST_XMM7_LO_ZX,
651 BS3CG1DST_XMM8_LO_ZX,
652 BS3CG1DST_XMM9_LO_ZX,
653 BS3CG1DST_XMM10_LO_ZX,
654 BS3CG1DST_XMM11_LO_ZX,
655 BS3CG1DST_XMM12_LO_ZX,
656 BS3CG1DST_XMM13_LO_ZX,
657 BS3CG1DST_XMM14_LO_ZX,
658 BS3CG1DST_XMM15_LO_ZX,
659 BS3CG1DST_XMM0_DW0,
660 BS3CG1DST_XMM1_DW0,
661 BS3CG1DST_XMM2_DW0,
662 BS3CG1DST_XMM3_DW0,
663 BS3CG1DST_XMM4_DW0,
664 BS3CG1DST_XMM5_DW0,
665 BS3CG1DST_XMM6_DW0,
666 BS3CG1DST_XMM7_DW0,
667 BS3CG1DST_XMM8_DW0,
668 BS3CG1DST_XMM9_DW0,
669 BS3CG1DST_XMM10_DW0,
670 BS3CG1DST_XMM11_DW0,
671 BS3CG1DST_XMM12_DW0,
672 BS3CG1DST_XMM13_DW0,
673 BS3CG1DST_XMM14_DW0,
674 BS3CG1DST_XMM15_DW0,
675 BS3CG1DST_XMM0_DW0_ZX,
676 BS3CG1DST_XMM1_DW0_ZX,
677 BS3CG1DST_XMM2_DW0_ZX,
678 BS3CG1DST_XMM3_DW0_ZX,
679 BS3CG1DST_XMM4_DW0_ZX,
680 BS3CG1DST_XMM5_DW0_ZX,
681 BS3CG1DST_XMM6_DW0_ZX,
682 BS3CG1DST_XMM7_DW0_ZX,
683 BS3CG1DST_XMM8_DW0_ZX,
684 BS3CG1DST_XMM9_DW0_ZX,
685 BS3CG1DST_XMM10_DW0_ZX,
686 BS3CG1DST_XMM11_DW0_ZX,
687 BS3CG1DST_XMM12_DW0_ZX,
688 BS3CG1DST_XMM13_DW0_ZX,
689 BS3CG1DST_XMM14_DW0_ZX,
690 BS3CG1DST_XMM15_DW0_ZX,
691 BS3CG1DST_XMM0_HI96,
692 BS3CG1DST_XMM1_HI96,
693 BS3CG1DST_XMM2_HI96,
694 BS3CG1DST_XMM3_HI96,
695 BS3CG1DST_XMM4_HI96,
696 BS3CG1DST_XMM5_HI96,
697 BS3CG1DST_XMM6_HI96,
698 BS3CG1DST_XMM7_HI96,
699 BS3CG1DST_XMM8_HI96,
700 BS3CG1DST_XMM9_HI96,
701 BS3CG1DST_XMM10_HI96,
702 BS3CG1DST_XMM11_HI96,
703 BS3CG1DST_XMM12_HI96,
704 BS3CG1DST_XMM13_HI96,
705 BS3CG1DST_XMM14_HI96,
706 BS3CG1DST_XMM15_HI96,
707 /* AVX registers. */
708 BS3CG1DST_YMM0,
709 BS3CG1DST_YMM1,
710 BS3CG1DST_YMM2,
711 BS3CG1DST_YMM3,
712 BS3CG1DST_YMM4,
713 BS3CG1DST_YMM5,
714 BS3CG1DST_YMM6,
715 BS3CG1DST_YMM7,
716 BS3CG1DST_YMM8,
717 BS3CG1DST_YMM9,
718 BS3CG1DST_YMM10,
719 BS3CG1DST_YMM11,
720 BS3CG1DST_YMM12,
721 BS3CG1DST_YMM13,
722 BS3CG1DST_YMM14,
723 BS3CG1DST_YMM15,
724
725 /* Special fields: */
726 BS3CG1DST_SPECIAL_START,
727 BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /**< Expected exception based on input or result. */
728
729 BS3CG1DST_END
730} BS3CG1DST;
731AssertCompile(BS3CG1DST_END <= 256);
732
733/** @name Selector opcode definitions.
734 *
735 * Selector programs are very simple, they are zero or more predicate tests
736 * that are ANDed together. If a predicate test fails, the test is skipped.
737 *
738 * One instruction is encoded as byte, where the first bit indicates what kind
739 * of test and the 7 remaining bits indicates which predicate to check.
740 *
741 * @{ */
742#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /**< The operator part (put in lower bit to reduce switch value range). */
743#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /**< Check that the predicate is true. */
744#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /**< Check that the predicate is false. */
745#define BS3CG1SEL_OP_PRED_SHIFT 1 /**< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. */
746/** @} */
747
748/**
749 * Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
750 */
751typedef enum BS3CG1PRED
752{
753 BS3CG1PRED_INVALID = 0,
754
755 /* Operand size. */
756 BS3CG1PRED_SIZE_O16,
757 BS3CG1PRED_SIZE_O32,
758 BS3CG1PRED_SIZE_O64,
759 /* VEX.L values. */
760 BS3CG1PRED_VEXL_0,
761 BS3CG1PRED_VEXL_1,
762 /* Execution ring. */
763 BS3CG1PRED_RING_0,
764 BS3CG1PRED_RING_1,
765 BS3CG1PRED_RING_2,
766 BS3CG1PRED_RING_3,
767 BS3CG1PRED_RING_0_THRU_2,
768 BS3CG1PRED_RING_1_THRU_3,
769 /* Basic code mode. */
770 BS3CG1PRED_CODE_64BIT,
771 BS3CG1PRED_CODE_32BIT,
772 BS3CG1PRED_CODE_16BIT,
773 /* CPU modes. */
774 BS3CG1PRED_MODE_REAL,
775 BS3CG1PRED_MODE_PROT,
776 BS3CG1PRED_MODE_LONG,
777 BS3CG1PRED_MODE_V86,
778 BS3CG1PRED_MODE_SMM,
779 BS3CG1PRED_MODE_VMX,
780 BS3CG1PRED_MODE_SVM,
781 /* Paging on/off */
782 BS3CG1PRED_PAGING_ON,
783 BS3CG1PRED_PAGING_OFF,
784 /* CPU Vendors. */
785 BS3CG1PRED_VENDOR_AMD,
786 BS3CG1PRED_VENDOR_INTEL,
787 BS3CG1PRED_VENDOR_VIA,
788 BS3CG1PRED_VENDOR_SHANGHAI,
789 BS3CG1PRED_VENDOR_HYGON,
790
791 BS3CG1PRED_END
792} BS3CG1PRED;
793
794
795/** The test instructions (generated). */
796extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
797/** The number of test instructions (generated). */
798extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
799/** The mnemonics (generated).
800 * Variable length sequence of mnemonics that runs in parallel to
801 * g_aBs3Cg1Instructions. */
802extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
803/** The opcodes (generated).
804 * Variable length sequence of opcode bytes that runs in parallel to
805 * g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
806extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
807/** The operands (generated).
808 * Variable length sequence of opcode values (BS3CG1OP) that runs in
809 * parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
810extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
811/** The test data that BS3CG1INSTR.
812 * In order to simplify generating these, we use a byte array. */
813extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
814
815
816#endif /* !VBOX_INCLUDED_SRC_bootsectors_bs3_cpu_generated_1_h */
817
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