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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac@ 70651

Last change on this file since 70651 was 70651, checked in by vboxsync, 7 years ago

bootsectors/bs3-cpu-instr-2: Added testcase for FSGSBASE instructions.
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File size: 7.8 KB
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1; $Id: bs3-cpu-instr-2-template.mac 70651 2018-01-19 16:00:42Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-instr-2 assembly template.
4;
5
6;
7; Copyright (C) 2007-2017 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; The contents of this file may alternatively be used under the terms
18; of the Common Development and Distribution License Version 1.0
19; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20; VirtualBox OSE distribution, in which case the provisions of the
21; CDDL are applicable instead of those of the GPL.
22;
23; You may elect to license modified versions of this file under the
24; terms and conditions of either the GPL or the CDDL or both.
25;
26
27
28;*********************************************************************************************************************************
29;* Header Files *
30;*********************************************************************************************************************************
31%include "bs3kit-template-header.mac" ; setup environment
32
33
34;*********************************************************************************************************************************
35;* External Symbols *
36;*********************************************************************************************************************************
37TMPL_BEGIN_TEXT
38
39
40;
41; Test code snippets containing code which differs between 16-bit, 32-bit
42; and 64-bit CPUs modes.
43;
44%ifdef BS3_INSTANTIATING_CMN
45
46BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
47 mul xBX
48.again:
49 ud2
50 jmp .again
51BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2
52
53
54BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
55 imul xBX
56.again:
57 ud2
58 jmp .again
59BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2
60
61
62BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
63 imul xCX, xBX
64.again:
65 ud2
66 jmp .again
67BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2
68
69
70BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
71 div xBX
72.again:
73 ud2
74 jmp .again
75BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2
76
77
78BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
79 idiv xBX
80.again:
81 ud2
82 jmp .again
83BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2
84
85
86 %if TMPL_BITS == 64
87BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
88 cmpxchg16b [rdi]
89.again:
90 ud2
91 jmp .again
92AssertCompile(.again - BS3_LAST_LABEL == 4)
93BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2
94
95
96BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
97 lock cmpxchg16b [rdi]
98.again:
99 ud2
100 jmp .again
101AssertCompile(.again - BS3_LAST_LABEL == 5)
102BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
103
104
105BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
106 o16 cmpxchg16b [rdi]
107.again:
108 ud2
109 jmp .again
110AssertCompile(.again - BS3_LAST_LABEL == 5)
111BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
112
113
114BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
115 db 0f0h, 066h
116 cmpxchg16b [rdi]
117.again:
118 ud2
119 jmp .again
120AssertCompile(.again - BS3_LAST_LABEL == 6)
121BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
122
123
124BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
125 repz cmpxchg16b [rdi]
126.again:
127 ud2
128 jmp .again
129AssertCompile(.again - BS3_LAST_LABEL == 5)
130BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
131
132
133BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
134 db 0f0h, 0f3h
135 cmpxchg16b [rdi]
136.again:
137 ud2
138 jmp .again
139AssertCompile(.again - BS3_LAST_LABEL == 6)
140BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
141
142BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
143 repnz cmpxchg16b [rdi]
144.again:
145 ud2
146 jmp .again
147AssertCompile(.again - BS3_LAST_LABEL == 5)
148BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
149
150
151BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
152 db 0f0h, 0f2h
153 cmpxchg16b [rdi]
154.again:
155 ud2
156 jmp .again
157AssertCompile(.again - BS3_LAST_LABEL == 6)
158BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
159
160
161BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
162 wrfsbase rbx
163.again:
164 ud2
165 jmp .again
166AssertCompile(.again - BS3_LAST_LABEL == 5)
167BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2
168
169
170BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
171 wrfsbase ebx
172.again:
173 ud2
174 jmp .again
175AssertCompile(.again - BS3_LAST_LABEL == 4)
176BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2
177
178
179BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
180 wrgsbase rbx
181.again:
182 ud2
183 jmp .again
184AssertCompile(.again - BS3_LAST_LABEL == 5)
185BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2
186
187
188BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
189 wrgsbase ebx
190.again:
191 ud2
192 jmp .again
193AssertCompile(.again - BS3_LAST_LABEL == 4)
194BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2
195
196
197BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
198 wrfsbase rbx
199 rdfsbase rcx
200.again:
201 ud2
202 jmp .again
203AssertCompile(.again - BS3_LAST_LABEL == 10)
204BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2
205
206
207BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
208 wrfsbase ebx
209 rdfsbase ecx
210.again:
211 ud2
212 jmp .again
213AssertCompile(.again - BS3_LAST_LABEL == 8)
214BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2
215
216
217BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
218 wrgsbase rbx
219 rdgsbase rcx
220.again:
221 ud2
222 jmp .again
223AssertCompile(.again - BS3_LAST_LABEL == 10)
224BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2
225
226
227BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
228 wrgsbase ebx
229 rdgsbase ecx
230.again:
231 ud2
232 jmp .again
233AssertCompile(.again - BS3_LAST_LABEL == 8)
234BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2
235
236
237BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
238 rdfsbase rbx
239.again:
240 ud2
241 jmp .again
242AssertCompile(.again - BS3_LAST_LABEL == 5)
243BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2
244
245
246BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
247 rdfsbase ebx
248.again:
249 ud2
250 jmp .again
251AssertCompile(.again - BS3_LAST_LABEL == 4)
252BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2
253
254
255BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
256 rdgsbase rbx
257.again:
258 ud2
259 jmp .again
260AssertCompile(.again - BS3_LAST_LABEL == 5)
261BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2
262
263
264BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
265 rdgsbase ebx
266.again:
267 ud2
268 jmp .again
269AssertCompile(.again - BS3_LAST_LABEL == 4)
270BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2
271
272
273;; @todo figure out this fudge. sigh.
274times (348) db 0cch ; fudge to avoid 'rderr' during boot.
275
276 %endif ; TMPL_BITS == 64
277
278
279%endif ; BS3_INSTANTIATING_CMN
280
281%include "bs3kit-template-footer.mac" ; reset environment
282
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