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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac@ 95533

Last change on this file since 95533 was 95532, checked in by vboxsync, 3 years ago

ValKit/bs3-cpu-instr-3: Simple [v]movlps tests. bugref:9898

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1; $Id: bs3-cpu-instr-3-template.mac 95532 2022-07-06 18:10:43Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-instr-3 - MMX, SSE and AVX instructions, assembly template.
4;
5
6;
7; Copyright (C) 2007-2022 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; The contents of this file may alternatively be used under the terms
18; of the Common Development and Distribution License Version 1.0
19; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20; VirtualBox OSE distribution, in which case the provisions of the
21; CDDL are applicable instead of those of the GPL.
22;
23; You may elect to license modified versions of this file under the
24; terms and conditions of either the GPL or the CDDL or both.
25;
26
27
28;*********************************************************************************************************************************
29;* Header Files *
30;*********************************************************************************************************************************
31%include "bs3kit-template-header.mac" ; setup environment
32
33
34;*********************************************************************************************************************************
35;* External Symbols *
36;*********************************************************************************************************************************
37TMPL_BEGIN_TEXT
38
39
40;
41; Test code snippets containing code which differs between 16-bit, 32-bit
42; and 64-bit CPUs modes.
43;
44%ifdef BS3_INSTANTIATING_CMN
45
46
47;;
48; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function
49; with an instruction length byte.
50;
51; ASSUMES the length is between the start of the function and the .again label.
52;
53 %ifndef BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED
54 %define BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED
55 %macro BS3CPUINSTR3_PROC_BEGIN_CMN 1
56 align 8, db 0cch
57 db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
58BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR
59 %endmacro
60 %endif
61
62;;
63; The EMIT_INSTR_PLUS_ICEBP macros is for creating a common function for and
64; named after a single instruction, followed by a looping ICEBP.
65;
66; This works like a prefix to the instruction invocation, only exception is that
67; instead of [fs:xBX] you write FSxBS as that's what is wanted in the name.
68;
69 %ifndef EMIT_INSTR_PLUS_ICEBP_DEFINED
70 %define EMIT_INSTR_PLUS_ICEBP_DEFINED
71
72 %macro EMIT_INSTR_PLUS_ICEBP 2
73BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _icebp
74 %define FSxBX [fs:xBX]
75 %1 %2
76 %undef FSxBX
77.again:
78 icebp
79 jmp .again
80BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _icebp
81 %endmacro
82
83 %macro EMIT_INSTR_PLUS_ICEBP 3
84BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp
85 %define FSxBX [fs:xBX]
86 %1 %2, %3
87 %undef FSxBX
88.again:
89 icebp
90 jmp .again
91BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp
92 %endmacro
93
94 %macro EMIT_INSTR_PLUS_ICEBP 4
95BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp
96 %define FSxBX [fs:xBX]
97 %1 %2, %3, %4
98 %undef FSxBX
99.again:
100 icebp
101 jmp .again
102BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp
103 %endmacro
104
105 %macro EMIT_INSTR_PLUS_ICEBP 5
106BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp
107 %define FSxBX [fs:xBX]
108 %1 %2, %3, %4, %5
109 %undef FSxBX
110.again:
111 icebp
112 jmp .again
113BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp
114 %endmacro
115
116 %endif
117
118
119
120%ifndef EMIT_TYPE1_INSTR_DEFINED
121 %define EMIT_TYPE1_INSTR_DEFINED
122 ;; @param 7 Indicates whether the 2nd and 3rd pair has MMX variants.
123 %macro EMIT_TYPE1_INSTR 7
124;
125; PXOR (SSE2) & VPXOR (AVX2)
126;
127BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_MM2_icebp
128 %1 mm1, mm2
129.again:
130 icebp
131 jmp .again
132BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_MM2_icebp
133
134BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_FSxBX_icebp
135 %1 mm1, [fs:xBX]
136.again:
137 icebp
138 jmp .again
139BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_FSxBX_icebp
140
141BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_XMM2_icebp
142 %1 xmm1, xmm2
143.again:
144 icebp
145 jmp .again
146BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_XMM2_icebp
147
148BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_FSxBX_icebp
149 %1 xmm1, [fs:xBX]
150.again:
151 icebp
152 jmp .again
153BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_FSxBX_icebp
154
155BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_XMM2_icebp
156 %2 xmm1, xmm1, xmm2
157.again:
158 icebp
159 jmp .again
160BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_XMM2_icebp
161
162BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_FSxBX_icebp
163 %2 xmm1, xmm1, [fs:xBX]
164.again:
165 icebp
166 jmp .again
167BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_FSxBX_icebp
168
169BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_YMM3_icebp
170 %2 ymm7, ymm2, ymm3
171.again:
172 icebp
173 jmp .again
174BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_YMM3_icebp
175
176BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_FSxBX_icebp
177 %2 ymm7, ymm2, [fs:xBX]
178.again:
179 icebp
180 jmp .again
181BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_FSxBX_icebp
182
183
184;
185; XORPS (SSE2) & VXORPS (AVX)
186;
187 %if %7 != 0
188BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_MM2_icebp
189 %3 mm1, mm2
190.again:
191 icebp
192 jmp .again
193BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_MM2_icebp
194
195BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_FSxBX_icebp
196 %3 mm1, [fs:xBX]
197.again:
198 icebp
199 jmp .again
200BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_FSxBX_icebp
201 %endif
202
203BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_XMM2_icebp
204 %3 xmm1, xmm2
205.again:
206 icebp
207 jmp .again
208BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_XMM2_icebp
209
210BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_FSxBX_icebp
211 %3 xmm1, [fs:xBX]
212.again:
213 icebp
214 jmp .again
215BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_FSxBX_icebp
216
217BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_XMM2_icebp
218 %4 xmm1, xmm1, xmm2
219.again:
220 icebp
221 jmp .again
222BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_XMM2_icebp
223
224BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_FSxBX_icebp
225 %4 xmm1, xmm1, [fs:xBX]
226.again:
227 icebp
228 jmp .again
229BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_FSxBX_icebp
230
231BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_YMM2_icebp
232 %4 ymm1, ymm1, ymm2
233.again:
234 icebp
235 jmp .again
236BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_YMM2_icebp
237
238BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_FSxBX_icebp
239 %4 ymm1, ymm1, [fs:xBX]
240.again:
241 icebp
242 jmp .again
243BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_FSxBX_icebp
244
245
246
247;
248; XORPD (SSE2) & VXORPD (AVX)
249;
250 %if %7 != 0
251BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_MM2_icebp
252 %5 mm1, mm2
253.again:
254 icebp
255 jmp .again
256BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_MM2_icebp
257
258BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_FSxBX_icebp
259 %5 mm1, [fs:xBX]
260.again:
261 icebp
262 jmp .again
263BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_FSxBX_icebp
264 %endif
265
266BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_XMM2_icebp
267 %5 xmm1, xmm2
268.again:
269 icebp
270 jmp .again
271BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_XMM2_icebp
272
273BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_FSxBX_icebp
274 %5 xmm1, [fs:xBX]
275.again:
276 icebp
277 jmp .again
278BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_FSxBX_icebp
279
280BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_XMM0_icebp
281 %6 xmm2, xmm1, xmm0
282.again:
283 icebp
284 jmp .again
285BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_XMM0_icebp
286
287BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_FSxBX_icebp
288 %6 xmm2, xmm1, [fs:xBX]
289.again:
290 icebp
291 jmp .again
292BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_FSxBX_icebp
293
294BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_YMM0_icebp
295 %6 ymm2, ymm1, ymm0
296.again:
297 icebp
298 jmp .again
299BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_YMM0_icebp
300
301BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_FSxBX_icebp
302 %6 ymm2, ymm1, [fs:xBX]
303.again:
304 icebp
305 jmp .again
306BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_FSxBX_icebp
307
308 %if TMPL_BITS == 64
309BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM10_YMM8_YMM15_icebp
310 %6 ymm10, ymm8, ymm15
311.again:
312 icebp
313 jmp .again
314BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM10_YMM8_YMM15_icebp
315 %endif
316
317 %endmacro ; EMIT_TYPE1_INSTR
318
319 %macro EMIT_TYPE1_ONE_INSTR 3
320 %if %3 != 0
321BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_MM2_icebp
322 %1 mm1, mm2
323.again:
324 icebp
325 jmp .again
326BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_MM2_icebp
327
328BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_FSxBX_icebp
329 %1 mm1, [fs:xBX]
330.again:
331 icebp
332 jmp .again
333BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_FSxBX_icebp
334 %endif
335
336BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_XMM2_icebp
337 %1 xmm1, xmm2
338.again:
339 icebp
340 jmp .again
341BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_XMM2_icebp
342
343BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_FSxBX_icebp
344 %1 xmm1, [fs:xBX]
345.again:
346 icebp
347 jmp .again
348BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_FSxBX_icebp
349
350BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _XMM2_XMM1_XMM0_icebp
351 %2 xmm2, xmm1, xmm0
352.again:
353 icebp
354 jmp .again
355BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _XMM2_XMM1_XMM0_icebp
356
357BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _XMM2_XMM1_FSxBX_icebp
358 %2 xmm2, xmm1, [fs:xBX]
359.again:
360 icebp
361 jmp .again
362BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _XMM2_XMM1_FSxBX_icebp
363
364BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM2_YMM1_YMM0_icebp
365 %2 ymm2, ymm1, ymm0
366.again:
367 icebp
368 jmp .again
369BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM2_YMM1_YMM0_icebp
370
371BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM2_YMM1_FSxBX_icebp
372 %2 ymm2, ymm1, [fs:xBX]
373.again:
374 icebp
375 jmp .again
376BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM2_YMM1_FSxBX_icebp
377
378 %if TMPL_BITS == 64
379BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM10_YMM8_YMM15_icebp
380 %2 ymm10, ymm8, ymm15
381.again:
382 icebp
383 jmp .again
384BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM10_YMM8_YMM15_icebp
385 %endif
386 %endmacro ; EMIT_TYPE1_ONE_INSTR
387
388%endif
389
390EMIT_TYPE1_INSTR pand, vpand, andps, vandps, andpd, vandpd, 0
391EMIT_TYPE1_INSTR pandn, vpandn, andnps, vandnps, andnpd, vandnpd, 0
392EMIT_TYPE1_INSTR por, vpor, orps, vorps, orpd, vorpd, 0
393EMIT_TYPE1_INSTR pxor, vpxor, xorps, vxorps, xorpd, vxorpd, 0
394
395EMIT_TYPE1_INSTR pcmpgtb, vpcmpgtb, pcmpgtw, vpcmpgtw, pcmpgtd, vpcmpgtd, 1
396EMIT_TYPE1_ONE_INSTR pcmpgtq, vpcmpgtq, 0
397EMIT_TYPE1_INSTR pcmpeqb, vpcmpeqb, pcmpeqw, vpcmpeqw, pcmpeqd, vpcmpeqd, 1
398EMIT_TYPE1_ONE_INSTR pcmpeqq, vpcmpeqq, 0
399
400EMIT_TYPE1_INSTR paddb, vpaddb, paddw, vpaddw, paddd, vpaddd, 1
401EMIT_TYPE1_ONE_INSTR paddq, vpaddq, 1
402
403EMIT_TYPE1_INSTR psubb, vpsubb, psubw, vpsubw, psubd, vpsubd, 1
404EMIT_TYPE1_ONE_INSTR psubq, vpsubq, 1
405
406
407;
408; Type 2 instructions. On the form: pxxxx sAX, [zy]mm0
409;
410%ifndef EMIT_TYPE2_ONE_INSTR_DEFINED
411 %define EMIT_TYPE2_ONE_INSTR_DEFINED
412 ;; @param 1 MMX/SSE instruction name
413 ;; @param 2 AVX instruction name
414 ;; @param 3 Whether to emit MMX function
415 ;; @param 4 The opcode byte. (assuming two byte / vex map 1)
416 %macro EMIT_TYPE2_ONE_INSTR 4
417 %if %3 != 0
418BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_MM2_icebp
419 %1 eax, mm2
420.again:
421 icebp
422 jmp .again
423BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_MM2_icebp
424
425BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_qword_FSxBX_icebp
426 %if TMPL_BITS == 16
427 db 64h, 0fh, %4, 7 ; %1 eax, qword [fs:xBX]
428 %else
429 db 64h, 0fh, %4, 3 ; %1 eax, qword [fs:xBX]
430 %endif
431.again:
432 icebp
433 jmp .again
434BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_qword_FSxBX_icebp
435 %endif
436
437BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_XMM2_icebp
438 %1 eax, xmm2
439.again:
440 icebp
441 jmp .again
442BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_XMM2_icebp
443
444BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_dqword_FSxBX_icebp
445 %if TMPL_BITS == 16
446 db 64h, 66h, 0fh, %4, 7 ; %1 eax, dqword [fs:xBX]
447 %else
448 db 64h, 66h, 0fh, %4, 3 ; %1 eax, dqword [fs:xBX]
449 %endif
450.again:
451 icebp
452 jmp .again
453BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _EAX_dqword_FSxBX_icebp
454
455BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_XMM2_icebp
456 %2 eax, xmm2
457.again:
458 icebp
459 jmp .again
460BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_XMM2_icebp
461
462BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_dqword_FSxBX_icebp
463 %if TMPL_BITS == 16
464 db 64h, 0c4h, 0e0h, 071h, %4, 7 ; %2 eax, dqword [fs:xBX]
465 %else
466 db 64h, 0c4h, 0e0h, 071h, %4, 3 ; %2 eax, dqword [fs:xBX]
467 %endif
468.again:
469 icebp
470 jmp .again
471BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_dqword_FSxBX_icebp
472
473BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_YMM2_icebp
474 %2 eax, ymm2
475.again:
476 icebp
477 jmp .again
478BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_YMM2_icebp
479
480BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_qqword_FSxBX_icebp
481 %if TMPL_BITS == 16
482 db 64h, 0c4h, 0e0h, 075h, %4, 7 ; %2 eax, qqword [fs:xBX]
483 %else
484 db 64h, 0c4h, 0e0h, 075h, %4, 3 ; %2 eax, qqword [fs:xBX]
485 %endif
486.again:
487 icebp
488 jmp .again
489BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _EAX_qqword_FSxBX_icebp
490
491 %if TMPL_BITS == 64
492BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _RAX_YMM9_icebp
493 %2 rax, ymm9
494.again:
495 icebp
496 jmp .again
497BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _RAX_YMM9_icebp
498 %endif
499 %endmacro ; EMIT_TYPE2_ONE_INSTR
500%endif
501
502EMIT_TYPE2_ONE_INSTR pmovmskb, vpmovmskb, 1, 0d7h
503
504;
505; [V]PSHUFB
506;
507EMIT_INSTR_PLUS_ICEBP pshufb, MM1, MM2
508EMIT_INSTR_PLUS_ICEBP pshufb, MM1, FSxBX
509
510EMIT_INSTR_PLUS_ICEBP pshufb, XMM1, XMM2
511EMIT_INSTR_PLUS_ICEBP pshufb, XMM1, FSxBX
512 %if TMPL_BITS == 64
513EMIT_INSTR_PLUS_ICEBP pshufb, XMM8, XMM9
514EMIT_INSTR_PLUS_ICEBP pshufb, XMM8, FSxBX
515 %endif
516
517EMIT_INSTR_PLUS_ICEBP vpshufb, XMM1, XMM2, XMM3
518EMIT_INSTR_PLUS_ICEBP vpshufb, XMM1, XMM2, FSxBX
519 %if TMPL_BITS == 64
520EMIT_INSTR_PLUS_ICEBP vpshufb, XMM8, XMM9, XMM10
521EMIT_INSTR_PLUS_ICEBP vpshufb, XMM8, XMM9, FSxBX
522 %endif
523
524EMIT_INSTR_PLUS_ICEBP vpshufb, YMM1, YMM2, YMM3
525EMIT_INSTR_PLUS_ICEBP vpshufb, YMM1, YMM2, FSxBX
526 %if TMPL_BITS == 64
527EMIT_INSTR_PLUS_ICEBP vpshufb, YMM8, YMM9, YMM10
528EMIT_INSTR_PLUS_ICEBP vpshufb, YMM8, YMM9, FSxBX
529 %endif
530
531;
532; PSHUFW
533;
534EMIT_INSTR_PLUS_ICEBP pshufw, MM1, MM2, 0FFh ; FF = top src word in all destination words
535EMIT_INSTR_PLUS_ICEBP pshufw, MM1, FSxBX, 0FFh
536EMIT_INSTR_PLUS_ICEBP pshufw, MM1, MM2, 01Bh ; 1B = word swap (like bswap but for words)
537EMIT_INSTR_PLUS_ICEBP pshufw, MM1, FSxBX, 01Bh
538
539;
540; [V]PSHUFHW
541;
542EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, XMM2, 0FFh
543EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, FSxBX, 0FFh
544EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, XMM2, 01Bh
545EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, FSxBX, 01Bh
546
547EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, XMM2, 0FFh
548EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, FSxBX, 0FFh
549EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, XMM2, 01Bh
550EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, FSxBX, 01Bh
551
552EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, YMM2, 0FFh
553EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, FSxBX, 0FFh
554EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, YMM2, 01Bh
555EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, FSxBX, 01Bh
556
557 %if TMPL_BITS == 64
558EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM12, YMM7, 0FFh
559EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM9, YMM12, 01Bh
560 %endif
561
562;
563; [V]PSHUFLW
564;
565EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, XMM2, 0FFh
566EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, FSxBX, 0FFh
567EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, XMM2, 01Bh
568EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, FSxBX, 01Bh
569
570EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, XMM2, 0FFh
571EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, FSxBX, 0FFh
572EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, XMM2, 01Bh
573EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, FSxBX, 01Bh
574
575EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, YMM2, 0FFh
576EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, FSxBX, 0FFh
577EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, YMM2, 01Bh
578EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, FSxBX, 01Bh
579
580 %if TMPL_BITS == 64
581EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM12, YMM7, 0FFh
582EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM9, YMM12, 01Bh
583 %endif
584
585;
586; [V]PSHUFD
587;
588EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, XMM2, 0FFh
589EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, FSxBX, 0FFh
590EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, XMM2, 01Bh
591EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, FSxBX, 01Bh
592
593EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, XMM2, 0FFh
594EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, FSxBX, 0FFh
595EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, XMM2, 01Bh
596EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, FSxBX, 01Bh
597
598EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, YMM2, 0FFh
599EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, FSxBX, 0FFh
600EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, YMM2, 01Bh
601EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, FSxBX, 01Bh
602
603 %if TMPL_BITS == 64
604EMIT_INSTR_PLUS_ICEBP vpshufd, YMM12, YMM7, 0FFh
605EMIT_INSTR_PLUS_ICEBP vpshufd, YMM9, YMM12, 01Bh
606 %endif
607
608;
609; [V]PUNPCKHBW
610;
611EMIT_INSTR_PLUS_ICEBP punpckhbw, MM1, MM2
612EMIT_INSTR_PLUS_ICEBP punpckhbw, MM1, FSxBX
613
614EMIT_INSTR_PLUS_ICEBP punpckhbw, XMM1, XMM2
615EMIT_INSTR_PLUS_ICEBP punpckhbw, XMM1, FSxBX
616 %if TMPL_BITS == 64
617EMIT_INSTR_PLUS_ICEBP punpckhbw, XMM8, XMM9
618EMIT_INSTR_PLUS_ICEBP punpckhbw, XMM8, FSxBX
619 %endif
620
621EMIT_INSTR_PLUS_ICEBP vpunpckhbw, XMM1, XMM2, XMM3
622EMIT_INSTR_PLUS_ICEBP vpunpckhbw, XMM1, XMM2, FSxBX
623 %if TMPL_BITS == 64
624EMIT_INSTR_PLUS_ICEBP vpunpckhbw, XMM8, XMM9, XMM10
625EMIT_INSTR_PLUS_ICEBP vpunpckhbw, XMM8, XMM9, FSxBX
626 %endif
627
628EMIT_INSTR_PLUS_ICEBP vpunpckhbw, YMM1, YMM2, YMM3
629EMIT_INSTR_PLUS_ICEBP vpunpckhbw, YMM1, YMM2, FSxBX
630 %if TMPL_BITS == 64
631EMIT_INSTR_PLUS_ICEBP vpunpckhbw, YMM8, YMM9, YMM10
632EMIT_INSTR_PLUS_ICEBP vpunpckhbw, YMM8, YMM9, FSxBX
633 %endif
634
635;
636; [V]PUNPCKHWD
637;
638EMIT_INSTR_PLUS_ICEBP punpckhwd, MM1, MM2
639EMIT_INSTR_PLUS_ICEBP punpckhwd, MM1, FSxBX
640
641EMIT_INSTR_PLUS_ICEBP punpckhwd, XMM1, XMM2
642EMIT_INSTR_PLUS_ICEBP punpckhwd, XMM1, FSxBX
643 %if TMPL_BITS == 64
644EMIT_INSTR_PLUS_ICEBP punpckhwd, XMM8, XMM9
645EMIT_INSTR_PLUS_ICEBP punpckhwd, XMM8, FSxBX
646 %endif
647
648EMIT_INSTR_PLUS_ICEBP vpunpckhwd, XMM1, XMM2, XMM3
649EMIT_INSTR_PLUS_ICEBP vpunpckhwd, XMM1, XMM2, FSxBX
650 %if TMPL_BITS == 64
651EMIT_INSTR_PLUS_ICEBP vpunpckhwd, XMM8, XMM9, XMM10
652EMIT_INSTR_PLUS_ICEBP vpunpckhwd, XMM8, XMM9, FSxBX
653 %endif
654
655EMIT_INSTR_PLUS_ICEBP vpunpckhwd, YMM1, YMM2, YMM3
656EMIT_INSTR_PLUS_ICEBP vpunpckhwd, YMM1, YMM2, FSxBX
657 %if TMPL_BITS == 64
658EMIT_INSTR_PLUS_ICEBP vpunpckhwd, YMM8, YMM9, YMM10
659EMIT_INSTR_PLUS_ICEBP vpunpckhwd, YMM8, YMM9, FSxBX
660 %endif
661
662;
663; [V]PUNPCKHDQ
664;
665EMIT_INSTR_PLUS_ICEBP punpckhdq, MM1, MM2
666EMIT_INSTR_PLUS_ICEBP punpckhdq, MM1, FSxBX
667
668EMIT_INSTR_PLUS_ICEBP punpckhdq, XMM1, XMM2
669EMIT_INSTR_PLUS_ICEBP punpckhdq, XMM1, FSxBX
670 %if TMPL_BITS == 64
671EMIT_INSTR_PLUS_ICEBP punpckhdq, XMM8, XMM9
672EMIT_INSTR_PLUS_ICEBP punpckhdq, XMM8, FSxBX
673 %endif
674
675EMIT_INSTR_PLUS_ICEBP vpunpckhdq, XMM1, XMM2, XMM3
676EMIT_INSTR_PLUS_ICEBP vpunpckhdq, XMM1, XMM2, FSxBX
677 %if TMPL_BITS == 64
678EMIT_INSTR_PLUS_ICEBP vpunpckhdq, XMM8, XMM9, XMM10
679EMIT_INSTR_PLUS_ICEBP vpunpckhdq, XMM8, XMM9, FSxBX
680 %endif
681
682EMIT_INSTR_PLUS_ICEBP vpunpckhdq, YMM1, YMM2, YMM3
683EMIT_INSTR_PLUS_ICEBP vpunpckhdq, YMM1, YMM2, FSxBX
684 %if TMPL_BITS == 64
685EMIT_INSTR_PLUS_ICEBP vpunpckhdq, YMM8, YMM9, YMM10
686EMIT_INSTR_PLUS_ICEBP vpunpckhdq, YMM8, YMM9, FSxBX
687 %endif
688
689;
690; [V]PUNPCKHQDQ (no MMX)
691;
692EMIT_INSTR_PLUS_ICEBP punpckhqdq, XMM1, XMM2
693EMIT_INSTR_PLUS_ICEBP punpckhqdq, XMM1, FSxBX
694 %if TMPL_BITS == 64
695EMIT_INSTR_PLUS_ICEBP punpckhqdq, XMM8, XMM9
696EMIT_INSTR_PLUS_ICEBP punpckhqdq, XMM8, FSxBX
697 %endif
698
699EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, XMM1, XMM2, XMM3
700EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, XMM1, XMM2, FSxBX
701 %if TMPL_BITS == 64
702EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, XMM8, XMM9, XMM10
703EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, XMM8, XMM9, FSxBX
704 %endif
705
706EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, YMM1, YMM2, YMM3
707EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, YMM1, YMM2, FSxBX
708 %if TMPL_BITS == 64
709EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, YMM8, YMM9, YMM10
710EMIT_INSTR_PLUS_ICEBP vpunpckhqdq, YMM8, YMM9, FSxBX
711 %endif
712
713;
714; [V]PUNPCKLBW
715;
716EMIT_INSTR_PLUS_ICEBP punpcklbw, MM1, MM2
717EMIT_INSTR_PLUS_ICEBP punpcklbw, MM1, FSxBX
718
719EMIT_INSTR_PLUS_ICEBP punpcklbw, XMM1, XMM2
720EMIT_INSTR_PLUS_ICEBP punpcklbw, XMM1, FSxBX
721 %if TMPL_BITS == 64
722EMIT_INSTR_PLUS_ICEBP punpcklbw, XMM8, XMM9
723EMIT_INSTR_PLUS_ICEBP punpcklbw, XMM8, FSxBX
724 %endif
725
726EMIT_INSTR_PLUS_ICEBP vpunpcklbw, XMM1, XMM2, XMM3
727EMIT_INSTR_PLUS_ICEBP vpunpcklbw, XMM1, XMM2, FSxBX
728 %if TMPL_BITS == 64
729EMIT_INSTR_PLUS_ICEBP vpunpcklbw, XMM8, XMM9, XMM10
730EMIT_INSTR_PLUS_ICEBP vpunpcklbw, XMM8, XMM9, FSxBX
731 %endif
732
733EMIT_INSTR_PLUS_ICEBP vpunpcklbw, YMM1, YMM2, YMM3
734EMIT_INSTR_PLUS_ICEBP vpunpcklbw, YMM1, YMM2, FSxBX
735 %if TMPL_BITS == 64
736EMIT_INSTR_PLUS_ICEBP vpunpcklbw, YMM8, YMM9, YMM10
737EMIT_INSTR_PLUS_ICEBP vpunpcklbw, YMM8, YMM9, FSxBX
738 %endif
739
740;
741; [V]PUNPCKLWD
742;
743EMIT_INSTR_PLUS_ICEBP punpcklwd, MM1, MM2
744EMIT_INSTR_PLUS_ICEBP punpcklwd, MM1, FSxBX
745
746EMIT_INSTR_PLUS_ICEBP punpcklwd, XMM1, XMM2
747EMIT_INSTR_PLUS_ICEBP punpcklwd, XMM1, FSxBX
748 %if TMPL_BITS == 64
749EMIT_INSTR_PLUS_ICEBP punpcklwd, XMM8, XMM9
750EMIT_INSTR_PLUS_ICEBP punpcklwd, XMM8, FSxBX
751 %endif
752
753EMIT_INSTR_PLUS_ICEBP vpunpcklwd, XMM1, XMM2, XMM3
754EMIT_INSTR_PLUS_ICEBP vpunpcklwd, XMM1, XMM2, FSxBX
755 %if TMPL_BITS == 64
756EMIT_INSTR_PLUS_ICEBP vpunpcklwd, XMM8, XMM9, XMM10
757EMIT_INSTR_PLUS_ICEBP vpunpcklwd, XMM8, XMM9, FSxBX
758 %endif
759
760EMIT_INSTR_PLUS_ICEBP vpunpcklwd, YMM1, YMM2, YMM3
761EMIT_INSTR_PLUS_ICEBP vpunpcklwd, YMM1, YMM2, FSxBX
762 %if TMPL_BITS == 64
763EMIT_INSTR_PLUS_ICEBP vpunpcklwd, YMM8, YMM9, YMM10
764EMIT_INSTR_PLUS_ICEBP vpunpcklwd, YMM8, YMM9, FSxBX
765 %endif
766
767;
768; [V]PUNPCKLDQ
769;
770EMIT_INSTR_PLUS_ICEBP punpckldq, MM1, MM2
771EMIT_INSTR_PLUS_ICEBP punpckldq, MM1, FSxBX
772
773EMIT_INSTR_PLUS_ICEBP punpckldq, XMM1, XMM2
774EMIT_INSTR_PLUS_ICEBP punpckldq, XMM1, FSxBX
775 %if TMPL_BITS == 64
776EMIT_INSTR_PLUS_ICEBP punpckldq, XMM8, XMM9
777EMIT_INSTR_PLUS_ICEBP punpckldq, XMM8, FSxBX
778 %endif
779
780EMIT_INSTR_PLUS_ICEBP vpunpckldq, XMM1, XMM2, XMM3
781EMIT_INSTR_PLUS_ICEBP vpunpckldq, XMM1, XMM2, FSxBX
782 %if TMPL_BITS == 64
783EMIT_INSTR_PLUS_ICEBP vpunpckldq, XMM8, XMM9, XMM10
784EMIT_INSTR_PLUS_ICEBP vpunpckldq, XMM8, XMM9, FSxBX
785 %endif
786
787EMIT_INSTR_PLUS_ICEBP vpunpckldq, YMM1, YMM2, YMM3
788EMIT_INSTR_PLUS_ICEBP vpunpckldq, YMM1, YMM2, FSxBX
789 %if TMPL_BITS == 64
790EMIT_INSTR_PLUS_ICEBP vpunpckldq, YMM8, YMM9, YMM10
791EMIT_INSTR_PLUS_ICEBP vpunpckldq, YMM8, YMM9, FSxBX
792 %endif
793
794;
795; [V]PUNPCKLQDQ (no MMX)
796;
797EMIT_INSTR_PLUS_ICEBP punpcklqdq, XMM1, XMM2
798EMIT_INSTR_PLUS_ICEBP punpcklqdq, XMM1, FSxBX
799 %if TMPL_BITS == 64
800EMIT_INSTR_PLUS_ICEBP punpcklqdq, XMM8, XMM9
801EMIT_INSTR_PLUS_ICEBP punpcklqdq, XMM8, FSxBX
802 %endif
803
804EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, XMM1, XMM2, XMM3
805EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, XMM1, XMM2, FSxBX
806 %if TMPL_BITS == 64
807EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, XMM8, XMM9, XMM10
808EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, XMM8, XMM9, FSxBX
809 %endif
810
811EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, YMM1, YMM2, YMM3
812EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, YMM1, YMM2, FSxBX
813 %if TMPL_BITS == 64
814EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, YMM8, YMM9, YMM10
815EMIT_INSTR_PLUS_ICEBP vpunpcklqdq, YMM8, YMM9, FSxBX
816 %endif
817
818;
819; [V]PACKSSWB
820;
821EMIT_INSTR_PLUS_ICEBP packsswb, MM1, MM2
822EMIT_INSTR_PLUS_ICEBP packsswb, MM1, FSxBX
823
824EMIT_INSTR_PLUS_ICEBP packsswb, XMM1, XMM2
825EMIT_INSTR_PLUS_ICEBP packsswb, XMM1, FSxBX
826 %if TMPL_BITS == 64
827EMIT_INSTR_PLUS_ICEBP packsswb, XMM8, XMM9
828EMIT_INSTR_PLUS_ICEBP packsswb, XMM8, FSxBX
829 %endif
830
831EMIT_INSTR_PLUS_ICEBP vpacksswb, XMM1, XMM2, XMM3
832EMIT_INSTR_PLUS_ICEBP vpacksswb, XMM1, XMM2, FSxBX
833 %if TMPL_BITS == 64
834EMIT_INSTR_PLUS_ICEBP vpacksswb, XMM8, XMM9, XMM10
835EMIT_INSTR_PLUS_ICEBP vpacksswb, XMM8, XMM9, FSxBX
836 %endif
837
838EMIT_INSTR_PLUS_ICEBP vpacksswb, YMM1, YMM2, YMM3
839EMIT_INSTR_PLUS_ICEBP vpacksswb, YMM1, YMM2, FSxBX
840 %if TMPL_BITS == 64
841EMIT_INSTR_PLUS_ICEBP vpacksswb, YMM8, YMM9, YMM10
842EMIT_INSTR_PLUS_ICEBP vpacksswb, YMM8, YMM9, FSxBX
843 %endif
844
845;
846; [V]PACKSSWD
847;
848EMIT_INSTR_PLUS_ICEBP packssdw, MM1, MM2
849EMIT_INSTR_PLUS_ICEBP packssdw, MM1, FSxBX
850
851EMIT_INSTR_PLUS_ICEBP packssdw, XMM1, XMM2
852EMIT_INSTR_PLUS_ICEBP packssdw, XMM1, FSxBX
853 %if TMPL_BITS == 64
854EMIT_INSTR_PLUS_ICEBP packssdw, XMM8, XMM9
855EMIT_INSTR_PLUS_ICEBP packssdw, XMM8, FSxBX
856 %endif
857
858EMIT_INSTR_PLUS_ICEBP vpackssdw, XMM1, XMM2, XMM3
859EMIT_INSTR_PLUS_ICEBP vpackssdw, XMM1, XMM2, FSxBX
860 %if TMPL_BITS == 64
861EMIT_INSTR_PLUS_ICEBP vpackssdw, XMM8, XMM9, XMM10
862EMIT_INSTR_PLUS_ICEBP vpackssdw, XMM8, XMM9, FSxBX
863 %endif
864
865EMIT_INSTR_PLUS_ICEBP vpackssdw, YMM1, YMM2, YMM3
866EMIT_INSTR_PLUS_ICEBP vpackssdw, YMM1, YMM2, FSxBX
867 %if TMPL_BITS == 64
868EMIT_INSTR_PLUS_ICEBP vpackssdw, YMM8, YMM9, YMM10
869EMIT_INSTR_PLUS_ICEBP vpackssdw, YMM8, YMM9, FSxBX
870 %endif
871
872;
873; [V]PACKUSWB
874;
875EMIT_INSTR_PLUS_ICEBP packuswb, MM1, MM2
876EMIT_INSTR_PLUS_ICEBP packuswb, MM1, FSxBX
877
878EMIT_INSTR_PLUS_ICEBP packuswb, XMM1, XMM2
879EMIT_INSTR_PLUS_ICEBP packuswb, XMM1, FSxBX
880 %if TMPL_BITS == 64
881EMIT_INSTR_PLUS_ICEBP packuswb, XMM8, XMM9
882EMIT_INSTR_PLUS_ICEBP packuswb, XMM8, FSxBX
883 %endif
884
885EMIT_INSTR_PLUS_ICEBP vpackuswb, XMM1, XMM2, XMM3
886EMIT_INSTR_PLUS_ICEBP vpackuswb, XMM1, XMM2, FSxBX
887 %if TMPL_BITS == 64
888EMIT_INSTR_PLUS_ICEBP vpackuswb, XMM8, XMM9, XMM10
889EMIT_INSTR_PLUS_ICEBP vpackuswb, XMM8, XMM9, FSxBX
890 %endif
891
892EMIT_INSTR_PLUS_ICEBP vpackuswb, YMM1, YMM2, YMM3
893EMIT_INSTR_PLUS_ICEBP vpackuswb, YMM1, YMM2, FSxBX
894 %if TMPL_BITS == 64
895EMIT_INSTR_PLUS_ICEBP vpackuswb, YMM8, YMM9, YMM10
896EMIT_INSTR_PLUS_ICEBP vpackuswb, YMM8, YMM9, FSxBX
897 %endif
898
899;
900; [V]PACKUSWD (no MMX)
901;
902EMIT_INSTR_PLUS_ICEBP packusdw, XMM1, XMM2
903EMIT_INSTR_PLUS_ICEBP packusdw, XMM1, FSxBX
904 %if TMPL_BITS == 64
905EMIT_INSTR_PLUS_ICEBP packusdw, XMM8, XMM9
906EMIT_INSTR_PLUS_ICEBP packusdw, XMM8, FSxBX
907 %endif
908
909EMIT_INSTR_PLUS_ICEBP vpackusdw, XMM1, XMM2, XMM3
910EMIT_INSTR_PLUS_ICEBP vpackusdw, XMM1, XMM2, FSxBX
911 %if TMPL_BITS == 64
912EMIT_INSTR_PLUS_ICEBP vpackusdw, XMM8, XMM9, XMM10
913EMIT_INSTR_PLUS_ICEBP vpackusdw, XMM8, XMM9, FSxBX
914 %endif
915
916EMIT_INSTR_PLUS_ICEBP vpackusdw, YMM1, YMM2, YMM3
917EMIT_INSTR_PLUS_ICEBP vpackusdw, YMM1, YMM2, FSxBX
918 %if TMPL_BITS == 64
919EMIT_INSTR_PLUS_ICEBP vpackusdw, YMM8, YMM9, YMM10
920EMIT_INSTR_PLUS_ICEBP vpackusdw, YMM8, YMM9, FSxBX
921 %endif
922
923;
924; [V]MOVNTDQA
925;
926EMIT_INSTR_PLUS_ICEBP movntdqa, XMM1, FSxBX
927EMIT_INSTR_PLUS_ICEBP vmovntdqa, XMM1, FSxBX
928EMIT_INSTR_PLUS_ICEBP vmovntdqa, YMM1, FSxBX
929 %if TMPL_BITS == 64
930EMIT_INSTR_PLUS_ICEBP movntdqa, XMM10, FSxBX
931EMIT_INSTR_PLUS_ICEBP vmovntdqa, XMM11, FSxBX
932EMIT_INSTR_PLUS_ICEBP vmovntdqa, YMM12, FSxBX
933 %endif
934
935;
936; [V]MOVUPS - not testing the 2nd register variant.
937;
938EMIT_INSTR_PLUS_ICEBP movups, XMM1, XMM2
939EMIT_INSTR_PLUS_ICEBP movups, XMM1, FSxBX
940EMIT_INSTR_PLUS_ICEBP movups, FSxBX, XMM1
941EMIT_INSTR_PLUS_ICEBP vmovups, XMM1, XMM2
942EMIT_INSTR_PLUS_ICEBP vmovups, XMM1, FSxBX
943EMIT_INSTR_PLUS_ICEBP vmovups, FSxBX, XMM1
944EMIT_INSTR_PLUS_ICEBP vmovups, YMM1, YMM2
945EMIT_INSTR_PLUS_ICEBP vmovups, YMM1, FSxBX
946EMIT_INSTR_PLUS_ICEBP vmovups, FSxBX, YMM1
947 %if TMPL_BITS == 64
948EMIT_INSTR_PLUS_ICEBP movups, XMM8, XMM12
949EMIT_INSTR_PLUS_ICEBP movups, XMM10, FSxBX
950EMIT_INSTR_PLUS_ICEBP movups, FSxBX, XMM10
951EMIT_INSTR_PLUS_ICEBP vmovups, XMM7, XMM14
952EMIT_INSTR_PLUS_ICEBP vmovups, XMM11, FSxBX
953EMIT_INSTR_PLUS_ICEBP vmovups, FSxBX, XMM11
954EMIT_INSTR_PLUS_ICEBP vmovups, YMM12, YMM8
955EMIT_INSTR_PLUS_ICEBP vmovups, YMM12, FSxBX
956EMIT_INSTR_PLUS_ICEBP vmovups, FSxBX, YMM12
957 %endif
958
959;
960; [V]MOVUPD - not testing the 2nd register variant.
961;
962EMIT_INSTR_PLUS_ICEBP movupd, XMM1, XMM2
963EMIT_INSTR_PLUS_ICEBP movupd, XMM1, FSxBX
964EMIT_INSTR_PLUS_ICEBP movupd, FSxBX, XMM1
965EMIT_INSTR_PLUS_ICEBP vmovupd, XMM1, XMM2
966EMIT_INSTR_PLUS_ICEBP vmovupd, XMM1, FSxBX
967EMIT_INSTR_PLUS_ICEBP vmovupd, FSxBX, XMM1
968EMIT_INSTR_PLUS_ICEBP vmovupd, YMM1, YMM2
969EMIT_INSTR_PLUS_ICEBP vmovupd, YMM1, FSxBX
970EMIT_INSTR_PLUS_ICEBP vmovupd, FSxBX, YMM1
971 %if TMPL_BITS == 64
972EMIT_INSTR_PLUS_ICEBP movupd, XMM8, XMM12
973EMIT_INSTR_PLUS_ICEBP movupd, XMM10, FSxBX
974EMIT_INSTR_PLUS_ICEBP movupd, FSxBX, XMM10
975EMIT_INSTR_PLUS_ICEBP vmovupd, XMM7, XMM14
976EMIT_INSTR_PLUS_ICEBP vmovupd, XMM11, FSxBX
977EMIT_INSTR_PLUS_ICEBP vmovupd, FSxBX, XMM11
978EMIT_INSTR_PLUS_ICEBP vmovupd, YMM12, YMM8
979EMIT_INSTR_PLUS_ICEBP vmovupd, YMM12, FSxBX
980EMIT_INSTR_PLUS_ICEBP vmovupd, FSxBX, YMM12
981 %endif
982
983;
984; [V]MOVSS - not testing the 2nd register variant.
985;
986EMIT_INSTR_PLUS_ICEBP movss, XMM1, XMM2
987EMIT_INSTR_PLUS_ICEBP movss, XMM1, FSxBX
988EMIT_INSTR_PLUS_ICEBP movss, FSxBX, XMM1
989EMIT_INSTR_PLUS_ICEBP vmovss, XMM1, XMM2
990EMIT_INSTR_PLUS_ICEBP vmovss, XMM1, FSxBX
991EMIT_INSTR_PLUS_ICEBP vmovss, FSxBX, XMM1
992 %if TMPL_BITS == 64
993EMIT_INSTR_PLUS_ICEBP movss, XMM11, XMM8
994EMIT_INSTR_PLUS_ICEBP movss, XMM8, FSxBX
995EMIT_INSTR_PLUS_ICEBP movss, FSxBX, XMM11
996EMIT_INSTR_PLUS_ICEBP vmovss, XMM9, XMM10
997EMIT_INSTR_PLUS_ICEBP vmovss, XMM10, FSxBX
998EMIT_INSTR_PLUS_ICEBP vmovss, FSxBX, XMM9
999 %endif
1000
1001;
1002; [V]MOVSD - not testing the 2nd register variant.
1003;
1004EMIT_INSTR_PLUS_ICEBP movsd, XMM1, XMM2
1005EMIT_INSTR_PLUS_ICEBP movsd, XMM1, FSxBX
1006EMIT_INSTR_PLUS_ICEBP movsd, FSxBX, XMM1
1007EMIT_INSTR_PLUS_ICEBP vmovsd, XMM1, XMM2
1008EMIT_INSTR_PLUS_ICEBP vmovsd, XMM1, FSxBX
1009EMIT_INSTR_PLUS_ICEBP vmovsd, FSxBX, XMM1
1010 %if TMPL_BITS == 64
1011EMIT_INSTR_PLUS_ICEBP movsd, XMM11, XMM8
1012EMIT_INSTR_PLUS_ICEBP movsd, XMM8, FSxBX
1013EMIT_INSTR_PLUS_ICEBP movsd, FSxBX, XMM11
1014EMIT_INSTR_PLUS_ICEBP vmovsd, XMM9, XMM10
1015EMIT_INSTR_PLUS_ICEBP vmovsd, XMM10, FSxBX
1016EMIT_INSTR_PLUS_ICEBP vmovsd, FSxBX, XMM9
1017 %endif
1018
1019;
1020; [V]MOVLPS - not testing the 2nd register variant.
1021;
1022EMIT_INSTR_PLUS_ICEBP movlps, XMM1, FSxBX
1023EMIT_INSTR_PLUS_ICEBP movlps, FSxBX, XMM1
1024EMIT_INSTR_PLUS_ICEBP vmovlps, XMM1, XMM2, FSxBX
1025EMIT_INSTR_PLUS_ICEBP vmovlps, FSxBX, XMM1
1026 %if TMPL_BITS == 64
1027EMIT_INSTR_PLUS_ICEBP movlps, XMM8, FSxBX
1028EMIT_INSTR_PLUS_ICEBP movlps, FSxBX, XMM11
1029EMIT_INSTR_PLUS_ICEBP vmovlps, XMM10, XMM14, FSxBX
1030EMIT_INSTR_PLUS_ICEBP vmovlps, FSxBX, XMM9
1031 %endif
1032
1033
1034%endif ; BS3_INSTANTIATING_CMN
1035
1036%include "bs3kit-template-footer.mac" ; reset environment
1037
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