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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32@ 95532

Last change on this file since 95532 was 95532, checked in by vboxsync, 2 years ago

ValKit/bs3-cpu-instr-3: Simple [v]movlps tests. bugref:9898
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1/* $Id: bs3-cpu-instr-3.c32 95532 2022-07-06 18:10:43Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-instr-3 - MMX, SSE and AVX instructions, C code template.
4 */
5
6/*
7 * Copyright (C) 2007-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28/*********************************************************************************************************************************
29* Header Files *
30*********************************************************************************************************************************/
31#include <bs3kit.h>
32
33#include <iprt/asm.h>
34#include <iprt/asm-amd64-x86.h>
35
36
37/*********************************************************************************************************************************
38* Defined Constants And Macros *
39*********************************************************************************************************************************/
40#define BS3_FNBS3FAR_PROTOTYPES_CMN(a_BaseNm) \
41 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c16); \
42 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c32); \
43 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c64)
44
45
46/** Converts an execution mode (BS3_MODE_XXX) into an index into an array
47 * initialized by BS3CPUINSTR3_TEST1_MODES_INIT,
48 * BS3CPUINSTR3_TEST2_MODES_INIT, BS3CPUINSTR3_TEST3_MODES_INIT, ... . */
49#define BS3CPUINSTR3_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2)
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55/** Instruction set type and operand width. */
56typedef enum
57{
58 T_INVALID,
59 T_MMX,
60 T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */
61 T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */
62 T_AXMMX,
63 T_AXMMX_OR_SSE,
64 T_SSE,
65 T_128BITS = T_SSE,
66 T_SSE2,
67 T_SSE3,
68 T_SSSE3,
69 T_SSE4_1,
70 T_SSE4_2,
71 T_SSE4A,
72 T_AVX_128,
73 T_AVX2_128,
74 T_AVX_256,
75 T_256BITS = T_AVX_256,
76 T_AVX2_256,
77 T_MAX
78} INPUT_TYPE_T;
79
80/** Memory or register rm variant. */
81enum {
82 RM_REG = 0,
83 RM_MEM,
84 RM_MEM32, /**< Memory operand is 32 bits. Hack for movss and similar. */
85 RM_MEM64 /**< Memory operand is 64 bits. Hack for movss and similar. */
86};
87
88/**
89 * Execution environment configuration.
90 */
91typedef struct BS3CPUINSTR3_CONFIG_T
92{
93 uint16_t fCr0Mp : 1;
94 uint16_t fCr0Em : 1;
95 uint16_t fCr0Ts : 1;
96 uint16_t fCr4OsFxSR : 1;
97 uint16_t fCr4OsXSave : 1;
98 uint16_t fXcr0Sse : 1;
99 uint16_t fXcr0Avx : 1;
100 /** x87 exception pending (IE + something unmasked). */
101 uint16_t fX87XcptPending : 1;
102 /** Aligned memory operands. If zero, they will be misaligned and tests w/o memory ops skipped. */
103 uint16_t fAligned : 1;
104 uint16_t fAlignCheck : 1;
105 uint16_t fMxCsrMM : 1; /**< AMD only */
106 uint8_t bXcptMmx;
107 uint8_t bXcptSse;
108 uint8_t bXcptAvx;
109} BS3CPUINSTR3_CONFIG_T;
110/** Pointer to an execution environment configuration. */
111typedef BS3CPUINSTR3_CONFIG_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_T;
112
113/** State saved by bs3CpuInstr3ConfigReconfigure. */
114typedef struct BS3CPUINSTR3_CONFIG_SAVED_T
115{
116 uint32_t uCr0;
117 uint32_t uCr4;
118 uint32_t uEfl;
119 uint16_t uFcw;
120 uint16_t uFsw;
121 uint32_t uMxCsr;
122} BS3CPUINSTR3_CONFIG_SAVED_T;
123typedef BS3CPUINSTR3_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTR3_CONFIG_SAVED_T;
124typedef BS3CPUINSTR3_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_SAVED_T;
125
126
127/*********************************************************************************************************************************
128* Global Variables *
129*********************************************************************************************************************************/
130static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false };
131static bool g_fAmdMisalignedSse = false;
132
133/** Size of g_pbBuf - at least three pages. */
134static uint32_t g_cbBuf;
135/** Buffer of g_cbBuf size. */
136static uint8_t BS3_FAR *g_pbBuf;
137
138/** Exception type \#1 test configurations, 16 & 32 bytes strictly aligned. */
139static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig1[] =
140{
141/*
142 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
143 * +AVX +AMD/SSE
144 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
145 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
146 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
147 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
148 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
149 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
150 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
151 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
152 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
153 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
154 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
155 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
156 /* Memory misalignment and alignment checks: */
157 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_GP }, /* #10 */
158 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_GP }, /* #11 */
159 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
160 /* AMD only: */
161 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
162 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
163};
164
165/** Exception type \#4 test configurations, 16 & 32 byte not strictly aligned. */
166static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4[] =
167{
168/*
169 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
170 * +AVX +AMD/SSE
171 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
172 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
173 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
174 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
175 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
176 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
177 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
178 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
179 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
180 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
181 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
182 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
183 /* Memory misalignment and alignment checks: */
184 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
185 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_AC }, /* #11 */
186 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
187 /* AMD only: */
188 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */
189 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */
190};
191
192/** Exception type \#4 test configurations, for the SSE version of movups. */
193static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4Unaligned[] =
194{
195/*
196 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
197 * +AVX +AMD/SSE
198 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
199 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
200 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
201 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
202 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
203 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
204 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
205 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
206 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
207 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
208 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
209 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
210 /* Memory misalignment and alignment checks: */
211 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */
212 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_DB, X86_XCPT_AC }, /* #11 */
213 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
214 /* AMD only: */
215 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */
216 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */
217};
218
219/** Exception type \#5 test configurations, less than 16 byte operands. */
220static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig5[] =
221{
222/*
223 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
224 * +AVX +AMD/SSE
225 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
226 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
227 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
228 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
229 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
230 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
231 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
232 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
233 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
234 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
235 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
236 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
237 /* Memory misalignment and alignment checks: */
238 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */
239 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */
240 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
241 /* AMD only: */
242 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */
243 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */
244};
245
246
247
248/**
249 * Reconfigures the execution environment according to @a pConfig.
250 *
251 * Call bs3CpuInstr3ConfigRestore to undo the changes.
252 *
253 * @returns true on success, false if the configuration cannot be applied. In
254 * the latter case, no context changes are made.
255 * @param pSavedCfg Where to save state we modify.
256 * @param pCtx The register context to modify.
257 * @param pExtCtx The extended register context to modify.
258 * @param pConfig The configuration to apply.
259 * @param bMode The target mode.
260 */
261static bool bs3CpuInstr3ConfigReconfigure(PBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx,
262 PCBS3CPUINSTR3_CONFIG_T pConfig, uint8_t bMode)
263{
264 /*
265 * Save context bits we may change here
266 */
267 pSavedCfg->uCr0 = pCtx->cr0.u32;
268 pSavedCfg->uCr4 = pCtx->cr4.u32;
269 pSavedCfg->uEfl = pCtx->rflags.u32;
270 pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx);
271 pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx);
272 pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx);
273
274 /*
275 * Can we make these changes?
276 */
277 if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse)
278 return false;
279
280 /* Currently we skip pending x87 exceptions in real mode as they cannot be
281 caught, given that we preserve the bios int10h. */
282 if (pConfig->fX87XcptPending && BS3_MODE_IS_RM_OR_V86(bMode))
283 return false;
284
285 /*
286 * Modify the test context.
287 */
288 if (pConfig->fCr0Mp)
289 pCtx->cr0.u32 |= X86_CR0_MP;
290 else
291 pCtx->cr0.u32 &= ~X86_CR0_MP;
292 if (pConfig->fCr0Em)
293 pCtx->cr0.u32 |= X86_CR0_EM;
294 else
295 pCtx->cr0.u32 &= ~X86_CR0_EM;
296 if (pConfig->fCr0Ts)
297 pCtx->cr0.u32 |= X86_CR0_TS;
298 else
299 pCtx->cr0.u32 &= ~X86_CR0_TS;
300
301 if (pConfig->fCr4OsFxSR)
302 pCtx->cr4.u32 |= X86_CR4_OSFXSR;
303 else
304 pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
305 /** @todo X86_CR4_OSXMMEEXCPT? */
306 if (pConfig->fCr4OsXSave)
307 pCtx->cr4.u32 |= X86_CR4_OSXSAVE;
308 else
309 pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE;
310
311 if (pConfig->fXcr0Sse)
312 pExtCtx->fXcr0Saved |= XSAVE_C_SSE;
313 else
314 pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE;
315 if (pConfig->fXcr0Avx)
316 pExtCtx->fXcr0Saved |= XSAVE_C_YMM;
317 else
318 pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM;
319
320 if (pConfig->fAlignCheck)
321 {
322 pCtx->rflags.u32 |= X86_EFL_AC;
323 pCtx->cr0.u32 |= X86_CR0_AM;
324 }
325 else
326 {
327 pCtx->rflags.u32 &= ~X86_EFL_AC;
328 pCtx->cr0.u32 &= ~X86_CR0_AM;
329 }
330
331 if (!pConfig->fX87XcptPending)
332 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B));
333 else
334 {
335 Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw & ~X86_FCW_ZM);
336 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw | X86_FSW_ZE | X86_FSW_ES | X86_FSW_B);
337 pCtx->cr0.u32 |= X86_CR0_NE;
338 }
339
340 if (pConfig->fMxCsrMM)
341 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM);
342 else
343 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM);
344 return true;
345}
346
347
348/**
349 * Undoes changes made by bs3CpuInstr3ConfigReconfigure.
350 */
351static void bs3CpuInstr3ConfigRestore(PCBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx)
352{
353 pCtx->cr0.u32 = pSavedCfg->uCr0;
354 pCtx->cr4.u32 = pSavedCfg->uCr4;
355 pCtx->rflags.u32 = pSavedCfg->uEfl;
356 pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal;
357 Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw);
358 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw);
359 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr);
360}
361
362
363/**
364 * Allocates two extended CPU contexts and initializes the first one
365 * with random data.
366 * @returns First extended context, initialized with randomish data. NULL on
367 * failure (complained).
368 * @param ppExtCtx2 Where to return the 2nd context.
369 */
370static PBS3EXTCTX bs3CpuInstr3AllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2)
371{
372 /* Allocate extended context structures. */
373 uint64_t fFlags;
374 uint16_t cb = Bs3ExtCtxGetSize(&fFlags);
375 PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2);
376 PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb);
377 if (pExtCtx1)
378 {
379 Bs3ExtCtxInit(pExtCtx1, cb, fFlags);
380 /** @todo populate with semi-random stuff. */
381
382 Bs3ExtCtxInit(pExtCtx2, cb, fFlags);
383 *ppExtCtx2 = pExtCtx2;
384 return pExtCtx1;
385 }
386 Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2);
387 *ppExtCtx2 = NULL;
388 return NULL;
389}
390
391static void bs3CpuInstr3FreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
392{
393 RT_NOREF_PV(pExtCtx2);
394 Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2);
395}
396
397/**
398 * Sets up SSE and maybe AVX.
399 */
400static void bs3CpuInstr3SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx)
401{
402 /* CR0: */
403 uint32_t cr0 = Bs3RegGetCr0();
404 cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
405 cr0 |= X86_CR0_NE;
406 Bs3RegSetCr0(cr0);
407
408 /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */
409 pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
410 pCtx->cr0.u32 |= X86_CR0_NE;
411
412 /* CR4: */
413 if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
414 {
415 uint32_t cr4 = Bs3RegGetCr4();
416 if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
417 {
418 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE;
419 Bs3RegSetCr4(cr4);
420 Bs3RegSetXcr0(pExtCtx->fXcr0Nominal);
421 }
422 else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
423 {
424 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT;
425 Bs3RegSetCr4(cr4);
426 }
427 pCtx->cr4.u32 = cr4;
428 }
429}
430
431
432
433/**
434 * Configures the buffer with electrict fences in paged modes.
435 *
436 * @returns Adjusted buffer pointer.
437 * @param pbBuf The buffer pointer.
438 * @param pcbBuf Pointer to the buffer size (input & output).
439 * @param bMode The testing target mode.
440 */
441DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstr3BufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode)
442{
443 if (BS3_MODE_IS_PAGED(bMode))
444 {
445 uint32_t cbBuf = *pcbBuf;
446 Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P);
447 Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P);
448 pbBuf += X86_PAGE_SIZE;
449 cbBuf -= X86_PAGE_SIZE * 2;
450 *pcbBuf = cbBuf;
451 }
452 return pbBuf;
453}
454
455
456/**
457 * Undoes what bs3CpuInstr3BufSetup did.
458 *
459 * @param pbBuf The buffer pointer.
460 * @param cbBuf The buffer size.
461 * @param bMode The testing target mode.
462 */
463DECLINLINE(void) bs3CpuInstr3BufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode)
464{
465 if (BS3_MODE_IS_PAGED(bMode))
466 {
467 Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0);
468 Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0);
469 }
470}
471
472
473/**
474 * Gets a buffer of a @a cbMemOp sized operand according to the given
475 * configuration and alignment restrictions.
476 *
477 * @returns Pointer to the buffer.
478 * @param pbBuf The buffer pointer.
479 * @param cbBuf The buffer size.
480 * @param cbMemOp The operand size.
481 * @param cbAlign The operand alignment restriction.
482 * @param pConfig The configuration.
483 */
484DECLINLINE(PRTUINT256U) bs3CpuInstr3BufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign,
485 PCBS3CPUINSTR3_CONFIG_T pConfig)
486{
487 if (pConfig->fAligned)
488 {
489 if (!pConfig->fAlignCheck)
490 return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp];
491 return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - cbAlign];
492 }
493 return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - 1];
494}
495
496
497/**
498 * Determins the size of memory operands.
499 */
500DECLINLINE(uint8_t) bs3CpuInstr3MemOpSize(uint8_t cbOperand, uint8_t enmRm)
501{
502 if (enmRm <= RM_MEM)
503 return cbOperand;
504 if (enmRm == RM_MEM32)
505 return sizeof(uint32_t);
506 if (enmRm == RM_MEM64)
507 return sizeof(uint64_t);
508 BS3_ASSERT(0);
509 return cbOperand;
510}
511
512
513/*
514 * Test type #1.
515 */
516
517typedef struct BS3CPUINSTR3_TEST1_VALUES_T
518{
519 RTUINT256U uSrc2;
520 RTUINT256U uSrc1; /**< uDstIn for MMX & SSE */
521 RTUINT256U uDstOut;
522} BS3CPUINSTR3_TEST1_VALUES_T;
523
524typedef struct BS3CPUINSTR3_TEST1_T
525{
526 FPFNBS3FAR pfnWorker;
527 uint8_t bAvxMisalignXcpt;
528 uint8_t enmRm;
529 uint8_t enmType;
530 uint8_t iRegDst;
531 uint8_t iRegSrc1;
532 uint8_t iRegSrc2;
533 uint8_t cValues;
534 BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues;
535} BS3CPUINSTR3_TEST1_T;
536
537typedef struct BS3CPUINSTR3_TEST1_MODE_T
538{
539 BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests;
540 unsigned cTests;
541} BS3CPUINSTR3_TEST1_MODE_T;
542
543/** Initializer for a BS3CPUINSTR3_TEST1_MODE_T array (three entries). */
544#define BS3CPUINSTR3_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
545 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
546
547
548/**
549 * Test type #1 worker.
550 */
551static uint8_t bs3CpuInstr3_WorkerTestType1(uint8_t bMode, BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests, unsigned cTests,
552 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs)
553{
554 BS3REGCTX Ctx;
555 BS3TRAPFRAME TrapFrame;
556 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
557 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
558 uint8_t BS3_FAR *pbBuf = g_pbBuf;
559 uint32_t cbBuf = g_cbBuf;
560 PBS3EXTCTX pExtCtxOut;
561 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
562 if (!pExtCtx)
563 return 0;
564
565 /* Ensure the structures are allocated before we sample the stack pointer. */
566 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
567 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
568
569 /*
570 * Create test context.
571 */
572 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
573 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
574 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
575 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]);
576
577 /*
578 * Run the tests in all rings since alignment issues may behave
579 * differently in ring-3 compared to ring-0.
580 */
581 for (;;)
582 {
583 unsigned iCfg;
584 for (iCfg = 0; iCfg < cConfigs; iCfg++)
585 {
586 unsigned iTest;
587 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
588 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
589 continue; /* unsupported config */
590
591 /*
592 * Iterate the tests.
593 */
594 for (iTest = 0; iTest < cTests; iTest++)
595 {
596 BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
597 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
598 unsigned const cValues = paTests[iTest].cValues;
599 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
600 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
601 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
602 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
603 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
604 uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm);
605 uint8_t const cbAlign = cbMemOp;
606 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
607 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD
608 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
609 : fSseInstr ? paConfigs[iCfg].bXcptSse
610 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
611 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
612 unsigned iVal;
613
614 /* If testing unaligned memory accesses, skip register-only tests. This allows
615 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
616 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
617 continue;
618
619 /* #AC is only raised in ring-3.: */
620 if (bXcptExpect == X86_XCPT_AC)
621 {
622 if (bRing != 3)
623 bXcptExpect = X86_XCPT_DB;
624 else if (fAvxInstr)
625 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
626 }
627
628 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
629
630 /*
631 * Iterate the test values and do the actual testing.
632 */
633 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
634 {
635 uint16_t cErrors;
636 uint16_t uSavedFtw = 0xff;
637 RTUINT256U uMemOpExpect;
638
639 /*
640 * Set up the context and some expectations.
641 */
642 /* dest */
643 if (paTests[iTest].iRegDst == UINT8_MAX)
644 {
645 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
646 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
647 if (bXcptExpect == X86_XCPT_DB)
648 uMemOpExpect = paValues[iVal].uDstOut;
649 else
650 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
651 }
652 else if (fMmxInstr)
653 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
654
655 /* source #1 (/ destination for MMX and SSE) */
656 if (paTests[iTest].iRegSrc1 == UINT8_MAX)
657 {
658 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
659 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp);
660 if (paTests[iTest].iRegDst == UINT8_MAX)
661 BS3_ASSERT(fSseInstr);
662 else
663 uMemOpExpect = paValues[iVal].uSrc1;
664 }
665 else if (fMmxInstr)
666 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
667 else if (fSseInstr)
668 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0);
669 else
670 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32);
671
672 /* source #2 */
673 if (paTests[iTest].iRegSrc2 == UINT8_MAX)
674 {
675 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
676 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX);
677 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp);
678 uMemOpExpect = paValues[iVal].uSrc2;
679 }
680 else if (fMmxInstr)
681 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
682 else if (fSseInstr)
683 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0);
684 else
685 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32);
686
687 /* Memory pointer. */
688 if (paTests[iTest].enmRm >= RM_MEM)
689 {
690 BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX
691 || paTests[iTest].iRegSrc1 == UINT8_MAX
692 || paTests[iTest].iRegSrc2 == UINT8_MAX);
693 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
694 }
695
696 /*
697 * Execute.
698 */
699 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
700
701 /*
702 * Check the result:
703 */
704 cErrors = Bs3TestSubErrorCount();
705
706 if (fMmxInstr && bXcptExpect == X86_XCPT_DB)
707 {
708 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
709 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */
710 }
711 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX)
712 {
713 if (fMmxInstr)
714 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET);
715 else if (fSseInstr)
716 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0);
717 else
718 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand);
719 }
720 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
721
722 if (TrapFrame.bXcpt != bXcptExpect)
723 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
724
725 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
726 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
727 {
728 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
729 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
730 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
731 }
732 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
733 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
734 pszMode, idTestStep);
735
736 if ( paTests[iTest].enmRm >= RM_MEM
737 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
738 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
739
740 if (cErrors != Bs3TestSubErrorCount())
741 {
742 if (paConfigs[iCfg].fAligned)
743 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
744 bRing, iCfg, iTest, iVal, bXcptExpect);
745 else
746 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
747 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
748 Bs3TestPrintf("\n");
749 }
750
751 if (uSavedFtw != 0xff)
752 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
753 }
754 }
755
756 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
757 }
758
759 /*
760 * Next ring.
761 */
762 bRing++;
763 if (bRing > 3 || bMode == BS3_MODE_RM)
764 break;
765 Bs3RegCtxConvertToRingX(&Ctx, bRing);
766 }
767
768 /*
769 * Cleanup.
770 */
771 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
772 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
773 return 0;
774}
775
776
777/*
778 * PAND, VPAND, ANDPS, VANDPS, ANDPD, VANDPD.
779 */
780BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_MM2_icebp);
781BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_FSxBX_icebp);
782BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_XMM2_icebp);
783BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_FSxBX_icebp);
784BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp);
785BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp);
786BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp);
787BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp);
788
789BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_XMM2_icebp);
790BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_FSxBX_icebp);
791BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp);
792BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp);
793BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp);
794BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp);
795
796BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_XMM2_icebp);
797BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_FSxBX_icebp);
798BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp);
799BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp);
800BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp);
801BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp);
802extern FNBS3FAR bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64;
803
804BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andps_andpd_pand(uint8_t bMode)
805{
806 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
807 {
808 { RTUINT256_INIT_C(0, 0, 0, 0),
809 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
810 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
811 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
812 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
813 /* = */ RTUINT256_INIT_C(0x5555666677770000, 0x1111222233334444, 0x1111222233334444, 0x5555666677770000) },
814 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
815 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
816 /* = */ RTUINT256_INIT_C(0x0c09d02808403294, 0x385406c840621622, 0x8000290816080282, 0x0050c020030090b9) },
817 };
818
819 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
820 {
821 { bs3CpuInstr3_pand_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
822 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
823 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
824 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
825 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
826 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
827 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
828 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
829
830 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
831 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
832 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
833 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
834 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
835 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
836
837 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
838 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
839 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
840 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
841 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
842 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
843 };
844 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
845 {
846 { bs3CpuInstr3_pand_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
847 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
848 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
849 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
850 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
851 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
852 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
853 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
854
855 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
856 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
857 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
858 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
859 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
860 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
861
862 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
863 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
864 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
865 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
866 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
867 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
868 };
869 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
870 {
871 { bs3CpuInstr3_pand_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
872 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
873 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
874 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
875 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
876 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
877 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
878 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
879
880 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
881 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
882 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
883 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
884 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
885 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
886
887 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
888 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
889 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
890 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
891 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
892 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
893 { bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
894 };
895
896 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
897 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
898 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
899 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
900}
901
902
903/*
904 * PANDN, VPANDN, ANDNPS, VANDNPS, ANDNPD, VANDNPD.
905 */
906BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_MM2_icebp);
907BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_FSxBX_icebp);
908BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_XMM2_icebp);
909BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_FSxBX_icebp);
910BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp);
911BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp);
912BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp);
913BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp);
914
915BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_XMM2_icebp);
916BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_FSxBX_icebp);
917BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp);
918BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp);
919BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp);
920BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp);
921
922BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_XMM2_icebp);
923BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp);
924BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp);
925BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp);
926BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp);
927BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp);
928extern FNBS3FAR bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64;
929
930BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andnps_andnpd_pandn(uint8_t bMode)
931{
932 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
933 {
934 { RTUINT256_INIT_C(0, 0, 0, 0),
935 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
936 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
937 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
938 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
939 /* = */ RTUINT256_INIT_C(0x0000000000008888, 0x0000000000000000, 0x0000000000000000, 0x0000000000008888) },
940 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
941 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
942 /* = */ RTUINT256_INIT_C(0x41002002649c4141, 0x06a01100260929c4, 0x342106a040449920, 0x9c0c205390090602) },
943 };
944
945 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
946 {
947 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
948 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
949 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
950 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
951 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
952 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
953 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
954 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
955
956 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
957 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
958 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
959 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
960 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
961 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
962
963 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
964 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
965 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
966 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
967 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
968 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
969 };
970 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
971 {
972 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
973 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
974 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
975 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
976 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
977 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
978 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
979 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
980
981 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
982 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
983 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
984 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
985 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
986 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
987
988 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
989 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
990 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
991 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
992 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
993 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
994 };
995 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
996 {
997 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
998 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
999 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1000 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1001 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1002 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1003 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1004 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1005
1006 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1007 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1008 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1009 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1010 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1011 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1012
1013 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1014 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1015 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1016 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1017 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1018 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1019 { bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
1020 };
1021
1022 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1023 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1024 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1025 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1026}
1027
1028
1029
1030/*
1031 * POR, VPOR, PORPS, VORPS, PORPD, VPORPD.
1032 */
1033BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_MM2_icebp);
1034BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_FSxBX_icebp);
1035BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_XMM2_icebp);
1036BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_FSxBX_icebp);
1037BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp);
1038BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp);
1039BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp);
1040BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp);
1041
1042BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_XMM2_icebp);
1043BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_FSxBX_icebp);
1044BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp);
1045BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp);
1046BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp);
1047BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp);
1048
1049BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_XMM2_icebp);
1050BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_FSxBX_icebp);
1051BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp);
1052BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp);
1053BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp);
1054BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp);
1055extern FNBS3FAR bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64;
1056
1057BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_orps_orpd_por(uint8_t bMode)
1058{
1059 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
1060 {
1061 { RTUINT256_INIT_C(0, 0, 0, 0),
1062 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
1063 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1064 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1065 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1066 /* = */ RTUINT256_INIT_C(0xddddeeeeffff8888, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff8888) },
1067 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1068 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1069 /* = */ RTUINT256_INIT_C(0x5fddfdae6dff73d5, 0xfffc9fec667b7ff7, 0xbc21effbffddfbe3, 0xdfdfedf3b38d9fff) },
1070 };
1071
1072 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1073 {
1074 { bs3CpuInstr3_por_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1075 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1076 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1077 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1078 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1079 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1080 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1081 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1082
1083 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1084 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1085 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1086 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1087 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1088 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1089
1090 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1091 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1092 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1093 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1094 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1095 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1096 };
1097 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1098 {
1099 { bs3CpuInstr3_por_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1100 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1101 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1102 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1103 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1104 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1105 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1106 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1107
1108 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1109 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1110 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1111 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1112 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1113 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1114
1115 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1116 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1117 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1118 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1119 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1120 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1121 };
1122 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1123 {
1124 { bs3CpuInstr3_por_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1125 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1126 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1127 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1128 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1129 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1130 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1131 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1132
1133 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1134 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1135 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1136 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1137 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1138 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1139
1140 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1141 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1142 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1143 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1144 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1145 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1146 { bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
1147 };
1148 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1149 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1150 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1151 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1152}
1153
1154
1155/*
1156 * PXOR, VPXOR, XORPS, VXORPS, XORPD, VXORPD.
1157 */
1158BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_MM2_icebp);
1159BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_FSxBX_icebp);
1160BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_XMM1_XMM2_icebp);
1161BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_XMM1_FSxBX_icebp);
1162BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp);
1163BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp);
1164BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp);
1165BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp);
1166
1167BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorps_XMM1_XMM2_icebp);
1168BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorps_XMM1_FSxBX_icebp);
1169BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp);
1170BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp);
1171BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp);
1172BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp);
1173
1174BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorpd_XMM1_XMM2_icebp);
1175BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp);
1176BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp);
1177BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp);
1178BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp);
1179BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp);
1180extern FNBS3FAR bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64;
1181
1182BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_xorps_xorpd_pxor(uint8_t bMode)
1183{
1184 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
1185 {
1186 { RTUINT256_INIT_C(0, 0, 0, 0),
1187 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
1188 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1189 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1190 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1191 /* = */ RTUINT256_INIT_C(0x8888888888888888, 0x8888888888888888, 0x8888888888888888, 0x8888888888888888) },
1192 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1193 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1194 /* = */ RTUINT256_INIT_C(0x53d42d8665bf4141, 0xc7a89924261969d5, 0x3c21c6f3e9d5f961, 0xdf8f2dd3b08d0f46) },
1195 };
1196
1197 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1198 {
1199 { bs3CpuInstr3_pxor_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1200 { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1201 { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1202 { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1203 { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1204 { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1205 { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1206 { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1207
1208 { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1209 { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1210 { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1211 { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1212 { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1213 { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1214
1215 { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1216 { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1217 { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1218 { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1219 { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1220 { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1221 };
1222 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1223 {
1224 { bs3CpuInstr3_pxor_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1225 { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1226 { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1227 { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1228 { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1229 { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1230 { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1231 { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1232
1233 { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1234 { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1235 { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1236 { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1237 { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1238 { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1239
1240 { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1241 { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1242 { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1243 { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1244 { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1245 { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1246 };
1247 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1248 {
1249 { bs3CpuInstr3_pxor_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1250 { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1251 { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1252 { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1253 { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1254 { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1255 { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1256 { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1257
1258 { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1259 { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1260 { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1261 { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1262 { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1263 { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1264
1265 { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1266 { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1267 { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1268 { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1269 { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1270 { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1271 { bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
1272 };
1273 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1274 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1275 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1276 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1277}
1278
1279
1280
1281/*
1282 * PCMPGTB, VPCMPGTB, PCMPGTW, VPCMPGTW, PCMPGTD, VPCMPGTD, PCMPGTQ, VPCMPGTQ.
1283 */
1284BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp);
1285BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp);
1286BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp);
1287BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp);
1288BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp);
1289BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp);
1290BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp);
1291BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp);
1292
1293BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp);
1294BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp);
1295BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp);
1296BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp);
1297BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp);
1298BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp);
1299BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp);
1300BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp);
1301
1302BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp);
1303BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp);
1304BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp);
1305BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp);
1306BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp);
1307BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp);
1308BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp);
1309BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp);
1310extern FNBS3FAR bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64;
1311
1312BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp);
1313BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp);
1314BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp);
1315BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp);
1316BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp);
1317BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp);
1318extern FNBS3FAR bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64;
1319
1320BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq(uint8_t bMode)
1321{
1322 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1323 {
1324 { RTUINT256_INIT_C(0, 0, 0, 0),
1325 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1326 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1327 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1328 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1329 /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) },
1330 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1331 /* < */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1332 /* = */ RTUINT256_INIT_C(0x0000000000ff0000, 0x00ff00ff00ffffff, 0x000000ff0000ffff, 0xff000000ff00ffff) },
1333 };
1334
1335 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1336 {
1337 { RTUINT256_INIT_C(0, 0, 0, 0),
1338 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1339 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1340 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1341 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1342 /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) },
1343 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1344 /* ^ */ RTUINT256_INIT_C(0x1eddddac77733294, 0xf95c8eec40725633, 0x3333e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st and 3rd value */
1345 /* = */ RTUINT256_INIT_C(0x00000000ffff0000, 0x000000000000ffff, 0xffff00000000ffff, 0xffff0000ffffffff) },
1346 };
1347
1348 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1349 {
1350 { RTUINT256_INIT_C(0, 0, 0, 0),
1351 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1352 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1353 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1354 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1355 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1356 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1357 /* < */ RTUINT256_INIT_C(0x555dddac09633294, 0xf95c8eec77725633, 0x7770e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st, 2nd and 3rd value */
1358 /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0xffffffffffffffff) },
1359 };
1360
1361 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
1362 {
1363 { RTUINT256_INIT_C(0, 0, 0, 0),
1364 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1365 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1366 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1367 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1368 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1369 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1370 /* < */ RTUINT256_INIT_C(0x77ddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st value */
1371 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff) },
1372 };
1373
1374 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1375 {
1376 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1377 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1378 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1379 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1380 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1381 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1382 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1383 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1384
1385 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1386 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1387 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1388 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1389 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1390 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1391 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1392 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1393
1394 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1395 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1396 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1397 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1398 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1399 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1400 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1401 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1402
1403 { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1404 { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1405 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1406 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1407 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1408 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1409 };
1410 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1411 {
1412 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1413 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1414 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1415 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1416 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1417 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1418 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1419 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1420
1421 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1422 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1423 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1424 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1425 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1426 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1427 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1428 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1429
1430 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1431 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1432 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1433 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1434 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1435 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1436 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1437 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1438
1439 { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1440 { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1441 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1442 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1443 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1444 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1445 };
1446 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1447 {
1448 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1449 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1450 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1451 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1452 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1453 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1454 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1455 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1456
1457 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1458 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1459 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1460 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1461 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1462 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1463 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1464 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1465
1466 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1467 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1468 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1469 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1470 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1471 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1472 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1473 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1474 { bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1475
1476 { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1477 { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1478 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1479 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1480 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1481 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1482 { bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1483 };
1484 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1485 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1486 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1487 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1488}
1489
1490
1491/*
1492 * PCMPEQB, VPCMPEQB, PCMPEQW, VPCMPEQW, PCMPEQD, VPCMPEQD, PCMPEQQ, VPCMPEQQ.
1493 */
1494BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp);
1495BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp);
1496BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp);
1497BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp);
1498BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp);
1499BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp);
1500BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp);
1501BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp);
1502
1503BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp);
1504BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp);
1505BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp);
1506BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp);
1507BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp);
1508BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp);
1509BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp);
1510BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp);
1511
1512BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp);
1513BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp);
1514BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp);
1515BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp);
1516BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp);
1517BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp);
1518BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp);
1519BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp);
1520extern FNBS3FAR bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64;
1521
1522BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp);
1523BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp);
1524BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp);
1525BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp);
1526BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp);
1527BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp);
1528extern FNBS3FAR bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64;
1529
1530BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq(uint8_t bMode)
1531{
1532 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1533 {
1534 { RTUINT256_INIT_C(0, 0, 0, 0),
1535 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1536 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1537 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1538 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1539 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1540 { RTUINT256_INIT_C(0x4dddf02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1541 /* ==*/ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf95c17ec667256e6, 0xb400e95bbf999bc3, 0x9cd3cda0230999fd), /* modified all to get some matches */
1542 /* = */ RTUINT256_INIT_C(0x00ff000000ff0000, 0x0000ff00ff0000ff, 0xff0000000000ff00, 0xff00000000ff0000) },
1543 };
1544
1545 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1546 {
1547 { RTUINT256_INIT_C(0, 0, 0, 0),
1548 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1549 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1550 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1551 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1552 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1553 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1554 /* ==*/ RTUINT256_INIT_C(0x1eddf02a6cdc3294, 0x3ef48eec666b5633, 0x88002fa8bf999ba2, 0x9c5ccda0238496bb), /* modified all to get some matches */
1555 /* = */ RTUINT256_INIT_C(0x0000ffffffff0000, 0xffff0000ffff0000, 0x0000ffff0000ffff, 0xffff00000000ffff) },
1556 };
1557
1558 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1559 {
1560 { RTUINT256_INIT_C(0, 0, 0, 0),
1561 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1562 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1563 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1564 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1565 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1566 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1567 /* ==*/ RTUINT256_INIT_C(0x4d09f02a09633294, 0x3ef417c8666b3fe6, 0x8800e95b564c9ba2, 0x9c5ce073238499fd), /* modified all to get some matches */
1568 /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0xffffffffffffffff, 0x00000000ffffffff, 0xffffffff00000000) },
1569 };
1570
1571 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
1572 {
1573 { RTUINT256_INIT_C(0, 0, 0, 0),
1574 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1575 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1576 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1577 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1578 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1579 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1580 /* ==*/ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd), /* modified 2nd and 3rd to get some matches */
1581 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000000) },
1582 };
1583
1584 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1585 {
1586 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1587 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1588 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1589 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1590 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1591 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1592 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1593 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1594
1595 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1596 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1597 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1598 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1599 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1600 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1601 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1602 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1603
1604 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1605 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1606 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1607 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1608 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1609 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1610 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1611 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1612
1613 { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1614 { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1615 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1616 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1617 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1618 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1619 };
1620 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1621 {
1622 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1623 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1624 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1625 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1626 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1627 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1628 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1629 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1630
1631 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1632 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1633 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1634 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1635 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1636 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1637 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1638 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1639
1640 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1641 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1642 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1643 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1644 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1645 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1646 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1647 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1648
1649 { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1650 { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1651 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1652 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1653 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1654 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1655 };
1656 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1657 {
1658 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1659 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1660 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1661 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1662 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1663 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1664 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1665 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1666
1667 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1668 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1669 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1670 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1671 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1672 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1673 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1674 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1675
1676 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1677 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1678 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1679 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1680 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1681 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1682 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1683 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1684 { bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1685
1686 { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1687 { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1688 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1689 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1690 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1691 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1692 { bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1693 };
1694 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1695 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1696 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1697 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1698}
1699
1700
1701/*
1702 * PADDB, VPADDB, PADDW, VPADDW, PADDD, VPADDD, PADDQ, VPADDQ.
1703 */
1704BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_MM1_MM2_icebp);
1705BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_MM1_FSxBX_icebp);
1706BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_XMM1_XMM2_icebp);
1707BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_XMM1_FSxBX_icebp);
1708BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp);
1709BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp);
1710BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp);
1711BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp);
1712
1713BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_MM1_MM2_icebp);
1714BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_MM1_FSxBX_icebp);
1715BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_XMM1_XMM2_icebp);
1716BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_XMM1_FSxBX_icebp);
1717BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp);
1718BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp);
1719BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp);
1720BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp);
1721
1722BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_MM1_MM2_icebp);
1723BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_MM1_FSxBX_icebp);
1724BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_XMM1_XMM2_icebp);
1725BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_XMM1_FSxBX_icebp);
1726BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp);
1727BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp);
1728BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp);
1729BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp);
1730extern FNBS3FAR bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64;
1731
1732BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_MM1_MM2_icebp);
1733BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_MM1_FSxBX_icebp);
1734BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_XMM1_XMM2_icebp);
1735BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_XMM1_FSxBX_icebp);
1736BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp);
1737BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp);
1738BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp);
1739BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp);
1740extern FNBS3FAR bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64;
1741
1742BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_paddb_paddw_paddd_paddq(uint8_t bMode)
1743{
1744 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1745 {
1746 { RTUINT256_INIT_C(0, 0, 0, 0),
1747 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1748 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1749 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1750 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1751 /* = */ RTUINT256_INIT_C(0x3232545476768888, 0xaaaacccceeee1010, 0xaaaacccceeee1010, 0x3232545476768888) },
1752 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1753 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1754 /* = */ RTUINT256_INIT_C(0x6be6cdd6753fa569, 0x3750a5b4a6dd9519, 0x3c21180315e5fd65, 0xdf2fad13b68d2fb8) },
1755 };
1756
1757 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1758 {
1759 { RTUINT256_INIT_C(0, 0, 0, 0),
1760 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1761 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1762 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1763 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1764 /* = */ RTUINT256_INIT_C(0x3332555477768888, 0xaaaacccceeee1110, 0xaaaacccceeee1110, 0x3332555477768888) },
1765 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1766 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1767 /* = */ RTUINT256_INIT_C(0x6be6cdd6763fA669, 0x3850A6B4A6DD9619, 0x3C21190315E5FE65, 0xE02FAE13B68D30B8) },
1768 };
1769
1770 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1771 {
1772 { RTUINT256_INIT_C(0, 0, 0, 0),
1773 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1774 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1775 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1776 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1777 /* = */ RTUINT256_INIT_C(0x3333555477768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555477768888) },
1778 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1779 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1780 /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190315E5FE65, 0xE030AE13B68E30B8) },
1781 };
1782
1783 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
1784 {
1785 { RTUINT256_INIT_C(0, 0, 0, 0),
1786 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1787 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1788 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1789 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1790 /* = */ RTUINT256_INIT_C(0x3333555577768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555577768888) },
1791 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1792 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1793 /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190415E5FE65, 0xE030AE13B68E30B8) },
1794 };
1795
1796 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1797 {
1798 { bs3CpuInstr3_paddb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1799 { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1800 { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1801 { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1802 { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1803 { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1804 { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1805 { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1806
1807 { bs3CpuInstr3_paddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1808 { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1809 { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1810 { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1811 { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1812 { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1813 { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1814 { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1815
1816 { bs3CpuInstr3_paddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1817 { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1818 { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1819 { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1820 { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1821 { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1822 { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1823 { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1824
1825 { bs3CpuInstr3_paddq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1826 { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1827 { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1828 { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1829 { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1830 { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1831 { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1832 { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1833 };
1834 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1835 {
1836 { bs3CpuInstr3_paddb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1837 { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1838 { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1839 { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1840 { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1841 { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1842 { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1843 { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1844
1845 { bs3CpuInstr3_paddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1846 { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1847 { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1848 { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1849 { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1850 { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1851 { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1852 { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1853
1854 { bs3CpuInstr3_paddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1855 { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1856 { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1857 { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1858 { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1859 { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1860 { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1861 { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1862
1863 { bs3CpuInstr3_paddq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1864 { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1865 { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1866 { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1867 { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1868 { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1869 { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1870 { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1871 };
1872 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1873 {
1874 { bs3CpuInstr3_paddb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1875 { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1876 { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1877 { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1878 { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1879 { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1880 { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1881 { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1882
1883 { bs3CpuInstr3_paddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1884 { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1885 { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1886 { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1887 { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1888 { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1889 { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1890 { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1891
1892 { bs3CpuInstr3_paddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1893 { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1894 { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1895 { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1896 { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1897 { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1898 { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1899 { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1900 { bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1901
1902 { bs3CpuInstr3_paddq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1903 { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1904 { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1905 { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1906 { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1907 { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1908 { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1909 { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1910 { bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1911 };
1912 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1913 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1914 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1915 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1916}
1917
1918
1919/*
1920 * PSUBB, VPSUBB, PSUBW, VPSUBW, PSUBD, VPSUBD, PSUBQ, VPSUBQ.
1921 */
1922BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_MM1_MM2_icebp);
1923BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_MM1_FSxBX_icebp);
1924BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_XMM1_XMM2_icebp);
1925BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_XMM1_FSxBX_icebp);
1926BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp);
1927BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp);
1928BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp);
1929BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp);
1930
1931BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_MM1_MM2_icebp);
1932BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_MM1_FSxBX_icebp);
1933BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_XMM1_XMM2_icebp);
1934BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_XMM1_FSxBX_icebp);
1935BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp);
1936BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp);
1937BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp);
1938BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp);
1939
1940BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_MM1_MM2_icebp);
1941BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_MM1_FSxBX_icebp);
1942BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_XMM1_XMM2_icebp);
1943BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_XMM1_FSxBX_icebp);
1944BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp);
1945BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp);
1946BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp);
1947BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp);
1948extern FNBS3FAR bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64;
1949
1950BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_MM1_MM2_icebp);
1951BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_MM1_FSxBX_icebp);
1952BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_XMM1_XMM2_icebp);
1953BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_XMM1_FSxBX_icebp);
1954BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp);
1955BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp);
1956BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp);
1957BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp);
1958extern FNBS3FAR bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64;
1959
1960BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psubb_psubw_psubd_psubq(uint8_t bMode)
1961{
1962 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1963 {
1964 { RTUINT256_INIT_C(0, 0, 0, 0),
1965 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1966 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1967 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1968 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1969 /* = */ RTUINT256_INIT_C(0x8888888888887878, 0x8888888888888888, 0x8888888888888888, 0x8888888888887878) },
1970 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1971 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1972 /* = */ RTUINT256_INIT_C(0xd1d4ed829d87bfbf, 0xbb687724da07174d, 0xd4dfbab3694dc721, 0xa777ed2d907b0342) },
1973 };
1974
1975 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1976 {
1977 { RTUINT256_INIT_C(0, 0, 0, 0),
1978 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1979 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1980 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1981 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1982 /* = */ RTUINT256_INIT_C(0x8888888888887778, 0x8888888888888888, 0x8888888888888888, 0x8888888888887778) },
1983 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1984 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1985 /* = */ RTUINT256_INIT_C(0xd1d4ed829c87bebf, 0xba687724da07164d, 0xd3dfb9b3694dc721, 0xa777ed2d907b0342) },
1986 };
1987
1988 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1989 {
1990 { RTUINT256_INIT_C(0, 0, 0, 0),
1991 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1992 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1993 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1994 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1995 /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) },
1996 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1997 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1998 /* = */ RTUINT256_INIT_C(0xd1d3ed829c86bebf, 0xba687724da07164d, 0xd3dfb9b3694cc721, 0xa776ed2d907b0342) },
1999 };
2000
2001 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
2002 {
2003 { RTUINT256_INIT_C(0, 0, 0, 0),
2004 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
2005 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
2006 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2007 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2008 /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) },
2009 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2010 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2011 /* = */ RTUINT256_INIT_C(0xd1d3ed819c86bebf, 0xba687723da07164d, 0xd3dfb9b3694cc721, 0xa776ed2c907b0342) },
2012 };
2013
2014 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2015 {
2016 { bs3CpuInstr3_psubb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2017 { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2018 { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2019 { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2020 { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2021 { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2022 { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2023 { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2024
2025 { bs3CpuInstr3_psubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2026 { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2027 { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2028 { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2029 { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2030 { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2031 { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2032 { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2033
2034 { bs3CpuInstr3_psubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2035 { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2036 { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2037 { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2038 { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2039 { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2040 { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2041 { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2042
2043 { bs3CpuInstr3_psubq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2044 { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2045 { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2046 { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2047 { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2048 { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2049 { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2050 { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2051 };
2052 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2053 {
2054 { bs3CpuInstr3_psubb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2055 { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2056 { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2057 { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2058 { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2059 { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2060 { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2061 { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2062
2063 { bs3CpuInstr3_psubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2064 { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2065 { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2066 { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2067 { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2068 { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2069 { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2070 { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2071
2072 { bs3CpuInstr3_psubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2073 { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2074 { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2075 { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2076 { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2077 { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2078 { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2079 { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2080
2081 { bs3CpuInstr3_psubq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2082 { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2083 { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2084 { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2085 { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2086 { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2087 { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2088 { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2089 };
2090 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2091 {
2092 { bs3CpuInstr3_psubb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2093 { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2094 { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2095 { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2096 { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2097 { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2098 { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2099 { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2100
2101 { bs3CpuInstr3_psubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2102 { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2103 { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2104 { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2105 { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2106 { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2107 { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2108 { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2109
2110 { bs3CpuInstr3_psubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2111 { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2112 { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2113 { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2114 { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2115 { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2116 { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2117 { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2118 { bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2119
2120 { bs3CpuInstr3_psubq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2121 { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2122 { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2123 { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2124 { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2125 { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2126 { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2127 { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2128 { bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2129 };
2130 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2131 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2132 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2133 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2134}
2135
2136
2137/*
2138 * PSHUFB
2139 */
2140BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_MM1_MM2_icebp);
2141BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_MM1_FSxBX_icebp);
2142BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_XMM1_XMM2_icebp);
2143BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp);
2144extern FNBS3FAR bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64;
2145extern FNBS3FAR bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64;
2146BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp);
2147BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp);
2148extern FNBS3FAR bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64;
2149extern FNBS3FAR bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64;
2150BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp);
2151BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp);
2152extern FNBS3FAR bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64;
2153extern FNBS3FAR bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64;
2154
2155BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufb(uint8_t bMode)
2156{
2157 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2158 {
2159 { /*mask*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2160 /*val*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2161 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2162 { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff),
2163 /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff),
2164 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) },
2165 { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0x7f7f7f7f7f7f7f7f),
2166 /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff),
2167 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff) },
2168 { /*mask*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2169 /*val*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2170 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xeeeedddddddd0000) },
2171 { /*mask*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2172 /*val*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2173 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00a0002300990000) },
2174 };
2175
2176 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2177 {
2178 { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0),
2179 /*val*/ RTUINT256_INIT_C(0, 0, 0, 0),
2180 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2181 { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
2182 /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
2183 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
2184 { /*mask*/ RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f),
2185 /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
2186 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
2187 { /*mask*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2188 /*val*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2189 /* => */ RTUINT256_INIT_C(0xaaaa999999990000, 0xccccbbbbbbbbaaaa, 0x0000ffffffffeeee, 0xeeeedddddddd0000) },
2190 { /*mask*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2191 /*val*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2192 /* => */ RTUINT256_INIT_C(0xdd320063ac004000, 0xdd00f9005c091e00, 0x00998800d35b0000, 0x005b002300620000) },
2193 };
2194
2195 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2196 {
2197 { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2198 { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2199 { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2200 { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2201 { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2202 { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2203 { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2204 { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2205 };
2206 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2207 {
2208 { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2209 { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2210 { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2211 { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2212 { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2213 { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2214 { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2215 { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2216 };
2217 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2218 {
2219 { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2220 { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2221 { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2222 { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2223 { bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2224 { bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2225 { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2226 { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2227 { bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2228 { bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2229 { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2230 { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2231 { bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2232 { bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2233 };
2234 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2235 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2236 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2237 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2238}
2239
2240
2241/*
2242 * [V]PUNPCKHBW
2243 */
2244BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_MM1_MM2_icebp);
2245BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp);
2246BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp);
2247BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp);
2248extern FNBS3FAR bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64;
2249extern FNBS3FAR bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64;
2250BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp);
2251BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp);
2252extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64;
2253extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64;
2254BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp);
2255BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp);
2256extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64;
2257extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64;
2258
2259BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhbw(uint8_t bMode)
2260{
2261 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2262 {
2263 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2264 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2265 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2266 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2267 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2268 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1e1f2e2f3e3f4e4) },
2269 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2270 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2271 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55dd55dd66ee66ee) },
2272 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2273 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2274 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c435cd3e0cd73a0) },
2275 };
2276 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2277 {
2278 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2279 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2280 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2281 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2282 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2283 /* => */ RTUINT256_INIT_C(0xf1b1f2b2f3b3f4b4, 0xf5b5f6b6f7b7f8b8, 0xd191d292d393d494, 0xd595d696d797d898) },
2284 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2285 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2286 /* => */ RTUINT256_INIT_C(0x55dd55dd66ee66ee, 0x77ff77ff88008800, 0x1199119922aa22aa, 0x33bb33bb44cc44cc) },
2287 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2288 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2289 /* => */ RTUINT256_INIT_C(0x4d1e09ddf0dd2aac, 0x6c09dc637332d594, 0xb48821002fe9a85b, 0x56bf4c999b62a2c3) },
2290 };
2291
2292 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2293 {
2294 { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2295 { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2296 { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2297 { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2298 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2299 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2300 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2301 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2302 };
2303 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2304 {
2305 { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2306 { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2307 { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2308 { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2309 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2310 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2311 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2312 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2313 };
2314 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2315 {
2316 { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2317 { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2318 { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2319 { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2320 { bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2321 { bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2322 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2323 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2324 { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2325 { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2326 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2327 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2328 { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2329 { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2330 };
2331 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2332 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2333 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2334 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2335}
2336
2337
2338/*
2339 * [V]PUNPCKHWD
2340 */
2341BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_MM1_MM2_icebp);
2342BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp);
2343BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp);
2344BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp);
2345extern FNBS3FAR bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64;
2346extern FNBS3FAR bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64;
2347BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp);
2348BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp);
2349extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64;
2350extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64;
2351BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp);
2352BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp);
2353extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64;
2354extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64;
2355
2356BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhwd(uint8_t bMode)
2357{
2358 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2359 {
2360 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2361 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2362 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2363 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2364 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2365 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2e1e2f3f4e3e4) },
2366 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2367 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2368 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x5555dddd6666eeee) },
2369 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2370 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2371 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5c43d3e073cda0) },
2372 };
2373 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2374 {
2375 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2376 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2377 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2378 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2379 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2380 /* => */ RTUINT256_INIT_C(0xf1f2b1b2f3f4b3b4, 0xf5f6b5b6f7f8b7b8, 0xd1d29192d3d49394, 0xd5d69596d7d89798) },
2381 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2382 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2383 /* => */ RTUINT256_INIT_C(0x5555dddd6666eeee, 0x7777ffff88880000, 0x111199992222aaaa, 0x3333bbbb4444cccc) },
2384 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2385 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2386 /* => */ RTUINT256_INIT_C(0x4d091eddf02addac, 0x6cdc096373d53294, 0xb42188002fa8e95b, 0x564cbf999ba262c3) },
2387 };
2388
2389 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2390 {
2391 { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2392 { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2393 { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2394 { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2395 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2396 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2397 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2398 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2399 };
2400 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2401 {
2402 { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2403 { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2404 { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2405 { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2406 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2407 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2408 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2409 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2410 };
2411 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2412 {
2413 { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2414 { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2415 { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2416 { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2417 { bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2418 { bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2419 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2420 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2421 { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2422 { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2423 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2424 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2425 { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2426 { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2427 };
2428 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2429 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2430 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2431 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2432}
2433
2434
2435/*
2436 * [V]PUNPCKHDQ
2437 */
2438BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_MM1_MM2_icebp);
2439BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp);
2440BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp);
2441BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp);
2442extern FNBS3FAR bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64;
2443extern FNBS3FAR bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64;
2444BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp);
2445BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp);
2446extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64;
2447extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64;
2448BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp);
2449BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp);
2450extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64;
2451extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64;
2452
2453BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhdq(uint8_t bMode)
2454{
2455 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2456 {
2457 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2458 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2459 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2460 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2461 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2462 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4e1e2e3e4) },
2463 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2464 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2465 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55556666ddddeeee) },
2466 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2467 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2468 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ce07343d3cda0) },
2469 };
2470 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2471 {
2472 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2473 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2474 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2475 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2476 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2477 /* => */ RTUINT256_INIT_C(0xf1f2f3f4b1b2b3b4, 0xf5f6f7f8b5b6b7b8, 0xd1d2d3d491929394, 0xd5d6d7d895969798) },
2478 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2479 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2480 /* => */ RTUINT256_INIT_C(0x55556666ddddeeee, 0x77778888ffff0000, 0x111122229999aaaa, 0x33334444bbbbcccc) },
2481 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2482 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2483 /* => */ RTUINT256_INIT_C(0x4d09f02a1eddddac, 0x6cdc73d509633294, 0xb4212fa88800e95b, 0x564c9ba2bf9962c3) },
2484 };
2485
2486 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2487 {
2488 { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2489 { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2490 { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2491 { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2492 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2493 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2494 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2495 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2496 };
2497 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2498 {
2499 { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2500 { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2501 { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2502 { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2503 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2504 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2505 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2506 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2507 };
2508 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2509 {
2510 { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2511 { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2512 { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2513 { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2514 { bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2515 { bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2516 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2517 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2518 { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2519 { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2520 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2521 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2522 { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2523 { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2524 };
2525 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2526 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2527 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2528 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2529}
2530
2531
2532/*
2533 * [V]PUNPCKHQDQ
2534 */
2535BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp);
2536BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp);
2537extern FNBS3FAR bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64;
2538extern FNBS3FAR bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64;
2539BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp);
2540BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp);
2541extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64;
2542extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64;
2543BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp);
2544BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp);
2545extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64;
2546extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64;
2547
2548BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhqdq(uint8_t bMode)
2549{
2550 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2551 {
2552 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2553 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2554 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2555 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2556 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2557 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) },
2558 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2559 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2560 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0xddddeeeeffff0000, 0x1111222233334444, 0x9999aaaabbbbcccc) },
2561 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2562 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2563 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) },
2564 };
2565
2566 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2567 {
2568 { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2569 { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2570 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2571 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2572 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2573 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2574 };
2575 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2576 {
2577 { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2578 { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2579 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2580 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2581 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2582 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2583 };
2584 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2585 {
2586 { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2587 { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2588 { bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2589 { bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2590 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2591 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2592 { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2593 { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2594 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2595 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2596 { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2597 { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2598 };
2599 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2600 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2601 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2602 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2603}
2604
2605
2606/*
2607 * [V]PUNPCKLBW
2608 */
2609BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_MM1_MM2_icebp);
2610BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp);
2611BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp);
2612BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp);
2613extern FNBS3FAR bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64;
2614extern FNBS3FAR bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64;
2615BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp);
2616BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp);
2617extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64;
2618extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64;
2619BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp);
2620BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp);
2621extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64;
2622extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64;
2623
2624BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklbw(uint8_t bMode)
2625{
2626 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2627 {
2628 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2629 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2630 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2631 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2632 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2633 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5e5f6e6f7e7f8e8) },
2634 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2635 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2636 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77ff77ff88008800) },
2637 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2638 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2639 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x932309849699bbfd) },
2640 };
2641 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2642 {
2643 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2644 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2645 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2646 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2647 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2648 /* => */ RTUINT256_INIT_C(0xe1a1e2a2e3a3e4a4, 0xe5a5e6a6e7a7e8a8, 0xc181c282c383c484, 0xc585c686c787c888) },
2649 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2650 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2651 /* => */ RTUINT256_INIT_C(0x1199119922aa22aa, 0x33bb33bb44cc44cc, 0x55dd55dd66ee66ee, 0x77ff77ff88008800) },
2652 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2653 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2654 /* => */ RTUINT256_INIT_C(0x3ef9f45c178ec8ec, 0x66406b723f56e633, 0x9c435cd3e0cd73a0, 0x932309849699bbfd) },
2655 };
2656
2657 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2658 {
2659 { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2660 { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2661 { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2662 { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2663 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2664 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2665 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2666 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2667 };
2668 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2669 {
2670 { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2671 { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2672 { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2673 { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2674 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2675 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2676 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2677 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2678 };
2679 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2680 {
2681 { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2682 { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2683 { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2684 { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2685 { bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2686 { bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2687 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2688 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2689 { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2690 { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2691 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2692 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2693 { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2694 { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2695 };
2696 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2697 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2698 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2699 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2700}
2701
2702
2703/*
2704 * [V]PUNPCKLWD
2705 */
2706BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_MM1_MM2_icebp);
2707BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp);
2708BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp);
2709BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp);
2710extern FNBS3FAR bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64;
2711extern FNBS3FAR bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64;
2712BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp);
2713BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp);
2714extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64;
2715extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64;
2716BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp);
2717BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp);
2718extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64;
2719extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64;
2720
2721BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklwd(uint8_t bMode)
2722{
2723 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2724 {
2725 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2726 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2727 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2728 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2729 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2730 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6e5e6f7f8e7e8) },
2731 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2732 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2733 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7777ffff88880000) },
2734 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2735 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2736 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9309238496bb99fd) },
2737 };
2738 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2739 {
2740 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2741 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2742 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2743 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2744 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2745 /* => */ RTUINT256_INIT_C(0xe1e2a1a2e3e4a3a4, 0xe5e6a5a6e7e8a7a8, 0xc1c28182c3c48384, 0xc5c68586c7c88788) },
2746 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2747 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2748 /* => */ RTUINT256_INIT_C(0x111199992222aaaa, 0x3333bbbb4444cccc, 0x5555dddd6666eeee, 0x7777ffff88880000) },
2749 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2750 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2751 /* => */ RTUINT256_INIT_C(0x3ef4f95c17c88eec, 0x666b40723fe65633, 0x9c5c43d3e073cda0, 0x9309238496bb99fd) },
2752 };
2753
2754 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2755 {
2756 { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2757 { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2758 { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2759 { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2760 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2761 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2762 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2763 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2764 };
2765 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2766 {
2767 { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2768 { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2769 { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2770 { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2771 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2772 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2773 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2774 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2775 };
2776 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2777 {
2778 { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2779 { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2780 { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2781 { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2782 { bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2783 { bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2784 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2785 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2786 { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2787 { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2788 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2789 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2790 { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2791 { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2792 };
2793 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2794 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2795 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2796 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2797}
2798
2799
2800/*
2801 * [V]PUNPCKLDQ
2802 */
2803BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_MM1_MM2_icebp);
2804BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp);
2805BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp);
2806BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp);
2807extern FNBS3FAR bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64;
2808extern FNBS3FAR bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64;
2809BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp);
2810BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp);
2811extern FNBS3FAR bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64;
2812extern FNBS3FAR bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64;
2813BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp);
2814BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp);
2815extern FNBS3FAR bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64;
2816extern FNBS3FAR bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64;
2817
2818BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckldq(uint8_t bMode)
2819{
2820 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2821 {
2822 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2823 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2824 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2825 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2826 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2827 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6f7f8e5e6e7e8) },
2828 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2829 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2830 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77778888ffff0000) },
2831 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2832 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2833 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x930996bb238499fd) },
2834 };
2835 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2836 {
2837 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2838 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2839 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2840 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2841 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2842 /* => */ RTUINT256_INIT_C(0xe1e2e3e4a1a2a3a4, 0xe5e6e7e8a5a6a7a8, 0xc1c2c3c481828384, 0xc5c6c7c885868788) },
2843 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2844 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2845 /* => */ RTUINT256_INIT_C(0x111122229999aaaa, 0x33334444bbbbcccc, 0x55556666ddddeeee, 0x77778888ffff0000) },
2846 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2847 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2848 /* => */ RTUINT256_INIT_C(0x3ef417c8f95c8eec, 0x666b3fe640725633, 0x9c5ce07343d3cda0, 0x930996bb238499fd) },
2849 };
2850
2851 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2852 {
2853 { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2854 { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2855 { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2856 { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2857 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2858 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2859 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2860 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2861 };
2862 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2863 {
2864 { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2865 { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2866 { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2867 { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2868 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2869 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2870 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2871 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2872 };
2873 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2874 {
2875 { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2876 { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2877 { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2878 { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2879 { bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2880 { bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2881 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2882 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2883 { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2884 { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2885 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2886 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2887 { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2888 { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2889 };
2890 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2891 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2892 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2893 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2894}
2895
2896
2897/*
2898 * [V]PUNPCKLQDQ
2899 */
2900BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp);
2901BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp);
2902extern FNBS3FAR bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64;
2903extern FNBS3FAR bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64;
2904BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp);
2905BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp);
2906extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64;
2907extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64;
2908BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp);
2909BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp);
2910extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64;
2911extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64;
2912
2913BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklqdq(uint8_t bMode)
2914{
2915 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2916 {
2917 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2918 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2919 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2920 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2921 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2922 /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) },
2923 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2924 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2925 /* => */ RTUINT256_INIT_C(0x1111222233334444, 0x9999aaaabbbbcccc, 0x5555666677778888, 0xddddeeeeffff0000) },
2926 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2927 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2928 /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) },
2929 };
2930
2931 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2932 {
2933 { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2934 { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2935 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2936 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2937 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2938 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2939 };
2940 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2941 {
2942 { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2943 { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2944 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2945 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2946 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2947 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2948 };
2949 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2950 {
2951 { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2952 { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2953 { bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2954 { bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2955 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2956 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2957 { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2958 { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2959 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2960 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2961 { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2962 { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2963 };
2964 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2965 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2966 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2967 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2968}
2969
2970
2971/*
2972 * [V]PACKSSWB
2973 */
2974BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_MM1_MM2_icebp);
2975BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_MM1_FSxBX_icebp);
2976BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_XMM1_XMM2_icebp);
2977BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp);
2978extern FNBS3FAR bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64;
2979extern FNBS3FAR bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64;
2980BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp);
2981BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp);
2982extern FNBS3FAR bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64;
2983extern FNBS3FAR bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64;
2984BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp);
2985BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp);
2986extern FNBS3FAR bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64;
2987extern FNBS3FAR bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64;
2988
2989BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packsswb(uint8_t bMode)
2990{
2991 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2992 {
2993 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2994 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2995 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2996 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2997 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2998 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8080808080808080) },
2999 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3000 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3001 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7f7f7f808080ff00) },
3002 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3003 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3004 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x808080807f807f80) },
3005 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042),
3006 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
3007 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8264fe4222808081) },
3008 };
3009 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3010 {
3011 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3012 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3013 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3014 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3015 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3016 /* => */ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080) },
3017 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3018 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3019 /* => */ RTUINT256_INIT_C(0x7f7f7f807f7f7f7f, 0x8080ff0080808080, 0x7f7f7f7f7f7f7f80, 0x808080808080ff00) },
3020 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3021 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3022 /* => */ RTUINT256_INIT_C(0x7f807f7f7f7f7f7f, 0x7f807f7f80807f7f, 0x807f7f8080808080, 0x8080807f7f807f80) },
3023 { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080),
3024 /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035),
3025 /* => */ RTUINT256_INIT_C(0x2225797efffe8880, 0x01020305070b0d11, 0x6432160842467f7f, 0x13171d25292b2f35) },
3026 };
3027
3028 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3029 {
3030 { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3031 { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3032 { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3033 { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3034 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3035 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3036 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3037 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3038 };
3039 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3040 {
3041 { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3042 { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3043 { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3044 { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3045 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3046 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3047 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3048 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3049 };
3050 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3051 {
3052 { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3053 { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3054 { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3055 { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3056 { bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3057 { bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3058 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3059 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3060 { bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3061 { bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3062 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3063 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3064 { bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3065 { bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3066 };
3067 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3068 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3069 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3070 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3071}
3072
3073
3074/*
3075 * [V]PACKSSDW
3076 */
3077BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_MM1_MM2_icebp);
3078BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_MM1_FSxBX_icebp);
3079BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_XMM1_XMM2_icebp);
3080BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp);
3081extern FNBS3FAR bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64;
3082extern FNBS3FAR bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64;
3083BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp);
3084BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp);
3085extern FNBS3FAR bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64;
3086extern FNBS3FAR bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64;
3087BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp);
3088BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp);
3089extern FNBS3FAR bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64;
3090extern FNBS3FAR bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64;
3091
3092BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packssdw(uint8_t bMode)
3093{
3094 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
3095 {
3096 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3097 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3098 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3099 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3100 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3101 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8000800080008000) },
3102 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3103 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3104 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7fff7fff80008000) },
3105 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3106 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3107 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x800080007fff7fff) },
3108 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xffff898400007495),
3109 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x00002222ffff9485),
3110 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8984749522229485) },
3111 };
3112 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3113 {
3114 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3115 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3116 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3117 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3118 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3119 /* => */ RTUINT256_INIT_C(0x8000800080008000, 0x8000800080008000, 0x8000800080008000, 0x8000800080008000) },
3120 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3121 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3122 /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x8000800080008000, 0x7fff7fff7fff7fff, 0x8000800080008000) },
3123 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3124 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3125 /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x7fff7fff80007fff, 0x80007fff80008000, 0x800080007fff7fff) },
3126 { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff),
3127 /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0),
3128 /* => */ RTUINT256_INIT_C(0x34902349a230e384, 0x80017ffecbaffffe, 0x80007ffe7fff8000, 0x64321608ffe0ffc0) },
3129 };
3130
3131 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3132 {
3133 { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3134 { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3135 { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3136 { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3137 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3138 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3139 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3140 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3141 };
3142 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3143 {
3144 { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3145 { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3146 { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3147 { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3148 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3149 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3150 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3151 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3152 };
3153 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3154 {
3155 { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3156 { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3157 { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3158 { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3159 { bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3160 { bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3161 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3162 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3163 { bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3164 { bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3165 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3166 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3167 { bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3168 { bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3169 };
3170 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3171 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3172 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3173 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3174}
3175
3176
3177/*
3178 * [V]PACKUSWB
3179 */
3180BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_MM1_MM2_icebp);
3181BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_MM1_FSxBX_icebp);
3182BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_XMM1_XMM2_icebp);
3183BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp);
3184extern FNBS3FAR bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64;
3185extern FNBS3FAR bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64;
3186BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp);
3187BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp);
3188extern FNBS3FAR bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64;
3189extern FNBS3FAR bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64;
3190BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp);
3191BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp);
3192extern FNBS3FAR bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64;
3193extern FNBS3FAR bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64;
3194
3195BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packuswb(uint8_t bMode)
3196{
3197 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
3198 {
3199 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3200 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3201 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3202 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3203 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3204 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) },
3205 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3206 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3207 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xffffff0000000000) },
3208 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3209 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3210 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00000000ff00ff00) },
3211 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042),
3212 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
3213 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x0064004222000000) },
3214 };
3215 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3216 {
3217 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3218 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3219 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3220 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3221 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3222 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
3223 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3224 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3225 /* => */ RTUINT256_INIT_C(0xffffff00ffffffff, 0x0000000000000000, 0xffffffffffffff00, 0x000000000000000) },
3226 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3227 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3228 /* => */ RTUINT256_INIT_C(0xff00ffffffffffff, 0xff00ffff0000ffff, 0x00ffff0000000000, 0x000000ffff00ff00) },
3229 { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080),
3230 /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035),
3231 /* => */ RTUINT256_INIT_C(0x2225797e00000000, 0x01020305070b0d11, 0x6432160842468880, 0x13171d25292b2f35) },
3232 };
3233
3234 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3235 {
3236 { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3237 { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3238 { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3239 { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3240 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3241 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3242 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3243 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3244 };
3245 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3246 {
3247 { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3248 { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3249 { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3250 { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3251 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3252 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3253 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3254 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3255 };
3256 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3257 {
3258 { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3259 { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3260 { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3261 { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3262 { bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3263 { bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3264 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3265 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3266 { bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3267 { bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3268 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3269 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3270 { bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3271 { bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3272 };
3273 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3274 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3275 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3276 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3277}
3278
3279
3280/*
3281 * [V]PACKUSDW
3282 */
3283BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packusdw_XMM1_XMM2_icebp);
3284BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp);
3285extern FNBS3FAR bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64;
3286extern FNBS3FAR bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64;
3287BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp);
3288BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp);
3289extern FNBS3FAR bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64;
3290extern FNBS3FAR bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64;
3291BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp);
3292BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp);
3293extern FNBS3FAR bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64;
3294extern FNBS3FAR bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64;
3295BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packusdw(uint8_t bMode)
3296{
3297 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3298 {
3299 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3300 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3301 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3302 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3303 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3304 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
3305 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3306 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3307 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000) },
3308 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3309 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3310 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffff0000ffff, 0x0000ffff00000000, 0x00000000ffffffff) },
3311 { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff),
3312 /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0),
3313 /* => */ RTUINT256_INIT_C(0x3490234900000000, 0x00007ffe00000000, 0x00007ffe80000000, 0x6432160800000000) },
3314 };
3315
3316 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3317 {
3318 { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3319 { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3320 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3321 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3322 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3323 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3324 };
3325 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3326 {
3327 { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3328 { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3329 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3330 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3331 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3332 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3333 };
3334 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3335 {
3336 { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3337 { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3338 { bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3339 { bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3340 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3341 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3342 { bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3343 { bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3344 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3345 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3346 { bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3347 { bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3348 };
3349 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3350 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3351 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3352 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3353}
3354
3355
3356/*
3357 * [V]MOVSS - move (mem) or merge (reg) scalar single-precision floating-point value.
3358 */
3359BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_XMM1_XMM2_icebp);
3360BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_XMM1_FSxBX_icebp);
3361BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_FSxBX_XMM1_icebp);
3362BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_XMM1_XMM2_icebp);
3363BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp);
3364BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp);
3365extern FNBS3FAR bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64;
3366extern FNBS3FAR bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64;
3367extern FNBS3FAR bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64;
3368extern FNBS3FAR bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64;
3369extern FNBS3FAR bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64;
3370extern FNBS3FAR bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64;
3371
3372BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movss(uint8_t bMode)
3373{
3374 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] =
3375 {
3376 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
3377 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
3378 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3379 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3380 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3381 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x81828384c5c6c7c8) },
3382 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3383 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3384 /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeee77778888) },
3385 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3386 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3387 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0930996bb) },
3388 };
3389 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] =
3390 {
3391 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
3392 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
3393 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3394 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3395 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3396 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000c5c6c7c8) },
3397 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3398 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3399 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000077778888) },
3400 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3401 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3402 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000930996bb) },
3403 };
3404
3405 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3406 {
3407 { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3408 { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3409 { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3410
3411 { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3412 { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3413 { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3414 };
3415 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3416 {
3417 { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3418 { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3419 { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3420
3421 { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3422 { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3423 { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3424 };
3425 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3426 {
3427 { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3428 { bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3429 { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3430 { bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3431 { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3432 { bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3433
3434 { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3435 { bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3436 { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3437 { bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3438 { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3439 { bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3440 };
3441 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3442 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3443 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3444 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
3445}
3446
3447
3448/*
3449 * [V]MOVSD - move (mem) or merge (reg) scalar single-precision floating-point value.
3450 */
3451BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_XMM1_XMM2_icebp);
3452BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_XMM1_FSxBX_icebp);
3453BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_FSxBX_XMM1_icebp);
3454BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp);
3455BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp);
3456BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp);
3457extern FNBS3FAR bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64;
3458extern FNBS3FAR bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64;
3459extern FNBS3FAR bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64;
3460extern FNBS3FAR bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64;
3461extern FNBS3FAR bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64;
3462extern FNBS3FAR bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64;
3463
3464BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsd(uint8_t bMode)
3465{
3466 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] =
3467 {
3468 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
3469 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
3470 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3471 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3472 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3473 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
3474 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
3475 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3476 /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
3477 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3478 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3479 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
3480 };
3481 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] =
3482 {
3483 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
3484 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
3485 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3486 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3487 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3488 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8) },
3489 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3490 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3491 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x5555666677778888) },
3492 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3493 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3494 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb) },
3495 };
3496
3497 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3498 {
3499 { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3500 { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3501 { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3502
3503 { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3504 { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3505 { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3506 };
3507 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3508 {
3509 { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3510 { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3511 { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3512
3513 { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3514 { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3515 { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3516 };
3517 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3518 {
3519 { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3520 { bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3521 { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3522 { bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3523 { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3524 { bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3525
3526 { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3527 { bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR },
3528 { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3529 { bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3530 { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3531 { bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM },
3532 };
3533 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3534 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3535 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3536 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
3537}
3538
3539
3540/*
3541 * [V]MOVLPS - Merge a low qword (two single precision floating-point values)
3542 * from memory with the high qword from a register (SSE destination
3543 * or VEX 2nd source).
3544 * The store variant just stores the lower qword.
3545 */
3546BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_XMM1_FSxBX_icebp);
3547BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_FSxBX_XMM1_icebp);
3548BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp);
3549BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp);
3550extern FNBS3FAR bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64;
3551extern FNBS3FAR bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64;
3552extern FNBS3FAR bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64;
3553extern FNBS3FAR bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64;
3554
3555BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movlps(uint8_t bMode)
3556{
3557 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] =
3558 {
3559 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3560 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3561 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3562 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3563 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3564 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
3565 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
3566 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3567 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
3568 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3569 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3570 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
3571 };
3572 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] =
3573 {
3574 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3575 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3576 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3577 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3578 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3579 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
3580 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
3581 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3582 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
3583 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3584 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3585 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
3586 };
3587
3588 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3589 {
3590 { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3591 { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
3592
3593 { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3594 { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
3595 };
3596 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3597 {
3598 { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3599 { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
3600
3601 { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3602 { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
3603 };
3604 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3605 {
3606 { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3607 { bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3608 { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
3609 { bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
3610
3611 { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3612 { bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
3613 { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
3614 { bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
3615 };
3616 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3617 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3618 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3619 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
3620}
3621
3622
3623
3624
3625
3626/*
3627 * Test type #2 - GPR <- MM/XMM/YMM, no VVVV.
3628 */
3629
3630typedef struct BS3CPUINSTR3_TEST2_VALUES_T
3631{
3632 RTUINT256U uSrc;
3633 uint64_t uDstOut;
3634} BS3CPUINSTR3_TEST2_VALUES_T;
3635
3636typedef struct BS3CPUINSTR3_TEST2_T
3637{
3638 FPFNBS3FAR pfnWorker;
3639 uint8_t bAvxMisalignXcpt;
3640 uint8_t enmRm;
3641 uint8_t enmType;
3642 uint8_t cbDst;
3643 uint8_t cBitsDstValMask;
3644 bool fInvalidEncoding;
3645 uint8_t iRegDst;
3646 uint8_t iRegSrc;
3647 uint8_t cValues;
3648 BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues;
3649} BS3CPUINSTR3_TEST2_T;
3650
3651typedef struct BS3CPUINSTR3_TEST2_MODE_T
3652{
3653 BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests;
3654 unsigned cTests;
3655} BS3CPUINSTR3_TEST2_MODE_T;
3656
3657/** Initializer for a BS3CPUINSTR3_TEST2_MODE_T array (three entries). */
3658#define BS3CPUINSTR3_TEST2_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
3659 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
3660
3661
3662/**
3663 * Test type #2 worker.
3664 */
3665static uint8_t bs3CpuInstr3_WorkerTestType2(uint8_t bMode, BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests, unsigned cTests,
3666 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs)
3667{
3668 BS3REGCTX Ctx;
3669 BS3TRAPFRAME TrapFrame;
3670 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
3671 uint8_t BS3_FAR *pbBuf = g_pbBuf;
3672 uint32_t cbBuf = g_cbBuf;
3673 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
3674 PBS3EXTCTX pExtCtxOut;
3675 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
3676 if (!pExtCtx)
3677 return 0;
3678
3679 /* Ensure the structures are allocated before we sample the stack pointer. */
3680 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
3681 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
3682
3683 /*
3684 * Create test context.
3685 */
3686 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
3687 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
3688 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
3689 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]);
3690
3691 /*
3692 * Run the tests in all rings since alignment issues may behave
3693 * differently in ring-3 compared to ring-0.
3694 */
3695 for (;;)
3696 {
3697 unsigned iCfg;
3698 for (iCfg = 0; iCfg < cConfigs; iCfg++)
3699 {
3700 unsigned iTest;
3701 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
3702 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
3703 continue; /* unsupported config */
3704
3705 /*
3706 * Iterate the tests.
3707 */
3708 for (iTest = 0; iTest < cTests; iTest++)
3709 {
3710 BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
3711 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
3712 unsigned const cValues = paTests[iTest].cValues;
3713 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
3714 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
3715 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
3716 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
3717 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
3718 uint8_t const cbMemOp = cbOperand;
3719 uint8_t const cbAlign = RT_MIN(cbOperand, 16);
3720 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
3721 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType]
3722 || paTests[iTest].fInvalidEncoding ? X86_XCPT_UD
3723 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
3724 : fSseInstr ? paConfigs[iCfg].bXcptSse
3725 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
3726 uint64_t const fDstValMask = paTests[iTest].cBitsDstValMask == 64 ? UINT64_MAX
3727 : RT_BIT_64(paTests[iTest].cBitsDstValMask) - 1;
3728 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
3729 unsigned iVal;
3730
3731 /* If testing unaligned memory accesses, skip register-only tests. This allows
3732 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
3733 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
3734 continue;
3735
3736 /* #AC is only raised in ring-3.: */
3737 if (bXcptExpect == X86_XCPT_AC)
3738 {
3739 if (bRing != 3)
3740 bXcptExpect = X86_XCPT_DB;
3741 else if (fAvxInstr)
3742 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
3743 }
3744
3745 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
3746
3747 /*
3748 * Iterate the test values and do the actual testing.
3749 */
3750 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
3751 {
3752 uint16_t cErrors;
3753 uint16_t uSavedFtw = 0xff;
3754 RTUINT256U uMemOpExpect;
3755
3756 /*
3757 * Set up the context and some expectations.
3758 */
3759 /* dest */
3760 if (paTests[iTest].iRegDst == UINT8_MAX)
3761 {
3762 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
3763 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
3764 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
3765 if (bXcptExpect == X86_XCPT_DB)
3766 switch (paTests[iTest].cbDst)
3767 {
3768 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uDstOut & fDstValMask); break;
3769 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uDstOut & fDstValMask); break;
3770 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uDstOut & fDstValMask); break;
3771 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uDstOut & fDstValMask); break;
3772 default: BS3_ASSERT(0);
3773 }
3774 }
3775
3776 /* source */
3777 if (paTests[iTest].iRegSrc == UINT8_MAX)
3778 {
3779 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
3780 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX);
3781 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc, cbMemOp);
3782 uMemOpExpect = paValues[iVal].uSrc;
3783 }
3784 else if (fMmxInstr)
3785 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
3786 else if (fSseInstr)
3787 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0);
3788 else
3789 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32);
3790
3791 /* Memory pointer. */
3792 if (paTests[iTest].enmRm >= RM_MEM)
3793 {
3794 BS3_ASSERT(paTests[iTest].iRegDst == UINT8_MAX || paTests[iTest].iRegSrc == UINT8_MAX);
3795 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
3796 }
3797
3798 /*
3799 * Execute.
3800 */
3801 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
3802
3803 /*
3804 * Check the result:
3805 */
3806 cErrors = Bs3TestSubErrorCount();
3807
3808 if (fMmxInstr && bXcptExpect == X86_XCPT_DB)
3809 {
3810 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
3811 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
3812 }
3813 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
3814
3815 if (TrapFrame.bXcpt != bXcptExpect)
3816 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
3817
3818 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX)
3819 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iRegDst, paValues[iVal].uDstOut & fDstValMask, paTests[iTest].cbDst);
3820 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
3821 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
3822 {
3823 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
3824 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
3825 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
3826 }
3827 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
3828 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
3829 pszMode, idTestStep);
3830
3831 if ( paTests[iTest].enmRm >= RM_MEM
3832 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbOperand) != 0)
3833 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
3834
3835 if (cErrors != Bs3TestSubErrorCount())
3836 {
3837 if (paConfigs[iCfg].fAligned)
3838 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
3839 bRing, iCfg, iTest, iVal, bXcptExpect);
3840 else
3841 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
3842 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
3843 Bs3TestPrintf("\n");
3844 }
3845
3846 if (uSavedFtw != 0xff)
3847 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
3848 }
3849 }
3850
3851 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
3852 }
3853
3854 /*
3855 * Next ring.
3856 */
3857 bRing++;
3858 if (bRing > 3 || bMode == BS3_MODE_RM)
3859 break;
3860 Bs3RegCtxConvertToRingX(&Ctx, bRing);
3861 }
3862
3863 /*
3864 * Cleanup.
3865 */
3866 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
3867 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
3868 return 0;
3869}
3870
3871
3872/*
3873 * PMOVMSKB, VPMOVMSKB.
3874 */
3875BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_MM2_icebp);
3876BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp);
3877BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp);
3878BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp);
3879BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp);
3880BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp);
3881BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp);
3882BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp);
3883extern FNBS3FAR bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64;
3884
3885BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovmskb(uint8_t bMode)
3886{
3887 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues[] =
3888 {
3889 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) },
3890 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffff) },
3891 { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00000000) },
3892 { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xffffffff) },
3893 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x03000003) },
3894 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x255193ab) },
3895 };
3896
3897 static BS3CPUINSTR3_TEST2_T const s_aTests16[] =
3898 {
3899 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3900 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3901 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3902 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3903 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3904 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3905 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 4, 32, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3906 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 4, 32, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3907 };
3908 static BS3CPUINSTR3_TEST2_T const s_aTests32[] =
3909 {
3910 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3911 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3912 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3913 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3914 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3915 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3916 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 4, 32, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3917 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 4, 32, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3918 };
3919 static BS3CPUINSTR3_TEST2_T const s_aTests64[] =
3920 {
3921 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 8, 8, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3922 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 8, 8, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3923 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3924 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3925 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3926 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3927 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
3928 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 8, 32, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
3929 { bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, 0, 9, RT_ELEMENTS(s_aValues), s_aValues },
3930 };
3931 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3932 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3933 return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3934 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3935}
3936
3937
3938/*
3939 * Test type #3.
3940 */
3941
3942typedef struct BS3CPUINSTR3_TEST3_VALUES_T
3943{
3944 RTUINT256U uSrc;
3945 RTUINT256U uDstOut;
3946} BS3CPUINSTR3_TEST3_VALUES_T;
3947
3948typedef struct BS3CPUINSTR3_TEST3_T
3949{
3950 FPFNBS3FAR pfnWorker;
3951 uint8_t bAvxMisalignXcpt;
3952 uint8_t enmRm;
3953 uint8_t enmType;
3954 uint8_t iRegDst;
3955 uint8_t iRegSrc;
3956 uint8_t cValues;
3957 BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues;
3958} BS3CPUINSTR3_TEST3_T;
3959
3960typedef struct BS3CPUINSTR3_TEST3_MODE_T
3961{
3962 BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests;
3963 unsigned cTests;
3964} BS3CPUINSTR3_TEST3_MODE_T;
3965
3966/** Initializer for a BS3CPUINSTR3_TEST3_MODE_T array (three entries). */
3967#define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
3968 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
3969
3970
3971/**
3972 * Test type #1 worker.
3973 */
3974static uint8_t bs3CpuInstr3_WorkerTestType3(uint8_t bMode, BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests, unsigned cTests,
3975 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint8_t cbMaxAlign)
3976{
3977 BS3REGCTX Ctx;
3978 BS3TRAPFRAME TrapFrame;
3979 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
3980 uint8_t BS3_FAR *pbBuf = g_pbBuf;
3981 uint32_t cbBuf = g_cbBuf;
3982 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
3983 PBS3EXTCTX pExtCtxOut;
3984 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
3985 if (!pExtCtx)
3986 return 0;
3987
3988 /* Ensure the structures are allocated before we sample the stack pointer. */
3989 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
3990 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
3991
3992 /*
3993 * Create test context.
3994 */
3995 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
3996 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
3997 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
3998
3999 /*
4000 * Run the tests in all rings since alignment issues may behave
4001 * differently in ring-3 compared to ring-0.
4002 */
4003 for (;;)
4004 {
4005 unsigned iCfg;
4006 for (iCfg = 0; iCfg < cConfigs; iCfg++)
4007 {
4008 unsigned iTest;
4009 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
4010 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
4011 continue; /* unsupported config */
4012
4013 /*
4014 * Iterate the tests.
4015 */
4016 for (iTest = 0; iTest < cTests; iTest++)
4017 {
4018 BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
4019 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
4020 unsigned const cValues = paTests[iTest].cValues;
4021 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
4022 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
4023 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
4024 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
4025 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
4026 uint8_t const cbMemOp = cbOperand;
4027 uint8_t const cbAlign = RT_MIN(cbOperand, !cbMaxAlign ? 16 : cbMaxAlign);
4028 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
4029 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD
4030 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
4031 : fSseInstr ? paConfigs[iCfg].bXcptSse
4032 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
4033 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
4034 unsigned iVal;
4035
4036 /* If testing unaligned memory accesses, skip register-only tests. This allows
4037 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
4038 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
4039 continue;
4040
4041 /* #AC is only raised in ring-3.: */
4042 if (bXcptExpect == X86_XCPT_AC)
4043 {
4044 if (bRing != 3)
4045 bXcptExpect = X86_XCPT_DB;
4046 else if (fAvxInstr)
4047 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
4048 }
4049
4050 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
4051
4052 /*
4053 * Iterate the test values and do the actual testing.
4054 */
4055 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
4056 {
4057 uint16_t cErrors;
4058 uint16_t uSavedFtw = 0xff;
4059 RTUINT256U uMemOpExpect;
4060
4061 /*
4062 * Set up the context and some expectations.
4063 */
4064 /* dest */
4065 if (paTests[iTest].iRegDst == UINT8_MAX)
4066 {
4067 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
4068 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
4069 if (bXcptExpect == X86_XCPT_DB)
4070 uMemOpExpect = paValues[iVal].uDstOut;
4071 else
4072 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
4073 }
4074 else if (fMmxInstr)
4075 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
4076
4077 /* source */
4078 if (paTests[iTest].iRegSrc == UINT8_MAX)
4079 {
4080 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
4081 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX);
4082 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc, cbMemOp);
4083 uMemOpExpect = paValues[iVal].uSrc;
4084 }
4085 else if (fMmxInstr)
4086 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
4087 else if (fSseInstr)
4088 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0);
4089 else
4090 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32);
4091
4092 /* Memory pointer. */
4093 if (paTests[iTest].enmRm >= RM_MEM)
4094 {
4095 BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX
4096 || paTests[iTest].iRegSrc == UINT8_MAX);
4097 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
4098 }
4099
4100 /*
4101 * Execute.
4102 */
4103 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
4104
4105 /*
4106 * Check the result:
4107 */
4108 cErrors = Bs3TestSubErrorCount();
4109
4110 if (bXcptExpect == X86_XCPT_DB && fMmxInstr)
4111 {
4112 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
4113 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
4114 }
4115 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX)
4116 {
4117 if (fMmxInstr)
4118 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET);
4119 else if (fSseInstr)
4120 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0);
4121 else
4122 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand);
4123 }
4124 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
4125
4126 if (TrapFrame.bXcpt != bXcptExpect)
4127 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
4128
4129 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
4130 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
4131 {
4132 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
4133 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
4134 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
4135 }
4136 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
4137 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
4138 pszMode, idTestStep);
4139
4140 if ( paTests[iTest].enmRm >= RM_MEM
4141 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
4142 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
4143
4144 if (cErrors != Bs3TestSubErrorCount())
4145 {
4146 /*if (paConfigs[iCfg].fAligned)
4147 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
4148 bRing, iCfg, iTest, iVal, bXcptExpect);
4149 else*/
4150 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
4151 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
4152 Bs3TestPrintf("\n");
4153 }
4154
4155 if (uSavedFtw != 0xff)
4156 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
4157 }
4158 }
4159
4160 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
4161 }
4162
4163 /*
4164 * Next ring.
4165 */
4166 bRing++;
4167 if (bRing > 3 || bMode == BS3_MODE_RM)
4168 break;
4169 Bs3RegCtxConvertToRingX(&Ctx, bRing);
4170 }
4171
4172 /*
4173 * Cleanup.
4174 */
4175 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
4176 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
4177 return 0;
4178}
4179
4180
4181/*
4182 * PSHUFW
4183 */
4184BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp);
4185BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp);
4186BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp);
4187BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp);
4188
4189BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufw(uint8_t bMode)
4190{
4191 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
4192 {
4193 { RTUINT256_INIT_C(0, 0, 0, 0),
4194 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4195 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff),
4196 /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) },
4197 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888),
4198 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x5555555555555555) },
4199 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb),
4200 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x9c5c9c5c9c5c9c5c) },
4201 };
4202
4203 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
4204 {
4205 { RTUINT256_INIT_C(0, 0, 0, 0),
4206 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4207 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff),
4208 /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) },
4209 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888),
4210 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x8888777766665555) },
4211 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb),
4212 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x96bb9309e0739c5c) },
4213 };
4214
4215 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4216 {
4217 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4218 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4219 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4220 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4221 };
4222 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4223 {
4224 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4225 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4226 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4227 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4228 };
4229 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4230 {
4231 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4232 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4233 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4234 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4235 };
4236 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4237 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4238 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4239 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
4240}
4241
4242
4243/*
4244 * [V]PSHUFHW
4245 */
4246BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp);
4247BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp);
4248BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp);
4249BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp);
4250
4251BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp);
4252BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp);
4253BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp);
4254BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp);
4255
4256BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp);
4257BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp);
4258BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp);
4259BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp);
4260extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64;
4261extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64;
4262
4263BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufhw(uint8_t bMode)
4264{
4265 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
4266 {
4267 { RTUINT256_INIT_C(0, 0, 0, 0),
4268 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4269 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4270 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4271 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4272 /* => */ RTUINT256_INIT_C(0x5555555555555555, 0x1111222233334444, 0x1111111111111111, 0x5555666677778888) },
4273 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4274 /* => */ RTUINT256_INIT_C(0x4d094d094d094d09, 0x3ef417c8666b3fe6, 0xb421b421b421b421, 0x9c5ce073930996bb) },
4275 };
4276
4277 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
4278 {
4279 { RTUINT256_INIT_C(0, 0, 0, 0),
4280 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4281 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4282 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4283 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4284 /* => */ RTUINT256_INIT_C(0x8888777766665555, 0x1111222233334444, 0x4444333322221111, 0x5555666677778888) },
4285 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4286 /* => */ RTUINT256_INIT_C(0x73d56cdcf02a4d09, 0x3ef417c8666b3fe6, 0x9ba2564c2fa8b421, 0x9c5ce073930996bb) },
4287 };
4288
4289 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4290 {
4291 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4292 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4293 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4294 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4295
4296 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4297 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4298 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4299 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4300
4301 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4302 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4303 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4304 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4305 };
4306 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4307 {
4308 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4309 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4310 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4311 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4312
4313 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4314 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4315 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4316 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4317
4318 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4319 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4320 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4321 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4322 };
4323 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4324 {
4325 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4326 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4327 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4328 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4329
4330 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4331 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4332 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4333 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4334
4335 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4336 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4337 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4338 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4339 { bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4340 { bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4341 };
4342 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4343 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4344 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4345 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
4346}
4347
4348
4349/*
4350 * [V]PSHUFLW
4351 */
4352BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp);
4353BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp);
4354BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp);
4355BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp);
4356
4357BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp);
4358BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp);
4359BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp);
4360BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp);
4361
4362BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp);
4363BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp);
4364BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp);
4365BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp);
4366extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64;
4367extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64;
4368
4369BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshuflw(uint8_t bMode)
4370{
4371 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
4372 {
4373 { RTUINT256_INIT_C(0, 0, 0, 0),
4374 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4375 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4376 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4377 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4378 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x1111111111111111, 0x1111222233334444, 0x5555555555555555) },
4379 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4380 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef43ef43ef43ef4, 0xb4212fa8564c9ba2, 0x9c5c9c5c9c5c9c5c) },
4381 };
4382
4383 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
4384 {
4385 { RTUINT256_INIT_C(0, 0, 0, 0),
4386 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4387 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4388 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4389 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4390 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x4444333322221111, 0x1111222233334444, 0x8888777766665555) },
4391 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4392 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3fe6666b17c83ef4, 0xb4212fa8564c9ba2, 0x96bb9309e0739c5c) },
4393 };
4394
4395 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4396 {
4397 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4398 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4399 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4400 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4401
4402 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4403 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4404 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4405 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4406
4407 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4408 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4409 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4410 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4411 };
4412 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4413 {
4414 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4415 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4416 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4417 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4418
4419 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4420 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4421 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4422 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4423
4424 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4425 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4426 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4427 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4428 };
4429 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4430 {
4431 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4432 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4433 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4434 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4435
4436 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4437 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4438 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4439 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4440
4441 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4442 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4443 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4444 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4445 { bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4446 { bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4447 };
4448 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4449 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4450 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4451 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
4452}
4453
4454
4455/*
4456 * [V]PSHUFHD
4457 */
4458BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp);
4459BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp);
4460BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp);
4461BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp);
4462
4463BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp);
4464BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp);
4465BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp);
4466BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp);
4467
4468BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp);
4469BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp);
4470BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp);
4471BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp);
4472extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64;
4473extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64;
4474
4475BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufd(uint8_t bMode)
4476{
4477 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
4478 {
4479 { RTUINT256_INIT_C(0, 0, 0, 0),
4480 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4481 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4482 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4483 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4484 /* => */ RTUINT256_INIT_C(0x5555666655556666, 0x5555666655556666, 0x1111222211112222, 0x1111222211112222) },
4485 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4486 /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x4d09f02a4d09f02a, 0xb4212fa8b4212fa8, 0xb4212fa8b4212fa8) },
4487 };
4488
4489 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
4490 {
4491 { RTUINT256_INIT_C(0, 0, 0, 0),
4492 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4493 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4494 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4495 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4496 /* => */ RTUINT256_INIT_C(0x3333444411112222, 0x7777888855556666, 0x7777888855556666, 0x3333444411112222) },
4497 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4498 /* => */ RTUINT256_INIT_C(0x666b3fe63ef417c8, 0x6cdc73d54d09f02a, 0x930996bb9c5ce073, 0x564c9ba2b4212fa8) },
4499 };
4500
4501 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4502 {
4503 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4504 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4505 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4506 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4507
4508 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4509 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4510 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4511 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4512
4513 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4514 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4515 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4516 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4517 };
4518 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4519 {
4520 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4521 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4522 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4523 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4524
4525 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4526 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4527 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4528 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4529
4530 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4531 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4532 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4533 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4534 };
4535 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4536 {
4537 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4538 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4539 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4540 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4541
4542 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4543 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4544 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4545 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4546
4547 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4548 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4549 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4550 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4551 { bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
4552 { bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B },
4553 };
4554 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4555 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4556 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4557 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
4558}
4559
4560
4561/**
4562 * Values shared by the move functions (same input as output).
4563 */
4564static BS3CPUINSTR3_TEST3_VALUES_T const g_aMoveValues3[] =
4565{
4566 { RTUINT256_INIT_C(0, 0, 0, 0),
4567 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4568 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
4569 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
4570 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
4571 /* => */ RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888) },
4572 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4573 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) },
4574};
4575
4576
4577/*
4578 * MOVNTDQA - load double qword, aligned, with non-temporal hint.
4579 */
4580BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp);
4581extern FNBS3FAR bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64;
4582BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp);
4583extern FNBS3FAR bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64;
4584BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp);
4585extern FNBS3FAR bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64;
4586
4587BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdqa(uint8_t bMode)
4588{
4589 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4590 {
4591 { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4592 { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4593 { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4594 };
4595 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4596 {
4597 { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4598 { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4599 { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4600 };
4601 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4602 {
4603 { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4604 { bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4605 { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4606 { bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4607 { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4608 { bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4609 };
4610 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4611 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4612 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4613 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
4614}
4615
4616
4617/*
4618 * MOVUPS - packed single-precision floating point, unaligned.
4619 *
4620 * Note! We only cover one of the two register<->register variants here
4621 * thanks to the assembler (probably the one with the smaller opcode).
4622 */
4623BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_XMM1_XMM2_icebp);
4624BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_XMM1_FSxBX_icebp);
4625extern FNBS3FAR bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64;
4626extern FNBS3FAR bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64;
4627BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_XMM1_XMM2_icebp);
4628BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp);
4629extern FNBS3FAR bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64;
4630extern FNBS3FAR bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64;
4631BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_YMM1_YMM2_icebp);
4632BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp);
4633extern FNBS3FAR bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64;
4634extern FNBS3FAR bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64;
4635
4636BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_FSxBX_XMM1_icebp);
4637extern FNBS3FAR bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64;
4638BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp);
4639extern FNBS3FAR bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64;
4640BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp);
4641extern FNBS3FAR bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64;
4642
4643BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movups(uint8_t bMode)
4644{
4645 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4646 {
4647 { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4648 { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4649 { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4650
4651 { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4652 { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4653 { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4654
4655 { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4656 { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4657 { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4658 };
4659 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4660 {
4661 { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4662 { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4663 { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4664
4665 { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4666 { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4667 { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4668
4669 { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4670 { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4671 { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4672 };
4673 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4674 {
4675 { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4676 { bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4677 { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4678 { bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4679 { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4680 { bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4681
4682 { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4683 { bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4684 { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4685 { bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4686 { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4687 { bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4688
4689 { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4690 { bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4691 { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4692 { bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4693 { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4694 { bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4695 };
4696 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4697 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4698 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4699 g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
4700}
4701
4702
4703/*
4704 * MOVUPD - packed double-precision floating point, unaligned.
4705 *
4706 * Note! We only cover one of the two register<->register variants here
4707 * thanks to the assembler (probably the one with the smaller opcode).
4708 */
4709BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_XMM1_XMM2_icebp);
4710BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_XMM1_FSxBX_icebp);
4711extern FNBS3FAR bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64;
4712extern FNBS3FAR bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64;
4713BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp);
4714BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp);
4715extern FNBS3FAR bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64;
4716extern FNBS3FAR bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64;
4717BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp);
4718BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp);
4719extern FNBS3FAR bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64;
4720extern FNBS3FAR bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64;
4721
4722BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_FSxBX_XMM1_icebp);
4723extern FNBS3FAR bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64;
4724BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp);
4725extern FNBS3FAR bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64;
4726BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp);
4727extern FNBS3FAR bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64;
4728
4729BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movupd(uint8_t bMode)
4730{
4731 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
4732 {
4733 { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4734 { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4735 { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4736
4737 { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4738 { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4739 { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4740
4741 { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4742 { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4743 { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4744 };
4745 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
4746 {
4747 { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4748 { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4749 { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4750
4751 { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4752 { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4753 { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4754
4755 { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4756 { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4757 { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4758 };
4759 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
4760 {
4761 { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4762 { bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4763 { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4764 { bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4765 { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4766 { bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4767
4768 { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4769 { bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4770 { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4771 { bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4772 { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4773 { bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4774
4775 { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4776 { bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4777 { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4778 { bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4779 { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4780 { bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
4781 };
4782 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4783 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4784 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4785 g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
4786}
4787
4788
4789/**
4790 * The 32-bit protected mode main function.
4791 *
4792 * The tests a driven by 32-bit test drivers, even for real-mode tests (though
4793 * we'll switch between PE32 and RM for each test step we perform). Given that
4794 * we test MMX, SSE and AVX here, we don't need to worry about 286 or 8086.
4795 *
4796 * Some extra steps needs to be taken to properly handle extended state in LM64
4797 * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode
4798 * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm).
4799 */
4800BS3_DECL(void) Main_pe32()
4801{
4802 static const BS3TESTMODEBYONEENTRY g_aTests[] =
4803 {
4804//#define ALL_TESTS
4805#if defined(ALL_TESTS)
4806 { "[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand, 0 },
4807 { "[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn, 0 },
4808 { "[v]orps/[v]orpd/[v]or", bs3CpuInstr3_v_orps_orpd_por, 0 },
4809 { "[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor, 0 },
4810#endif
4811#if defined(ALL_TESTS)
4812 { "[v]pcmpgtb/[v]pcmpgtw/[v]pcmpgtd/[v]pcmpgtq", bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq, 0 },
4813 { "[v]pcmpeqb/[v]pcmpeqw/[v]pcmpeqd/[v]pcmpeqq", bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq, 0 },
4814#endif
4815#if defined(ALL_TESTS)
4816 { "[v]paddb/[v]paddw/[v]paddd/[v]paddq", bs3CpuInstr3_v_paddb_paddw_paddd_paddq, 0 },
4817 { "[v]psubb/[v]psubw/[v]psubd/[v]psubq", bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 },
4818#endif
4819#if defined(ALL_TESTS)
4820 { "[v]pmovmskb", bs3CpuInstr3_v_pmovmskb, 0 },
4821 { "pshufb", bs3CpuInstr3_pshufb, 0 },
4822 { "pshufw", bs3CpuInstr3_pshufw, 0 },
4823 { "[v]pshufhw", bs3CpuInstr3_v_pshufhw, 0 },
4824 { "[v]pshuflw", bs3CpuInstr3_v_pshuflw, 0 },
4825 { "[v]pshufd", bs3CpuInstr3_v_pshufd, 0 },
4826#endif
4827#if defined(ALL_TESTS)
4828 { "[v]punpckhbw", bs3CpuInstr3_v_punpckhbw, 0 },
4829 { "[v]punpckhwd", bs3CpuInstr3_v_punpckhwd, 0 },
4830 { "[v]punpckhdq", bs3CpuInstr3_v_punpckhdq, 0 },
4831 { "[v]punpckhqdq", bs3CpuInstr3_v_punpckhqdq, 0 },
4832#endif
4833#if defined(ALL_TESTS)
4834 { "[v]punpcklbw", bs3CpuInstr3_v_punpcklbw, 0 },
4835 { "[v]punpcklwd", bs3CpuInstr3_v_punpcklwd, 0 },
4836 { "[v]punpckldq", bs3CpuInstr3_v_punpckldq, 0 },
4837 { "[v]punpcklqdq", bs3CpuInstr3_v_punpcklqdq, 0 },
4838#endif
4839#if defined(ALL_TESTS)
4840 { "[v]packsswb", bs3CpuInstr3_v_packsswb, 0 },
4841 { "[v]packssdw", bs3CpuInstr3_v_packssdw, 0 },
4842 { "[v]packuswb", bs3CpuInstr3_v_packuswb, 0 },
4843 { "[v]packusdw", bs3CpuInstr3_v_packusdw, 0 },
4844#endif
4845#if defined(ALL_TESTS)
4846 { "[v]movntdqa", bs3CpuInstr3_v_movntdqa, 0 },
4847 { "[v]movups", bs3CpuInstr3_v_movups, 0 },
4848 { "[v]movupd", bs3CpuInstr3_v_movupd, 0 },
4849 { "[v]movss", bs3CpuInstr3_v_movss, 0 },
4850 { "[v]movsd", bs3CpuInstr3_v_movsd, 0 },
4851 { "[v]movlps", bs3CpuInstr3_v_movlps, 0 },
4852#endif
4853 };
4854 Bs3TestInit("bs3-cpu-instr-3");
4855
4856 /*
4857 * Initialize globals.
4858 */
4859 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
4860 {
4861 uint32_t fEbx, fEcx, fEdx;
4862 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
4863 g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX);
4864 g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
4865 g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3);
4866 g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
4867 g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
4868 g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3);
4869 g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3);
4870 g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
4871 g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
4872 g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
4873 g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
4874
4875 if (ASMCpuId_EAX(0) >= 7)
4876 {
4877 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL);
4878 g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
4879 g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
4880 }
4881
4882 if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES)
4883 {
4884 ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
4885 g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4886 g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4887 g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4888 }
4889 g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE];
4890 }
4891
4892 /*
4893 * Allocate a buffer for testing.
4894 */
4895 g_cbBuf = X86_PAGE_SIZE * 4;
4896 g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf);
4897 if (g_pbBuf)
4898 {
4899 /*
4900 * Do the tests.
4901 */
4902 Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY);
4903 }
4904 else
4905 Bs3TestFailed("Failed to allocate 16K buffer");
4906
4907 Bs3TestTerm();
4908}
4909
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