VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32@ 96105

Last change on this file since 96105 was 96105, checked in by vboxsync, 3 years ago

ValidationKit/bs3-cpu-instr-3: Add simple [v]pmuludq instructions testcase, bugref:9898
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File size: 715.5 KB
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1/* $Id: bs3-cpu-instr-3.c32 96105 2022-08-08 09:10:34Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-instr-3 - MMX, SSE and AVX instructions, C code template.
4 */
5
6/*
7 * Copyright (C) 2007-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28/*********************************************************************************************************************************
29* Header Files *
30*********************************************************************************************************************************/
31#include <bs3kit.h>
32
33#include <iprt/asm.h>
34#include <iprt/asm-amd64-x86.h>
35
36
37/*********************************************************************************************************************************
38* Defined Constants And Macros *
39*********************************************************************************************************************************/
40#define BS3_FNBS3FAR_PROTOTYPES_CMN(a_BaseNm) \
41 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c16); \
42 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c32); \
43 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c64)
44
45
46/** Converts an execution mode (BS3_MODE_XXX) into an index into an array
47 * initialized by BS3CPUINSTR3_TEST1_MODES_INIT,
48 * BS3CPUINSTR3_TEST2_MODES_INIT, BS3CPUINSTR3_TEST3_MODES_INIT, ... . */
49#define BS3CPUINSTR3_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2)
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55/** Instruction set type and operand width. */
56typedef enum
57{
58 T_INVALID,
59 T_MMX,
60 T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */
61 T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */
62 T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */
63 T_AXMMX,
64 T_AXMMX_OR_SSE,
65 T_SSE,
66 T_128BITS = T_SSE,
67 T_SSE2,
68 T_SSE3,
69 T_SSSE3,
70 T_SSE4_1,
71 T_SSE4_2,
72 T_SSE4A,
73 T_AVX_128,
74 T_AVX2_128,
75 T_AVX_256,
76 T_256BITS = T_AVX_256,
77 T_AVX2_256,
78 T_MAX
79} INPUT_TYPE_T;
80
81/** Memory or register rm variant. */
82enum {
83 RM_REG = 0,
84 RM_MEM,
85 RM_MEM32, /**< Memory operand is 32 bits. Hack for movss and similar. */
86 RM_MEM64 /**< Memory operand is 64 bits. Hack for movss and similar. */
87};
88
89/**
90 * Execution environment configuration.
91 */
92typedef struct BS3CPUINSTR3_CONFIG_T
93{
94 uint16_t fCr0Mp : 1;
95 uint16_t fCr0Em : 1;
96 uint16_t fCr0Ts : 1;
97 uint16_t fCr4OsFxSR : 1;
98 uint16_t fCr4OsXSave : 1;
99 uint16_t fXcr0Sse : 1;
100 uint16_t fXcr0Avx : 1;
101 /** x87 exception pending (IE + something unmasked). */
102 uint16_t fX87XcptPending : 1;
103 /** Aligned memory operands. If zero, they will be misaligned and tests w/o memory ops skipped. */
104 uint16_t fAligned : 1;
105 uint16_t fAlignCheck : 1;
106 uint16_t fMxCsrMM : 1; /**< AMD only */
107 uint8_t bXcptMmx;
108 uint8_t bXcptSse;
109 uint8_t bXcptAvx;
110} BS3CPUINSTR3_CONFIG_T;
111/** Pointer to an execution environment configuration. */
112typedef BS3CPUINSTR3_CONFIG_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_T;
113
114/** State saved by bs3CpuInstr3ConfigReconfigure. */
115typedef struct BS3CPUINSTR3_CONFIG_SAVED_T
116{
117 uint32_t uCr0;
118 uint32_t uCr4;
119 uint32_t uEfl;
120 uint16_t uFcw;
121 uint16_t uFsw;
122 uint32_t uMxCsr;
123} BS3CPUINSTR3_CONFIG_SAVED_T;
124typedef BS3CPUINSTR3_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTR3_CONFIG_SAVED_T;
125typedef BS3CPUINSTR3_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_SAVED_T;
126
127
128/*********************************************************************************************************************************
129* Global Variables *
130*********************************************************************************************************************************/
131static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false };
132static bool g_fAmdMisalignedSse = false;
133
134/** Size of g_pbBuf - at least three pages. */
135static uint32_t g_cbBuf;
136/** Buffer of g_cbBuf size. */
137static uint8_t BS3_FAR *g_pbBuf;
138
139/** Exception type \#1 test configurations, 16 & 32 bytes strictly aligned. */
140static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig1[] =
141{
142/*
143 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
144 * +AVX +AMD/SSE
145 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
146 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
147 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
148 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
149 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
150 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
151 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
152 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
153 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
154 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
155 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
156 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
157 /* Memory misalignment and alignment checks: */
158 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_GP }, /* #10 */
159 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_GP }, /* #11 */
160 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
161 /* AMD only: */
162 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
163 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
164};
165
166/** Exception type \#4 test configurations, 16 & 32 byte not strictly aligned. */
167static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4[] =
168{
169/*
170 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
171 * +AVX +AMD/SSE
172 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
173 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
174 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
175 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
176 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
177 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
178 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
179 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
180 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
181 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
182 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
183 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
184 /* Memory misalignment and alignment checks: */
185 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
186 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_AC }, /* #11 */
187 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
188 /* AMD only: */
189 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */
190 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */
191};
192
193/** Exception type \#4 test configurations, for the SSE version of movups. */
194static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4Unaligned[] =
195{
196/*
197 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
198 * +AVX +AMD/SSE
199 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
200 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
201 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
202 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
203 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
204 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
205 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
206 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
207 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
208 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
209 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
210 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
211 /* Memory misalignment and alignment checks: */
212 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */
213 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_DB, X86_XCPT_AC }, /* #11 */
214 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
215 /* AMD only: */
216 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */
217 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */
218};
219
220/** Exception type \#5 test configurations, less than 16 byte operands. */
221static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig5[] =
222{
223/*
224 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to
225 * +AVX +AMD/SSE
226 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR
227 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */
228 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
229 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
230 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */
231 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */
232 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */
233 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */
234 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */
235 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
236 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
237 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */
238 /* Memory misalignment and alignment checks: */
239 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */
240 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */
241 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
242 /* AMD only: */
243 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */
244 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */
245};
246
247
248
249/**
250 * Reconfigures the execution environment according to @a pConfig.
251 *
252 * Call bs3CpuInstr3ConfigRestore to undo the changes.
253 *
254 * @returns true on success, false if the configuration cannot be applied. In
255 * the latter case, no context changes are made.
256 * @param pSavedCfg Where to save state we modify.
257 * @param pCtx The register context to modify.
258 * @param pExtCtx The extended register context to modify.
259 * @param pConfig The configuration to apply.
260 * @param bMode The target mode.
261 */
262static bool bs3CpuInstr3ConfigReconfigure(PBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx,
263 PCBS3CPUINSTR3_CONFIG_T pConfig, uint8_t bMode)
264{
265 /*
266 * Save context bits we may change here
267 */
268 pSavedCfg->uCr0 = pCtx->cr0.u32;
269 pSavedCfg->uCr4 = pCtx->cr4.u32;
270 pSavedCfg->uEfl = pCtx->rflags.u32;
271 pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx);
272 pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx);
273 pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx);
274
275 /*
276 * Can we make these changes?
277 */
278 if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse)
279 return false;
280
281 /* Currently we skip pending x87 exceptions in real mode as they cannot be
282 caught, given that we preserve the bios int10h. */
283 if (pConfig->fX87XcptPending && BS3_MODE_IS_RM_OR_V86(bMode))
284 return false;
285
286 /*
287 * Modify the test context.
288 */
289 if (pConfig->fCr0Mp)
290 pCtx->cr0.u32 |= X86_CR0_MP;
291 else
292 pCtx->cr0.u32 &= ~X86_CR0_MP;
293 if (pConfig->fCr0Em)
294 pCtx->cr0.u32 |= X86_CR0_EM;
295 else
296 pCtx->cr0.u32 &= ~X86_CR0_EM;
297 if (pConfig->fCr0Ts)
298 pCtx->cr0.u32 |= X86_CR0_TS;
299 else
300 pCtx->cr0.u32 &= ~X86_CR0_TS;
301
302 if (pConfig->fCr4OsFxSR)
303 pCtx->cr4.u32 |= X86_CR4_OSFXSR;
304 else
305 pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
306 /** @todo X86_CR4_OSXMMEEXCPT? */
307 if (pConfig->fCr4OsXSave)
308 pCtx->cr4.u32 |= X86_CR4_OSXSAVE;
309 else
310 pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE;
311
312 if (pConfig->fXcr0Sse)
313 pExtCtx->fXcr0Saved |= XSAVE_C_SSE;
314 else
315 pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE;
316 if (pConfig->fXcr0Avx)
317 pExtCtx->fXcr0Saved |= XSAVE_C_YMM;
318 else
319 pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM;
320
321 if (pConfig->fAlignCheck)
322 {
323 pCtx->rflags.u32 |= X86_EFL_AC;
324 pCtx->cr0.u32 |= X86_CR0_AM;
325 }
326 else
327 {
328 pCtx->rflags.u32 &= ~X86_EFL_AC;
329 pCtx->cr0.u32 &= ~X86_CR0_AM;
330 }
331
332 if (!pConfig->fX87XcptPending)
333 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B));
334 else
335 {
336 Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw & ~X86_FCW_ZM);
337 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw | X86_FSW_ZE | X86_FSW_ES | X86_FSW_B);
338 pCtx->cr0.u32 |= X86_CR0_NE;
339 }
340
341 if (pConfig->fMxCsrMM)
342 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM);
343 else
344 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM);
345 return true;
346}
347
348
349/**
350 * Undoes changes made by bs3CpuInstr3ConfigReconfigure.
351 */
352static void bs3CpuInstr3ConfigRestore(PCBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx)
353{
354 pCtx->cr0.u32 = pSavedCfg->uCr0;
355 pCtx->cr4.u32 = pSavedCfg->uCr4;
356 pCtx->rflags.u32 = pSavedCfg->uEfl;
357 pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal;
358 Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw);
359 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw);
360 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr);
361}
362
363
364/**
365 * Allocates two extended CPU contexts and initializes the first one
366 * with random data.
367 * @returns First extended context, initialized with randomish data. NULL on
368 * failure (complained).
369 * @param ppExtCtx2 Where to return the 2nd context.
370 */
371static PBS3EXTCTX bs3CpuInstr3AllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2)
372{
373 /* Allocate extended context structures. */
374 uint64_t fFlags;
375 uint16_t cb = Bs3ExtCtxGetSize(&fFlags);
376 PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2);
377 PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb);
378 if (pExtCtx1)
379 {
380 Bs3ExtCtxInit(pExtCtx1, cb, fFlags);
381 /** @todo populate with semi-random stuff. */
382
383 Bs3ExtCtxInit(pExtCtx2, cb, fFlags);
384 *ppExtCtx2 = pExtCtx2;
385 return pExtCtx1;
386 }
387 Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2);
388 *ppExtCtx2 = NULL;
389 return NULL;
390}
391
392static void bs3CpuInstr3FreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
393{
394 RT_NOREF_PV(pExtCtx2);
395 Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2);
396}
397
398/**
399 * Sets up SSE and maybe AVX.
400 */
401static void bs3CpuInstr3SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx)
402{
403 /* CR0: */
404 uint32_t cr0 = Bs3RegGetCr0();
405 cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
406 cr0 |= X86_CR0_NE;
407 Bs3RegSetCr0(cr0);
408
409 /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */
410 pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
411 pCtx->cr0.u32 |= X86_CR0_NE;
412
413 /* CR4: */
414 if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
415 {
416 uint32_t cr4 = Bs3RegGetCr4();
417 if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
418 {
419 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE;
420 Bs3RegSetCr4(cr4);
421 Bs3RegSetXcr0(pExtCtx->fXcr0Nominal);
422 }
423 else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
424 {
425 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT;
426 Bs3RegSetCr4(cr4);
427 }
428 pCtx->cr4.u32 = cr4;
429 }
430}
431
432
433
434/**
435 * Configures the buffer with electrict fences in paged modes.
436 *
437 * @returns Adjusted buffer pointer.
438 * @param pbBuf The buffer pointer.
439 * @param pcbBuf Pointer to the buffer size (input & output).
440 * @param bMode The testing target mode.
441 */
442DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstr3BufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode)
443{
444 if (BS3_MODE_IS_PAGED(bMode))
445 {
446 uint32_t cbBuf = *pcbBuf;
447 Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P);
448 Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P);
449 pbBuf += X86_PAGE_SIZE;
450 cbBuf -= X86_PAGE_SIZE * 2;
451 *pcbBuf = cbBuf;
452 }
453 return pbBuf;
454}
455
456
457/**
458 * Undoes what bs3CpuInstr3BufSetup did.
459 *
460 * @param pbBuf The buffer pointer.
461 * @param cbBuf The buffer size.
462 * @param bMode The testing target mode.
463 */
464DECLINLINE(void) bs3CpuInstr3BufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode)
465{
466 if (BS3_MODE_IS_PAGED(bMode))
467 {
468 Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0);
469 Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0);
470 }
471}
472
473
474/**
475 * Gets a buffer of a @a cbMemOp sized operand according to the given
476 * configuration and alignment restrictions.
477 *
478 * @returns Pointer to the buffer.
479 * @param pbBuf The buffer pointer.
480 * @param cbBuf The buffer size.
481 * @param cbMemOp The operand size.
482 * @param cbAlign The operand alignment restriction.
483 * @param pConfig The configuration.
484 */
485DECLINLINE(PRTUINT256U) bs3CpuInstr3BufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign,
486 PCBS3CPUINSTR3_CONFIG_T pConfig)
487{
488 if (pConfig->fAligned)
489 {
490 if (!pConfig->fAlignCheck)
491 return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp];
492 return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - cbAlign];
493 }
494 return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - 1];
495}
496
497
498/**
499 * Determins the size of memory operands.
500 */
501DECLINLINE(uint8_t) bs3CpuInstr3MemOpSize(uint8_t cbOperand, uint8_t enmRm)
502{
503 if (enmRm <= RM_MEM)
504 return cbOperand;
505 if (enmRm == RM_MEM32)
506 return sizeof(uint32_t);
507 if (enmRm == RM_MEM64)
508 return sizeof(uint64_t);
509 BS3_ASSERT(0);
510 return cbOperand;
511}
512
513
514/*
515 * Test type #1.
516 */
517
518typedef struct BS3CPUINSTR3_TEST1_VALUES_T
519{
520 RTUINT256U uSrc2;
521 RTUINT256U uSrc1; /**< uDstIn for MMX & SSE */
522 RTUINT256U uDstOut;
523} BS3CPUINSTR3_TEST1_VALUES_T;
524
525typedef struct BS3CPUINSTR3_TEST1_T
526{
527 FPFNBS3FAR pfnWorker;
528 uint8_t bAvxMisalignXcpt;
529 uint8_t enmRm;
530 uint8_t enmType;
531 uint8_t iRegDst;
532 uint8_t iRegSrc1;
533 uint8_t iRegSrc2;
534 uint8_t cValues;
535 BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues;
536} BS3CPUINSTR3_TEST1_T;
537
538typedef struct BS3CPUINSTR3_TEST1_MODE_T
539{
540 BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests;
541 unsigned cTests;
542} BS3CPUINSTR3_TEST1_MODE_T;
543
544/** Initializer for a BS3CPUINSTR3_TEST1_MODE_T array (three entries). */
545#define BS3CPUINSTR3_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
546 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
547
548
549/**
550 * Test type #1 worker.
551 */
552static uint8_t bs3CpuInstr3_WorkerTestType1(uint8_t bMode, BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests, unsigned cTests,
553 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs)
554{
555 BS3REGCTX Ctx;
556 BS3TRAPFRAME TrapFrame;
557 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
558 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
559 uint8_t BS3_FAR *pbBuf = g_pbBuf;
560 uint32_t cbBuf = g_cbBuf;
561 PBS3EXTCTX pExtCtxOut;
562 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
563 if (!pExtCtx)
564 return 0;
565
566 /* Ensure the structures are allocated before we sample the stack pointer. */
567 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
568 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
569
570 /*
571 * Create test context.
572 */
573 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
574 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
575 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
576 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]);
577
578 /*
579 * Run the tests in all rings since alignment issues may behave
580 * differently in ring-3 compared to ring-0.
581 */
582 for (;;)
583 {
584 unsigned iCfg;
585 for (iCfg = 0; iCfg < cConfigs; iCfg++)
586 {
587 unsigned iTest;
588 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
589 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
590 continue; /* unsupported config */
591
592 /*
593 * Iterate the tests.
594 */
595 for (iTest = 0; iTest < cTests; iTest++)
596 {
597 BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
598 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
599 unsigned const cValues = paTests[iTest].cValues;
600 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
601 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
602 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
603 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
604 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
605 uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm);
606 uint8_t const cbAlign = cbMemOp;
607 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
608 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD
609 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
610 : fSseInstr ? paConfigs[iCfg].bXcptSse
611 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
612 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
613 unsigned iVal;
614
615 /* If testing unaligned memory accesses, skip register-only tests. This allows
616 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
617 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
618 continue;
619
620 /* #AC is only raised in ring-3.: */
621 if (bXcptExpect == X86_XCPT_AC)
622 {
623 if (bRing != 3)
624 bXcptExpect = X86_XCPT_DB;
625 else if (fAvxInstr)
626 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
627 }
628
629 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
630
631 /*
632 * Iterate the test values and do the actual testing.
633 */
634 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
635 {
636 uint16_t cErrors;
637 uint16_t uSavedFtw = 0xff;
638 RTUINT256U uMemOpExpect;
639
640 /*
641 * Set up the context and some expectations.
642 */
643 /* dest */
644 if (paTests[iTest].iRegDst == UINT8_MAX)
645 {
646 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
647 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
648 if (bXcptExpect == X86_XCPT_DB)
649 uMemOpExpect = paValues[iVal].uDstOut;
650 else
651 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
652 }
653 else if (fMmxInstr)
654 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
655
656 /* source #1 (/ destination for MMX and SSE) */
657 if (paTests[iTest].iRegSrc1 == UINT8_MAX)
658 {
659 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
660 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp);
661 if (paTests[iTest].iRegDst == UINT8_MAX)
662 BS3_ASSERT(fSseInstr);
663 else
664 uMemOpExpect = paValues[iVal].uSrc1;
665 }
666 else if (fMmxInstr)
667 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
668 else if (fSseInstr)
669 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0);
670 else
671 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32);
672
673 /* source #2 */
674 if (paTests[iTest].iRegSrc2 == UINT8_MAX)
675 {
676 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
677 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX);
678 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp);
679 uMemOpExpect = paValues[iVal].uSrc2;
680 }
681 else if (fMmxInstr)
682 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
683 else if (fSseInstr)
684 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0);
685 else
686 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32);
687
688 /* Memory pointer. */
689 if (paTests[iTest].enmRm >= RM_MEM)
690 {
691 BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX
692 || paTests[iTest].iRegSrc1 == UINT8_MAX
693 || paTests[iTest].iRegSrc2 == UINT8_MAX);
694 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
695 }
696
697 /*
698 * Execute.
699 */
700 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
701
702 /*
703 * Check the result:
704 */
705 cErrors = Bs3TestSubErrorCount();
706
707 if (fMmxInstr && bXcptExpect == X86_XCPT_DB)
708 {
709 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
710 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */
711 }
712 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX)
713 {
714 if (fMmxInstr)
715 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET);
716 else if (fSseInstr)
717 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0);
718 else
719 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand);
720 }
721 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
722
723 if (TrapFrame.bXcpt != bXcptExpect)
724 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
725
726 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
727 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
728 {
729 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
730 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
731 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
732 }
733 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
734 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
735 pszMode, idTestStep);
736
737 if ( paTests[iTest].enmRm >= RM_MEM
738 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
739 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
740
741 if (cErrors != Bs3TestSubErrorCount())
742 {
743 if (paConfigs[iCfg].fAligned)
744 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
745 bRing, iCfg, iTest, iVal, bXcptExpect);
746 else
747 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
748 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
749 Bs3TestPrintf("\n");
750 }
751
752 if (uSavedFtw != 0xff)
753 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
754 }
755 }
756
757 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
758 }
759
760 /*
761 * Next ring.
762 */
763 bRing++;
764 if (bRing > 3 || bMode == BS3_MODE_RM)
765 break;
766 Bs3RegCtxConvertToRingX(&Ctx, bRing);
767 }
768
769 /*
770 * Cleanup.
771 */
772 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
773 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
774 return 0;
775}
776
777
778/*
779 * PAND, VPAND, ANDPS, VANDPS, ANDPD, VANDPD.
780 */
781BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_MM2_icebp);
782BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_FSxBX_icebp);
783BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_XMM2_icebp);
784BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_FSxBX_icebp);
785BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp);
786BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp);
787BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp);
788BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp);
789
790BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_XMM2_icebp);
791BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_FSxBX_icebp);
792BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp);
793BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp);
794BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp);
795BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp);
796
797BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_XMM2_icebp);
798BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_FSxBX_icebp);
799BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp);
800BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp);
801BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp);
802BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp);
803extern FNBS3FAR bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64;
804
805BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andps_andpd_pand(uint8_t bMode)
806{
807 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
808 {
809 { RTUINT256_INIT_C(0, 0, 0, 0),
810 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
811 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
812 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
813 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
814 /* = */ RTUINT256_INIT_C(0x5555666677770000, 0x1111222233334444, 0x1111222233334444, 0x5555666677770000) },
815 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
816 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
817 /* = */ RTUINT256_INIT_C(0x0c09d02808403294, 0x385406c840621622, 0x8000290816080282, 0x0050c020030090b9) },
818 };
819
820 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
821 {
822 { bs3CpuInstr3_pand_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
823 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
824 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
825 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
826 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
827 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
828 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
829 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
830
831 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
832 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
833 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
834 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
835 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
836 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
837
838 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
839 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
840 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
841 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
842 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
843 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
844 };
845 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
846 {
847 { bs3CpuInstr3_pand_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
848 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
849 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
850 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
851 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
852 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
853 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
854 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
855
856 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
857 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
858 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
859 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
860 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
861 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
862
863 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
864 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
865 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
866 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
867 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
868 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
869 };
870 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
871 {
872 { bs3CpuInstr3_pand_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
873 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
874 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
875 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
876 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
877 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
878 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
879 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
880
881 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
882 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
883 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
884 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
885 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
886 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
887
888 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
889 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
890 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
891 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
892 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
893 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
894 { bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
895 };
896
897 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
898 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
899 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
900 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
901}
902
903
904/*
905 * PANDN, VPANDN, ANDNPS, VANDNPS, ANDNPD, VANDNPD.
906 */
907BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_MM2_icebp);
908BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_FSxBX_icebp);
909BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_XMM2_icebp);
910BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_FSxBX_icebp);
911BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp);
912BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp);
913BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp);
914BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp);
915
916BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_XMM2_icebp);
917BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_FSxBX_icebp);
918BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp);
919BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp);
920BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp);
921BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp);
922
923BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_XMM2_icebp);
924BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp);
925BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp);
926BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp);
927BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp);
928BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp);
929extern FNBS3FAR bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64;
930
931BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andnps_andnpd_pandn(uint8_t bMode)
932{
933 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
934 {
935 { RTUINT256_INIT_C(0, 0, 0, 0),
936 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
937 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
938 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
939 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
940 /* = */ RTUINT256_INIT_C(0x0000000000008888, 0x0000000000000000, 0x0000000000000000, 0x0000000000008888) },
941 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
942 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
943 /* = */ RTUINT256_INIT_C(0x41002002649c4141, 0x06a01100260929c4, 0x342106a040449920, 0x9c0c205390090602) },
944 };
945
946 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
947 {
948 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
949 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
950 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
951 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
952 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
953 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
954 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
955 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
956
957 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
958 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
959 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
960 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
961 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
962 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
963
964 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
965 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
966 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
967 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
968 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
969 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
970 };
971 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
972 {
973 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
974 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
975 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
976 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
977 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
978 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
979 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
980 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
981
982 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
983 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
984 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
985 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
986 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
987 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
988
989 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
990 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
991 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
992 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
993 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
994 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
995 };
996 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
997 {
998 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
999 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1000 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1001 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1002 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1003 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1004 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1005 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1006
1007 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1008 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1009 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1010 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1011 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1012 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1013
1014 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1015 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1016 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1017 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1018 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1019 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1020 { bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
1021 };
1022
1023 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1024 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1025 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1026 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1027}
1028
1029
1030
1031/*
1032 * POR, VPOR, PORPS, VORPS, PORPD, VPORPD.
1033 */
1034BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_MM2_icebp);
1035BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_FSxBX_icebp);
1036BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_XMM2_icebp);
1037BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_FSxBX_icebp);
1038BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp);
1039BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp);
1040BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp);
1041BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp);
1042
1043BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_XMM2_icebp);
1044BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_FSxBX_icebp);
1045BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp);
1046BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp);
1047BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp);
1048BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp);
1049
1050BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_XMM2_icebp);
1051BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_FSxBX_icebp);
1052BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp);
1053BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp);
1054BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp);
1055BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp);
1056extern FNBS3FAR bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64;
1057
1058BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_orps_orpd_por(uint8_t bMode)
1059{
1060 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
1061 {
1062 { RTUINT256_INIT_C(0, 0, 0, 0),
1063 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
1064 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1065 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1066 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1067 /* = */ RTUINT256_INIT_C(0xddddeeeeffff8888, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff8888) },
1068 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1069 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1070 /* = */ RTUINT256_INIT_C(0x5fddfdae6dff73d5, 0xfffc9fec667b7ff7, 0xbc21effbffddfbe3, 0xdfdfedf3b38d9fff) },
1071 };
1072
1073 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1074 {
1075 { bs3CpuInstr3_por_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1076 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1077 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1078 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1079 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1080 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1081 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1082 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1083
1084 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1085 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1086 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1087 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1088 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1089 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1090
1091 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1092 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1093 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1094 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1095 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1096 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1097 };
1098 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1099 {
1100 { bs3CpuInstr3_por_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1101 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1102 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1103 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1104 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1105 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1106 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1107 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1108
1109 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1110 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1111 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1112 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1113 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1114 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1115
1116 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1117 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1118 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1119 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1120 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1121 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1122 };
1123 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1124 {
1125 { bs3CpuInstr3_por_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1126 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1127 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1128 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1129 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1130 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1131 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1132 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1133
1134 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1135 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1136 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1137 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1138 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1139 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1140
1141 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1142 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1143 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1144 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1145 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1146 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1147 { bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
1148 };
1149 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1150 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1151 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1152 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1153}
1154
1155
1156/*
1157 * PXOR, VPXOR, XORPS, VXORPS, XORPD, VXORPD.
1158 */
1159BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_MM2_icebp);
1160BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_FSxBX_icebp);
1161BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_XMM1_XMM2_icebp);
1162BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_XMM1_FSxBX_icebp);
1163BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp);
1164BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp);
1165BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp);
1166BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp);
1167
1168BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorps_XMM1_XMM2_icebp);
1169BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorps_XMM1_FSxBX_icebp);
1170BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp);
1171BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp);
1172BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp);
1173BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp);
1174
1175BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorpd_XMM1_XMM2_icebp);
1176BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp);
1177BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp);
1178BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp);
1179BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp);
1180BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp);
1181extern FNBS3FAR bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64;
1182
1183BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_xorps_xorpd_pxor(uint8_t bMode)
1184{
1185 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
1186 {
1187 { RTUINT256_INIT_C(0, 0, 0, 0),
1188 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0),
1189 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1190 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1191 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1192 /* = */ RTUINT256_INIT_C(0x8888888888888888, 0x8888888888888888, 0x8888888888888888, 0x8888888888888888) },
1193 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1194 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1195 /* = */ RTUINT256_INIT_C(0x53d42d8665bf4141, 0xc7a89924261969d5, 0x3c21c6f3e9d5f961, 0xdf8f2dd3b08d0f46) },
1196 };
1197
1198 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1199 {
1200 { bs3CpuInstr3_pxor_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1201 { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1202 { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1203 { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1204 { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1205 { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1206 { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1207 { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1208
1209 { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1210 { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1211 { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1212 { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1213 { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1214 { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1215
1216 { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1217 { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1218 { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1219 { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1220 { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1221 { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1222 };
1223 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1224 {
1225 { bs3CpuInstr3_pxor_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1226 { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1227 { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1228 { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1229 { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1230 { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1231 { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1232 { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1233
1234 { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1235 { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1236 { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1237 { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1238 { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1239 { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1240
1241 { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1242 { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1243 { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1244 { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1245 { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1246 { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1247 };
1248 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1249 {
1250 { bs3CpuInstr3_pxor_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1251 { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1252 { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1253 { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1254 { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1255 { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1256 { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
1257 { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
1258
1259 { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1260 { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1261 { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1262 { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1263 { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1264 { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1265
1266 { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
1267 { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1268 { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1269 { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1270 { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues },
1271 { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
1272 { bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues },
1273 };
1274 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1275 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1276 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1277 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1278}
1279
1280
1281
1282/*
1283 * PCMPGTB, VPCMPGTB, PCMPGTW, VPCMPGTW, PCMPGTD, VPCMPGTD, PCMPGTQ, VPCMPGTQ.
1284 */
1285BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp);
1286BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp);
1287BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp);
1288BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp);
1289BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp);
1290BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp);
1291BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp);
1292BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp);
1293
1294BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp);
1295BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp);
1296BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp);
1297BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp);
1298BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp);
1299BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp);
1300BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp);
1301BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp);
1302
1303BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp);
1304BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp);
1305BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp);
1306BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp);
1307BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp);
1308BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp);
1309BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp);
1310BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp);
1311extern FNBS3FAR bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64;
1312
1313BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp);
1314BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp);
1315BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp);
1316BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp);
1317BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp);
1318BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp);
1319extern FNBS3FAR bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64;
1320
1321BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq(uint8_t bMode)
1322{
1323 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1324 {
1325 { RTUINT256_INIT_C(0, 0, 0, 0),
1326 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1327 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1328 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1329 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1330 /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) },
1331 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1332 /* < */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1333 /* = */ RTUINT256_INIT_C(0x0000000000ff0000, 0x00ff00ff00ffffff, 0x000000ff0000ffff, 0xff000000ff00ffff) },
1334 };
1335
1336 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1337 {
1338 { RTUINT256_INIT_C(0, 0, 0, 0),
1339 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1340 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1341 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1342 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1343 /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) },
1344 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1345 /* ^ */ RTUINT256_INIT_C(0x1eddddac77733294, 0xf95c8eec40725633, 0x3333e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st and 3rd value */
1346 /* = */ RTUINT256_INIT_C(0x00000000ffff0000, 0x000000000000ffff, 0xffff00000000ffff, 0xffff0000ffffffff) },
1347 };
1348
1349 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1350 {
1351 { RTUINT256_INIT_C(0, 0, 0, 0),
1352 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1353 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1354 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1355 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1356 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1357 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1358 /* < */ RTUINT256_INIT_C(0x555dddac09633294, 0xf95c8eec77725633, 0x7770e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st, 2nd and 3rd value */
1359 /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0xffffffffffffffff) },
1360 };
1361
1362 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
1363 {
1364 { RTUINT256_INIT_C(0, 0, 0, 0),
1365 /* < */ RTUINT256_INIT_C(0, 0, 0, 0),
1366 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1367 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1368 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1369 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1370 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1371 /* < */ RTUINT256_INIT_C(0x77ddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st value */
1372 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff) },
1373 };
1374
1375 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1376 {
1377 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1378 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1379 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1380 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1381 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1382 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1383 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1384 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1385
1386 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1387 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1388 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1389 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1390 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1391 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1392 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1393 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1394
1395 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1396 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1397 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1398 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1399 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1400 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1401 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1402 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1403
1404 { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1405 { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1406 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1407 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1408 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1409 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1410 };
1411 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1412 {
1413 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1414 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1415 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1416 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1417 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1418 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1419 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1420 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1421
1422 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1423 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1424 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1425 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1426 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1427 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1428 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1429 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1430
1431 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1432 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1433 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1434 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1435 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1436 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1437 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1438 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1439
1440 { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1441 { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1442 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1443 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1444 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1445 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1446 };
1447 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1448 {
1449 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1450 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1451 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1452 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1453 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1454 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1455 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1456 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1457
1458 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1459 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1460 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1461 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1462 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1463 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1464 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1465 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1466
1467 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1468 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1469 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1470 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1471 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1472 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1473 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1474 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1475 { bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1476
1477 { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1478 { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1479 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1480 { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1481 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1482 { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1483 { bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesQ },
1484 };
1485 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1486 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1487 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1488 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1489}
1490
1491
1492/*
1493 * PCMPEQB, VPCMPEQB, PCMPEQW, VPCMPEQW, PCMPEQD, VPCMPEQD, PCMPEQQ, VPCMPEQQ.
1494 */
1495BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp);
1496BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp);
1497BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp);
1498BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp);
1499BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp);
1500BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp);
1501BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp);
1502BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp);
1503
1504BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp);
1505BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp);
1506BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp);
1507BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp);
1508BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp);
1509BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp);
1510BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp);
1511BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp);
1512
1513BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp);
1514BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp);
1515BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp);
1516BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp);
1517BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp);
1518BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp);
1519BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp);
1520BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp);
1521extern FNBS3FAR bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64;
1522
1523BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp);
1524BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp);
1525BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp);
1526BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp);
1527BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp);
1528BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp);
1529extern FNBS3FAR bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64;
1530
1531BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq(uint8_t bMode)
1532{
1533 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1534 {
1535 { RTUINT256_INIT_C(0, 0, 0, 0),
1536 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1537 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1538 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1539 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1540 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1541 { RTUINT256_INIT_C(0x4dddf02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1542 /* ==*/ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf95c17ec667256e6, 0xb400e95bbf999bc3, 0x9cd3cda0230999fd), /* modified all to get some matches */
1543 /* = */ RTUINT256_INIT_C(0x00ff000000ff0000, 0x0000ff00ff0000ff, 0xff0000000000ff00, 0xff00000000ff0000) },
1544 };
1545
1546 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1547 {
1548 { RTUINT256_INIT_C(0, 0, 0, 0),
1549 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1550 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1551 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1552 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1553 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1554 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1555 /* ==*/ RTUINT256_INIT_C(0x1eddf02a6cdc3294, 0x3ef48eec666b5633, 0x88002fa8bf999ba2, 0x9c5ccda0238496bb), /* modified all to get some matches */
1556 /* = */ RTUINT256_INIT_C(0x0000ffffffff0000, 0xffff0000ffff0000, 0x0000ffff0000ffff, 0xffff00000000ffff) },
1557 };
1558
1559 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1560 {
1561 { RTUINT256_INIT_C(0, 0, 0, 0),
1562 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1563 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1564 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1565 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1566 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1567 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1568 /* ==*/ RTUINT256_INIT_C(0x4d09f02a09633294, 0x3ef417c8666b3fe6, 0x8800e95b564c9ba2, 0x9c5ce073238499fd), /* modified all to get some matches */
1569 /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0xffffffffffffffff, 0x00000000ffffffff, 0xffffffff00000000) },
1570 };
1571
1572 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
1573 {
1574 { RTUINT256_INIT_C(0, 0, 0, 0),
1575 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0),
1576 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
1577 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1578 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1579 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
1580 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1581 /* ==*/ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd), /* modified 2nd and 3rd to get some matches */
1582 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000000) },
1583 };
1584
1585 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1586 {
1587 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1588 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1589 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1590 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1591 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1592 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1593 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1594 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1595
1596 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1597 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1598 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1599 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1600 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1601 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1602 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1603 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1604
1605 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1606 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1607 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1608 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1609 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1610 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1611 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1612 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1613
1614 { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1615 { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1616 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1617 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1618 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1619 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1620 };
1621 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1622 {
1623 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1624 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1625 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1626 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1627 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1628 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1629 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1630 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1631
1632 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1633 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1634 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1635 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1636 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1637 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1638 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1639 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1640
1641 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1642 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1643 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1644 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1645 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1646 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1647 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1648 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1649
1650 { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1651 { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1652 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1653 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1654 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1655 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1656 };
1657 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1658 {
1659 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1660 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1661 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1662 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1663 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1664 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1665 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1666 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1667
1668 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1669 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1670 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1671 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1672 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1673 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1674 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1675 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1676
1677 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1678 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1679 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1680 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1681 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1682 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1683 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1684 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1685 { bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1686
1687 { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1688 { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1689 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1690 { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1691 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1692 { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1693 { bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1694 };
1695 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1696 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1697 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1698 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1699}
1700
1701
1702/*
1703 * PADDB, VPADDB, PADDW, VPADDW, PADDD, VPADDD, PADDQ, VPADDQ.
1704 */
1705BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_MM1_MM2_icebp);
1706BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_MM1_FSxBX_icebp);
1707BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_XMM1_XMM2_icebp);
1708BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_XMM1_FSxBX_icebp);
1709BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp);
1710BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp);
1711BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp);
1712BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp);
1713
1714BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_MM1_MM2_icebp);
1715BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_MM1_FSxBX_icebp);
1716BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_XMM1_XMM2_icebp);
1717BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_XMM1_FSxBX_icebp);
1718BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp);
1719BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp);
1720BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp);
1721BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp);
1722
1723BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_MM1_MM2_icebp);
1724BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_MM1_FSxBX_icebp);
1725BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_XMM1_XMM2_icebp);
1726BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_XMM1_FSxBX_icebp);
1727BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp);
1728BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp);
1729BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp);
1730BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp);
1731extern FNBS3FAR bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64;
1732
1733BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_MM1_MM2_icebp);
1734BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_MM1_FSxBX_icebp);
1735BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_XMM1_XMM2_icebp);
1736BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_XMM1_FSxBX_icebp);
1737BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp);
1738BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp);
1739BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp);
1740BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp);
1741extern FNBS3FAR bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64;
1742
1743BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_paddb_paddw_paddd_paddq(uint8_t bMode)
1744{
1745 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1746 {
1747 { RTUINT256_INIT_C(0, 0, 0, 0),
1748 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1749 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1750 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1751 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1752 /* = */ RTUINT256_INIT_C(0x3232545476768888, 0xaaaacccceeee1010, 0xaaaacccceeee1010, 0x3232545476768888) },
1753 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1754 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1755 /* = */ RTUINT256_INIT_C(0x6be6cdd6753fa569, 0x3750a5b4a6dd9519, 0x3c21180315e5fd65, 0xdf2fad13b68d2fb8) },
1756 };
1757
1758 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1759 {
1760 { RTUINT256_INIT_C(0, 0, 0, 0),
1761 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1762 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1763 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1764 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1765 /* = */ RTUINT256_INIT_C(0x3332555477768888, 0xaaaacccceeee1110, 0xaaaacccceeee1110, 0x3332555477768888) },
1766 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1767 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1768 /* = */ RTUINT256_INIT_C(0x6be6cdd6763fA669, 0x3850A6B4A6DD9619, 0x3C21190315E5FE65, 0xE02FAE13B68D30B8) },
1769 };
1770
1771 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1772 {
1773 { RTUINT256_INIT_C(0, 0, 0, 0),
1774 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1775 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1776 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1777 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1778 /* = */ RTUINT256_INIT_C(0x3333555477768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555477768888) },
1779 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1780 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1781 /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190315E5FE65, 0xE030AE13B68E30B8) },
1782 };
1783
1784 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
1785 {
1786 { RTUINT256_INIT_C(0, 0, 0, 0),
1787 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1788 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1789 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1790 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1791 /* = */ RTUINT256_INIT_C(0x3333555577768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555577768888) },
1792 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1793 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1794 /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190415E5FE65, 0xE030AE13B68E30B8) },
1795 };
1796
1797 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
1798 {
1799 { bs3CpuInstr3_paddb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1800 { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1801 { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1802 { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1803 { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1804 { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1805 { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1806 { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1807
1808 { bs3CpuInstr3_paddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1809 { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1810 { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1811 { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1812 { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1813 { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1814 { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1815 { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1816
1817 { bs3CpuInstr3_paddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1818 { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1819 { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1820 { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1821 { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1822 { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1823 { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1824 { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1825
1826 { bs3CpuInstr3_paddq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1827 { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1828 { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1829 { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1830 { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1831 { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1832 { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1833 { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1834 };
1835 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
1836 {
1837 { bs3CpuInstr3_paddb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1838 { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1839 { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1840 { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1841 { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1842 { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1843 { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1844 { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1845
1846 { bs3CpuInstr3_paddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1847 { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1848 { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1849 { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1850 { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1851 { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1852 { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1853 { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1854
1855 { bs3CpuInstr3_paddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1856 { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1857 { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1858 { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1859 { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1860 { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1861 { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1862 { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1863
1864 { bs3CpuInstr3_paddq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1865 { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1866 { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1867 { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1868 { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1869 { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1870 { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1871 { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1872 };
1873 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
1874 {
1875 { bs3CpuInstr3_paddb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1876 { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1877 { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1878 { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1879 { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1880 { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1881 { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1882 { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
1883
1884 { bs3CpuInstr3_paddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1885 { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1886 { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1887 { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1888 { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1889 { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1890 { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1891 { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
1892
1893 { bs3CpuInstr3_paddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1894 { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1895 { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1896 { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1897 { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1898 { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1899 { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1900 { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1901 { bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
1902
1903 { bs3CpuInstr3_paddq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1904 { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1905 { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1906 { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1907 { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1908 { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1909 { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1910 { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1911 { bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
1912 };
1913 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1914 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
1915 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1916 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
1917}
1918
1919
1920/*
1921 * PSUBB, VPSUBB, PSUBW, VPSUBW, PSUBD, VPSUBD, PSUBQ, VPSUBQ.
1922 */
1923BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_MM1_MM2_icebp);
1924BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_MM1_FSxBX_icebp);
1925BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_XMM1_XMM2_icebp);
1926BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_XMM1_FSxBX_icebp);
1927BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp);
1928BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp);
1929BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp);
1930BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp);
1931
1932BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_MM1_MM2_icebp);
1933BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_MM1_FSxBX_icebp);
1934BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_XMM1_XMM2_icebp);
1935BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_XMM1_FSxBX_icebp);
1936BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp);
1937BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp);
1938BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp);
1939BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp);
1940
1941BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_MM1_MM2_icebp);
1942BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_MM1_FSxBX_icebp);
1943BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_XMM1_XMM2_icebp);
1944BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_XMM1_FSxBX_icebp);
1945BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp);
1946BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp);
1947BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp);
1948BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp);
1949extern FNBS3FAR bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64;
1950
1951BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_MM1_MM2_icebp);
1952BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_MM1_FSxBX_icebp);
1953BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_XMM1_XMM2_icebp);
1954BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_XMM1_FSxBX_icebp);
1955BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp);
1956BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp);
1957BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp);
1958BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp);
1959extern FNBS3FAR bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64;
1960
1961BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psubb_psubw_psubd_psubq(uint8_t bMode)
1962{
1963 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
1964 {
1965 { RTUINT256_INIT_C(0, 0, 0, 0),
1966 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1967 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1968 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1969 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1970 /* = */ RTUINT256_INIT_C(0x8888888888887878, 0x8888888888888888, 0x8888888888888888, 0x8888888888887878) },
1971 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1972 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1973 /* = */ RTUINT256_INIT_C(0xd1d4ed829d87bfbf, 0xbb687724da07174d, 0xd4dfbab3694dc721, 0xa777ed2d907b0342) },
1974 };
1975
1976 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
1977 {
1978 { RTUINT256_INIT_C(0, 0, 0, 0),
1979 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1980 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1981 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1982 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1983 /* = */ RTUINT256_INIT_C(0x8888888888887778, 0x8888888888888888, 0x8888888888888888, 0x8888888888887778) },
1984 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1985 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1986 /* = */ RTUINT256_INIT_C(0xd1d4ed829c87bebf, 0xba687724da07164d, 0xd3dfb9b3694dc721, 0xa777ed2d907b0342) },
1987 };
1988
1989 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
1990 {
1991 { RTUINT256_INIT_C(0, 0, 0, 0),
1992 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
1993 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
1994 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
1995 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
1996 /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) },
1997 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
1998 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
1999 /* = */ RTUINT256_INIT_C(0xd1d3ed829c86bebf, 0xba687724da07164d, 0xd3dfb9b3694cc721, 0xa776ed2d907b0342) },
2000 };
2001
2002 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] =
2003 {
2004 { RTUINT256_INIT_C(0, 0, 0, 0),
2005 /* + */ RTUINT256_INIT_C(0, 0, 0, 0),
2006 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
2007 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2008 /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2009 /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) },
2010 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2011 /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2012 /* = */ RTUINT256_INIT_C(0xd1d3ed819c86bebf, 0xba687723da07164d, 0xd3dfb9b3694cc721, 0xa776ed2c907b0342) },
2013 };
2014
2015 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2016 {
2017 { bs3CpuInstr3_psubb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2018 { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2019 { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2020 { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2021 { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2022 { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2023 { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2024 { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2025
2026 { bs3CpuInstr3_psubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2027 { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2028 { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2029 { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2030 { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2031 { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2032 { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2033 { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2034
2035 { bs3CpuInstr3_psubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2036 { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2037 { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2038 { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2039 { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2040 { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2041 { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2042 { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2043
2044 { bs3CpuInstr3_psubq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2045 { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2046 { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2047 { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2048 { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2049 { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2050 { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2051 { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2052 };
2053 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2054 {
2055 { bs3CpuInstr3_psubb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2056 { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2057 { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2058 { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2059 { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2060 { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2061 { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2062 { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2063
2064 { bs3CpuInstr3_psubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2065 { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2066 { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2067 { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2068 { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2069 { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2070 { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2071 { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2072
2073 { bs3CpuInstr3_psubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2074 { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2075 { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2076 { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2077 { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2078 { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2079 { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2080 { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2081
2082 { bs3CpuInstr3_psubq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2083 { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2084 { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2085 { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2086 { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2087 { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2088 { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2089 { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2090 };
2091 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2092 {
2093 { bs3CpuInstr3_psubb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2094 { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2095 { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2096 { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2097 { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2098 { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2099 { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2100 { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
2101
2102 { bs3CpuInstr3_psubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2103 { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2104 { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2105 { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2106 { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2107 { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2108 { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2109 { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2110
2111 { bs3CpuInstr3_psubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2112 { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2113 { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2114 { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2115 { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2116 { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2117 { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2118 { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2119 { bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2120
2121 { bs3CpuInstr3_psubq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2122 { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2123 { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2124 { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2125 { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2126 { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2127 { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2128 { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2129 { bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
2130 };
2131 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2132 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2133 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2134 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2135}
2136
2137
2138/*
2139 * PMULLW, VPMULLW, PMULLD, VPMULLD.
2140 */
2141BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_MM1_MM2_icebp);
2142BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_MM1_FSxBX_icebp);
2143BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_XMM1_XMM2_icebp);
2144BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp);
2145BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp);
2146BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp);
2147BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp);
2148BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp);
2149
2150BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulld_XMM1_XMM2_icebp);
2151BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp);
2152BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp);
2153BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp);
2154BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp);
2155BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp);
2156extern FNBS3FAR bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64;
2157extern FNBS3FAR bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64;
2158
2159BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmullw_pmulld(uint8_t bMode)
2160{
2161 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
2162 {
2163 { RTUINT256_INIT_C(0, 0, 0, 0),
2164 /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
2165 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
2166 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2167 /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2168 /* = */ RTUINT256_INIT_C(0x0b6106d488890000, 0x5c293e94a7419630, 0x5c293e94a7419630, 0x0b6106d488890000) },
2169 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2170 /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2171 /* = */ RTUINT256_INIT_C(0x8ec59e38d5149124, 0xf3b0dc605ba6fed2, 0x8800d8b8476c9066, 0xf3d45ee00ba4b9cf) },
2172 };
2173
2174 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
2175 {
2176 { RTUINT256_INIT_C(0, 0, 0, 0),
2177 /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
2178 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
2179 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2180 /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2181 /* = */ RTUINT256_INIT_C(0x2ea606d477780000, 0x6e5d3e9430ec9630, 0x6e5d3e9430ec9630, 0x2ea606d477780000) },
2182 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2183 /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2184 /* = */ RTUINT256_INIT_C(0x97439e3846719124, 0x8216dc606340fed2, 0x7c2bd8b8f1c09066, 0x31915ee054fbb9cf) },
2185 };
2186
2187 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2188 {
2189 { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2190 { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2191 { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2192 { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2193 { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2194 { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2195 { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2196 { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2197
2198 { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2199 { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2200 { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2201 { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2202 { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2203 { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2204 };
2205 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2206 {
2207 { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2208 { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2209 { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2210 { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2211 { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2212 { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2213 { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2214 { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2215
2216 { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2217 { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2218 { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2219 { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2220 { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2221 { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2222 };
2223 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2224 {
2225 { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2226 { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2227 { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2228 { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2229 { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2230 { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2231 { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2232 { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2233
2234 { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2235 { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2236 { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2237 { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2238 { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2239 { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2240 { bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2241 { bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 10, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
2242 };
2243 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2244 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2245 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2246 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2247}
2248
2249
2250/*
2251 * PMULHW, VPMULHW.
2252 */
2253BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_MM1_MM2_icebp);
2254BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp);
2255BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp);
2256BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp);
2257BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp);
2258BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp);
2259BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp);
2260BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp);
2261
2262BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhw(uint8_t bMode)
2263{
2264 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
2265 {
2266 { RTUINT256_INIT_C(0, 0, 0, 0),
2267 /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
2268 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
2269 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2270 /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2271 /* = */ RTUINT256_INIT_C(0xf49ff92cffff0000, 0xf92cf49ff258f258, 0xf92cf49ff258f258, 0xf49ff92cffff0000) },
2272 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2273 /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2274 /* = */ RTUINT256_INIT_C(0x0949021f03fd16e2, 0xfe5df57e19c81583, 0x2390fbc8ea4ad947, 0xe5990635f0e229f2) },
2275 };
2276
2277 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2278 {
2279 { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2280 { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2281 { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2282 { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2283 { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2284 { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2285 { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2286 { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2287 };
2288 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2289 {
2290 { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2291 { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2292 { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2293 { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2294 { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2295 { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2296 { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2297 { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2298 };
2299 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2300 {
2301 { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2302 { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2303 { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2304 { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2305 { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2306 { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2307 { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2308 { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2309 };
2310 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2311 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2312 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2313 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2314}
2315
2316
2317/*
2318 * PMULHUW, VPMULHUW.
2319 */
2320BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_MM1_MM2_icebp);
2321BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp);
2322BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp);
2323BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp);
2324BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp);
2325BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp);
2326BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp);
2327BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp);
2328
2329BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhuw(uint8_t bMode)
2330{
2331 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
2332 {
2333 { RTUINT256_INIT_C(0, 0, 0, 0),
2334 /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
2335 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
2336 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2337 /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2338 /* = */ RTUINT256_INIT_C(0x49f45f9277760000, 0x0a3d16c1258b369c, 0x0a3d16c1258b369c, 0x49f45f9277760000) },
2339 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2340 /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2341 /* = */ RTUINT256_INIT_C(0x0949cff503fd16e2, 0x3d510d4619c81583, 0x5fb12b7040963c0a, 0x296cb44814665aaa) },
2342 };
2343
2344 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2345 {
2346 { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2347 { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2348 { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2349 { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2350 { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2351 { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2352 { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2353 { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2354 };
2355 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2356 {
2357 { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2358 { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2359 { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2360 { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2361 { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2362 { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2363 { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2364 { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2365 };
2366 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2367 {
2368 { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2369 { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2370 { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2371 { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2372 { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2373 { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2374 { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2375 { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
2376 };
2377 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2378 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2379 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2380 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2381}
2382
2383
2384/*
2385 * PSHUFB
2386 */
2387BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_MM1_MM2_icebp);
2388BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_MM1_FSxBX_icebp);
2389BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_XMM1_XMM2_icebp);
2390BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp);
2391extern FNBS3FAR bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64;
2392extern FNBS3FAR bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64;
2393BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp);
2394BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp);
2395extern FNBS3FAR bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64;
2396extern FNBS3FAR bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64;
2397BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp);
2398BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp);
2399extern FNBS3FAR bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64;
2400extern FNBS3FAR bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64;
2401
2402BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufb(uint8_t bMode)
2403{
2404 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2405 {
2406 { /*mask*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2407 /*val*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2408 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2409 { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff),
2410 /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff),
2411 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) },
2412 { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0x7f7f7f7f7f7f7f7f),
2413 /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff),
2414 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff) },
2415 { /*mask*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2416 /*val*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2417 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xeeeedddddddd0000) },
2418 { /*mask*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2419 /*val*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2420 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00a0002300990000) },
2421 };
2422
2423 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2424 {
2425 { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0),
2426 /*val*/ RTUINT256_INIT_C(0, 0, 0, 0),
2427 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2428 { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
2429 /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
2430 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
2431 { /*mask*/ RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f),
2432 /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
2433 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
2434 { /*mask*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2435 /*val*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2436 /* => */ RTUINT256_INIT_C(0xaaaa999999990000, 0xccccbbbbbbbbaaaa, 0x0000ffffffffeeee, 0xeeeedddddddd0000) },
2437 { /*mask*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2438 /*val*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2439 /* => */ RTUINT256_INIT_C(0xdd320063ac004000, 0xdd00f9005c091e00, 0x00998800d35b0000, 0x005b002300620000) },
2440 };
2441
2442 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2443 {
2444 { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2445 { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2446 { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2447 { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2448 { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2449 { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2450 { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2451 { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2452 };
2453 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2454 {
2455 { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2456 { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2457 { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2458 { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2459 { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2460 { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2461 { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2462 { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2463 };
2464 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2465 {
2466 { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2467 { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2468 { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2469 { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2470 { bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2471 { bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2472 { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2473 { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2474 { bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2475 { bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2476 { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2477 { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2478 { bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2479 { bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2480 };
2481 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2482 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2483 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2484 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2485}
2486
2487
2488/*
2489 * [V]PUNPCKHBW
2490 */
2491BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_MM1_MM2_icebp);
2492BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp);
2493BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp);
2494BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp);
2495extern FNBS3FAR bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64;
2496extern FNBS3FAR bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64;
2497BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp);
2498BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp);
2499extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64;
2500extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64;
2501BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp);
2502BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp);
2503extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64;
2504extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64;
2505
2506BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhbw(uint8_t bMode)
2507{
2508 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2509 {
2510 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2511 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2512 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2513 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2514 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2515 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1e1f2e2f3e3f4e4) },
2516 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2517 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2518 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55dd55dd66ee66ee) },
2519 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2520 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2521 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c435cd3e0cd73a0) },
2522 };
2523 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2524 {
2525 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2526 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2527 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2528 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2529 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2530 /* => */ RTUINT256_INIT_C(0xf1b1f2b2f3b3f4b4, 0xf5b5f6b6f7b7f8b8, 0xd191d292d393d494, 0xd595d696d797d898) },
2531 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2532 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2533 /* => */ RTUINT256_INIT_C(0x55dd55dd66ee66ee, 0x77ff77ff88008800, 0x1199119922aa22aa, 0x33bb33bb44cc44cc) },
2534 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2535 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2536 /* => */ RTUINT256_INIT_C(0x4d1e09ddf0dd2aac, 0x6c09dc637332d594, 0xb48821002fe9a85b, 0x56bf4c999b62a2c3) },
2537 };
2538
2539 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2540 {
2541 { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2542 { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2543 { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2544 { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2545 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2546 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2547 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2548 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2549 };
2550 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2551 {
2552 { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2553 { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2554 { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2555 { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2556 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2557 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2558 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2559 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2560 };
2561 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2562 {
2563 { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2564 { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2565 { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2566 { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2567 { bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2568 { bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2569 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2570 { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2571 { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2572 { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2573 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2574 { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2575 { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2576 { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2577 };
2578 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2579 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2580 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2581 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2582}
2583
2584
2585/*
2586 * [V]PUNPCKHWD
2587 */
2588BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_MM1_MM2_icebp);
2589BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp);
2590BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp);
2591BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp);
2592extern FNBS3FAR bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64;
2593extern FNBS3FAR bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64;
2594BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp);
2595BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp);
2596extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64;
2597extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64;
2598BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp);
2599BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp);
2600extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64;
2601extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64;
2602
2603BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhwd(uint8_t bMode)
2604{
2605 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2606 {
2607 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2608 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2609 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2610 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2611 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2612 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2e1e2f3f4e3e4) },
2613 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2614 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2615 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x5555dddd6666eeee) },
2616 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2617 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2618 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5c43d3e073cda0) },
2619 };
2620 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2621 {
2622 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2623 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2624 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2625 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2626 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2627 /* => */ RTUINT256_INIT_C(0xf1f2b1b2f3f4b3b4, 0xf5f6b5b6f7f8b7b8, 0xd1d29192d3d49394, 0xd5d69596d7d89798) },
2628 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2629 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2630 /* => */ RTUINT256_INIT_C(0x5555dddd6666eeee, 0x7777ffff88880000, 0x111199992222aaaa, 0x3333bbbb4444cccc) },
2631 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2632 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2633 /* => */ RTUINT256_INIT_C(0x4d091eddf02addac, 0x6cdc096373d53294, 0xb42188002fa8e95b, 0x564cbf999ba262c3) },
2634 };
2635
2636 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2637 {
2638 { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2639 { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2640 { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2641 { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2642 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2643 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2644 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2645 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2646 };
2647 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2648 {
2649 { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2650 { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2651 { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2652 { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2653 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2654 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2655 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2656 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2657 };
2658 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2659 {
2660 { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2661 { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2662 { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2663 { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2664 { bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2665 { bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2666 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2667 { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2668 { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2669 { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2670 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2671 { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2672 { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2673 { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2674 };
2675 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2676 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2677 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2678 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2679}
2680
2681
2682/*
2683 * [V]PUNPCKHDQ
2684 */
2685BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_MM1_MM2_icebp);
2686BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp);
2687BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp);
2688BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp);
2689extern FNBS3FAR bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64;
2690extern FNBS3FAR bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64;
2691BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp);
2692BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp);
2693extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64;
2694extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64;
2695BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp);
2696BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp);
2697extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64;
2698extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64;
2699
2700BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhdq(uint8_t bMode)
2701{
2702 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2703 {
2704 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2705 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2706 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2707 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2708 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2709 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4e1e2e3e4) },
2710 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2711 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2712 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55556666ddddeeee) },
2713 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2714 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2715 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ce07343d3cda0) },
2716 };
2717 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2718 {
2719 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2720 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2721 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2722 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2723 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2724 /* => */ RTUINT256_INIT_C(0xf1f2f3f4b1b2b3b4, 0xf5f6f7f8b5b6b7b8, 0xd1d2d3d491929394, 0xd5d6d7d895969798) },
2725 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2726 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2727 /* => */ RTUINT256_INIT_C(0x55556666ddddeeee, 0x77778888ffff0000, 0x111122229999aaaa, 0x33334444bbbbcccc) },
2728 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2729 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2730 /* => */ RTUINT256_INIT_C(0x4d09f02a1eddddac, 0x6cdc73d509633294, 0xb4212fa88800e95b, 0x564c9ba2bf9962c3) },
2731 };
2732
2733 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2734 {
2735 { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2736 { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2737 { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2738 { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2739 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2740 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2741 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2742 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2743 };
2744 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2745 {
2746 { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2747 { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2748 { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2749 { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2750 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2751 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2752 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2753 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2754 };
2755 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2756 {
2757 { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2758 { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2759 { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2760 { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2761 { bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2762 { bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2763 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2764 { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2765 { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2766 { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2767 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2768 { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2769 { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2770 { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2771 };
2772 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2773 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2774 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2775 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2776}
2777
2778
2779/*
2780 * [V]PUNPCKHQDQ
2781 */
2782BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp);
2783BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp);
2784extern FNBS3FAR bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64;
2785extern FNBS3FAR bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64;
2786BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp);
2787BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp);
2788extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64;
2789extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64;
2790BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp);
2791BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp);
2792extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64;
2793extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64;
2794
2795BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhqdq(uint8_t bMode)
2796{
2797 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2798 {
2799 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2800 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2801 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2802 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2803 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2804 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) },
2805 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2806 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2807 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0xddddeeeeffff0000, 0x1111222233334444, 0x9999aaaabbbbcccc) },
2808 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2809 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2810 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) },
2811 };
2812
2813 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2814 {
2815 { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2816 { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2817 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2818 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2819 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2820 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2821 };
2822 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2823 {
2824 { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2825 { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2826 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2827 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2828 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2829 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2830 };
2831 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2832 {
2833 { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2834 { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2835 { bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2836 { bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2837 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2838 { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2839 { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2840 { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2841 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2842 { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2843 { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2844 { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2845 };
2846 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2847 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2848 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2849 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2850}
2851
2852
2853/*
2854 * [V]PUNPCKLBW
2855 */
2856BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_MM1_MM2_icebp);
2857BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp);
2858BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp);
2859BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp);
2860extern FNBS3FAR bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64;
2861extern FNBS3FAR bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64;
2862BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp);
2863BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp);
2864extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64;
2865extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64;
2866BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp);
2867BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp);
2868extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64;
2869extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64;
2870
2871BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklbw(uint8_t bMode)
2872{
2873 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2874 {
2875 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2876 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2877 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2878 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2879 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2880 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5e5f6e6f7e7f8e8) },
2881 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2882 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2883 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77ff77ff88008800) },
2884 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2885 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2886 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x932309849699bbfd) },
2887 };
2888 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2889 {
2890 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2891 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2892 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2893 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2894 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2895 /* => */ RTUINT256_INIT_C(0xe1a1e2a2e3a3e4a4, 0xe5a5e6a6e7a7e8a8, 0xc181c282c383c484, 0xc585c686c787c888) },
2896 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2897 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2898 /* => */ RTUINT256_INIT_C(0x1199119922aa22aa, 0x33bb33bb44cc44cc, 0x55dd55dd66ee66ee, 0x77ff77ff88008800) },
2899 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2900 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2901 /* => */ RTUINT256_INIT_C(0x3ef9f45c178ec8ec, 0x66406b723f56e633, 0x9c435cd3e0cd73a0, 0x932309849699bbfd) },
2902 };
2903
2904 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
2905 {
2906 { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2907 { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2908 { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2909 { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2910 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2911 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2912 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2913 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2914 };
2915 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
2916 {
2917 { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2918 { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2919 { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2920 { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2921 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2922 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2923 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2924 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2925 };
2926 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
2927 {
2928 { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
2929 { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
2930 { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2931 { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2932 { bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2933 { bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2934 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2935 { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2936 { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2937 { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2938 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2939 { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2940 { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2941 { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
2942 };
2943 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2944 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
2945 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2946 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
2947}
2948
2949
2950/*
2951 * [V]PUNPCKLWD
2952 */
2953BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_MM1_MM2_icebp);
2954BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp);
2955BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp);
2956BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp);
2957extern FNBS3FAR bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64;
2958extern FNBS3FAR bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64;
2959BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp);
2960BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp);
2961extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64;
2962extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64;
2963BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp);
2964BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp);
2965extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64;
2966extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64;
2967
2968BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklwd(uint8_t bMode)
2969{
2970 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
2971 {
2972 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2973 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
2974 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
2975 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
2976 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
2977 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6e5e6f7f8e7e8) },
2978 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
2979 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
2980 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7777ffff88880000) },
2981 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
2982 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
2983 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9309238496bb99fd) },
2984 };
2985 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
2986 {
2987 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
2988 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
2989 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
2990 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
2991 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
2992 /* => */ RTUINT256_INIT_C(0xe1e2a1a2e3e4a3a4, 0xe5e6a5a6e7e8a7a8, 0xc1c28182c3c48384, 0xc5c68586c7c88788) },
2993 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
2994 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
2995 /* => */ RTUINT256_INIT_C(0x111199992222aaaa, 0x3333bbbb4444cccc, 0x5555dddd6666eeee, 0x7777ffff88880000) },
2996 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
2997 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
2998 /* => */ RTUINT256_INIT_C(0x3ef4f95c17c88eec, 0x666b40723fe65633, 0x9c5c43d3e073cda0, 0x9309238496bb99fd) },
2999 };
3000
3001 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3002 {
3003 { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3004 { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3005 { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3006 { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3007 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3008 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3009 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3010 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3011 };
3012 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3013 {
3014 { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3015 { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3016 { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3017 { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3018 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3019 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3020 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3021 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3022 };
3023 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3024 {
3025 { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3026 { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3027 { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3028 { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3029 { bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3030 { bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3031 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3032 { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3033 { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3034 { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3035 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3036 { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3037 { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3038 { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3039 };
3040 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3041 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3042 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3043 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3044}
3045
3046
3047/*
3048 * [V]PUNPCKLDQ
3049 */
3050BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_MM1_MM2_icebp);
3051BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp);
3052BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp);
3053BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp);
3054extern FNBS3FAR bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64;
3055extern FNBS3FAR bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64;
3056BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp);
3057BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp);
3058extern FNBS3FAR bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64;
3059extern FNBS3FAR bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64;
3060BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp);
3061BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp);
3062extern FNBS3FAR bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64;
3063extern FNBS3FAR bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64;
3064
3065BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckldq(uint8_t bMode)
3066{
3067 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
3068 {
3069 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3070 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3071 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3072 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3073 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3074 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6f7f8e5e6e7e8) },
3075 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3076 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3077 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77778888ffff0000) },
3078 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3079 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3080 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x930996bb238499fd) },
3081 };
3082 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3083 {
3084 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3085 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3086 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3087 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3088 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3089 /* => */ RTUINT256_INIT_C(0xe1e2e3e4a1a2a3a4, 0xe5e6e7e8a5a6a7a8, 0xc1c2c3c481828384, 0xc5c6c7c885868788) },
3090 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3091 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3092 /* => */ RTUINT256_INIT_C(0x111122229999aaaa, 0x33334444bbbbcccc, 0x55556666ddddeeee, 0x77778888ffff0000) },
3093 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3094 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3095 /* => */ RTUINT256_INIT_C(0x3ef417c8f95c8eec, 0x666b3fe640725633, 0x9c5ce07343d3cda0, 0x930996bb238499fd) },
3096 };
3097
3098 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3099 {
3100 { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3101 { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3102 { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3103 { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3104 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3105 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3106 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3107 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3108 };
3109 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3110 {
3111 { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3112 { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3113 { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3114 { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3115 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3116 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3117 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3118 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3119 };
3120 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3121 {
3122 { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3123 { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3124 { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3125 { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3126 { bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3127 { bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3128 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3129 { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3130 { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3131 { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3132 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3133 { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3134 { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3135 { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3136 };
3137 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3138 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3139 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3140 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3141}
3142
3143
3144/*
3145 * [V]PUNPCKLQDQ
3146 */
3147BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp);
3148BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp);
3149extern FNBS3FAR bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64;
3150extern FNBS3FAR bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64;
3151BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp);
3152BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp);
3153extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64;
3154extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64;
3155BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp);
3156BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp);
3157extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64;
3158extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64;
3159
3160BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklqdq(uint8_t bMode)
3161{
3162 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3163 {
3164 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3165 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3166 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3167 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3168 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3169 /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) },
3170 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3171 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3172 /* => */ RTUINT256_INIT_C(0x1111222233334444, 0x9999aaaabbbbcccc, 0x5555666677778888, 0xddddeeeeffff0000) },
3173 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3174 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3175 /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) },
3176 };
3177
3178 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3179 {
3180 { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3181 { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3182 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3183 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3184 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3185 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3186 };
3187 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3188 {
3189 { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3190 { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3191 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3192 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3193 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3194 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3195 };
3196 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3197 {
3198 { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3199 { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3200 { bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3201 { bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3202 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3203 { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3204 { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3205 { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3206 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3207 { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3208 { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3209 { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3210 };
3211 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3212 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3213 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3214 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3215}
3216
3217
3218/*
3219 * [V]PACKSSWB
3220 */
3221BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_MM1_MM2_icebp);
3222BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_MM1_FSxBX_icebp);
3223BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_XMM1_XMM2_icebp);
3224BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp);
3225extern FNBS3FAR bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64;
3226extern FNBS3FAR bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64;
3227BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp);
3228BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp);
3229extern FNBS3FAR bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64;
3230extern FNBS3FAR bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64;
3231BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp);
3232BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp);
3233extern FNBS3FAR bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64;
3234extern FNBS3FAR bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64;
3235
3236BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packsswb(uint8_t bMode)
3237{
3238 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
3239 {
3240 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3241 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3242 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3243 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3244 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3245 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8080808080808080) },
3246 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3247 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3248 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7f7f7f808080ff00) },
3249 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3250 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3251 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x808080807f807f80) },
3252 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042),
3253 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
3254 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8264fe4222808081) },
3255 };
3256 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3257 {
3258 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3259 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3260 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3261 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3262 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3263 /* => */ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080) },
3264 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3265 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3266 /* => */ RTUINT256_INIT_C(0x7f7f7f807f7f7f7f, 0x8080ff0080808080, 0x7f7f7f7f7f7f7f80, 0x808080808080ff00) },
3267 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3268 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3269 /* => */ RTUINT256_INIT_C(0x7f807f7f7f7f7f7f, 0x7f807f7f80807f7f, 0x807f7f8080808080, 0x8080807f7f807f80) },
3270 { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080),
3271 /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035),
3272 /* => */ RTUINT256_INIT_C(0x2225797efffe8880, 0x01020305070b0d11, 0x6432160842467f7f, 0x13171d25292b2f35) },
3273 };
3274
3275 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3276 {
3277 { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3278 { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3279 { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3280 { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3281 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3282 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3283 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3284 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3285 };
3286 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3287 {
3288 { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3289 { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3290 { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3291 { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3292 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3293 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3294 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3295 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3296 };
3297 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3298 {
3299 { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3300 { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3301 { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3302 { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3303 { bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3304 { bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3305 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3306 { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3307 { bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3308 { bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3309 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3310 { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3311 { bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3312 { bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3313 };
3314 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3315 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3316 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3317 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3318}
3319
3320
3321/*
3322 * [V]PACKSSDW
3323 */
3324BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_MM1_MM2_icebp);
3325BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_MM1_FSxBX_icebp);
3326BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_XMM1_XMM2_icebp);
3327BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp);
3328extern FNBS3FAR bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64;
3329extern FNBS3FAR bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64;
3330BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp);
3331BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp);
3332extern FNBS3FAR bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64;
3333extern FNBS3FAR bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64;
3334BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp);
3335BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp);
3336extern FNBS3FAR bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64;
3337extern FNBS3FAR bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64;
3338
3339BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packssdw(uint8_t bMode)
3340{
3341 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
3342 {
3343 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3344 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3345 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3346 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3347 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3348 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8000800080008000) },
3349 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3350 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3351 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7fff7fff80008000) },
3352 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3353 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3354 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x800080007fff7fff) },
3355 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xffff898400007495),
3356 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x00002222ffff9485),
3357 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8984749522229485) },
3358 };
3359 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3360 {
3361 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3362 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3363 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3364 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3365 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3366 /* => */ RTUINT256_INIT_C(0x8000800080008000, 0x8000800080008000, 0x8000800080008000, 0x8000800080008000) },
3367 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3368 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3369 /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x8000800080008000, 0x7fff7fff7fff7fff, 0x8000800080008000) },
3370 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3371 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3372 /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x7fff7fff80007fff, 0x80007fff80008000, 0x800080007fff7fff) },
3373 { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff),
3374 /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0),
3375 /* => */ RTUINT256_INIT_C(0x34902349a230e384, 0x80017ffecbaffffe, 0x80007ffe7fff8000, 0x64321608ffe0ffc0) },
3376 };
3377
3378 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3379 {
3380 { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3381 { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3382 { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3383 { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3384 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3385 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3386 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3387 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3388 };
3389 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3390 {
3391 { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3392 { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3393 { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3394 { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3395 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3396 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3397 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3398 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3399 };
3400 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3401 {
3402 { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3403 { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3404 { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3405 { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3406 { bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3407 { bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3408 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3409 { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3410 { bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3411 { bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3412 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3413 { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3414 { bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3415 { bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3416 };
3417 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3418 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3419 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3420 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3421}
3422
3423
3424/*
3425 * [V]PACKUSWB
3426 */
3427BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_MM1_MM2_icebp);
3428BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_MM1_FSxBX_icebp);
3429BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_XMM1_XMM2_icebp);
3430BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp);
3431extern FNBS3FAR bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64;
3432extern FNBS3FAR bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64;
3433BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp);
3434BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp);
3435extern FNBS3FAR bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64;
3436extern FNBS3FAR bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64;
3437BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp);
3438BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp);
3439extern FNBS3FAR bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64;
3440extern FNBS3FAR bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64;
3441
3442BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packuswb(uint8_t bMode)
3443{
3444 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
3445 {
3446 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3447 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3448 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3449 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3450 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3451 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) },
3452 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3453 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3454 /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xffffff0000000000) },
3455 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3456 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3457 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00000000ff00ff00) },
3458 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042),
3459 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
3460 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x0064004222000000) },
3461 };
3462 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3463 {
3464 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3465 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3466 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3467 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3468 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3469 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
3470 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3471 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3472 /* => */ RTUINT256_INIT_C(0xffffff00ffffffff, 0x0000000000000000, 0xffffffffffffff00, 0x000000000000000) },
3473 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3474 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3475 /* => */ RTUINT256_INIT_C(0xff00ffffffffffff, 0xff00ffff0000ffff, 0x00ffff0000000000, 0x000000ffff00ff00) },
3476 { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080),
3477 /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035),
3478 /* => */ RTUINT256_INIT_C(0x2225797e00000000, 0x01020305070b0d11, 0x6432160842468880, 0x13171d25292b2f35) },
3479 };
3480
3481 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3482 {
3483 { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3484 { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3485 { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3486 { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3487 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3488 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3489 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3490 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3491 };
3492 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3493 {
3494 { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3495 { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3496 { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3497 { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3498 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3499 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3500 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3501 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3502 };
3503 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3504 {
3505 { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 },
3506 { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
3507 { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3508 { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3509 { bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3510 { bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3511 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3512 { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3513 { bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3514 { bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3515 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3516 { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3517 { bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3518 { bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3519 };
3520 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3521 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3522 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3523 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3524}
3525
3526
3527/*
3528 * [V]PACKUSDW
3529 */
3530BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packusdw_XMM1_XMM2_icebp);
3531BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp);
3532extern FNBS3FAR bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64;
3533extern FNBS3FAR bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64;
3534BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp);
3535BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp);
3536extern FNBS3FAR bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64;
3537extern FNBS3FAR bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64;
3538BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp);
3539BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp);
3540extern FNBS3FAR bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64;
3541extern FNBS3FAR bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64;
3542BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packusdw(uint8_t bMode)
3543{
3544 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
3545 {
3546 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3547 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3548 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3549 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3550 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3551 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },
3552 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
3553 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
3554 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000) },
3555 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3556 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3557 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffff0000ffff, 0x0000ffff00000000, 0x00000000ffffffff) },
3558 { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff),
3559 /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0),
3560 /* => */ RTUINT256_INIT_C(0x3490234900000000, 0x00007ffe00000000, 0x00007ffe80000000, 0x6432160800000000) },
3561 };
3562
3563 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3564 {
3565 { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3566 { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3567 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3568 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3569 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3570 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3571 };
3572 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3573 {
3574 { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3575 { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3576 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3577 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3578 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3579 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3580 };
3581 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3582 {
3583 { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3584 { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3585 { bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3586 { bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3587 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3588 { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3589 { bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3590 { bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3591 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3592 { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3593 { bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3594 { bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
3595 };
3596 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3597 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3598 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3599 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3600}
3601
3602
3603/*
3604 * [V]PMAXUB - Compare unsigned byte integers and returns maximum values.
3605 * [V]PMAXUW - Compare unsigned word integers and returns maximum values.
3606 * [V]PMAXUD - Compare unsigned double word integers and returns maximum values.
3607 */
3608BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_MM1_MM2_icebp);
3609BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp);
3610BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp);
3611BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp);
3612extern FNBS3FAR bs3CpuInstr3_pmaxub_XMM8_XMM9_icebp_c64;
3613extern FNBS3FAR bs3CpuInstr3_pmaxub_XMM8_FSxBX_icebp_c64;
3614BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp);
3615BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp);
3616extern FNBS3FAR bs3CpuInstr3_vpmaxub_XMM8_XMM9_XMM10_icebp_c64;
3617extern FNBS3FAR bs3CpuInstr3_vpmaxub_XMM8_XMM9_FSxBX_icebp_c64;
3618BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp);
3619BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp);
3620extern FNBS3FAR bs3CpuInstr3_vpmaxub_YMM8_YMM9_YMM10_icebp_c64;
3621extern FNBS3FAR bs3CpuInstr3_vpmaxub_YMM8_YMM9_FSxBX_icebp_c64;
3622
3623BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp);
3624BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp);
3625extern FNBS3FAR bs3CpuInstr3_pmaxuw_XMM8_XMM9_icebp_c64;
3626extern FNBS3FAR bs3CpuInstr3_pmaxuw_XMM8_FSxBX_icebp_c64;
3627BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp);
3628BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp);
3629extern FNBS3FAR bs3CpuInstr3_vpmaxuw_XMM8_XMM9_XMM10_icebp_c64;
3630extern FNBS3FAR bs3CpuInstr3_vpmaxuw_XMM8_XMM9_FSxBX_icebp_c64;
3631BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp);
3632BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp);
3633extern FNBS3FAR bs3CpuInstr3_vpmaxuw_YMM8_YMM9_YMM10_icebp_c64;
3634extern FNBS3FAR bs3CpuInstr3_vpmaxuw_YMM8_YMM9_FSxBX_icebp_c64;
3635
3636BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp);
3637BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp);
3638extern FNBS3FAR bs3CpuInstr3_pmaxud_XMM8_XMM9_icebp_c64;
3639extern FNBS3FAR bs3CpuInstr3_pmaxud_XMM8_FSxBX_icebp_c64;
3640BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp);
3641BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp);
3642extern FNBS3FAR bs3CpuInstr3_vpmaxud_XMM8_XMM9_XMM10_icebp_c64;
3643extern FNBS3FAR bs3CpuInstr3_vpmaxud_XMM8_XMM9_FSxBX_icebp_c64;
3644BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp);
3645BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp);
3646extern FNBS3FAR bs3CpuInstr3_vpmaxud_YMM8_YMM9_YMM10_icebp_c64;
3647extern FNBS3FAR bs3CpuInstr3_vpmaxud_YMM8_YMM9_FSxBX_icebp_c64;
3648
3649BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxub_pmaxuw_pmaxud(uint8_t bMode)
3650{
3651 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] =
3652 {
3653 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3654 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3655 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3656 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3657 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3658 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8) },
3659 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3660 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3661 /* => */ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff8888) },
3662 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3663 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3664 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9cd3e0a0938499fd) },
3665 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042),
3666 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
3667 /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe64fffeff81) },
3668 };
3669 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
3670 {
3671 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3672 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3673 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3674 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3675 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3676 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
3677 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3678 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3679 /* => */ RTUINT256_INIT_C(0x4dddf0ac6cdc73d5, 0xf9f48eec667256e6, 0xb421e9a8bf999bc3, 0x9cd3e0a0938499fd) },
3680 };
3681 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
3682 {
3683 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3684 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3685 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3686 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3687 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3688 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
3689 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3690 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3691 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0xf95c8eec666b5633, 0xb421e95bbf999ba2, 0x9c5ce073930999fd) },
3692 };
3693 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
3694 {
3695 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3696 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3697 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3698 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3699 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3700 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
3701 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3702 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3703 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0xf95c8eec666b3fe6, 0xb4212fa8bf9962c3, 0x9c5ce073930996bb) },
3704 };
3705
3706 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3707 {
3708 { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3709 { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3710 { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3711 { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3712 { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3713 { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3714 { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3715 { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3716
3717 { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3718 { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3719 { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3720 { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3721 { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3722 { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3723
3724 { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3725 { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3726 { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3727 { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3728 { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3729 { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3730 };
3731 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3732 {
3733 { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3734 { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3735 { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3736 { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3737 { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3738 { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3739 { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3740 { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3741
3742 { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3743 { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3744 { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3745 { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3746 { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3747 { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3748
3749 { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3750 { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3751 { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3752 { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3753 { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3754 { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3755 };
3756 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3757 {
3758 { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3759 { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3760 { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3761 { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3762 { bs3CpuInstr3_pmaxub_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3763 { bs3CpuInstr3_pmaxub_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3764 { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3765 { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3766 { bs3CpuInstr3_vpmaxub_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3767 { bs3CpuInstr3_vpmaxub_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3768 { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3769 { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3770 { bs3CpuInstr3_vpmaxub_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3771 { bs3CpuInstr3_vpmaxub_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3772
3773 { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3774 { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3775 { bs3CpuInstr3_pmaxuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3776 { bs3CpuInstr3_pmaxuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3777 { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3778 { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3779 { bs3CpuInstr3_vpmaxuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3780 { bs3CpuInstr3_vpmaxuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3781 { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3782 { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3783 { bs3CpuInstr3_vpmaxuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3784 { bs3CpuInstr3_vpmaxuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3785
3786 { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3787 { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3788 { bs3CpuInstr3_pmaxud_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3789 { bs3CpuInstr3_pmaxud_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3790 { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3791 { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3792 { bs3CpuInstr3_vpmaxud_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3793 { bs3CpuInstr3_vpmaxud_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3794 { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3795 { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3796 { bs3CpuInstr3_vpmaxud_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3797 { bs3CpuInstr3_vpmaxud_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3798 };
3799 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3800 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
3801 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3802 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
3803}
3804
3805
3806/*
3807 * [V]PMAXSB - Compare signed byte integers and returns maximum values.
3808 * [V]PMAXSW - Compare signed word integers and returns maximum values.
3809 * [V]PMAXSD - Compare signed double word integers and returns maximum values.
3810 */
3811BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp);
3812BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp);
3813extern FNBS3FAR bs3CpuInstr3_pmaxsb_XMM8_XMM9_icebp_c64;
3814extern FNBS3FAR bs3CpuInstr3_pmaxsb_XMM8_FSxBX_icebp_c64;
3815BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp);
3816BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp);
3817extern FNBS3FAR bs3CpuInstr3_vpmaxsb_XMM8_XMM9_XMM10_icebp_c64;
3818extern FNBS3FAR bs3CpuInstr3_vpmaxsb_XMM8_XMM9_FSxBX_icebp_c64;
3819BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp);
3820BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp);
3821extern FNBS3FAR bs3CpuInstr3_vpmaxsb_YMM8_YMM9_YMM10_icebp_c64;
3822extern FNBS3FAR bs3CpuInstr3_vpmaxsb_YMM8_YMM9_FSxBX_icebp_c64;
3823
3824BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_MM1_MM2_icebp);
3825BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp);
3826BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp);
3827BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp);
3828extern FNBS3FAR bs3CpuInstr3_pmaxsw_XMM8_XMM9_icebp_c64;
3829extern FNBS3FAR bs3CpuInstr3_pmaxsw_XMM8_FSxBX_icebp_c64;
3830BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp);
3831BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp);
3832extern FNBS3FAR bs3CpuInstr3_vpmaxsw_XMM8_XMM9_XMM10_icebp_c64;
3833extern FNBS3FAR bs3CpuInstr3_vpmaxsw_XMM8_XMM9_FSxBX_icebp_c64;
3834BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp);
3835BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp);
3836extern FNBS3FAR bs3CpuInstr3_vpmaxsw_YMM8_YMM9_YMM10_icebp_c64;
3837extern FNBS3FAR bs3CpuInstr3_vpmaxsw_YMM8_YMM9_FSxBX_icebp_c64;
3838
3839BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp);
3840BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp);
3841extern FNBS3FAR bs3CpuInstr3_pmaxsd_XMM8_XMM9_icebp_c64;
3842extern FNBS3FAR bs3CpuInstr3_pmaxsd_XMM8_FSxBX_icebp_c64;
3843BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp);
3844BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp);
3845extern FNBS3FAR bs3CpuInstr3_vpmaxsd_XMM8_XMM9_XMM10_icebp_c64;
3846extern FNBS3FAR bs3CpuInstr3_vpmaxsd_XMM8_XMM9_FSxBX_icebp_c64;
3847BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp);
3848BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp);
3849extern FNBS3FAR bs3CpuInstr3_vpmaxsd_YMM8_YMM9_YMM10_icebp_c64;
3850extern FNBS3FAR bs3CpuInstr3_vpmaxsd_YMM8_YMM9_FSxBX_icebp_c64;
3851
3852BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxsb_pmaxsw_pmaxsd(uint8_t bMode)
3853{
3854 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] =
3855 {
3856 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3857 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
3858 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
3859 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
3860 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
3861 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8) },
3862 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
3863 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
3864 /* => */ RTUINT256_INIT_C( 4, 6, 7, 0x5555666677770000) },
3865 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
3866 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
3867 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x43d3e073238499fd) },
3868 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042),
3869 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
3870 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00220064fffe0042) },
3871 };
3872 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
3873 {
3874 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3875 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3876 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3877 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3878 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3879 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
3880 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3881 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3882 /* => */ RTUINT256_INIT_C(0x4d09f02a6c6373d5, 0x3e5c17ec66725633, 0xb4212f5b564c62c3, 0x435ce073230999fd) },
3883 };
3884 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
3885 {
3886 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3887 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3888 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3889 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3890 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3891 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
3892 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3893 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3894 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b5633, 0xb4212fa8564c62c3, 0x43d3e073238499fd) },
3895 };
3896 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
3897 {
3898 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
3899 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
3900 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
3901 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
3902 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
3903 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
3904 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
3905 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
3906 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd) },
3907 };
3908
3909 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
3910 {
3911 { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3912 { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3913 { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3914 { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3915 { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3916 { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3917
3918 { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3919 { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3920 { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3921 { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3922 { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3923 { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3924 { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3925 { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3926
3927 { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3928 { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3929 { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3930 { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3931 { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3932 { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3933 };
3934 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
3935 {
3936 { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3937 { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3938 { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3939 { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3940 { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3941 { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3942
3943 { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3944 { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3945 { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3946 { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3947 { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3948 { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3949 { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3950 { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3951
3952 { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3953 { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3954 { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3955 { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3956 { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3957 { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3958 };
3959 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
3960 {
3961 { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3962 { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3963 { bs3CpuInstr3_pmaxsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3964 { bs3CpuInstr3_pmaxsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3965 { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3966 { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3967 { bs3CpuInstr3_vpmaxsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3968 { bs3CpuInstr3_vpmaxsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3969 { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3970 { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3971 { bs3CpuInstr3_vpmaxsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3972 { bs3CpuInstr3_vpmaxsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
3973
3974 { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3975 { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
3976 { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3977 { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3978 { bs3CpuInstr3_pmaxsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3979 { bs3CpuInstr3_pmaxsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3980 { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3981 { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3982 { bs3CpuInstr3_vpmaxsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3983 { bs3CpuInstr3_vpmaxsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3984 { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3985 { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3986 { bs3CpuInstr3_vpmaxsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3987 { bs3CpuInstr3_vpmaxsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
3988
3989 { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3990 { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3991 { bs3CpuInstr3_pmaxsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3992 { bs3CpuInstr3_pmaxsd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3993 { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3994 { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3995 { bs3CpuInstr3_vpmaxsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3996 { bs3CpuInstr3_vpmaxsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3997 { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3998 { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
3999 { bs3CpuInstr3_vpmaxsd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4000 { bs3CpuInstr3_vpmaxsd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4001 };
4002 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4003 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4004 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4005 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
4006}
4007
4008
4009/*
4010 * [V]PMINUB - Compare unsigned byte integers and returns minimum values.
4011 * [V]PMINUW - Compare unsigned word integers and returns minimum values.
4012 * [V]PMINUD - Compare unsigned double word integers and returns minimum values.
4013 */
4014BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_MM1_MM2_icebp);
4015BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_MM1_FSxBX_icebp);
4016BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_XMM1_XMM2_icebp);
4017BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_XMM1_FSxBX_icebp);
4018extern FNBS3FAR bs3CpuInstr3_pminub_XMM8_XMM9_icebp_c64;
4019extern FNBS3FAR bs3CpuInstr3_pminub_XMM8_FSxBX_icebp_c64;
4020BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp);
4021BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp);
4022extern FNBS3FAR bs3CpuInstr3_vpminub_XMM8_XMM9_XMM10_icebp_c64;
4023extern FNBS3FAR bs3CpuInstr3_vpminub_XMM8_XMM9_FSxBX_icebp_c64;
4024BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp);
4025BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp);
4026extern FNBS3FAR bs3CpuInstr3_vpminub_YMM8_YMM9_YMM10_icebp_c64;
4027extern FNBS3FAR bs3CpuInstr3_vpminub_YMM8_YMM9_FSxBX_icebp_c64;
4028
4029BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminuw_XMM1_XMM2_icebp);
4030BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp);
4031extern FNBS3FAR bs3CpuInstr3_pminuw_XMM8_XMM9_icebp_c64;
4032extern FNBS3FAR bs3CpuInstr3_pminuw_XMM8_FSxBX_icebp_c64;
4033BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp);
4034BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp);
4035extern FNBS3FAR bs3CpuInstr3_vpminuw_XMM8_XMM9_XMM10_icebp_c64;
4036extern FNBS3FAR bs3CpuInstr3_vpminuw_XMM8_XMM9_FSxBX_icebp_c64;
4037BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp);
4038BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp);
4039extern FNBS3FAR bs3CpuInstr3_vpminuw_YMM8_YMM9_YMM10_icebp_c64;
4040extern FNBS3FAR bs3CpuInstr3_vpminuw_YMM8_YMM9_FSxBX_icebp_c64;
4041
4042BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminud_XMM1_XMM2_icebp);
4043BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminud_XMM1_FSxBX_icebp);
4044extern FNBS3FAR bs3CpuInstr3_pminud_XMM8_XMM9_icebp_c64;
4045extern FNBS3FAR bs3CpuInstr3_pminud_XMM8_FSxBX_icebp_c64;
4046BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp);
4047BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp);
4048extern FNBS3FAR bs3CpuInstr3_vpminud_XMM8_XMM9_XMM10_icebp_c64;
4049extern FNBS3FAR bs3CpuInstr3_vpminud_XMM8_XMM9_FSxBX_icebp_c64;
4050BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp);
4051BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp);
4052extern FNBS3FAR bs3CpuInstr3_vpminud_YMM8_YMM9_YMM10_icebp_c64;
4053extern FNBS3FAR bs3CpuInstr3_vpminud_YMM8_YMM9_FSxBX_icebp_c64;
4054
4055BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pminub_pminuw_pminud(uint8_t bMode)
4056{
4057 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] =
4058 {
4059 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
4060 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
4061 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
4062 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
4063 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
4064 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8) },
4065 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
4066 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
4067 /* => */ RTUINT256_INIT_C( 4, 6, 7, 0x5555666677770000) },
4068 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
4069 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
4070 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x435ccd73230996bb) },
4071 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042),
4072 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
4073 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00220000ff800042) },
4074 };
4075 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
4076 {
4077 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4078 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4079 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4080 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4081 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4082 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) },
4083 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4084 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4085 /* => */ RTUINT256_INIT_C(0x1e09dd2a09633294, 0x3e5c17c8406b3f33, 0x88002f5b564c62a2, 0x435ccd73230996bb) },
4086 };
4087 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
4088 {
4089 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4090 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4091 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4092 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4093 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4094 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) },
4095 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4096 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4097 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c840723fe6, 0x88002fa8564c62c3, 0x43d3cda0238496bb) },
4098 };
4099 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
4100 {
4101 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4102 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4103 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4104 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4105 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4106 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) },
4107 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4108 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4109 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c840725633, 0x8800e95b564c9ba2, 0x43d3cda0238499fd) },
4110 };
4111
4112 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4113 {
4114 { bs3CpuInstr3_pminub_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4115 { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4116 { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4117 { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4118 { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4119 { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4120 { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4121 { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4122
4123 { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4124 { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4125 { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4126 { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4127 { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4128 { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4129
4130 { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4131 { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4132 { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4133 { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4134 { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4135 { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4136 };
4137 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4138 {
4139 { bs3CpuInstr3_pminub_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4140 { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4141 { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4142 { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4143 { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4144 { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4145 { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4146 { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4147
4148 { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4149 { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4150 { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4151 { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4152 { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4153 { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4154
4155 { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4156 { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4157 { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4158 { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4159 { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4160 { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4161 };
4162 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4163 {
4164 { bs3CpuInstr3_pminub_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4165 { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4166 { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4167 { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4168 { bs3CpuInstr3_pminub_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4169 { bs3CpuInstr3_pminub_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4170 { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4171 { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4172 { bs3CpuInstr3_vpminub_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4173 { bs3CpuInstr3_vpminub_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4174 { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4175 { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4176 { bs3CpuInstr3_vpminub_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4177 { bs3CpuInstr3_vpminub_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4178
4179 { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4180 { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4181 { bs3CpuInstr3_pminuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4182 { bs3CpuInstr3_pminuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4183 { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4184 { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4185 { bs3CpuInstr3_vpminuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4186 { bs3CpuInstr3_vpminuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4187 { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4188 { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4189 { bs3CpuInstr3_vpminuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4190 { bs3CpuInstr3_vpminuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4191
4192 { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4193 { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4194 { bs3CpuInstr3_pminud_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4195 { bs3CpuInstr3_pminud_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4196 { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4197 { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4198 { bs3CpuInstr3_vpminud_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4199 { bs3CpuInstr3_vpminud_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4200 { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4201 { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4202 { bs3CpuInstr3_vpminud_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4203 { bs3CpuInstr3_vpminud_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4204 };
4205 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4206 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4207 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4208 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
4209}
4210
4211
4212/*
4213 * [V]PMINSB - Compare signed byte integers and returns minimum values.
4214 * [V]PMINSW - Compare signed word integers and returns minimum values.
4215 * [V]PMINSD - Compare signed double word integers and returns minimum values.
4216 */
4217BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsb_XMM1_XMM2_icebp);
4218BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp);
4219extern FNBS3FAR bs3CpuInstr3_pminsb_XMM8_XMM9_icebp_c64;
4220extern FNBS3FAR bs3CpuInstr3_pminsb_XMM8_FSxBX_icebp_c64;
4221BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp);
4222BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp);
4223extern FNBS3FAR bs3CpuInstr3_vpminsb_XMM8_XMM9_XMM10_icebp_c64;
4224extern FNBS3FAR bs3CpuInstr3_vpminsb_XMM8_XMM9_FSxBX_icebp_c64;
4225BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp);
4226BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp);
4227extern FNBS3FAR bs3CpuInstr3_vpminsb_YMM8_YMM9_YMM10_icebp_c64;
4228extern FNBS3FAR bs3CpuInstr3_vpminsb_YMM8_YMM9_FSxBX_icebp_c64;
4229
4230BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_MM1_MM2_icebp);
4231BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_MM1_FSxBX_icebp);
4232BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_XMM1_XMM2_icebp);
4233BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp);
4234extern FNBS3FAR bs3CpuInstr3_pminsw_XMM8_XMM9_icebp_c64;
4235extern FNBS3FAR bs3CpuInstr3_pminsw_XMM8_FSxBX_icebp_c64;
4236BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp);
4237BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp);
4238extern FNBS3FAR bs3CpuInstr3_vpminsw_XMM8_XMM9_XMM10_icebp_c64;
4239extern FNBS3FAR bs3CpuInstr3_vpminsw_XMM8_XMM9_FSxBX_icebp_c64;
4240BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp);
4241BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp);
4242extern FNBS3FAR bs3CpuInstr3_vpminsw_YMM8_YMM9_YMM10_icebp_c64;
4243extern FNBS3FAR bs3CpuInstr3_vpminsw_YMM8_YMM9_FSxBX_icebp_c64;
4244
4245BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsd_XMM1_XMM2_icebp);
4246BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp);
4247extern FNBS3FAR bs3CpuInstr3_pminsd_XMM8_XMM9_icebp_c64;
4248extern FNBS3FAR bs3CpuInstr3_pminsd_XMM8_FSxBX_icebp_c64;
4249BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp);
4250BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp);
4251extern FNBS3FAR bs3CpuInstr3_vpminsd_XMM8_XMM9_XMM10_icebp_c64;
4252extern FNBS3FAR bs3CpuInstr3_vpminsd_XMM8_XMM9_FSxBX_icebp_c64;
4253BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp);
4254BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp);
4255extern FNBS3FAR bs3CpuInstr3_vpminsd_YMM8_YMM9_YMM10_icebp_c64;
4256extern FNBS3FAR bs3CpuInstr3_vpminsd_YMM8_YMM9_FSxBX_icebp_c64;
4257
4258BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pminsb_pminsw_pminsd(uint8_t bMode)
4259{
4260 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] =
4261 {
4262 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0),
4263 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0),
4264 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) },
4265 { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8),
4266 /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8),
4267 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8) },
4268 { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888),
4269 /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000),
4270 /* => */ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff8888) },
4271 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
4272 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
4273 /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ccda0930996bb) },
4274 { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042),
4275 /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
4276 /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe00ff80ff81) },
4277 };
4278 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
4279 {
4280 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4281 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4282 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4283 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4284 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4285 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) },
4286 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4287 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4288 /* => */ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf9f48ec8406b3fe6, 0x8800e9a8bf999ba2, 0x9cd3cda0938496bb) },
4289 };
4290 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
4291 {
4292 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4293 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4294 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4295 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4296 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4297 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) },
4298 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4299 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4300 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40723fe6, 0x8800e95bbf999ba2, 0x9c5ccda0930996bb) },
4301 };
4302 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
4303 {
4304 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4305 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4306 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4307 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4308 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4309 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) },
4310 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4311 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4312 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
4313 };
4314
4315 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4316 {
4317 { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4318 { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4319 { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4320 { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4321 { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4322 { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4323
4324 { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4325 { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4326 { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4327 { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4328 { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4329 { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4330 { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4331 { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4332
4333 { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4334 { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4335 { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4336 { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4337 { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4338 { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4339 };
4340 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4341 {
4342 { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4343 { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4344 { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4345 { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4346 { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4347 { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4348
4349 { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4350 { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4351 { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4352 { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4353 { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4354 { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4355 { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4356 { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4357
4358 { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4359 { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4360 { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4361 { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4362 { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4363 { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4364 };
4365 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4366 {
4367 { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4368 { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4369 { bs3CpuInstr3_pminsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4370 { bs3CpuInstr3_pminsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4371 { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4372 { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4373 { bs3CpuInstr3_vpminsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4374 { bs3CpuInstr3_vpminsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4375 { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4376 { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4377 { bs3CpuInstr3_vpminsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4378 { bs3CpuInstr3_vpminsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4379
4380 { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4381 { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 },
4382 { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4383 { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4384 { bs3CpuInstr3_pminsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4385 { bs3CpuInstr3_pminsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4386 { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4387 { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4388 { bs3CpuInstr3_vpminsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4389 { bs3CpuInstr3_vpminsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4390 { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4391 { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4392 { bs3CpuInstr3_vpminsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4393 { bs3CpuInstr3_vpminsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4394
4395 { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4396 { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4397 { bs3CpuInstr3_pminsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4398 { bs3CpuInstr3_pminsd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4399 { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4400 { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4401 { bs3CpuInstr3_vpminsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4402 { bs3CpuInstr3_vpminsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4403 { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4404 { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4405 { bs3CpuInstr3_vpminsd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4406 { bs3CpuInstr3_vpminsd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
4407 };
4408 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4409 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4410 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4411 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
4412}
4413
4414
4415/*
4416 * [V]MOVSS - move (mem) or merge (reg) scalar single-precision floating-point value.
4417 */
4418BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_XMM1_XMM2_icebp);
4419BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_XMM1_FSxBX_icebp);
4420BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_FSxBX_XMM1_icebp);
4421BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_XMM1_XMM2_icebp);
4422BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp);
4423BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp);
4424extern FNBS3FAR bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64;
4425extern FNBS3FAR bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64;
4426extern FNBS3FAR bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64;
4427extern FNBS3FAR bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64;
4428extern FNBS3FAR bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64;
4429extern FNBS3FAR bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64;
4430
4431BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movss(uint8_t bMode)
4432{
4433 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] =
4434 {
4435 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
4436 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
4437 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4438 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4439 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4440 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x81828384c5c6c7c8) },
4441 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4442 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4443 /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeee77778888) },
4444 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4445 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4446 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0930996bb) },
4447 };
4448 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] =
4449 {
4450 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
4451 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
4452 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4453 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4454 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4455 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000c5c6c7c8) },
4456 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4457 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4458 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000077778888) },
4459 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4460 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4461 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000930996bb) },
4462 };
4463
4464 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4465 {
4466 { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4467 { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4468 { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4469
4470 { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4471 { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4472 { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4473 };
4474 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4475 {
4476 { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4477 { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4478 { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4479
4480 { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4481 { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4482 { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4483 };
4484 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4485 {
4486 { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4487 { bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4488 { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4489 { bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4490 { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4491 { bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4492
4493 { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4494 { bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4495 { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4496 { bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4497 { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4498 { bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4499 };
4500 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4501 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4502 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4503 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
4504}
4505
4506
4507/*
4508 * [V]MOVSD - move (mem) or merge (reg) scalar single-precision floating-point value.
4509 */
4510BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_XMM1_XMM2_icebp);
4511BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_XMM1_FSxBX_icebp);
4512BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_FSxBX_XMM1_icebp);
4513BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp);
4514BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp);
4515BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp);
4516extern FNBS3FAR bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64;
4517extern FNBS3FAR bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64;
4518extern FNBS3FAR bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64;
4519extern FNBS3FAR bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64;
4520extern FNBS3FAR bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64;
4521extern FNBS3FAR bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64;
4522
4523BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsd(uint8_t bMode)
4524{
4525 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] =
4526 {
4527 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
4528 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
4529 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4530 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4531 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4532 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
4533 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
4534 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4535 /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
4536 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4537 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4538 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
4539 };
4540 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] =
4541 {
4542 { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0),
4543 /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0),
4544 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4545 { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4546 /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4547 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8) },
4548 { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4549 /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4550 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x5555666677778888) },
4551 { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4552 /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4553 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb) },
4554 };
4555
4556 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4557 {
4558 { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4559 { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4560 { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4561
4562 { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4563 { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4564 { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4565 };
4566 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4567 {
4568 { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4569 { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4570 { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4571
4572 { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4573 { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4574 { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4575 };
4576 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4577 {
4578 { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4579 { bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4580 { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4581 { bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4582 { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4583 { bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4584
4585 { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4586 { bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR },
4587 { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4588 { bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4589 { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4590 { bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM },
4591 };
4592 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4593 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4594 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4595 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
4596}
4597
4598
4599/*
4600 * [V]MOVLPS - Merge a low qword (two single precision floating-point values)
4601 * from memory with the high qword from a register (SSE destination
4602 * or VEX 2nd source).
4603 * The store variant just stores the high qword.
4604 * [V]MOVLPD - Same, just using double precision floating-point unit.
4605 */
4606BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_XMM1_FSxBX_icebp);
4607BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_FSxBX_XMM1_icebp);
4608BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp);
4609BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp);
4610extern FNBS3FAR bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64;
4611extern FNBS3FAR bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64;
4612extern FNBS3FAR bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64;
4613extern FNBS3FAR bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64;
4614
4615BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp);
4616BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp);
4617BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp);
4618BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp);
4619extern FNBS3FAR bs3CpuInstr3_movlpd_XMM8_FSxBX_icebp_c64;
4620extern FNBS3FAR bs3CpuInstr3_movlpd_FSxBX_XMM11_icebp_c64;
4621extern FNBS3FAR bs3CpuInstr3_vmovlpd_XMM10_XMM14_FSxBX_icebp_c64;
4622extern FNBS3FAR bs3CpuInstr3_vmovlpd_FSxBX_XMM9_icebp_c64;
4623
4624BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movlps_movlpd(uint8_t bMode)
4625{
4626 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] =
4627 {
4628 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4629 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4630 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4631 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4632 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4633 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
4634 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
4635 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4636 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
4637 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4638 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4639 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
4640 };
4641 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] =
4642 {
4643 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4644 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4645 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4646 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4647 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4648 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
4649 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
4650 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4651 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
4652 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4653 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4654 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
4655 };
4656
4657 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4658 {
4659 { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4660 { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4661 { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4662 { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4663
4664 { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4665 { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4666 { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4667 { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4668 };
4669 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4670 {
4671 { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4672 { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4673 { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4674 { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4675
4676 { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4677 { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4678 { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4679 { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4680 };
4681 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4682 {
4683 { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4684 { bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4685 { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4686 { bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4687 { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4688 { bs3CpuInstr3_movlpd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4689 { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4690 { bs3CpuInstr3_movlpd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4691
4692 { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4693 { bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4694 { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4695 { bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4696 { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4697 { bs3CpuInstr3_vmovlpd_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4698 { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4699 { bs3CpuInstr3_vmovlpd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4700 };
4701 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4702 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4703 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4704 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
4705}
4706
4707
4708/*
4709 * [V]MOVHPS - Merge a high qword (two single precision floating-point values)
4710 * from memory with the low qword from a register (SSE destination
4711 * or VEX 2nd source).
4712 * The store variant just stores the high qword.
4713 * [V]MOVHPD - Same, just using double precision floating-point unit.
4714 */
4715BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhps_XMM1_FSxBX_icebp);
4716BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhps_FSxBX_XMM1_icebp);
4717BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp);
4718BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp);
4719extern FNBS3FAR bs3CpuInstr3_movhps_XMM8_FSxBX_icebp_c64;
4720extern FNBS3FAR bs3CpuInstr3_movhps_FSxBX_XMM11_icebp_c64;
4721extern FNBS3FAR bs3CpuInstr3_vmovhps_XMM10_XMM14_FSxBX_icebp_c64;
4722extern FNBS3FAR bs3CpuInstr3_vmovhps_FSxBX_XMM9_icebp_c64;
4723
4724BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp);
4725BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp);
4726BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp);
4727BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp);
4728extern FNBS3FAR bs3CpuInstr3_movhpd_XMM8_FSxBX_icebp_c64;
4729extern FNBS3FAR bs3CpuInstr3_movhpd_FSxBX_XMM11_icebp_c64;
4730extern FNBS3FAR bs3CpuInstr3_vmovhpd_XMM10_XMM14_FSxBX_icebp_c64;
4731extern FNBS3FAR bs3CpuInstr3_vmovhpd_FSxBX_XMM9_icebp_c64;
4732
4733BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movhps_movhpd(uint8_t bMode)
4734{
4735 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] =
4736 {
4737 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4738 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4739 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4740 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4741 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4742 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) },
4743 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
4744 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4745 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x5555666677778888, 0xddddeeeeffff0000) },
4746 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4747 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4748 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb, 0x43d3cda0238499fd) },
4749 };
4750 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] =
4751 {
4752 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4753 /*ign*/ RTUINT256_INIT_C(0, 0, 0, 0),
4754 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4755 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4756 /*ign*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4757 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xd1d2d3d4d5d6d7d8) },
4758 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
4759 /*ign*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4760 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x1111222233334444) },
4761 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4762 /*ign*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4763 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xb4212fa8564c9ba2) },
4764 };
4765
4766 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4767 {
4768 { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4769 { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4770 { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4771 { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4772
4773 { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4774 { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4775 { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4776 { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4777 };
4778 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4779 {
4780 { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4781 { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4782 { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4783 { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4784
4785 { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4786 { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4787 { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4788 { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4789 };
4790 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4791 {
4792 { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4793 { bs3CpuInstr3_movhps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4794 { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4795 { bs3CpuInstr3_movhps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4796 { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4797 { bs3CpuInstr3_movhpd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4798 { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4799 { bs3CpuInstr3_movhpd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
4800
4801 { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4802 { bs3CpuInstr3_vmovhps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4803 { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4804 { bs3CpuInstr3_vmovhps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4805 { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4806 { bs3CpuInstr3_vmovhpd_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
4807 { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4808 { bs3CpuInstr3_vmovhpd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
4809 };
4810 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4811 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4812 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4813 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
4814}
4815
4816
4817/*
4818 * [V]MOVHLPS - Move high qword in source (2) to low qword in destination, leaving
4819 * the high qword in the destination as it was. The VEX variant
4820 * takes the high qword from the first source operand.
4821 */
4822BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhlps_XMM1_XMM2_icebp);
4823BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp);
4824extern FNBS3FAR bs3CpuInstr3_movhlps_XMM8_XMM12_icebp_c64;
4825extern FNBS3FAR bs3CpuInstr3_vmovhlps_XMM10_XMM14_XMM12_icebp_c64;
4826
4827BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movhlps(uint8_t bMode)
4828{
4829 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
4830 {
4831 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4832 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4833 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4834 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4835 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4836 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xd1d2d3d4d5d6d7d8) },
4837 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
4838 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
4839 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x1111222233334444) },
4840 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4841 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4842 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0xb4212fa8564c9ba2) },
4843 };
4844
4845 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4846 {
4847 { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
4848 { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
4849 };
4850 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4851 {
4852 { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
4853 { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
4854 };
4855 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4856 {
4857 { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
4858 { bs3CpuInstr3_movhlps_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 12, RT_ELEMENTS(s_aValues), s_aValues },
4859 { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
4860 { bs3CpuInstr3_vmovhlps_XMM10_XMM14_XMM12_icebp_c64, 255, RM_REG, T_AVX_128, 10, 14, 12, RT_ELEMENTS(s_aValues), s_aValues },
4861 };
4862 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4863 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
4864 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4865 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
4866}
4867
4868
4869/*
4870 * [V]PAVGB - Average unsigned packed byte integers with rounding.
4871 * [V]PAVGW - Average unsigned packed word integers with rounding.
4872 */
4873BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_MM1_MM2_icebp);
4874BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_MM1_FSxBX_icebp);
4875BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_XMM1_XMM2_icebp);
4876BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp);
4877extern FNBS3FAR bs3CpuInstr3_pavgb_XMM8_XMM9_icebp_c64;
4878extern FNBS3FAR bs3CpuInstr3_pavgb_XMM8_FSxBX_icebp_c64;
4879BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp);
4880BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp);
4881extern FNBS3FAR bs3CpuInstr3_vpavgb_XMM8_XMM9_XMM10_icebp_c64;
4882extern FNBS3FAR bs3CpuInstr3_vpavgb_XMM8_XMM9_FSxBX_icebp_c64;
4883BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp);
4884BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp);
4885extern FNBS3FAR bs3CpuInstr3_vpavgb_YMM8_YMM9_YMM10_icebp_c64;
4886extern FNBS3FAR bs3CpuInstr3_vpavgb_YMM8_YMM9_FSxBX_icebp_c64;
4887
4888BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_MM1_MM2_icebp);
4889BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_MM1_FSxBX_icebp);
4890BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_XMM1_XMM2_icebp);
4891BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp);
4892extern FNBS3FAR bs3CpuInstr3_pavgw_XMM8_XMM9_icebp_c64;
4893extern FNBS3FAR bs3CpuInstr3_pavgw_XMM8_FSxBX_icebp_c64;
4894BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp);
4895BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp);
4896extern FNBS3FAR bs3CpuInstr3_vpavgw_XMM8_XMM9_XMM10_icebp_c64;
4897extern FNBS3FAR bs3CpuInstr3_vpavgw_XMM8_XMM9_FSxBX_icebp_c64;
4898BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp);
4899BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp);
4900extern FNBS3FAR bs3CpuInstr3_vpavgw_YMM8_YMM9_YMM10_icebp_c64;
4901extern FNBS3FAR bs3CpuInstr3_vpavgw_YMM8_YMM9_FSxBX_icebp_c64;
4902
4903BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pavgb_pavgw(uint8_t bMode)
4904{
4905 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
4906 {
4907 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4908 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4909 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4910 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4911 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4912 /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) },
4913 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4914 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4915 /* => */ RTUINT256_INIT_C(0x3673e76b3ba053b5, 0x9ca853da536f4b8d, 0x9e118c828b737fb3, 0x7098d78a5b4798dc) },
4916 };
4917 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
4918 {
4919 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
4920 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
4921 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
4922 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
4923 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
4924 /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) },
4925 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
4926 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
4927 /* => */ RTUINT256_INIT_C(0x35f3e6eb3b205335, 0x9c28535a536f4b0d, 0x9e118c828af37f33, 0x7018d70a5b47985c) },
4928 };
4929
4930 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
4931 {
4932 { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4933 { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4934 { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4935 { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4936 { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4937 { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4938 { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4939 { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4940
4941 { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4942 { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4943 { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4944 { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4945 { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4946 { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4947 { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4948 { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4949 };
4950 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
4951 {
4952 { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4953 { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4954 { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4955 { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4956 { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4957 { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4958 { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4959 { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4960
4961 { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4962 { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4963 { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4964 { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4965 { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4966 { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4967 { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4968 { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4969 };
4970 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
4971 {
4972 { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4973 { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4974 { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4975 { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4976 { bs3CpuInstr3_pavgb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4977 { bs3CpuInstr3_pavgb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4978 { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4979 { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4980 { bs3CpuInstr3_vpavgb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4981 { bs3CpuInstr3_vpavgb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4982 { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4983 { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4984 { bs3CpuInstr3_vpavgb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4985 { bs3CpuInstr3_vpavgb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
4986
4987 { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4988 { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4989 { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4990 { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4991 { bs3CpuInstr3_pavgw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4992 { bs3CpuInstr3_pavgw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4993 { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4994 { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4995 { bs3CpuInstr3_vpavgw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4996 { bs3CpuInstr3_vpavgw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4997 { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4998 { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
4999 { bs3CpuInstr3_vpavgw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5000 { bs3CpuInstr3_vpavgw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5001 };
5002 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5003 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5004 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5005 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5006}
5007
5008
5009/*
5010 * [V]PSIGNB - Negate/Zero/Keep the destination packed byte integers based on the sign of the corresponding source operand.
5011 * [V]PSIGNW - Negate/Zero/Keep the destination packed word integers based on the sign of the corresponding source operand.
5012 * [V]PSIGND - Negate/Zero/Keep the destination packed doubleword integers based on the sign of the corresponding source operand.
5013 */
5014BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_MM1_MM2_icebp);
5015BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_MM1_FSxBX_icebp);
5016BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_XMM1_XMM2_icebp);
5017BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_XMM1_FSxBX_icebp);
5018extern FNBS3FAR bs3CpuInstr3_psignb_XMM8_XMM9_icebp_c64;
5019extern FNBS3FAR bs3CpuInstr3_psignb_XMM8_FSxBX_icebp_c64;
5020BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp);
5021BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp);
5022extern FNBS3FAR bs3CpuInstr3_vpsignb_XMM8_XMM9_XMM10_icebp_c64;
5023extern FNBS3FAR bs3CpuInstr3_vpsignb_XMM8_XMM9_FSxBX_icebp_c64;
5024BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp);
5025BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp);
5026extern FNBS3FAR bs3CpuInstr3_vpsignb_YMM8_YMM9_YMM10_icebp_c64;
5027extern FNBS3FAR bs3CpuInstr3_vpsignb_YMM8_YMM9_FSxBX_icebp_c64;
5028
5029BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_MM1_MM2_icebp);
5030BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_MM1_FSxBX_icebp);
5031BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_XMM1_XMM2_icebp);
5032BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_XMM1_FSxBX_icebp);
5033extern FNBS3FAR bs3CpuInstr3_psignw_XMM8_XMM9_icebp_c64;
5034extern FNBS3FAR bs3CpuInstr3_psignw_XMM8_FSxBX_icebp_c64;
5035BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp);
5036BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp);
5037extern FNBS3FAR bs3CpuInstr3_vpsignw_XMM8_XMM9_XMM10_icebp_c64;
5038extern FNBS3FAR bs3CpuInstr3_vpsignw_XMM8_XMM9_FSxBX_icebp_c64;
5039BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp);
5040BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp);
5041extern FNBS3FAR bs3CpuInstr3_vpsignw_YMM8_YMM9_YMM10_icebp_c64;
5042extern FNBS3FAR bs3CpuInstr3_vpsignw_YMM8_YMM9_FSxBX_icebp_c64;
5043
5044BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_MM1_MM2_icebp);
5045BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_MM1_FSxBX_icebp);
5046BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_XMM1_XMM2_icebp);
5047BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_XMM1_FSxBX_icebp);
5048extern FNBS3FAR bs3CpuInstr3_psignd_XMM8_XMM9_icebp_c64;
5049extern FNBS3FAR bs3CpuInstr3_psignd_XMM8_FSxBX_icebp_c64;
5050BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp);
5051BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp);
5052extern FNBS3FAR bs3CpuInstr3_vpsignd_XMM8_XMM9_XMM10_icebp_c64;
5053extern FNBS3FAR bs3CpuInstr3_vpsignd_XMM8_XMM9_FSxBX_icebp_c64;
5054BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp);
5055BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp);
5056extern FNBS3FAR bs3CpuInstr3_vpsignd_YMM8_YMM9_YMM10_icebp_c64;
5057extern FNBS3FAR bs3CpuInstr3_vpsignd_YMM8_YMM9_FSxBX_icebp_c64;
5058
5059BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psignb_psignw_psignd(uint8_t bMode)
5060{
5061 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] =
5062 {
5063 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5064 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5065 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5066 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5067 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5068 /* => */ RTUINT256_INIT_C(0x4f4e4d4c4b4a4948, 0x5f5e5d5c5b5a5958, 0x6f6e6d6c6b6a6968, 0x7f7e7d7c7b7a7978) },
5069 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5070 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5071 /* => */ RTUINT256_INIT_C(0x1edd23ac099d326c, 0xf9a48e14407256cd, 0x7800e9a5bf999e3d, 0xbdd333a0dd846703) },
5072 };
5073 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
5074 {
5075 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5076 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5077 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5078 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5079 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5080 /* => */ RTUINT256_INIT_C(0x4e4e4c4c4a4a4848, 0x5e5e5c5c5a5a5858, 0x6e6e6c6c6a6a6868, 0x7e7e7c7c7a7a7878) },
5081 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5082 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5083 /* => */ RTUINT256_INIT_C(0x1edd225409633294, 0xf95c8eec40725633, 0x7800e95bbf999d3d, 0xbc2d3260dc7c6603) },
5084 };
5085 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
5086 {
5087 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5088 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5089 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5090 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5091 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5092 /* => */ RTUINT256_INIT_C(0x4e4d4c4c4a494848, 0x5e5d5c5c5a595858, 0x6e6d6c6c6a696868, 0x7e7d7c7c7a797878) },
5093 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5094 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5095 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x77ff16a5bf9962c3, 0xbc2c3260dc7b6603) },
5096 };
5097
5098 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5099 {
5100 { bs3CpuInstr3_psignb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5101 { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5102 { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5103 { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5104 { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5105 { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5106 { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5107 { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5108
5109 { bs3CpuInstr3_psignw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5110 { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5111 { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5112 { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5113 { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5114 { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5115 { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5116 { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5117
5118 { bs3CpuInstr3_psignd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5119 { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5120 { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5121 { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5122 { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5123 { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5124 { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5125 { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5126 };
5127 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5128 {
5129 { bs3CpuInstr3_psignb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5130 { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5131 { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5132 { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5133 { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5134 { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5135 { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5136 { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5137
5138 { bs3CpuInstr3_psignw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5139 { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5140 { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5141 { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5142 { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5143 { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5144 { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5145 { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5146
5147 { bs3CpuInstr3_psignd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5148 { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5149 { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5150 { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5151 { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5152 { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5153 { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5154 { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5155 };
5156 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5157 {
5158 { bs3CpuInstr3_psignb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5159 { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5160 { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5161 { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5162 { bs3CpuInstr3_psignb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5163 { bs3CpuInstr3_psignb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5164 { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5165 { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5166 { bs3CpuInstr3_vpsignb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5167 { bs3CpuInstr3_vpsignb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5168 { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5169 { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5170 { bs3CpuInstr3_vpsignb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5171 { bs3CpuInstr3_vpsignb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
5172
5173 { bs3CpuInstr3_psignw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5174 { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5175 { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5176 { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5177 { bs3CpuInstr3_psignw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5178 { bs3CpuInstr3_psignw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5179 { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5180 { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5181 { bs3CpuInstr3_vpsignw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5182 { bs3CpuInstr3_vpsignw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5183 { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5184 { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5185 { bs3CpuInstr3_vpsignw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5186 { bs3CpuInstr3_vpsignw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
5187
5188 { bs3CpuInstr3_psignd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5189 { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5190 { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5191 { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5192 { bs3CpuInstr3_psignd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5193 { bs3CpuInstr3_psignd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5194 { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5195 { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5196 { bs3CpuInstr3_vpsignd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5197 { bs3CpuInstr3_vpsignd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5198 { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5199 { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5200 { bs3CpuInstr3_vpsignd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5201 { bs3CpuInstr3_vpsignd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
5202 };
5203 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5204 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5205 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5206 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5207}
5208
5209
5210/*
5211 * [V]PHADDW - Horizontally add word sized signed integers.
5212 * [V]PHADDD - Horizontally add doubleword sized signed integers.
5213 */
5214BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_MM1_MM2_icebp);
5215BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_MM1_FSxBX_icebp);
5216BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_XMM1_XMM2_icebp);
5217BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp);
5218extern FNBS3FAR bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64;
5219extern FNBS3FAR bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64;
5220BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp);
5221BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp);
5222extern FNBS3FAR bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64;
5223extern FNBS3FAR bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64;
5224BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp);
5225BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp);
5226extern FNBS3FAR bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64;
5227extern FNBS3FAR bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64;
5228
5229BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_MM1_MM2_icebp);
5230BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_MM1_FSxBX_icebp);
5231BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_XMM1_XMM2_icebp);
5232BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp);
5233extern FNBS3FAR bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64;
5234extern FNBS3FAR bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64;
5235BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp);
5236BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp);
5237extern FNBS3FAR bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64;
5238extern FNBS3FAR bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64;
5239BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp);
5240BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp);
5241extern FNBS3FAR bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64;
5242extern FNBS3FAR bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64;
5243
5244BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddw_phaddd(uint8_t bMode)
5245{
5246 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] =
5247 {
5248 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5249 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5250 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5251 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5252 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5253 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e05060d0e) },
5254 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5255 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5256 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x7ccf29c41173bd81) },
5257 };
5258 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] =
5259 {
5260 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5261 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5262 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5263 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5264 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5265 /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) },
5266 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5267 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5268 /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) },
5269 };
5270 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] =
5271 {
5272 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5273 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5274 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5275 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5276 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5277 /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x65666d6e45464d4e, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) },
5278 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5279 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5280 /* => */ RTUINT256_INIT_C(0x3d33e0b156bca651, 0xfc893bf7884896a5, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) },
5281 };
5282 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] =
5283 {
5284 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5285 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5286 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5287 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5288 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5289 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x87898b8c07090b0c) },
5290 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5291 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5292 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x2f66772e6758679d) },
5293 };
5294 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] =
5295 {
5296 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5297 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5298 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5299 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5300 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5301 /* => */ RTUINT256_INIT_C( 9, 10, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) },
5302 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5303 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5304 /* => */ RTUINT256_INIT_C( 13, 14, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) },
5305 };
5306 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] =
5307 {
5308 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5309 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5310 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5311 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5312 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5313 /* => */ RTUINT256_INIT_C(0xe7e9ebecc7c9cbcc, 0x67696b6c47494b4c, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) },
5314 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5315 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5316 /* => */ RTUINT256_INIT_C(0xb9e663ffa55f57ae, 0x2841104039cee51f, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) },
5317 };
5318
5319 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5320 {
5321 { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5322 { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5323 { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5324 { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5325 { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5326 { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5327 { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5328 { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5329
5330 { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5331 { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5332 { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5333 { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5334 { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5335 { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5336 { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5337 { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5338 };
5339 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5340 {
5341 { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5342 { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5343 { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5344 { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5345 { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5346 { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5347 { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5348 { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5349
5350 { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5351 { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5352 { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5353 { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5354 { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5355 { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5356 { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5357 { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5358 };
5359 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5360 {
5361 { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5362 { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5363 { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5364 { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5365 { bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5366 { bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5367 { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5368 { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5369 { bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5370 { bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5371 { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5372 { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5373 { bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5374 { bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5375
5376 { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5377 { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5378 { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5379 { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5380 { bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5381 { bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5382 { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5383 { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5384 { bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5385 { bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5386 { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5387 { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5388 { bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5389 { bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5390 };
5391 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5392 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5393 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5394 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5395}
5396
5397
5398/*
5399 * [V]PHSUBW - Horizontally subtract word sized signed integers.
5400 * [V]PHSUBD - Horizontally subtract doubleword sized signed integers.
5401 */
5402BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_MM1_MM2_icebp);
5403BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_MM1_FSxBX_icebp);
5404BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_XMM1_XMM2_icebp);
5405BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp);
5406extern FNBS3FAR bs3CpuInstr3_phsubw_XMM8_XMM9_icebp_c64;
5407extern FNBS3FAR bs3CpuInstr3_phsubw_XMM8_FSxBX_icebp_c64;
5408BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp);
5409BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp);
5410extern FNBS3FAR bs3CpuInstr3_vphsubw_XMM8_XMM9_XMM10_icebp_c64;
5411extern FNBS3FAR bs3CpuInstr3_vphsubw_XMM8_XMM9_FSxBX_icebp_c64;
5412BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp);
5413BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp);
5414extern FNBS3FAR bs3CpuInstr3_vphsubw_YMM8_YMM9_YMM10_icebp_c64;
5415extern FNBS3FAR bs3CpuInstr3_vphsubw_YMM8_YMM9_FSxBX_icebp_c64;
5416
5417BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_MM1_MM2_icebp);
5418BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_MM1_FSxBX_icebp);
5419BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_XMM1_XMM2_icebp);
5420BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp);
5421extern FNBS3FAR bs3CpuInstr3_phsubd_XMM8_XMM9_icebp_c64;
5422extern FNBS3FAR bs3CpuInstr3_phsubd_XMM8_FSxBX_icebp_c64;
5423BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp);
5424BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp);
5425extern FNBS3FAR bs3CpuInstr3_vphsubd_XMM8_XMM9_XMM10_icebp_c64;
5426extern FNBS3FAR bs3CpuInstr3_vphsubd_XMM8_XMM9_FSxBX_icebp_c64;
5427BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp);
5428BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp);
5429extern FNBS3FAR bs3CpuInstr3_vphsubd_YMM8_YMM9_YMM10_icebp_c64;
5430extern FNBS3FAR bs3CpuInstr3_vphsubd_YMM8_YMM9_FSxBX_icebp_c64;
5431
5432BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phsubw_phsubd(uint8_t bMode)
5433{
5434 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] =
5435 {
5436 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5437 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5438 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5439 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5440 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5441 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0202020202020202) },
5442 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5443 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5444 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x441703b289cd7679) },
5445 };
5446 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] =
5447 {
5448 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5449 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5450 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5451 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5452 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5453 /* => */ RTUINT256_INIT_C( 9, 10, 0x0202020202020202, 0x0202020202020202) },
5454 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5455 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5456 /* => */ RTUINT256_INIT_C( 13, 14, 0x7b874556441703b2, 0x615ba32a89cd7679) },
5457 };
5458 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] =
5459 {
5460 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5461 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5462 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5463 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5464 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5465 /* => */ RTUINT256_INIT_C(0x0202020202020202, 0x0202020202020202, 0x0202020202020202, 0x0202020202020202) },
5466 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5467 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5468 /* => */ RTUINT256_INIT_C(0xa32106f9d8d4d97b, 0xbecf2931959015c1, 0x7b874556441703b2, 0x615ba32a89cd7679) },
5469 };
5470 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] =
5471 {
5472 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5473 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5474 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5475 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5476 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5477 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0404040404040404) },
5478 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5479 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5480 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0xf6acb648dfb0cc5d) },
5481 };
5482 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] =
5483 {
5484 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5485 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5486 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5487 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5488 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5489 /* => */ RTUINT256_INIT_C( 9, 10, 0x0404040404040404, 0x0404040404040404) },
5490 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5491 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5492 /* => */ RTUINT256_INIT_C( 13, 14, 0xa22b6bfaf6acb648, 0x37987968dfb0cc5d) },
5493 };
5494 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] =
5495 {
5496 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5497 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5498 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5499 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5500 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5501 /* => */ RTUINT256_INIT_C(0x0404040404040404, 0x0404040404040404, 0x0404040404040404, 0x0404040404040404) },
5502 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5503 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5504 /* => */ RTUINT256_INIT_C(0x1fd283ab2777281e, 0xea8554e84715c747, 0xa22b6bfaf6acb648, 0x37987968dfb0cc5d) },
5505 };
5506
5507 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5508 {
5509 { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5510 { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5511 { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5512 { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5513 { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5514 { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5515 { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5516 { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5517
5518 { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5519 { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5520 { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5521 { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5522 { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5523 { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5524 { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5525 { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5526 };
5527 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5528 {
5529 { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5530 { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5531 { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5532 { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5533 { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5534 { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5535 { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5536 { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5537
5538 { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5539 { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5540 { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5541 { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5542 { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5543 { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5544 { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5545 { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5546 };
5547 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5548 {
5549 { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5550 { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5551 { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5552 { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5553 { bs3CpuInstr3_phsubw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5554 { bs3CpuInstr3_phsubw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5555 { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5556 { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5557 { bs3CpuInstr3_vphsubw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5558 { bs3CpuInstr3_vphsubw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5559 { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5560 { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5561 { bs3CpuInstr3_vphsubw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5562 { bs3CpuInstr3_vphsubw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5563
5564 { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5565 { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D },
5566 { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5567 { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5568 { bs3CpuInstr3_phsubd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5569 { bs3CpuInstr3_phsubd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5570 { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5571 { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5572 { bs3CpuInstr3_vphsubd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5573 { bs3CpuInstr3_vphsubd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D },
5574 { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5575 { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5576 { bs3CpuInstr3_vphsubd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5577 { bs3CpuInstr3_vphsubd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D },
5578 };
5579 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5580 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5581 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5582 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5583}
5584
5585
5586/*
5587 * [V]PHADDSW - Horizontally add and saturate word sized signed integers.
5588 */
5589BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_MM1_MM2_icebp);
5590BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp);
5591BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp);
5592BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp);
5593extern FNBS3FAR bs3CpuInstr3_phaddsw_XMM8_XMM9_icebp_c64;
5594extern FNBS3FAR bs3CpuInstr3_phaddsw_XMM8_FSxBX_icebp_c64;
5595BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp);
5596BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp);
5597extern FNBS3FAR bs3CpuInstr3_vphaddsw_XMM8_XMM9_XMM10_icebp_c64;
5598extern FNBS3FAR bs3CpuInstr3_vphaddsw_XMM8_XMM9_FSxBX_icebp_c64;
5599BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp);
5600BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp);
5601extern FNBS3FAR bs3CpuInstr3_vphaddsw_YMM8_YMM9_YMM10_icebp_c64;
5602extern FNBS3FAR bs3CpuInstr3_vphaddsw_YMM8_YMM9_FSxBX_icebp_c64;
5603
5604BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddsw(uint8_t bMode)
5605{
5606 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] =
5607 {
5608 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5609 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5610 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5611 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5612 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5613 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e80008000) },
5614 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5615 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5616 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x800080001173bd81) },
5617 };
5618 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] =
5619 {
5620 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5621 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5622 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5623 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5624 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5625 /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x8000800080008000) },
5626 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5627 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5628 /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee80008000, 0x8000225c1173bd81) },
5629 };
5630 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] =
5631 {
5632 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5633 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5634 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5635 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5636 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5637 /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x8000800080008000, 0xa5a6adae85868d8e, 0x8000800080008000) },
5638 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5639 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5640 /* => */ RTUINT256_INIT_C(0x3d337fff56bc7fff, 0xfc893bf788487fff, 0xe3c9f1ee80008000, 0x8000225c1173bd81) },
5641 };
5642
5643 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5644 {
5645 { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5646 { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5647 { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5648 { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5649 { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5650 { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5651 { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5652 { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5653 };
5654 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5655 {
5656 { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5657 { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5658 { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5659 { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5660 { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5661 { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5662 { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5663 { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5664 };
5665 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5666 {
5667 { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5668 { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5669 { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5670 { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5671 { bs3CpuInstr3_phaddsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5672 { bs3CpuInstr3_phaddsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5673 { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5674 { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5675 { bs3CpuInstr3_vphaddsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5676 { bs3CpuInstr3_vphaddsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5677 { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5678 { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5679 { bs3CpuInstr3_vphaddsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5680 { bs3CpuInstr3_vphaddsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5681 };
5682 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5683 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5684 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5685 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5686}
5687
5688
5689/*
5690 * [V]PHSUBSW - Horizontally subtract and saturate word sized signed integers.
5691 */
5692BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_MM1_MM2_icebp);
5693BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp);
5694BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp);
5695BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp);
5696extern FNBS3FAR bs3CpuInstr3_phsubsw_XMM8_XMM9_icebp_c64;
5697extern FNBS3FAR bs3CpuInstr3_phsubsw_XMM8_FSxBX_icebp_c64;
5698BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp);
5699BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp);
5700extern FNBS3FAR bs3CpuInstr3_vphsubsw_XMM8_XMM9_XMM10_icebp_c64;
5701extern FNBS3FAR bs3CpuInstr3_vphsubsw_XMM8_XMM9_FSxBX_icebp_c64;
5702BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp);
5703BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp);
5704extern FNBS3FAR bs3CpuInstr3_vphsubsw_YMM8_YMM9_YMM10_icebp_c64;
5705extern FNBS3FAR bs3CpuInstr3_vphsubsw_YMM8_YMM9_FSxBX_icebp_c64;
5706
5707BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phsubsw(uint8_t bMode)
5708{
5709 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] =
5710 {
5711 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5712 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5713 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5714 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5715 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5716 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0202020202020202) },
5717 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5718 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5719 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x441703b289cd8000) },
5720 };
5721 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] =
5722 {
5723 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5724 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5725 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5726 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5727 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5728 /* => */ RTUINT256_INIT_C( 9, 10, 0x0202020202020202, 0x0202020202020202) },
5729 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5730 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5731 /* => */ RTUINT256_INIT_C( 13, 14, 0x7b878000441703b2, 0x615b7fff89cd8000) },
5732 };
5733 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] =
5734 {
5735 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5736 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5737 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5738 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5739 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5740 /* => */ RTUINT256_INIT_C(0x0202020202020202, 0x0202020202020202, 0x0202020202020202, 0x0202020202020202) },
5741 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5742 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5743 /* => */ RTUINT256_INIT_C(0xa32106f9d8d4d97b, 0xbecf2931959015c1, 0x7b878000441703b2, 0x615b7fff89cd8000) },
5744 };
5745
5746 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5747 {
5748 { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5749 { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5750 { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5751 { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5752 { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5753 { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5754 { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5755 { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5756 };
5757 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5758 {
5759 { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5760 { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5761 { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5762 { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5763 { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5764 { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5765 { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5766 { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5767 };
5768 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5769 {
5770 { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5771 { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5772 { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5773 { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5774 { bs3CpuInstr3_phsubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5775 { bs3CpuInstr3_phsubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5776 { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5777 { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5778 { bs3CpuInstr3_vphsubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5779 { bs3CpuInstr3_vphsubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5780 { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5781 { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5782 { bs3CpuInstr3_vphsubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5783 { bs3CpuInstr3_vphsubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5784 };
5785 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5786 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5787 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5788 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5789}
5790
5791
5792/*
5793 * [V]PMADDUBSW - Horizontally subtract and saturate word sized signed integers.
5794 */
5795BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp);
5796BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp);
5797BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp);
5798BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp);
5799extern FNBS3FAR bs3CpuInstr3_pmaddubsw_XMM8_XMM9_icebp_c64;
5800extern FNBS3FAR bs3CpuInstr3_pmaddubsw_XMM8_FSxBX_icebp_c64;
5801BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp);
5802BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp);
5803extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_XMM10_icebp_c64;
5804extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_FSxBX_icebp_c64;
5805BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp);
5806BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp);
5807extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_YMM10_icebp_c64;
5808extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_FSxBX_icebp_c64;
5809
5810BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaddubsw(uint8_t bMode)
5811{
5812 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] =
5813 {
5814 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5815 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5816 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5817 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5818 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5819 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xc0c5c1d9c2fdc431) },
5820 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5821 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5822 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x31a82e40f5bd8000) },
5823 };
5824 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] =
5825 {
5826 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5827 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5828 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5829 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5830 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5831 /* => */ RTUINT256_INIT_C( 9, 10, 0xcb25ccb9ce5dd011, 0xc0c5c1d9c2fdc431) },
5832 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5833 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5834 /* => */ RTUINT256_INIT_C( 13, 14, 0xd7a00b7f6d9691bc, 0x31a82e40f5bd8000) },
5835 };
5836 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] =
5837 {
5838 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5839 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5840 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5841 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5842 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5843 /* => */ RTUINT256_INIT_C(0xebe5ee79f11df3d1, 0xd985db99ddbddff1, 0xcb25ccb9ce5dd011, 0xc0c5c1d9c2fdc431) },
5844 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5845 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5846 /* => */ RTUINT256_INIT_C(0x10cb0e68f5e0fd9a, 0x37fed92249260ffc, 0xd7a00b7f6d9691bc, 0x31a82e40f5bd8000) },
5847 };
5848
5849 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5850 {
5851 { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5852 { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5853 { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5854 { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5855 { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5856 { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5857 { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5858 { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5859 };
5860 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5861 {
5862 { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5863 { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5864 { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5865 { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5866 { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5867 { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5868 { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5869 { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5870 };
5871 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5872 {
5873 { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5874 { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W },
5875 { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5876 { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5877 { bs3CpuInstr3_pmaddubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5878 { bs3CpuInstr3_pmaddubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5879 { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5880 { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5881 { bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5882 { bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W },
5883 { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5884 { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5885 { bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5886 { bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W },
5887 };
5888 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5889 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5890 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5891 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5892}
5893
5894
5895/*
5896 * [V]PMULHRSW - Vertically multiply, round and scale word sized signed integers and extract the high 16-bits.
5897 */
5898BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp);
5899BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp);
5900BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp);
5901BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp);
5902extern FNBS3FAR bs3CpuInstr3_pmulhrsw_XMM8_XMM9_icebp_c64;
5903extern FNBS3FAR bs3CpuInstr3_pmulhrsw_XMM8_FSxBX_icebp_c64;
5904BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp);
5905BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp);
5906extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_XMM10_icebp_c64;
5907extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_FSxBX_icebp_c64;
5908BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp);
5909BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp);
5910extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_YMM10_icebp_c64;
5911extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_FSxBX_icebp_c64;
5912
5913BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhrsw(uint8_t bMode)
5914{
5915 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
5916 {
5917 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5918 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5919 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5920 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
5921 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
5922 /* => */ RTUINT256_INIT_C(0x0899072e05d40489, 0x16341448126d10a1, 0x27d7256a230e20c1, 0x3d823a9437b734e9) },
5923 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
5924 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
5925 /* => */ RTUINT256_INIT_C(0x1293043f07fc2dc5, 0xfcbceafe33912b08, 0x4721f792d495b28f, 0xcb340c6be1c453e5) },
5926 };
5927
5928 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
5929 {
5930 { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
5931 { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
5932 { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
5933 { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
5934 { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
5935 { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
5936 { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
5937 { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
5938 };
5939 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
5940 {
5941 { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
5942 { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
5943 { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
5944 { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
5945 { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
5946 { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
5947 { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
5948 { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
5949 };
5950 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
5951 {
5952 { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
5953 { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
5954 { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
5955 { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
5956 { bs3CpuInstr3_pmulhrsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues },
5957 { bs3CpuInstr3_pmulhrsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues },
5958 { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
5959 { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
5960 { bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
5961 { bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
5962 { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
5963 { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
5964 { bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
5965 { bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
5966 };
5967 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5968 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
5969 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5970 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
5971}
5972
5973
5974/*
5975 * [V]PSADBW - Compute sum of absolute differences of packed unsigned byte integers.
5976 */
5977BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_MM1_MM2_icebp);
5978BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_MM1_FSxBX_icebp);
5979BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_XMM1_XMM2_icebp);
5980BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp);
5981extern FNBS3FAR bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64;
5982extern FNBS3FAR bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64;
5983BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp);
5984BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp);
5985extern FNBS3FAR bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64;
5986extern FNBS3FAR bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64;
5987BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp);
5988BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp);
5989extern FNBS3FAR bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64;
5990extern FNBS3FAR bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64;
5991
5992BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psadbw(uint8_t bMode)
5993{
5994 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
5995 {
5996 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
5997 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
5998 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
5999 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
6000 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
6001 /* => */ RTUINT256_INIT_C(0x0000000000000200, 0x0000000000000200, 0x0000000000000200, 0x0000000000000200) },
6002 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
6003 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
6004 /* => */ RTUINT256_INIT_C(0x00000000000002f6, 0x00000000000002e5, 0x0000000000000264, 0x0000000000000240) },
6005 };
6006
6007 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
6008 {
6009 { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6010 { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6011 { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6012 { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6013 { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6014 { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6015 { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6016 { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6017 };
6018 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
6019 {
6020 { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6021 { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6022 { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6023 { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6024 { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6025 { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6026 { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6027 { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6028 };
6029 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
6030 {
6031 { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6032 { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6033 { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6034 { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6035 { bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues },
6036 { bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues },
6037 { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6038 { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6039 { bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
6040 { bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
6041 { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6042 { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6043 { bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
6044 { bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
6045 };
6046 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6047 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
6048 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6049 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
6050}
6051
6052
6053/*
6054 * [V]PMULDQ - Multiply packed signed double word integers.
6055 */
6056BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp);
6057BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp);
6058extern FNBS3FAR bs3CpuInstr3_pmuldq_XMM8_XMM9_icebp_c64;
6059extern FNBS3FAR bs3CpuInstr3_pmuldq_XMM8_FSxBX_icebp_c64;
6060BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp);
6061BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp);
6062extern FNBS3FAR bs3CpuInstr3_vpmuldq_XMM8_XMM9_XMM10_icebp_c64;
6063extern FNBS3FAR bs3CpuInstr3_vpmuldq_XMM8_XMM9_FSxBX_icebp_c64;
6064BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp);
6065BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp);
6066extern FNBS3FAR bs3CpuInstr3_vpmuldq_YMM8_YMM9_YMM10_icebp_c64;
6067extern FNBS3FAR bs3CpuInstr3_vpmuldq_YMM8_YMM9_FSxBX_icebp_c64;
6068
6069BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmuldq(uint8_t bMode)
6070{
6071 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
6072 {
6073 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
6074 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
6075 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
6076 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
6077 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
6078 /* => */ RTUINT256_INIT_C(0x02e97bbaf7148240, 0x0935ee3369408840, 0x118666b3e1709040, 0x1bdae53c5fa49a40) },
6079 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
6080 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
6081 /* => */ RTUINT256_INIT_C(0x03fdeed546719124, 0x19c88e386340fed2, 0xea4a418ff1c09066, 0xf0e1df0254fbb9cf) },
6082 };
6083
6084 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
6085 {
6086 { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6087 { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6088 { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6089 { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6090 { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6091 { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6092 };
6093 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
6094 {
6095 { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6096 { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6097 { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6098 { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6099 { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6100 { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6101 };
6102 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
6103 {
6104 { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6105 { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6106 { bs3CpuInstr3_pmuldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues },
6107 { bs3CpuInstr3_pmuldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues },
6108 { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6109 { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6110 { bs3CpuInstr3_vpmuldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
6111 { bs3CpuInstr3_vpmuldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
6112 { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6113 { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6114 { bs3CpuInstr3_vpmuldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
6115 { bs3CpuInstr3_vpmuldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
6116 };
6117 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6118 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
6119 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6120 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
6121}
6122
6123
6124/*
6125 * [V]PMULUDQ - Multiply packed unsigned double word integers.
6126 */
6127BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_MM1_MM2_icebp);
6128BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp);
6129BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp);
6130BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp);
6131extern FNBS3FAR bs3CpuInstr3_pmuludq_XMM8_XMM9_icebp_c64;
6132extern FNBS3FAR bs3CpuInstr3_pmuludq_XMM8_FSxBX_icebp_c64;
6133BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp);
6134BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp);
6135extern FNBS3FAR bs3CpuInstr3_vpmuludq_XMM8_XMM9_XMM10_icebp_c64;
6136extern FNBS3FAR bs3CpuInstr3_vpmuludq_XMM8_XMM9_FSxBX_icebp_c64;
6137BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp);
6138BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp);
6139extern FNBS3FAR bs3CpuInstr3_vpmuludq_YMM8_YMM9_YMM10_icebp_c64;
6140extern FNBS3FAR bs3CpuInstr3_vpmuludq_YMM8_YMM9_FSxBX_icebp_c64;
6141
6142BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmuludq(uint8_t bMode)
6143{
6144 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
6145 {
6146 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
6147 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
6148 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
6149 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
6150 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
6151 /* => */ RTUINT256_INIT_C(0xae972b6af7148240, 0x94c37dc369408840, 0x7cf3d623e1709040, 0x6728348c5fa49a40) },
6152 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
6153 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
6154 /* => */ RTUINT256_INIT_C(0x03fdeed546719124, 0x19c88e386340fed2, 0x4096dd31f1c09066, 0x146678ff54fbb9cf) },
6155 };
6156
6157 static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
6158 {
6159 { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6160 { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6161 { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6162 { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6163 { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6164 { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6165 { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6166 { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6167 };
6168 static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
6169 {
6170 { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6171 { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6172 { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6173 { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6174 { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6175 { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6176 { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6177 { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6178 };
6179 static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
6180 {
6181 { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6182 { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6183 { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
6184 { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6185 { bs3CpuInstr3_pmuludq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues },
6186 { bs3CpuInstr3_pmuludq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues },
6187 { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6188 { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6189 { bs3CpuInstr3_vpmuludq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
6190 { bs3CpuInstr3_vpmuludq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
6191 { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues },
6192 { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues },
6193 { bs3CpuInstr3_vpmuludq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues },
6194 { bs3CpuInstr3_vpmuludq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
6195 };
6196 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6197 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
6198 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6199 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
6200}
6201
6202
6203/*
6204 * Test type #2 - GPR <- MM/XMM/YMM, no VVVV.
6205 */
6206
6207typedef struct BS3CPUINSTR3_TEST2_VALUES_T
6208{
6209 RTUINT256U uMedia;
6210 uint64_t uGpr;
6211} BS3CPUINSTR3_TEST2_VALUES_T;
6212
6213typedef struct BS3CPUINSTR3_TEST2_T
6214{
6215 FPFNBS3FAR pfnWorker;
6216 uint8_t bAvxMisalignXcpt;
6217 uint8_t enmRm;
6218 uint8_t enmType;
6219 uint8_t cbGpr;
6220 uint8_t cBitsGprValMask;
6221 bool fInvalidEncoding;
6222 bool fGprDst;
6223 uint8_t iGprReg;
6224 uint8_t iMediaReg;
6225 uint8_t cValues;
6226 BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues;
6227} BS3CPUINSTR3_TEST2_T;
6228
6229typedef struct BS3CPUINSTR3_TEST2_MODE_T
6230{
6231 BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests;
6232 unsigned cTests;
6233} BS3CPUINSTR3_TEST2_MODE_T;
6234
6235/** Initializer for a BS3CPUINSTR3_TEST2_MODE_T array (three entries). */
6236#define BS3CPUINSTR3_TEST2_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
6237 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
6238
6239
6240/**
6241 * Test type #2 worker.
6242 */
6243static uint8_t bs3CpuInstr3_WorkerTestType2(uint8_t bMode, BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests, unsigned cTests,
6244 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs)
6245{
6246 BS3REGCTX Ctx;
6247 BS3TRAPFRAME TrapFrame;
6248 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
6249 uint8_t BS3_FAR *pbBuf = g_pbBuf;
6250 uint32_t cbBuf = g_cbBuf;
6251 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
6252 PBS3EXTCTX pExtCtxOut;
6253 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
6254 if (!pExtCtx)
6255 return 0;
6256
6257 /* Ensure the structures are allocated before we sample the stack pointer. */
6258 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
6259 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
6260
6261 /*
6262 * Create test context.
6263 */
6264 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
6265 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
6266 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
6267
6268 /*
6269 * Run the tests in all rings since alignment issues may behave
6270 * differently in ring-3 compared to ring-0.
6271 */
6272 for (;;)
6273 {
6274 unsigned iCfg;
6275 for (iCfg = 0; iCfg < cConfigs; iCfg++)
6276 {
6277 unsigned iTest;
6278 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
6279 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
6280 continue; /* unsupported config */
6281
6282 /*
6283 * Iterate the tests.
6284 */
6285 for (iTest = 0; iTest < cTests; iTest++)
6286 {
6287 BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
6288 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
6289 unsigned const cValues = paTests[iTest].cValues;
6290 bool const fGprDst = paTests[iTest].fGprDst;
6291 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
6292 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
6293 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
6294 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
6295 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
6296 uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm);
6297 uint8_t const cbAlign = RT_MIN(cbOperand, 16);
6298 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
6299 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType]
6300 || paTests[iTest].fInvalidEncoding ? X86_XCPT_UD
6301 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
6302 : fSseInstr ? paConfigs[iCfg].bXcptSse
6303 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
6304 uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX
6305 : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1;
6306 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
6307 unsigned iVal;
6308
6309 /* If testing unaligned memory accesses, skip register-only tests. This allows
6310 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
6311 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
6312 continue;
6313
6314 /* #AC is only raised in ring-3.: */
6315 if (bXcptExpect == X86_XCPT_AC)
6316 {
6317 if (bRing != 3)
6318 bXcptExpect = X86_XCPT_DB;
6319 else if (fAvxInstr)
6320 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
6321 }
6322
6323 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
6324
6325 /*
6326 * Iterate the test values and do the actual testing.
6327 */
6328 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
6329 {
6330 uint16_t cErrors;
6331 uint16_t uSavedFtw = 0xff;
6332 RTUINT256U uMemOpExpect;
6333
6334 /*
6335 * Set up the context and some expectations.
6336 */
6337 if (fGprDst)
6338 {
6339 /* dest - gpr/mem */
6340 if (paTests[iTest].iGprReg == UINT8_MAX)
6341 {
6342 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
6343 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
6344 if (bXcptExpect != X86_XCPT_DB)
6345 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
6346 else
6347 {
6348 Bs3MemSet(&uMemOpExpect, 0xaa, sizeof(uMemOpExpect));
6349 switch (paTests[iTest].cbGpr)
6350 {
6351 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break;
6352 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break;
6353 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break;
6354 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break;
6355 default: BS3_ASSERT(0);
6356 }
6357 }
6358 }
6359 else
6360 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, UINT64_C(0xcccccccccccccccc),
6361 BS3_MODE_IS_64BIT_CODE(bMode) ? 8 : 4); /* we only restore 63:32 when bMode==LM64 */
6362
6363 /* source - media/mem */
6364 if (paTests[iTest].iMediaReg == UINT8_MAX)
6365 {
6366 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
6367 BS3_ASSERT(paTests[iTest].iGprReg != UINT8_MAX);
6368 Bs3MemCpy(puMemOp, &paValues[iVal].uMedia, cbMemOp);
6369 uMemOpExpect = paValues[iVal].uMedia;
6370 }
6371 else if (fMmxInstr)
6372 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
6373 else if (fSseInstr)
6374 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0);
6375 else
6376 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32);
6377 }
6378 else
6379 {
6380 /* dest - media */
6381 if (paTests[iTest].iMediaReg == UINT8_MAX)
6382 {
6383 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
6384 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
6385 if (bXcptExpect == X86_XCPT_DB)
6386 uMemOpExpect = paValues[iVal].uMedia;
6387 else
6388 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
6389 }
6390
6391 /* source - gpr/mem */
6392 if (paTests[iTest].iGprReg == UINT8_MAX)
6393 {
6394 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
6395 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
6396 if (bXcptExpect == X86_XCPT_DB)
6397 switch (paTests[iTest].cbGpr)
6398 {
6399 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break;
6400 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break;
6401 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break;
6402 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break;
6403 default: BS3_ASSERT(0);
6404 }
6405 Bs3MemCpy(puMemOp, &uMemOpExpect, cbMemOp);
6406 }
6407 else
6408 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr);
6409 }
6410
6411 /* Memory pointer. */
6412 if (paTests[iTest].enmRm >= RM_MEM)
6413 {
6414 BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaReg == UINT8_MAX);
6415 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
6416 }
6417
6418 /*
6419 * Execute.
6420 */
6421 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
6422
6423 /*
6424 * Check the result:
6425 */
6426 cErrors = Bs3TestSubErrorCount();
6427
6428 if (fMmxInstr && bXcptExpect == X86_XCPT_DB)
6429 {
6430 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
6431 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
6432 }
6433 if (!fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iMediaReg != UINT8_MAX)
6434 {
6435 if (fMmxInstr)
6436 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_SET);
6437 else if (fSseInstr)
6438 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0);
6439 else
6440 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32);
6441 }
6442 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
6443
6444 if (TrapFrame.bXcpt != bXcptExpect)
6445 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
6446
6447 if (fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iGprReg != UINT8_MAX)
6448 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask,
6449 paTests[iTest].cbGpr >= 4 ? 8 : paTests[iTest].cbGpr);
6450 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
6451 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
6452 {
6453 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
6454 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
6455 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
6456 }
6457 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
6458 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
6459 pszMode, idTestStep);
6460
6461 if ( paTests[iTest].enmRm >= RM_MEM
6462 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
6463 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
6464
6465 if (cErrors != Bs3TestSubErrorCount())
6466 {
6467 if (paConfigs[iCfg].fAligned)
6468 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
6469 bRing, iCfg, iTest, iVal, bXcptExpect);
6470 else
6471 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
6472 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
6473 Bs3TestPrintf("\n");
6474 }
6475
6476 if (uSavedFtw != 0xff)
6477 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
6478 }
6479 }
6480
6481 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
6482 }
6483
6484 /*
6485 * Next ring.
6486 */
6487 bRing++;
6488 if (bRing > 3 || bMode == BS3_MODE_RM)
6489 break;
6490 Bs3RegCtxConvertToRingX(&Ctx, bRing);
6491 }
6492
6493 /*
6494 * Cleanup.
6495 */
6496 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
6497 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
6498 return 0;
6499}
6500
6501
6502/*
6503 * PMOVMSKB, VPMOVMSKB.
6504 */
6505BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_MM2_icebp);
6506BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp);
6507BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp);
6508BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp);
6509BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp);
6510BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp);
6511BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp);
6512BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp);
6513extern FNBS3FAR bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64;
6514
6515BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovmskb(uint8_t bMode)
6516{
6517 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues[] =
6518 {
6519 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) },
6520 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffff) },
6521 { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00000000) },
6522 { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xffffffff) },
6523 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x03000003) },
6524 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x255193ab) },
6525 };
6526
6527 static BS3CPUINSTR3_TEST2_T const s_aTests16[] =
6528 {
6529 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6530 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6531 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6532 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6533 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6534 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6535 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6536 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6537 };
6538 static BS3CPUINSTR3_TEST2_T const s_aTests32[] =
6539 {
6540 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6541 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6542 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6543 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6544 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6545 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6546 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6547 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6548 };
6549 static BS3CPUINSTR3_TEST2_T const s_aTests64[] =
6550 {
6551 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 8, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6552 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 8, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6553 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6554 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6555 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6556 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6557 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },
6558 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 8, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
6559 { bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 9, RT_ELEMENTS(s_aValues), s_aValues },
6560 };
6561 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6562 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
6563 return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6564 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
6565}
6566
6567
6568/*
6569 * [V]MOVD / [V]MOVQ - greg/mem variants only.
6570 */
6571
6572BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_MM1_EDX_icebp);
6573BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_MM1_FSxBX_icebp);
6574BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_EAX_MM1_icebp);
6575BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_FSxBX_MM1_icebp);
6576extern FNBS3FAR bs3CpuInstr3_movd_MM1_R9D_icebp_c64;
6577extern FNBS3FAR bs3CpuInstr3_movd_R10D_MM0_icebp_c64;
6578
6579BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_XMM1_EAX_icebp);
6580BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_XMM1_FSxBX_icebp);
6581BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_EAX_XMM1_icebp);
6582BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_FSxBX_XMM1_icebp);
6583extern FNBS3FAR bs3CpuInstr3_movd_XMM9_R8D_icebp_c64;
6584extern FNBS3FAR bs3CpuInstr3_movd_R8D_XMM9_icebp_c64;
6585extern FNBS3FAR bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64;
6586extern FNBS3FAR bs3CpuInstr3_movd_FSxBX_XMM9_icebp_c64;
6587
6588BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_XMM1_EAX_icebp);
6589BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp);
6590BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_EDX_XMM1_icebp);
6591BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp);
6592extern FNBS3FAR bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64;
6593extern FNBS3FAR bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64;
6594extern FNBS3FAR bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64;
6595extern FNBS3FAR bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64;
6596
6597BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_MM1_MM2_icebp);
6598BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_MM1_FSxBX_icebp);
6599BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_FSxBX_MM1_icebp);
6600extern FNBS3FAR bs3CpuInstr3_movq_R9_MM1_icebp_c64;
6601extern FNBS3FAR bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64;
6602extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64;
6603extern FNBS3FAR bs3CpuInstr3_movq_MM1_R9_icebp_c64;
6604
6605BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_XMM1_XMM2_icebp);
6606BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_XMM1_FSxBX_icebp);
6607BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_FSxBX_XMM1_icebp);
6608extern FNBS3FAR bs3CpuInstr3_movq_XMM9_R8_icebp_c64;
6609extern FNBS3FAR bs3CpuInstr3_movq_R8_XMM9_icebp_c64;
6610extern FNBS3FAR bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64;
6611extern FNBS3FAR bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64;
6612extern FNBS3FAR bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64;
6613extern FNBS3FAR bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64;
6614extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64;
6615extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64;
6616
6617BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_XMM1_XMM2_icebp);
6618BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp);
6619BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp);
6620extern FNBS3FAR bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64;
6621extern FNBS3FAR bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64;
6622extern FNBS3FAR bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64;
6623extern FNBS3FAR bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64;
6624extern FNBS3FAR bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64;
6625extern FNBS3FAR bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64;
6626extern FNBS3FAR bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64;
6627extern FNBS3FAR bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64;
6628
6629
6630BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movd_movq(uint8_t bMode)
6631{
6632 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesRm[] =
6633 {
6634 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) },
6635 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) },
6636 { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) },
6637 { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080808080808080) },
6638 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555666677778888) },
6639 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) },
6640 };
6641 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaD[] =
6642 {
6643 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) },
6644 { RTUINT256_INIT_C(0, 0, 0, 0x00000000ffffffff), UINT64_C(0xffffffffffffffff) },
6645 { RTUINT256_INIT_C(0, 0, 0, 0x000000007f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) },
6646 { RTUINT256_INIT_C(0, 0, 0, 0x0000000080808080), UINT64_C(0x8080808080808080) },
6647 { RTUINT256_INIT_C(0, 0, 0, 0x0000000077778888), UINT64_C(0x5555666677778888) },
6648 { RTUINT256_INIT_C(0, 0, 0, 0x00000000930996bb), UINT64_C(0x9c5ce073930996bb) },
6649 };
6650 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaQ[] =
6651 {
6652 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) },
6653 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) },
6654 { RTUINT256_INIT_C(0, 0, 0, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) },
6655 { RTUINT256_INIT_C(0, 0, 0, 0x8080808080808080), UINT64_C(0x8080808080808080) },
6656 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), UINT64_C(0x5555666677778888) },
6657 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) },
6658 };
6659
6660 /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */
6661 static BS3CPUINSTR3_TEST2_T const s_aTests16[] =
6662 {
6663 { bs3CpuInstr3_movd_MM1_EDX_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6664 { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6665 { bs3CpuInstr3_movd_EAX_MM1_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6666 { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6667
6668 { bs3CpuInstr3_movd_XMM1_EAX_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6669 { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6670 { bs3CpuInstr3_movd_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6671 { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6672
6673 { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6674 { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6675 { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6676 { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6677 { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6678 { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6679 { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6680 { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6681
6682 { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6683 { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6684 };
6685 static BS3CPUINSTR3_TEST2_T const s_aTests32[] =
6686 {
6687 { bs3CpuInstr3_movd_MM1_EDX_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6688 { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6689 { bs3CpuInstr3_movd_EAX_MM1_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6690 { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6691
6692 { bs3CpuInstr3_movd_XMM1_EAX_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6693 { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6694 { bs3CpuInstr3_movd_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6695 { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6696
6697 { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6698 { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6699 { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6700 { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6701
6702 { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6703 { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6704
6705 { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6706 { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6707
6708 { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6709 { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6710 };
6711 static BS3CPUINSTR3_TEST2_T const s_aTests64[] =
6712 {
6713 { bs3CpuInstr3_movd_MM1_EDX_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6714 { bs3CpuInstr3_movd_MM1_R9D_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 9, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6715 { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6716 { bs3CpuInstr3_movd_EAX_MM1_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6717 { bs3CpuInstr3_movd_R10D_MM0_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 10, 0, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6718 { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6719
6720 { bs3CpuInstr3_movd_XMM1_EAX_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6721 { bs3CpuInstr3_movd_XMM9_R8D_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6722 { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6723 { bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6724 { bs3CpuInstr3_movd_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6725 { bs3CpuInstr3_movd_R8D_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6726 { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6727
6728 { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6729 { bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 9, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6730 { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6731 { bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD },
6732 { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6733 { bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6734 { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6735 { bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6736
6737 { bs3CpuInstr3_movq_MM1_R9_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, false, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6738 { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6739 { bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6740 { bs3CpuInstr3_movq_R9_MM1_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, true, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6741 { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6742 { bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6743
6744 { bs3CpuInstr3_movq_XMM9_R8_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6745 { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6746 { bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6747 { bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6748 { bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6749 { bs3CpuInstr3_movq_R8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6750 { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6751 { bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6752 { bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6753 { bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6754
6755 { bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6756 { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6757 { bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6758 { bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6759 { bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ },
6760 { bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6761 { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6762 { bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6763 { bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6764 { bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm },
6765 };
6766 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6767 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
6768 return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6769 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
6770}
6771
6772
6773
6774
6775/*
6776 * Test type #3 - two MM/XMM/YMM operands, no flags.
6777 */
6778
6779typedef struct BS3CPUINSTR3_TEST3_VALUES_T
6780{
6781 RTUINT256U uSrc;
6782 RTUINT256U uDstOut;
6783} BS3CPUINSTR3_TEST3_VALUES_T;
6784
6785typedef struct BS3CPUINSTR3_TEST3_T
6786{
6787 FPFNBS3FAR pfnWorker;
6788 uint8_t bAvxMisalignXcpt;
6789 uint8_t enmRm;
6790 uint8_t enmType;
6791 uint8_t iRegDst;
6792 uint8_t iRegSrc;
6793 uint8_t cValues;
6794 BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues;
6795} BS3CPUINSTR3_TEST3_T;
6796
6797typedef struct BS3CPUINSTR3_TEST3_MODE_T
6798{
6799 BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests;
6800 unsigned cTests;
6801} BS3CPUINSTR3_TEST3_MODE_T;
6802
6803/** Initializer for a BS3CPUINSTR3_TEST3_MODE_T array (three entries). */
6804#define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
6805 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
6806
6807
6808/**
6809 * Test type #1 worker.
6810 */
6811static uint8_t bs3CpuInstr3_WorkerTestType3(uint8_t bMode, BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests, unsigned cTests,
6812 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint8_t cbMaxAlign)
6813{
6814 BS3REGCTX Ctx;
6815 BS3TRAPFRAME TrapFrame;
6816 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
6817 uint8_t BS3_FAR *pbBuf = g_pbBuf;
6818 uint32_t cbBuf = g_cbBuf;
6819 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
6820 PBS3EXTCTX pExtCtxOut;
6821 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
6822 if (!pExtCtx)
6823 return 0;
6824
6825 /* Ensure the structures are allocated before we sample the stack pointer. */
6826 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
6827 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
6828
6829 /*
6830 * Create test context.
6831 */
6832 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
6833 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
6834 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
6835
6836 /*
6837 * Run the tests in all rings since alignment issues may behave
6838 * differently in ring-3 compared to ring-0.
6839 */
6840 for (;;)
6841 {
6842 unsigned iCfg;
6843 for (iCfg = 0; iCfg < cConfigs; iCfg++)
6844 {
6845 unsigned iTest;
6846 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
6847 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
6848 continue; /* unsupported config */
6849
6850 /*
6851 * Iterate the tests.
6852 */
6853 for (iTest = 0; iTest < cTests; iTest++)
6854 {
6855 BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
6856 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
6857 unsigned const cValues = paTests[iTest].cValues;
6858 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
6859 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
6860 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
6861 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
6862 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
6863 uint8_t const cbMemOp = cbOperand;
6864 uint8_t const cbAlign = RT_MIN(cbOperand, !cbMaxAlign ? 16 : cbMaxAlign);
6865 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
6866 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD
6867 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
6868 : fSseInstr ? paConfigs[iCfg].bXcptSse
6869 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
6870 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
6871 unsigned iVal;
6872
6873 /* If testing unaligned memory accesses, skip register-only tests. This allows
6874 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
6875 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
6876 continue;
6877
6878 /* #AC is only raised in ring-3.: */
6879 if (bXcptExpect == X86_XCPT_AC)
6880 {
6881 if (bRing != 3)
6882 bXcptExpect = X86_XCPT_DB;
6883 else if (fAvxInstr)
6884 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
6885 }
6886
6887 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
6888
6889 /*
6890 * Iterate the test values and do the actual testing.
6891 */
6892 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
6893 {
6894 uint16_t cErrors;
6895 uint16_t uSavedFtw = 0xff;
6896 RTUINT256U uMemOpExpect;
6897
6898 /*
6899 * Set up the context and some expectations.
6900 */
6901 /* dest */
6902 if (paTests[iTest].iRegDst == UINT8_MAX)
6903 {
6904 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
6905 Bs3MemSet(puMemOp, 0xcc, cbMemOp);
6906 if (bXcptExpect == X86_XCPT_DB)
6907 uMemOpExpect = paValues[iVal].uDstOut;
6908 else
6909 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect));
6910 }
6911 else if (fMmxInstr)
6912 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
6913
6914 /* source */
6915 if (paTests[iTest].iRegSrc == UINT8_MAX)
6916 {
6917 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
6918 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX);
6919 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc, cbMemOp);
6920 uMemOpExpect = paValues[iVal].uSrc;
6921 }
6922 else if (fMmxInstr)
6923 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
6924 else if (fSseInstr)
6925 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0);
6926 else
6927 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32);
6928
6929 /* Memory pointer. */
6930 if (paTests[iTest].enmRm >= RM_MEM)
6931 {
6932 BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX
6933 || paTests[iTest].iRegSrc == UINT8_MAX);
6934 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
6935 }
6936
6937 /*
6938 * Execute.
6939 */
6940 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
6941
6942 /*
6943 * Check the result:
6944 */
6945 cErrors = Bs3TestSubErrorCount();
6946
6947 if (bXcptExpect == X86_XCPT_DB && fMmxInstr)
6948 {
6949 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
6950 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
6951 }
6952 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX)
6953 {
6954 if (fMmxInstr)
6955 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET);
6956 else if (fSseInstr)
6957 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0);
6958 else
6959 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand);
6960 }
6961 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
6962
6963 if (TrapFrame.bXcpt != bXcptExpect)
6964 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
6965
6966 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
6967 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
6968 {
6969 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
6970 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
6971 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
6972 }
6973 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
6974 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
6975 pszMode, idTestStep);
6976
6977 if ( paTests[iTest].enmRm >= RM_MEM
6978 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
6979 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
6980
6981 if (cErrors != Bs3TestSubErrorCount())
6982 {
6983 if (paConfigs[iCfg].fAligned)
6984 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
6985 bRing, iCfg, iTest, iVal, bXcptExpect);
6986 else
6987 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
6988 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
6989 Bs3TestPrintf("\n");
6990 }
6991
6992 if (uSavedFtw != 0xff)
6993 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
6994 }
6995 }
6996
6997 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
6998 }
6999
7000 /*
7001 * Next ring.
7002 */
7003 bRing++;
7004 if (bRing > 3 || bMode == BS3_MODE_RM)
7005 break;
7006 Bs3RegCtxConvertToRingX(&Ctx, bRing);
7007 }
7008
7009 /*
7010 * Cleanup.
7011 */
7012 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
7013 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
7014 return 0;
7015}
7016
7017
7018/*
7019 * PSHUFW
7020 */
7021BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp);
7022BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp);
7023BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp);
7024BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp);
7025
7026BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufw(uint8_t bMode)
7027{
7028 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
7029 {
7030 { RTUINT256_INIT_C(0, 0, 0, 0),
7031 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7032 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff),
7033 /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) },
7034 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888),
7035 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x5555555555555555) },
7036 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb),
7037 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x9c5c9c5c9c5c9c5c) },
7038 };
7039
7040 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
7041 {
7042 { RTUINT256_INIT_C(0, 0, 0, 0),
7043 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7044 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff),
7045 /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) },
7046 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888),
7047 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x8888777766665555) },
7048 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb),
7049 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x96bb9309e0739c5c) },
7050 };
7051
7052 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7053 {
7054 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7055 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7056 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7057 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7058 };
7059 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7060 {
7061 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7062 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7063 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7064 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7065 };
7066 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7067 {
7068 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7069 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7070 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7071 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7072 };
7073 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7074 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7075 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7076 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
7077}
7078
7079
7080/*
7081 * [V]PSHUFHW
7082 */
7083BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp);
7084BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp);
7085BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp);
7086BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp);
7087
7088BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp);
7089BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp);
7090BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp);
7091BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp);
7092
7093BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp);
7094BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp);
7095BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp);
7096BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp);
7097extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64;
7098extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64;
7099
7100BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufhw(uint8_t bMode)
7101{
7102 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
7103 {
7104 { RTUINT256_INIT_C(0, 0, 0, 0),
7105 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7106 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7107 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7108 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
7109 /* => */ RTUINT256_INIT_C(0x5555555555555555, 0x1111222233334444, 0x1111111111111111, 0x5555666677778888) },
7110 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7111 /* => */ RTUINT256_INIT_C(0x4d094d094d094d09, 0x3ef417c8666b3fe6, 0xb421b421b421b421, 0x9c5ce073930996bb) },
7112 };
7113
7114 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
7115 {
7116 { RTUINT256_INIT_C(0, 0, 0, 0),
7117 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7118 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7119 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7120 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
7121 /* => */ RTUINT256_INIT_C(0x8888777766665555, 0x1111222233334444, 0x4444333322221111, 0x5555666677778888) },
7122 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7123 /* => */ RTUINT256_INIT_C(0x73d56cdcf02a4d09, 0x3ef417c8666b3fe6, 0x9ba2564c2fa8b421, 0x9c5ce073930996bb) },
7124 };
7125
7126 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7127 {
7128 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7129 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7130 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7131 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7132
7133 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7134 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7135 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7136 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7137
7138 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7139 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7140 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7141 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7142 };
7143 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7144 {
7145 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7146 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7147 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7148 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7149
7150 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7151 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7152 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7153 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7154
7155 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7156 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7157 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7158 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7159 };
7160 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7161 {
7162 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7163 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7164 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7165 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7166
7167 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7168 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7169 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7170 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7171
7172 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7173 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7174 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7175 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7176 { bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7177 { bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7178 };
7179 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7180 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7181 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7182 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
7183}
7184
7185
7186/*
7187 * [V]PSHUFLW
7188 */
7189BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp);
7190BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp);
7191BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp);
7192BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp);
7193
7194BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp);
7195BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp);
7196BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp);
7197BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp);
7198
7199BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp);
7200BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp);
7201BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp);
7202BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp);
7203extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64;
7204extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64;
7205
7206BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshuflw(uint8_t bMode)
7207{
7208 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
7209 {
7210 { RTUINT256_INIT_C(0, 0, 0, 0),
7211 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7212 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7213 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7214 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
7215 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x1111111111111111, 0x1111222233334444, 0x5555555555555555) },
7216 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7217 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef43ef43ef43ef4, 0xb4212fa8564c9ba2, 0x9c5c9c5c9c5c9c5c) },
7218 };
7219
7220 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
7221 {
7222 { RTUINT256_INIT_C(0, 0, 0, 0),
7223 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7224 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7225 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7226 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
7227 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x4444333322221111, 0x1111222233334444, 0x8888777766665555) },
7228 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7229 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3fe6666b17c83ef4, 0xb4212fa8564c9ba2, 0x96bb9309e0739c5c) },
7230 };
7231
7232 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7233 {
7234 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7235 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7236 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7237 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7238
7239 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7240 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7241 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7242 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7243
7244 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7245 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7246 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7247 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7248 };
7249 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7250 {
7251 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7252 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7253 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7254 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7255
7256 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7257 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7258 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7259 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7260
7261 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7262 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7263 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7264 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7265 };
7266 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7267 {
7268 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7269 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7270 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7271 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7272
7273 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7274 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7275 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7276 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7277
7278 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7279 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7280 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7281 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7282 { bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7283 { bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7284 };
7285 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7286 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7287 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7288 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
7289}
7290
7291
7292/*
7293 * [V]PSHUFHD
7294 */
7295BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp);
7296BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp);
7297BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp);
7298BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp);
7299
7300BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp);
7301BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp);
7302BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp);
7303BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp);
7304
7305BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp);
7306BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp);
7307BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp);
7308BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp);
7309extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64;
7310extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64;
7311
7312BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufd(uint8_t bMode)
7313{
7314 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] =
7315 {
7316 { RTUINT256_INIT_C(0, 0, 0, 0),
7317 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7318 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7319 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7320 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
7321 /* => */ RTUINT256_INIT_C(0x5555666655556666, 0x5555666655556666, 0x1111222211112222, 0x1111222211112222) },
7322 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7323 /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x4d09f02a4d09f02a, 0xb4212fa8b4212fa8, 0xb4212fa8b4212fa8) },
7324 };
7325
7326 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] =
7327 {
7328 { RTUINT256_INIT_C(0, 0, 0, 0),
7329 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7330 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7331 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7332 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
7333 /* => */ RTUINT256_INIT_C(0x3333444411112222, 0x7777888855556666, 0x7777888855556666, 0x3333444411112222) },
7334 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7335 /* => */ RTUINT256_INIT_C(0x666b3fe63ef417c8, 0x6cdc73d54d09f02a, 0x930996bb9c5ce073, 0x564c9ba2b4212fa8) },
7336 };
7337
7338 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7339 {
7340 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7341 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7342 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7343 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7344
7345 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7346 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7347 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7348 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7349
7350 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7351 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7352 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7353 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7354 };
7355 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7356 {
7357 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7358 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7359 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7360 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7361
7362 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7363 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7364 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7365 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7366
7367 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7368 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7369 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7370 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7371 };
7372 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7373 {
7374 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7375 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7376 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7377 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7378
7379 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7380 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7381 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7382 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7383
7384 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7385 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7386 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7387 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7388 { bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF },
7389 { bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B },
7390 };
7391 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7392 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7393 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7394 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
7395}
7396
7397
7398/**
7399 * Values shared by the move functions (same input as output).
7400 */
7401static BS3CPUINSTR3_TEST3_VALUES_T const g_aMoveValues3[] =
7402{
7403 { RTUINT256_INIT_C(0, 0, 0, 0),
7404 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7405 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7406 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7407 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
7408 /* => */ RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888) },
7409 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7410 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) },
7411};
7412
7413
7414/*
7415 * MOVNTDQA - load double qword, strictly aligned, with non-temporal hint.
7416 */
7417BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp);
7418extern FNBS3FAR bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64;
7419BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp);
7420extern FNBS3FAR bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64;
7421BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp);
7422extern FNBS3FAR bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64;
7423
7424BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdqa(uint8_t bMode)
7425{
7426 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7427 {
7428 { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7429 { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7430 { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7431 };
7432 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7433 {
7434 { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7435 { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7436 { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7437 };
7438 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7439 {
7440 { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7441 { bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7442 { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7443 { bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7444 { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7445 { bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7446 };
7447 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7448 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7449 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7450 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
7451}
7452
7453
7454/*
7455 * MOVNTDQ - store double qword, strictly aligned, with non-temporal hint.
7456 */
7457BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp);
7458extern FNBS3FAR bs3CpuInstr3_movntdq_FSxBX_XMM10_icebp_c64;
7459BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp);
7460extern FNBS3FAR bs3CpuInstr3_vmovntdq_FSxBX_XMM10_icebp_c64;
7461BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp);
7462extern FNBS3FAR bs3CpuInstr3_vmovntdq_FSxBX_YMM10_icebp_c64;
7463
7464BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdq(uint8_t bMode)
7465{
7466 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7467 {
7468 { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7469 { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7470 { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7471 };
7472 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7473 {
7474 { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7475 { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7476 { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7477 };
7478 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7479 {
7480 { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7481 { bs3CpuInstr3_movntdq_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7482 { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7483 { bs3CpuInstr3_vmovntdq_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7484 { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7485 { bs3CpuInstr3_vmovntdq_FSxBX_YMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7486 };
7487 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7488 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7489 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7490 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
7491}
7492
7493
7494/*
7495 * [V]MOVNPS / [V]MOVNTPD - load single/double precision floating-point, aligned,
7496 * with non-temporal hint. Only difference is the unit.
7497 */
7498BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntps_FSxBX_XMM1_icebp);
7499extern FNBS3FAR bs3CpuInstr3_movntps_FSxBX_XMM10_icebp_c64;
7500BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp);
7501extern FNBS3FAR bs3CpuInstr3_vmovntps_FSxBX_XMM11_icebp_c64;
7502BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp);
7503extern FNBS3FAR bs3CpuInstr3_vmovntps_FSxBX_YMM12_icebp_c64;
7504
7505BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp);
7506extern FNBS3FAR bs3CpuInstr3_movntpd_FSxBX_XMM10_icebp_c64;
7507BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp);
7508extern FNBS3FAR bs3CpuInstr3_vmovntpd_FSxBX_XMM11_icebp_c64;
7509BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp);
7510extern FNBS3FAR bs3CpuInstr3_vmovntpd_FSxBX_YMM12_icebp_c64;
7511
7512BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntps_movntpd(uint8_t bMode)
7513{
7514 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7515 {
7516 { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7517 { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7518 { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7519
7520 { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7521 { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7522 { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7523 };
7524 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7525 {
7526 { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7527 { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7528 { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7529
7530 { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7531 { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7532 { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7533 };
7534 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7535 {
7536 { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7537 { bs3CpuInstr3_movntps_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7538 { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7539 { bs3CpuInstr3_vmovntps_FSxBX_XMM11_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7540 { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7541 { bs3CpuInstr3_vmovntps_FSxBX_YMM12_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7542
7543 { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7544 { bs3CpuInstr3_movntpd_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7545 { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7546 { bs3CpuInstr3_vmovntpd_FSxBX_XMM11_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7547 { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7548 { bs3CpuInstr3_vmovntpd_FSxBX_YMM12_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7549 };
7550 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7551 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7552 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7553 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
7554}
7555
7556
7557/*
7558 * MOVUPS - packed single-precision floating point, unaligned.
7559 *
7560 * Note! We only cover one of the two register<->register variants here
7561 * thanks to the assembler (probably the one with the smaller opcode).
7562 */
7563BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_XMM1_XMM2_icebp);
7564BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_XMM1_FSxBX_icebp);
7565extern FNBS3FAR bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64;
7566extern FNBS3FAR bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64;
7567BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_XMM1_XMM2_icebp);
7568BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp);
7569extern FNBS3FAR bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64;
7570extern FNBS3FAR bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64;
7571BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_YMM1_YMM2_icebp);
7572BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp);
7573extern FNBS3FAR bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64;
7574extern FNBS3FAR bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64;
7575
7576BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_FSxBX_XMM1_icebp);
7577extern FNBS3FAR bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64;
7578BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp);
7579extern FNBS3FAR bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64;
7580BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp);
7581extern FNBS3FAR bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64;
7582
7583BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movups(uint8_t bMode)
7584{
7585 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7586 {
7587 { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7588 { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7589 { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7590
7591 { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7592 { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7593 { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7594
7595 { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7596 { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7597 { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7598 };
7599 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7600 {
7601 { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7602 { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7603 { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7604
7605 { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7606 { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7607 { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7608
7609 { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7610 { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7611 { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7612 };
7613 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7614 {
7615 { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7616 { bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7617 { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7618 { bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7619 { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7620 { bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7621
7622 { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7623 { bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7624 { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7625 { bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7626 { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7627 { bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7628
7629 { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7630 { bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7631 { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7632 { bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7633 { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7634 { bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7635 };
7636 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7637 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7638 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7639 g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
7640}
7641
7642
7643/*
7644 * MOVUPD - packed double-precision floating point, unaligned.
7645 *
7646 * Note! We only cover one of the two register<->register variants here
7647 * thanks to the assembler (probably the one with the smaller opcode).
7648 */
7649BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_XMM1_XMM2_icebp);
7650BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_XMM1_FSxBX_icebp);
7651extern FNBS3FAR bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64;
7652extern FNBS3FAR bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64;
7653BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp);
7654BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp);
7655extern FNBS3FAR bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64;
7656extern FNBS3FAR bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64;
7657BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp);
7658BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp);
7659extern FNBS3FAR bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64;
7660extern FNBS3FAR bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64;
7661
7662BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_FSxBX_XMM1_icebp);
7663extern FNBS3FAR bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64;
7664BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp);
7665extern FNBS3FAR bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64;
7666BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp);
7667extern FNBS3FAR bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64;
7668
7669BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movupd(uint8_t bMode)
7670{
7671 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7672 {
7673 { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7674 { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7675 { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7676
7677 { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7678 { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7679 { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7680
7681 { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7682 { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7683 { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7684 };
7685 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7686 {
7687 { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7688 { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7689 { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7690
7691 { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7692 { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7693 { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7694
7695 { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7696 { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7697 { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7698 };
7699 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7700 {
7701 { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7702 { bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7703 { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7704 { bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7705 { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7706 { bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7707
7708 { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7709 { bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7710 { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7711 { bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7712 { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7713 { bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7714
7715 { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7716 { bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7717 { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7718 { bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7719 { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7720 { bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7721 };
7722 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7723 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7724 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7725 g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
7726}
7727
7728
7729/*
7730 * [V]MOVSLDUP - Duplicate even single precision floating-point values.
7731 */
7732BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsldup_XMM1_XMM2_icebp);
7733BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp);
7734extern FNBS3FAR bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64;
7735extern FNBS3FAR bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64;
7736BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp);
7737BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp);
7738extern FNBS3FAR bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64;
7739extern FNBS3FAR bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64;
7740BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp);
7741BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp);
7742extern FNBS3FAR bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64;
7743extern FNBS3FAR bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64;
7744
7745BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsldup(uint8_t bMode)
7746{
7747 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] =
7748 {
7749 { RTUINT256_INIT_C(0, 0, 0, 0),
7750 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7751 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7752 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7753 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
7754 /* => */ RTUINT256_INIT_C(0xbbbbccccbbbbcccc, 0xffff2121ffff2121, 0x3333444433334444, 0x7777888877778888) },
7755 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7756 /* => */ RTUINT256_INIT_C(0x6cdc73d56cdc73d5, 0x666b3fe6666b3fe6, 0x564c9ba2564c9ba2, 0x930996bb930996bb) },
7757 };
7758
7759 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7760 {
7761 { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7762 { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7763
7764 { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7765 { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7766
7767 { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7768 { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7769 };
7770 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7771 {
7772 { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7773 { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7774
7775 { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7776 { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7777
7778 { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7779 { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7780 };
7781 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7782 {
7783 { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7784 { bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues },
7785 { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7786 { bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues },
7787
7788 { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7789 { bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues },
7790 { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7791 { bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues },
7792
7793 { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7794 { bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues },
7795 { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7796 { bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues },
7797 };
7798 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7799 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7800 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7801 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
7802}
7803
7804
7805/*
7806 * [V]MOVSHDUP - Duplicate even single precision floating-point values.
7807 */
7808BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movshdup_XMM1_XMM2_icebp);
7809BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp);
7810extern FNBS3FAR bs3CpuInstr3_movshdup_XMM8_XMM12_icebp_c64;
7811extern FNBS3FAR bs3CpuInstr3_movshdup_XMM10_FSxBX_icebp_c64;
7812BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp);
7813BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp);
7814extern FNBS3FAR bs3CpuInstr3_vmovshdup_XMM7_XMM14_icebp_c64;
7815extern FNBS3FAR bs3CpuInstr3_vmovshdup_XMM11_FSxBX_icebp_c64;
7816BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp);
7817BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp);
7818extern FNBS3FAR bs3CpuInstr3_vmovshdup_YMM12_YMM8_icebp_c64;
7819extern FNBS3FAR bs3CpuInstr3_vmovshdup_YMM12_FSxBX_icebp_c64;
7820
7821BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movshdup(uint8_t bMode)
7822{
7823 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] =
7824 {
7825 { RTUINT256_INIT_C(0, 0, 0, 0),
7826 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7827 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7828 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7829 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
7830 /* => */ RTUINT256_INIT_C(0x9999aaaa9999aaaa, 0xddddeeeeddddeeee, 0x1111222211112222, 0x5555666655556666) },
7831 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7832 /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x3ef417c83ef417c8, 0xb4212fa8b4212fa8, 0x9c5ce0739c5ce073) },
7833 };
7834
7835 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7836 {
7837 { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7838 { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7839
7840 { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7841 { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7842
7843 { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7844 { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7845 };
7846 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7847 {
7848 { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7849 { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7850
7851 { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7852 { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7853
7854 { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7855 { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7856 };
7857 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7858 {
7859 { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7860 { bs3CpuInstr3_movshdup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues },
7861 { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7862 { bs3CpuInstr3_movshdup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues },
7863
7864 { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7865 { bs3CpuInstr3_vmovshdup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues },
7866 { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7867 { bs3CpuInstr3_vmovshdup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues },
7868
7869 { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7870 { bs3CpuInstr3_vmovshdup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues },
7871 { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7872 { bs3CpuInstr3_vmovshdup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues },
7873 };
7874 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7875 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7876 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7877 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/);
7878}
7879
7880
7881/*
7882 * [V]MOVDDUP - Duplicate even single precision floating-point values.
7883 *
7884 * Similar to MOVSLDUP, but different exception class and unit size.
7885 */
7886BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movddup_XMM1_XMM2_icebp);
7887BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movddup_XMM1_FSxBX_icebp);
7888extern FNBS3FAR bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64;
7889extern FNBS3FAR bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64;
7890BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp);
7891BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp);
7892extern FNBS3FAR bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64;
7893extern FNBS3FAR bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64;
7894BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp);
7895BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp);
7896extern FNBS3FAR bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64;
7897extern FNBS3FAR bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64;
7898
7899BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movddup(uint8_t bMode)
7900{
7901 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] =
7902 {
7903 { RTUINT256_INIT_C(0, 0, 0, 0),
7904 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
7905 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
7906 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) },
7907 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
7908 /* => */ RTUINT256_INIT_C(0xddddeeeeffff2121, 0xddddeeeeffff2121, 0x5555666677778888, 0x5555666677778888) },
7909 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
7910 /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0x3ef417c8666b3fe6, 0x9c5ce073930996bb, 0x9c5ce073930996bb) },
7911 };
7912
7913 /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */
7914 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7915 {
7916 { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7917 { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7918
7919 { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7920 { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7921
7922 { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7923 { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7924 };
7925 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
7926 {
7927 { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7928 { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7929
7930 { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7931 { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7932
7933 { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7934 { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7935 };
7936 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
7937 {
7938 { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7939 { bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues },
7940 { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7941 { bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues },
7942
7943 { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7944 { bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues },
7945 { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7946 { bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues },
7947
7948 { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
7949 { bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues },
7950 { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
7951 { bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues },
7952 };
7953 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7954 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
7955 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7956 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), 0 /*cbMaxAlign*/);
7957}
7958
7959
7960/*
7961 * [V]MOVAPS / [V]MOVAPD
7962 */
7963BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movaps_XMM1_XMM2_icebp);
7964BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movaps_XMM1_FSxBX_icebp);
7965extern FNBS3FAR bs3CpuInstr3_movaps_XMM8_XMM12_icebp_c64;
7966extern FNBS3FAR bs3CpuInstr3_movaps_XMM10_FSxBX_icebp_c64;
7967BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp);
7968BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp);
7969extern FNBS3FAR bs3CpuInstr3_vmovaps_XMM7_XMM14_icebp_c64;
7970extern FNBS3FAR bs3CpuInstr3_vmovaps_XMM11_FSxBX_icebp_c64;
7971BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp);
7972BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp);
7973extern FNBS3FAR bs3CpuInstr3_vmovaps_YMM12_YMM8_icebp_c64;
7974extern FNBS3FAR bs3CpuInstr3_vmovaps_YMM12_FSxBX_icebp_c64;
7975
7976BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movapd_XMM1_XMM2_icebp);
7977BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movapd_XMM1_FSxBX_icebp);
7978extern FNBS3FAR bs3CpuInstr3_movapd_XMM8_XMM12_icebp_c64;
7979extern FNBS3FAR bs3CpuInstr3_movapd_XMM10_FSxBX_icebp_c64;
7980BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp);
7981BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp);
7982extern FNBS3FAR bs3CpuInstr3_vmovapd_XMM7_XMM14_icebp_c64;
7983extern FNBS3FAR bs3CpuInstr3_vmovapd_XMM11_FSxBX_icebp_c64;
7984BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp);
7985BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp);
7986extern FNBS3FAR bs3CpuInstr3_vmovapd_YMM12_YMM8_icebp_c64;
7987extern FNBS3FAR bs3CpuInstr3_vmovapd_YMM12_FSxBX_icebp_c64;
7988
7989BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movaps_movapd(uint8_t bMode)
7990{
7991 /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */
7992 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
7993 {
7994 { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7995 { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7996 { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7997 { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
7998
7999 { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8000 { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8001 { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8002 { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8003
8004 { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8005 { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8006 { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8007 { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8008 };
8009 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
8010 {
8011 { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8012 { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8013 { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8014 { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8015
8016 { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8017 { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8018 { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8019 { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8020
8021 { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8022 { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8023 { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8024 { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8025 };
8026 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
8027 {
8028 { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8029 { bs3CpuInstr3_movaps_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8030 { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8031 { bs3CpuInstr3_movaps_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8032 { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8033 { bs3CpuInstr3_movapd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8034 { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8035 { bs3CpuInstr3_movapd_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8036
8037 { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8038 { bs3CpuInstr3_vmovaps_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8039 { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8040 { bs3CpuInstr3_vmovaps_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8041 { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8042 { bs3CpuInstr3_vmovapd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8043 { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8044 { bs3CpuInstr3_vmovapd_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8045
8046 { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8047 { bs3CpuInstr3_vmovaps_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8048 { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8049 { bs3CpuInstr3_vmovaps_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8050 { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8051 { bs3CpuInstr3_vmovapd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8052 { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8053 { bs3CpuInstr3_vmovapd_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8054 };
8055 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
8056 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
8057 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
8058 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
8059}
8060
8061
8062/*
8063 * [V]MOVDQU - move unaligned packed qwords.
8064 */
8065BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqu_XMM1_XMM2_icebp);
8066BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp);
8067BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp);
8068extern FNBS3FAR bs3CpuInstr3_movdqu_XMM8_XMM12_icebp_c64;
8069extern FNBS3FAR bs3CpuInstr3_07f_movdqu_XMM8_XMM12_icebp_c64;
8070extern FNBS3FAR bs3CpuInstr3_movdqu_XMM10_FSxBX_icebp_c64;
8071BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp);
8072BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp);
8073BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp);
8074extern FNBS3FAR bs3CpuInstr3_vmovdqu_XMM7_XMM14_icebp_c64;
8075extern FNBS3FAR bs3CpuInstr3_vmovdqu_XMM11_FSxBX_icebp_c64;
8076BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp);
8077BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp);
8078BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp);
8079extern FNBS3FAR bs3CpuInstr3_vmovdqu_YMM12_YMM8_icebp_c64;
8080extern FNBS3FAR bs3CpuInstr3_vmovdqu_YMM12_FSxBX_icebp_c64;
8081
8082BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp);
8083extern FNBS3FAR bs3CpuInstr3_movdqu_FSxBX_XMM10_icebp_c64;
8084BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp);
8085extern FNBS3FAR bs3CpuInstr3_vmovdqu_FSxBX_XMM11_icebp_c64;
8086BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp);
8087extern FNBS3FAR bs3CpuInstr3_vmovdqu_FSxBX_YMM12_icebp_c64;
8088
8089BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movdqu(uint8_t bMode)
8090{
8091 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
8092 {
8093 { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8094 { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8095 { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8096 { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8097
8098 { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8099 { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8100 { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8101 { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8102
8103 { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8104 { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8105 { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8106 { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8107 };
8108 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
8109 {
8110 { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8111 { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8112 { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8113 { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8114
8115 { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8116 { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8117 { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8118 { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8119
8120 { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8121 { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8122 { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8123 { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8124 };
8125 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
8126 {
8127 { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8128 { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8129 { bs3CpuInstr3_movdqu_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8130 { bs3CpuInstr3_07f_movdqu_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8131 { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8132 { bs3CpuInstr3_movdqu_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8133 { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8134 { bs3CpuInstr3_movdqu_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8135
8136 { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8137 { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8138 { bs3CpuInstr3_vmovdqu_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8139 { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8140 { bs3CpuInstr3_vmovdqu_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8141 { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8142 { bs3CpuInstr3_vmovdqu_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8143
8144 { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8145 { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8146 { bs3CpuInstr3_vmovdqu_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8147 { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8148 { bs3CpuInstr3_vmovdqu_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8149 { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8150 { bs3CpuInstr3_vmovdqu_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8151 };
8152 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
8153 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
8154 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
8155 g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
8156}
8157
8158
8159/*
8160 * [V]MOVDQA - move aligned packed qwords.
8161 */
8162BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqa_XMM1_XMM2_icebp);
8163BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp);
8164BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp);
8165extern FNBS3FAR bs3CpuInstr3_movdqa_XMM8_XMM12_icebp_c64;
8166extern FNBS3FAR bs3CpuInstr3_07f_movdqa_XMM8_XMM12_icebp_c64;
8167extern FNBS3FAR bs3CpuInstr3_movdqa_XMM10_FSxBX_icebp_c64;
8168BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp);
8169BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp);
8170BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp);
8171extern FNBS3FAR bs3CpuInstr3_vmovdqa_XMM8_XMM14_icebp_c64;
8172extern FNBS3FAR bs3CpuInstr3_07f_vmovdqa_XMM8_XMM14_icebp_c64;
8173extern FNBS3FAR bs3CpuInstr3_vmovdqa_XMM11_FSxBX_icebp_c64;
8174BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp);
8175BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp);
8176BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp);
8177extern FNBS3FAR bs3CpuInstr3_vmovdqa_YMM12_YMM8_icebp_c64;
8178extern FNBS3FAR bs3CpuInstr3_07f_vmovdqa_YMM12_YMM8_icebp_c64;
8179extern FNBS3FAR bs3CpuInstr3_vmovdqa_YMM12_FSxBX_icebp_c64;
8180
8181BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp);
8182extern FNBS3FAR bs3CpuInstr3_movdqa_FSxBX_XMM10_icebp_c64;
8183BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp);
8184extern FNBS3FAR bs3CpuInstr3_vmovdqa_FSxBX_XMM11_icebp_c64;
8185BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp);
8186extern FNBS3FAR bs3CpuInstr3_vmovdqa_FSxBX_YMM12_icebp_c64;
8187
8188BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movdqa(uint8_t bMode)
8189{
8190 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
8191 {
8192 { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8193 { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8194 { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8195 { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c16, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8196
8197 { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8198 { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8199 { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8200 { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8201
8202 { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8203 { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8204 { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8205 { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8206 };
8207 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
8208 {
8209 { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8210 { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8211 { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8212 { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c32, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8213
8214 { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8215 { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8216 { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8217 { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8218
8219 { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8220 { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8221 { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8222 { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8223 };
8224 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
8225 {
8226 { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8227 { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8228 { bs3CpuInstr3_movdqa_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8229 { bs3CpuInstr3_07f_movdqa_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8230 { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8231 { bs3CpuInstr3_movdqa_XMM10_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8232 { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c64, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8233 { bs3CpuInstr3_movdqa_FSxBX_XMM10_icebp_c64, 255, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8234
8235 { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8236 { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8237 { bs3CpuInstr3_vmovdqa_XMM8_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 8, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8238 { bs3CpuInstr3_07f_vmovdqa_XMM8_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 8, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8239 { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8240 { bs3CpuInstr3_vmovdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8241 { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8242 { bs3CpuInstr3_vmovdqa_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8243
8244 { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8245 { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8246 { bs3CpuInstr3_vmovdqa_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8247 { bs3CpuInstr3_07f_vmovdqa_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8248 { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8249 { bs3CpuInstr3_vmovdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8250 { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8251 { bs3CpuInstr3_vmovdqa_FSxBX_YMM12_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
8252 };
8253 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
8254 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
8255 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
8256 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
8257}
8258
8259
8260/*
8261 * [V]PABSB / [V]PABSW / [V]PABSD
8262 */
8263BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_MM1_MM2_icebp);
8264BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_MM1_FSxBX_icebp);
8265BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_XMM1_XMM2_icebp);
8266BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp);
8267extern FNBS3FAR bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64;
8268extern FNBS3FAR bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64;
8269BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp);
8270BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp);
8271extern FNBS3FAR bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64;
8272extern FNBS3FAR bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64;
8273BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp);
8274BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp);
8275extern FNBS3FAR bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64;
8276extern FNBS3FAR bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64;
8277
8278BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_MM1_MM2_icebp);
8279BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_MM1_FSxBX_icebp);
8280BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_XMM1_XMM2_icebp);
8281BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp);
8282extern FNBS3FAR bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64;
8283extern FNBS3FAR bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64;
8284BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp);
8285BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp);
8286extern FNBS3FAR bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64;
8287extern FNBS3FAR bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64;
8288BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp);
8289BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp);
8290extern FNBS3FAR bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64;
8291extern FNBS3FAR bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64;
8292
8293BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_MM1_MM2_icebp);
8294BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_MM1_FSxBX_icebp);
8295BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_XMM1_XMM2_icebp);
8296BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp);
8297extern FNBS3FAR bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64;
8298extern FNBS3FAR bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64;
8299BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp);
8300BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp);
8301extern FNBS3FAR bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64;
8302extern FNBS3FAR bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64;
8303BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp);
8304BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp);
8305extern FNBS3FAR bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64;
8306extern FNBS3FAR bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64;
8307
8308BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pabsb_pabsw_pabsd(uint8_t bMode)
8309{
8310 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesB[] =
8311 {
8312 { RTUINT256_INIT_C(0, 0, 0, 0),
8313 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
8314 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
8315 /* => */ RTUINT256_INIT_C(0x0101010101010101, 0x0101010101010101, 0x0101010101010101, 0x0101010101010101) },
8316 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
8317 /* => */ RTUINT256_INIT_C(0x6767565645453434, 0x2323121201012121, 0x1111222233334444, 0x5555666677777878) },
8318 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
8319 /* => */ RTUINT256_INIT_C(0x4d09102a6c24732b, 0x3e0c1738666b3f1a, 0x4c212f58564c655e, 0x645c20736d096a45) },
8320 };
8321 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesW[] =
8322 {
8323 { RTUINT256_INIT_C(0, 0, 0, 0),
8324 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
8325 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
8326 /* => */ RTUINT256_INIT_C(0x0001000100010001, 0x0001000100010001, 0x0001000100010001, 0x0001000100010001) },
8327 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
8328 /* => */ RTUINT256_INIT_C(0x6667555644453334, 0x2223111200012121, 0x1111222233334444, 0x5555666677777778) },
8329 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
8330 /* => */ RTUINT256_INIT_C(0x4d090fd66cdc73d5, 0x3ef417c8666b3fe6, 0x4bdf2fa8564c645e, 0x63a41f8d6cf76945) },
8331 };
8332 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesD[] =
8333 {
8334 { RTUINT256_INIT_C(0, 0, 0, 0),
8335 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
8336 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
8337 /* => */ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001) },
8338 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
8339 /* => */ RTUINT256_INIT_C(0x6666555644443334, 0x222211120000dedf, 0x1111222233334444, 0x5555666677778888) },
8340 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
8341 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0x4bded058564c9ba2, 0x63a31f8d6cf66945) },
8342 };
8343
8344 static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
8345 {
8346 { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8347 { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8348 { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8349 { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8350 { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8351 { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8352 { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8353 { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8354
8355 { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8356 { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8357 { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8358 { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8359 { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8360 { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8361 { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8362 { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8363
8364 { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8365 { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8366 { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8367 { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8368 { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8369 { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8370 { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8371 { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8372 };
8373 static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
8374 {
8375 { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8376 { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8377 { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8378 { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8379 { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8380 { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8381 { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8382 { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8383
8384 { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8385 { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8386 { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8387 { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8388 { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8389 { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8390 { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8391 { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8392
8393 { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8394 { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8395 { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8396 { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8397 { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8398 { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8399 { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8400 { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8401 };
8402 static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
8403 {
8404 { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8405 { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8406 { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8407 { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8408 { bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8409 { bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8410 { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8411 { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8412 { bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8413 { bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8414 { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8415 { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8416 { bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8417 { bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
8418
8419 { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8420 { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8421 { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8422 { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8423 { bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8424 { bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8425 { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8426 { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8427 { bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8428 { bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8429 { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8430 { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8431 { bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8432 { bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
8433
8434 { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8435 { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8436 { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8437 { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8438 { bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8439 { bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8440 { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8441 { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8442 { bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8443 { bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8444 { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8445 { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8446 { bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8447 { bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
8448 };
8449 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
8450 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
8451 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
8452 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
8453}
8454
8455
8456
8457/*
8458 * Test type #4 - two source MM/XMM/YMM operands, outputs only eflags.
8459 *
8460 * Probably only used by the PTEST instruction.
8461 */
8462
8463typedef struct BS3CPUINSTR3_TEST4_VALUES_T
8464{
8465 RTUINT256U uSrc2;
8466 RTUINT256U uSrc1;
8467 uint16_t afEflOut[3]; /* [0]=MM result, [1]=XMM result, [2]=YMM result */
8468} BS3CPUINSTR3_TEST4_VALUES_T;
8469
8470typedef struct BS3CPUINSTR3_TEST4_T
8471{
8472 FPFNBS3FAR pfnWorker;
8473 uint8_t bAvxMisalignXcpt;
8474 uint8_t enmRm;
8475 uint8_t enmType;
8476 uint8_t iRegSrc1;
8477 uint8_t iRegSrc2;
8478 uint8_t cValues;
8479 BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues;
8480} BS3CPUINSTR3_TEST4_T;
8481
8482typedef struct BS3CPUINSTR3_TEST4_MODE_T
8483{
8484 BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests;
8485 unsigned cTests;
8486} BS3CPUINSTR3_TEST4_MODE_T;
8487
8488/** Initializer for a BS3CPUINSTR3_TEST4_MODE_T array (three entries). */
8489#define BS3CPUINSTR3_TEST4_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
8490 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
8491
8492
8493/**
8494 * Test type #4 worker.
8495 */
8496static uint8_t bs3CpuInstr3_WorkerTestType4(uint8_t bMode, BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests, unsigned cTests,
8497 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint32_t fEflCheck)
8498{
8499 BS3REGCTX Ctx;
8500 BS3TRAPFRAME TrapFrame;
8501 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
8502 uint8_t BS3_FAR *pbBuf = g_pbBuf;
8503 uint32_t cbBuf = g_cbBuf;
8504 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
8505 PBS3EXTCTX pExtCtxOut;
8506 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
8507 if (!pExtCtx)
8508 return 0;
8509
8510 /* Ensure the structures are allocated before we sample the stack pointer. */
8511 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
8512 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
8513
8514 /*
8515 * Create test context.
8516 */
8517 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
8518 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
8519 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
8520
8521 /*
8522 * Run the tests in all rings since alignment issues may behave
8523 * differently in ring-3 compared to ring-0.
8524 */
8525 for (;;)
8526 {
8527 unsigned iCfg;
8528 for (iCfg = 0; iCfg < cConfigs; iCfg++)
8529 {
8530 unsigned iTest;
8531 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
8532 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
8533 continue; /* unsupported config */
8534
8535 /*
8536 * Iterate the tests.
8537 */
8538 for (iTest = 0; iTest < cTests; iTest++)
8539 {
8540 BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
8541 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
8542 unsigned const cValues = paTests[iTest].cValues;
8543 bool const fMmxInstr = paTests[iTest].enmType < T_SSE;
8544 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
8545 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128;
8546 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8
8547 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
8548 uint8_t const cbMemOp = cbOperand;
8549 uint8_t const cbAlign = RT_MIN(cbOperand, 16);
8550 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
8551 uint8_t const idxEflOut = cbOperand == 32 ? 2 : cbOperand == 16 ? 1 : 0;
8552 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD
8553 : fMmxInstr ? paConfigs[iCfg].bXcptMmx
8554 : fSseInstr ? paConfigs[iCfg].bXcptSse
8555 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
8556 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
8557 unsigned iVal;
8558
8559 /* If testing unaligned memory accesses, skip register-only tests. This allows
8560 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
8561 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
8562 continue;
8563
8564 /* #AC is only raised in ring-3.: */
8565 if (bXcptExpect == X86_XCPT_AC)
8566 {
8567 if (bRing != 3)
8568 bXcptExpect = X86_XCPT_DB;
8569 else if (fAvxInstr)
8570 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
8571 }
8572
8573 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
8574
8575 /*
8576 * Iterate the test values and do the actual testing.
8577 */
8578 for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
8579 {
8580 unsigned iEflVariation;
8581 uint32_t const fSavedEfl = Ctx.rflags.u32;
8582 for (iEflVariation = 0; iEflVariation < 2; iEflVariation++)
8583 {
8584 uint16_t cErrors;
8585 uint16_t uSavedFtw = 0xff;
8586 RTUINT256U uMemOpExpect;
8587
8588 /*
8589 * Set up the context and some expectations.
8590 */
8591 /* eflags */
8592 if (iEflVariation)
8593 Ctx.rflags.u32 = fSavedEfl | X86_EFL_STATUS_BITS;
8594 else
8595 Ctx.rflags.u32 = fSavedEfl & ~X86_EFL_STATUS_BITS;
8596
8597 /* source1 */
8598 if (paTests[iTest].iRegSrc1 == UINT8_MAX)
8599 {
8600 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
8601 BS3_ASSERT(paTests[iTest].iRegSrc2 != UINT8_MAX);
8602 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp);
8603 uMemOpExpect = paValues[iVal].uSrc1;
8604 }
8605 else if (fMmxInstr)
8606 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
8607 else if (fSseInstr)
8608 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0);
8609 else
8610 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32);
8611
8612 /* source2 */
8613 if (paTests[iTest].iRegSrc2 == UINT8_MAX)
8614 {
8615 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
8616 BS3_ASSERT(paTests[iTest].iRegSrc1 != UINT8_MAX);
8617 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp);
8618 uMemOpExpect = paValues[iVal].uSrc2;
8619 }
8620 else if (fMmxInstr)
8621 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
8622 else if (fSseInstr)
8623 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0);
8624 else
8625 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32);
8626
8627 /* Memory pointer. */
8628 if (paTests[iTest].enmRm >= RM_MEM)
8629 {
8630 BS3_ASSERT( paTests[iTest].iRegSrc1 == UINT8_MAX
8631 || paTests[iTest].iRegSrc2 == UINT8_MAX);
8632 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
8633 }
8634
8635 /*
8636 * Execute.
8637 */
8638 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
8639
8640 /*
8641 * Check the result:
8642 */
8643 cErrors = Bs3TestSubErrorCount();
8644
8645 if (bXcptExpect == X86_XCPT_DB && fMmxInstr)
8646 {
8647 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
8648 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
8649 }
8650 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
8651
8652 if (TrapFrame.bXcpt != bXcptExpect)
8653 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
8654
8655 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
8656 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
8657 {
8658 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
8659 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
8660 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
8661 }
8662 if (bXcptExpect == X86_XCPT_DB)
8663 Ctx.rflags.u32 = (Ctx.rflags.u32 & ~fEflCheck) | paValues[iVal].afEflOut[idxEflOut];
8664 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
8665 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
8666 pszMode, idTestStep);
8667
8668 if ( paTests[iTest].enmRm >= RM_MEM
8669 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
8670 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
8671
8672 if (cErrors != Bs3TestSubErrorCount())
8673 {
8674 if (paConfigs[iCfg].fAligned)
8675 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x)",
8676 bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect);
8677 else
8678 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
8679 bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect,
8680 puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
8681 Bs3TestPrintf("\n");
8682 }
8683
8684 if (uSavedFtw != 0xff)
8685 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
8686 }
8687 Ctx.rflags.u32 = fSavedEfl;
8688 }
8689 }
8690
8691 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
8692 }
8693
8694 /*
8695 * Next ring.
8696 */
8697 bRing++;
8698 if (bRing > 3 || bMode == BS3_MODE_RM)
8699 break;
8700 Bs3RegCtxConvertToRingX(&Ctx, bRing);
8701 }
8702
8703 /*
8704 * Cleanup.
8705 */
8706 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
8707 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
8708 return 0;
8709}
8710
8711
8712/*
8713 * PTEST
8714 */
8715BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_XMM2_icebp);
8716BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_FSxBX_icebp);
8717extern FNBS3FAR bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64;
8718extern FNBS3FAR bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64;
8719
8720BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_XMM2_icebp);
8721BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_FSxBX_icebp);
8722extern FNBS3FAR bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64;
8723extern FNBS3FAR bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64;
8724
8725BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_YMM2_icebp);
8726BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_FSxBX_icebp);
8727extern FNBS3FAR bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64;
8728extern FNBS3FAR bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64;
8729
8730BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_ptest(uint8_t bMode)
8731{
8732 static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] =
8733 {
8734 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
8735 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
8736 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
8737 { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
8738 /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
8739 /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
8740 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
8741 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
8742 /* => */ { 0, 0, 0 } },
8743 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
8744 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
8745 /* => */ { 0, 0, 0 } },
8746 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
8747 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
8748 /* => */ { 0, 0, 0 } },
8749 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
8750 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
8751 /* => */ { 0, 0, 0 } },
8752 };
8753
8754 static BS3CPUINSTR3_TEST4_T const s_aTests16[] =
8755 {
8756 { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8757 { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8758 { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8759 { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8760 { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8761 { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8762 };
8763 static BS3CPUINSTR3_TEST4_T const s_aTests32[] =
8764 {
8765 { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8766 { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8767 { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8768 { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8769 { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8770 { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8771 };
8772 static BS3CPUINSTR3_TEST4_T const s_aTests64[] =
8773 {
8774 { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8775 { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8776 { bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValues), s_aValues },
8777 { bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
8778 { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8779 { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8780 { bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues },
8781 { bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
8782 { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
8783 { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },
8784 { bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues },
8785 { bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues },
8786 };
8787 static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
8788 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
8789 return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
8790 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
8791}
8792
8793
8794/**
8795 * The 32-bit protected mode main function.
8796 *
8797 * The tests a driven by 32-bit test drivers, even for real-mode tests (though
8798 * we'll switch between PE32 and RM for each test step we perform). Given that
8799 * we test MMX, SSE and AVX here, we don't need to worry about 286 or 8086.
8800 *
8801 * Some extra steps needs to be taken to properly handle extended state in LM64
8802 * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode
8803 * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm).
8804 */
8805BS3_DECL(void) Main_pe32()
8806{
8807 static const BS3TESTMODEBYONEENTRY g_aTests[] =
8808 {
8809#ifndef DEBUG_bird
8810# define ALL_TESTS
8811#endif
8812#if defined(ALL_TESTS)
8813 { "[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand, 0 },
8814 { "[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn, 0 },
8815 { "[v]orps/[v]orpd/[v]or", bs3CpuInstr3_v_orps_orpd_por, 0 },
8816 { "[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor, 0 },
8817#endif
8818#if defined(ALL_TESTS)
8819 { "[v]pcmpgtb/[v]pcmpgtw/[v]pcmpgtd/[v]pcmpgtq", bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq, 0 },
8820 { "[v]pcmpeqb/[v]pcmpeqw/[v]pcmpeqd/[v]pcmpeqq", bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq, 0 },
8821#endif
8822#if defined(ALL_TESTS)
8823 { "[v]paddb/[v]paddw/[v]paddd/[v]paddq", bs3CpuInstr3_v_paddb_paddw_paddd_paddq, 0 },
8824 { "[v]psubb/[v]psubw/[v]psubd/[v]psubq", bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 },
8825#endif
8826#if defined(ALL_TESTS)
8827 { "[v]pmullw/[v]pmulld", bs3CpuInstr3_v_pmullw_pmulld, 0 },
8828 { "[v]pmulhw", bs3CpuInstr3_v_pmulhw, 0 },
8829 { "[v]pmulhuw", bs3CpuInstr3_v_pmulhuw, 0 },
8830#endif
8831#if defined(ALL_TESTS)
8832 { "[v]pmovmskb", bs3CpuInstr3_v_pmovmskb, 0 },
8833 { "pshufb", bs3CpuInstr3_pshufb, 0 },
8834 { "pshufw", bs3CpuInstr3_pshufw, 0 },
8835 { "[v]pshufhw", bs3CpuInstr3_v_pshufhw, 0 },
8836 { "[v]pshuflw", bs3CpuInstr3_v_pshuflw, 0 },
8837 { "[v]pshufd", bs3CpuInstr3_v_pshufd, 0 },
8838#endif
8839#if defined(ALL_TESTS)
8840 { "[v]punpckhbw", bs3CpuInstr3_v_punpckhbw, 0 },
8841 { "[v]punpckhwd", bs3CpuInstr3_v_punpckhwd, 0 },
8842 { "[v]punpckhdq", bs3CpuInstr3_v_punpckhdq, 0 },
8843 { "[v]punpckhqdq", bs3CpuInstr3_v_punpckhqdq, 0 },
8844#endif
8845#if defined(ALL_TESTS)
8846 { "[v]punpcklbw", bs3CpuInstr3_v_punpcklbw, 0 },
8847 { "[v]punpcklwd", bs3CpuInstr3_v_punpcklwd, 0 },
8848 { "[v]punpckldq", bs3CpuInstr3_v_punpckldq, 0 },
8849 { "[v]punpcklqdq", bs3CpuInstr3_v_punpcklqdq, 0 },
8850#endif
8851#if defined(ALL_TESTS)
8852 { "[v]packsswb", bs3CpuInstr3_v_packsswb, 0 },
8853 { "[v]packssdw", bs3CpuInstr3_v_packssdw, 0 },
8854 { "[v]packuswb", bs3CpuInstr3_v_packuswb, 0 },
8855 { "[v]packusdw", bs3CpuInstr3_v_packusdw, 0 },
8856#endif
8857#if defined(ALL_TESTS)
8858 { "[v]pmaxub/[v]pmaxuw/[v]pmaxud", bs3CpuInstr3_v_pmaxub_pmaxuw_pmaxud, 0 },
8859 { "[v]pmaxsb/[v]pmaxsw/[v]pmaxsd", bs3CpuInstr3_v_pmaxsb_pmaxsw_pmaxsd, 0 },
8860 { "[v]pminub/[v]pminuw/[v]pminud", bs3CpuInstr3_v_pminub_pminuw_pminud, 0 },
8861 { "[v]pminsb/[v]pminsw/[v]pminsd", bs3CpuInstr3_v_pminsb_pminsw_pminsd, 0 },
8862#endif
8863#if defined(ALL_TESTS)
8864 { "[v]movntdqa", bs3CpuInstr3_v_movntdqa, 0 },
8865 { "[v]movntdq", bs3CpuInstr3_v_movntdq, 0 },
8866 { "[v]movntps_movntpd", bs3CpuInstr3_v_movntps_movntpd, 0 },
8867 { "[v]movups", bs3CpuInstr3_v_movups, 0 },
8868 { "[v]movupd", bs3CpuInstr3_v_movupd, 0 },
8869 { "[v]movss", bs3CpuInstr3_v_movss, 0 },
8870 { "[v]movsd", bs3CpuInstr3_v_movsd, 0 },
8871 { "[v]movhlps", bs3CpuInstr3_v_movhlps, 0 },
8872 { "[v]movlps/[v]movlpd", bs3CpuInstr3_v_movlps_movlpd, 0 },
8873 { "[v]movhps/[v]movhpd", bs3CpuInstr3_v_movhps_movhpd, 0 },
8874 { "[v]movsldup", bs3CpuInstr3_v_movsldup, 0 },
8875 { "[v]movshdup", bs3CpuInstr3_v_movshdup, 0 },
8876 { "[v]movddup", bs3CpuInstr3_v_movddup, 0 },
8877 { "[v]movaps_movapd", bs3CpuInstr3_v_movaps_movapd, 0 },
8878 { "[v]movd_movq", bs3CpuInstr3_v_movd_movq, 0 },
8879 { "[v]movdqu", bs3CpuInstr3_v_movdqu, 0 },
8880 { "[v]movdqa", bs3CpuInstr3_v_movdqa, 0 },
8881#endif
8882#if defined(ALL_TESTS)
8883 { "[v]ptest", bs3CpuInstr3_v_ptest, 0 },
8884#endif
8885#if defined(ALL_TESTS)
8886 { "[v]pavgb/[v]pavgw", bs3CpuInstr3_v_pavgb_pavgw, 0 },
8887#endif
8888#if defined(ALL_TESTS)
8889 { "[v]pabsb/[v]pabsw/[v]pabsd", bs3CpuInstr3_v_pabsb_pabsw_pabsd, 0 },
8890 { "[v]psignb/[v]psignw/[v]psignd", bs3CpuInstr3_v_psignb_psignw_psignd, 0 },
8891#endif
8892#if defined(ALL_TESTS)
8893 { "[v]phaddw/[v]phaddd", bs3CpuInstr3_v_phaddw_phaddd, 0 },
8894 { "[v]phsubw/[v]phsubd", bs3CpuInstr3_v_phsubw_phsubd, 0 },
8895 { "[v]phaddsw", bs3CpuInstr3_v_phaddsw, 0 },
8896 { "[v]phsubsw", bs3CpuInstr3_v_phsubsw, 0 },
8897 { "[v]pmaddubsw", bs3CpuInstr3_v_pmaddubsw, 0 },
8898#endif
8899#if defined(ALL_TESTS)
8900 { "[v]pmulhrsw", bs3CpuInstr3_v_pmulhrsw, 0 },
8901 { "[v]psadbw", bs3CpuInstr3_v_psadbw, 0 },
8902 { "[v]pmuldq", bs3CpuInstr3_v_pmuldq, 0 },
8903 { "[v]pmuludq", bs3CpuInstr3_v_pmuludq, 0 },
8904#endif
8905 };
8906 Bs3TestInit("bs3-cpu-instr-3");
8907
8908 /*
8909 * Initialize globals.
8910 */
8911 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
8912 {
8913 uint32_t fEbx, fEcx, fEdx;
8914 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
8915 g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX);
8916 g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
8917 g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
8918 g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3);
8919 g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
8920 g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
8921 g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3);
8922 g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3);
8923 g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
8924 g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
8925 g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
8926 g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
8927
8928 if (ASMCpuId_EAX(0) >= 7)
8929 {
8930 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL);
8931 g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
8932 g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
8933 }
8934
8935 if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES)
8936 {
8937 ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
8938 g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
8939 g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A);
8940 g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
8941 }
8942 g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE];
8943 }
8944
8945 /*
8946 * Allocate a buffer for testing.
8947 */
8948 g_cbBuf = X86_PAGE_SIZE * 4;
8949 g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf);
8950 if (g_pbBuf)
8951 {
8952 /*
8953 * Do the tests.
8954 */
8955 Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY);
8956 }
8957 else
8958 Bs3TestFailed("Failed to allocate 16K buffer");
8959
8960 Bs3TestTerm();
8961}
8962
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