| 1 | /* $Id: bs3-cpu-instr-4.c32 105292 2024-07-12 10:16:16Z vboxsync $ */
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| 2 | /** @file
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| 3 | * BS3Kit - bs3-cpu-instr-4 - SSE, AVX FPU instructions, C code template.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * The contents of this file may alternatively be used under the terms
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| 26 | * of the Common Development and Distribution License Version 1.0
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| 27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | * in the VirtualBox distribution, in which case the provisions of the
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| 29 | * CDDL are applicable instead of those of the GPL.
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| 30 | *
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| 31 | * You may elect to license modified versions of this file under the
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| 32 | * terms and conditions of either the GPL or the CDDL or both.
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| 33 | *
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| 34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | */
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| 36 |
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| 37 |
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| 38 | /*********************************************************************************************************************************
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| 39 | * Header Files *
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| 40 | *********************************************************************************************************************************/
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| 41 | #include <bs3kit.h>
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| 42 | #include "bs3-cpu-instr-4-asm-auto.h"
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| 43 |
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| 44 | #include <iprt/asm.h>
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| 45 | #include <iprt/asm-amd64-x86.h>
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| 46 |
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| 47 |
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| 48 | /*********************************************************************************************************************************
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| 49 | * Defined Constants And Macros *
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| 50 | *********************************************************************************************************************************/
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| 51 | /** Converts an execution mode (BS3_MODE_XXX) into an index into an array
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| 52 | * initialized by BS3CPUINSTR4_TEST1_MODES_INIT etc. */
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| 53 | #define BS3CPUINSTR4_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2)
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| 54 |
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| 55 | /** Maximum length for the names of all SIMD FP exception flags combined. */
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| 56 | #define BS3_FP_XCPT_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
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| 57 |
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| 58 | /*
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| 59 | * Single-precision (32 bits) floating-point defines.
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| 60 | */
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| 61 | /** The max exponent value for a single-precision floating-point normal. */
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| 62 | #define BS3_FP32_EXP_NORMAL_MAX 254
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| 63 | /** The min exponent value for a single-precision floating-point normal. */
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| 64 | #define BS3_FP32_EXP_NORMAL_MIN 1
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| 65 | /** The max fraction value for a single-precision floating-point normal. */
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| 66 | #define BS3_FP32_FRACTION_NORMAL_MAX 0x7fffff
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| 67 | /** The min fraction value for a single-precision floating-point normal. */
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| 68 | #define BS3_FP32_FRACTION_NORMAL_MIN 0
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| 69 | /** The exponent bias for the single-precision floating-point format. */
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| 70 | #define BS3_FP32_EXP_BIAS RTFLOAT32U_EXP_BIAS
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| 71 | /** Fraction width (in bits) for the single-precision floating-point format. */
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| 72 | #define BS3_FP32_FRACTION_BITS RTFLOAT32U_FRACTION_BITS
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| 73 | /** The max exponent value for a single-precision floating-point integer without
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| 74 | * losing precision. */
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| 75 | #define BS3_FP32_EXP_SAFE_INT_MAX BS3_FP32_EXP_BIAS + BS3_FP32_FRACTION_BITS
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| 76 | /** The min exponent value for a single-precision floating-point integer without
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| 77 | * losing precision. */
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| 78 | #define BS3_FP32_EXP_SAFE_INT_MIN 1
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| 79 | /** The max fraction value for a double-precision floating-point denormal. */
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| 80 | #define BS3_FP32_FRACTION_DENORMAL_MAX 0x7fffff
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| 81 | /** The min fraction value for a double-precision floating-point denormal. */
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| 82 | #define BS3_FP32_FRACTION_DENORMAL_MIN 1
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| 83 |
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| 84 | #define BS3_FP32_NORMAL_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_NORMAL_MAX)
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| 85 | #define BS3_FP32_NORMAL_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, BS3_FP32_FRACTION_NORMAL_MIN, BS3_FP32_EXP_NORMAL_MIN)
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| 86 | #define BS3_FP32_ZERO(a_Sign) RTFLOAT32U_INIT_ZERO(a_Sign)
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| 87 | #define BS3_FP32_ONE(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0, RTFLOAT32U_EXP_BIAS)
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| 88 | #define BS3_FP32_VAL(a_Sign, a_Frac, a_Exp) RTFLOAT32U_INIT_C(a_Sign, a_Frac, a_Exp)
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| 89 | #define BS3_FP32_INF(a_Sign) RTFLOAT32U_INIT_INF(a_Sign)
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| 90 | #define BS3_FP32_QNAN(a_Sign) RTFLOAT32U_INIT_QNAN(a_Sign)
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| 91 | #define BS3_FP32_QNAN_VAL(a_Sign, a_Val) RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val)
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| 92 | #define BS3_FP32_SNAN(a_Sign) RTFLOAT32U_INIT_SNAN(a_Sign)
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| 93 |
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| 94 |
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| 95 | /*
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| 96 | * Single-precision floating normals.
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| 97 | * Fraction - 23 bits, all usable.
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| 98 | * Exponent - 8 bits, least significant bit MBZ.
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| 99 | */
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| 100 | #define BS3_FP32_NORMAL_VAL_0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x401ac0, 0x78)
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| 101 | #define BS3_FP32_NORMAL_VAL_1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5fcabd, 0xbc)
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| 102 | #define BS3_FP32_NORMAL_VAL_2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7e117a, 0x7e)
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| 103 | #define BS3_FP32_NORMAL_VAL_3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5b5b5b, 0x9a)
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| 104 | #define BS3_FP32_NORMAL_VAL_4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x1e0f1f, 0x32)
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| 105 | #define BS3_FP32_NORMAL_VAL_5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x012345, 0x56)
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| 106 | #define BS3_FP32_NORMAL_VAL_6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x330b3b, 0x90)
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| 107 | #define BS3_FP32_NORMAL_VAL_7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x4ebeb4, 0x30)
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| 108 | /* The maximum integer value (all 23 + 1 implied bit of the fraction part set) without losing precision. */
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| 109 | #define BS3_FP32_NORMAL_SAFE_INT_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX)
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| 110 | /* The minimum integer value without losing precision. */
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| 111 | #define BS3_FP32_NORMAL_SAFE_INT_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, BS3_FP32_FRACTION_NORMAL_MIN, BS3_FP32_EXP_SAFE_INT_MIN)
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| 112 |
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| 113 | /*
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| 114 | * Single-precision floating-point denormals.
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| 115 | */
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| 116 | /** The maximum denormal value. */
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| 117 | #define BS3_FP32_DENORMAL_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, BS3_FP32_FRACTION_DENORMAL_MAX, 0)
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| 118 | /** The maximum denormal value. */
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| 119 | #define BS3_FP32_DENORMAL_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, BS3_FP32_FRACTION_DENORMAL_MIN, 0)
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| 120 |
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| 121 | /*
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| 122 | * Single-precision random values (incl. potentially invalid values).
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| 123 | * We don't care what the exact values are as these are meant to populate
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| 124 | * unmodified operands and be compared bitwise.
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| 125 | */
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| 126 | #define BS3_FP32_RAND_VAL_0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7bacda, 0x55)
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| 127 | #define BS3_FP32_RAND_VAL_1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7010f0, 0xc0)
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| 128 | #define BS3_FP32_RAND_VAL_2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x4ffcbe, 0xf1)
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| 129 | #define BS3_FP32_RAND_VAL_3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x2fd7c8, 0x1f)
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| 130 | #define BS3_FP32_RAND_VAL_4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5b5b5b, 0x09)
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| 131 | #define BS3_FP32_RAND_VAL_5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x3d2d1d, 0x99)
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| 132 | #define BS3_FP32_RAND_VAL_6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x123456, 0x5e)
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| 133 | #define BS3_FP32_RAND_VAL_7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x05432f, 0xd7)
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| 134 |
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| 135 | /*
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| 136 | * Double-precision (64 bits) floating-point defines.
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| 137 | */
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| 138 | /** The max exponent value for a double-precision floating-point normal. */
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| 139 | #define BS3_FP64_EXP_NORMAL_MAX 2046
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| 140 | /** The min exponent value for a double-precision floating-point normal. */
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| 141 | #define BS3_FP64_EXP_NORMAL_MIN 1
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| 142 | /** The max fraction value for a double-precision floating-point normal. */
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| 143 | #define BS3_FP64_FRACTION_NORMAL_MAX 0xfffffffffffff
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| 144 | /** The min fraction value for a double-precision floating-point normal. */
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| 145 | #define BS3_FP64_FRACTION_NORMAL_MIN 0
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| 146 | /** The exponent bias for the double-precision floating-point format. */
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| 147 | #define BS3_FP64_EXP_BIAS RTFLOAT64U_EXP_BIAS
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| 148 | /** Fraction width (in bits) for the double-precision floating-point format. */
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| 149 | #define BS3_FP64_FRACTION_BITS RTFLOAT64U_FRACTION_BITS
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| 150 | /** The max exponent value for a double-precision floating-point integer without
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| 151 | * losing precision. */
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| 152 | #define BS3_FP64_EXP_SAFE_INT_MAX BS3_FP64_EXP_BIAS + BS3_FP64_FRACTION_BITS
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| 153 | /** The min exponent value for a double-precision floating-point integer without
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| 154 | * losing precision. */
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| 155 | #define BS3_FP64_EXP_SAFE_INT_MIN 1
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| 156 | /** The max fraction value for a double-precision floating-point denormal. */
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| 157 | #define BS3_FP64_FRACTION_DENORMAL_MAX 0xfffffffffffff
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| 158 | /** The min fraction value for a double-precision floating-point denormal. */
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| 159 | #define BS3_FP64_FRACTION_DENORMAL_MIN 1
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| 160 |
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| 161 | #define BS3_FP64_NORMAL_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, BS3_FP64_FRACTION_NORMAL_MAX, BS3_FP64_EXP_NORMAL_MAX)
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| 162 | #define BS3_FP64_NORMAL_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, BS3_FP64_FRACTION_NORMAL_MIN, BS3_FP64_EXP_NORMAL_MIN)
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| 163 | #define BS3_FP64_ZERO(a_Sign) RTFLOAT64U_INIT_ZERO(a_Sign)
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| 164 | #define BS3_FP64_ONE(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0, RTFLOAT64U_EXP_BIAS)
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| 165 | #define BS3_FP64_VAL(a_Sign, a_Frac, a_Exp) RTFLOAT64U_INIT_C(a_Sign, a_Frac, a_Exp)
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| 166 | #define BS3_FP64_INF(a_Sign) RTFLOAT64U_INIT_INF(a_Sign)
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| 167 | #define BS3_FP64_QNAN(a_Sign) RTFLOAT64U_INIT_QNAN(a_Sign)
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| 168 | #define BS3_FP64_QNAN_VAL(a_Sign, a_Val) RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val)
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| 169 | #define BS3_FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign)
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| 170 | #define BS3_FP64_SNAN_VAL(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val)
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| 171 |
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| 172 | /*
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| 173 | * Double-precision floating-point normals.
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| 174 | * Fraction - 52 bits, all usable.
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| 175 | * Exponent - 11 bits, least significant bit MBZ.
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| 176 | */
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| 177 | #define BS3_FP64_NORMAL_VAL_0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xacc01adec0de5, 0x30c)
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| 178 | #define BS3_FP64_NORMAL_VAL_1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xf10a7ab1ec01a, 0x4bc)
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| 179 | #define BS3_FP64_NORMAL_VAL_2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xca5cadea1b1ed, 0x3ae)
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| 180 | #define BS3_FP64_NORMAL_VAL_3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xb5b5b5b5b5b5b, 0x7fe)
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| 181 | /* The maximum integer value (all 52 + 1 implied bit of the fraction part set) without losing precision. */
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| 182 | #define BS3_FP64_NORMAL_SAFE_INT_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, BS3_FP64_FRACTION_NORMAL_MAX, BS3_FP64_EXP_SAFE_INT_MAX)
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| 183 | /* The minimum integer value without losing precision. */
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| 184 | #define BS3_FP64_NORMAL_SAFE_INT_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, BS3_FP64_FRACTION_NORMAL_MIN, BS3_FP64_EXP_SAFE_INT_MIN)
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| 185 |
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| 186 | /*
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| 187 | * Double-precision floating-point denormals.
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| 188 | */
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| 189 | /** The maximum denormal value. */
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| 190 | #define BS3_FP64_DENORMAL_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, BS3_FP64_FRACTION_DENORMAL_MAX, 0)
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| 191 | /** The maximum denormal value. */
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| 192 | #define BS3_FP64_DENORMAL_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, BS3_FP64_FRACTION_DENORMAL_MIN, 0)
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| 193 |
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| 194 |
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| 195 | /*********************************************************************************************************************************
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| 196 | * Structures and Typedefs *
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| 197 | *********************************************************************************************************************************/
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| 198 | /** Instruction set type and operand width. */
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| 199 | typedef enum BS3CPUINSTRX_INSTRTYPE_T
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| 200 | {
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| 201 | T_INVALID,
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| 202 | T_MMX,
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| 203 | T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */
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| 204 | T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */
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| 205 | T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */
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| 206 | T_AXMMX,
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| 207 | T_AXMMX_OR_SSE,
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| 208 | T_SSE,
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| 209 | T_128BITS = T_SSE,
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| 210 | T_SSE2,
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| 211 | T_SSE3,
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| 212 | T_SSSE3,
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| 213 | T_SSE4_1,
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| 214 | T_SSE4_2,
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| 215 | T_SSE4A,
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| 216 | T_PCLMUL,
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| 217 | T_SHA,
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| 218 | T_AVX_128,
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| 219 | T_AVX2_128,
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| 220 | T_AVX_PCLMUL,
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| 221 | T_AVX_256,
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| 222 | T_256BITS = T_AVX_256,
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| 223 | T_AVX2_256,
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| 224 | T_MAX
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| 225 | } BS3CPUINSTRX_INSTRTYPE_T;
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| 226 |
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| 227 | /** Memory or register rm variant. */
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| 228 | enum {
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| 229 | RM_REG = 0,
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| 230 | RM_MEM,
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| 231 | RM_MEM8, /**< Memory operand is 8 bytes. Hack for movss and similar. */
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| 232 | RM_MEM16, /**< Memory operand is 16 bytes. Hack for movss and similar. */
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| 233 | RM_MEM32, /**< Memory operand is 32 bytes. Hack for movss and similar. */
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| 234 | RM_MEM64 /**< Memory operand is 64 bytes. Hack for movss and similar. */
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| 235 | };
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| 236 |
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| 237 | /**
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| 238 | * Execution environment configuration.
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| 239 | */
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| 240 | typedef struct BS3CPUINSTR4_CONFIG_T
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| 241 | {
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| 242 | uint16_t fCr0Mp : 1;
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| 243 | uint16_t fCr0Em : 1;
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| 244 | uint16_t fCr0Ts : 1;
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| 245 | uint16_t fCr4OsFxSR : 1;
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| 246 | uint16_t fCr4OsXSave : 1;
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| 247 | uint16_t fCr4OsXmmExcpt : 1;
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| 248 | uint16_t fXcr0Sse : 1;
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| 249 | uint16_t fXcr0Avx : 1;
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| 250 | uint16_t fAligned : 1; /**< Aligned mem operands. If 0, they will be misaligned and tests w/o mem operands skipped. */
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| 251 | uint16_t fAlignCheck : 1;
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| 252 | uint16_t fMxCsrMM : 1; /**< AMD only */
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| 253 | uint8_t bXcptSse;
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| 254 | uint8_t bXcptAvx;
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| 255 | } BS3CPUINSTR4_CONFIG_T;
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| 256 | /** Pointer to an execution environment configuration. */
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| 257 | typedef BS3CPUINSTR4_CONFIG_T const BS3_FAR *PCBS3CPUINSTR4_CONFIG_T;
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| 258 |
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| 259 | /** State saved by bs3CpuInstr4ConfigReconfigure. */
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| 260 | typedef struct BS3CPUINSTRX_CONFIG_SAVED_T
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| 261 | {
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| 262 | uint32_t uCr0;
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| 263 | uint32_t uCr4;
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| 264 | uint32_t uEfl;
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| 265 | uint16_t uFcw;
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| 266 | uint16_t uFsw;
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| 267 | uint32_t uMxCsr;
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| 268 | } BS3CPUINSTRX_CONFIG_SAVED_T;
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| 269 | typedef BS3CPUINSTRX_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTRX_CONFIG_SAVED_T;
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| 270 | typedef BS3CPUINSTRX_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTRX_CONFIG_SAVED_T;
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| 271 |
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| 272 | /**
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| 273 | * YMM packed single-precision floating-point register.
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| 274 | * @todo move to x86.h?
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| 275 | */
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| 276 | typedef union X86YMMFLOATPSREG
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| 277 | {
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| 278 | /** Packed single-precision floating-point view. */
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| 279 | RTFLOAT32U ar32[8];
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| 280 | /** 256-bit integer view. */
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| 281 | RTUINT256U ymm;
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| 282 | } X86YMMFLOATPSREG;
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| 283 | # ifndef VBOX_FOR_DTRACE_LIB
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| 284 | AssertCompileSize(X86YMMFLOATPSREG, 32);
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| 285 | AssertCompileSize(X86YMMFLOATPSREG, sizeof(X86YMMREG));
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| 286 | # endif
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| 287 | /** Pointer to a YMM packed single-precision floating-point register. */
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| 288 | typedef X86YMMFLOATPSREG BS3_FAR *PX86YMMFLOATPSREG;
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| 289 | /** Pointer to a const YMM single-precision packed floating-point register. */
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| 290 | typedef X86YMMFLOATPSREG const BS3_FAR *PCX86YMMFLOATPSREG;
|
|---|
| 291 |
|
|---|
| 292 | /**
|
|---|
| 293 | * YMM packed double-precision floating-point register.
|
|---|
| 294 | * @todo move to x86.h?
|
|---|
| 295 | */
|
|---|
| 296 | typedef union X86YMMFLOATPDREG
|
|---|
| 297 | {
|
|---|
| 298 | /** Packed double-precision floating-point view. */
|
|---|
| 299 | RTFLOAT64U ar64[4];
|
|---|
| 300 | /** 256-bit integer view. */
|
|---|
| 301 | RTUINT256U ymm;
|
|---|
| 302 | } X86YMMFLOATPDREG;
|
|---|
| 303 | # ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 304 | AssertCompileSize(X86YMMFLOATPDREG, 32);
|
|---|
| 305 | AssertCompileSize(X86YMMFLOATPDREG, sizeof(X86YMMREG));
|
|---|
| 306 | # endif
|
|---|
| 307 | /** Pointer to a YMM packed floating-point register. */
|
|---|
| 308 | typedef X86YMMFLOATPDREG BS3_FAR *PX86YMMFLOATPDREG;
|
|---|
| 309 | /** Pointer to a const YMM packed floating-point register. */
|
|---|
| 310 | typedef X86YMMFLOATPDREG const BS3_FAR *PCX86YMMFLOATPDREG;
|
|---|
| 311 |
|
|---|
| 312 | /**
|
|---|
| 313 | * YMM scalar single-precision floating-point register.
|
|---|
| 314 | * @todo move to x86.h?
|
|---|
| 315 | */
|
|---|
| 316 | typedef union X86YMMFLOATSSREG
|
|---|
| 317 | {
|
|---|
| 318 | /** Scalar single-precision floating-point view. */
|
|---|
| 319 | RTFLOAT32U ar32[8];
|
|---|
| 320 | /** 256-bit integer view. */
|
|---|
| 321 | RTUINT256U ymm;
|
|---|
| 322 | } X86YMMFLOATSSREG;
|
|---|
| 323 | # ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 324 | AssertCompileSize(X86YMMFLOATSSREG, 32);
|
|---|
| 325 | AssertCompileSize(X86YMMFLOATSSREG, sizeof(X86YMMREG));
|
|---|
| 326 | # endif
|
|---|
| 327 | /** Pointer to a YMM scalar single-precision floating-point register. */
|
|---|
| 328 | typedef X86YMMFLOATSSREG BS3_FAR *PX86YMMFLOATSSREG;
|
|---|
| 329 | /** Pointer to a const YMM scalar single-precision floating-point register. */
|
|---|
| 330 | typedef X86YMMFLOATSSREG const BS3_FAR *PCX86YMMFLOATSSREG;
|
|---|
| 331 |
|
|---|
| 332 | /**
|
|---|
| 333 | * YMM scalar double-precision floating-point register.
|
|---|
| 334 | * @todo move to x86.h?
|
|---|
| 335 | */
|
|---|
| 336 | typedef union X86YMMFLOATSDREG
|
|---|
| 337 | {
|
|---|
| 338 | /** Scalar double-precision floating-point view. */
|
|---|
| 339 | RTFLOAT64U ar64[3];
|
|---|
| 340 | /** 256-bit integer view. */
|
|---|
| 341 | RTUINT256U ymm;
|
|---|
| 342 | } X86YMMFLOATSDREG;
|
|---|
| 343 | # ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 344 | AssertCompileSize(X86YMMFLOATSDREG, 32);
|
|---|
| 345 | AssertCompileSize(X86YMMFLOATSDREG, sizeof(X86YMMREG));
|
|---|
| 346 | # endif
|
|---|
| 347 | /** Pointer to a YMM scalar double-precision floating-point register. */
|
|---|
| 348 | typedef X86YMMFLOATSDREG BS3_FAR *PX86YMMFLOATSDREG;
|
|---|
| 349 | /** Pointer to a const YMM scalar double-precision floating-point register. */
|
|---|
| 350 | typedef X86YMMFLOATSDREG const BS3_FAR *PCX86YMMFLOATSDREG;
|
|---|
| 351 |
|
|---|
| 352 | /**
|
|---|
| 353 | * YMM scalar quadruple-precision floating-point register.
|
|---|
| 354 | * @todo move to x86.h?
|
|---|
| 355 | */
|
|---|
| 356 | typedef union X86YMMFLOATSQREG
|
|---|
| 357 | {
|
|---|
| 358 | /** Scalar quadruple-precision floating point view. */
|
|---|
| 359 | RTFLOAT128U ar128[2];
|
|---|
| 360 | /** 256-bit integer view. */
|
|---|
| 361 | RTUINT256U ymm;
|
|---|
| 362 | } X86YMMFLOATSQREG;
|
|---|
| 363 | # ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 364 | AssertCompileSize(X86YMMFLOATSQREG, 32);
|
|---|
| 365 | AssertCompileSize(X86YMMFLOATSQREG, sizeof(X86YMMREG));
|
|---|
| 366 | # endif
|
|---|
| 367 | /** Pointer to a YMM scalar quadruple-precision floating-point register. */
|
|---|
| 368 | typedef X86YMMFLOATSQREG *PX86YMMFLOATSQREG;
|
|---|
| 369 | /** Pointer to a const YMM scalar quadruple-precision floating-point register. */
|
|---|
| 370 | typedef X86YMMFLOATSQREG const *PCX86YMMFLOATSQREG;
|
|---|
| 371 |
|
|---|
| 372 |
|
|---|
| 373 | /*********************************************************************************************************************************
|
|---|
| 374 | * Global Variables *
|
|---|
| 375 | *********************************************************************************************************************************/
|
|---|
| 376 | static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false };
|
|---|
| 377 | static bool g_fAmdMisalignedSse = false;
|
|---|
| 378 | static uint8_t g_enmExtCtxMethod = BS3EXTCTXMETHOD_INVALID;
|
|---|
| 379 | static bool g_fMxCsrDazSupported = false;
|
|---|
| 380 |
|
|---|
| 381 | /** Zero value (indexed by fSign). */
|
|---|
| 382 | RTFLOAT32U const g_ar32Zero[] = { RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(1) };
|
|---|
| 383 | RTFLOAT64U const g_ar64Zero[] = { RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(1) };
|
|---|
| 384 |
|
|---|
| 385 | /** One value (indexed by fSign). */
|
|---|
| 386 | RTFLOAT32U const g_ar32One[] = { RTFLOAT32U_INIT_C(0, 0, RTFLOAT32U_EXP_BIAS),
|
|---|
| 387 | RTFLOAT32U_INIT_C(1, 0, RTFLOAT32U_EXP_BIAS) };
|
|---|
| 388 | RTFLOAT64U const g_ar64One[] = { RTFLOAT64U_INIT_C(0, 0, RTFLOAT64U_EXP_BIAS),
|
|---|
| 389 | RTFLOAT64U_INIT_C(1, 0, RTFLOAT64U_EXP_BIAS) };
|
|---|
| 390 |
|
|---|
| 391 | /** Infinity (indexed by fSign). */
|
|---|
| 392 | RTFLOAT32U const g_ar32Infinity[] = { RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(1) };
|
|---|
| 393 | RTFLOAT64U const g_ar64Infinity[] = { RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(1) };
|
|---|
| 394 |
|
|---|
| 395 | /** Default QNaNs (indexed by fSign). */
|
|---|
| 396 | RTFLOAT32U const g_ar32QNaN[] = { RTFLOAT32U_INIT_QNAN(0), RTFLOAT32U_INIT_QNAN(1) };
|
|---|
| 397 | RTFLOAT64U const g_ar64QNaN[] = { RTFLOAT64U_INIT_QNAN(0), RTFLOAT64U_INIT_QNAN(1) };
|
|---|
| 398 |
|
|---|
| 399 | /** Size of g_pbBuf - at least three pages. */
|
|---|
| 400 | static uint32_t g_cbBuf;
|
|---|
| 401 | /** Buffer of g_cbBuf size. */
|
|---|
| 402 | static uint8_t BS3_FAR *g_pbBuf;
|
|---|
| 403 | /** RW alias for the buffer memory at g_pbBuf. Set up by bs3CpuInstrXBufSetup. */
|
|---|
| 404 | static uint8_t BS3_FAR *g_pbBufAlias;
|
|---|
| 405 | /** RW alias for the memory at g_pbBuf. */
|
|---|
| 406 | static uint8_t BS3_FAR *g_pbBufAliasAlloc;
|
|---|
| 407 |
|
|---|
| 408 | /** Exception type \#2 test configurations, 16 & 32 bytes strictly aligned. */
|
|---|
| 409 | static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig2[] =
|
|---|
| 410 | {
|
|---|
| 411 | /*
|
|---|
| 412 | * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
|
|---|
| 413 | * +AVX +AVX +AMD/SSE +AMD/SSE
|
|---|
| 414 | * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
|
|---|
| 415 | * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
|
|---|
| 416 | { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
|
|---|
| 417 | { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
|
|---|
| 418 | { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
|
|---|
| 419 | { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
|
|---|
| 420 | { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
|
|---|
| 421 | { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
|
|---|
| 422 | { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
|
|---|
| 423 | { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
|
|---|
| 424 | { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
|
|---|
| 425 | { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
|
|---|
| 426 | /* Memory misalignment and alignment checks: */
|
|---|
| 427 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
|
|---|
| 428 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #11 */
|
|---|
| 429 | { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
|
|---|
| 430 | /* AMD only: */
|
|---|
| 431 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
|
|---|
| 432 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
|
|---|
| 433 | };
|
|---|
| 434 |
|
|---|
| 435 | /** Exception type \#3 test configurations (< 16-byte memory argument). */
|
|---|
| 436 | static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig3[] =
|
|---|
| 437 | {
|
|---|
| 438 | /*
|
|---|
| 439 | * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
|
|---|
| 440 | * +AVX +AVX +AMD/SSE +AMD/SSE
|
|---|
| 441 | * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
|
|---|
| 442 | * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
|
|---|
| 443 | { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
|
|---|
| 444 | { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
|
|---|
| 445 | { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
|
|---|
| 446 | { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
|
|---|
| 447 | { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
|
|---|
| 448 | { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
|
|---|
| 449 | { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
|
|---|
| 450 | { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
|
|---|
| 451 | { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
|
|---|
| 452 | { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
|
|---|
| 453 | /* Memory misalignment and alignment checks: */
|
|---|
| 454 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* [Avx]:DB */
|
|---|
| 455 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */ /* [Avx]:AC */
|
|---|
| 456 | { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
|
|---|
| 457 | /* AMD only: */
|
|---|
| 458 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
|
|---|
| 459 | { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
|
|---|
| 460 | };
|
|---|
| 461 |
|
|---|
| 462 |
|
|---|
| 463 | /**
|
|---|
| 464 | * Returns the name of an X86 exception given the vector.
|
|---|
| 465 | *
|
|---|
| 466 | * @returns Name of the exception.
|
|---|
| 467 | * @param uVector The exception vector.
|
|---|
| 468 | */
|
|---|
| 469 | static const char BS3_FAR *bs3CpuInstr4XcptName(uint8_t uVector)
|
|---|
| 470 | {
|
|---|
| 471 | switch (uVector)
|
|---|
| 472 | {
|
|---|
| 473 | case X86_XCPT_DE: return "#DE";
|
|---|
| 474 | case X86_XCPT_DB: return "#DB";
|
|---|
| 475 | case X86_XCPT_NMI: return "#NMI";
|
|---|
| 476 | case X86_XCPT_BP: return "#BP";
|
|---|
| 477 | case X86_XCPT_OF: return "#OF";
|
|---|
| 478 | case X86_XCPT_BR: return "#BR";
|
|---|
| 479 | case X86_XCPT_UD: return "#UD";
|
|---|
| 480 | case X86_XCPT_NM: return "#NM";
|
|---|
| 481 | case X86_XCPT_DF: return "#DF";
|
|---|
| 482 | case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
|
|---|
| 483 | case X86_XCPT_TS: return "#TS";
|
|---|
| 484 | case X86_XCPT_NP: return "#NP";
|
|---|
| 485 | case X86_XCPT_SS: return "#SS";
|
|---|
| 486 | case X86_XCPT_GP: return "#GP";
|
|---|
| 487 | case X86_XCPT_PF: return "#PF";
|
|---|
| 488 | case X86_XCPT_MF: return "#MF";
|
|---|
| 489 | case X86_XCPT_AC: return "#AC";
|
|---|
| 490 | case X86_XCPT_MC: return "#MC";
|
|---|
| 491 | case X86_XCPT_XF: return "#XF";
|
|---|
| 492 | case X86_XCPT_VE: return "#VE";
|
|---|
| 493 | case X86_XCPT_CP: return "#CP";
|
|---|
| 494 | case X86_XCPT_VC: return "#VC";
|
|---|
| 495 | case X86_XCPT_SX: return "#SX";
|
|---|
| 496 | }
|
|---|
| 497 | return "UNKNOWN";
|
|---|
| 498 | }
|
|---|
| 499 |
|
|---|
| 500 |
|
|---|
| 501 | DECL_FORCE_INLINE(bool) bs3CpuInstr4IsSse(uint8_t enmType)
|
|---|
| 502 | {
|
|---|
| 503 | return enmType >= T_SSE && enmType < T_AVX_128;
|
|---|
| 504 | }
|
|---|
| 505 |
|
|---|
| 506 |
|
|---|
| 507 | DECL_FORCE_INLINE(bool) bs3CpuInstr4IsAvx(uint8_t enmType)
|
|---|
| 508 | {
|
|---|
| 509 | return enmType >= T_AVX_128;
|
|---|
| 510 | }
|
|---|
| 511 |
|
|---|
| 512 |
|
|---|
| 513 | DECL_FORCE_INLINE(uint8_t) bs3CpuInstr4GetOperandSize(uint8_t enmType)
|
|---|
| 514 | {
|
|---|
| 515 | return enmType < T_128BITS ? 64/8
|
|---|
| 516 | : enmType < T_256BITS ? 128/8 : 256/8;
|
|---|
| 517 | }
|
|---|
| 518 |
|
|---|
| 519 |
|
|---|
| 520 | /**
|
|---|
| 521 | * Gets the names of floating-point exception flags that are set for a given MXCSR.
|
|---|
| 522 | *
|
|---|
| 523 | * @returns Names of floating-point exception flags that are set.
|
|---|
| 524 | * @param pszBuf Where to store the floating-point exception flags.
|
|---|
| 525 | * @param cchBuf The size of the buffer.
|
|---|
| 526 | * @param fMxCsr The MXCSR value.
|
|---|
| 527 | */
|
|---|
| 528 | static size_t bs3CpuInstr4GetXcptFlags(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t fMxCsr)
|
|---|
| 529 | {
|
|---|
| 530 | BS3_ASSERT(cchBuf >= BS3_FP_XCPT_NAMES_MAXLEN);
|
|---|
| 531 | if (!(fMxCsr & X86_MXCSR_XCPT_FLAGS))
|
|---|
| 532 | return Bs3StrPrintf(pszBuf, cchBuf, " None");
|
|---|
| 533 | return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", fMxCsr & X86_MXCSR_IE ? " IE" : "", fMxCsr & X86_MXCSR_DE ? " DE" : "",
|
|---|
| 534 | fMxCsr & X86_MXCSR_ZE ? " ZE" : "", fMxCsr & X86_MXCSR_OE ? " OE" : "",
|
|---|
| 535 | fMxCsr & X86_MXCSR_UE ? " UE" : "", fMxCsr & X86_MXCSR_PE ? " PE" : "");
|
|---|
| 536 | }
|
|---|
| 537 |
|
|---|
| 538 |
|
|---|
| 539 | /**
|
|---|
| 540 | * Reconfigures the execution environment according to @a pConfig.
|
|---|
| 541 | *
|
|---|
| 542 | * Call bs3CpuInstrXConfigRestore to undo the changes.
|
|---|
| 543 | *
|
|---|
| 544 | * @returns true on success, false if the configuration cannot be applied. In
|
|---|
| 545 | * the latter case, no context changes are made.
|
|---|
| 546 | * @param pSavedCfg Where to save state we modify.
|
|---|
| 547 | * @param pCtx The register context to modify.
|
|---|
| 548 | * @param pExtCtx The extended register context to modify.
|
|---|
| 549 | * @param pConfig The configuration to apply.
|
|---|
| 550 | * @param bMode The target mode.
|
|---|
| 551 | */
|
|---|
| 552 | static bool bs3CpuInstr4ConfigReconfigure(PBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx,
|
|---|
| 553 | PCBS3CPUINSTR4_CONFIG_T pConfig, uint8_t bMode)
|
|---|
| 554 | {
|
|---|
| 555 | /*
|
|---|
| 556 | * Save context bits we may change here
|
|---|
| 557 | */
|
|---|
| 558 | pSavedCfg->uCr0 = pCtx->cr0.u32;
|
|---|
| 559 | pSavedCfg->uCr4 = pCtx->cr4.u32;
|
|---|
| 560 | pSavedCfg->uEfl = pCtx->rflags.u32;
|
|---|
| 561 | pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx);
|
|---|
| 562 | pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx);
|
|---|
| 563 | pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx);
|
|---|
| 564 |
|
|---|
| 565 | /*
|
|---|
| 566 | * Can we make these changes?
|
|---|
| 567 | */
|
|---|
| 568 | if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse)
|
|---|
| 569 | return false;
|
|---|
| 570 |
|
|---|
| 571 | /*
|
|---|
| 572 | * Modify the test context.
|
|---|
| 573 | */
|
|---|
| 574 | if (pConfig->fCr0Mp)
|
|---|
| 575 | pCtx->cr0.u32 |= X86_CR0_MP;
|
|---|
| 576 | else
|
|---|
| 577 | pCtx->cr0.u32 &= ~X86_CR0_MP;
|
|---|
| 578 | if (pConfig->fCr0Em)
|
|---|
| 579 | pCtx->cr0.u32 |= X86_CR0_EM;
|
|---|
| 580 | else
|
|---|
| 581 | pCtx->cr0.u32 &= ~X86_CR0_EM;
|
|---|
| 582 | if (pConfig->fCr0Ts)
|
|---|
| 583 | pCtx->cr0.u32 |= X86_CR0_TS;
|
|---|
| 584 | else
|
|---|
| 585 | pCtx->cr0.u32 &= ~X86_CR0_TS;
|
|---|
| 586 |
|
|---|
| 587 | if (pConfig->fCr4OsFxSR)
|
|---|
| 588 | pCtx->cr4.u32 |= X86_CR4_OSFXSR;
|
|---|
| 589 | else
|
|---|
| 590 | pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
|
|---|
| 591 |
|
|---|
| 592 | if (pConfig->fCr4OsXmmExcpt && g_afTypeSupports[T_SSE])
|
|---|
| 593 | pCtx->cr4.u32 |= X86_CR4_OSXMMEEXCPT;
|
|---|
| 594 | else
|
|---|
| 595 | pCtx->cr4.u32 &= ~X86_CR4_OSXMMEEXCPT;
|
|---|
| 596 |
|
|---|
| 597 | if (pConfig->fCr4OsFxSR)
|
|---|
| 598 | pCtx->cr4.u32 |= X86_CR4_OSFXSR;
|
|---|
| 599 | else
|
|---|
| 600 | pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
|
|---|
| 601 |
|
|---|
| 602 | if (pConfig->fCr4OsXSave)
|
|---|
| 603 | pCtx->cr4.u32 |= X86_CR4_OSXSAVE;
|
|---|
| 604 | else
|
|---|
| 605 | pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE;
|
|---|
| 606 |
|
|---|
| 607 | if (pConfig->fXcr0Sse)
|
|---|
| 608 | pExtCtx->fXcr0Saved |= XSAVE_C_SSE;
|
|---|
| 609 | else
|
|---|
| 610 | pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE;
|
|---|
| 611 | if (pConfig->fXcr0Avx && g_afTypeSupports[T_AVX_256])
|
|---|
| 612 | pExtCtx->fXcr0Saved |= XSAVE_C_YMM;
|
|---|
| 613 | else
|
|---|
| 614 | pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM;
|
|---|
| 615 |
|
|---|
| 616 | if (pConfig->fAlignCheck)
|
|---|
| 617 | {
|
|---|
| 618 | pCtx->rflags.u32 |= X86_EFL_AC;
|
|---|
| 619 | pCtx->cr0.u32 |= X86_CR0_AM;
|
|---|
| 620 | }
|
|---|
| 621 | else
|
|---|
| 622 | {
|
|---|
| 623 | pCtx->rflags.u32 &= ~X86_EFL_AC;
|
|---|
| 624 | pCtx->cr0.u32 &= ~X86_CR0_AM;
|
|---|
| 625 | }
|
|---|
| 626 |
|
|---|
| 627 | /** @todo Can we remove this? x87 FPU and SIMD are independent. */
|
|---|
| 628 | Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B));
|
|---|
| 629 |
|
|---|
| 630 | if (pConfig->fMxCsrMM)
|
|---|
| 631 | Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM);
|
|---|
| 632 | else
|
|---|
| 633 | Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM);
|
|---|
| 634 | return true;
|
|---|
| 635 | }
|
|---|
| 636 |
|
|---|
| 637 |
|
|---|
| 638 | /**
|
|---|
| 639 | * Undoes changes made by bs3CpuInstr4ConfigReconfigure.
|
|---|
| 640 | */
|
|---|
| 641 | static void bs3CpuInstrXConfigRestore(PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx)
|
|---|
| 642 | {
|
|---|
| 643 | pCtx->cr0.u32 = pSavedCfg->uCr0;
|
|---|
| 644 | pCtx->cr4.u32 = pSavedCfg->uCr4;
|
|---|
| 645 | pCtx->rflags.u32 = pSavedCfg->uEfl;
|
|---|
| 646 | pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal;
|
|---|
| 647 | Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw);
|
|---|
| 648 | Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw);
|
|---|
| 649 | Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr);
|
|---|
| 650 | }
|
|---|
| 651 |
|
|---|
| 652 |
|
|---|
| 653 | /**
|
|---|
| 654 | * Allocates three extended CPU contexts and initializes the first one
|
|---|
| 655 | * with random data.
|
|---|
| 656 | * @returns First extended context, initialized with randomish data. NULL on
|
|---|
| 657 | * failure (complained).
|
|---|
| 658 | * @param ppExtCtx2 Where to return the 2nd context.
|
|---|
| 659 | */
|
|---|
| 660 | static PBS3EXTCTX bs3CpuInstrXAllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2)
|
|---|
| 661 | {
|
|---|
| 662 | /* Allocate extended context structures. */
|
|---|
| 663 | uint64_t fFlags;
|
|---|
| 664 | uint16_t cb = Bs3ExtCtxGetSize(&fFlags);
|
|---|
| 665 | PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2);
|
|---|
| 666 | PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb);
|
|---|
| 667 | if (pExtCtx1)
|
|---|
| 668 | {
|
|---|
| 669 | Bs3ExtCtxInit(pExtCtx1, cb, fFlags);
|
|---|
| 670 | /** @todo populate with semi-random stuff. */
|
|---|
| 671 |
|
|---|
| 672 | Bs3ExtCtxInit(pExtCtx2, cb, fFlags);
|
|---|
| 673 | *ppExtCtx2 = pExtCtx2;
|
|---|
| 674 | return pExtCtx1;
|
|---|
| 675 | }
|
|---|
| 676 | Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2);
|
|---|
| 677 | *ppExtCtx2 = NULL;
|
|---|
| 678 | return NULL;
|
|---|
| 679 | }
|
|---|
| 680 |
|
|---|
| 681 |
|
|---|
| 682 | /**
|
|---|
| 683 | * Frees the extended CPU contexts allocated by bs3CpuInstrXAllocExtCtxs.
|
|---|
| 684 | *
|
|---|
| 685 | * @param pExtCtx1 The first extended context.
|
|---|
| 686 | * @param pExtCtx2 The second extended context.
|
|---|
| 687 | */
|
|---|
| 688 | static void bs3CpuInstrXFreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
|
|---|
| 689 | {
|
|---|
| 690 | RT_NOREF_PV(pExtCtx2);
|
|---|
| 691 | Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2);
|
|---|
| 692 | }
|
|---|
| 693 |
|
|---|
| 694 |
|
|---|
| 695 | /**
|
|---|
| 696 | * Sets up SSE and AVX bits relevant for FPU instructions.
|
|---|
| 697 | */
|
|---|
| 698 | static void bs3CpuInstr4SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx)
|
|---|
| 699 | {
|
|---|
| 700 | /* CR0: */
|
|---|
| 701 | uint32_t cr0 = Bs3RegGetCr0();
|
|---|
| 702 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
|
|---|
| 703 | cr0 |= X86_CR0_NE;
|
|---|
| 704 | Bs3RegSetCr0(cr0);
|
|---|
| 705 |
|
|---|
| 706 | /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */
|
|---|
| 707 | pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
|
|---|
| 708 | pCtx->cr0.u32 |= X86_CR0_NE;
|
|---|
| 709 |
|
|---|
| 710 | /* CR4: */
|
|---|
| 711 | BS3_ASSERT( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
|
|---|
| 712 | || pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE);
|
|---|
| 713 | {
|
|---|
| 714 | uint32_t cr4 = Bs3RegGetCr4();
|
|---|
| 715 | if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
|
|---|
| 716 | {
|
|---|
| 717 | cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE;
|
|---|
| 718 | Bs3RegSetCr4(cr4);
|
|---|
| 719 | Bs3RegSetXcr0(pExtCtx->fXcr0Nominal);
|
|---|
| 720 | }
|
|---|
| 721 | else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
|
|---|
| 722 | {
|
|---|
| 723 | cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT;
|
|---|
| 724 | Bs3RegSetCr4(cr4);
|
|---|
| 725 | }
|
|---|
| 726 | pCtx->cr4.u32 = cr4;
|
|---|
| 727 | }
|
|---|
| 728 | }
|
|---|
| 729 |
|
|---|
| 730 |
|
|---|
| 731 | /**
|
|---|
| 732 | * Configures the buffer with electric fences in paged modes.
|
|---|
| 733 | *
|
|---|
| 734 | * @returns Adjusted buffer pointer.
|
|---|
| 735 | * @param pbBuf The buffer pointer.
|
|---|
| 736 | * @param pcbBuf Pointer to the buffer size (input & output).
|
|---|
| 737 | * @param bMode The testing target mode.
|
|---|
| 738 | */
|
|---|
| 739 | DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode)
|
|---|
| 740 | {
|
|---|
| 741 | if (BS3_MODE_IS_PAGED(bMode))
|
|---|
| 742 | {
|
|---|
| 743 | int rc;
|
|---|
| 744 | uint32_t cbBuf = *pcbBuf;
|
|---|
| 745 | Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P);
|
|---|
| 746 | Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P);
|
|---|
| 747 | pbBuf += X86_PAGE_SIZE;
|
|---|
| 748 | cbBuf -= X86_PAGE_SIZE * 2;
|
|---|
| 749 | *pcbBuf = cbBuf;
|
|---|
| 750 |
|
|---|
| 751 | g_pbBufAlias = g_pbBufAliasAlloc;
|
|---|
| 752 | rc = Bs3PagingAlias((uintptr_t)g_pbBufAlias, (uintptr_t)pbBuf, cbBuf + X86_PAGE_SIZE, /* must include the tail guard pg */
|
|---|
| 753 | X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
|
|---|
| 754 | if (RT_FAILURE(rc))
|
|---|
| 755 | Bs3TestFailedF("Bs3PagingAlias failed on %p/%p LB %#x: %d", g_pbBufAlias, pbBuf, cbBuf, rc);
|
|---|
| 756 | }
|
|---|
| 757 | else
|
|---|
| 758 | g_pbBufAlias = pbBuf;
|
|---|
| 759 | return pbBuf;
|
|---|
| 760 | }
|
|---|
| 761 |
|
|---|
| 762 |
|
|---|
| 763 | /**
|
|---|
| 764 | * Undoes what bs3CpuInstrXBufSetup did.
|
|---|
| 765 | *
|
|---|
| 766 | * @param pbBuf The buffer pointer.
|
|---|
| 767 | * @param cbBuf The buffer size.
|
|---|
| 768 | * @param bMode The testing target mode.
|
|---|
| 769 | */
|
|---|
| 770 | DECLINLINE(void) bs3CpuInstrXBufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode)
|
|---|
| 771 | {
|
|---|
| 772 | if (BS3_MODE_IS_PAGED(bMode))
|
|---|
| 773 | {
|
|---|
| 774 | Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0);
|
|---|
| 775 | Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0);
|
|---|
| 776 | }
|
|---|
| 777 | }
|
|---|
| 778 |
|
|---|
| 779 |
|
|---|
| 780 | /**
|
|---|
| 781 | * Gets a buffer of a @a cbMemOp sized operand according to the given
|
|---|
| 782 | * configuration and alignment restrictions.
|
|---|
| 783 | *
|
|---|
| 784 | * @returns Pointer to the buffer.
|
|---|
| 785 | * @param pbBuf The buffer pointer.
|
|---|
| 786 | * @param cbBuf The buffer size.
|
|---|
| 787 | * @param cbMemOp The operand size.
|
|---|
| 788 | * @param cbAlign The operand alignment restriction.
|
|---|
| 789 | * @param pConfig The configuration.
|
|---|
| 790 | * @param fPageFault The \#PF test setting.
|
|---|
| 791 | */
|
|---|
| 792 | DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign,
|
|---|
| 793 | PCBS3CPUINSTR4_CONFIG_T pConfig, unsigned fPageFault)
|
|---|
| 794 | {
|
|---|
| 795 | /* All allocations are at the tail end of the buffer, so that we've got a
|
|---|
| 796 | guard page following the operand. When asked to consistenly trigger
|
|---|
| 797 | a #PF, we slide the buffer into that guard page. */
|
|---|
| 798 | if (fPageFault)
|
|---|
| 799 | cbBuf += X86_PAGE_SIZE;
|
|---|
| 800 |
|
|---|
| 801 | if (pConfig->fAligned)
|
|---|
| 802 | {
|
|---|
| 803 | if (!pConfig->fAlignCheck)
|
|---|
| 804 | return &pbBuf[cbBuf - cbMemOp];
|
|---|
| 805 | return &pbBuf[cbBuf - cbMemOp - cbAlign];
|
|---|
| 806 | }
|
|---|
| 807 | return &pbBuf[cbBuf - cbMemOp - 1];
|
|---|
| 808 | }
|
|---|
| 809 |
|
|---|
| 810 |
|
|---|
| 811 | /**
|
|---|
| 812 | * Determines the size of memory operands.
|
|---|
| 813 | */
|
|---|
| 814 | DECLINLINE(uint8_t) bs3CpuInstrXMemOpSize(uint8_t cbOperand, uint8_t enmRm)
|
|---|
| 815 | {
|
|---|
| 816 | if (enmRm <= RM_MEM)
|
|---|
| 817 | return cbOperand;
|
|---|
| 818 | if (enmRm == RM_MEM8)
|
|---|
| 819 | return sizeof(uint8_t);
|
|---|
| 820 | if (enmRm == RM_MEM16)
|
|---|
| 821 | return sizeof(uint16_t);
|
|---|
| 822 | if (enmRm == RM_MEM32)
|
|---|
| 823 | return sizeof(uint32_t);
|
|---|
| 824 | if (enmRm == RM_MEM64)
|
|---|
| 825 | return sizeof(uint64_t);
|
|---|
| 826 | BS3_ASSERT(0);
|
|---|
| 827 | return cbOperand;
|
|---|
| 828 | }
|
|---|
| 829 |
|
|---|
| 830 |
|
|---|
| 831 | /*
|
|---|
| 832 | * Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly
|
|---|
| 833 | * skips a large fraction of the micro-tests. It is sufficiently random
|
|---|
| 834 | * that over a large number of runs, all micro-tests will be hit.
|
|---|
| 835 | *
|
|---|
| 836 | * This improves the runtime of the worst case (`#define ALL_TESTS' on a
|
|---|
| 837 | * debug build, run with '--execute-all-in-iem') from ~9000 to ~800 seconds
|
|---|
| 838 | * (on an Intel Core i7-10700, fwiw).
|
|---|
| 839 | *
|
|---|
| 840 | * To activate this 'developer's speed-testing mode', turn on
|
|---|
| 841 | * `#define BS3_SKIPIT_DO_SKIP' here.
|
|---|
| 842 | *
|
|---|
| 843 | * BS3_SKIPIT_AVG_SKIP governs approximately how many micro-tests are
|
|---|
| 844 | * skipped in a row; e.g. the default of 26 means about every 27th
|
|---|
| 845 | * micro-test is run during a particular test run. (This is not 27x
|
|---|
| 846 | * faster due to other activities which are not skipped!) Note this is
|
|---|
| 847 | * only an average; the actual skips are random.
|
|---|
| 848 | *
|
|---|
| 849 | * You can also modify bs3CpuInstrX_SkipIt() to focus on specific sub-tests,
|
|---|
| 850 | * using its (currently ignored) `bRing, iCfg, iTest, iVal, iVariant' args
|
|---|
| 851 | * (to enable this: turn on `#define BS3_SKIPIT_DO_ARGS': which costs about
|
|---|
| 852 | * 3% performance).
|
|---|
| 853 | *
|
|---|
| 854 | * Note! The skipping is not compatible with testing the native recompiler as
|
|---|
| 855 | * it requires the test code to be run a number of times before it kicks
|
|---|
| 856 | * in and does the native recompilation (currently around 16 times).
|
|---|
| 857 | */
|
|---|
| 858 | #define BS3_SKIPIT_AVG_SKIP 26
|
|---|
| 859 | #define BS3_SKIPIT_REPORT_COUNT 150000
|
|---|
| 860 | #undef BS3_SKIPIT_DO_SKIP
|
|---|
| 861 | #undef BS3_SKIPIT_DO_ARGS
|
|---|
| 862 |
|
|---|
| 863 | #ifndef BS3_SKIPIT_DO_SKIP
|
|---|
| 864 | # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) (false)
|
|---|
| 865 | #else
|
|---|
| 866 | # include <iprt/asm-amd64-x86.h>
|
|---|
| 867 | # include <iprt/asm-math.h>
|
|---|
| 868 |
|
|---|
| 869 | DECLINLINE(uint32_t) bs3CpuInstrX_SimpleRand(void)
|
|---|
| 870 | {
|
|---|
| 871 | /*
|
|---|
| 872 | * A simple Lehmer linear congruential pseudo-random number
|
|---|
| 873 | * generator using the constants suggested by Park & Miller:
|
|---|
| 874 | *
|
|---|
| 875 | * modulus = 2^31 - 1 (INT32_MAX)
|
|---|
| 876 | * multiplier = 7^5 (16807)
|
|---|
| 877 | *
|
|---|
| 878 | * It produces numbers in the range [1..INT32_MAX-1] and is
|
|---|
| 879 | * more chaotic in the higher bits.
|
|---|
| 880 | *
|
|---|
| 881 | * Note! Runtime/common/rand/randparkmiller.cpp is also use this algorithm,
|
|---|
| 882 | * though the zero handling is different.
|
|---|
| 883 | */
|
|---|
| 884 | static uint32_t s_uSeedMemory = 0;
|
|---|
| 885 | uint32_t uVal = s_uSeedMemory;
|
|---|
| 886 | if (!uVal)
|
|---|
| 887 | uVal = (uint32_t)ASMReadTSC();
|
|---|
| 888 | uVal = ASMModU64ByU32RetU32(ASMMult2xU32RetU64(uVal, 16807), INT32_MAX);
|
|---|
| 889 | s_uSeedMemory = uVal;
|
|---|
| 890 | return uVal;
|
|---|
| 891 | }
|
|---|
| 892 |
|
|---|
| 893 | static unsigned g_cSeen, g_cSkipped;
|
|---|
| 894 |
|
|---|
| 895 | static void bs3CpuInstrX_ShowTallies(void)
|
|---|
| 896 | {
|
|---|
| 897 | Bs3TestPrintf("Micro-tests %d: tested %d / skipped %d\n", g_cSeen, g_cSeen - g_cSkipped, g_cSkipped);
|
|---|
| 898 | }
|
|---|
| 899 |
|
|---|
| 900 | # ifdef BS3_SKIPIT_DO_ARGS
|
|---|
| 901 | # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt(bRing, iCfg, iTest, iVal, iVariant)
|
|---|
| 902 | static bool bs3CpuInstrX_SkipIt(uint8_t bRing, unsigned iCfg, unsigned iTest, unsigned iVal, unsigned iVariant)
|
|---|
| 903 | # else
|
|---|
| 904 | # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt()
|
|---|
| 905 | static bool bs3CpuInstrX_SkipIt(void)
|
|---|
| 906 | # endif
|
|---|
| 907 | {
|
|---|
| 908 | static unsigned s_uTimes = 0;
|
|---|
| 909 | bool fSkip;
|
|---|
| 910 |
|
|---|
| 911 | /* Cache calls to the relatively expensive random routine */
|
|---|
| 912 | if (!s_uTimes)
|
|---|
| 913 | s_uTimes = bs3CpuInstrX_SimpleRand() % (BS3_SKIPIT_AVG_SKIP * 2 + 1) + 1;
|
|---|
| 914 | fSkip = --s_uTimes > 0;
|
|---|
| 915 | if (fSkip)
|
|---|
| 916 | ++g_cSkipped;
|
|---|
| 917 |
|
|---|
| 918 | if (++g_cSeen % BS3_SKIPIT_REPORT_COUNT == 0)
|
|---|
| 919 | bs3CpuInstrX_ShowTallies();
|
|---|
| 920 | return fSkip;
|
|---|
| 921 | }
|
|---|
| 922 |
|
|---|
| 923 | #endif /* BS3_SKIPIT_DO_SKIP */
|
|---|
| 924 |
|
|---|
| 925 | /*
|
|---|
| 926 | * Test type #1.
|
|---|
| 927 | * Generic YMM registers.
|
|---|
| 928 | */
|
|---|
| 929 | typedef struct BS3CPUINSTR4_TEST1_VALUES_T
|
|---|
| 930 | {
|
|---|
| 931 | X86YMMREG uSrc2; /**< Second source operand. */
|
|---|
| 932 | X86YMMREG uSrc1; /**< uDstIn for SSE */
|
|---|
| 933 | X86YMMREG uDstOut; /**< Destination output. */
|
|---|
| 934 | uint32_t fMxCsrMask; /**< MXCSR exception mask. */
|
|---|
| 935 | uint32_t fDenormalsAreZero; /**< DAZ (Denormals-Are-Zero) exception mask. */
|
|---|
| 936 | uint32_t fFlushToZero; /**< Flush-To-Zero (FZ) exception mask. */
|
|---|
| 937 | uint32_t fRoundingCtlMask; /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
|
|---|
| 938 | uint32_t f128ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 128-bit instruction. */
|
|---|
| 939 | uint32_t f256ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 256-bit instructions. */
|
|---|
| 940 | } BS3CPUINSTR4_TEST1_VALUES_T;
|
|---|
| 941 |
|
|---|
| 942 | /*
|
|---|
| 943 | * Test type #1.
|
|---|
| 944 | * Packed single-precision.
|
|---|
| 945 | */
|
|---|
| 946 | typedef struct BS3CPUINSTR4_TEST1_VALUES_PS_T
|
|---|
| 947 | {
|
|---|
| 948 | X86YMMFLOATPSREG uSrc2; /**< Second source operand. */
|
|---|
| 949 | X86YMMFLOATPSREG uSrc1; /**< uDstIn for SSE */
|
|---|
| 950 | X86YMMFLOATPSREG uDstOut; /**< Destination output. */
|
|---|
| 951 | uint32_t fMxCsrMask; /**< MXCSR exception mask. */
|
|---|
| 952 | uint32_t fDenormalsAreZero; /**< DAZ (Denormals-Are-Zero) exception mask. */
|
|---|
| 953 | uint32_t fFlushToZero; /**< Flush-To-Zero (FZ) exception mask. */
|
|---|
| 954 | uint32_t fRoundingCtlMask; /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
|
|---|
| 955 | uint32_t f128ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 128-bit instruction. */
|
|---|
| 956 | uint32_t f256ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 256-bit instructions. */
|
|---|
| 957 | } BS3CPUINSTR4_TEST1_VALUES_PS_T;
|
|---|
| 958 | AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
|
|---|
| 959 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
|
|---|
| 960 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
|
|---|
| 961 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
|
|---|
| 962 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fMxCsrMask, BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
|
|---|
| 963 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fDenormalsAreZero, BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
|
|---|
| 964 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fFlushToZero, BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
|
|---|
| 965 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fRoundingCtlMask, BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
|
|---|
| 966 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f128ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f128ExpectedMxCsrFlags);
|
|---|
| 967 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f256ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f256ExpectedMxCsrFlags);
|
|---|
| 968 |
|
|---|
| 969 | /*
|
|---|
| 970 | * Test type #1.
|
|---|
| 971 | * Packed double-precision.
|
|---|
| 972 | */
|
|---|
| 973 | typedef struct BS3CPUINSTR4_TEST1_VALUES_PD_T
|
|---|
| 974 | {
|
|---|
| 975 | X86YMMFLOATPDREG uSrc2; /**< Second source operand. */
|
|---|
| 976 | X86YMMFLOATPDREG uSrc1; /**< uDstIn for SSE */
|
|---|
| 977 | X86YMMFLOATPDREG uDstOut; /**< Destination output. */
|
|---|
| 978 | uint32_t fMxCsrMask; /**< MXCSR exception mask. */
|
|---|
| 979 | uint32_t fDenormalsAreZero; /**< DAZ (Denormals-Are-Zero) exception mask. */
|
|---|
| 980 | uint32_t fFlushToZero; /**< Flush-To-Zero (FZ) exception mask. */
|
|---|
| 981 | uint32_t fRoundingCtlMask; /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
|
|---|
| 982 | uint32_t f128ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 128-bit instruction. */
|
|---|
| 983 | uint32_t f256ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 256-bit instructions. */
|
|---|
| 984 | } BS3CPUINSTR4_TEST1_VALUES_PD_T;
|
|---|
| 985 | AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
|
|---|
| 986 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
|
|---|
| 987 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
|
|---|
| 988 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
|
|---|
| 989 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fMxCsrMask, BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
|
|---|
| 990 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fDenormalsAreZero, BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
|
|---|
| 991 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fFlushToZero, BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
|
|---|
| 992 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fRoundingCtlMask, BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
|
|---|
| 993 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f128ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f128ExpectedMxCsrFlags);
|
|---|
| 994 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f256ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f256ExpectedMxCsrFlags);
|
|---|
| 995 |
|
|---|
| 996 | /*
|
|---|
| 997 | * Test type #1.
|
|---|
| 998 | * Scalar single-precision.
|
|---|
| 999 | */
|
|---|
| 1000 | typedef struct BS3CPUINSTR4_TEST1_VALUES_SS_T
|
|---|
| 1001 | {
|
|---|
| 1002 | X86YMMFLOATSSREG uSrc2; /**< Second source operand. */
|
|---|
| 1003 | X86YMMFLOATSSREG uSrc1; /**< uDstIn for SSE */
|
|---|
| 1004 | X86YMMFLOATSSREG uDstOut; /**< Destination output. */
|
|---|
| 1005 | uint32_t fMxCsrMask; /**< MXCSR exception mask. */
|
|---|
| 1006 | uint32_t fDenormalsAreZero; /**< DAZ (Denormals-Are-Zero) exception mask. */
|
|---|
| 1007 | uint32_t fFlushToZero; /**< Flush-To-Zero (FZ) exception mask. */
|
|---|
| 1008 | uint32_t fRoundingCtlMask; /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
|
|---|
| 1009 | uint32_t f128ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 128-bit instruction. */
|
|---|
| 1010 | uint32_t f256ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 256-bit instructions. */
|
|---|
| 1011 | } BS3CPUINSTR4_TEST1_VALUES_SS_T;
|
|---|
| 1012 | AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
|
|---|
| 1013 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
|
|---|
| 1014 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
|
|---|
| 1015 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
|
|---|
| 1016 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, fMxCsrMask, BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
|
|---|
| 1017 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, fDenormalsAreZero, BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
|
|---|
| 1018 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, fFlushToZero, BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
|
|---|
| 1019 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, fRoundingCtlMask, BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
|
|---|
| 1020 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f128ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f128ExpectedMxCsrFlags);
|
|---|
| 1021 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f256ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f256ExpectedMxCsrFlags);
|
|---|
| 1022 |
|
|---|
| 1023 | /*
|
|---|
| 1024 | * Test type #1.
|
|---|
| 1025 | * Scalar quadruple-precision.
|
|---|
| 1026 | */
|
|---|
| 1027 | typedef struct BS3CPUINSTR4_TEST1_VALUES_SQ_T
|
|---|
| 1028 | {
|
|---|
| 1029 | X86YMMFLOATSQREG uSrc2; /**< Second source operand. */
|
|---|
| 1030 | X86YMMFLOATSQREG uSrc1; /**< uDstIn for SSE */
|
|---|
| 1031 | X86YMMFLOATSQREG uDstOut; /**< Destination output. */
|
|---|
| 1032 | uint32_t fMxCsrMask; /**< MXCSR exception mask. */
|
|---|
| 1033 | uint32_t fDenormalsAreZero; /**< DAZ (Denormals-Are-Zero) exception mask. */
|
|---|
| 1034 | uint32_t fFlushToZero; /**< Flush-To-Zero (FZ) exception mask. */
|
|---|
| 1035 | uint32_t fRoundingCtlMask; /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
|
|---|
| 1036 | uint32_t f128ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 128-bit instruction. */
|
|---|
| 1037 | uint32_t f256ExpectedMxCsrFlags; /**< Expected MXCSR exception flags for 256-bit instructions. */
|
|---|
| 1038 | } BS3CPUINSTR4_TEST1_VALUES_SQ_T;
|
|---|
| 1039 | AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SQ_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
|
|---|
| 1040 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
|
|---|
| 1041 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
|
|---|
| 1042 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
|
|---|
| 1043 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fMxCsrMask, BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
|
|---|
| 1044 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fDenormalsAreZero, BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
|
|---|
| 1045 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fFlushToZero, BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
|
|---|
| 1046 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fRoundingCtlMask, BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
|
|---|
| 1047 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f128ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f128ExpectedMxCsrFlags);
|
|---|
| 1048 | AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f256ExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, f256ExpectedMxCsrFlags);
|
|---|
| 1049 |
|
|---|
| 1050 | typedef struct BS3CPUINSTR4_TEST1_T
|
|---|
| 1051 | {
|
|---|
| 1052 | FPFNBS3FAR pfnWorker; /**< Test function worker. */
|
|---|
| 1053 | uint8_t bAvxMisalignXcpt; /**< AVX misalignment exception. */
|
|---|
| 1054 | uint8_t enmRm; /**< R/M type. */
|
|---|
| 1055 | uint8_t enmType; /**< CPU instruction type (see T_XXX). */
|
|---|
| 1056 | uint8_t iRegDst; /**< Index of destination register, UINT8_MAX if N/A. */
|
|---|
| 1057 | uint8_t iRegSrc1; /**< Index of first source register, UINT8_MAX if N/A. */
|
|---|
| 1058 | uint8_t iRegSrc2; /**< Index of second source register, UINT8_MAX if N/A. */
|
|---|
| 1059 | uint8_t cValues; /**< Number of test values in @c paValues. */
|
|---|
| 1060 | BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *paValues; /**< Test values. */
|
|---|
| 1061 | } BS3CPUINSTR4_TEST1_T;
|
|---|
| 1062 |
|
|---|
| 1063 | typedef struct BS3CPUINSTR4_TEST1_MODE_T
|
|---|
| 1064 | {
|
|---|
| 1065 | BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests;
|
|---|
| 1066 | unsigned cTests;
|
|---|
| 1067 | } BS3CPUINSTR4_TEST1_MODE_T;
|
|---|
| 1068 |
|
|---|
| 1069 | /** Initializer for a BS3CPUINSTR4_TEST1_MODE_T array (three entries). */
|
|---|
| 1070 | #define BS3CPUINSTR4_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
|
|---|
| 1071 | { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
|
|---|
| 1072 |
|
|---|
| 1073 | typedef struct BS3CPUINSTR4_TEST1_CTX_T
|
|---|
| 1074 | {
|
|---|
| 1075 | BS3CPUINSTR4_CONFIG_T const BS3_FAR *pConfig; /**< The test execution environment configuration. */
|
|---|
| 1076 | BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest; /**< The instruction being tested. */
|
|---|
| 1077 | unsigned iVal; /**< Which iteration of the test value is this. */
|
|---|
| 1078 | const char BS3_FAR *pszMode; /**< The testing mode (e.g. real, protected, paged and permutations). */
|
|---|
| 1079 | PBS3TRAPFRAME pTrapFrame; /**< The exception (trap) frame. */
|
|---|
| 1080 | PBS3REGCTX pCtx; /**< The general-purpose register context. */
|
|---|
| 1081 | PBS3EXTCTX pExtCtx; /**< The extended (FPU) register context. */
|
|---|
| 1082 | PBS3EXTCTX pExtCtxOut; /**< The output extended (FPU) register context. */
|
|---|
| 1083 | uint8_t BS3_FAR *puMemOp; /**< The memory operand buffer. */
|
|---|
| 1084 | uint8_t BS3_FAR *puMemOpAlias; /**< The memory operand alias buffer for comparing result. */
|
|---|
| 1085 | uint8_t cbMemOp; /**< Size of the memory operand (and alias) buffer in bytes. */
|
|---|
| 1086 | uint8_t cbOperand; /**< Size of the instruction operand (8 for MMX, 16 for SSE etc). */
|
|---|
| 1087 | uint8_t cbInstr; /**< Size of the instruction opcode. */
|
|---|
| 1088 | uint8_t bXcptExpect; /**< The expected exception while/after executing the instruction. */
|
|---|
| 1089 | uint16_t idTestStep; /**< The test iteration step. */
|
|---|
| 1090 | } BS3CPUINSTR4_TEST1_CTX_T;
|
|---|
| 1091 | /** Pointer to a test 1 context. */
|
|---|
| 1092 | typedef BS3CPUINSTR4_TEST1_CTX_T BS3_FAR *PBS3CPUINSTR4_TEST1_CTX_T;
|
|---|
| 1093 |
|
|---|
| 1094 |
|
|---|
| 1095 | /**
|
|---|
| 1096 | * Worker for bs3CpuInstr4_WorkerTestType1.
|
|---|
| 1097 | */
|
|---|
| 1098 | static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
|
|---|
| 1099 | PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
|
|---|
| 1100 | {
|
|---|
| 1101 | BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = pTestCtx->pTest;
|
|---|
| 1102 | BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
|
|---|
| 1103 | PBS3TRAPFRAME pTrapFrame = pTestCtx->pTrapFrame;
|
|---|
| 1104 | PBS3REGCTX pCtx = pTestCtx->pCtx;
|
|---|
| 1105 | PBS3EXTCTX pExtCtx = pTestCtx->pExtCtx;
|
|---|
| 1106 | PBS3EXTCTX pExtCtxOut = pTestCtx->pExtCtxOut;
|
|---|
| 1107 | uint8_t BS3_FAR *puMemOp = pTestCtx->puMemOp;
|
|---|
| 1108 | uint8_t BS3_FAR *puMemOpAlias = pTestCtx->puMemOpAlias;
|
|---|
| 1109 | uint8_t cbMemOp = pTestCtx->cbMemOp;
|
|---|
| 1110 | uint8_t const cbOperand = pTestCtx->cbOperand;
|
|---|
| 1111 | uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)pTestCtx->pTest->pfnWorker)[-1];
|
|---|
| 1112 | uint8_t bXcptExpect = pTestCtx->bXcptExpect;
|
|---|
| 1113 | uint8_t const bFpXcpt = pTestCtx->pConfig->fCr4OsXmmExcpt ? X86_XCPT_XF : X86_XCPT_UD;
|
|---|
| 1114 | uint32_t const fExpectedMxCsrFlags = pTestCtx->cbOperand > 16 ? pValues->f256ExpectedMxCsrFlags
|
|---|
| 1115 | : pValues->f128ExpectedMxCsrFlags;
|
|---|
| 1116 | bool const fFpFlagsExpect = RT_BOOL( (fExpectedMxCsrFlags
|
|---|
| 1117 | & (~pValues->fMxCsrMask >> X86_MXCSR_XCPT_MASK_SHIFT)) & X86_MXCSR_XCPT_FLAGS);
|
|---|
| 1118 | bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
|
|---|
| 1119 | uint32_t uMxCsr;
|
|---|
| 1120 | X86YMMREG MemOpExpect;
|
|---|
| 1121 | uint16_t cErrors;
|
|---|
| 1122 |
|
|---|
| 1123 | /*
|
|---|
| 1124 | * Set up the context and some expectations.
|
|---|
| 1125 | */
|
|---|
| 1126 | /* Destination. */
|
|---|
| 1127 | Bs3MemZero(&MemOpExpect, sizeof(MemOpExpect));
|
|---|
| 1128 | if (pTest->iRegDst == UINT8_MAX)
|
|---|
| 1129 | {
|
|---|
| 1130 | BS3_ASSERT(pTest->enmRm >= RM_MEM);
|
|---|
| 1131 | Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp);
|
|---|
| 1132 | if (bXcptExpect == X86_XCPT_DB)
|
|---|
| 1133 | MemOpExpect.ymm = pValues->uDstOut.ymm;
|
|---|
| 1134 | else
|
|---|
| 1135 | Bs3MemSet(&MemOpExpect, 0xcc, sizeof(MemOpExpect));
|
|---|
| 1136 | }
|
|---|
| 1137 |
|
|---|
| 1138 | /* Source #1 (/ destination for SSE). */
|
|---|
| 1139 | if (pTest->iRegSrc1 == UINT8_MAX)
|
|---|
| 1140 | {
|
|---|
| 1141 | BS3_ASSERT(pTest->enmRm >= RM_MEM);
|
|---|
| 1142 | Bs3MemCpy(puMemOpAlias, &pValues->uSrc1, cbMemOp);
|
|---|
| 1143 | if (pTest->iRegDst == UINT8_MAX)
|
|---|
| 1144 | BS3_ASSERT(fSseInstr);
|
|---|
| 1145 | else
|
|---|
| 1146 | MemOpExpect.ymm = pValues->uSrc1.ymm;
|
|---|
| 1147 | }
|
|---|
| 1148 | else if (fSseInstr)
|
|---|
| 1149 | Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm.DQWords.dqw0);
|
|---|
| 1150 | else
|
|---|
| 1151 | Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm, 32);
|
|---|
| 1152 |
|
|---|
| 1153 | /* Source #2. */
|
|---|
| 1154 | if (pTest->iRegSrc2 == UINT8_MAX)
|
|---|
| 1155 | {
|
|---|
| 1156 | BS3_ASSERT(pTest->enmRm >= RM_MEM);
|
|---|
| 1157 | BS3_ASSERT(pTest->iRegDst != UINT8_MAX && pTest->iRegSrc1 != UINT8_MAX);
|
|---|
| 1158 | Bs3MemCpy(puMemOpAlias, &pValues->uSrc2, cbMemOp);
|
|---|
| 1159 | MemOpExpect.ymm = pValues->uSrc2.ymm;
|
|---|
| 1160 | }
|
|---|
| 1161 | else if (fSseInstr)
|
|---|
| 1162 | Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm.DQWords.dqw0);
|
|---|
| 1163 | else
|
|---|
| 1164 | Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm, 32);
|
|---|
| 1165 |
|
|---|
| 1166 | /* Memory pointer. */
|
|---|
| 1167 | if (pTest->enmRm >= RM_MEM)
|
|---|
| 1168 | {
|
|---|
| 1169 | BS3_ASSERT( pTest->iRegDst == UINT8_MAX
|
|---|
| 1170 | || pTest->iRegSrc1 == UINT8_MAX
|
|---|
| 1171 | || pTest->iRegSrc2 == UINT8_MAX);
|
|---|
| 1172 | Bs3RegCtxSetGrpSegFromCurPtr(pCtx, &pCtx->rbx, &pCtx->fs, puMemOp);
|
|---|
| 1173 | }
|
|---|
| 1174 |
|
|---|
| 1175 | /* Setup MXCSR for the current test. */
|
|---|
| 1176 | uMxCsr = (pSavedCfg->uMxCsr & ~(X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_MASK))
|
|---|
| 1177 | | (pValues->fMxCsrMask & X86_MXCSR_XCPT_MASK)
|
|---|
| 1178 | | (pValues->fRoundingCtlMask & X86_MXCSR_RC_MASK);
|
|---|
| 1179 | if ( pValues->fDenormalsAreZero == X86_MXCSR_DAZ
|
|---|
| 1180 | && g_fMxCsrDazSupported)
|
|---|
| 1181 | uMxCsr |= X86_MXCSR_DAZ;
|
|---|
| 1182 | if (pValues->fFlushToZero == X86_MXCSR_FZ)
|
|---|
| 1183 | uMxCsr |= X86_MXCSR_FZ;
|
|---|
| 1184 | Bs3ExtCtxSetMxCsr(pExtCtx, uMxCsr);
|
|---|
| 1185 |
|
|---|
| 1186 | /*
|
|---|
| 1187 | * Prepare globals and execute.
|
|---|
| 1188 | */
|
|---|
| 1189 | g_uBs3TrapEipHint = pCtx->rip.u32;
|
|---|
| 1190 | if ( bXcptExpect == X86_XCPT_DB
|
|---|
| 1191 | && !fFpFlagsExpect)
|
|---|
| 1192 | g_uBs3TrapEipHint += cbInstr + 1;
|
|---|
| 1193 | Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut);
|
|---|
| 1194 |
|
|---|
| 1195 | /*
|
|---|
| 1196 | * Check the result.
|
|---|
| 1197 | *
|
|---|
| 1198 | * If a floating-point exception is expected, the destination is not updated by the instruction.
|
|---|
| 1199 | * In the case of SSE instructions, updating the destination here will work because it is the same
|
|---|
| 1200 | * as the source, but for AVX++ it won't because the destination is different and would contain 0s.
|
|---|
| 1201 | */
|
|---|
| 1202 | cErrors = Bs3TestSubErrorCount();
|
|---|
| 1203 | if ( bXcptExpect == X86_XCPT_DB
|
|---|
| 1204 | && !fFpFlagsExpect
|
|---|
| 1205 | && pTest->iRegDst != UINT8_MAX)
|
|---|
| 1206 | {
|
|---|
| 1207 | if (fSseInstr)
|
|---|
| 1208 | Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm.DQWords.dqw0);
|
|---|
| 1209 | else
|
|---|
| 1210 | Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm, cbOperand);
|
|---|
| 1211 | }
|
|---|
| 1212 | #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */
|
|---|
| 1213 | if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE
|
|---|
| 1214 | && pExtCtx->Ctx.x.Hdr.bmXState == 0x7
|
|---|
| 1215 | && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3)
|
|---|
| 1216 | pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7;
|
|---|
| 1217 | #endif
|
|---|
| 1218 | if (bXcptExpect == X86_XCPT_DB)
|
|---|
| 1219 | Bs3ExtCtxSetMxCsr(pExtCtx, (uMxCsr & ~X86_MXCSR_XCPT_FLAGS)
|
|---|
| 1220 | | (fExpectedMxCsrFlags & X86_MXCSR_XCPT_FLAGS));
|
|---|
| 1221 | Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pTestCtx->pszMode, pTestCtx->idTestStep);
|
|---|
| 1222 |
|
|---|
| 1223 | if (bXcptExpect == X86_XCPT_DB)
|
|---|
| 1224 | {
|
|---|
| 1225 | uint32_t const fMxCsrXcptFlags = Bs3ExtCtxGetMxCsr(pExtCtxOut) & X86_MXCSR_XCPT_FLAGS;
|
|---|
| 1226 |
|
|---|
| 1227 | /* Check if the SIMD FP exception flags (or lack of) are as expected. */
|
|---|
| 1228 | if (fMxCsrXcptFlags != (fExpectedMxCsrFlags & X86_MXCSR_XCPT_FLAGS))
|
|---|
| 1229 | {
|
|---|
| 1230 | char szGotBuf[BS3_FP_XCPT_NAMES_MAXLEN];
|
|---|
| 1231 | char szExpectBuf[BS3_FP_XCPT_NAMES_MAXLEN];
|
|---|
| 1232 | bs3CpuInstr4GetXcptFlags(&szExpectBuf[0], sizeof(szExpectBuf), fExpectedMxCsrFlags);
|
|---|
| 1233 | bs3CpuInstr4GetXcptFlags(&szGotBuf[0], sizeof(szGotBuf), fMxCsrXcptFlags);
|
|---|
| 1234 | Bs3TestFailedF("Expected floating-point xcpt flags%s, got%s", szExpectBuf, szGotBuf);
|
|---|
| 1235 | }
|
|---|
| 1236 |
|
|---|
| 1237 | /* Check if the SIMD FP exception (or lack of) is as expected. */
|
|---|
| 1238 | if (fFpFlagsExpect)
|
|---|
| 1239 | {
|
|---|
| 1240 | if (pTrapFrame->bXcpt == bFpXcpt)
|
|---|
| 1241 | { /* likely */ }
|
|---|
| 1242 | else
|
|---|
| 1243 | Bs3TestFailedF("Expected floating-point xcpt %s, got %s", bs3CpuInstr4XcptName(bFpXcpt),
|
|---|
| 1244 | bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
|
|---|
| 1245 | }
|
|---|
| 1246 | else if (pTrapFrame->bXcpt == X86_XCPT_DB)
|
|---|
| 1247 | { /* likely */ }
|
|---|
| 1248 | else
|
|---|
| 1249 | Bs3TestFailedF("Expected no xcpt, got %s", bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
|
|---|
| 1250 | }
|
|---|
| 1251 | /* Check if non-FP exception is as expected. */
|
|---|
| 1252 | else if (pTrapFrame->bXcpt != bXcptExpect)
|
|---|
| 1253 | Bs3TestFailedF("Expected xcpt %s, got %s", bs3CpuInstr4XcptName(bXcptExpect), bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
|
|---|
| 1254 |
|
|---|
| 1255 | /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
|
|---|
| 1256 | if (bMode == BS3_MODE_RM && (pCtx->rflags.u32 & X86_EFL_AC))
|
|---|
| 1257 | {
|
|---|
| 1258 | if (pTrapFrame->Ctx.rflags.u32 & X86_EFL_AC)
|
|---|
| 1259 | Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", pTrapFrame->bXcpt);
|
|---|
| 1260 | pTrapFrame->Ctx.rflags.u32 |= X86_EFL_AC;
|
|---|
| 1261 | }
|
|---|
| 1262 | if (bXcptExpect == X86_XCPT_PF)
|
|---|
| 1263 | pCtx->cr2.u = (uintptr_t)puMemOp;
|
|---|
| 1264 | Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, bXcptExpect == X86_XCPT_DB && !fFpFlagsExpect ? cbInstr + 1 : 0, 0 /*cbSpAdjust*/,
|
|---|
| 1265 | (bXcptExpect == X86_XCPT_DB && !fFpFlagsExpect) || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
|
|---|
| 1266 | pTestCtx->pszMode, pTestCtx->idTestStep);
|
|---|
| 1267 | pCtx->cr2.u = 0;
|
|---|
| 1268 |
|
|---|
| 1269 | if ( pTest->enmRm >= RM_MEM
|
|---|
| 1270 | && Bs3MemCmp(puMemOpAlias, &MemOpExpect, cbMemOp) != 0)
|
|---|
| 1271 | Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &MemOpExpect, cbMemOp, puMemOpAlias);
|
|---|
| 1272 |
|
|---|
| 1273 | return cErrors;
|
|---|
| 1274 | }
|
|---|
| 1275 |
|
|---|
| 1276 |
|
|---|
| 1277 | /**
|
|---|
| 1278 | * Test type #1 worker.
|
|---|
| 1279 | */
|
|---|
| 1280 | static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
|
|---|
| 1281 | PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs)
|
|---|
| 1282 | {
|
|---|
| 1283 | BS3REGCTX Ctx;
|
|---|
| 1284 | BS3TRAPFRAME TrapFrame;
|
|---|
| 1285 | const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
|
|---|
| 1286 | uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
|
|---|
| 1287 | uint8_t BS3_FAR *pbBuf = g_pbBuf;
|
|---|
| 1288 | uint32_t cbBuf = g_cbBuf;
|
|---|
| 1289 | PBS3EXTCTX pExtCtxOut;
|
|---|
| 1290 | PBS3EXTCTX pExtCtx = bs3CpuInstrXAllocExtCtxs(&pExtCtxOut);
|
|---|
| 1291 | if (pExtCtx)
|
|---|
| 1292 | { /* likely */ }
|
|---|
| 1293 | else
|
|---|
| 1294 | return 0;
|
|---|
| 1295 | if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
|
|---|
| 1296 | { /* likely */ }
|
|---|
| 1297 | else
|
|---|
| 1298 | {
|
|---|
| 1299 | Bs3TestPrintf("Skipped due to ancient FPU state format\n");
|
|---|
| 1300 | return 0;
|
|---|
| 1301 | }
|
|---|
| 1302 |
|
|---|
| 1303 | /* Ensure the structures are allocated before we sample the stack pointer. */
|
|---|
| 1304 | Bs3MemSet(&Ctx, 0, sizeof(Ctx));
|
|---|
| 1305 | Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
|
|---|
| 1306 |
|
|---|
| 1307 | /*
|
|---|
| 1308 | * Create test context.
|
|---|
| 1309 | */
|
|---|
| 1310 | pbBuf = bs3CpuInstrXBufSetup(pbBuf, &cbBuf, bMode);
|
|---|
| 1311 | Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
|
|---|
| 1312 | bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx);
|
|---|
| 1313 |
|
|---|
| 1314 | /*
|
|---|
| 1315 | * Run the tests in all rings since alignment issues may behave
|
|---|
| 1316 | * differently in ring-3 compared to ring-0.
|
|---|
| 1317 | */
|
|---|
| 1318 | for (;;)
|
|---|
| 1319 | {
|
|---|
| 1320 | unsigned fPf = 0;
|
|---|
| 1321 | do
|
|---|
| 1322 | {
|
|---|
| 1323 | unsigned iCfg;
|
|---|
| 1324 | for (iCfg = 0; iCfg < cConfigs; iCfg++)
|
|---|
| 1325 | {
|
|---|
| 1326 | unsigned iTest;
|
|---|
| 1327 | BS3CPUINSTRX_CONFIG_SAVED_T SavedCfg;
|
|---|
| 1328 | if (!bs3CpuInstr4ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
|
|---|
| 1329 | continue; /* unsupported config */
|
|---|
| 1330 |
|
|---|
| 1331 | /*
|
|---|
| 1332 | * Iterate the tests.
|
|---|
| 1333 | */
|
|---|
| 1334 | for (iTest = 0; iTest < cTests; iTest++)
|
|---|
| 1335 | {
|
|---|
| 1336 | BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = &paTests[iTest];
|
|---|
| 1337 | unsigned const cValues = pTest->cValues;
|
|---|
| 1338 | bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
|
|---|
| 1339 | bool const fAvxInstr = bs3CpuInstr4IsAvx(pTest->enmType);
|
|---|
| 1340 | uint8_t const cbOperand = bs3CpuInstr4GetOperandSize(pTest->enmType);
|
|---|
| 1341 | uint8_t const cbMemOp = bs3CpuInstrXMemOpSize(cbOperand, pTest->enmRm);
|
|---|
| 1342 | uint8_t const cbAlign = cbMemOp;
|
|---|
| 1343 | uint8_t BS3_FAR *puMemOp = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf);
|
|---|
| 1344 | uint8_t *puMemOpAlias = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf];
|
|---|
| 1345 | uint8_t bXcptExpect = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD
|
|---|
| 1346 | : fSseInstr ? paConfigs[iCfg].bXcptSse
|
|---|
| 1347 | : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
|
|---|
| 1348 | uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
|
|---|
| 1349 | unsigned cRecompRuns = 0;
|
|---|
| 1350 | unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues;
|
|---|
| 1351 | unsigned iVal;
|
|---|
| 1352 |
|
|---|
| 1353 | /* If testing unaligned memory accesses (or #PF), skip register-only tests. This
|
|---|
| 1354 | allows setting bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
|
|---|
| 1355 | if ( (pTest->enmRm == RM_REG || pTest->enmRm == RM_MEM8)
|
|---|
| 1356 | && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf))
|
|---|
| 1357 | continue;
|
|---|
| 1358 |
|
|---|
| 1359 | /* #AC is only raised in ring-3. */
|
|---|
| 1360 | if (bXcptExpect == X86_XCPT_AC)
|
|---|
| 1361 | {
|
|---|
| 1362 | if (bRing != 3)
|
|---|
| 1363 | bXcptExpect = X86_XCPT_DB;
|
|---|
| 1364 | else if (fAvxInstr)
|
|---|
| 1365 | bXcptExpect = pTest->bAvxMisalignXcpt; /* they generally don't raise #AC */
|
|---|
| 1366 | }
|
|---|
| 1367 |
|
|---|
| 1368 | if (fPf && bXcptExpect == X86_XCPT_DB)
|
|---|
| 1369 | bXcptExpect = X86_XCPT_PF;
|
|---|
| 1370 |
|
|---|
| 1371 | Bs3RegCtxSetRipCsFromCurPtr(&Ctx, pTest->pfnWorker);
|
|---|
| 1372 |
|
|---|
| 1373 | /*
|
|---|
| 1374 | * Iterate the test values and do the actual testing.
|
|---|
| 1375 | */
|
|---|
| 1376 | while (cRecompRuns < cMaxRecompRuns)
|
|---|
| 1377 | {
|
|---|
| 1378 | for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
|
|---|
| 1379 | {
|
|---|
| 1380 | uint16_t cErrors;
|
|---|
| 1381 | BS3CPUINSTR4_TEST1_CTX_T TestCtx;
|
|---|
| 1382 | uint32_t const fExpectedMxCsrFlags = pTest->enmType >= T_128BITS
|
|---|
| 1383 | ? pTest->paValues[iVal].f128ExpectedMxCsrFlags
|
|---|
| 1384 | : pTest->paValues[iVal].f256ExpectedMxCsrFlags;
|
|---|
| 1385 |
|
|---|
| 1386 | if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0))
|
|---|
| 1387 | continue;
|
|---|
| 1388 |
|
|---|
| 1389 | /*
|
|---|
| 1390 | * If the hardware does not support DAZ bit and we are testing DE exceptions,
|
|---|
| 1391 | * then skip testing them. We still want to test values that set the MXCSR.DAZ
|
|---|
| 1392 | * if we are not expecting DE exceptions to make sure DAZ bit in and of itself
|
|---|
| 1393 | * is not influencing other cases.
|
|---|
| 1394 | */
|
|---|
| 1395 | if ( !g_fMxCsrDazSupported
|
|---|
| 1396 | && pTest->paValues[iVal].fDenormalsAreZero == X86_MXCSR_DAZ
|
|---|
| 1397 | && (fExpectedMxCsrFlags & X86_MXCSR_DE))
|
|---|
| 1398 | continue;
|
|---|
| 1399 |
|
|---|
| 1400 | /*
|
|---|
| 1401 | * Setup the test instruction context and pass it to the worker.
|
|---|
| 1402 | * A few of these can be figured out by the worker but initializing
|
|---|
| 1403 | * it outside the inner most loop is more optimal.
|
|---|
| 1404 | */
|
|---|
| 1405 | TestCtx.pConfig = &paConfigs[iCfg];
|
|---|
| 1406 | TestCtx.pTest = pTest;
|
|---|
| 1407 | TestCtx.iVal = iVal;
|
|---|
| 1408 | TestCtx.pszMode = pszMode;
|
|---|
| 1409 | TestCtx.pTrapFrame = &TrapFrame;
|
|---|
| 1410 | TestCtx.pCtx = &Ctx;
|
|---|
| 1411 | TestCtx.pExtCtx = pExtCtx;
|
|---|
| 1412 | TestCtx.pExtCtxOut = pExtCtxOut;
|
|---|
| 1413 | TestCtx.puMemOp = (uint8_t *)puMemOp;
|
|---|
| 1414 | TestCtx.puMemOpAlias = puMemOpAlias;
|
|---|
| 1415 | TestCtx.cbMemOp = cbMemOp;
|
|---|
| 1416 | TestCtx.cbOperand = cbOperand;
|
|---|
| 1417 | TestCtx.bXcptExpect = bXcptExpect;
|
|---|
| 1418 | TestCtx.idTestStep = idTestStep;
|
|---|
| 1419 | cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
|
|---|
| 1420 | if (cErrors != Bs3TestSubErrorCount())
|
|---|
| 1421 | {
|
|---|
| 1422 | if (paConfigs[iCfg].fAligned)
|
|---|
| 1423 | Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, %s %u-bit)",
|
|---|
| 1424 | Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
|
|---|
| 1425 | bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), fSseInstr ? "SSE" : "AVX", cbOperand * 8);
|
|---|
| 1426 | else
|
|---|
| 1427 | Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, puMemOp=%p, EFLAGS=%#RX32, %s %u-bit)",
|
|---|
| 1428 | Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
|
|---|
| 1429 | bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), puMemOp,
|
|---|
| 1430 | TrapFrame.Ctx.rflags.u32, fSseInstr ? "SSE" : "AVX", cbOperand * 8);
|
|---|
| 1431 | Bs3TestPrintf("\n");
|
|---|
| 1432 | }
|
|---|
| 1433 | }
|
|---|
| 1434 | }
|
|---|
| 1435 | }
|
|---|
| 1436 | bs3CpuInstrXConfigRestore(&SavedCfg, &Ctx, pExtCtx);
|
|---|
| 1437 | }
|
|---|
| 1438 | } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode));
|
|---|
| 1439 |
|
|---|
| 1440 | /*
|
|---|
| 1441 | * Next ring.
|
|---|
| 1442 | */
|
|---|
| 1443 | bRing++;
|
|---|
| 1444 | if (bRing > 3 || bMode == BS3_MODE_RM)
|
|---|
| 1445 | break;
|
|---|
| 1446 | Bs3RegCtxConvertToRingX(&Ctx, bRing);
|
|---|
| 1447 | }
|
|---|
| 1448 |
|
|---|
| 1449 | /*
|
|---|
| 1450 | * Cleanup.
|
|---|
| 1451 | */
|
|---|
| 1452 | bs3CpuInstrXBufCleanup(pbBuf, cbBuf, bMode);
|
|---|
| 1453 | bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut);
|
|---|
| 1454 | return 0;
|
|---|
| 1455 | }
|
|---|
| 1456 |
|
|---|
| 1457 |
|
|---|
| 1458 | /*
|
|---|
| 1459 | * [V]ADDPS.
|
|---|
| 1460 | */
|
|---|
| 1461 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addps(uint8_t bMode)
|
|---|
| 1462 | {
|
|---|
| 1463 | static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
|
|---|
| 1464 | {
|
|---|
| 1465 | /*
|
|---|
| 1466 | * Zero.
|
|---|
| 1467 | */
|
|---|
| 1468 | /* 0*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1469 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1470 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1471 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1472 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1473 | /*flags */ 0, 0 },
|
|---|
| 1474 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1475 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1476 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1477 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1478 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1479 | /*flags */ 0, 0 },
|
|---|
| 1480 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1481 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1482 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1483 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1484 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1485 | /*flags */ 0, 0 },
|
|---|
| 1486 | { { /*src2 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 1487 | { /*src1 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 1488 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 1489 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1490 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1491 | /*flags */ 0, 0 },
|
|---|
| 1492 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 1493 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 1494 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 1495 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1496 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1497 | /*flags */ 0, 0 },
|
|---|
| 1498 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 1499 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 1500 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 1501 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1502 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 1503 | /*flags */ 0, 0 },
|
|---|
| 1504 | /*
|
|---|
| 1505 | * Infinity.
|
|---|
| 1506 | */
|
|---|
| 1507 | /* 6*/{ { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1508 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1509 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1510 | /*mask */ X86_MXCSR_IM,
|
|---|
| 1511 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1512 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1513 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1514 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1515 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1516 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1517 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1518 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1519 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1520 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1521 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1522 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1523 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 1524 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 1525 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 1526 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 1527 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(0) } },
|
|---|
| 1528 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1529 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 1530 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 1531 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(0) } },
|
|---|
| 1532 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_INF(1) } },
|
|---|
| 1533 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1), BS3_FP32_INF(1) } },
|
|---|
| 1534 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1535 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1536 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1537 | /*
|
|---|
| 1538 | * Overflow, Precision.
|
|---|
| 1539 | */
|
|---|
| 1540 | /*11*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1541 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1542 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), } },
|
|---|
| 1543 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1544 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1545 | /*flags */ 0, X86_MXCSR_OE },
|
|---|
| 1546 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1547 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1548 | { /* => */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1549 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 1550 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1551 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1552 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1553 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1554 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_VAL(1, 0, 2), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_VAL(1, 0, 2), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 1555 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 1556 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 1557 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1558 | { { /*src2 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1) } },
|
|---|
| 1559 | { /*src1 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1) } },
|
|---|
| 1560 | { /* => */ { BS3_FP32_VAL(1, 0, 2), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_VAL(1, 0, 2) } },
|
|---|
| 1561 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 1562 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1563 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1564 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1565 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1566 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1567 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1568 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1569 | /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1570 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1571 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1572 | { /* => */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 1573 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 1574 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1575 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1576 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 1577 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 1578 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX + 1) } },
|
|---|
| 1579 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1580 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1581 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 1582 | /*
|
|---|
| 1583 | * Normals.
|
|---|
| 1584 | */
|
|---|
| 1585 | /*18*/{ { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7f)/* 1.75*/, BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7d)/*0.25*/, BS3_FP32_VAL(0, 0x600000, 0x7f)/* 1.75*/, BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7d)/*0.25*/ } },
|
|---|
| 1586 | { /*src1 */ { BS3_FP32_VAL(1, 0, 0x7d)/*-0.25*/, BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7e)/*0.50*/, BS3_FP32_VAL(1, 0, 0x7d)/*-0.25*/, BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7e)/*0.50*/ } },
|
|---|
| 1587 | { /* => */ { BS3_FP32_VAL(0, 0x400000, 0x7f)/* 1.50*/, BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x400000, 0x7e)/*0.75*/, BS3_FP32_VAL(0, 0x400000, 0x7f)/* 1.50*/, BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x400000, 0x7e)/*0.75*/ } },
|
|---|
| 1588 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1589 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 1590 | /*flags */ 0, 0 },
|
|---|
| 1591 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1592 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1593 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1594 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1595 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1596 | /*flags */ 0, 0 },
|
|---|
| 1597 | { { /*src2 */ { BS3_FP32_VAL(0, 0x5ca5b8, 0x93)/*1807543*/, BS3_FP32_VAL(0, 0x5c0000, 0x84)/*55*/, BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x5c0000, 0x84)/*55*/, BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_VAL(0, 0x534000, 0x86)/*211.25*/, BS3_FP32_ZERO(0) } },
|
|---|
| 1598 | { /*src1 */ { BS3_FP32_VAL(0, 0x1ea980, 0x8f)/* 81235*/, BS3_FP32_VAL(0, 0x600000, 0x81)/* 7*/, BS3_FP32_VAL(0, 0x7c9000, 0x88)/* 1010.25*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x600000, 0x81)/* 7*/, BS3_FP32_VAL(0, 0x7c9000, 0x88)/* 1010.25*/, BS3_FP32_ONE(1) /*- 1.00*/, BS3_FP32_ZERO(0) } },
|
|---|
| 1599 | { /* => */ { BS3_FP32_VAL(0, 0x669050, 0x93)/*1888778*/, BS3_FP32_VAL(0, 0x780000, 0x84)/*62*/, BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357.00*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x780000, 0x84)/*62*/, BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357.00*/, BS3_FP32_VAL(0, 0x524000, 0x86)/*210.25*/, BS3_FP32_ZERO(0) } },
|
|---|
| 1600 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1601 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1602 | /*flags */ 0, 0 },
|
|---|
| 1603 | { { /*src2 */ { BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ONE(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1604 | { /*src1 */ { BS3_FP32_VAL(1, 0x712060, 0x92)/*- 987654*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_VAL(1, 0x712060, 0x92)/*- 987654*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ONE(0), BS3_FP32_ONE(0) } },
|
|---|
| 1605 | { /* => */ { BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_VAL(0, 0x3c614e, 0x97)/*24691356*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_VAL(0, 0x3c614e, 0x97)/*24691356*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(0) } },
|
|---|
| 1606 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1607 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1608 | /*flags */ 0, 0 },
|
|---|
| 1609 | { { /*src2 */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1610 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1611 | { /* => */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 1612 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1613 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1614 | /*flags */ 0, 0 },
|
|---|
| 1615 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(1), BS3_FP32_ONE(1), BS3_FP32_ZERO(1), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(1), } },
|
|---|
| 1616 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), } },
|
|---|
| 1617 | { /* => */ { BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ZERO(1), BS3_FP32_ONE(1), BS3_FP32_ZERO(1), BS3_FP32_ONE(1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1) } },
|
|---|
| 1618 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1619 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1620 | /*flags */ 0, 0 },
|
|---|
| 1621 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0) } },
|
|---|
| 1622 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0) } },
|
|---|
| 1623 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0, 2) , BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0, 2) } },
|
|---|
| 1624 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1625 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1626 | /*flags */ 0, 0 },
|
|---|
| 1627 | { { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/, BS3_FP32_VAL(0, 0x3ce348, 0x90)/*193421.125*/, BS3_FP32_VAL(0, 0x6423f2, 0x92)/*934463.125*/, BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0x16b43a, 0x93)/*1234567.25*/, BS3_FP32_VAL(0, 0x792318, 0x91)/*510232.75*/, BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/ } },
|
|---|
| 1628 | { /*src1 */ { BS3_FP32_VAL(0, 0x769b50, 0x92)/*1010101.000*/, BS3_FP32_VAL(0, 0x430ebc, 0x91)/*399477.875*/, BS3_FP32_VAL(1, 0x0a19f0, 0x8f)/*-70707.875*/, BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0x00c6d3, 0x94)/*2109876.75*/, BS3_FP32_VAL(1, 0x316740, 0x8e)/*-45415.25*/, BS3_FP32_VAL(0, 0x769b50, 0x92)/*1010101.000*/ } },
|
|---|
| 1629 | { /* => */ { BS3_FP32_VAL(0, 0x769b5e, 0x92)/*1010101.875*/, BS3_FP32_VAL(0, 0x10c030, 0x92)/*592899.000*/, BS3_FP32_VAL(0, 0x52e0b4, 0x92)/*863755.250*/, BS3_FP32_VAL(1, 0, 2), BS3_FP32_VAL(0, 0, 2), BS3_FP32_VAL(0, 0x4c20f0, 0x94)/*3344444.00*/, BS3_FP32_VAL(0, 0x62f630, 0x91)/*464817.50*/, BS3_FP32_VAL(0, 0x769b5e, 0x92)/*1010101.875*/ } },
|
|---|
| 1630 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1631 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 1632 | /*flags */ 0, 0 },
|
|---|
| 1633 | /*
|
|---|
| 1634 | * Denormals.
|
|---|
| 1635 | */
|
|---|
| 1636 | /*26*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1637 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 1638 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 1639 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1640 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1641 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 1642 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1643 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1644 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1645 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1646 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1647 | /*flags */ 0, 0 },
|
|---|
| 1648 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 1649 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0) } },
|
|---|
| 1650 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), } },
|
|---|
| 1651 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1652 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1653 | /*flags */ 0, 0 },
|
|---|
| 1654 | { { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1655 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1656 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1657 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1658 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1659 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 1660 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 1661 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1662 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1663 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1664 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1665 | /*flags */ 0, 0 },
|
|---|
| 1666 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 1667 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0) } },
|
|---|
| 1668 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) , BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1669 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1670 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1671 | /*flags */ 0, 0 },
|
|---|
| 1672 | /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 1673 | };
|
|---|
| 1674 |
|
|---|
| 1675 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 1676 | {
|
|---|
| 1677 | { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1678 | { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1679 |
|
|---|
| 1680 | { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1681 | { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1682 |
|
|---|
| 1683 | { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1684 | { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1685 | };
|
|---|
| 1686 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 1687 | {
|
|---|
| 1688 | { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1689 | { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1690 |
|
|---|
| 1691 | { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1692 | { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1693 |
|
|---|
| 1694 | { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1695 | { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1696 | };
|
|---|
| 1697 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 1698 | {
|
|---|
| 1699 | { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1700 | { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1701 |
|
|---|
| 1702 | { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1703 | { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1704 |
|
|---|
| 1705 | { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1706 | { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1707 |
|
|---|
| 1708 | { bs3CpuInstr4_addps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1709 | { bs3CpuInstr4_addps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1710 |
|
|---|
| 1711 | { bs3CpuInstr4_vaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1712 | { bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1713 | };
|
|---|
| 1714 |
|
|---|
| 1715 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 1716 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 1717 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 1718 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 1719 | }
|
|---|
| 1720 |
|
|---|
| 1721 |
|
|---|
| 1722 | /*
|
|---|
| 1723 | * [V]ADDPD.
|
|---|
| 1724 | */
|
|---|
| 1725 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addpd(uint8_t bMode)
|
|---|
| 1726 | {
|
|---|
| 1727 | static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
|
|---|
| 1728 | {
|
|---|
| 1729 | /*
|
|---|
| 1730 | * Zero.
|
|---|
| 1731 | */
|
|---|
| 1732 | /* 0*/{ { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1733 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1734 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1735 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1736 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1737 | /*flags */ 0, 0 },
|
|---|
| 1738 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1739 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1740 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1741 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1742 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 1743 | /*flags */ 0, 0 },
|
|---|
| 1744 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1745 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1746 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1747 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1748 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_DOWN,
|
|---|
| 1749 | /*flags */ 0, 0 },
|
|---|
| 1750 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 1751 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 1752 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 1753 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1754 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1755 | /*flags */ 0, 0 },
|
|---|
| 1756 | { { /*src2 */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1757 | { /*src1 */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1758 | { /* => */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1759 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1760 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1761 | /*flags */ 0, 0 },
|
|---|
| 1762 | /*
|
|---|
| 1763 | * Infinity.
|
|---|
| 1764 | */
|
|---|
| 1765 | /* 5*/{ { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1766 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1767 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1768 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 1769 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1770 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1771 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1772 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1773 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1774 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 1775 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 1776 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1777 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1778 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1779 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1780 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 1781 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1782 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1783 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_INF(1) } },
|
|---|
| 1784 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 1785 | { /* => */ { BS3_FP64_QNAN(1), BS3_FP64_QNAN(1), BS3_FP64_ZERO(0), BS3_FP64_QNAN(1) } },
|
|---|
| 1786 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1787 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1788 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 1789 | { { /*src2 */ { BS3_FP64_VAL(0, 0, 0x3fd)/*0.25*/, BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_INF(1) } },
|
|---|
| 1790 | { /*src1 */ { BS3_FP64_VAL(0, 0, 0x3fe)/*0.50*/, BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 1791 | { /* => */ { BS3_FP64_VAL(0, 0x8000000000000, 0x3fe)/*0.75*/, BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_QNAN(1) } },
|
|---|
| 1792 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1793 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1794 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 1795 | /*
|
|---|
| 1796 | * Overflow, Precision.
|
|---|
| 1797 | */
|
|---|
| 1798 | /*10*/{ { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 1799 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 1800 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1801 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1802 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1803 | /*flags */ X86_MXCSR_OE, X86_MXCSR_OE },
|
|---|
| 1804 | { { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1805 | { /*src1 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1806 | { /* => */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1807 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1808 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1809 | /*flags */ X86_MXCSR_OE, X86_MXCSR_OE },
|
|---|
| 1810 | { { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 1811 | { /*src1 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 1812 | { /* => */ { BS3_FP64_INF(0), BS3_FP64_VAL(1, 0, 2), BS3_FP64_ZERO(0), BS3_FP64_INF(0), } },
|
|---|
| 1813 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 1814 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 1815 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1816 | { { /*src2 */ { BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1817 | { /*src1 */ { BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0) } },
|
|---|
| 1818 | { /* => */ { BS3_FP64_VAL(1, 0, 2), BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1819 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 1820 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1821 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1822 | { { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 1823 | { /*src1 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 1824 | { /* => */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 1825 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1826 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1827 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 1828 | { { /*src2 */ { BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 1829 | { /*src1 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 1830 | { /* => */ { BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_VAL(1, BS3_FP64_FRACTION_NORMAL_MAX, BS3_FP64_EXP_SAFE_INT_MAX + 1) } },
|
|---|
| 1831 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1832 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1833 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 1834 | /** @todo Why does the below on cause PE?! */
|
|---|
| 1835 | { { /*src2 */ { BS3_FP64_VAL(0, 0xc000000000000, 0x3ff)/* 1.75*/, BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0, 0x3fd)/*0.25*/ } },
|
|---|
| 1836 | { /*src1 */ { BS3_FP64_VAL(1, 0, 0x07d)/*-0.25*/, BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0, 0x3fe)/*0.50*/ } },
|
|---|
| 1837 | { /* => */ { BS3_FP64_VAL(0, 0xbffffffffffff, 0x3ff)/* 1.50*/, BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0x8000000000000, 0x3fe)/*0.75*/ } },
|
|---|
| 1838 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1839 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 1840 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 1841 | /*
|
|---|
| 1842 | * Normals.
|
|---|
| 1843 | */
|
|---|
| 1844 | /*17*/{ { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_VAL_1(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1845 | { /*src1 */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_VAL_1(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1846 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1847 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1848 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1849 | /*flags */ 0, 0 },
|
|---|
| 1850 | { { /*src2 */ { BS3_FP64_VAL(0, 0, 0x409)/*1024*/, BS3_FP64_VAL(0, 0xb800000000000, 0x404)/*55*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1851 | { /*src1 */ { BS3_FP64_VAL(0, 0, 0x408)/* 512*/, BS3_FP64_VAL(0, 0xc000000000000, 0x401)/* 7*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1852 | { /* => */ { BS3_FP64_VAL(0, 0x8000000000000, 0x409)/*1536*/, BS3_FP64_VAL(0, 0xf000000000000, 0x404)/*62*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1853 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1854 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1855 | /*flags */ 0, 0 },
|
|---|
| 1856 | { { /*src2 */ { BS3_FP64_VAL(0, 0x26580b4800000, 0x41d)/* 1234567890*/, BS3_FP64_VAL(0, 0xd6f3458800000, 0x41c)/*987654321*/, BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
|
|---|
| 1857 | { /*src1 */ { BS3_FP64_VAL(1, 0x26580b4800000, 0x41d)/*-1234567890*/, BS3_FP64_VAL(1, 0x9000000000000, 0x405)/* -100*/, BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } },
|
|---|
| 1858 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xd6f3426800000, 0x41c)/*987654221*/, BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
|
|---|
| 1859 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1860 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1861 | /*flags */ 0, 0 },
|
|---|
| 1862 | { { /*src2 */ { BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1863 | { /*src1 */ { BS3_FP64_ONE(0), BS3_FP64_ONE(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1864 | { /* => */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1865 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1866 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1867 | /*flags */ 0, 0 },
|
|---|
| 1868 | { { /*src2 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_ONE(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1869 | { /*src1 */ { BS3_FP64_ONE(0), BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1870 | { /* => */ { BS3_FP64_VAL(0, 0, BS3_FP64_EXP_SAFE_INT_MAX + 1), BS3_FP64_VAL(1, 0, BS3_FP64_EXP_SAFE_INT_MAX + 1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1871 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1872 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1873 | /*flags */ 0, 0 },
|
|---|
| 1874 | { { /*src2 */ { BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_NORMAL_SAFE_INT_MIN(0) } },
|
|---|
| 1875 | { /*src1 */ { BS3_FP64_NORMAL_SAFE_INT_MIN(1), BS3_FP64_NORMAL_SAFE_INT_MIN(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(0) } },
|
|---|
| 1876 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(1), BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_VAL(0, 0, 2) } },
|
|---|
| 1877 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1878 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1879 | /*flags */ 0, 0 },
|
|---|
| 1880 | { { /*src2 */ { BS3_FP64_VAL(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(1) } },
|
|---|
| 1881 | { /*src1 */ { BS3_FP64_VAL(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(1) } },
|
|---|
| 1882 | { /* => */ { BS3_FP64_VAL(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_VAL(1, 0, 2) } },
|
|---|
| 1883 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1884 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 1885 | /*flags */ 0, 0 },
|
|---|
| 1886 | /*
|
|---|
| 1887 | * Denormals.
|
|---|
| 1888 | */
|
|---|
| 1889 | /*24*/{ { /*src2 */ { BS3_FP64_DENORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1890 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1891 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1892 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1893 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1894 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 1895 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1896 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_DENORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1897 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1898 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1899 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1900 | /*flags */ 0, 0 },
|
|---|
| 1901 | { { /*src2 */ { BS3_FP64_DENORMAL_MIN(0), BS3_FP64_DENORMAL_MIN(0), BS3_FP64_DENORMAL_MAX(0), BS3_FP64_DENORMAL_MAX(0) } },
|
|---|
| 1902 | { /*src1 */ { BS3_FP64_DENORMAL_MAX(0), BS3_FP64_DENORMAL_MIN(0), BS3_FP64_DENORMAL_MAX(0), BS3_FP64_DENORMAL_MIN(0) } },
|
|---|
| 1903 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 1904 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1905 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1906 | /*flags */ 0, 0 },
|
|---|
| 1907 | /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 1908 | };
|
|---|
| 1909 |
|
|---|
| 1910 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 1911 | {
|
|---|
| 1912 | { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1913 | { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1914 |
|
|---|
| 1915 | { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1916 | { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1917 |
|
|---|
| 1918 | { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1919 | { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1920 | };
|
|---|
| 1921 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 1922 | {
|
|---|
| 1923 | { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1924 | { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1925 |
|
|---|
| 1926 | { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1927 | { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1928 |
|
|---|
| 1929 | { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1930 | { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1931 | };
|
|---|
| 1932 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 1933 | {
|
|---|
| 1934 | { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1935 | { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1936 |
|
|---|
| 1937 | { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1938 | { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1939 |
|
|---|
| 1940 | { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1941 | { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1942 |
|
|---|
| 1943 | { bs3CpuInstr4_addpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1944 | { bs3CpuInstr4_addpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1945 |
|
|---|
| 1946 | { bs3CpuInstr4_vaddpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1947 | { bs3CpuInstr4_vaddpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 1948 | };
|
|---|
| 1949 |
|
|---|
| 1950 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 1951 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 1952 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 1953 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 1954 | }
|
|---|
| 1955 |
|
|---|
| 1956 | /*
|
|---|
| 1957 | * [V]ADDSS.
|
|---|
| 1958 | */
|
|---|
| 1959 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addss(uint8_t bMode)
|
|---|
| 1960 | {
|
|---|
| 1961 | static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
|
|---|
| 1962 | {
|
|---|
| 1963 | /*
|
|---|
| 1964 | * Zero.
|
|---|
| 1965 | */
|
|---|
| 1966 | /* 0*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1967 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1968 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 1969 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 1970 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1971 | /*flags */ 0, 0 },
|
|---|
| 1972 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(0), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1973 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 1974 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 1975 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1976 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 1977 | /*flags */ 0, 0 },
|
|---|
| 1978 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(0), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1979 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 1980 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 1981 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1982 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 1983 | /*flags */ 0, 0 },
|
|---|
| 1984 | { { /*src2 */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 1985 | { /*src1 */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1986 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1987 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1988 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 1989 | /*flags */ 0, 0 },
|
|---|
| 1990 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 1991 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1992 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1993 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 1994 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 1995 | /*flags */ 0, 0 },
|
|---|
| 1996 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 1997 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 1998 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 1999 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2000 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2001 | /*flags */ 0, 0 },
|
|---|
| 2002 | /*
|
|---|
| 2003 | * Infinity.
|
|---|
| 2004 | */
|
|---|
| 2005 | /* 6*/{ { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2006 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2007 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2008 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 2009 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2010 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2011 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_7(0), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2012 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2013 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2014 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 2015 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2016 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2017 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2018 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2019 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2020 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2021 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2022 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2023 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2024 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2025 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2026 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2027 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2028 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2029 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 2030 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2031 | { /* => */ { BS3_FP32_QNAN(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2032 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2033 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2034 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2035 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2036 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2037 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2038 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2039 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2040 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2041 | /*
|
|---|
| 2042 | * Overflow, Precision.
|
|---|
| 2043 | */
|
|---|
| 2044 | /*12*/{ { /*src2 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2045 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2046 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2047 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2048 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2049 | /*flags */ X86_MXCSR_OE, X86_MXCSR_OE },
|
|---|
| 2050 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2051 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2052 | { /* => */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2053 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2054 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2055 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2056 | { { /*src2 */ { BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 2057 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2058 | { /* => */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2059 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2060 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2061 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2062 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2063 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2064 | { /* => */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2065 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2066 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2067 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2068 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1) } },
|
|---|
| 2069 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2070 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2071 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2072 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2073 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2074 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2075 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2076 | { /* => */ { BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2077 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2078 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2079 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2080 | /*
|
|---|
| 2081 | * Normals.
|
|---|
| 2082 | */
|
|---|
| 2083 | /*18*/{ { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7f)/* 1.75*/, BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2084 | { /*src1 */ { BS3_FP32_VAL(1, 0, 0x7d)/*-0.25*/, BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2085 | { /* => */ { BS3_FP32_VAL(0, 0x400000, 0x7f)/* 1.50*/, BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 2086 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2087 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2088 | /*flags */ 0, 0 },
|
|---|
| 2089 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1) } },
|
|---|
| 2090 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2091 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2092 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2093 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2094 | /*flags */ 0, 0 },
|
|---|
| 2095 | { { /*src2 */ { BS3_FP32_VAL(0, 0x5ca5b8, 0x93)/*1807543*/, BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2096 | { /*src1 */ { BS3_FP32_VAL(0, 0x1ea980, 0x8f)/* 81235*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2097 | { /* => */ { BS3_FP32_VAL(0, 0x669050, 0x93)/*1888778*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2098 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2099 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2100 | /*flags */ 0, 0 },
|
|---|
| 2101 | { { /*src2 */ { BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 2102 | { /*src1 */ { BS3_FP32_VAL(0, 0x7c9000, 0x88)/* 1010.25*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2103 | { /* => */ { BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357.00*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 2104 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2105 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2106 | /*flags */ 0, 0 },
|
|---|
| 2107 | { { /*src2 */ { BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 2108 | { /*src1 */ { BS3_FP32_VAL(1, 0x712060, 0x92)/*- 987654*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2109 | { /* => */ { BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2110 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2111 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2112 | /*flags */ 0, 0 },
|
|---|
| 2113 | { { /*src2 */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 2114 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2115 | { /* => */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2116 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2117 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2118 | /*flags */ 0, 0 },
|
|---|
| 2119 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 2120 | { /*src1 */ { BS3_FP32_ONE(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2121 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2122 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2123 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2124 | /*flags */ 0, 0 },
|
|---|
| 2125 | { { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/, BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 2126 | { /*src1 */ { BS3_FP32_VAL(0, 0x769b50, 0x92)/*1010101.000*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2127 | { /* => */ { BS3_FP32_VAL(0, 0x769b5e, 0x92)/*1010101.875*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 2128 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2129 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2130 | /*flags */ 0, 0 },
|
|---|
| 2131 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2132 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 2133 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 2134 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2135 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2136 | /*flags */ 0, 0 },
|
|---|
| 2137 | /*
|
|---|
| 2138 | * Denormals.
|
|---|
| 2139 | */
|
|---|
| 2140 | /*27*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(0) } },
|
|---|
| 2141 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_0(0) } },
|
|---|
| 2142 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_0(0) } },
|
|---|
| 2143 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2144 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2145 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 2146 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2147 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 2148 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 2149 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2150 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2151 | /*flags */ 0, 0 },
|
|---|
| 2152 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_7(0) } },
|
|---|
| 2153 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2154 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 2155 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2156 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2157 | /*flags */ 0, 0 },
|
|---|
| 2158 | /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 2159 | };
|
|---|
| 2160 |
|
|---|
| 2161 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 2162 | {
|
|---|
| 2163 | { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2164 | { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2165 |
|
|---|
| 2166 | { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2167 | { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2168 | };
|
|---|
| 2169 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 2170 | {
|
|---|
| 2171 | { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2172 | { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2173 |
|
|---|
| 2174 | { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2175 | { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2176 | };
|
|---|
| 2177 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 2178 | {
|
|---|
| 2179 | { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2180 | { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2181 |
|
|---|
| 2182 | { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2183 | { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2184 |
|
|---|
| 2185 | { bs3CpuInstr4_addss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2186 | { bs3CpuInstr4_addss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2187 | };
|
|---|
| 2188 |
|
|---|
| 2189 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 2190 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 2191 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 2192 | g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
|
|---|
| 2193 | }
|
|---|
| 2194 |
|
|---|
| 2195 |
|
|---|
| 2196 | /*
|
|---|
| 2197 | * [V]HADDPS.
|
|---|
| 2198 | */
|
|---|
| 2199 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddps(uint8_t bMode)
|
|---|
| 2200 | {
|
|---|
| 2201 | static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
|
|---|
| 2202 | {
|
|---|
| 2203 | /*
|
|---|
| 2204 | * Zero.
|
|---|
| 2205 | */
|
|---|
| 2206 | /* 0*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2207 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2208 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2209 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2210 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2211 | /*flags */ 0, 0 },
|
|---|
| 2212 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2213 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2214 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2215 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2216 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2217 | /*flags */ 0, 0 },
|
|---|
| 2218 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2219 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2220 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2221 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2222 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2223 | /*flags */ 0, 0 },
|
|---|
| 2224 | { { /*src2 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2225 | { /*src1 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2226 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2227 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2228 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2229 | /*flags */ 0, 0 },
|
|---|
| 2230 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 2231 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 2232 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2233 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2234 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2235 | /*flags */ 0, 0 },
|
|---|
| 2236 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2237 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2238 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 2239 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2240 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2241 | /*flags */ 0, 0 },
|
|---|
| 2242 | /*
|
|---|
| 2243 | * Infinity.
|
|---|
| 2244 | */
|
|---|
| 2245 | /* 6*/{ { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_INF(1) } },
|
|---|
| 2246 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2247 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1) } },
|
|---|
| 2248 | /*mask */ X86_MXCSR_IM,
|
|---|
| 2249 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2250 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2251 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2252 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_INF(0) } },
|
|---|
| 2253 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2254 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2255 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2256 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 2257 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2258 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_INF(0) } },
|
|---|
| 2259 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2260 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2261 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2262 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2263 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2264 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2265 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(0) } },
|
|---|
| 2266 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2267 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2268 | /*flags */ 0, 0 },
|
|---|
| 2269 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_QNAN(1), BS3_FP32_INF(1), BS3_FP32_QNAN(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2270 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_QNAN(0), BS3_FP32_INF(1), BS3_FP32_QNAN(0), BS3_FP32_INF(1), BS3_FP32_QNAN(1), BS3_FP32_INF(0), BS3_FP32_INF(0) } },
|
|---|
| 2271 | { /* => */ { BS3_FP32_QNAN(0), BS3_FP32_QNAN(0), BS3_FP32_QNAN(1), BS3_FP32_QNAN(0), BS3_FP32_QNAN(1), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2272 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2273 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2274 | /*flags */ 0, 0 },
|
|---|
| 2275 | /*
|
|---|
| 2276 | * Overflow, Precision.
|
|---|
| 2277 | */
|
|---|
| 2278 | /*11*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2279 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1) } },
|
|---|
| 2280 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), } },
|
|---|
| 2281 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2282 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2283 | /*flags */ 0, X86_MXCSR_OE },
|
|---|
| 2284 | { { /*src2 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2285 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2286 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MIN, BS3_FP32_EXP_NORMAL_MIN + 1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2287 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2288 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2289 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2290 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2291 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2292 | { /* => */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2293 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2294 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2295 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2296 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2297 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MAX(1) } },
|
|---|
| 2298 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_VAL(1, 0, 2), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_INF(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2299 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2300 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2301 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2302 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2303 | { /*src1 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1) } },
|
|---|
| 2304 | { /* => */ { BS3_FP32_VAL(1, 0, 2), BS3_FP32_VAL(0, 0, 2), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_VAL(1, 0, 2), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2305 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2306 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2307 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2308 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2309 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1) } },
|
|---|
| 2310 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2311 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2312 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2313 | /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2314 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2315 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2316 | { /* => */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2317 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2318 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2319 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2320 | /*
|
|---|
| 2321 | * Normals.
|
|---|
| 2322 | */
|
|---|
| 2323 | /*18*/{ { /*src2 */ { BS3_FP32_VAL(0, 0, 0x7d)/* 0.25*/, BS3_FP32_VAL(0, 0, 0x7e)/*0.50*/, BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_VAL(0, 0x400000, 0x7f)/*1.50*/, BS3_FP32_VAL(0, 0, 0x7d)/*0.25*/ } },
|
|---|
| 2324 | { /*src1 */ { BS3_FP32_VAL(1, 0, 0x7d)/*-0.25*/, BS3_FP32_VAL(0, 0x600000, 0x7f)/*1.75*/, BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7e)/*0.50*/, BS3_FP32_VAL(0, 0, 0x7d)/*0.25*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2325 | { /* => */ { BS3_FP32_VAL(0, 0x400000, 0x7f)/* 1.50*/, BS3_FP32_NORMAL_MAX(1), BS3_FP32_VAL(0, 0x400000, 0x7e)/*0.75*/, BS3_FP32_NORMAL_MAX(0), BS3_FP32_VAL(0, 0x400000, 0x7e)/*0.75*/, BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_VAL(0, 0x600000, 0x7f)/*1.75*/ } },
|
|---|
| 2326 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2327 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2328 | /*flags */ 0, 0 },
|
|---|
| 2329 | { { /*src2 */ { BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_NORMAL_VAL_4(1), BS3_FP32_NORMAL_VAL_4(0), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_NORMAL_VAL_2(1), BS3_FP32_NORMAL_VAL_2(0) } },
|
|---|
| 2330 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_VAL_3(0), BS3_FP32_NORMAL_VAL_3(1) } },
|
|---|
| 2331 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2332 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2333 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2334 | /*flags */ 0, 0 },
|
|---|
| 2335 | { { /*src2 */ { BS3_FP32_VAL(0, 0x5c0000, 0x84)/* 55*/, BS3_FP32_VAL(0, 0x600000, 0x81)/* 7.00*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x5c0000, 0x84)/* 55.00*/, BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357*/, BS3_FP32_VAL(1, 0x7c9000, 0x88)/*-1010.25*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x534000, 0x86)/*211.25*/ } },
|
|---|
| 2336 | { /*src1 */ { BS3_FP32_VAL(0, 0x669050, 0x93)/*1888778*/, BS3_FP32_VAL(1, 0x1ea980, 0x8f)/* -81235.00*/, BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357*/, BS3_FP32_VAL(1, 0x7c9000, 0x88)/*-1010.25*/, BS3_FP32_VAL(0, 0x5c0000, 0x84)/* 55*/, BS3_FP32_VAL(0, 0x600000, 0x81)/*7*/, BS3_FP32_VAL(0, 0x534000, 0x86)/*211.25*/, BS3_FP32_ONE(1) } },
|
|---|
| 2337 | { /* => */ { BS3_FP32_VAL(0, 0x5ca5b8, 0x93)/*1807543*/, BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_VAL(0, 0x780000, 0x84)/* 62*/, BS3_FP32_VAL(0, 0x5c0000, 0x84)/* 55.00*/, BS3_FP32_VAL(0, 0x780000, 0x84)/* 62*/, BS3_FP32_VAL(0, 0x524000, 0x86)/*210.25*/, BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_VAL(0, 0x534000, 0x86)/*211.25*/ } },
|
|---|
| 2338 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2339 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2340 | /*flags */ 0, 0 },
|
|---|
| 2341 | { { /*src2 */ { BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_VAL(0, 0x3c614e, 0x97)/*24691356*/, BS3_FP32_VAL(1, 0x3c614e, 0x96)/*-12345678*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(1) } },
|
|---|
| 2342 | { /*src1 */ { BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_VAL(1, 0x712060, 0x92)/* -987654*/, BS3_FP32_NORMAL_VAL_3(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_VAL(1, 0x712060, 0x92)/* -987654*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(0) } },
|
|---|
| 2343 | { /* => */ { BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_NORMAL_VAL_3(1), BS3_FP32_VAL(0, 0x3c614e, 0x97)/*24691356*/, BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_ONE(0), BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ONE(1) } },
|
|---|
| 2344 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2345 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2346 | /*flags */ 0, 0 },
|
|---|
| 2347 | { { /*src2 */ { BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2348 | { /*src1 */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(1), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(1) } },
|
|---|
| 2349 | { /* => */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ZERO(0), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ZERO(0), BS3_FP32_ONE(1) } },
|
|---|
| 2350 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2351 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2352 | /*flags */ 0, 0 },
|
|---|
| 2353 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2354 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ONE(1) } },
|
|---|
| 2355 | { /* => */ { BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ONE(1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ONE(1) } },
|
|---|
| 2356 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2357 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2358 | /*flags */ 0, 0 },
|
|---|
| 2359 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2360 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ONE(1) } },
|
|---|
| 2361 | { /* => */ { BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ONE(1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ONE(1) } },
|
|---|
| 2362 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2363 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2364 | /*flags */ 0, 0 },
|
|---|
| 2365 | { { /*src2 */ { BS3_FP32_VAL(0, 0x6423f2, 0x92)/* 934463.125*/, BS3_FP32_VAL(1, 0x0a19f0, 0x8f)/*-70707.875*/, BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/, BS3_FP32_VAL(0, 0x769b50, 0x92)/*1010101.000*/ } },
|
|---|
| 2366 | { /*src1 */ { BS3_FP32_VAL(0, 0x769b50, 0x92)/*1010101.000*/, BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/, BS3_FP32_VAL(0, 0x430ebc, 0x91)/*399477.875*/, BS3_FP32_VAL(0, 0x3ce348, 0x90)/*193421.125*/, BS3_FP32_VAL(0, 0x16b43a, 0x93)/*1234567.25*/, BS3_FP32_VAL(0, 0x00c6d3, 0x94)/*2109876.75*/, BS3_FP32_VAL(0, 0x792318, 0x91)/*510232.750*/, BS3_FP32_VAL(1, 0x316740, 0x8e)/* -45415.250*/ } },
|
|---|
| 2367 | { /* => */ { BS3_FP32_VAL(0, 0x769b5e, 0x92)/*1010101.875*/, BS3_FP32_VAL(0, 0x10c030, 0x92)/*592899.000*/, BS3_FP32_VAL(0, 0x52e0b4, 0x92)/*863755.250*/, BS3_FP32_VAL(1, 0, 2), BS3_FP32_VAL(0, 0x4c20f0, 0x94)/*3344444.00*/, BS3_FP32_VAL(0, 0x62f630, 0x91)/*464817.50*/, BS3_FP32_VAL(0, 0, 2), BS3_FP32_VAL(0, 0x769b5e, 0x92)/*1010101.875*/ } },
|
|---|
| 2368 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2369 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2370 | /*flags */ 0, 0 },
|
|---|
| 2371 | /*
|
|---|
| 2372 | * Denormals.
|
|---|
| 2373 | */
|
|---|
| 2374 | /*26*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2375 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 2376 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2377 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2378 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2379 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 2380 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2381 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2382 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2383 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2384 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2385 | /*flags */ 0, 0 },
|
|---|
| 2386 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 2387 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0) } },
|
|---|
| 2388 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), } },
|
|---|
| 2389 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2390 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2391 | /*flags */ 0, 0 },
|
|---|
| 2392 | { { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2393 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2394 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2395 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2396 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2397 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 2398 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 2399 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2400 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2401 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2402 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2403 | /*flags */ 0, 0 },
|
|---|
| 2404 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 2405 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0) } },
|
|---|
| 2406 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) , BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2407 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2408 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2409 | /*flags */ 0, 0 },
|
|---|
| 2410 | /** @todo Denormals; Rounding, FZ etc. */
|
|---|
| 2411 | };
|
|---|
| 2412 |
|
|---|
| 2413 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 2414 | {
|
|---|
| 2415 | { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2416 | { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2417 |
|
|---|
| 2418 | { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2419 | { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2420 |
|
|---|
| 2421 | { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2422 | { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2423 | };
|
|---|
| 2424 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 2425 | {
|
|---|
| 2426 | { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2427 | { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2428 |
|
|---|
| 2429 | { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2430 | { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2431 |
|
|---|
| 2432 | { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2433 | { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2434 | };
|
|---|
| 2435 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 2436 | {
|
|---|
| 2437 | { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2438 | { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2439 |
|
|---|
| 2440 | { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2441 | { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2442 |
|
|---|
| 2443 | { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2444 | { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2445 |
|
|---|
| 2446 | { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2447 | { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2448 |
|
|---|
| 2449 | { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2450 | { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2451 | };
|
|---|
| 2452 |
|
|---|
| 2453 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 2454 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 2455 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 2456 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 2457 | }
|
|---|
| 2458 |
|
|---|
| 2459 |
|
|---|
| 2460 | /*
|
|---|
| 2461 | * [V]SUBPS.
|
|---|
| 2462 | */
|
|---|
| 2463 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subps(uint8_t bMode)
|
|---|
| 2464 | {
|
|---|
| 2465 | static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
|
|---|
| 2466 | {
|
|---|
| 2467 | /*
|
|---|
| 2468 | * Zero.
|
|---|
| 2469 | */
|
|---|
| 2470 | /* 0*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2471 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2472 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2473 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2474 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2475 | /*flags */ 0, 0 },
|
|---|
| 2476 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2477 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2478 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2479 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2480 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2481 | /*flags */ 0, 0 },
|
|---|
| 2482 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2483 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2484 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2485 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2486 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2487 | /*flags */ 0, 0 },
|
|---|
| 2488 | { { /*src2 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2489 | { /*src1 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2490 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2491 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2492 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2493 | /*flags */ 0, 0 },
|
|---|
| 2494 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 2495 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 2496 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2497 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2498 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2499 | /*flags */ 0, 0 },
|
|---|
| 2500 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2501 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 2502 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 2503 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2504 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2505 | /*flags */ 0, 0 },
|
|---|
| 2506 | /*
|
|---|
| 2507 | * Infinity.
|
|---|
| 2508 | */
|
|---|
| 2509 | /* 6*/{ { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 2510 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 2511 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 2512 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 2513 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2514 | /*flags */ 0, 0 },
|
|---|
| 2515 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 2516 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 2517 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1) } },
|
|---|
| 2518 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2519 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2520 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2521 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 2522 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 2523 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1) } },
|
|---|
| 2524 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2525 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2526 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2527 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2528 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2529 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2530 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2531 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2532 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 2533 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 2534 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 2535 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1) } },
|
|---|
| 2536 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2537 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2538 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 2539 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(0) } },
|
|---|
| 2540 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_INF(1) } },
|
|---|
| 2541 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_ZERO(0), BS3_FP32_QNAN(1), BS3_FP32_QNAN(1), BS3_FP32_INF(1) } },
|
|---|
| 2542 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2543 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2544 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2545 | /*
|
|---|
| 2546 | * Overflow, Precision.
|
|---|
| 2547 | */
|
|---|
| 2548 | /*12*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2549 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2550 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2551 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2552 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2553 | /*flags */ 0, X86_MXCSR_PE },
|
|---|
| 2554 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2555 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2556 | { /* => */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2557 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2558 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2559 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2560 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2561 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1) } },
|
|---|
| 2562 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 2563 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2564 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2565 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2566 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(1, 0, 2), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2567 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 2568 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2569 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2570 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2571 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2572 | { { /*src2 */ { BS3_FP32_VAL(1, 0, 2), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_VAL(1, 0, 2) } },
|
|---|
| 2573 | { /*src1 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(1) } },
|
|---|
| 2574 | { /* => */ { BS3_FP32_NORMAL_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2575 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2576 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2577 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2578 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2579 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2580 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2581 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2582 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2583 | /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2584 | { { /*src2 */ { BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2585 | { /*src1 */ { BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 2586 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2587 | /*mask */ ~(X86_MXCSR_OM | X86_MXCSR_PM),
|
|---|
| 2588 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2589 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2590 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2591 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2592 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2593 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2594 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2595 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2596 | /*
|
|---|
| 2597 | * Normals.
|
|---|
| 2598 | */
|
|---|
| 2599 | /*20*/{ { /*src2 */ { BS3_FP32_VAL(0, 0, 0x7d)/*0.25*/, BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(1, 0, 0x7e)/*-0.50*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_VAL(0, 0x400000, 0x7e)/* 0.75*/ } },
|
|---|
| 2600 | { /*src1 */ { BS3_FP32_VAL(0, 0x600000, 0x7f)/*1.75*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(1, 0x400000, 0x7e)/*-0.75*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_VAL(0, 0, 0x7e)/* 0.50*/ } },
|
|---|
| 2601 | { /* => */ { BS3_FP32_VAL(0, 0x400000, 0x7f)/*1.50*/, BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_VAL(1, 0, 0x7d)/*-0.25*/, BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_VAL(1, 0, 0x7d)/*-0.25*/ } },
|
|---|
| 2602 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2603 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2604 | /*flags */ 0, 0 },
|
|---|
| 2605 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2606 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2607 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2608 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2609 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2610 | /*flags */ 0, 0 },
|
|---|
| 2611 | { { /*src2 */ { BS3_FP32_VAL(0, 0x5ca5b8, 0x93)/*1807543*/, BS3_FP32_VAL(0, 0x600000, 0x81)/* 7*/, BS3_FP32_VAL(0, 0x7c9000, 0x88)/* 1010.25*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x5c0000, 0x84)/* 55*/, BS3_FP32_VAL(0, 0x2514d6, 0x93)/* 1352346.75*/, BS3_FP32_VAL(0, 0x534000, 0x86)/*211.25*/, BS3_FP32_ZERO(0) } },
|
|---|
| 2612 | { /*src1 */ { BS3_FP32_VAL(0, 0x669050, 0x93)/*1888778*/, BS3_FP32_VAL(0, 0x780000, 0x84)/*62*/, BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357.00*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(1, 0x600000, 0x81)/* -7*/, BS3_FP32_VAL(1, 0x7c9000, 0x88)/* -1010.25*/, BS3_FP32_ONE(0) /* 1.00*/, BS3_FP32_ZERO(0) } },
|
|---|
| 2613 | { /* => */ { BS3_FP32_VAL(0, 0x1ea980, 0x8f)/* 81235*/, BS3_FP32_VAL(0, 0x5c0000, 0x84)/*55*/, BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_ZERO(0), BS3_FP32_VAL(1, 0x780000, 0x84)/*-62*/, BS3_FP32_VAL(1, 0x253468, 0x93)/*-1353357.00*/, BS3_FP32_VAL(1, 0x524000, 0x86)/*210.25*/, BS3_FP32_ZERO(0) } },
|
|---|
| 2614 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2615 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2616 | /*flags */ 0, 0 },
|
|---|
| 2617 | { { /*src2 */ { BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_VAL(1, 0x3c614e, 0x96)/*-12345678*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0x712060, 0x92)/* 987654*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2618 | { /*src1 */ { BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/* 12345678*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_VAL(0, 0x3c614e, 0x97)/*24691356*/, BS3_FP32_ONE(0), BS3_FP32_ONE(0) } },
|
|---|
| 2619 | { /* => */ { BS3_FP32_VAL(0, 0x712060, 0x92)/* 987654*/, BS3_FP32_VAL(0, 0x3c614e, 0x97)/* 24691356*/, BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_VAL(0, 0x3c614e, 0x96)/*12345678*/, BS3_FP32_ONE(0), BS3_FP32_ONE(0) } },
|
|---|
| 2620 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2621 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2622 | /*flags */ 0, 0 },
|
|---|
| 2623 | { { /*src2 */ { BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2624 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ONE(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 2625 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2626 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2627 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2628 | /*flags */ 0, 0 },
|
|---|
| 2629 | { { /*src2 */ { BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ZERO(1), BS3_FP32_ONE(1), BS3_FP32_ZERO(1), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0) } },
|
|---|
| 2630 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1) } },
|
|---|
| 2631 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_VAL(1, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_VAL(0, 0, BS3_FP32_EXP_SAFE_INT_MAX + 1), BS3_FP32_ONE(0) } },
|
|---|
| 2632 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2633 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2634 | /*flags */ 0, 0 },
|
|---|
| 2635 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1) } },
|
|---|
| 2636 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 2), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1) } },
|
|---|
| 2637 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2638 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2639 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2640 | /*flags */ 0, 0 },
|
|---|
| 2641 | { { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/, BS3_FP32_VAL(0, 0x3ce348, 0x90)/*193421.125*/, BS3_FP32_VAL(1, 0x0a19f0, 0x8f)/*-70707.875*/, BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0x00c6d3, 0x94)/*2109876.75*/, BS3_FP32_VAL(0, 0x316740, 0x8e)/* 45415.25*/, BS3_FP32_VAL(0, 0x600000, 0x7e)/* 0.875*/ } },
|
|---|
| 2642 | { /*src1 */ { BS3_FP32_VAL(0, 0x769b5e, 0x92)/*1010101.875*/, BS3_FP32_VAL(0, 0x10c030, 0x92)/*592899.000*/, BS3_FP32_VAL(0, 0x52e0b4, 0x92)/*863755.250*/, BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_VAL(0, 0x4c20f0, 0x94)/*3344444.00*/, BS3_FP32_VAL(0, 0x792318, 0x91)/*510232.75*/, BS3_FP32_VAL(1, 0x769b50, 0x92)/*-1010101.000*/ } },
|
|---|
| 2643 | { /* => */ { BS3_FP32_VAL(0, 0x769b50, 0x92)/*1010101.000*/, BS3_FP32_VAL(0, 0x430ebc, 0x91)/*399477.875*/, BS3_FP32_VAL(0, 0x6423f2, 0x92)/*934463.125*/, BS3_FP32_VAL(0, 0, 2), BS3_FP32_VAL(1, 0, 2), BS3_FP32_VAL(0, 0x16b43a, 0x93)/*1234567.25*/, BS3_FP32_VAL(0, 0x62f630, 0x91)/*464817.50*/, BS3_FP32_VAL(1, 0x769b5e, 0x92)/*-1010101.875*/ } },
|
|---|
| 2644 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2645 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2646 | /*flags */ 0, 0 },
|
|---|
| 2647 | /*28*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2648 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 2649 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 2650 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2651 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2652 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 2653 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2654 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2655 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2656 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2657 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2658 | /*flags */ 0, 0 },
|
|---|
| 2659 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 2660 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0) } },
|
|---|
| 2661 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), } },
|
|---|
| 2662 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2663 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2664 | /*flags */ 0, 0 },
|
|---|
| 2665 | /*
|
|---|
| 2666 | * Denormals.
|
|---|
| 2667 | */
|
|---|
| 2668 | /*31*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2669 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2670 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2671 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2672 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2673 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 2674 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(1) } },
|
|---|
| 2675 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2676 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2677 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2678 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2679 | /*flags */ 0, 0 },
|
|---|
| 2680 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(1), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 2681 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(1), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(1), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_DENORMAL_MIN(0) } },
|
|---|
| 2682 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) , BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 2683 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2684 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2685 | /*flags */ 0, 0 },
|
|---|
| 2686 | /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 2687 | };
|
|---|
| 2688 |
|
|---|
| 2689 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 2690 | {
|
|---|
| 2691 | { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2692 | { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2693 |
|
|---|
| 2694 | { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2695 | { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2696 |
|
|---|
| 2697 | { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2698 | { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2699 | };
|
|---|
| 2700 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 2701 | {
|
|---|
| 2702 | { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2703 | { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2704 |
|
|---|
| 2705 | { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2706 | { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2707 |
|
|---|
| 2708 | { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2709 | { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2710 | };
|
|---|
| 2711 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 2712 | {
|
|---|
| 2713 | { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2714 | { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2715 |
|
|---|
| 2716 | { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2717 | { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2718 |
|
|---|
| 2719 | { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2720 | { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2721 |
|
|---|
| 2722 | { bs3CpuInstr4_subps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2723 | { bs3CpuInstr4_subps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2724 |
|
|---|
| 2725 | { bs3CpuInstr4_vsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2726 | { bs3CpuInstr4_vsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2727 | };
|
|---|
| 2728 |
|
|---|
| 2729 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 2730 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 2731 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 2732 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 2733 | }
|
|---|
| 2734 |
|
|---|
| 2735 |
|
|---|
| 2736 | /*
|
|---|
| 2737 | * [V]SUBPD.
|
|---|
| 2738 | */
|
|---|
| 2739 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subpd(uint8_t bMode)
|
|---|
| 2740 | {
|
|---|
| 2741 | static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
|
|---|
| 2742 | {
|
|---|
| 2743 | /*
|
|---|
| 2744 | * Zero.
|
|---|
| 2745 | */
|
|---|
| 2746 | /* 0*/{ { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2747 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2748 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2749 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2750 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2751 | /*flags */ 0, 0 },
|
|---|
| 2752 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2753 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2754 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2755 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2756 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2757 | /*flags */ 0, 0 },
|
|---|
| 2758 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2759 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2760 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2761 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2762 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2763 | /*flags */ 0, 0 },
|
|---|
| 2764 | { { /*src2 */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2765 | { /*src1 */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2766 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2767 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2768 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2769 | /*flags */ 0, 0 },
|
|---|
| 2770 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 2771 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 2772 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2773 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2774 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2775 | /*flags */ 0, 0 },
|
|---|
| 2776 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2777 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2778 | { /* => */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 2779 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2780 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2781 | /*flags */ 0, 0 },
|
|---|
| 2782 | /*
|
|---|
| 2783 | * Infinity.
|
|---|
| 2784 | */
|
|---|
| 2785 | /* 6*/{ { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(1) } },
|
|---|
| 2786 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 2787 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 2788 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 2789 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2790 | /*flags */ 0, 0 },
|
|---|
| 2791 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(1), BS3_FP64_INF(1) } },
|
|---|
| 2792 | { /*src1 */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_INF(1) } },
|
|---|
| 2793 | { /* => */ { BS3_FP64_QNAN(1), BS3_FP64_QNAN(1), BS3_FP64_INF(0), BS3_FP64_QNAN(1) } },
|
|---|
| 2794 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2795 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2796 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2797 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(1) } },
|
|---|
| 2798 | { /*src1 */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_INF(1) } },
|
|---|
| 2799 | { /* => */ { BS3_FP64_QNAN(1), BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_QNAN(1) } },
|
|---|
| 2800 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2801 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2802 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2803 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(1), BS3_FP64_INF(1) } },
|
|---|
| 2804 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_INF(1) } },
|
|---|
| 2805 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_QNAN(1) } },
|
|---|
| 2806 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2807 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2808 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 2809 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 2810 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 2811 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_QNAN(1) } },
|
|---|
| 2812 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2813 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2814 | /*flags */ 0, X86_MXCSR_IE },
|
|---|
| 2815 | { { /*src2 */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(0) } },
|
|---|
| 2816 | { /*src1 */ { BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(1) } },
|
|---|
| 2817 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1) } },
|
|---|
| 2818 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2819 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2820 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 2821 | /*
|
|---|
| 2822 | * Overflow, Precision.
|
|---|
| 2823 | */
|
|---|
| 2824 | /*12*/{ { /*src2 */ { BS3_FP64_NORMAL_MIN(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(0) } },
|
|---|
| 2825 | { /*src1 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 2826 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2827 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2828 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2829 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2830 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(0) } },
|
|---|
| 2831 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 2832 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2833 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2834 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2835 | /*flags */ 0, X86_MXCSR_PE },
|
|---|
| 2836 | { { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 2837 | { /*src1 */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 2838 | { /* => */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2839 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2840 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2841 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2842 | { { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 2843 | { /*src1 */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 2844 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(1) } },
|
|---|
| 2845 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2846 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2847 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2848 | { { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_VAL(1, 0, 2), BS3_FP64_NORMAL_MIN(1) } },
|
|---|
| 2849 | { /*src1 */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(1) } },
|
|---|
| 2850 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_ZERO(0), } },
|
|---|
| 2851 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2852 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 2853 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2854 | { { /*src2 */ { BS3_FP64_VAL(1, 0, 2), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_VAL(1, 0, 2) } },
|
|---|
| 2855 | { /*src1 */ { BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MIN(1) } },
|
|---|
| 2856 | { /* => */ { BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MIN(0) } },
|
|---|
| 2857 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 2858 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2859 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2860 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 2861 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 2862 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1) } },
|
|---|
| 2863 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2864 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2865 | /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2866 | { { /*src2 */ { BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(0) } },
|
|---|
| 2867 | { /*src1 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0) } },
|
|---|
| 2868 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2869 | /*mask */ ~(X86_MXCSR_OM | X86_MXCSR_PM),
|
|---|
| 2870 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2871 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 2872 | { { /*src2 */ { BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2873 | { /*src1 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 2874 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2875 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2876 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 2877 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 2878 | /*
|
|---|
| 2879 | * Normals.
|
|---|
| 2880 | */
|
|---|
| 2881 | /*21*/{ { /*src2 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_VAL_1(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_VAL_1(0) } },
|
|---|
| 2882 | { /*src1 */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_VAL_1(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_VAL_1(0) } },
|
|---|
| 2883 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 2884 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2885 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2886 | /*flags */ 0, 0 },
|
|---|
| 2887 | { { /*src2 */ { BS3_FP64_VAL(0, 0, 0x409)/*1024*/, BS3_FP64_VAL(0, 0xb800000000000, 0x404)/*55*/, BS3_FP64_VAL(1, 0xc000000000000, 0x401)/* 7*/, BS3_FP64_VAL(0, 0x8000000000000, 0x409)/*1536*/ } },
|
|---|
| 2888 | { /*src1 */ { BS3_FP64_VAL(0, 0x8000000000000, 0x409)/*1536*/, BS3_FP64_VAL(1, 0xc000000000000, 0x401)/* 7*/, BS3_FP64_VAL(0, 0xb800000000000, 0x404)/*55*/, BS3_FP64_VAL(0, 0, 0x409)/*1024*/ } },
|
|---|
| 2889 | { /* => */ { BS3_FP64_VAL(0, 0, 0x408)/* 512*/, BS3_FP64_VAL(1, 0xf000000000000, 0x404)/*62*/, BS3_FP64_VAL(0, 0xf000000000000, 0x404)/*62*/, BS3_FP64_VAL(1, 0, 0x408)/* 512*/ } },
|
|---|
| 2890 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2891 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2892 | /*flags */ 0, 0 },
|
|---|
| 2893 | { { /*src2 */ { BS3_FP64_VAL(0, 0x26580b4800000, 0x41d)/*1234567890*/, BS3_FP64_VAL(0, 0x9000000000000, 0x405)/* 100*/, BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } },
|
|---|
| 2894 | { /*src1 */ { BS3_FP64_VAL(0, 0x26580b4800000, 0x41d)/*1234567890*/, BS3_FP64_VAL(0, 0xd6f3458800000, 0x41c)/*987654321*/, BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
|
|---|
| 2895 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xd6f3426800000, 0x41c)/*987654221*/, BS3_FP64_ZERO(0), BS3_FP64_VAL(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
|
|---|
| 2896 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2897 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2898 | /*flags */ 0, 0 },
|
|---|
| 2899 | { { /*src2 */ { BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2900 | { /*src1 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_ONE(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2901 | { /* => */ { BS3_FP64_ONE(0), BS3_FP64_VAL(1, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2902 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2903 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2904 | /*flags */ 0, 0 },
|
|---|
| 2905 | { { /*src2 */ { BS3_FP64_ONE(0), BS3_FP64_ONE(1), BS3_FP64_ONE(1), BS3_FP64_NORMAL_SAFE_INT_MAX(0), } },
|
|---|
| 2906 | { /*src1 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_ONE(0), } },
|
|---|
| 2907 | { /* => */ { BS3_FP64_VAL(0, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX), BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_VAL(1, BS3_FP64_FRACTION_NORMAL_MAX - 1, BS3_FP64_EXP_SAFE_INT_MAX) } },
|
|---|
| 2908 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2909 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2910 | /*flags */ 0, 0 },
|
|---|
| 2911 | { { /*src2 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_NORMAL_SAFE_INT_MIN(1) } },
|
|---|
| 2912 | { /*src1 */ { BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MIN(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(0) } },
|
|---|
| 2913 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_NORMAL_SAFE_INT_MIN(1), BS3_FP64_NORMAL_SAFE_INT_MIN(1), BS3_FP64_VAL(0, 0, 2) } },
|
|---|
| 2914 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2915 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 2916 | /*flags */ 0, 0 },
|
|---|
| 2917 | { { /*src2 */ { BS3_FP64_VAL(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_NORMAL_SAFE_INT_MIN(0) } },
|
|---|
| 2918 | { /*src1 */ { BS3_FP64_VAL(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_NORMAL_SAFE_INT_MIN(1) } },
|
|---|
| 2919 | { /* => */ { BS3_FP64_VAL(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_VAL(1, 0, 2) } },
|
|---|
| 2920 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2921 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 2922 | /*flags */ 0, 0 },
|
|---|
| 2923 | /*
|
|---|
| 2924 | * Denormals.
|
|---|
| 2925 | */
|
|---|
| 2926 | /*28*/{ { /*src2 */ { BS3_FP64_DENORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2927 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2928 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2929 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 2930 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2931 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 2932 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2933 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_DENORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2934 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2935 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2936 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 2937 | /*flags */ 0, 0 },
|
|---|
| 2938 | { { /*src2 */ { BS3_FP64_DENORMAL_MIN(0), BS3_FP64_DENORMAL_MIN(0), BS3_FP64_DENORMAL_MAX(0), BS3_FP64_DENORMAL_MAX(0) } },
|
|---|
| 2939 | { /*src1 */ { BS3_FP64_DENORMAL_MAX(0), BS3_FP64_DENORMAL_MIN(0), BS3_FP64_DENORMAL_MAX(0), BS3_FP64_DENORMAL_MIN(0) } },
|
|---|
| 2940 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 2941 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 2942 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 2943 | /*flags */ 0, 0 },
|
|---|
| 2944 | /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 2945 | };
|
|---|
| 2946 |
|
|---|
| 2947 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 2948 | {
|
|---|
| 2949 | { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2950 | { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2951 |
|
|---|
| 2952 | { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2953 | { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2954 |
|
|---|
| 2955 | { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2956 | { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2957 | };
|
|---|
| 2958 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 2959 | {
|
|---|
| 2960 | { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2961 | { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2962 |
|
|---|
| 2963 | { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2964 | { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2965 |
|
|---|
| 2966 | { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2967 | { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2968 | };
|
|---|
| 2969 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 2970 | {
|
|---|
| 2971 | { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2972 | { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2973 |
|
|---|
| 2974 | { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2975 | { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2976 |
|
|---|
| 2977 | { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2978 | { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2979 |
|
|---|
| 2980 | { bs3CpuInstr4_subpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2981 | { bs3CpuInstr4_subpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2982 |
|
|---|
| 2983 | { bs3CpuInstr4_vsubpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2984 | { bs3CpuInstr4_vsubpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 2985 | };
|
|---|
| 2986 |
|
|---|
| 2987 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 2988 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 2989 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 2990 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 2991 | }
|
|---|
| 2992 |
|
|---|
| 2993 |
|
|---|
| 2994 | /*
|
|---|
| 2995 | * [V]SUBSS.
|
|---|
| 2996 | */
|
|---|
| 2997 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subss(uint8_t bMode)
|
|---|
| 2998 | {
|
|---|
| 2999 | static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
|
|---|
| 3000 | {
|
|---|
| 3001 | /*
|
|---|
| 3002 | * Zero.
|
|---|
| 3003 | */
|
|---|
| 3004 | /* 0*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3005 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3006 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3007 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3008 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3009 | /*flags */ 0, 0 },
|
|---|
| 3010 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(0), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3011 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3012 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3013 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3014 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3015 | /*flags */ 0, 0 },
|
|---|
| 3016 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(0), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3017 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3018 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3019 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3020 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 3021 | /*flags */ 0, 0 },
|
|---|
| 3022 | { { /*src2 */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3023 | { /*src1 */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3024 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3025 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3026 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3027 | /*flags */ 0, 0 },
|
|---|
| 3028 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3029 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3030 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3031 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3032 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3033 | /*flags */ 0, 0 },
|
|---|
| 3034 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3035 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3036 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3037 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3038 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3039 | /*flags */ 0, 0 },
|
|---|
| 3040 | /*
|
|---|
| 3041 | * Infinity.
|
|---|
| 3042 | */
|
|---|
| 3043 | /* 6*/{ { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3044 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3045 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3046 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 3047 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3048 | /*flags */ 0, 0 },
|
|---|
| 3049 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_7(0), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3050 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3051 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3052 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 3053 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3054 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 3055 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3056 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3057 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3058 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3059 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3060 | /*flags */ 0, 0 },
|
|---|
| 3061 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3062 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3063 | { /* => */ { BS3_FP32_QNAN(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3064 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3065 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3066 | /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
|
|---|
| 3067 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 3068 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3069 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3070 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3071 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3072 | /*flags */ 0, 0 },
|
|---|
| 3073 | { { /*src2 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3074 | { /*src1 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 3075 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 3076 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3077 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3078 | /*flags */ 0, 0 },
|
|---|
| 3079 | /*
|
|---|
| 3080 | * Overflow, Precision.
|
|---|
| 3081 | */
|
|---|
| 3082 | /*12*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 3083 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3084 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3085 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3086 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3087 | /*flags */ 0, X86_MXCSR_PE },
|
|---|
| 3088 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3089 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3090 | { /* => */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3091 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 3092 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3093 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3094 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3095 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(1) } },
|
|---|
| 3096 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 3097 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 3098 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3099 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3100 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3101 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3102 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3103 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 3104 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3105 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3106 | { { /*src2 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3107 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3108 | { /* => */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3109 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 3110 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3111 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 3112 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3113 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3114 | { /* => */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3115 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3116 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3117 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3118 | { { /*src2 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3119 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3120 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3121 | /*mask */ ~(X86_MXCSR_OM | X86_MXCSR_PM),
|
|---|
| 3122 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3123 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 3124 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3125 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3126 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3127 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3128 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3129 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 3130 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3131 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3132 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3133 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3134 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3135 | /*flags */ X86_MXCSR_PE, X86_MXCSR_PE },
|
|---|
| 3136 | /*
|
|---|
| 3137 | * Normals.
|
|---|
| 3138 | */
|
|---|
| 3139 | /*18*/{ { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7f)/*1.75*/, BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3140 | { /*src1 */ { BS3_FP32_VAL(0, 0, 0x7d)/*0.25*/, BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 3141 | { /* => */ { BS3_FP32_VAL(1, 0x400000, 0x7f)/*1.50*/, BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 3142 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3143 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3144 | /*flags */ 0, 0 },
|
|---|
| 3145 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1) } },
|
|---|
| 3146 | { /*src1 */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3147 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3148 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3149 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3150 | /*flags */ 0, 0 },
|
|---|
| 3151 | { { /*src2 */ { BS3_FP32_VAL(0, 0x5ca5b8, 0x93)/*1807543*/, BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3152 | { /*src1 */ { BS3_FP32_VAL(0, 0x669050, 0x93)/*1888778*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3153 | { /* => */ { BS3_FP32_VAL(0, 0x1ea980, 0x8f)/* 81235*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3154 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3155 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3156 | /*flags */ 0, 0 },
|
|---|
| 3157 | { { /*src2 */ { BS3_FP32_VAL(0, 0x2514d6, 0x93)/*1352346.75*/, BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
|
|---|
| 3158 | { /*src1 */ { BS3_FP32_VAL(0, 0x253468, 0x93)/*1353357.00*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3159 | { /* => */ { BS3_FP32_VAL(0, 0x7c9000, 0x88)/* 1010.25*/, BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
|
|---|
| 3160 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3161 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3162 | /*flags */ 0, 0 },
|
|---|
| 3163 | { { /*src2 */ { BS3_FP32_VAL(0, 0x712060, 0x92)/* 987654*/, BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 3164 | { /*src1 */ { BS3_FP32_VAL(0, 0x74429f, 0x97)/*32015678*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3165 | { /* => */ { BS3_FP32_VAL(0, 0x6cb99c, 0x97)/*31028024*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3166 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3167 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3168 | /*flags */ 0, 0 },
|
|---|
| 3169 | { { /*src2 */ { BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 3170 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3171 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3172 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3173 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3174 | /*flags */ 0, 0 },
|
|---|
| 3175 | { { /*src2 */ { BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 3176 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3177 | { /* => */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3178 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3179 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3180 | /*flags */ 0, 0 },
|
|---|
| 3181 | { { /*src2 */ { BS3_FP32_VAL(1, 0x600000, 0x7e)/* -0.875*/, BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_3(1) } },
|
|---|
| 3182 | { /*src1 */ { BS3_FP32_VAL(0, 0x769b50, 0x92)/* 1010101.000*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3183 | { /* => */ { BS3_FP32_VAL(0, 0x769b5e, 0x92)/* 1010101.875*/, BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_6(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0) } },
|
|---|
| 3184 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3185 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3186 | /*flags */ 0, 0 },
|
|---|
| 3187 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3188 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 3189 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 3190 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3191 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3192 | /*flags */ 0, 0 },
|
|---|
| 3193 | /*
|
|---|
| 3194 | * Denormals.
|
|---|
| 3195 | */
|
|---|
| 3196 | /*27*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(0) } },
|
|---|
| 3197 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_0(0) } },
|
|---|
| 3198 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_0(0) } },
|
|---|
| 3199 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3200 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3201 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 3202 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3203 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 3204 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_7(1) } },
|
|---|
| 3205 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3206 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3207 | /*flags */ 0, 0 },
|
|---|
| 3208 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_7(0) } },
|
|---|
| 3209 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3210 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_1(1), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_6(1) } },
|
|---|
| 3211 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3212 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 3213 | /*flags */ 0, 0 },
|
|---|
| 3214 | /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 3215 | };
|
|---|
| 3216 |
|
|---|
| 3217 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 3218 | {
|
|---|
| 3219 | { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3220 | { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3221 |
|
|---|
| 3222 | { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3223 | { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3224 | };
|
|---|
| 3225 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 3226 | {
|
|---|
| 3227 | { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3228 | { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3229 |
|
|---|
| 3230 | { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3231 | { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3232 | };
|
|---|
| 3233 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 3234 | {
|
|---|
| 3235 | { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3236 | { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3237 |
|
|---|
| 3238 | { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3239 | { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3240 |
|
|---|
| 3241 | { bs3CpuInstr4_subss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3242 | { bs3CpuInstr4_subss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3243 | };
|
|---|
| 3244 |
|
|---|
| 3245 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 3246 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 3247 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 3248 | g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
|
|---|
| 3249 | }
|
|---|
| 3250 |
|
|---|
| 3251 |
|
|---|
| 3252 | /*
|
|---|
| 3253 | * [V]MULPS.
|
|---|
| 3254 | */
|
|---|
| 3255 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulps(uint8_t bMode)
|
|---|
| 3256 | {
|
|---|
| 3257 | static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
|
|---|
| 3258 | {
|
|---|
| 3259 | /*
|
|---|
| 3260 | * Zero.
|
|---|
| 3261 | */
|
|---|
| 3262 | /* 0*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3263 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3264 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3265 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3266 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3267 | /*flags */ 0, 0 },
|
|---|
| 3268 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3269 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3270 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3271 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3272 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3273 | /*flags */ 0, 0 },
|
|---|
| 3274 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3275 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3276 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3277 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3278 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 3279 | /*flags */ 0, 0 },
|
|---|
| 3280 | { { /*src2 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 3281 | { /*src1 */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 3282 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3283 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3284 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3285 | /*flags */ 0, 0 },
|
|---|
| 3286 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 3287 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 3288 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3289 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3290 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3291 | /*flags */ 0, 0 },
|
|---|
| 3292 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 3293 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
|
|---|
| 3294 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 3295 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3296 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3297 | /*flags */ 0, 0 },
|
|---|
| 3298 | { { /*src2 */ { BS3_FP32_NORMAL_VAL_0(0), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_3(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_NORMAL_VAL_4(0), BS3_FP32_NORMAL_VAL_3(0) } },
|
|---|
| 3299 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_2(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 3300 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
|
|---|
| 3301 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3302 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3303 | /*flags */ 0, 0 },
|
|---|
| 3304 | /*
|
|---|
| 3305 | * Infinity.
|
|---|
| 3306 | */
|
|---|
| 3307 | /* 7*/{ { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3308 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3309 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3310 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 3311 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3312 | /*flags */ 0, 0 },
|
|---|
| 3313 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3314 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3315 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3316 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3317 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3318 | /*flags */ 0, 0 },
|
|---|
| 3319 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 3320 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0) } },
|
|---|
| 3321 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3322 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3323 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3324 | /*flags */ 0, 0 },
|
|---|
| 3325 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0) } },
|
|---|
| 3326 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 3327 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(1) } },
|
|---|
| 3328 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3329 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3330 | /*flags */ 0, 0 },
|
|---|
| 3331 | { { /*src2 */ { BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(0) } },
|
|---|
| 3332 | { /*src1 */ { BS3_FP32_INF(1), BS3_FP32_INF(0), BS3_FP32_ZERO(1), BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_INF(1) } },
|
|---|
| 3333 | { /* => */ { BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_INF(1), BS3_FP32_ZERO(1), BS3_FP32_INF(1), BS3_FP32_INF(1), BS3_FP32_INF(1) } },
|
|---|
| 3334 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3335 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3336 | /*flags */ 0, 0 },
|
|---|
| 3337 | /*
|
|---|
| 3338 | * Normals.
|
|---|
| 3339 | */
|
|---|
| 3340 | /*12*/{ { /*src2 */ { BS3_FP32_VAL(0, 0x600000, 0x7f)/*1.7500*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7d)/*0.250*/, BS3_FP32_VAL(0, 0x600000, 0x7f)/* 1.7500*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7d)/*0.250*/ } },
|
|---|
| 3341 | { /*src1 */ { BS3_FP32_VAL(0, 0, 0x7d)/*0.2500*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7e)/*0.500*/, BS3_FP32_VAL(1, 0, 0x7d)/*-0.2500*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7e)/*0.500*/ } },
|
|---|
| 3342 | { /* => */ { BS3_FP32_VAL(0, 0x600000, 0x7d)/*0.4375*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7c)/*0.125*/, BS3_FP32_VAL(1, 0x600000, 0x7d)/*-0.4375*/, BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 0x7c)/*0.125*/ } },
|
|---|
| 3343 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3344 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3345 | /*flags */ 0, 0 },
|
|---|
| 3346 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_NORMAL_VAL_2(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3347 | { /*src1 */ { BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_NORMAL_VAL_3(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_VAL_3(0) } },
|
|---|
| 3348 | { /* => */ { BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_1(1), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_VAL_3(0), BS3_FP32_NORMAL_MIN(0), BS3_FP32_NORMAL_VAL_1(0), BS3_FP32_NORMAL_VAL_2(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3349 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3350 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3351 | /*flags */ 0, 0 },
|
|---|
| 3352 | { { /*src2 */ { BS3_FP32_VAL(0, 0x61e000, 0x89)/* 1807*/, BS3_FP32_VAL(0, 0x4a30b8, 0x8f)/* 103521.4375*/, BS3_FP32_VAL(0, 0x1a5200, 0x8c)/* 9876.5*/, BS3_FP32_VAL(0, 0x0ba000, 0x86)/* 139.625000*/, BS3_FP32_VAL(0, 0x200000, 0x7e)/*0.625000*/, BS3_FP32_VAL(0, 0x22fae4, 0x93)/*1335132.50*/, BS3_FP32_VAL(0, 0x23b6a0, 0x8e)/*41910.625000*/, BS3_FP32_VAL(0, 0x3d400, 0x86)/*131.828125*/ } },
|
|---|
| 3353 | { /*src1 */ { BS3_FP32_VAL(0, 0x504000, 0x8a)/* 3332*/, BS3_FP32_VAL(0, 0x600000, 0x82)/* 14.0000*/, BS3_FP32_VAL(1, 0x1a4000, 0x89)/* -1234.0*/, BS3_FP32_VAL(0, 0x265000, 0x87)/* 332.625000*/, BS3_FP32_VAL(0, 0, 0x7c)/*0.125000*/, BS3_FP32_VAL(0, 0x200000, 0x80)/* 2.50*/, BS3_FP32_VAL(0, 0, 0x7c)/* 0.125000*/, BS3_FP32_ONE(1) /* -1.000000*/ } },
|
|---|
| 3354 | { /* => */ { BS3_FP32_VAL(0, 0x37be78, 0x95)/*6020924*/, BS3_FP32_VAL(0, 0x30eaa1, 0x93)/*1449300.1250*/, BS3_FP32_VAL(1, 0x39f7d1, 0x96)/*-12187601.0*/, BS3_FP32_VAL(0, 0x356ac4, 0x8e)/*46442.765625*/, BS3_FP32_VAL(0, 0x200000, 0x7b)/*0.078125*/, BS3_FP32_VAL(0, 0x4bb99d, 0x94)/*3337831.25*/, BS3_FP32_VAL(0, 0x23b6a0, 0x8b)/* 5238.828125*/, BS3_FP32_VAL(1, 0x3d400, 0x86)/*-131.828125*/ } },
|
|---|
| 3355 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3356 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3357 | /*flags */ 0, 0 },
|
|---|
| 3358 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0) } },
|
|---|
| 3359 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_ONE(0) } },
|
|---|
| 3360 | { /* => */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX - 1, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_ONE(0), BS3_FP32_ONE(0) } },
|
|---|
| 3361 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3362 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3363 | /*flags */ 0, 0 },
|
|---|
| 3364 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ONE(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_VAL(0, 0, 2) } },
|
|---|
| 3365 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_ONE(0) } },
|
|---|
| 3366 | { /* => */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_ZERO(1), BS3_FP32_NORMAL_SAFE_INT_MIN(1), BS3_FP32_ZERO(0), BS3_FP32_VAL(0, 0, 2) } },
|
|---|
| 3367 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3368 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3369 | /*flags */ 0, 0 },
|
|---|
| 3370 | /** @todo More Normals. */
|
|---|
| 3371 | /*
|
|---|
| 3372 | * Denormals.
|
|---|
| 3373 | */
|
|---|
| 3374 | /*17*/{ { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_ONE(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_ONE(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 3375 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_ONE(1), BS3_FP32_ONE(1), } },
|
|---|
| 3376 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(0) } },
|
|---|
| 3377 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3378 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3379 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 3380 | { { /*src2 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_RAND_VAL_5(0), BS3_FP32_ONE(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_ONE(1), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_5(1) } },
|
|---|
| 3381 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_ONE(1), BS3_FP32_ONE(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_ONE(1), BS3_FP32_ONE(1), } },
|
|---|
| 3382 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(0) } },
|
|---|
| 3383 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3384 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3385 | /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
|
|---|
| 3386 | { { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ONE(0) } },
|
|---|
| 3387 | { /*src1 */ { BS3_FP32_DENORMAL_MIN(1), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 3388 | { /* => */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3389 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3390 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3391 | /*flags */ 0, 0 },
|
|---|
| 3392 | { { /*src2 */ { BS3_FP32_DENORMAL_MIN(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_DENORMAL_MAX(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_DENORMAL_MAX(0) } },
|
|---|
| 3393 | { /*src1 */ { BS3_FP32_DENORMAL_MAX(0), BS3_FP32_ONE(0), BS3_FP32_DENORMAL_MIN(1), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_DENORMAL_MIN(0), BS3_FP32_RAND_VAL_4(0) } },
|
|---|
| 3394 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_0(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3395 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3396 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 3397 | /*flags */ 0, 0 },
|
|---|
| 3398 | /** @todo More Denormals. */
|
|---|
| 3399 | /*
|
|---|
| 3400 | * Overflow, Precision.
|
|---|
| 3401 | */
|
|---|
| 3402 | /*21*/{ { /*src2 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_VAL_7(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3403 | { /*src1 */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3404 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_INF(0), BS3_FP32_NORMAL_VAL_7(0), BS3_FP32_INF(0), BS3_FP32_INF(0), } },
|
|---|
| 3405 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3406 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3407 | /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3408 | { { /*src2 */ { BS3_FP32_NORMAL_VAL_5(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3409 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ONE(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_6(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3410 | { /* => */ { BS3_FP32_NORMAL_VAL_5(0), BS3_FP32_INF(0), BS3_FP32_INF(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_6(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3411 | /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
|
|---|
| 3412 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3413 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3414 | { { /*src2 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_VAL_7(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3415 | { /*src1 */ { BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3416 | { /* => */ { BS3_FP32_INF(0), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_INF(0), BS3_FP32_INF(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_VAL_7(0), BS3_FP32_INF(0) } },
|
|---|
| 3417 | /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
|
|---|
| 3418 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
|
|---|
| 3419 | /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
|
|---|
| 3420 | { { /*src2 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_VAL_5(0), BS3_FP32_ONE(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 3421 | { /*src1 */ { BS3_FP32_NORMAL_MIN(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ONE(0), BS3_FP32_ONE(1), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MIN(0) } },
|
|---|
| 3422 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_VAL_5(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0) } },
|
|---|
| 3423 | /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
|
|---|
| 3424 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3425 | /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
|
|---|
| 3426 | { { /*src2 */ { BS3_FP32_NORMAL_VAL_6(0), BS3_FP32_ONE(1), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3427 | { /*src1 */ { BS3_FP32_ONE(0), BS3_FP32_NORMAL_VAL_6(1), BS3_FP32_ONE(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(1), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3428 | { /* => */ { BS3_FP32_NORMAL_VAL_6(0), BS3_FP32_NORMAL_VAL_6(0), BS3_FP32_ZERO(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_NORMAL_MAX(0) } },
|
|---|
| 3429 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3430 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3431 | /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3432 | { { /*src2 */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MIN(0), BS3_FP32_NORMAL_MAX(0), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 3433 | { /*src1 */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ONE(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1), BS3_FP32_NORMAL_SAFE_INT_MAX(0), BS3_FP32_NORMAL_MAX(1), BS3_FP32_ZERO(0), BS3_FP32_NORMAL_SAFE_INT_MAX(1) } },
|
|---|
| 3434 | { /* => */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
|
|---|
| 3435 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3436 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3437 | /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
|
|---|
| 3438 | /** @todo Underflow, Precision; Rounding, FZ etc. */
|
|---|
| 3439 | };
|
|---|
| 3440 |
|
|---|
| 3441 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 3442 | {
|
|---|
| 3443 | { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3444 | { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3445 |
|
|---|
| 3446 | { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3447 | { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3448 |
|
|---|
| 3449 | { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3450 | { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3451 | };
|
|---|
| 3452 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 3453 | {
|
|---|
| 3454 | { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3455 | { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3456 |
|
|---|
| 3457 | { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3458 | { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3459 |
|
|---|
| 3460 | { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3461 | { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3462 | };
|
|---|
| 3463 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 3464 | {
|
|---|
| 3465 | { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3466 | { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3467 |
|
|---|
| 3468 | { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3469 | { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3470 |
|
|---|
| 3471 | { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3472 | { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3473 |
|
|---|
| 3474 | { bs3CpuInstr4_mulps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3475 | { bs3CpuInstr4_mulps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3476 |
|
|---|
| 3477 | { bs3CpuInstr4_vmulps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3478 | { bs3CpuInstr4_vmulps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3479 | };
|
|---|
| 3480 |
|
|---|
| 3481 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 3482 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 3483 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 3484 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 3485 | }
|
|---|
| 3486 |
|
|---|
| 3487 |
|
|---|
| 3488 | /*
|
|---|
| 3489 | * [V]MULPD.
|
|---|
| 3490 | */
|
|---|
| 3491 | BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulpd(uint8_t bMode)
|
|---|
| 3492 | {
|
|---|
| 3493 | static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
|
|---|
| 3494 | {
|
|---|
| 3495 | /*
|
|---|
| 3496 | * Zero.
|
|---|
| 3497 | */
|
|---|
| 3498 | /* 0*/{ { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 3499 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 3500 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0) } },
|
|---|
| 3501 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3502 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3503 | /*flags */ 0, 0 },
|
|---|
| 3504 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3505 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3506 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3507 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3508 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3509 | /*flags */ 0, 0 },
|
|---|
| 3510 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3511 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3512 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3513 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3514 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 3515 | /*flags */ 0, 0 },
|
|---|
| 3516 | { { /*src2 */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3517 | { /*src1 */ { BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3518 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3519 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3520 | /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
|
|---|
| 3521 | /*flags */ 0, 0 },
|
|---|
| 3522 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), } },
|
|---|
| 3523 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), } },
|
|---|
| 3524 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), } },
|
|---|
| 3525 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3526 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3527 | /*flags */ 0, 0 },
|
|---|
| 3528 | { { /*src2 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), } },
|
|---|
| 3529 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), } },
|
|---|
| 3530 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), } },
|
|---|
| 3531 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3532 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3533 | /*flags */ 0, 0 },
|
|---|
| 3534 | { { /*src2 */ { BS3_FP64_NORMAL_VAL_0(0), BS3_FP64_NORMAL_VAL_1(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_VAL_3(1) } },
|
|---|
| 3535 | { /*src1 */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_VAL_2(1), BS3_FP64_ZERO(1), } },
|
|---|
| 3536 | { /* => */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(1), BS3_FP64_ZERO(1), BS3_FP64_ZERO(0), } },
|
|---|
| 3537 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3538 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
|
|---|
| 3539 | /*flags */ 0, 0 },
|
|---|
| 3540 | /*
|
|---|
| 3541 | * Infinity.
|
|---|
| 3542 | */
|
|---|
| 3543 | /* 7*/{ { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_ZERO(0), BS3_FP64_INF(1), BS3_FP64_ZERO(0) } },
|
|---|
| 3544 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_INF(0), BS3_FP64_ZERO(0) } },
|
|---|
| 3545 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_INF(1), BS3_FP64_ZERO(0) } },
|
|---|
| 3546 | /*mask */ ~X86_MXCSR_IM,
|
|---|
| 3547 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3548 | /*flags */ 0, 0 },
|
|---|
| 3549 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(1) } },
|
|---|
| 3550 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(0) } },
|
|---|
| 3551 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(1) } },
|
|---|
| 3552 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3553 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
|
|---|
| 3554 | /*flags */ 0, 0 },
|
|---|
| 3555 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_ZERO(1), BS3_FP64_INF(0) } },
|
|---|
| 3556 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_ZERO(1), BS3_FP64_INF(0) } },
|
|---|
| 3557 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 3558 | /*mask */ ~X86_MXCSR_XCPT_MASK,
|
|---|
| 3559 | /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3560 | /*flags */ 0, 0 },
|
|---|
| 3561 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_ZERO(1), BS3_FP64_INF(0) } },
|
|---|
| 3562 | { /*src1 */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_ZERO(1), BS3_FP64_INF(0) } },
|
|---|
| 3563 | { /* => */ { BS3_FP64_INF(1), BS3_FP64_INF(1), BS3_FP64_ZERO(0), BS3_FP64_INF(0) } },
|
|---|
| 3564 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3565 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
|
|---|
| 3566 | /*flags */ 0, 0 },
|
|---|
| 3567 | { { /*src2 */ { BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_ONE(0), BS3_FP64_INF(0) } },
|
|---|
| 3568 | { /*src1 */ { BS3_FP64_ONE(0), BS3_FP64_NORMAL_VAL_0(0), BS3_FP64_INF(0), BS3_FP64_NORMAL_VAL_1(0) } },
|
|---|
| 3569 | { /* => */ { BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(0), BS3_FP64_INF(0) } },
|
|---|
| 3570 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3571 | /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_DOWN,
|
|---|
| 3572 | /*flags */ 0, 0 },
|
|---|
| 3573 | { { /*src2 */ { BS3_FP64_INF(1), BS3_FP64_INF(0), BS3_FP64_NORMAL_VAL_3(0), BS3_FP64_INF(1) } },
|
|---|
| 3574 | { /*src1 */ { BS3_FP64_ONE(1), BS3_FP64_NORMAL_VAL_3(1), BS3_FP64_INF(1), BS3_FP64_NORMAL_VAL_1(1) } },
|
|---|
| 3575 | { /* => */ { BS3_FP64_INF(0), BS3_FP64_INF(1), BS3_FP64_INF(1), BS3_FP64_INF(0) } },
|
|---|
| 3576 | /*mask */ X86_MXCSR_XCPT_MASK,
|
|---|
| 3577 | /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
|
|---|
| 3578 | /*flags */ 0, 0 },
|
|---|
| 3579 | };
|
|---|
| 3580 |
|
|---|
| 3581 | static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
|
|---|
| 3582 | {
|
|---|
| 3583 | { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3584 | { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3585 |
|
|---|
| 3586 | { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3587 | { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3588 |
|
|---|
| 3589 | { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3590 | { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3591 | };
|
|---|
| 3592 | static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
|
|---|
| 3593 | {
|
|---|
| 3594 | { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3595 | { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3596 |
|
|---|
| 3597 | { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3598 | { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3599 |
|
|---|
| 3600 | { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3601 | { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3602 | };
|
|---|
| 3603 | static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
|
|---|
| 3604 | {
|
|---|
| 3605 | { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3606 | { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3607 |
|
|---|
| 3608 | { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3609 | { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3610 |
|
|---|
| 3611 | { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3612 | { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3613 |
|
|---|
| 3614 | { bs3CpuInstr4_mulpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3615 | { bs3CpuInstr4_mulpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3616 |
|
|---|
| 3617 | { bs3CpuInstr4_vmulpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3618 | { bs3CpuInstr4_vmulpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
|
|---|
| 3619 | };
|
|---|
| 3620 |
|
|---|
| 3621 | static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
|
|---|
| 3622 | unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
|
|---|
| 3623 | return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
|
|---|
| 3624 | g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
|
|---|
| 3625 | }
|
|---|
| 3626 |
|
|---|
| 3627 |
|
|---|
| 3628 | /**
|
|---|
| 3629 | * The 32-bit protected mode main function.
|
|---|
| 3630 | *
|
|---|
| 3631 | * The tests a driven by 32-bit test drivers, even for real-mode tests (though
|
|---|
| 3632 | * we'll switch between PE32 and RM for each test step we perform). Given that
|
|---|
| 3633 | * we test SSE and AVX here, we don't need to worry about 286 or 8086.
|
|---|
| 3634 | *
|
|---|
| 3635 | * Some extra steps needs to be taken to properly handle extended state in LM64
|
|---|
| 3636 | * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode
|
|---|
| 3637 | * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm).
|
|---|
| 3638 | */
|
|---|
| 3639 | BS3_DECL(void) Main_pe32()
|
|---|
| 3640 | {
|
|---|
| 3641 | static const BS3TESTMODEBYONEENTRY g_aTests[] =
|
|---|
| 3642 | {
|
|---|
| 3643 | #if 1 /*ndef DEBUG_bird*/
|
|---|
| 3644 | # define ALL_TESTS
|
|---|
| 3645 | #endif
|
|---|
| 3646 | #if defined(ALL_TESTS)
|
|---|
| 3647 | { "[v]addps", bs3CpuInstr4_v_addps, 0 },
|
|---|
| 3648 | { "[v]addpd", bs3CpuInstr4_v_addpd, 0 },
|
|---|
| 3649 | { "[v]addss", bs3CpuInstr4_v_addss, 0 },
|
|---|
| 3650 | { "[v]haddps", bs3CpuInstr4_v_haddps, 0 },
|
|---|
| 3651 | { "[v]subps", bs3CpuInstr4_v_subps, 0 },
|
|---|
| 3652 | { "[v]subpd", bs3CpuInstr4_v_subpd, 0 },
|
|---|
| 3653 | { "[v]subss", bs3CpuInstr4_v_subss, 0 },
|
|---|
| 3654 | { "[v]mulps", bs3CpuInstr4_v_mulps, 0 },
|
|---|
| 3655 | { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 },
|
|---|
| 3656 | #endif
|
|---|
| 3657 | };
|
|---|
| 3658 | Bs3TestInit("bs3-cpu-instr-4");
|
|---|
| 3659 |
|
|---|
| 3660 | /*
|
|---|
| 3661 | * Initialize globals.
|
|---|
| 3662 | */
|
|---|
| 3663 | if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
|
|---|
| 3664 | {
|
|---|
| 3665 | uint32_t fEbx, fEcx, fEdx;
|
|---|
| 3666 | ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
|
|---|
| 3667 | g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX);
|
|---|
| 3668 | g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
|
|---|
| 3669 | g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
|
|---|
| 3670 | g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3);
|
|---|
| 3671 | g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
|
|---|
| 3672 | g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
|
|---|
| 3673 | g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3);
|
|---|
| 3674 | g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3);
|
|---|
| 3675 | g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
|
|---|
| 3676 | g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
|
|---|
| 3677 | g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
|
|---|
| 3678 | g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
|
|---|
| 3679 | g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
|
|---|
| 3680 | g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL)
|
|---|
| 3681 | && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
|
|---|
| 3682 |
|
|---|
| 3683 | if (ASMCpuId_EAX(0) >= 7)
|
|---|
| 3684 | {
|
|---|
| 3685 | ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL);
|
|---|
| 3686 | g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
|
|---|
| 3687 | g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
|
|---|
| 3688 | g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA);
|
|---|
| 3689 | }
|
|---|
| 3690 |
|
|---|
| 3691 | if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES)
|
|---|
| 3692 | {
|
|---|
| 3693 | ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
|
|---|
| 3694 | g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
|
|---|
| 3695 | g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A);
|
|---|
| 3696 | g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
|
|---|
| 3697 | }
|
|---|
| 3698 | g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE];
|
|---|
| 3699 |
|
|---|
| 3700 | /*
|
|---|
| 3701 | * Figure out FPU save/restore method and support for DAZ bit.
|
|---|
| 3702 | */
|
|---|
| 3703 | {
|
|---|
| 3704 | /** @todo Add bs3kit API to just get the ext ctx method without needing to
|
|---|
| 3705 | * alloc/free a context. Replicating the logic in the bs3kit here, though
|
|---|
| 3706 | * doable, runs a risk of not updating this when the other logic is
|
|---|
| 3707 | * changed. */
|
|---|
| 3708 | uint64_t fFlags;
|
|---|
| 3709 | uint16_t const cbExtCtx = Bs3ExtCtxGetSize(&fFlags);
|
|---|
| 3710 | PBS3EXTCTX pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cbExtCtx);
|
|---|
| 3711 | if (pExtCtx)
|
|---|
| 3712 | {
|
|---|
| 3713 | Bs3ExtCtxInit(pExtCtx, cbExtCtx, fFlags);
|
|---|
| 3714 | g_enmExtCtxMethod = pExtCtx->enmMethod;
|
|---|
| 3715 | if ( ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_XSAVE
|
|---|
| 3716 | && (pExtCtx->Ctx.x.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
|
|---|
| 3717 | || ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_FXSAVE)
|
|---|
| 3718 | && (pExtCtx->Ctx.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
|
|---|
| 3719 | g_fMxCsrDazSupported = true;
|
|---|
| 3720 | }
|
|---|
| 3721 | else
|
|---|
| 3722 | Bs3TestFailedF("Failed to allocate %u bytes for extended CPU context (tiled addressable)\n", cbExtCtx);
|
|---|
| 3723 | }
|
|---|
| 3724 |
|
|---|
| 3725 | /*
|
|---|
| 3726 | * Allocate a buffer for testing.
|
|---|
| 3727 | */
|
|---|
| 3728 | g_cbBuf = X86_PAGE_SIZE * 4;
|
|---|
| 3729 | g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf);
|
|---|
| 3730 | if (g_pbBuf)
|
|---|
| 3731 | {
|
|---|
| 3732 | g_pbBufAliasAlloc = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_TILED, g_cbBuf);
|
|---|
| 3733 | if (g_pbBufAliasAlloc)
|
|---|
| 3734 | {
|
|---|
| 3735 | /*
|
|---|
| 3736 | * Do the tests.
|
|---|
| 3737 | */
|
|---|
| 3738 | Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY);
|
|---|
| 3739 | #ifdef BS3_SKIPIT_DO_SKIP
|
|---|
| 3740 | bs3CpuInstrX_ShowTallies();
|
|---|
| 3741 | #endif
|
|---|
| 3742 | }
|
|---|
| 3743 | else
|
|---|
| 3744 | Bs3TestFailed("Failed to allocate 16K alias buffer (tiled addressable)");
|
|---|
| 3745 | }
|
|---|
| 3746 | else
|
|---|
| 3747 | Bs3TestFailed("Failed to allocate 16K buffer (real mode addressable)");
|
|---|
| 3748 | }
|
|---|
| 3749 |
|
|---|
| 3750 | Bs3TestTerm();
|
|---|
| 3751 | }
|
|---|
| 3752 |
|
|---|
