bs3-cpu-instr-4.c32@ 105458

Last change on this file since 105458 was 105458, checked in by vboxsync, 4 months ago
ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: Allow setting all MXCSR bits (other than MXCSR.MM bit) prior to testing the instruction and explicitly specifying FP-exception for 128-bit and 256-bit variants.
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1	/* $Id: bs3-cpu-instr-4.c32 105458 2024-07-24 08:24:49Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-instr-4 - SSE, AVX FPU instructions, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* The contents of this file may alternatively be used under the terms
26	* of the Common Development and Distribution License Version 1.0
27	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	* in the VirtualBox distribution, in which case the provisions of the
29	* CDDL are applicable instead of those of the GPL.
30	*
31	* You may elect to license modified versions of this file under the
32	* terms and conditions of either the GPL or the CDDL or both.
33	*
34	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	*/
36
37
38	/*********************************************************************************************************************************
39	* Header Files *
40	*********************************************************************************************************************************/
41	#include <bs3kit.h>
42	#include "bs3-cpu-instr-4-asm-auto.h"
43
44	#include <iprt/asm.h>
45	#include <iprt/asm-amd64-x86.h>
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	/** Converts an execution mode (BS3_MODE_XXX) into an index into an array
52	* initialized by BS3CPUINSTR4_TEST1_MODES_INIT etc. */
53	#define BS3CPUINSTR4_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2)
54
55	/** Maximum length for the names of all SIMD FP exception flags combined. */
56	#define FP_XCPT_FLAGS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
57	/** Maximum length for the names of all SIMD FP exception masks combined. */
58	#define FP_XCPT_MASKS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
59	/** Maximum length for the names of all SIMD FP exception other bits combined. */
60	#define FP_XCPT_OTHERS_NAMES_MAXLEN sizeof(" DAZ FZ MM RC=NEAREST ")
61
62	/*
63	* Single-precision (32 bits) floating-point defines.
64	*/
65	/** The max exponent value for a single-precision floating-point normal. */
66	#define FP32_EXP_NORM_MAX 254
67	/** The min exponent value for a single-precision floating-point normal. */
68	#define FP32_EXP_NORM_MIN 1
69	/** The max fraction value for a single-precision floating-point normal. */
70	#define FP32_FRAC_NORM_MAX 0x7fffff
71	/** The min fraction value for a single-precision floating-point normal. */
72	#define FP32_FRAC_NORM_MIN 0
73	/** The exponent bias for the single-precision floating-point format. */
74	#define FP32_EXP_BIAS RTFLOAT32U_EXP_BIAS
75	/** Fraction width (in bits) for the single-precision floating-point format. */
76	#define FP32_FRAC_BITS RTFLOAT32U_FRACTION_BITS
77	/** The max exponent value for a single-precision floating-point integer without
78	* losing precision. */
79	#define FP32_EXP_SAFE_INT_MAX FP32_EXP_BIAS + FP32_FRAC_BITS
80	/** The min exponent value for a single-precision floating-point integer without
81	* losing precision. */
82	#define FP32_EXP_SAFE_INT_MIN 1
83	/** The max fraction value for a double-precision floating-point denormal. */
84	#define FP32_FRAC_DENORM_MAX 0x7fffff
85	/** The min fraction value for a double-precision floating-point denormal. */
86	#define FP32_FRAC_DENORM_MIN 1
87
88	#define FP32_NORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_NORM_MAX)
89	#define FP32_NORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN)
90	#define FP32_0(a_Sign) RTFLOAT32U_INIT_ZERO(a_Sign)
91	#define FP32_1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0, RTFLOAT32U_EXP_BIAS)
92	#define FP32_V(a_Sign, a_Frac, a_Exp) RTFLOAT32U_INIT_C(a_Sign, a_Frac, a_Exp)
93	#define FP32_INF(a_Sign) RTFLOAT32U_INIT_INF(a_Sign)
94	#define FP32_QNAN(a_Sign) RTFLOAT32U_INIT_QNAN(a_Sign)
95	#define FP32_QNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val)
96	#define FP32_SNAN(a_Sign) RTFLOAT32U_INIT_SNAN(a_Sign)
97	#define FP32_SNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_SNAN_EX(a_Sign, a_Val)
98
99	/*
100	* Single-precision floating normals.
101	* Fraction - 23 bits, all usable.
102	* Exponent - 8 bits, least significant bit MBZ.
103	*/
104	#define FP32_FRAC_V0 0x401ac0
105	#define FP32_FRAC_V1 0x5fcabd
106	#define FP32_FRAC_V2 0x7e117a
107	#define FP32_FRAC_V3 0x5b5b5b
108	#define FP32_FRAC_V4 0x1e0f1f
109	#define FP32_FRAC_V5 0x012345
110	#define FP32_FRAC_V6 0x330b3b
111	#define FP32_FRAC_V7 0x4ebeb4
112	#define FP32_EXP_V0 0x78
113	#define FP32_EXP_V1 0xbc
114	#define FP32_EXP_V2 0x7e
115	#define FP32_EXP_V3 0x9a
116	#define FP32_EXP_V4 0x32
117	#define FP32_EXP_V5 0x56
118	#define FP32_EXP_V6 0x90
119	#define FP32_EXP_V7 0x30
120	AssertCompile(!(FP32_EXP_V0 & RT_BIT(0)));
121	AssertCompile(!(FP32_EXP_V1 & RT_BIT(0)));
122	AssertCompile(!(FP32_EXP_V2 & RT_BIT(0)));
123	AssertCompile(!(FP32_EXP_V3 & RT_BIT(0)));
124	AssertCompile(!(FP32_EXP_V4 & RT_BIT(0)));
125	AssertCompile(!(FP32_EXP_V5 & RT_BIT(0)));
126	AssertCompile(!(FP32_EXP_V6 & RT_BIT(0)));
127	AssertCompile(!(FP32_EXP_V7 & RT_BIT(0)));
128	#define FP32_NORM_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V0, FP32_EXP_V0)
129	#define FP32_NORM_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V1, FP32_EXP_V1)
130	#define FP32_NORM_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V2, FP32_EXP_V2)
131	#define FP32_NORM_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V3, FP32_EXP_V3)
132	#define FP32_NORM_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V4, FP32_EXP_V4)
133	#define FP32_NORM_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V5, FP32_EXP_V5)
134	#define FP32_NORM_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V6, FP32_EXP_V6)
135	#define FP32_NORM_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V7, FP32_EXP_V7)
136	/* The maximum integer value (all 23 + 1 implied bit of the fraction part set) without losing precision. */
137	#define FP32_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX)
138	/* The minimum integer value without losing precision. */
139	#define FP32_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_SAFE_INT_MIN)
140
141	/*
142	* Single-precision floating-point denormals.
143	*/
144	/** The maximum denormal value. */
145	#define FP32_DENORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MAX, 0)
146	/** The maximum denormal value. */
147	#define FP32_DENORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MIN, 0)
148
149	/*
150	* Single-precision random values (incl. potentially invalid values).
151	* We don't care what the exact values are as these are meant to populate
152	* unmodified operands and be compared bitwise.
153	*/
154	#define FP32_RAND_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7bacda, 0x55)
155	#define FP32_RAND_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7010f0, 0xc0)
156	#define FP32_RAND_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x4ffcbe, 0xf1)
157	#define FP32_RAND_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x2fd7c8, 0x1f)
158	#define FP32_RAND_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5b5b5b, 0x09)
159	#define FP32_RAND_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x3d2d1d, 0x99)
160	#define FP32_RAND_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x123456, 0x5e)
161	#define FP32_RAND_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x05432f, 0xd7)
162
163	/*
164	* Double-precision (64 bits) floating-point defines.
165	*/
166	/** The max exponent value for a double-precision floating-point normal. */
167	#define FP64_EXP_NORM_MAX 2046
168	/** The min exponent value for a double-precision floating-point normal. */
169	#define FP64_EXP_NORM_MIN 1
170	/** The max fraction value for a double-precision floating-point normal. */
171	#define FP64_FRAC_NORM_MAX 0xfffffffffffff
172	/** The min fraction value for a double-precision floating-point normal. */
173	#define FP64_FRAC_NORM_MIN 0
174	/** The exponent bias for the double-precision floating-point format. */
175	#define FP64_EXP_BIAS RTFLOAT64U_EXP_BIAS
176	/** Fraction width (in bits) for the double-precision floating-point format. */
177	#define FP64_FRAC_BITS RTFLOAT64U_FRACTION_BITS
178	/** The max exponent value for a double-precision floating-point integer without
179	* losing precision. */
180	#define FP64_EXP_SAFE_INT_MAX FP64_EXP_BIAS + FP64_FRAC_BITS
181	/** The min exponent value for a double-precision floating-point integer without
182	* losing precision. */
183	#define FP64_EXP_SAFE_INT_MIN 1
184	/** The max fraction value for a double-precision floating-point denormal. */
185	#define FP64_FRAC_DENORM_MAX 0xfffffffffffff
186	/** The min fraction value for a double-precision floating-point denormal. */
187	#define FP64_FRAC_DENORM_MIN 1
188
189	#define FP64_NORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX)
190	#define FP64_NORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_NORM_MIN)
191	#define FP64_0(a_Sign) RTFLOAT64U_INIT_ZERO(a_Sign)
192	#define FP64_1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0, RTFLOAT64U_EXP_BIAS)
193	#define FP64_V(a_Sign, a_Frac, a_Exp) RTFLOAT64U_INIT_C(a_Sign, a_Frac, a_Exp)
194	#define FP64_INF(a_Sign) RTFLOAT64U_INIT_INF(a_Sign)
195	#define FP64_QNAN(a_Sign) RTFLOAT64U_INIT_QNAN(a_Sign)
196	#define FP64_QNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val)
197	#define FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign)
198	#define FP64_SNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val)
199
200	/*
201	* Double-precision floating-point normals.
202	* Fraction - 52 bits, all usable.
203	* Exponent - 11 bits, least significant bit MBZ.
204	*/
205	#define FP64_FRAC_V0 0xacc01adec0de5
206	#define FP64_FRAC_V1 0xf10a7ab1ec01a
207	#define FP64_FRAC_V2 0xca5cadea1b1ed
208	#define FP64_FRAC_V3 0xb5b5b5b5b5b5b
209	#define FP64_EXP_V0 0x30c
210	#define FP64_EXP_V1 0x4bc
211	#define FP64_EXP_V2 0x3ae
212	#define FP64_EXP_V3 0x7fe
213	AssertCompile(!(FP64_EXP_V0 & RT_BIT(0)));
214	AssertCompile(!(FP64_EXP_V1 & RT_BIT(0)));
215	AssertCompile(!(FP64_EXP_V2 & RT_BIT(0)));
216	AssertCompile(!(FP64_EXP_V3 & RT_BIT(0)));
217	#define FP64_NORM_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V0, FP64_EXP_V0)
218	#define FP64_NORM_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V1, FP64_EXP_V1)
219	#define FP64_NORM_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V2, FP64_EXP_V2)
220	#define FP64_NORM_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V3, FP64_EXP_V3)
221	/* The maximum integer value (all 52 + 1 implied bit of the fraction part set) without losing precision. */
222	#define FP64_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX)
223	/* The minimum integer value without losing precision. */
224	#define FP64_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_SAFE_INT_MIN)
225
226	/*
227	* Double-precision floating-point denormals.
228	*/
229	/** The maximum denormal value. */
230	#define FP64_DENORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MAX, 0)
231	/** The maximum denormal value. */
232	#define FP64_DENORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MIN, 0)
233
234
235	/*********************************************************************************************************************************
236	* Structures and Typedefs *
237	*********************************************************************************************************************************/
238	/** Instruction set type and operand width. */
239	typedef enum BS3CPUINSTRX_INSTRTYPE_T
240	{
241	T_INVALID,
242	T_MMX,
243	T_MMX_SSE, /*< MMX instruction, but require the SSE CPUID to work. /
244	T_MMX_SSE2, /*< MMX instruction, but require the SSE2 CPUID to work. /
245	T_MMX_SSSE3, /*< MMX instruction, but require the SSSE3 CPUID to work. /
246	T_AXMMX,
247	T_AXMMX_OR_SSE,
248	T_SSE,
249	T_128BITS = T_SSE,
250	T_SSE2,
251	T_SSE3,
252	T_SSSE3,
253	T_SSE4_1,
254	T_SSE4_2,
255	T_SSE4A,
256	T_PCLMUL,
257	T_SHA,
258	T_AVX_128,
259	T_AVX2_128,
260	T_AVX_PCLMUL,
261	T_AVX_256,
262	T_256BITS = T_AVX_256,
263	T_AVX2_256,
264	T_MAX
265	} BS3CPUINSTRX_INSTRTYPE_T;
266
267	/** Memory or register rm variant. */
268	enum {
269	RM_REG = 0,
270	RM_MEM,
271	RM_MEM8, /*< Memory operand is 8 bytes. Hack for movss and similar. /
272	RM_MEM16, /*< Memory operand is 16 bytes. Hack for movss and similar. /
273	RM_MEM32, /*< Memory operand is 32 bytes. Hack for movss and similar. /
274	RM_MEM64 /*< Memory operand is 64 bytes. Hack for movss and similar. /
275	};
276
277	/**
278	* Execution environment configuration.
279	*/
280	typedef struct BS3CPUINSTR4_CONFIG_T
281	{
282	uint16_t fCr0Mp : 1;
283	uint16_t fCr0Em : 1;
284	uint16_t fCr0Ts : 1;
285	uint16_t fCr4OsFxSR : 1;
286	uint16_t fCr4OsXSave : 1;
287	uint16_t fCr4OsXmmExcpt : 1;
288	uint16_t fXcr0Sse : 1;
289	uint16_t fXcr0Avx : 1;
290	uint16_t fAligned : 1; /*< Aligned mem operands. If 0, they will be misaligned and tests w/o mem operands skipped. /
291	uint16_t fAlignCheck : 1;
292	uint16_t fMxCsrMM : 1; /*< AMD only /
293	uint8_t bXcptSse;
294	uint8_t bXcptAvx;
295	} BS3CPUINSTR4_CONFIG_T;
296	/** Pointer to an execution environment configuration. */
297	typedef BS3CPUINSTR4_CONFIG_T const BS3_FAR *PCBS3CPUINSTR4_CONFIG_T;
298
299	/** State saved by bs3CpuInstr4ConfigReconfigure. */
300	typedef struct BS3CPUINSTRX_CONFIG_SAVED_T
301	{
302	uint32_t uCr0;
303	uint32_t uCr4;
304	uint32_t uEfl;
305	uint16_t uFcw;
306	uint16_t uFsw;
307	uint32_t uMxCsr;
308	} BS3CPUINSTRX_CONFIG_SAVED_T;
309	typedef BS3CPUINSTRX_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTRX_CONFIG_SAVED_T;
310	typedef BS3CPUINSTRX_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTRX_CONFIG_SAVED_T;
311
312	/**
313	* YMM packed single-precision floating-point register.
314	* @todo move to x86.h?
315	*/
316	typedef union X86YMMFLOATPSREG
317	{
318	/** Packed single-precision floating-point view. */
319	RTFLOAT32U ar32[8];
320	/** 256-bit integer view. */
321	RTUINT256U ymm;
322	} X86YMMFLOATPSREG;
323	# ifndef VBOX_FOR_DTRACE_LIB
324	AssertCompileSize(X86YMMFLOATPSREG, 32);
325	AssertCompileSize(X86YMMFLOATPSREG, sizeof(X86YMMREG));
326	# endif
327	/** Pointer to a YMM packed single-precision floating-point register. */
328	typedef X86YMMFLOATPSREG BS3_FAR *PX86YMMFLOATPSREG;
329	/** Pointer to a const YMM single-precision packed floating-point register. */
330	typedef X86YMMFLOATPSREG const BS3_FAR *PCX86YMMFLOATPSREG;
331
332	/**
333	* YMM packed double-precision floating-point register.
334	* @todo move to x86.h?
335	*/
336	typedef union X86YMMFLOATPDREG
337	{
338	/** Packed double-precision floating-point view. */
339	RTFLOAT64U ar64[4];
340	/** 256-bit integer view. */
341	RTUINT256U ymm;
342	} X86YMMFLOATPDREG;
343	# ifndef VBOX_FOR_DTRACE_LIB
344	AssertCompileSize(X86YMMFLOATPDREG, 32);
345	AssertCompileSize(X86YMMFLOATPDREG, sizeof(X86YMMREG));
346	# endif
347	/** Pointer to a YMM packed floating-point register. */
348	typedef X86YMMFLOATPDREG BS3_FAR *PX86YMMFLOATPDREG;
349	/** Pointer to a const YMM packed floating-point register. */
350	typedef X86YMMFLOATPDREG const BS3_FAR *PCX86YMMFLOATPDREG;
351
352	/**
353	* YMM scalar single-precision floating-point register.
354	* @todo move to x86.h?
355	*/
356	typedef union X86YMMFLOATSSREG
357	{
358	/** Scalar single-precision floating-point view. */
359	RTFLOAT32U ar32[8];
360	/** 256-bit integer view. */
361	RTUINT256U ymm;
362	} X86YMMFLOATSSREG;
363	# ifndef VBOX_FOR_DTRACE_LIB
364	AssertCompileSize(X86YMMFLOATSSREG, 32);
365	AssertCompileSize(X86YMMFLOATSSREG, sizeof(X86YMMREG));
366	# endif
367	/** Pointer to a YMM scalar single-precision floating-point register. */
368	typedef X86YMMFLOATSSREG BS3_FAR *PX86YMMFLOATSSREG;
369	/** Pointer to a const YMM scalar single-precision floating-point register. */
370	typedef X86YMMFLOATSSREG const BS3_FAR *PCX86YMMFLOATSSREG;
371
372	/**
373	* YMM scalar double-precision floating-point register.
374	* @todo move to x86.h?
375	*/
376	typedef union X86YMMFLOATSDREG
377	{
378	/** Scalar double-precision floating-point view. */
379	RTFLOAT64U ar64[3];
380	/** 256-bit integer view. */
381	RTUINT256U ymm;
382	} X86YMMFLOATSDREG;
383	# ifndef VBOX_FOR_DTRACE_LIB
384	AssertCompileSize(X86YMMFLOATSDREG, 32);
385	AssertCompileSize(X86YMMFLOATSDREG, sizeof(X86YMMREG));
386	# endif
387	/** Pointer to a YMM scalar double-precision floating-point register. */
388	typedef X86YMMFLOATSDREG BS3_FAR *PX86YMMFLOATSDREG;
389	/** Pointer to a const YMM scalar double-precision floating-point register. */
390	typedef X86YMMFLOATSDREG const BS3_FAR *PCX86YMMFLOATSDREG;
391
392	/**
393	* YMM scalar quadruple-precision floating-point register.
394	* @todo move to x86.h?
395	*/
396	typedef union X86YMMFLOATSQREG
397	{
398	/** Scalar quadruple-precision floating point view. */
399	RTFLOAT128U ar128[2];
400	/** 256-bit integer view. */
401	RTUINT256U ymm;
402	} X86YMMFLOATSQREG;
403	# ifndef VBOX_FOR_DTRACE_LIB
404	AssertCompileSize(X86YMMFLOATSQREG, 32);
405	AssertCompileSize(X86YMMFLOATSQREG, sizeof(X86YMMREG));
406	# endif
407	/** Pointer to a YMM scalar quadruple-precision floating-point register. */
408	typedef X86YMMFLOATSQREG *PX86YMMFLOATSQREG;
409	/** Pointer to a const YMM scalar quadruple-precision floating-point register. */
410	typedef X86YMMFLOATSQREG const *PCX86YMMFLOATSQREG;
411
412
413	/*********************************************************************************************************************************
414	* Global Variables *
415	*********************************************************************************************************************************/
416	static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false };
417	static bool g_fAmdMisalignedSse = false;
418	static uint8_t g_enmExtCtxMethod = BS3EXTCTXMETHOD_INVALID;
419	static bool g_fMxCsrDazSupported = false;
420
421	/** Size of g_pbBuf - at least three pages. */
422	static uint32_t g_cbBuf;
423	/** Buffer of g_cbBuf size. */
424	static uint8_t BS3_FAR *g_pbBuf;
425	/** RW alias for the buffer memory at g_pbBuf. Set up by bs3CpuInstrXBufSetup. */
426	static uint8_t BS3_FAR *g_pbBufAlias;
427	/** RW alias for the memory at g_pbBuf. */
428	static uint8_t BS3_FAR *g_pbBufAliasAlloc;
429
430	/** Exception type \#2 test configurations, 16 & 32 bytes strictly aligned. */
431	static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig2[] =
432	{
433	/*
434	* X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
435	* +AVX +AVX +AMD/SSE +AMD/SSE
436	* CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
437	* MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
438	{ 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
439	{ 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
440	{ 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
441	{ 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
442	{ 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
443	{ 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
444	{ 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
445	{ 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
446	{ 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
447	{ 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
448	/* Memory misalignment and alignment checks: */
449	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
450	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #11 */
451	{ 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
452	/* AMD only: */
453	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
454	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
455	};
456
457	/** Exception type \#3 test configurations (< 16-byte memory argument). */
458	static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig3[] =
459	{
460	/*
461	* X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
462	* +AVX +AVX +AMD/SSE +AMD/SSE
463	* CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
464	* MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
465	{ 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
466	{ 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
467	{ 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
468	{ 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
469	{ 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
470	{ 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
471	{ 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
472	{ 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
473	{ 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
474	{ 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
475	/* Memory misalignment and alignment checks: */
476	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #10 / / [Avx]:DB */
477	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC }, /* #11 / / [Avx]:AC */
478	{ 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
479	/* AMD only: */
480	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
481	{ 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
482	};
483
484
485	/**
486	* Returns the name of an X86 exception given the vector.
487	*
488	* @returns Name of the exception.
489	* @param uVector The exception vector.
490	*/
491	static const char BS3_FAR *bs3CpuInstr4XcptName(uint8_t uVector)
492	{
493	switch (uVector)
494	{
495	case X86_XCPT_DE: return "#DE";
496	case X86_XCPT_DB: return "#DB";
497	case X86_XCPT_NMI: return "#NMI";
498	case X86_XCPT_BP: return "#BP";
499	case X86_XCPT_OF: return "#OF";
500	case X86_XCPT_BR: return "#BR";
501	case X86_XCPT_UD: return "#UD";
502	case X86_XCPT_NM: return "#NM";
503	case X86_XCPT_DF: return "#DF";
504	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
505	case X86_XCPT_TS: return "#TS";
506	case X86_XCPT_NP: return "#NP";
507	case X86_XCPT_SS: return "#SS";
508	case X86_XCPT_GP: return "#GP";
509	case X86_XCPT_PF: return "#PF";
510	case X86_XCPT_MF: return "#MF";
511	case X86_XCPT_AC: return "#AC";
512	case X86_XCPT_MC: return "#MC";
513	case X86_XCPT_XF: return "#XF";
514	case X86_XCPT_VE: return "#VE";
515	case X86_XCPT_CP: return "#CP";
516	case X86_XCPT_VC: return "#VC";
517	case X86_XCPT_SX: return "#SX";
518	}
519	return "UNKNOWN";
520	}
521
522
523	DECL_FORCE_INLINE(bool) bs3CpuInstr4IsSse(uint8_t enmType)
524	{
525	return enmType >= T_SSE && enmType < T_AVX_128;
526	}
527
528
529	DECL_FORCE_INLINE(bool) bs3CpuInstr4IsAvx(uint8_t enmType)
530	{
531	return enmType >= T_AVX_128;
532	}
533
534
535	DECL_FORCE_INLINE(uint8_t) bs3CpuInstr4GetOperandSize(uint8_t enmType)
536	{
537	return enmType < T_128BITS ? 64/8
538	: enmType < T_256BITS ? 128/8 : 256/8;
539	}
540
541
542	/**
543	* Gets the names of floating-point exception flags that are set for a given MXCSR.
544	*
545	* @returns Names of floating-point exception flags that are set.
546	* @param pszBuf Where to store the floating-point exception flags.
547	* @param cchBuf The size of the buffer.
548	* @param uMxCsr The MXCSR value.
549	*/
550	static size_t bs3CpuInstr4GetXcptFlags(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
551	{
552	BS3_ASSERT(cchBuf >= FP_XCPT_FLAGS_NAMES_MAXLEN);
553	return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IE ? " IE" : "", uMxCsr & X86_MXCSR_DE ? " DE" : "",
554	uMxCsr & X86_MXCSR_ZE ? " ZE" : "", uMxCsr & X86_MXCSR_OE ? " OE" : "",
555	uMxCsr & X86_MXCSR_UE ? " UE" : "", uMxCsr & X86_MXCSR_PE ? " PE" : "");
556	}
557
558	/**
559	* Gets the names of floating-point exception mask that are set for a given MXCSR.
560	*
561	* @returns Names of floating-point exception flags that are set.
562	* @param pszBuf Where to store the floating-point exception flags.
563	* @param cchBuf The size of the buffer.
564	* @param uMxCsr The MXCSR value.
565	*/
566	static size_t bs3CpuInstr4GetXcptMasks(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
567	{
568	BS3_ASSERT(cchBuf >= FP_XCPT_MASKS_NAMES_MAXLEN);
569	return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IM ? " IM" : "", uMxCsr & X86_MXCSR_DM ? " DM" : "",
570	uMxCsr & X86_MXCSR_ZM ? " ZM" : "", uMxCsr & X86_MXCSR_OM ? " OM" : "",
571	uMxCsr & X86_MXCSR_UM ? " UM" : "", uMxCsr & X86_MXCSR_PM ? " PM" : "");
572	}
573
574
575	/**
576	* Gets the names of floating-point bits other than flags and masks that are set for
577	* a given MXCSR.
578	*
579	* @returns Names of floating-point exception flags that are set.
580	* @param pszBuf Where to store the floating-point exception flags.
581	* @param cchBuf The size of the buffer.
582	* @param uMxCsr The MXCSR value.
583	*/
584	static size_t bs3CpuInstr4GetXcptOthers(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
585	{
586	uint32_t const fMxCsrRc = uMxCsr & X86_MXCSR_RC_MASK;
587	BS3_ASSERT(cchBuf >= FP_XCPT_OTHERS_NAMES_MAXLEN);
588	return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s", uMxCsr & X86_MXCSR_DAZ ? " DAZ" : "",
589	uMxCsr & X86_MXCSR_FZ ? " FZ" : "",
590	uMxCsr & X86_MXCSR_MM ? " MM" : "",
591	fMxCsrRc == X86_MXCSR_RC_NEAREST ? " RC=NEAREST" :
592	fMxCsrRc == X86_MXCSR_RC_DOWN ? " RC=DOWN" :
593	fMxCsrRc == X86_MXCSR_RC_UP ? " RC=UP" :
594	fMxCsrRc == X86_MXCSR_RC_ZERO ? " RC=ZERO" : "");
595	}
596
597
598	/**
599	* Reconfigures the execution environment according to @a pConfig.
600	*
601	* Call bs3CpuInstrXConfigRestore to undo the changes.
602	*
603	* @returns true on success, false if the configuration cannot be applied. In
604	* the latter case, no context changes are made.
605	* @param pSavedCfg Where to save state we modify.
606	* @param pCtx The register context to modify.
607	* @param pExtCtx The extended register context to modify.
608	* @param pConfig The configuration to apply.
609	* @param bMode The target mode.
610	*/
611	static bool bs3CpuInstr4ConfigReconfigure(PBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx,
612	PCBS3CPUINSTR4_CONFIG_T pConfig, uint8_t bMode)
613	{
614	/*
615	* Save context bits we may change here
616	*/
617	pSavedCfg->uCr0 = pCtx->cr0.u32;
618	pSavedCfg->uCr4 = pCtx->cr4.u32;
619	pSavedCfg->uEfl = pCtx->rflags.u32;
620	pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx);
621	pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx);
622	pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx);
623
624	/*
625	* Can we make these changes?
626	*/
627	if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse)
628	return false;
629
630	/*
631	* Modify the test context.
632	*/
633	if (pConfig->fCr0Mp)
634	pCtx->cr0.u32 \|= X86_CR0_MP;
635	else
636	pCtx->cr0.u32 &= ~X86_CR0_MP;
637	if (pConfig->fCr0Em)
638	pCtx->cr0.u32 \|= X86_CR0_EM;
639	else
640	pCtx->cr0.u32 &= ~X86_CR0_EM;
641	if (pConfig->fCr0Ts)
642	pCtx->cr0.u32 \|= X86_CR0_TS;
643	else
644	pCtx->cr0.u32 &= ~X86_CR0_TS;
645
646	if (pConfig->fCr4OsFxSR)
647	pCtx->cr4.u32 \|= X86_CR4_OSFXSR;
648	else
649	pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
650
651	if (pConfig->fCr4OsXmmExcpt && g_afTypeSupports[T_SSE])
652	pCtx->cr4.u32 \|= X86_CR4_OSXMMEEXCPT;
653	else
654	pCtx->cr4.u32 &= ~X86_CR4_OSXMMEEXCPT;
655
656	if (pConfig->fCr4OsFxSR)
657	pCtx->cr4.u32 \|= X86_CR4_OSFXSR;
658	else
659	pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
660
661	if (pConfig->fCr4OsXSave)
662	pCtx->cr4.u32 \|= X86_CR4_OSXSAVE;
663	else
664	pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE;
665
666	if (pConfig->fXcr0Sse)
667	pExtCtx->fXcr0Saved \|= XSAVE_C_SSE;
668	else
669	pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE;
670	if (pConfig->fXcr0Avx && g_afTypeSupports[T_AVX_256])
671	pExtCtx->fXcr0Saved \|= XSAVE_C_YMM;
672	else
673	pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM;
674
675	if (pConfig->fAlignCheck)
676	{
677	pCtx->rflags.u32 \|= X86_EFL_AC;
678	pCtx->cr0.u32 \|= X86_CR0_AM;
679	}
680	else
681	{
682	pCtx->rflags.u32 &= ~X86_EFL_AC;
683	pCtx->cr0.u32 &= ~X86_CR0_AM;
684	}
685
686	/** @todo Can we remove this? x87 FPU and SIMD are independent. */
687	Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES \| X86_FSW_B));
688
689	if (pConfig->fMxCsrMM)
690	Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr \| X86_MXCSR_MM);
691	else
692	Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM);
693	return true;
694	}
695
696
697	/**
698	* Undoes changes made by bs3CpuInstr4ConfigReconfigure.
699	*/
700	static void bs3CpuInstrXConfigRestore(PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx)
701	{
702	pCtx->cr0.u32 = pSavedCfg->uCr0;
703	pCtx->cr4.u32 = pSavedCfg->uCr4;
704	pCtx->rflags.u32 = pSavedCfg->uEfl;
705	pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal;
706	Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw);
707	Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw);
708	Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr);
709	}
710
711
712	/**
713	* Allocates three extended CPU contexts and initializes the first one
714	* with random data.
715	* @returns First extended context, initialized with randomish data. NULL on
716	* failure (complained).
717	* @param ppExtCtx2 Where to return the 2nd context.
718	*/
719	static PBS3EXTCTX bs3CpuInstrXAllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2)
720	{
721	/* Allocate extended context structures. */
722	uint64_t fFlags;
723	uint16_t cb = Bs3ExtCtxGetSize(&fFlags);
724	PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2);
725	PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb);
726	if (pExtCtx1)
727	{
728	Bs3ExtCtxInit(pExtCtx1, cb, fFlags);
729	/** @todo populate with semi-random stuff. */
730
731	Bs3ExtCtxInit(pExtCtx2, cb, fFlags);
732	*ppExtCtx2 = pExtCtx2;
733	return pExtCtx1;
734	}
735	Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2);
736	*ppExtCtx2 = NULL;
737	return NULL;
738	}
739
740
741	/**
742	* Frees the extended CPU contexts allocated by bs3CpuInstrXAllocExtCtxs.
743	*
744	* @param pExtCtx1 The first extended context.
745	* @param pExtCtx2 The second extended context.
746	*/
747	static void bs3CpuInstrXFreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
748	{
749	RT_NOREF_PV(pExtCtx2);
750	Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2);
751	}
752
753
754	/**
755	* Sets up SSE and AVX bits relevant for FPU instructions.
756	*/
757	static void bs3CpuInstr4SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx)
758	{
759	/* CR0: */
760	uint32_t cr0 = Bs3RegGetCr0();
761	cr0 &= ~(X86_CR0_TS \| X86_CR0_MP \| X86_CR0_EM);
762	cr0 \|= X86_CR0_NE;
763	Bs3RegSetCr0(cr0);
764
765	/* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */
766	pCtx->cr0.u32 &= ~(X86_CR0_TS \| X86_CR0_MP \| X86_CR0_EM);
767	pCtx->cr0.u32 \|= X86_CR0_NE;
768
769	/* CR4: */
770	BS3_ASSERT( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
771	\|\| pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE);
772	{
773	uint32_t cr4 = Bs3RegGetCr4();
774	if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
775	{
776	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE;
777	Bs3RegSetCr4(cr4);
778	Bs3RegSetXcr0(pExtCtx->fXcr0Nominal);
779	}
780	else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
781	{
782	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT;
783	Bs3RegSetCr4(cr4);
784	}
785	pCtx->cr4.u32 = cr4;
786	}
787	}
788
789
790	/**
791	* Configures the buffer with electric fences in paged modes.
792	*
793	* @returns Adjusted buffer pointer.
794	* @param pbBuf The buffer pointer.
795	* @param pcbBuf Pointer to the buffer size (input & output).
796	* @param bMode The testing target mode.
797	*/
798	DECLINLINE(uint8_t BS3_FAR ) bs3CpuInstrXBufSetup(uint8_t BS3_FAR pbBuf, uint32_t *pcbBuf, uint8_t bMode)
799	{
800	if (BS3_MODE_IS_PAGED(bMode))
801	{
802	int rc;
803	uint32_t cbBuf = *pcbBuf;
804	Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P);
805	Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P);
806	pbBuf += X86_PAGE_SIZE;
807	cbBuf -= X86_PAGE_SIZE * 2;
808	*pcbBuf = cbBuf;
809
810	g_pbBufAlias = g_pbBufAliasAlloc;
811	rc = Bs3PagingAlias((uintptr_t)g_pbBufAlias, (uintptr_t)pbBuf, cbBuf + X86_PAGE_SIZE, /* must include the tail guard pg */
812	X86_PTE_P \| X86_PTE_A \| X86_PTE_D \| X86_PTE_RW);
813	if (RT_FAILURE(rc))
814	Bs3TestFailedF("Bs3PagingAlias failed on %p/%p LB %#x: %d", g_pbBufAlias, pbBuf, cbBuf, rc);
815	}
816	else
817	g_pbBufAlias = pbBuf;
818	return pbBuf;
819	}
820
821
822	/**
823	* Undoes what bs3CpuInstrXBufSetup did.
824	*
825	* @param pbBuf The buffer pointer.
826	* @param cbBuf The buffer size.
827	* @param bMode The testing target mode.
828	*/
829	DECLINLINE(void) bs3CpuInstrXBufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode)
830	{
831	if (BS3_MODE_IS_PAGED(bMode))
832	{
833	Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0);
834	Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0);
835	}
836	}
837
838
839	/**
840	* Gets a buffer of a @a cbMemOp sized operand according to the given
841	* configuration and alignment restrictions.
842	*
843	* @returns Pointer to the buffer.
844	* @param pbBuf The buffer pointer.
845	* @param cbBuf The buffer size.
846	* @param cbMemOp The operand size.
847	* @param cbAlign The operand alignment restriction.
848	* @param pConfig The configuration.
849	* @param fPageFault The \#PF test setting.
850	*/
851	DECLINLINE(uint8_t BS3_FAR ) bs3CpuInstrXBufForOperand(uint8_t BS3_FAR pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign,
852	PCBS3CPUINSTR4_CONFIG_T pConfig, unsigned fPageFault)
853	{
854	/* All allocations are at the tail end of the buffer, so that we've got a
855	guard page following the operand. When asked to consistenly trigger
856	a #PF, we slide the buffer into that guard page. */
857	if (fPageFault)
858	cbBuf += X86_PAGE_SIZE;
859
860	if (pConfig->fAligned)
861	{
862	if (!pConfig->fAlignCheck)
863	return &pbBuf[cbBuf - cbMemOp];
864	return &pbBuf[cbBuf - cbMemOp - cbAlign];
865	}
866	return &pbBuf[cbBuf - cbMemOp - 1];
867	}
868
869
870	/**
871	* Determines the size of memory operands.
872	*/
873	DECLINLINE(uint8_t) bs3CpuInstrXMemOpSize(uint8_t cbOperand, uint8_t enmRm)
874	{
875	if (enmRm <= RM_MEM)
876	return cbOperand;
877	if (enmRm == RM_MEM8)
878	return sizeof(uint8_t);
879	if (enmRm == RM_MEM16)
880	return sizeof(uint16_t);
881	if (enmRm == RM_MEM32)
882	return sizeof(uint32_t);
883	if (enmRm == RM_MEM64)
884	return sizeof(uint64_t);
885	BS3_ASSERT(0);
886	return cbOperand;
887	}
888
889
890	/*
891	* Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly
892	* skips a large fraction of the micro-tests. It is sufficiently random
893	* that over a large number of runs, all micro-tests will be hit.
894	*
895	* This improves the runtime of the worst case (`#define ALL_TESTS' on a
896	* debug build, run with '--execute-all-in-iem') from ~9000 to ~800 seconds
897	* (on an Intel Core i7-10700, fwiw).
898	*
899	* To activate this 'developer's speed-testing mode', turn on
900	* `#define BS3_SKIPIT_DO_SKIP' here.
901	*
902	* BS3_SKIPIT_AVG_SKIP governs approximately how many micro-tests are
903	* skipped in a row; e.g. the default of 26 means about every 27th
904	* micro-test is run during a particular test run. (This is not 27x
905	* faster due to other activities which are not skipped!) Note this is
906	* only an average; the actual skips are random.
907	*
908	* You can also modify bs3CpuInstrX_SkipIt() to focus on specific sub-tests,
909	* using its (currently ignored) `bRing, iCfg, iTest, iVal, iVariant' args
910	* (to enable this: turn on `#define BS3_SKIPIT_DO_ARGS': which costs about
911	* 3% performance).
912	*
913	* Note! The skipping is not compatible with testing the native recompiler as
914	* it requires the test code to be run a number of times before it kicks
915	* in and does the native recompilation (currently around 16 times).
916	*/
917	#define BS3_SKIPIT_AVG_SKIP 26
918	#define BS3_SKIPIT_REPORT_COUNT 150000
919	#undef BS3_SKIPIT_DO_SKIP
920	#undef BS3_SKIPIT_DO_ARGS
921
922	#ifndef BS3_SKIPIT_DO_SKIP
923	# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) (false)
924	#else
925	# include <iprt/asm-amd64-x86.h>
926	# include <iprt/asm-math.h>
927
928	DECLINLINE(uint32_t) bs3CpuInstrX_SimpleRand(void)
929	{
930	/*
931	* A simple Lehmer linear congruential pseudo-random number
932	* generator using the constants suggested by Park & Miller:
933	*
934	* modulus = 2^31 - 1 (INT32_MAX)
935	* multiplier = 7^5 (16807)
936	*
937	* It produces numbers in the range [1..INT32_MAX-1] and is
938	* more chaotic in the higher bits.
939	*
940	* Note! Runtime/common/rand/randparkmiller.cpp is also use this algorithm,
941	* though the zero handling is different.
942	*/
943	static uint32_t s_uSeedMemory = 0;
944	uint32_t uVal = s_uSeedMemory;
945	if (!uVal)
946	uVal = (uint32_t)ASMReadTSC();
947	uVal = ASMModU64ByU32RetU32(ASMMult2xU32RetU64(uVal, 16807), INT32_MAX);
948	s_uSeedMemory = uVal;
949	return uVal;
950	}
951
952	static unsigned g_cSeen, g_cSkipped;
953
954	static void bs3CpuInstrX_ShowTallies(void)
955	{
956	Bs3TestPrintf("Micro-tests %d: tested %d / skipped %d\n", g_cSeen, g_cSeen - g_cSkipped, g_cSkipped);
957	}
958
959	# ifdef BS3_SKIPIT_DO_ARGS
960	# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt(bRing, iCfg, iTest, iVal, iVariant)
961	static bool bs3CpuInstrX_SkipIt(uint8_t bRing, unsigned iCfg, unsigned iTest, unsigned iVal, unsigned iVariant)
962	# else
963	# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt()
964	static bool bs3CpuInstrX_SkipIt(void)
965	# endif
966	{
967	static unsigned s_uTimes = 0;
968	bool fSkip;
969
970	/* Cache calls to the relatively expensive random routine */
971	if (!s_uTimes)
972	s_uTimes = bs3CpuInstrX_SimpleRand() % (BS3_SKIPIT_AVG_SKIP * 2 + 1) + 1;
973	fSkip = --s_uTimes > 0;
974	if (fSkip)
975	++g_cSkipped;
976
977	if (++g_cSeen % BS3_SKIPIT_REPORT_COUNT == 0)
978	bs3CpuInstrX_ShowTallies();
979	return fSkip;
980	}
981
982	#endif /* BS3_SKIPIT_DO_SKIP */
983
984	/*
985	* Test type #1.
986	* Generic YMM registers.
987	*/
988	typedef struct BS3CPUINSTR4_TEST1_VALUES_T
989	{
990	X86YMMREG uSrc2; /*< Second source operand. /
991	X86YMMREG uSrc1; /*< uDstIn for SSE /
992	X86YMMREG uDstOut; /*< Destination output. /
993	uint32_t uMxCsr; /*< MXCSR to set prior to executing the instruction. /
994	uint32_t u128ExpectedMxCsr; /*< Expected MXCSR for a 128-bit instruction. /
995	uint32_t u256ExpectedMxCsr; /*< Expected MXCSR for a 256-bit instructions. /
996	uint8_t f128FpXcptExpected; /*< Whether a floating-point exception is expected for a 128-bit instruction. /
997	uint8_t f256FpXcptExpected; /*< Whether a floating-point exception is expected for a 256-bit instruction. /
998	uint8_t afPadding[2]; /*< Alignment padding. /
999	} BS3CPUINSTR4_TEST1_VALUES_T;
1000
1001	/*
1002	* Test type #1.
1003	* Packed single-precision.
1004	*/
1005	typedef struct BS3CPUINSTR4_TEST1_VALUES_PS_T
1006	{
1007	X86YMMFLOATPSREG uSrc2; /*< Second source operand. /
1008	X86YMMFLOATPSREG uSrc1; /*< uDstIn for SSE /
1009	X86YMMFLOATPSREG uDstOut; /*< Destination output. /
1010	uint32_t uMxCsr; /*< MXCSR to set prior to executing the instruction. /
1011	uint32_t u128ExpectedMxCsr; /*< Expected MXCSR for a 128-bit instruction. /
1012	uint32_t u256ExpectedMxCsr; /*< Expected MXCSR for a 256-bit instructions. /
1013	uint8_t f128FpXcptExpected; /*< Whether a floating-point exception is expected for a 128-bit instruction. /
1014	uint8_t f256FpXcptExpected; /*< Whether a floating-point exception is expected for a 256-bit instruction. /
1015	uint8_t afPadding[2]; /*< Alignment padding. /
1016	} BS3CPUINSTR4_TEST1_VALUES_PS_T;
1017	AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1018	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1019	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1020	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1021	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1022	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1023	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1024	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1025	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1026
1027	/*
1028	* Test type #1.
1029	* Packed double-precision.
1030	*/
1031	typedef struct BS3CPUINSTR4_TEST1_VALUES_PD_T
1032	{
1033	X86YMMFLOATPDREG uSrc2; /*< Second source operand. /
1034	X86YMMFLOATPDREG uSrc1; /*< uDstIn for SSE /
1035	X86YMMFLOATPDREG uDstOut; /*< Destination output. /
1036	uint32_t uMxCsr; /*< MXCSR to set prior to executing the instruction. /
1037	uint32_t u128ExpectedMxCsr; /*< Expected MXCSR for a 128-bit instruction. /
1038	uint32_t u256ExpectedMxCsr; /*< Expected MXCSR for a 256-bit instructions. /
1039	uint8_t f128FpXcptExpected; /*< Whether a floating-point exception is expected for a 128-bit instruction. /
1040	uint8_t f256FpXcptExpected; /*< Whether a floating-point exception is expected for a 256-bit instruction. /
1041	uint8_t afPadding[2]; /*< Alignment padding. /
1042	} BS3CPUINSTR4_TEST1_VALUES_PD_T;
1043	AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1044	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1045	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1046	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1047	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1048	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1049	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1050	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1051	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1052
1053	/*
1054	* Test type #1.
1055	* Scalar single-precision.
1056	*/
1057	typedef struct BS3CPUINSTR4_TEST1_VALUES_SS_T
1058	{
1059	X86YMMFLOATSSREG uSrc2; /*< Second source operand. /
1060	X86YMMFLOATSSREG uSrc1; /*< uDstIn for SSE /
1061	X86YMMFLOATSSREG uDstOut; /*< Destination output. /
1062	uint32_t uMxCsr; /*< MXCSR to set prior to executing the instruction. /
1063	uint32_t u128ExpectedMxCsr; /*< Expected MXCSR for a 128-bit instruction. /
1064	uint32_t u256ExpectedMxCsr; /*< Expected MXCSR for a 256-bit instructions. /
1065	uint8_t f128FpXcptExpected; /*< Whether a floating-point exception is expected for a 128-bit instruction. /
1066	uint8_t f256FpXcptExpected; /*< Whether a floating-point exception is expected for a 256-bit instruction. /
1067	uint8_t afPadding[2]; /*< Alignment padding. /
1068	} BS3CPUINSTR4_TEST1_VALUES_SS_T;
1069	AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1070	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1071	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1072	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1073	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1074	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1075	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1076	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1077	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1078
1079	/*
1080	* Test type #1.
1081	* Scalar quadruple-precision.
1082	*/
1083	typedef struct BS3CPUINSTR4_TEST1_VALUES_SQ_T
1084	{
1085	X86YMMFLOATSQREG uSrc2; /*< Second source operand. /
1086	X86YMMFLOATSQREG uSrc1; /*< uDstIn for SSE /
1087	X86YMMFLOATSQREG uDstOut; /*< Destination output. /
1088	uint32_t uMxCsr; /*< MXCSR to set prior to executing the instruction. /
1089	uint32_t u128ExpectedMxCsr; /*< Expected MXCSR for a 128-bit instruction. /
1090	uint32_t u256ExpectedMxCsr; /*< Expected MXCSR for a 256-bit instructions. /
1091	uint8_t f128FpXcptExpected; /*< Whether a floating-point exception is expected for a 128-bit instruction. /
1092	uint8_t f256FpXcptExpected; /*< Whether a floating-point exception is expected for a 256-bit instruction. /
1093	uint8_t afPadding[2]; /*< Alignment padding. /
1094	} BS3CPUINSTR4_TEST1_VALUES_SQ_T;
1095	AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SQ_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1096	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1097	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1098	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1099	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1100	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1101	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1102	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1103	AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1104
1105	typedef struct BS3CPUINSTR4_TEST1_T
1106	{
1107	FPFNBS3FAR pfnWorker; /*< Test function worker. /
1108	uint8_t bAvxMisalignXcpt; /*< AVX misalignment exception. /
1109	uint8_t enmRm; /*< R/M type. /
1110	uint8_t enmType; /*< CPU instruction type (see T_XXX). /
1111	uint8_t iRegDst; /*< Index of destination register, UINT8_MAX if N/A. /
1112	uint8_t iRegSrc1; /*< Index of first source register, UINT8_MAX if N/A. /
1113	uint8_t iRegSrc2; /*< Index of second source register, UINT8_MAX if N/A. /
1114	uint8_t cValues; /*< Number of test values in @c paValues. /
1115	BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR paValues; /< Test values. /
1116	} BS3CPUINSTR4_TEST1_T;
1117
1118	typedef struct BS3CPUINSTR4_TEST1_MODE_T
1119	{
1120	BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests;
1121	unsigned cTests;
1122	} BS3CPUINSTR4_TEST1_MODE_T;
1123
1124	/** Initializer for a BS3CPUINSTR4_TEST1_MODE_T array (three entries). */
1125	#define BS3CPUINSTR4_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
1126	{ { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
1127
1128	typedef struct BS3CPUINSTR4_TEST1_CTX_T
1129	{
1130	BS3CPUINSTR4_CONFIG_T const BS3_FAR pConfig; /< The test execution environment configuration. /
1131	BS3CPUINSTR4_TEST1_T const BS3_FAR pTest; /< The instruction being tested. /
1132	unsigned iVal; /*< Which iteration of the test value is this. /
1133	const char BS3_FAR pszMode; /< The testing mode (e.g. real, protected, paged and permutations). /
1134	PBS3TRAPFRAME pTrapFrame; /*< The exception (trap) frame. /
1135	PBS3REGCTX pCtx; /*< The general-purpose register context. /
1136	PBS3EXTCTX pExtCtx; /*< The extended (FPU) register context. /
1137	PBS3EXTCTX pExtCtxOut; /*< The output extended (FPU) register context. /
1138	uint8_t BS3_FAR puMemOp; /< The memory operand buffer. /
1139	uint8_t BS3_FAR puMemOpAlias; /< The memory operand alias buffer for comparing result. /
1140	uint8_t cbMemOp; /*< Size of the memory operand (and alias) buffer in bytes. /
1141	uint8_t cbOperand; /*< Size of the instruction operand (8 for MMX, 16 for SSE etc). /
1142	uint8_t cbInstr; /*< Size of the instruction opcode. /
1143	uint8_t bXcptExpect; /*< The expected exception while/after executing the instruction. /
1144	uint16_t idTestStep; /*< The test iteration step. /
1145	} BS3CPUINSTR4_TEST1_CTX_T;
1146	/** Pointer to a test 1 context. */
1147	typedef BS3CPUINSTR4_TEST1_CTX_T BS3_FAR *PBS3CPUINSTR4_TEST1_CTX_T;
1148
1149
1150	/**
1151	* Worker for bs3CpuInstr4_WorkerTestType1.
1152	*/
1153	static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
1154	PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
1155	{
1156	BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = pTestCtx->pTest;
1157	BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
1158	PBS3TRAPFRAME pTrapFrame = pTestCtx->pTrapFrame;
1159	PBS3REGCTX pCtx = pTestCtx->pCtx;
1160	PBS3EXTCTX pExtCtx = pTestCtx->pExtCtx;
1161	PBS3EXTCTX pExtCtxOut = pTestCtx->pExtCtxOut;
1162	uint8_t BS3_FAR *puMemOp = pTestCtx->puMemOp;
1163	uint8_t BS3_FAR *puMemOpAlias = pTestCtx->puMemOpAlias;
1164	uint8_t cbMemOp = pTestCtx->cbMemOp;
1165	uint8_t const cbOperand = pTestCtx->cbOperand;
1166	uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)pTestCtx->pTest->pfnWorker)[-1];
1167	uint8_t bXcptExpect = pTestCtx->bXcptExpect;
1168	uint8_t const bFpXcpt = pTestCtx->pConfig->fCr4OsXmmExcpt ? X86_XCPT_XF : X86_XCPT_UD;
1169	bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
1170	uint32_t uMxCsr;
1171	X86YMMREG MemOpExpect;
1172	uint16_t cErrors;
1173	uint32_t uExpectedMxCsr;
1174	bool fFpXcptExpected;
1175
1176	/*
1177	* An exception may be raised based on the test value (128 vs 256 bits).
1178	* In addition, we allow setting the exception flags (and mask) prior to
1179	* executing the instruction, so we cannot use the exception flags to figure
1180	* out if an exception will be raised. Hence, the input values provide us
1181	* explicitly whether an exception is expected for 128 and 256-bit variants.
1182	*/
1183	if (pTestCtx->cbOperand > 16)
1184	{
1185	uExpectedMxCsr = pValues->u256ExpectedMxCsr;
1186	fFpXcptExpected = pValues->f256FpXcptExpected;
1187	}
1188	else
1189	{
1190	uExpectedMxCsr = pValues->u128ExpectedMxCsr;
1191	fFpXcptExpected = pValues->f128FpXcptExpected;
1192	}
1193
1194	/*
1195	* Set up the context and some expectations.
1196	*/
1197	/* Destination. */
1198	Bs3MemZero(&MemOpExpect, sizeof(MemOpExpect));
1199	if (pTest->iRegDst == UINT8_MAX)
1200	{
1201	BS3_ASSERT(pTest->enmRm >= RM_MEM);
1202	Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp);
1203	if (bXcptExpect == X86_XCPT_DB)
1204	MemOpExpect.ymm = pValues->uDstOut.ymm;
1205	else
1206	Bs3MemSet(&MemOpExpect, 0xcc, sizeof(MemOpExpect));
1207	}
1208
1209	/* Source #1 (/ destination for SSE). */
1210	if (pTest->iRegSrc1 == UINT8_MAX)
1211	{
1212	BS3_ASSERT(pTest->enmRm >= RM_MEM);
1213	Bs3MemCpy(puMemOpAlias, &pValues->uSrc1, cbMemOp);
1214	if (pTest->iRegDst == UINT8_MAX)
1215	BS3_ASSERT(fSseInstr);
1216	else
1217	MemOpExpect.ymm = pValues->uSrc1.ymm;
1218	}
1219	else if (fSseInstr)
1220	Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm.DQWords.dqw0);
1221	else
1222	Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm, 32);
1223
1224	/* Source #2. */
1225	if (pTest->iRegSrc2 == UINT8_MAX)
1226	{
1227	BS3_ASSERT(pTest->enmRm >= RM_MEM);
1228	BS3_ASSERT(pTest->iRegDst != UINT8_MAX && pTest->iRegSrc1 != UINT8_MAX);
1229	Bs3MemCpy(puMemOpAlias, &pValues->uSrc2, cbMemOp);
1230	MemOpExpect.ymm = pValues->uSrc2.ymm;
1231	}
1232	else if (fSseInstr)
1233	Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm.DQWords.dqw0);
1234	else
1235	Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm, 32);
1236
1237	/* Memory pointer. */
1238	if (pTest->enmRm >= RM_MEM)
1239	{
1240	BS3_ASSERT( pTest->iRegDst == UINT8_MAX
1241	\|\| pTest->iRegSrc1 == UINT8_MAX
1242	\|\| pTest->iRegSrc2 == UINT8_MAX);
1243	Bs3RegCtxSetGrpSegFromCurPtr(pCtx, &pCtx->rbx, &pCtx->fs, puMemOp);
1244	}
1245
1246	/* Setup MXCSR for the current test. */
1247	uMxCsr = (pSavedCfg->uMxCsr & X86_MXCSR_MM) \| pValues->uMxCsr;
1248	BS3_ASSERT(!(uMxCsr & X86_MXCSR_MM));
1249	BS3_ASSERT(!(uMxCsr & X86_MXCSR_DAZ) \|\| g_fMxCsrDazSupported);
1250	Bs3ExtCtxSetMxCsr(pExtCtx, uMxCsr);
1251
1252	/*
1253	* Prepare globals and execute.
1254	*/
1255	g_uBs3TrapEipHint = pCtx->rip.u32;
1256	if ( bXcptExpect == X86_XCPT_DB
1257	&& !fFpXcptExpected)
1258	g_uBs3TrapEipHint += cbInstr + 1;
1259	Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut);
1260
1261	/*
1262	* Check the result.
1263	*
1264	* If a floating-point exception is expected, the destination is not updated by the instruction.
1265	* In the case of SSE instructions, updating the destination here will work because it is the same
1266	* as the source, but for AVX++ it won't because the destination is different and would contain 0s.
1267	*/
1268	cErrors = Bs3TestSubErrorCount();
1269	if ( bXcptExpect == X86_XCPT_DB
1270	&& !fFpXcptExpected
1271	&& pTest->iRegDst != UINT8_MAX)
1272	{
1273	if (fSseInstr)
1274	Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm.DQWords.dqw0);
1275	else
1276	Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm, cbOperand);
1277	}
1278	#if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */
1279	if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE
1280	&& pExtCtx->Ctx.x.Hdr.bmXState == 0x7
1281	&& pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3)
1282	pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7;
1283	#endif
1284	if (bXcptExpect == X86_XCPT_DB)
1285	Bs3ExtCtxSetMxCsr(pExtCtx, uExpectedMxCsr \| (pSavedCfg->uMxCsr & X86_MXCSR_MM));
1286	Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /fFlags/, pTestCtx->pszMode, pTestCtx->idTestStep);
1287
1288	if (bXcptExpect == X86_XCPT_DB)
1289	{
1290	uint32_t const uGotMxCsr = Bs3ExtCtxGetMxCsr(pExtCtxOut) & ~X86_MXCSR_MM;
1291
1292	/* Check if the SIMD FP exception flags and mask (or lack of) are as expected. */
1293	if (uGotMxCsr != uExpectedMxCsr)
1294	{
1295	char szExpectFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
1296	char szExpectMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
1297	char szExpectOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
1298	char szGotFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
1299	char szGotMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
1300	char szGotOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
1301	bs3CpuInstr4GetXcptFlags(&szExpectFlags[0], sizeof(szExpectFlags), uExpectedMxCsr);
1302	bs3CpuInstr4GetXcptMasks(&szExpectMasks[0], sizeof(szExpectMasks), uExpectedMxCsr);
1303	bs3CpuInstr4GetXcptOthers(&szExpectOthers[0], sizeof(szExpectOthers), uExpectedMxCsr);
1304	bs3CpuInstr4GetXcptFlags(&szGotFlags[0], sizeof(szGotFlags), uGotMxCsr);
1305	bs3CpuInstr4GetXcptMasks(&szGotMasks[0], sizeof(szGotMasks), uGotMxCsr);
1306	bs3CpuInstr4GetXcptOthers(&szGotOthers[0], sizeof(szGotOthers), uGotMxCsr);
1307	Bs3TestFailedF("Expected MXCSR %#RX32 (%s%s%s ) got MXCSR %#RX32 (%s%s%s )", uExpectedMxCsr,
1308	szExpectFlags, szExpectMasks, szExpectOthers, uGotMxCsr, szGotFlags, szGotMasks, szGotOthers);
1309	}
1310
1311	/* Check if the SIMD FP exception (or lack of) is as expected. */
1312	if (fFpXcptExpected)
1313	{
1314	if (pTrapFrame->bXcpt == bFpXcpt)
1315	{ /* likely */ }
1316	else
1317	Bs3TestFailedF("Expected floating-point xcpt %s, got %s", bs3CpuInstr4XcptName(bFpXcpt),
1318	bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1319	}
1320	else if (pTrapFrame->bXcpt == X86_XCPT_DB)
1321	{ /* likely */ }
1322	else
1323	Bs3TestFailedF("Expected no xcpt, got %s", bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1324	}
1325	/* Check if non-FP exception is as expected. */
1326	else if (pTrapFrame->bXcpt != bXcptExpect)
1327	Bs3TestFailedF("Expected xcpt %s, got %s", bs3CpuInstr4XcptName(bXcptExpect), bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1328
1329	/* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
1330	if (bMode == BS3_MODE_RM && (pCtx->rflags.u32 & X86_EFL_AC))
1331	{
1332	if (pTrapFrame->Ctx.rflags.u32 & X86_EFL_AC)
1333	Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", pTrapFrame->bXcpt);
1334	pTrapFrame->Ctx.rflags.u32 \|= X86_EFL_AC;
1335	}
1336	if (bXcptExpect == X86_XCPT_PF)
1337	pCtx->cr2.u = (uintptr_t)puMemOp;
1338	Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, bXcptExpect == X86_XCPT_DB && !fFpXcptExpected ? cbInstr + 1 : 0, 0 /cbSpAdjust/,
1339	(bXcptExpect == X86_XCPT_DB && !fFpXcptExpected) \|\| BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
1340	pTestCtx->pszMode, pTestCtx->idTestStep);
1341	pCtx->cr2.u = 0;
1342
1343	if ( pTest->enmRm >= RM_MEM
1344	&& Bs3MemCmp(puMemOpAlias, &MemOpExpect, cbMemOp) != 0)
1345	Bs3TestFailedF("Expected uMemOp %.Rhxs, got %.Rhxs", cbMemOp, &MemOpExpect, cbMemOp, puMemOpAlias);
1346
1347	return cErrors;
1348	}
1349
1350
1351	/**
1352	* Test type #1 worker.
1353	*/
1354	static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
1355	PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs)
1356	{
1357	BS3REGCTX Ctx;
1358	BS3TRAPFRAME TrapFrame;
1359	const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
1360	uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
1361	uint8_t BS3_FAR *pbBuf = g_pbBuf;
1362	uint32_t cbBuf = g_cbBuf;
1363	PBS3EXTCTX pExtCtxOut;
1364	PBS3EXTCTX pExtCtx = bs3CpuInstrXAllocExtCtxs(&pExtCtxOut);
1365	if (pExtCtx)
1366	{ /* likely */ }
1367	else
1368	return 0;
1369	if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
1370	{ /* likely */ }
1371	else
1372	{
1373	Bs3TestPrintf("Skipped due to ancient FPU state format\n");
1374	return 0;
1375	}
1376
1377	/* Ensure the structures are allocated before we sample the stack pointer. */
1378	Bs3MemSet(&Ctx, 0, sizeof(Ctx));
1379	Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
1380
1381	/*
1382	* Create test context.
1383	*/
1384	pbBuf = bs3CpuInstrXBufSetup(pbBuf, &cbBuf, bMode);
1385	Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
1386	bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx);
1387
1388	/*
1389	* Run the tests in all rings since alignment issues may behave
1390	* differently in ring-3 compared to ring-0.
1391	*/
1392	for (;;)
1393	{
1394	unsigned fPf = 0;
1395	do
1396	{
1397	unsigned iCfg;
1398	for (iCfg = 0; iCfg < cConfigs; iCfg++)
1399	{
1400	unsigned iTest;
1401	BS3CPUINSTRX_CONFIG_SAVED_T SavedCfg;
1402	if (!bs3CpuInstr4ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
1403	continue; /* unsupported config */
1404
1405	/*
1406	* Iterate the tests.
1407	*/
1408	for (iTest = 0; iTest < cTests; iTest++)
1409	{
1410	BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = &paTests[iTest];
1411	unsigned const cValues = pTest->cValues;
1412	bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
1413	bool const fAvxInstr = bs3CpuInstr4IsAvx(pTest->enmType);
1414	uint8_t const cbOperand = bs3CpuInstr4GetOperandSize(pTest->enmType);
1415	uint8_t const cbMemOp = bs3CpuInstrXMemOpSize(cbOperand, pTest->enmRm);
1416	uint8_t const cbAlign = cbMemOp;
1417	uint8_t BS3_FAR *puMemOp = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf);
1418	uint8_t *puMemOpAlias = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf];
1419	uint8_t bXcptExpect = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD
1420	: fSseInstr ? paConfigs[iCfg].bXcptSse
1421	: BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
1422	uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
1423	unsigned cRecompRuns = 0;
1424	unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues;
1425	unsigned iVal;
1426
1427	/* If testing unaligned memory accesses (or #PF), skip register-only tests. This
1428	allows setting bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
1429	if ( (pTest->enmRm == RM_REG \|\| pTest->enmRm == RM_MEM8)
1430	&& (!paConfigs[iCfg].fAligned \|\| paConfigs[iCfg].fAlignCheck \|\| fPf))
1431	continue;
1432
1433	/* #AC is only raised in ring-3. */
1434	if (bXcptExpect == X86_XCPT_AC)
1435	{
1436	if (bRing != 3)
1437	bXcptExpect = X86_XCPT_DB;
1438	else if (fAvxInstr)
1439	bXcptExpect = pTest->bAvxMisalignXcpt; /* they generally don't raise #AC */
1440	}
1441
1442	if (fPf && bXcptExpect == X86_XCPT_DB)
1443	bXcptExpect = X86_XCPT_PF;
1444
1445	Bs3RegCtxSetRipCsFromCurPtr(&Ctx, pTest->pfnWorker);
1446
1447	/*
1448	* Iterate the test values and do the actual testing.
1449	*/
1450	while (cRecompRuns < cMaxRecompRuns)
1451	{
1452	for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
1453	{
1454	uint16_t cErrors;
1455	BS3CPUINSTR4_TEST1_CTX_T TestCtx;
1456
1457	if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0))
1458	continue;
1459
1460	/*
1461	* If the hardware does not support DAZ bit skip test values that set it.
1462	*/
1463	if ( !g_fMxCsrDazSupported
1464	&& (pTest->paValues[iVal].uMxCsr & X86_MXCSR_DAZ))
1465	continue;
1466
1467	/*
1468	* Setup the test instruction context and pass it to the worker.
1469	* A few of these can be figured out by the worker but initializing
1470	* it outside the inner most loop is more optimal.
1471	*/
1472	TestCtx.pConfig = &paConfigs[iCfg];
1473	TestCtx.pTest = pTest;
1474	TestCtx.iVal = iVal;
1475	TestCtx.pszMode = pszMode;
1476	TestCtx.pTrapFrame = &TrapFrame;
1477	TestCtx.pCtx = &Ctx;
1478	TestCtx.pExtCtx = pExtCtx;
1479	TestCtx.pExtCtxOut = pExtCtxOut;
1480	TestCtx.puMemOp = (uint8_t *)puMemOp;
1481	TestCtx.puMemOpAlias = puMemOpAlias;
1482	TestCtx.cbMemOp = cbMemOp;
1483	TestCtx.cbOperand = cbOperand;
1484	TestCtx.bXcptExpect = bXcptExpect;
1485	TestCtx.idTestStep = idTestStep;
1486	cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
1487	if (cErrors != Bs3TestSubErrorCount())
1488	{
1489	if (paConfigs[iCfg].fAligned)
1490	Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, %s %u-bit)",
1491	Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
1492	bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), fSseInstr ? "SSE" : "AVX", cbOperand * 8);
1493	else
1494	Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, puMemOp=%p, EFLAGS=%#RX32, %s %u-bit)",
1495	Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
1496	bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), puMemOp,
1497	TrapFrame.Ctx.rflags.u32, fSseInstr ? "SSE" : "AVX", cbOperand * 8);
1498	Bs3TestPrintf("\n");
1499	}
1500	}
1501	}
1502	}
1503	bs3CpuInstrXConfigRestore(&SavedCfg, &Ctx, pExtCtx);
1504	}
1505	} while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode));
1506
1507	/*
1508	* Next ring.
1509	*/
1510	bRing++;
1511	if (bRing > 3 \|\| bMode == BS3_MODE_RM)
1512	break;
1513	Bs3RegCtxConvertToRingX(&Ctx, bRing);
1514	}
1515
1516	/*
1517	* Cleanup.
1518	*/
1519	bs3CpuInstrXBufCleanup(pbBuf, cbBuf, bMode);
1520	bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut);
1521	return 0;
1522	}
1523
1524
1525	/*
1526	* [V]ADDPS.
1527	*/
1528	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addps(uint8_t bMode)
1529	{
1530	static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
1531	{
1532	/*
1533	* Zero.
1534	*/
1535	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1536	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1537	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1538	/mxcsr:in / 0,
1539	/128:out / 0,
1540	/256:out / 0,
1541	/xcpt? / false, false },
1542	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1543	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1544	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1545	/mxcsr:in / 0,
1546	/128:out / 0,
1547	/256:out / 0,
1548	/xcpt? / false, false },
1549	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1550	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1551	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1552	/mxcsr:in / X86_MXCSR_RC_ZERO,
1553	/128:out / X86_MXCSR_RC_ZERO,
1554	/256:out / X86_MXCSR_RC_ZERO,
1555	/xcpt? / false, false },
1556	{ { /src2 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1557	{ /src1 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1558	{ /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1559	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
1560	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
1561	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
1562	/xcpt? / false, false },
1563	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1564	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1565	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1566	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1567	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1568	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1569	/xcpt? / false, false },
1570	{ { /src2 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1571	{ /src1 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1572	{ /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1573	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1574	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1575	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1576	/xcpt? / false, false },
1577	/*
1578	* Infinity.
1579	*/
1580	/* 6/{ { /src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1581	{ /src1 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1582	{ /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1583	/mxcsr:in / X86_MXCSR_IM,
1584	/128:out / X86_MXCSR_IM \| X86_MXCSR_IE,
1585	/256:out / X86_MXCSR_IM \| X86_MXCSR_IE,
1586	/xcpt? / false, false },
1587	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1588	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1589	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1590	/mxcsr:in / 0,
1591	/128:out / X86_MXCSR_IE,
1592	/256:out / X86_MXCSR_IE,
1593	/xcpt? / true, true },
1594	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
1595	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
1596	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
1597	/mxcsr:in / X86_MXCSR_FZ,
1598	/128:out / X86_MXCSR_FZ,
1599	/256:out / X86_MXCSR_FZ \| X86_MXCSR_IE,
1600	/xcpt? / false, true },
1601	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
1602	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
1603	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(0) } },
1604	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1605	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1606	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1607	/xcpt? / false, true },
1608	{ { /src2 / { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
1609	{ /src1 / { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
1610	{ /* => */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
1611	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
1612	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1613	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1614	/xcpt? / true, true },
1615	/*
1616	* Overflow, Precision.
1617	*/
1618	/11/{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1619	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1620	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), } },
1621	/mxcsr:in / 0,
1622	/128:out / 0,
1623	/256:out / X86_MXCSR_OE,
1624	/xcpt? / false, true },
1625	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } },
1626	{ /src1 / { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0) } },
1627	{ /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } },
1628	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO,
1629	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
1630	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
1631	/xcpt? / false, false },
1632	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
1633	{ /src1 / { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
1634	{ /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0) } },
1635	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1636	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_OE \| X86_MXCSR_PE,
1637	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_OE \| X86_MXCSR_PE,
1638	/xcpt? / false, false },
1639	{ { /src2 / { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
1640	{ /src1 / { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
1641	{ /* => */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },
1642	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1643	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_OE \| X86_MXCSR_PE,
1644	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_OE \| X86_MXCSR_PE,
1645	/xcpt? / false, false },
1646	{ { /src2 / { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1647	{ /src1 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1648	{ /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1649	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ,
1650	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ,
1651	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OE,
1652	/xcpt? / false, true },
1653	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1654	{ /src1 / { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1655	{ /* => */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1656	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO,
1657	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
1658	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
1659	/xcpt? / false, false },
1660	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
1661	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
1662	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_NORM_MAX(1), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1) } },
1663	/mxcsr:in / 0,
1664	/128:out / X86_MXCSR_PE,
1665	/256:out / X86_MXCSR_PE,
1666	/xcpt? / true, true },
1667	/*
1668	* Normals.
1669	*/
1670	/18/{ { /src2 / { FP32_V(0, 0x600000, 0x7f)/* 1.75/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/0.25/, FP32_V(0, 0x600000, 0x7f)/ 1.75/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/0.25*/ } },
1671	{ /src1 / { FP32_V(1, 0, 0x7d)/-0.25/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/0.50/, FP32_V(1, 0, 0x7d)/-0.25/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/0.50/ } },
1672	{ /* => / { FP32_V(0, 0x400000, 0x7f)/ 1.50/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/0.75/, FP32_V(0, 0x400000, 0x7f)/ 1.50/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/0.75*/ } },
1673	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1674	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1675	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1676	/xcpt? / false, false },
1677	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
1678	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0) } },
1679	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1680	/mxcsr:in / 0,
1681	/128:out / 0,
1682	/256:out / 0,
1683	/xcpt? / false, false },
1684	{ { /src2 / { FP32_V(0, 0x5ca5b8, 0x93)/1807543/, FP32_V(0, 0x5c0000, 0x84)/55/, FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/55/, FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_V(0, 0x534000, 0x86)/211.25/, FP32_0(0) } },
1685	{ /src1 / { FP32_V(0, 0x1ea980, 0x8f)/* 81235/, FP32_V(0, 0x600000, 0x81)/ 7/, FP32_V(0, 0x7c9000, 0x88)/ 1010.25/, FP32_0(0), FP32_V(0, 0x600000, 0x81)/ 7/, FP32_V(0, 0x7c9000, 0x88)/ 1010.25/, FP32_1(1) /- 1.00*/, FP32_0(0) } },
1686	{ /* => / { FP32_V(0, 0x669050, 0x93)/1888778/, FP32_V(0, 0x780000, 0x84)/62/, FP32_V(0, 0x253468, 0x93)/1353357.00/, FP32_0(0), FP32_V(0, 0x780000, 0x84)/62/, FP32_V(0, 0x253468, 0x93)/1353357.00/, FP32_V(0, 0x524000, 0x86)/210.25*/, FP32_0(0) } },
1687	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
1688	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
1689	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
1690	/xcpt? / false, false },
1691	{ { /src2 / { FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_V(0, 0x3c614e, 0x96)/12345678/, FP32_0(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_V(0, 0x3c614e, 0x96)/12345678/, FP32_1(1), FP32_0(0) } },
1692	{ /src1 / { FP32_V(1, 0x712060, 0x92)/- 987654/, FP32_V(0, 0x3c614e, 0x96)/12345678/, FP32_0(0), FP32_1(0), FP32_V(1, 0x712060, 0x92)/- 987654/, FP32_V(0, 0x3c614e, 0x96)/12345678/, FP32_1(0), FP32_1(0) } },
1693	{ /* => / { FP32_V(0, 0x6cb99c, 0x97)/31028024/, FP32_V(0, 0x3c614e, 0x97)/24691356/, FP32_0(0), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/31028024/, FP32_V(0, 0x3c614e, 0x97)/24691356*/, FP32_0(0), FP32_1(0) } },
1694	/mxcsr:in / X86_MXCSR_FZ,
1695	/128:out / X86_MXCSR_FZ,
1696	/256:out / X86_MXCSR_FZ,
1697	/xcpt? / false, false },
1698	{ { /src2 / { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } },
1699	{ /src1 / { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_0(1), FP32_0(0) } },
1700	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(1), FP32_0(0) } },
1701	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
1702	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
1703	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
1704	/xcpt? / false, false },
1705	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), } },
1706	{ /src1 / { FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), } },
1707	{ /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
1708	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1709	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1710	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1711	/xcpt? / false, false },
1712	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0) } },
1713	{ /src1 / { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0) } },
1714	{ /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } },
1715	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1716	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1717	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1718	/xcpt? / false, false },
1719	{ { /src2 / { FP32_V(0, 0x600000, 0x7e)/* 0.875/, FP32_V(0, 0x3ce348, 0x90)/193421.125/, FP32_V(0, 0x6423f2, 0x92)/934463.125/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/1234567.25/, FP32_V(0, 0x792318, 0x91)/510232.75/, FP32_V(0, 0x600000, 0x7e)/ 0.875*/ } },
1720	{ /src1 / { FP32_V(0, 0x769b50, 0x92)/1010101.000/, FP32_V(0, 0x430ebc, 0x91)/399477.875/, FP32_V(1, 0x0a19f0, 0x8f)/-70707.875/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/2109876.75/, FP32_V(1, 0x316740, 0x8e)/-45415.25/, FP32_V(0, 0x769b50, 0x92)/1010101.000/ } },
1721	{ /* => / { FP32_V(0, 0x769b5e, 0x92)/1010101.875/, FP32_V(0, 0x10c030, 0x92)/592899.000/, FP32_V(0, 0x52e0b4, 0x92)/863755.250/, FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/3344444.00/, FP32_V(0, 0x62f630, 0x91)/464817.50/, FP32_V(0, 0x769b5e, 0x92)/1010101.875*/ } },
1722	/mxcsr:in / X86_MXCSR_RC_DOWN,
1723	/128:out / X86_MXCSR_RC_DOWN,
1724	/256:out / X86_MXCSR_RC_DOWN,
1725	/xcpt? / false, false },
1726	/*
1727	* Denormals.
1728	*/
1729	/26/{ { /src2 / { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1730	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1731	{ /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1732	/mxcsr:in / 0,
1733	/128:out / X86_MXCSR_DE,
1734	/256:out / X86_MXCSR_DE,
1735	/xcpt? / true, true },
1736	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1737	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
1738	{ /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
1739	/mxcsr:in / X86_MXCSR_XCPT_MASK,
1740	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
1741	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
1742	/xcpt? / false, false },
1743	{ { /src2 / { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
1744	{ /src1 / { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
1745	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1746	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
1747	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
1748	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
1749	/xcpt? / false, false },
1750	{ { /src2 / { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1751	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1752	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1753	/mxcsr:in / 0,
1754	/128:out / X86_MXCSR_DE,
1755	/256:out / X86_MXCSR_DE,
1756	/xcpt? / true, true },
1757	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1758	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1759	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1760	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ,
1761	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ,
1762	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ,
1763	/xcpt? / false, false },
1764	{ { /src2 / { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
1765	{ /src1 / { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
1766	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1767	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1768	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1769	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1770	/xcpt? / false, false },
1771	/** @todo More Denormals. */
1772	/*
1773	* Invalids.
1774	*/
1775	/32/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1776	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1777	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1778	/mxcsr:in / X86_MXCSR_XCPT_MASK,
1779	/128:out / X86_MXCSR_XCPT_MASK,
1780	/256:out / X86_MXCSR_XCPT_MASK,
1781	/xcpt? / false, false },
1782	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1783	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
1784	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1785	/mxcsr:in / X86_MXCSR_XCPT_MASK,
1786	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
1787	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
1788	/xcpt? / false, false },
1789	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
1790	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1791	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1792	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
1793	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
1794	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
1795	/xcpt? / false, false },
1796	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
1797	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
1798	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
1799	/mxcsr:in / X86_MXCSR_XCPT_MASK,
1800	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
1801	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
1802	/xcpt? / false, false },
1803	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1804	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1805	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1806	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS,
1807	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS,
1808	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS,
1809	/xcpt? / false, false },
1810	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
1811	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1812	{ /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1813	/mxcsr:in / X86_MXCSR_XCPT_MASK,
1814	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
1815	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
1816	/xcpt? / false, false },
1817	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1818	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1819	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1820	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1821	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1822	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1823	/xcpt? / false, false },
1824	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1825	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
1826	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1827	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1828	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1829	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1830	/xcpt? / true, true },
1831	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
1832	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1833	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1834	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1835	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
1836	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
1837	/xcpt? / true, true },
1838	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
1839	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
1840	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
1841	/mxcsr:in / X86_MXCSR_RC_UP,
1842	/128:out / X86_MXCSR_RC_UP \| X86_MXCSR_IE,
1843	/256:out / X86_MXCSR_RC_UP \| X86_MXCSR_IE,
1844	/xcpt? / true, true },
1845	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1846	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1847	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1848	/mxcsr:in / 0,
1849	/128:out / 0,
1850	/256:out / 0,
1851	/xcpt? / false, false },
1852	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
1853	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1854	{ /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1855	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
1856	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1857	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1858	/xcpt? / true, true },
1859	/** @todo Underflow, Precision; Rounding, FZ etc. */
1860	};
1861
1862	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
1863	{
1864	{ bs3CpuInstr4_addps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1865	{ bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1866
1867	{ bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1868	{ bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1869
1870	{ bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1871	{ bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1872	};
1873	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
1874	{
1875	{ bs3CpuInstr4_addps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1876	{ bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1877
1878	{ bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1879	{ bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1880
1881	{ bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1882	{ bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1883	};
1884	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
1885	{
1886	{ bs3CpuInstr4_addps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1887	{ bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1888
1889	{ bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1890	{ bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1891
1892	{ bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1893	{ bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1894
1895	{ bs3CpuInstr4_addps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1896	{ bs3CpuInstr4_addps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1897
1898	{ bs3CpuInstr4_vaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1899	{ bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1900	};
1901
1902	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1903	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
1904	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1905	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
1906	}
1907
1908
1909	/*
1910	* [V]ADDPD.
1911	*/
1912	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addpd(uint8_t bMode)
1913	{
1914	static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
1915	{
1916	/*
1917	* Zero.
1918	*/
1919	/* 0/{ { /src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1920	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1921	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1922	/mxcsr:in / X86_MXCSR_XCPT_MASK,
1923	/128:out / X86_MXCSR_XCPT_MASK,
1924	/256:out / X86_MXCSR_XCPT_MASK,
1925	/xcpt? / false, false },
1926	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1927	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1928	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1929	/mxcsr:in / X86_MXCSR_FZ,
1930	/128:out / X86_MXCSR_FZ,
1931	/256:out / X86_MXCSR_FZ,
1932	/xcpt? / false, false },
1933	{ { /src2 / { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1934	{ /src1 / { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1935	{ /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1936	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_DOWN,
1937	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_DOWN,
1938	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_DOWN,
1939	/xcpt? / false, false },
1940	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1941	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1942	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1943	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ,
1944	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ,
1945	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ,
1946	/xcpt? / false, false },
1947	{ { /src2 / { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1948	{ /src1 / { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1949	{ /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1950	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1951	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1952	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
1953	/xcpt? / false, false },
1954	/*
1955	* Infinity.
1956	*/
1957	/* 5/{ { /src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1958	{ /src1 / { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
1959	{ /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
1960	/mxcsr:in / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM,
1961	/128:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_IE,
1962	/256:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_IE,
1963	/xcpt? / true, true },
1964	{ { /src2 / { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } },
1965	{ /src1 / { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
1966	{ /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
1967	/mxcsr:in / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
1968	/128:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_IE,
1969	/256:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_IE,
1970	/xcpt? / true, true },
1971	{ { /src2 / { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } },
1972	{ /src1 / { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
1973	{ /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
1974	/mxcsr:in / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
1975	/128:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
1976	/256:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
1977	/xcpt? / true, true },
1978	{ { /src2 / { FP64_INF(0), FP64_INF(1), FP64_0(0), FP64_INF(1) } },
1979	{ /src1 / { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } },
1980	{ /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } },
1981	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
1982	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1983	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1984	/xcpt? / false, false },
1985	{ { /src2 / { FP64_V(0, 0, 0x3fd)/0.25/, FP64_0(1), FP64_0(0), FP64_INF(1) } },
1986	{ /src1 / { FP64_V(0, 0, 0x3fe)/0.50/, FP64_0(1), FP64_0(0), FP64_INF(0) } },
1987	{ /* => / { FP64_V(0, 0x8000000000000, 0x3fe)/0.75*/, FP64_0(1), FP64_0(0), FP64_QNAN(1) } },
1988	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
1989	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
1990	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
1991	/xcpt? / false, false },
1992	/*
1993	* Overflow, Precision.
1994	*/
1995	/10/{ { /src2 / { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } },
1996	{ /src1 / { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } },
1997	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1998	/mxcsr:in / 0,
1999	/128:out / X86_MXCSR_OE,
2000	/256:out / X86_MXCSR_OE,
2001	/xcpt? / true, true },
2002	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } },
2003	{ /src1 / { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } },
2004	{ /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } },
2005	/mxcsr:in / 0,
2006	/128:out / X86_MXCSR_OE,
2007	/256:out / X86_MXCSR_OE,
2008	/xcpt? / true, true },
2009	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
2010	{ /src1 / { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
2011	{ /* => */ { FP64_INF(0), FP64_V(1, 0, 2), FP64_0(0), FP64_INF(0) } },
2012	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ,
2013	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OE \| X86_MXCSR_PE,
2014	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OE \| X86_MXCSR_PE,
2015	/xcpt? / false, false },
2016	{ { /src2 / { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
2017	{ /src1 / { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },
2018	{ /* => */ { FP64_V(1, 0, 2), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2019	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_FZ,
2020	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_FZ \| X86_MXCSR_OE \| X86_MXCSR_PE,
2021	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_FZ \| X86_MXCSR_OE \| X86_MXCSR_PE,
2022	/xcpt? / false, false },
2023	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2024	{ /src1 / { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2025	{ /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2026	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2027	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
2028	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
2029	/xcpt? / false, false },
2030	{ { /src2 / { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },
2031	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },
2032	{ /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } },
2033	/mxcsr:in / X86_MXCSR_RC_ZERO,
2034	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2035	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2036	/xcpt? / true, true },
2037	/** @todo Why does the below on cause PE?! */
2038	{ { /src2 / { FP64_V(0, 0xc000000000000, 0x3ff)/* 1.75/, FP64_NORM_MAX(0), FP64_0(0), FP64_V(0, 0, 0x3fd)/0.25*/ } },
2039	{ /src1 / { FP64_V(1, 0, 0x07d)/-0.25/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0, 0x3fe)/0.50/ } },
2040	{ /* => / { FP64_V(0, 0xbffffffffffff, 0x3ff)/ 1.50/, FP64_0(1), FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/0.75*/ } },
2041	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2042	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_PE,
2043	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_PE,
2044	/xcpt? / false, false },
2045	/*
2046	* Normals.
2047	*/
2048	/17/{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } },
2049	{ /src1 / { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_0(0) } },
2050	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2051	/mxcsr:in / 0,
2052	/128:out / 0,
2053	/256:out / 0,
2054	/xcpt? / false, false },
2055	{ { /src2 / { FP64_V(0, 0, 0x409)/1024/, FP64_V(0, 0xb800000000000, 0x404)/55/, FP64_0(0), FP64_0(0) } },
2056	{ /src1 / { FP64_V(0, 0, 0x408)/* 512/, FP64_V(0, 0xc000000000000, 0x401)/ 7*/, FP64_0(0), FP64_0(0) } },
2057	{ /* => / { FP64_V(0, 0x8000000000000, 0x409)/1536/, FP64_V(0, 0xf000000000000, 0x404)/62*/, FP64_0(0), FP64_0(0) } },
2058	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2059	/128:out / X86_MXCSR_XCPT_MASK,
2060	/256:out / X86_MXCSR_XCPT_MASK,
2061	/xcpt? / false, false },
2062	{ { /src2 / { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890/, FP64_V(0, 0xd6f3458800000, 0x41c)/987654321/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/4072598000007579.5*/ } },
2063	{ /src1 / { FP64_V(1, 0x26580b4800000, 0x41d)/-1234567890/, FP64_V(1, 0x9000000000000, 0x405)/* -100/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/ 123450000.5*/ } },
2064	{ /* => / { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/987654221/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/4072598123457580.0*/ } },
2065	/mxcsr:in / 0,
2066	/128:out / 0,
2067	/256:out / 0,
2068	/xcpt? / false, false },
2069	{ { /src2 / { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } },
2070	{ /src1 / { FP64_1(0), FP64_1(1), FP64_0(0), FP64_0(0) } },
2071	{ /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
2072	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2073	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2074	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2075	/xcpt? / false, false },
2076	{ { /src2 / { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_0(0), FP64_0(0) } },
2077	{ /src1 / { FP64_1(0), FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_0(0) } },
2078	{ /* => */ { FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_0(0), FP64_0(0) } },
2079	/mxcsr:in / X86_MXCSR_FZ,
2080	/128:out / X86_MXCSR_FZ,
2081	/256:out / X86_MXCSR_FZ,
2082	/xcpt? / false, false },
2083	{ { /src2 / { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
2084	{ /src1 / { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },
2085	{ /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2) } },
2086	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2087	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2088	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2089	/xcpt? / false, false },
2090	{ { /src2 / { FP64_V(0, 0xc122186c3cfd0, 0x42d)/123456789876543.25/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
2091	{ /src1 / { FP64_V(0, 0xb88e0395d49b0, 0x42d)/121098765432102.75/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
2092	{ /* => / { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2) } },
2093	/mxcsr:in / X86_MXCSR_RC_UP,
2094	/128:out / X86_MXCSR_RC_UP,
2095	/256:out / X86_MXCSR_RC_UP,
2096	/xcpt? / false, false },
2097	/*
2098	* Denormals.
2099	*/
2100	/24/{ { /src2 / { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2101	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2102	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2103	/mxcsr:in / 0,
2104	/128:out / X86_MXCSR_DE,
2105	/256:out / X86_MXCSR_DE,
2106	/xcpt? / true, true },
2107	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2108	{ /src1 / { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
2109	{ /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
2110	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2111	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
2112	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
2113	/xcpt? / false, false },
2114	{ { /src2 / { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
2115	{ /src1 / { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
2116	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2117	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2118	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2119	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2120	/xcpt? / false, false },
2121	/** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
2122	/*
2123	* Invalids.
2124	*/
2125	/27/{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2126	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2127	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2128	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2129	/128:out / X86_MXCSR_XCPT_MASK,
2130	/256:out / X86_MXCSR_XCPT_MASK,
2131	/xcpt? / false, false },
2132	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2133	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2134	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2135	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2136	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2137	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2138	/xcpt? / false, false },
2139	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2140	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2141	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2142	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2143	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2144	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2145	/xcpt? / false, false },
2146	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2147	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
2148	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
2149	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2150	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2151	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2152	/xcpt? / false, false },
2153	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2154	{ /src1 / { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
2155	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2156	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2157	/128:out / X86_MXCSR_XCPT_MASK,
2158	/256:out / X86_MXCSR_XCPT_MASK,
2159	/xcpt? / false, false },
2160	{ { /src2 / { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2161	{ /src1 / { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
2162	{ /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2163	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2164	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2165	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2166	/xcpt? / false, false },
2167	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2168	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2169	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2170	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2171	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2172	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2173	/xcpt? / false, false },
2174	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
2175	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
2176	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
2177	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2178	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2179	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2180	/xcpt? / true, true },
2181	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2182	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2183	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2184	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2185	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2186	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2187	/xcpt? / true, true },
2188	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2189	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
2190	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2191	/mxcsr:in / X86_MXCSR_RC_UP,
2192	/128:out / X86_MXCSR_RC_UP \| X86_MXCSR_IE,
2193	/256:out / X86_MXCSR_RC_UP \| X86_MXCSR_IE,
2194	/xcpt? / true, true },
2195	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2196	{ /src1 / { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
2197	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2198	/mxcsr:in / X86_MXCSR_RC_DOWN,
2199	/128:out / X86_MXCSR_RC_DOWN,
2200	/256:out / X86_MXCSR_RC_DOWN,
2201	/xcpt? / false, false },
2202	{ { /src2 / { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2203	{ /src1 / { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
2204	{ /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2205	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2206	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2207	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2208	/xcpt? / true, true },
2209	};
2210
2211	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2212	{
2213	{ bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2214	{ bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2215
2216	{ bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2217	{ bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2218
2219	{ bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2220	{ bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2221	};
2222	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2223	{
2224	{ bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2225	{ bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2226
2227	{ bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2228	{ bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2229
2230	{ bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2231	{ bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2232	};
2233	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2234	{
2235	{ bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2236	{ bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2237
2238	{ bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2239	{ bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2240
2241	{ bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2242	{ bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2243
2244	{ bs3CpuInstr4_addpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2245	{ bs3CpuInstr4_addpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2246
2247	{ bs3CpuInstr4_vaddpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2248	{ bs3CpuInstr4_vaddpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2249	};
2250
2251	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2252	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2253	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2254	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
2255	}
2256
2257
2258	/*
2259	* [V]ADDSS.
2260	*/
2261	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addss(uint8_t bMode)
2262	{
2263	static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
2264	{
2265	/*
2266	* Zero.
2267	*/
2268	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2269	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2270	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2271	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2272	/128:out / X86_MXCSR_XCPT_MASK,
2273	/256:out / X86_MXCSR_XCPT_MASK,
2274	/xcpt? / false, false },
2275	{ { /src2 / { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2276	{ /src1 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2277	{ /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2278	/mxcsr:in / 0,
2279	/128:out / 0,
2280	/256:out / 0,
2281	/xcpt? / false, false },
2282	{ { /src2 / { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2283	{ /src1 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2284	{ /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2285	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2286	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2287	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2288	/xcpt? / false, false },
2289	{ { /src2 / { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2290	{ /src1 / { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2291	{ /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2292	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2293	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2294	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2295	/xcpt? / false, false },
2296	{ { /src2 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2297	{ /src1 / { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2298	{ /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2299	/mxcsr:in / X86_MXCSR_FZ,
2300	/128:out / X86_MXCSR_FZ,
2301	/256:out / X86_MXCSR_FZ,
2302	/xcpt? / false, false },
2303	{ { /src2 / { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2304	{ /src1 / { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2305	{ /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2306	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_DOWN,
2307	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_DOWN,
2308	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_DOWN,
2309	/xcpt? / false, false },
2310	/*
2311	* Infinity.
2312	*/
2313	/* 6/{ { /src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2314	{ /src1 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2315	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2316	/mxcsr:in / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM,
2317	/128:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_IE,
2318	/256:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_IE,
2319	/xcpt? / true, true },
2320	{ { /src2 / { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2321	{ /src1 / { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2322	{ /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2323	/mxcsr:in / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO,
2324	/128:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2325	/256:out / X86_MXCSR_DM \| X86_MXCSR_ZM \| X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2326	/xcpt? / true, true },
2327	{ { /src2 / { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2328	{ /src1 / { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2329	{ /* => */ { FP32_QNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2330	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_DOWN,
2331	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_DOWN \| X86_MXCSR_IE,
2332	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_DOWN \| X86_MXCSR_IE,
2333	/xcpt? / false, false },
2334	{ { /src2 / { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2335	{ /src1 / { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2336	{ /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2337	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
2338	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
2339	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
2340	/xcpt? / false, false },
2341	{ { /src2 / { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2342	{ /src1 / { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2343	{ /* => */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2344	/mxcsr:in / X86_MXCSR_FZ,
2345	/128:out / X86_MXCSR_FZ \| X86_MXCSR_IE,
2346	/256:out / X86_MXCSR_FZ \| X86_MXCSR_IE,
2347	/xcpt? / true, true },
2348	{ { /src2 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
2349	{ /src1 / { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2350	{ /* => */ { FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2351	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2352	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2353	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2354	/xcpt? / true, true },
2355	/*
2356	* Overflow, Precision.
2357	*/
2358	/12/{ { /src2 / { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
2359	{ /src1 / { FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2360	{ /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2361	/mxcsr:in / 0,
2362	/128:out / X86_MXCSR_OE,
2363	/256:out / X86_MXCSR_OE,
2364	/xcpt? / true, true },
2365	{ { /src2 / { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2366	{ /src1 / { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2367	{ /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2368	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM,
2369	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
2370	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
2371	/xcpt? / false, false },
2372	{ { /src2 / { FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2373	{ /src1 / { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2374	{ /* => */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2375	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OM \| X86_MXCSR_PM,
2376	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_PE,
2377	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_PE,
2378	/xcpt? / false, false },
2379	{ { /src2 / { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2380	{ /src1 / { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2381	{ /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2382	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM,
2383	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
2384	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
2385	/xcpt? / false, false },
2386	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
2387	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2388	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2389	/mxcsr:in / X86_MXCSR_RC_ZERO,
2390	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2391	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2392	/xcpt? / true, true },
2393	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2394	{ /src1 / { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2395	{ /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2396	/mxcsr:in / X86_MXCSR_RC_ZERO,
2397	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2398	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2399	/xcpt? / true, true },
2400	/*
2401	* Normals.
2402	*/
2403	/18/{ { /src2 / { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2404	{ /src1 / { FP32_V(1, 0, 0x7d)/-0.25/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2405	{ /* => / { FP32_V(0, 0x400000, 0x7f)/ 1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2406	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2407	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2408	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2409	/xcpt? / false, false },
2410	{ { /src2 / { FP32_NORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
2411	{ /src1 / { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2412	{ /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2413	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2414	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2415	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2416	/xcpt? / false, false },
2417	{ { /src2 / { FP32_V(0, 0x5ca5b8, 0x93)/1807543/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2418	{ /src1 / { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2419	{ /* => / { FP32_V(0, 0x669050, 0x93)/1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2420	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2421	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2422	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2423	/xcpt? / false, false },
2424	{ { /src2 / { FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2425	{ /src1 / { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2426	{ /* => / { FP32_V(0, 0x253468, 0x93)/1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2427	/mxcsr:in / 0,
2428	/128:out / 0,
2429	/256:out / 0,
2430	/xcpt? / false, false },
2431	{ { /src2 / { FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2432	{ /src1 / { FP32_V(1, 0x712060, 0x92)/- 987654/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2433	{ /* => / { FP32_V(0, 0x6cb99c, 0x97)/31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2434	/mxcsr:in / X86_MXCSR_RC_ZERO,
2435	/128:out / X86_MXCSR_RC_ZERO,
2436	/256:out / X86_MXCSR_RC_ZERO,
2437	/xcpt? / false, false },
2438	{ { /src2 / { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2439	{ /src1 / { FP32_1(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2440	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2441	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2442	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2443	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2444	/xcpt? / false, false },
2445	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2446	{ /src1 / { FP32_1(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2447	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2448	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2449	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2450	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2451	/xcpt? / false, false },
2452	{ { /src2 / { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2453	{ /src1 / { FP32_V(0, 0x769b50, 0x92)/1010101.000/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2454	{ /* => / { FP32_V(0, 0x769b5e, 0x92)/1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2455	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2456	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2457	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2458	/xcpt? / false, false },
2459	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
2460	{ /src1 / { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2461	{ /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2462	/mxcsr:in / X86_MXCSR_FZ,
2463	/128:out / X86_MXCSR_FZ,
2464	/256:out / X86_MXCSR_FZ,
2465	/xcpt? / false, false },
2466	/*
2467	* Denormals.
2468	*/
2469	/27/{ { /src2 / { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
2470	{ /src1 / { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
2471	{ /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
2472	/mxcsr:in / X86_MXCSR_DE,
2473	/128:out / X86_MXCSR_DE,
2474	/256:out / X86_MXCSR_DE,
2475	/xcpt? / true, true },
2476	{ { /src2 / { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
2477	{ /src1 / { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2478	{ /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2479	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2480	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2481	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2482	/xcpt? / false, false },
2483	{ { /src2 / { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
2484	{ /src1 / { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
2485	{ /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
2486	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_DE,
2487	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_DE,
2488	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_DE,
2489	/xcpt? / true, true },
2490	/** @todo More denormals etc. */
2491	/*
2492	* Invalids.
2493	*/
2494	/* QNan, QNan (Masked). */
2495	/30/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2496	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2497	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2498	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2499	/128:out / X86_MXCSR_XCPT_MASK,
2500	/256:out / X86_MXCSR_XCPT_MASK,
2501	/xcpt? / false, false },
2502	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2503	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2504	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2505	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2506	/128:out / X86_MXCSR_XCPT_MASK,
2507	/256:out / X86_MXCSR_XCPT_MASK,
2508	/xcpt? / false, false },
2509	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2510	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2511	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2512	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2513	/128:out / X86_MXCSR_XCPT_MASK,
2514	/256:out / X86_MXCSR_XCPT_MASK,
2515	/xcpt? / false, false },
2516	/* QNan, SNan (Masked). */
2517	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2518	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2519	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2520	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2521	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2522	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2523	/xcpt? / false, false },
2524	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2525	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2526	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2527	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2528	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2529	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2530	/xcpt? / false, false },
2531	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2532	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2533	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2534	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2535	/128:out / X86_MXCSR_XCPT_MASK,
2536	/256:out / X86_MXCSR_XCPT_MASK,
2537	/xcpt? / false, false },
2538	/* SNan, QNan (Masked). */
2539	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2540	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2541	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2542	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2543	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2544	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2545	/xcpt? / false, false },
2546	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2547	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2548	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2549	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2550	/128:out / X86_MXCSR_XCPT_MASK,
2551	/256:out / X86_MXCSR_XCPT_MASK,
2552	/xcpt? / false, false },
2553	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2554	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2555	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2556	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2557	/128:out / X86_MXCSR_XCPT_MASK,
2558	/256:out / X86_MXCSR_XCPT_MASK,
2559	/xcpt? / false, false },
2560	/* SNan, SNan (Masked). */
2561	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2562	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2563	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2564	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2565	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2566	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2567	/xcpt? / false, false },
2568	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2569	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2570	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2571	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2572	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2573	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2574	/xcpt? / false, false },
2575	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2576	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2577	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2578	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2579	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2580	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2581	/xcpt? / false, false },
2582	/* QNan, Norm FP (Masked). */
2583	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
2584	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2585	{ /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2586	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2587	/128:out / X86_MXCSR_XCPT_MASK,
2588	/256:out / X86_MXCSR_XCPT_MASK,
2589	/xcpt? / false, false },
2590	/* SNan, Norm FP (Masked). */
2591	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
2592	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2593	{ /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2594	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2595	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2596	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2597	/xcpt? / false, false },
2598	/* QNan, QNan (Unmasked). */
2599	/44/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2600	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2601	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2602	/mxcsr:in / 0,
2603	/128:out / 0,
2604	/256:out / 0,
2605	/xcpt? / false, false },
2606	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2607	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2608	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2609	/mxcsr:in / 0,
2610	/128:out / 0,
2611	/256:out / 0,
2612	/xcpt? / false, false },
2613	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2614	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2615	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2616	/mxcsr:in / 0,
2617	/128:out / 0,
2618	/256:out / 0,
2619	/xcpt? / false, false },
2620
2621	/* QNan, SNan (Unmasked). */
2622	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2623	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2624	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2625	/mxcsr:in / 0,
2626	/128:out / X86_MXCSR_IE,
2627	/256:out / X86_MXCSR_IE,
2628	/xcpt? / true, true },
2629	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2630	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2631	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2632	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2633	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_IE,
2634	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN \| X86_MXCSR_IE,
2635	/xcpt? / true, true },
2636	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2637	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2638	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2639	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2640	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2641	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2642	/xcpt? / false, false },
2643	/* SNan, QNan (Unmasked). */
2644	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2645	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2646	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2647	/mxcsr:in / X86_MXCSR_DAZ,
2648	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_IE,
2649	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_IE,
2650	/xcpt? / true, true },
2651	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2652	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2653	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2654	/mxcsr:in / X86_MXCSR_RC_UP,
2655	/128:out / X86_MXCSR_RC_UP,
2656	/256:out / X86_MXCSR_RC_UP,
2657	/xcpt? / false, false },
2658	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2659	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2660	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2661	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2662	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2663	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2664	/xcpt? / false, false },
2665	/* SNan, SNan (Unmasked). */
2666	/54/{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2667	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2668	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2669	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ,
2670	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_IE,
2671	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_IE,
2672	/xcpt? / true, true },
2673	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2674	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2675	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2676	/mxcsr:in / X86_MXCSR_RC_ZERO,
2677	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2678	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2679	/xcpt? / true, true },
2680	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2681	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2682	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2683	/mxcsr:in / 0,
2684	/128:out / X86_MXCSR_IE,
2685	/256:out / X86_MXCSR_IE,
2686	/xcpt? / true, true },
2687	/* QNan, Norm FP (Unmasked). */
2688	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
2689	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2690	{ /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2691	/mxcsr:in / X86_MXCSR_FZ,
2692	/128:out / X86_MXCSR_FZ,
2693	/256:out / X86_MXCSR_FZ,
2694	/xcpt? / false, false },
2695	/* SNan, Norm FP (Unmasked). */
2696	/58/{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
2697	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2698	{ /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2699	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2700	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2701	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
2702	/xcpt? / true, true },
2703	/** @todo Underflow, Precision; Rounding, FZ etc. */
2704	};
2705
2706	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2707	{
2708	{ bs3CpuInstr4_addss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2709	{ bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2710
2711	{ bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2712	{ bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2713	};
2714	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2715	{
2716	{ bs3CpuInstr4_addss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2717	{ bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2718
2719	{ bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2720	{ bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2721	};
2722	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2723	{
2724	{ bs3CpuInstr4_addss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2725	{ bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2726
2727	{ bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2728	{ bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2729
2730	{ bs3CpuInstr4_addss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2731	{ bs3CpuInstr4_addss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2732	};
2733
2734	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2735	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2736	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2737	g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
2738	}
2739
2740
2741	/*
2742	* [V]HADDPS.
2743	*/
2744	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddps(uint8_t bMode)
2745	{
2746	static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
2747	{
2748	/*
2749	* Zero.
2750	*/
2751	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2752	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2753	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2754	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2755	/128:out / X86_MXCSR_XCPT_MASK,
2756	/256:out / X86_MXCSR_XCPT_MASK,
2757	/xcpt? / false, false },
2758	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2759	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2760	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2761	/mxcsr:in / 0,
2762	/128:out / 0,
2763	/256:out / 0,
2764	/xcpt? / false, false },
2765	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2766	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2767	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2768	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2769	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2770	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
2771	/xcpt? / false, false },
2772	{ { /src2 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
2773	{ /src1 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
2774	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2775	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2776	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2777	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
2778	/xcpt? / false, false },
2779	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
2780	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
2781	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
2782	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2783	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2784	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
2785	/xcpt? / false, false },
2786	{ { /src2 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
2787	{ /src1 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
2788	{ /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
2789	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2790	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2791	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2792	/xcpt? / false, false },
2793	/*
2794	* Infinity.
2795	*/
2796	/* 6/{ { /src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
2797	{ /src1 / { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0) } },
2798	{ /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1) } },
2799	/mxcsr:in / X86_MXCSR_IM,
2800	/128:out / X86_MXCSR_IM \| X86_MXCSR_IE,
2801	/256:out / X86_MXCSR_IM \| X86_MXCSR_IE,
2802	/xcpt? / false, false },
2803	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
2804	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
2805	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
2806	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2807	/128:out / X86_MXCSR_XCPT_MASK,
2808	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
2809	/xcpt? / false, false },
2810	{ { /src2 / { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
2811	{ /src1 / { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
2812	{ /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
2813	/mxcsr:in / X86_MXCSR_FZ,
2814	/128:out / X86_MXCSR_FZ \| X86_MXCSR_IE,
2815	/256:out / X86_MXCSR_FZ \| X86_MXCSR_IE,
2816	/xcpt? / true, true },
2817	{ { /src2 / { FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0) } },
2818	{ /src1 / { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2819	{ /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0) } },
2820	/mxcsr:in / 0,
2821	/128:out / 0,
2822	/256:out / 0,
2823	/xcpt? / false, false },
2824	{ { /src2 / { FP32_INF(0), FP32_QNAN(1), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
2825	{ /src1 / { FP32_INF(0), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } },
2826	{ /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
2827	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2828	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2829	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2830	/xcpt? / false, false },
2831	/*
2832	* Overflow, Precision.
2833	*/
2834	/11/{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
2835	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
2836	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2837	/mxcsr:in / 0,
2838	/128:out / 0,
2839	/256:out / X86_MXCSR_OE,
2840	/xcpt? / false, true },
2841	{ { /src2 / { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2842	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2843	{ /* => */ { FP32_INF(1), FP32_INF(1), FP32_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2844	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM,
2845	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
2846	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
2847	/xcpt? / false, false },
2848	{ { /src2 / { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
2849	{ /src1 / { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
2850	{ /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
2851	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO,
2852	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
2853	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
2854	/xcpt? / false, false },
2855	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
2856	{ /src1 / { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1) } },
2857	{ /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0), FP32_NORM_MAX(0) } },
2858	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_UP,
2859	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_UP \| X86_MXCSR_OE \| X86_MXCSR_PE,
2860	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_UP \| X86_MXCSR_OE \| X86_MXCSR_PE,
2861	/xcpt? / false, false },
2862	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
2863	{ /src1 / { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
2864	{ /* => */ { FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(0) } },
2865	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO,
2866	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
2867	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OE \| X86_MXCSR_PE,
2868	/xcpt? / false, false },
2869	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
2870	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
2871	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } },
2872	/mxcsr:in / X86_MXCSR_RC_ZERO,
2873	/128:out / X86_MXCSR_RC_ZERO,
2874	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_OE,
2875	/xcpt? / false, true },
2876	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
2877	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
2878	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } },
2879	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2880	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2881	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
2882	/xcpt? / false, false },
2883	/*
2884	* Normals.
2885	*/
2886	/18/{ { /src2 / { FP32_V(0, 0, 0x7d)/* 0.25/, FP32_V(0, 0, 0x7e)/0.50/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7f)/1.50/, FP32_V(0, 0, 0x7d)/0.25*/ } },
2887	{ /src1 / { FP32_V(1, 0, 0x7d)/-0.25/, FP32_V(0, 0x600000, 0x7f)/1.75/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/0.50/, FP32_V(0, 0, 0x7d)/0.25/, FP32_0(0), FP32_0(0) } },
2888	{ /* => / { FP32_V(0, 0x400000, 0x7f)/ 1.50/, FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7e)/0.75/, FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7e)/0.75/, FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x600000, 0x7f)/1.75*/ } },
2889	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2890	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2891	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
2892	/xcpt? / false, false },
2893	{ { /src2 / { FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V4(1), FP32_NORM_V4(0), FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V2(0) } },
2894	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_V3(0), FP32_NORM_V3(1) } },
2895	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2896	/mxcsr:in / 0,
2897	/128:out / 0,
2898	/256:out / 0,
2899	/xcpt? / false, false },
2900	{ { /src2 / { FP32_V(0, 0x5c0000, 0x84)/* 55/, FP32_V(0, 0x600000, 0x81)/ 7.00/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/ 55.00/, FP32_V(0, 0x253468, 0x93)/1353357/, FP32_V(1, 0x7c9000, 0x88)/-1010.25/, FP32_0(0), FP32_V(0, 0x534000, 0x86)/211.25*/ } },
2901	{ /src1 / { FP32_V(0, 0x669050, 0x93)/1888778/, FP32_V(1, 0x1ea980, 0x8f)/* -81235.00/, FP32_V(0, 0x253468, 0x93)/1353357/, FP32_V(1, 0x7c9000, 0x88)/-1010.25/, FP32_V(0, 0x5c0000, 0x84)/ 55/, FP32_V(0, 0x600000, 0x81)/7/, FP32_V(0, 0x534000, 0x86)/211.25*/, FP32_1(1) } },
2902	{ /* => / { FP32_V(0, 0x5ca5b8, 0x93)/1807543/, FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_V(0, 0x780000, 0x84)/ 62/, FP32_V(0, 0x5c0000, 0x84)/ 55.00/, FP32_V(0, 0x780000, 0x84)/ 62/, FP32_V(0, 0x524000, 0x86)/210.25/, FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_V(0, 0x534000, 0x86)/211.25*/ } },
2903	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2904	/128:out / X86_MXCSR_XCPT_MASK,
2905	/256:out / X86_MXCSR_XCPT_MASK,
2906	/xcpt? / false, false },
2907	{ { /src2 / { FP32_V(0, 0x3c614e, 0x96)/12345678/, FP32_V(0, 0x3c614e, 0x96)/12345678/, FP32_0(0), FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/24691356/, FP32_V(1, 0x3c614e, 0x96)/-12345678/, FP32_0(0), FP32_1(1) } },
2908	{ /src1 / { FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_V(1, 0x712060, 0x92)/* -987654/, FP32_NORM_V3(1), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_V(1, 0x712060, 0x92)/ -987654*/, FP32_0(0), FP32_1(0) } },
2909	{ /* => / { FP32_V(0, 0x6cb99c, 0x97)/31028024/, FP32_NORM_V3(1), FP32_V(0, 0x3c614e, 0x97)/24691356/, FP32_NORM_V1(0), FP32_V(0, 0x6cb99c, 0x97)/31028024/, FP32_1(0), FP32_V(0, 0x3c614e, 0x96)/12345678*/, FP32_1(1) } },
2910	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2911	/128:out / X86_MXCSR_XCPT_MASK,
2912	/256:out / X86_MXCSR_XCPT_MASK,
2913	/xcpt? / false, false },
2914	{ { /src2 / { FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0), FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0) } },
2915	{ /src1 / { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } },
2916	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1) } },
2917	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2918	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2919	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_ZERO,
2920	/xcpt? / false, false },
2921	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } },
2922	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } },
2923	{ /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } },
2924	/mxcsr:in / 0,
2925	/128:out / 0,
2926	/256:out / 0,
2927	/xcpt? / false, false },
2928	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } },
2929	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } },
2930	{ /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } },
2931	/mxcsr:in / X86_MXCSR_FZ,
2932	/128:out / X86_MXCSR_FZ,
2933	/256:out / X86_MXCSR_FZ,
2934	/xcpt? / false, false },
2935	{ { /src2 / { FP32_V(0, 0x6423f2, 0x92)/* 934463.125/, FP32_V(1, 0x0a19f0, 0x8f)/-70707.875/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x600000, 0x7e)/ 0.875/, FP32_V(0, 0x769b50, 0x92)/1010101.000*/ } },
2936	{ /src1 / { FP32_V(0, 0x769b50, 0x92)/1010101.000/, FP32_V(0, 0x600000, 0x7e)/* 0.875/, FP32_V(0, 0x430ebc, 0x91)/399477.875/, FP32_V(0, 0x3ce348, 0x90)/193421.125/, FP32_V(0, 0x16b43a, 0x93)/1234567.25/, FP32_V(0, 0x00c6d3, 0x94)/2109876.75/, FP32_V(0, 0x792318, 0x91)/510232.750/, FP32_V(1, 0x316740, 0x8e)/ -45415.250*/ } },
2937	{ /* => / { FP32_V(0, 0x769b5e, 0x92)/1010101.875/, FP32_V(0, 0x10c030, 0x92)/592899.000/, FP32_V(0, 0x52e0b4, 0x92)/863755.250/, FP32_V(1, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/3344444.00/, FP32_V(0, 0x62f630, 0x91)/464817.50/, FP32_V(0, 0, 2), FP32_V(0, 0x769b5e, 0x92)/1010101.875*/ } },
2938	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2939	/128:out / X86_MXCSR_XCPT_MASK,
2940	/256:out / X86_MXCSR_XCPT_MASK,
2941	/xcpt? / false, false },
2942	/*
2943	* Denormals.
2944	*/
2945	/26/{ { /src2 / { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2946	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
2947	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2948	/mxcsr:in / 0,
2949	/128:out / X86_MXCSR_DE,
2950	/256:out / X86_MXCSR_DE,
2951	/xcpt? / true, true },
2952	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2953	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
2954	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2955	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_XCPT_MASK,
2956	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_XCPT_MASK,
2957	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_XCPT_MASK,
2958	/xcpt? / false, false },
2959	{ { /src2 / { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
2960	{ /src1 / { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
2961	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), } },
2962	/mxcsr:in / X86_MXCSR_DAZ,
2963	/128:out / X86_MXCSR_DAZ,
2964	/256:out / X86_MXCSR_DAZ,
2965	/xcpt? / false, false },
2966	{ { /src2 / { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2967	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2968	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2969	/mxcsr:in / 0,
2970	/128:out / X86_MXCSR_DE,
2971	/256:out / X86_MXCSR_DE,
2972	/xcpt? / true, true },
2973	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
2974	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2975	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2976	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_XCPT_MASK,
2977	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_XCPT_MASK,
2978	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_XCPT_MASK,
2979	/xcpt? / false, false },
2980	{ { /src2 / { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
2981	{ /src1 / { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
2982	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2983	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
2984	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
2985	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
2986	/xcpt? / false, false },
2987	/** @todo Denormals; Rounding, FZ etc. */
2988	/*
2989	* Invalids.
2990	*/
2991	/32/{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2992	{ /src1 / { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2993	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },
2994	/mxcsr:in / X86_MXCSR_XCPT_MASK,
2995	/128:out / X86_MXCSR_XCPT_MASK,
2996	/256:out / X86_MXCSR_XCPT_MASK,
2997	/xcpt? / false, false },
2998	{ { /src2 / { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },
2999	{ /src1 / { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3000	{ /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3001	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3002	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3003	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3004	/xcpt? / false, false },
3005	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3006	{ /src1 / { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3007	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3008	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3009	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3010	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3011	/xcpt? / false, false },
3012	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3013	{ /src1 / { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3014	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3015	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3016	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3017	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3018	/xcpt? / false, false },
3019	{ { /src2 / { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },
3020	{ /src1 / { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3021	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3022	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3023	/128:out / X86_MXCSR_XCPT_MASK,
3024	/256:out / X86_MXCSR_XCPT_MASK,
3025	/xcpt? / false, false },
3026	{ { /src2 / { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },
3027	{ /src1 / { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3028	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3029	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3030	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3031	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3032	/xcpt? / false, false },
3033	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3034	{ /src1 / { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3035	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },
3036	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3037	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3038	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3039	/xcpt? / false, false },
3040	{ { /src2 / { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },
3041	{ /src1 / { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3042	{ /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3043	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_UP,
3044	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
3045	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
3046	/xcpt? / true, true },
3047	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3048	{ /src1 / { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3049	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3050	/mxcsr:in / 0,
3051	/128:out / X86_MXCSR_IE,
3052	/256:out / X86_MXCSR_IE,
3053	/xcpt? / true, true },
3054	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3055	{ /src1 / { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3056	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3057	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
3058	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
3059	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_IE,
3060	/xcpt? / true, true },
3061	{ { /src2 / { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },
3062	{ /src1 / { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3063	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3064	/mxcsr:in / 0,
3065	/128:out / 0,
3066	/256:out / 0,
3067	/xcpt? / false, false },
3068	{ { /src2 / { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },
3069	{ /src1 / { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3070	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3071	/mxcsr:in / X86_MXCSR_RC_UP,
3072	/128:out / X86_MXCSR_RC_UP\|X86_MXCSR_IE,
3073	/256:out / X86_MXCSR_RC_UP\|X86_MXCSR_IE,
3074	/xcpt? / true, true },
3075	/** @todo Underflow, Precision; Rounding, FZ etc. */
3076	};
3077
3078	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3079	{
3080	{ bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3081	{ bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3082
3083	{ bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3084	{ bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3085
3086	{ bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3087	{ bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3088	};
3089	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3090	{
3091	{ bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3092	{ bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3093
3094	{ bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3095	{ bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3096
3097	{ bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3098	{ bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3099	};
3100	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3101	{
3102	{ bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3103	{ bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3104
3105	{ bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3106	{ bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3107
3108	{ bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3109	{ bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3110
3111	{ bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3112	{ bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3113
3114	{ bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3115	{ bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3116	};
3117
3118	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3119	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3120	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3121	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
3122	}
3123
3124
3125	/*
3126	* [V]SUBPS.
3127	*/
3128	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subps(uint8_t bMode)
3129	{
3130	static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
3131	{
3132	/*
3133	* Zero.
3134	*/
3135	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3136	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3137	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3138	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3139	/128:out / X86_MXCSR_XCPT_MASK,
3140	/256:out / X86_MXCSR_XCPT_MASK,
3141	/xcpt? / false, false },
3142	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3143	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3144	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3145	/mxcsr:in / 0,
3146	/128:out / 0,
3147	/256:out / 0,
3148	/xcpt? / false, false },
3149	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3150	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3151	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3152	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
3153	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
3154	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP,
3155	/xcpt? / false, false },
3156	{ { /src2 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
3157	{ /src1 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
3158	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3159	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3160	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3161	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3162	/xcpt? / false, false },
3163	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
3164	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
3165	{ /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
3166	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_DOWN,
3167	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_DOWN,
3168	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_DOWN,
3169	/xcpt? / false, false },
3170	{ { /src2 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3171	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3172	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3173	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_FLAGS,
3174	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_FLAGS,
3175	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_FLAGS,
3176	/xcpt? / false, false },
3177	/*
3178	* Infinity.
3179	*/
3180	/* 6/{ { /src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3181	{ /src1 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3182	{ /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3183	/mxcsr:in / X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3184	/128:out / X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3185	/256:out / X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3186	/xcpt? / false, false },
3187	{ { /src2 / { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3188	{ /src1 / { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3189	{ /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
3190	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3191	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3192	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3193	/xcpt? / false, false },
3194	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3195	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3196	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
3197	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3198	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3199	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3200	/xcpt? / false, false },
3201	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
3202	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
3203	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
3204	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
3205	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
3206	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
3207	/xcpt? / false, false },
3208	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3209	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3210	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
3211	/mxcsr:in / X86_MXCSR_FZ,
3212	/128:out / X86_MXCSR_FZ,
3213	/256:out / X86_MXCSR_FZ \| X86_MXCSR_IE,
3214	/xcpt? / false, true },
3215	{ { /src2 / { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
3216	{ /src1 / { FP32_INF(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
3217	{ /* => */ { FP32_INF(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
3218	/mxcsr:in / X86_MXCSR_RC_ZERO,
3219	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3220	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3221	/xcpt? / true, true },
3222	/*
3223	* Overflow, Precision.
3224	*/
3225	/12/{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3226	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
3227	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3228	/mxcsr:in / 0,
3229	/128:out / 0,
3230	/256:out / X86_MXCSR_PE,
3231	/xcpt? / false, true },
3232	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
3233	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3234	{ /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0) } },
3235	/mxcsr:in / X86_MXCSR_OM \| X86_MXCSR_PM,
3236	/128:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3237	/256:out / X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3238	/xcpt? / false, false },
3239	{ { /src2 / { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
3240	{ /src1 / { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
3241	{ /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3242	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OM \| X86_MXCSR_PM,
3243	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3244	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3245	/xcpt? / false, false },
3246	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, 2), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
3247	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
3248	{ /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0) } },
3249	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OM \| X86_MXCSR_PM,
3250	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3251	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3252	/xcpt? / false, false },
3253	{ { /src2 / { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },
3254	{ /src1 / { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },
3255	{ /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
3256	/mxcsr:in / X86_MXCSR_RC_ZERO \| X86_MXCSR_OM \| X86_MXCSR_PM,
3257	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3258	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_OM \| X86_MXCSR_PM \| X86_MXCSR_OE \| X86_MXCSR_PE,
3259	/xcpt? / false, false },
3260	{ { /src2 / { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3261	{ /src1 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3262	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } },
3263	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
3264	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
3265	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP \| X86_MXCSR_OE \| X86_MXCSR_PE,
3266	/xcpt? / false, false },
3267	{ { /src2 / { FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3268	{ /src1 / { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3269	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3270	/mxcsr:in / X86_MXCSR_RC_ZERO,
3271	/128:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
3272	/256:out / X86_MXCSR_RC_ZERO \| X86_MXCSR_PE,
3273	/xcpt? / true, true },
3274	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3275	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3276	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3277	/mxcsr:in / X86_MXCSR_RC_DOWN,
3278	/128:out / X86_MXCSR_RC_DOWN \| X86_MXCSR_OE \| X86_MXCSR_PE,
3279	/256:out / X86_MXCSR_RC_DOWN \| X86_MXCSR_OE \| X86_MXCSR_PE,
3280	/xcpt? / true, true },
3281	/*
3282	* Normals.
3283	*/
3284	/20/{ { /src2 / { FP32_V(0, 0, 0x7d)/0.25/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_V(1, 0, 0x7e)/-0.50/, FP32_0(0), FP32_0(1), FP32_V(0, 0x400000, 0x7e)/* 0.75*/ } },
3285	{ /src1 / { FP32_V(0, 0x600000, 0x7f)/1.75/, FP32_0(0), FP32_0(0), FP32_0(0), FP32_V(1, 0x400000, 0x7e)/-0.75/, FP32_0(0), FP32_0(1), FP32_V(0, 0, 0x7e)/* 0.50*/ } },
3286	{ /* => / { FP32_V(0, 0x400000, 0x7f)/1.50/, FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/-0.25/, FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/-0.25*/ } },
3287	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
3288	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
3289	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
3290	/xcpt? / false, false },
3291	{ { /src2 / { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
3292	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
3293	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3294	/mxcsr:in / 0,
3295	/128:out / 0,
3296	/256:out / 0,
3297	/xcpt? / false, false },
3298	{ { /src2 / { FP32_V(0, 0x5ca5b8, 0x93)/1807543/, FP32_V(0, 0x600000, 0x81)/* 7/, FP32_V(0, 0x7c9000, 0x88)/ 1010.25/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/ 55/, FP32_V(0, 0x2514d6, 0x93)/ 1352346.75/, FP32_V(0, 0x534000, 0x86)/211.25*/, FP32_0(0) } },
3299	{ /src1 / { FP32_V(0, 0x669050, 0x93)/1888778/, FP32_V(0, 0x780000, 0x84)/62/, FP32_V(0, 0x253468, 0x93)/1353357.00/, FP32_0(0), FP32_V(1, 0x600000, 0x81)/* -7/, FP32_V(1, 0x7c9000, 0x88)/ -1010.25/, FP32_1(0) / 1.00*/, FP32_0(0) } },
3300	{ /* => / { FP32_V(0, 0x1ea980, 0x8f)/ 81235/, FP32_V(0, 0x5c0000, 0x84)/55/, FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_0(0), FP32_V(1, 0x780000, 0x84)/-62/, FP32_V(1, 0x253468, 0x93)/-1353357.00/, FP32_V(1, 0x524000, 0x86)/210.25*/, FP32_0(0) } },
3301	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS \| X86_MXCSR_RC_ZERO \| X86_MXCSR_FZ,
3302	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS \| X86_MXCSR_RC_ZERO \| X86_MXCSR_FZ,
3303	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_XCPT_FLAGS \| X86_MXCSR_RC_ZERO \| X86_MXCSR_FZ,
3304	/xcpt? / false, false },
3305	{ { /src2 / { FP32_V(0, 0x6cb99c, 0x97)/31028024/, FP32_V(1, 0x3c614e, 0x96)/-12345678/, FP32_0(0), FP32_0(0), FP32_V(0, 0x712060, 0x92)/* 987654/, FP32_V(0, 0x3c614e, 0x96)/12345678*/, FP32_0(0), FP32_0(0) } },
3306	{ /src1 / { FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_V(0, 0x3c614e, 0x96)/* 12345678/, FP32_0(0), FP32_1(0), FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_V(0, 0x3c614e, 0x97)/24691356*/, FP32_1(0), FP32_1(0) } },
3307	{ /* => / { FP32_V(0, 0x712060, 0x92)/ 987654/, FP32_V(0, 0x3c614e, 0x97)/ 24691356/, FP32_0(1), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/31028024/, FP32_V(0, 0x3c614e, 0x96)/12345678*/, FP32_1(0), FP32_1(0) } },
3308	/mxcsr:in / X86_MXCSR_RC_DOWN,
3309	/128:out / X86_MXCSR_RC_DOWN,
3310	/256:out / X86_MXCSR_RC_DOWN,
3311	/xcpt? / false, false },
3312	{ { /src2 / { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } },
3313	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_0(1), FP32_0(0) } },
3314	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0) } },
3315	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
3316	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
3317	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
3318	/xcpt? / false, false },
3319	{ { /src2 / { FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0) } },
3320	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
3321	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(0), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(0) } },
3322	/mxcsr:in / X86_MXCSR_RC_UP,
3323	/128:out / X86_MXCSR_RC_UP,
3324	/256:out / X86_MXCSR_RC_UP,
3325	/xcpt? / false, false },
3326	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },
3327	{ /src1 / { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } },
3328	{ /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0) } },
3329	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3330	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3331	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3332	/xcpt? / false, false },
3333	{ { /src2 / { FP32_V(0, 0x600000, 0x7e)/* 0.875/, FP32_V(0, 0x3ce348, 0x90)/193421.125/, FP32_V(1, 0x0a19f0, 0x8f)/-70707.875/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/2109876.75/, FP32_V(0, 0x316740, 0x8e)/ 45415.25/, FP32_V(0, 0x600000, 0x7e)/ 0.875*/ } },
3334	{ /src1 / { FP32_V(0, 0x769b5e, 0x92)/1010101.875/, FP32_V(0, 0x10c030, 0x92)/592899.000/, FP32_V(0, 0x52e0b4, 0x92)/863755.250/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/3344444.00/, FP32_V(0, 0x792318, 0x91)/510232.75/, FP32_V(1, 0x769b50, 0x92)/-1010101.000/ } },
3335	{ /* => / { FP32_V(0, 0x769b50, 0x92)/1010101.000/, FP32_V(0, 0x430ebc, 0x91)/399477.875/, FP32_V(0, 0x6423f2, 0x92)/934463.125/, FP32_V(0, 0, 2), FP32_V(1, 0, 2), FP32_V(0, 0x16b43a, 0x93)/1234567.25/, FP32_V(0, 0x62f630, 0x91)/464817.50/, FP32_V(1, 0x769b5e, 0x92)/-1010101.875*/ } },
3336	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3337	/128:out / X86_MXCSR_XCPT_MASK,
3338	/256:out / X86_MXCSR_XCPT_MASK,
3339	/xcpt? / false, false },
3340	/*
3341	* Denormals.
3342	*/
3343	/28/{ { /src2 / { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3344	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3345	{ /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3346	/mxcsr:in / 0,
3347	/128:out / X86_MXCSR_DE,
3348	/256:out / X86_MXCSR_DE,
3349	/xcpt? / true, true },
3350	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3351	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
3352	{ /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
3353	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3354	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
3355	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
3356	/xcpt? / false, false },
3357	{ { /src2 / { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
3358	{ /src1 / { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
3359	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3360	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
3361	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
3362	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_XCPT_MASK \| X86_MXCSR_RC_UP,
3363	/xcpt? / false, false },
3364	{ { /src2 / { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3365	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3366	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3367	/mxcsr:in / 0,
3368	/128:out / X86_MXCSR_DE,
3369	/256:out / X86_MXCSR_DE,
3370	/xcpt? / true, true },
3371	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3372	{ /src1 / { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3373	{ /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0) } },
3374	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3375	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
3376	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_DE,
3377	/xcpt? / false, false },
3378	{ { /src2 / { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0) } },
3379	{ /src1 / { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } },
3380	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3381	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_XCPT_MASK,
3382	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_XCPT_MASK,
3383	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_UP \| X86_MXCSR_XCPT_MASK,
3384	/xcpt? / false, false },
3385	/** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
3386	/*
3387	* Invalids.
3388	*/
3389	/34/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3390	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3391	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3392	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3393	/128:out / X86_MXCSR_XCPT_MASK,
3394	/256:out / X86_MXCSR_XCPT_MASK,
3395	/xcpt? / false, false },
3396	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3397	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3398	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3399	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3400	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3401	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3402	/xcpt? / false, false },
3403	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
3404	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3405	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3406	/mxcsr:in / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ,
3407	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
3408	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_FZ \| X86_MXCSR_IE,
3409	/xcpt? / false, false },
3410	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3411	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3412	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
3413	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3414	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3415	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3416	/xcpt? / false, false },
3417	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3418	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3419	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3420	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3421	/128:out / X86_MXCSR_XCPT_MASK,
3422	/256:out / X86_MXCSR_XCPT_MASK,
3423	/xcpt? / false, false },
3424	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
3425	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3426	{ /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3427	/mxcsr:in / X86_MXCSR_XCPT_MASK,
3428	/128:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3429	/256:out / X86_MXCSR_XCPT_MASK \| X86_MXCSR_IE,
3430	/xcpt? / false, false },
3431	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3432	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3433	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3434	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
3435	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
3436	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_DOWN,
3437	/xcpt? / false, false },
3438	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3439	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3440	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3441	/mxcsr:in / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3442	/128:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3443	/256:out / X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3444	/xcpt? / true, true },
3445	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
3446	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3447	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3448	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO,
3449	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3450	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_FZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3451	/xcpt? / true, true },
3452	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3453	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3454	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
3455	/mxcsr:in / X86_MXCSR_RC_UP,
3456	/128:out / X86_MXCSR_RC_UP \| X86_MXCSR_IE,
3457	/256:out / X86_MXCSR_RC_UP \| X86_MXCSR_IE,
3458	/xcpt? / true, true },
3459	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3460	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3461	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3462	/mxcsr:in / X86_MXCSR_RC_DOWN,
3463	/128:out / X86_MXCSR_RC_DOWN,
3464	/256:out / X86_MXCSR_RC_DOWN,
3465	/xcpt? / false, false },
3466	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
3467	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3468	{ /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3469	/mxcsr:in / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO,
3470	/128:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3471	/256:out / X86_MXCSR_DAZ \| X86_MXCSR_RC_ZERO \| X86_MXCSR_IE,
3472	/xcpt? / true, true },
3473	};
3474
3475	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3476	{
3477	{ bs3CpuInstr4_subps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3478	{ bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3479
3480	{ bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3481	{ bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3482
3483	{ bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3484	{ bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3485	};
3486	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3487	{
3488	{ bs3CpuInstr4_subps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3489	{ bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3490
3491	{ bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3492	{ bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3493
3494	{ bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3495	{ bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3496	};
3497	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3498	{
3499	{ bs3CpuInstr4_subps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3500	{ bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3501
3502	{ bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3503	{ bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3504
3505	{ bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3506	{ bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3507
3508	{ bs3CpuInstr4_subps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3509	{ bs3CpuInstr4_subps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3510
3511	{ bs3CpuInstr4_vsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3512	{ bs3CpuInstr4_vsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3513	};
3514
3515	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3516	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3517	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3518	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
3519	}
3520
3521
3522	#if 0
3523	/*
3524	* [V]SUBPD.
3525	*/
3526	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subpd(uint8_t bMode)
3527	{
3528	static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
3529	{
3530	/*
3531	* Zero.
3532	*/
3533	/* 0/{ { /src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3534	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3535	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3536	/mask / X86_MXCSR_XCPT_MASK,
3537	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3538	/flags / 0, 0 },
3539	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3540	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3541	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3542	/mask / ~X86_MXCSR_XCPT_MASK,
3543	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3544	/flags / 0, 0 },
3545	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3546	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3547	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3548	/mask / ~X86_MXCSR_XCPT_MASK,
3549	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
3550	/flags / 0, 0 },
3551	{ { /src2 / { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
3552	{ /src1 / { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
3553	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3554	/mask / ~X86_MXCSR_XCPT_MASK,
3555	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
3556	/flags / 0, 0 },
3557	{ { /src2 / { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
3558	{ /src1 / { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
3559	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3560	/mask / ~X86_MXCSR_XCPT_MASK,
3561	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3562	/flags / 0, 0 },
3563	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3564	{ /src1 / { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } },
3565	{ /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
3566	/mask / X86_MXCSR_XCPT_MASK,
3567	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
3568	/flags / 0, 0 },
3569	/*
3570	* Infinity.
3571	*/
3572	/* 6/{ { /src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_INF(1) } },
3573	{ /src1 / { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3574	{ /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3575	/mask / ~X86_MXCSR_IM,
3576	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3577	/flags / 0, 0 },
3578	{ { /src2 / { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } },
3579	{ /src1 / { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
3580	{ /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(0), FP64_QNAN(1) } },
3581	/mask / X86_MXCSR_XCPT_MASK,
3582	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3583	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3584	{ { /src2 / { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
3585	{ /src1 / { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
3586	{ /* => */ { FP64_QNAN(1), FP64_INF(1), FP64_INF(0), FP64_QNAN(1) } },
3587	/mask / X86_MXCSR_XCPT_MASK,
3588	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3589	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3590	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } },
3591	{ /src1 / { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(1) } },
3592	{ /* => */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_QNAN(1) } },
3593	/mask / X86_MXCSR_XCPT_MASK,
3594	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3595	/flags / 0, X86_MXCSR_IE },
3596	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3597	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3598	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_QNAN(1) } },
3599	/mask / ~X86_MXCSR_XCPT_MASK,
3600	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3601	/flags / 0, X86_MXCSR_IE },
3602	{ { /src2 / { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
3603	{ /src1 / { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
3604	{ /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
3605	/mask / ~X86_MXCSR_XCPT_MASK,
3606	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3607	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3608	/*
3609	* Overflow, Precision.
3610	*/
3611	/12/{ { /src2 / { FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3612	{ /src1 / { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
3613	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3614	/mask / ~X86_MXCSR_XCPT_MASK,
3615	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3616	/flags / X86_MXCSR_PE, X86_MXCSR_PE },
3617	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3618	{ /src1 / { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
3619	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3620	/mask / ~X86_MXCSR_XCPT_MASK,
3621	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3622	/flags / 0, X86_MXCSR_PE },
3623	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
3624	{ /src1 / { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
3625	{ /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } },
3626	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3627	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3628	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3629	{ { /src2 / { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } },
3630	{ /src1 / { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
3631	{ /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } },
3632	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3633	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3634	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3635	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },
3636	{ /src1 / { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
3637	{ /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } },
3638	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3639	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3640	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3641	{ { /src2 / { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } },
3642	{ /src1 / { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },
3643	{ /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
3644	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3645	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3646	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3647	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
3648	{ /src1 / { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
3649	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
3650	/mask / X86_MXCSR_XCPT_MASK,
3651	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3652	/flags / 0, X86_MXCSR_OE \| X86_MXCSR_PE },
3653	{ { /src2 / { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3654	{ /src1 / { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
3655	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3656	/mask / ~(X86_MXCSR_OM \| X86_MXCSR_PM),
3657	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3658	/flags / X86_MXCSR_PE, X86_MXCSR_PE },
3659	{ { /src2 / { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
3660	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
3661	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3662	/mask / ~X86_MXCSR_XCPT_MASK,
3663	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3664	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3665	/*
3666	* Normals.
3667	*/
3668	/21/{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
3669	{ /src1 / { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
3670	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3671	/mask / ~X86_MXCSR_XCPT_MASK,
3672	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3673	/flags / 0, 0 },
3674	{ { /src2 / { FP64_V(0, 0, 0x409)/1024/, FP64_V(0, 0xb800000000000, 0x404)/55/, FP64_V(1, 0xc000000000000, 0x401)/* 7/, FP64_V(0, 0x8000000000000, 0x409)/1536*/ } },
3675	{ /src1 / { FP64_V(0, 0x8000000000000, 0x409)/1536/, FP64_V(1, 0xc000000000000, 0x401)/* 7/, FP64_V(0, 0xb800000000000, 0x404)/55/, FP64_V(0, 0, 0x409)/1024*/ } },
3676	{ /* => / { FP64_V(0, 0, 0x408)/ 512/, FP64_V(1, 0xf000000000000, 0x404)/62/, FP64_V(0, 0xf000000000000, 0x404)/62/, FP64_V(1, 0, 0x408)/ 512*/ } },
3677	/mask / X86_MXCSR_XCPT_MASK,
3678	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3679	/flags / 0, 0 },
3680	{ { /src2 / { FP64_V(0, 0x26580b4800000, 0x41d)/1234567890/, FP64_V(0, 0x9000000000000, 0x405)/* 100/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/ 123450000.5*/ } },
3681	{ /src1 / { FP64_V(0, 0x26580b4800000, 0x41d)/1234567890/, FP64_V(0, 0xd6f3458800000, 0x41c)/987654321/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/4072598123457580.0/ } },
3682	{ /* => / { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/987654221/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/4072598000007579.5*/ } },
3683	/mask / ~X86_MXCSR_XCPT_MASK,
3684	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3685	/flags / 0, 0 },
3686	{ { /src2 / { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } },
3687	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_0(0), FP64_0(0) } },
3688	{ /* => */ { FP64_1(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
3689	/mask / X86_MXCSR_XCPT_MASK,
3690	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3691	/flags / 0, 0 },
3692	{ { /src2 / { FP64_1(0), FP64_1(1), FP64_1(1), FP64_NORM_SAFE_INT_MAX(0) } },
3693	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0) } },
3694	{ /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } },
3695	/mask / X86_MXCSR_XCPT_MASK,
3696	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3697	/flags / 0, 0 },
3698	{ { /src2 / { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
3699	{ /src1 / { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },
3700	{ /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, 2) } },
3701	/mask / ~X86_MXCSR_XCPT_MASK,
3702	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3703	/flags / 0, 0 },
3704	{ { /src2 / { FP64_V(0, 0xc122186c3cfd0, 0x42d)/123456789876543.25/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } },
3705	{ /src1 / { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/244555555308646.00/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } },
3706	{ /* => / { FP64_V(0, 0xb88e0395d49b0, 0x42d)/121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, 2) } },
3707	/mask / X86_MXCSR_XCPT_MASK,
3708	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
3709	/flags / 0, 0 },
3710	/*
3711	* Denormals.
3712	*/
3713	/28/{ { /src2 / { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3714	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3715	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3716	/mask / ~X86_MXCSR_XCPT_MASK,
3717	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3718	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
3719	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3720	{ /src1 / { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
3721	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3722	/mask / X86_MXCSR_XCPT_MASK,
3723	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
3724	/flags / 0, 0 },
3725	{ { /src2 / { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
3726	{ /src1 / { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
3727	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3728	/mask / X86_MXCSR_XCPT_MASK,
3729	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
3730	/flags / 0, 0 },
3731	/** @todo More denormals. */
3732	/*
3733	* Invalids.
3734	*/
3735	/31/{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3736	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3737	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3738	/mask / X86_MXCSR_XCPT_MASK,
3739	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3740	/flags / 0, 0 },
3741	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3742	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0) } },
3743	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3744	/mask / X86_MXCSR_XCPT_MASK,
3745	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3746	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3747	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3748	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3749	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3750	/mask / X86_MXCSR_XCPT_MASK,
3751	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3752	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3753	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3754	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
3755	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3756	/mask / X86_MXCSR_XCPT_MASK,
3757	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3758	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3759	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3760	{ /src1 / { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3761	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3762	/mask / X86_MXCSR_XCPT_MASK,
3763	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3764	/flags / 0, 0 },
3765	{ { /src2 / { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3766	{ /src1 / { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3767	{ /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3768	/mask / X86_MXCSR_XCPT_MASK,
3769	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3770	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3771	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) , FP64_QNAN_V(0, FP64_FRAC_V1) } },
3772	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3773	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3774	/mask / ~X86_MXCSR_XCPT_MASK,
3775	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
3776	/flags / 0, 0 },
3777	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
3778	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
3779	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
3780	/mask / ~X86_MXCSR_XCPT_MASK,
3781	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3782	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3783	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3784	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3785	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3786	/mask / ~X86_MXCSR_XCPT_MASK,
3787	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3788	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3789	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3790	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3791	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3792	/mask / ~X86_MXCSR_XCPT_MASK,
3793	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_UP,
3794	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3795	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3796	{ /src1 / { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
3797	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3798	/mask / ~X86_MXCSR_XCPT_MASK,
3799	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
3800	/flags / 0, 0 },
3801	{ { /src2 / { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3802	{ /src1 / { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
3803	{ /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3804	/mask / ~X86_MXCSR_XCPT_MASK,
3805	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
3806	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3807	/** @todo Underflow, Precision; Rounding, FZ etc. */
3808	};
3809
3810	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3811	{
3812	{ bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3813	{ bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3814
3815	{ bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3816	{ bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3817
3818	{ bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3819	{ bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3820	};
3821	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3822	{
3823	{ bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3824	{ bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3825
3826	{ bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3827	{ bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3828
3829	{ bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3830	{ bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3831	};
3832	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3833	{
3834	{ bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3835	{ bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3836
3837	{ bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3838	{ bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3839
3840	{ bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3841	{ bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3842
3843	{ bs3CpuInstr4_subpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3844	{ bs3CpuInstr4_subpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3845
3846	{ bs3CpuInstr4_vsubpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3847	{ bs3CpuInstr4_vsubpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3848	};
3849
3850	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3851	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3852	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3853	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
3854	}
3855
3856
3857	/*
3858	* [V]SUBSS.
3859	*/
3860	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subss(uint8_t bMode)
3861	{
3862	static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
3863	{
3864	/*
3865	* Zero.
3866	*/
3867	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3868	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3869	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3870	/mask / X86_MXCSR_XCPT_MASK,
3871	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3872	/flags / 0, 0 },
3873	{ { /src2 / { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
3874	{ /src1 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3875	{ /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3876	/mask / ~X86_MXCSR_XCPT_MASK,
3877	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3878	/flags / 0, 0 },
3879	{ { /src2 / { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
3880	{ /src1 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3881	{ /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3882	/mask / ~X86_MXCSR_XCPT_MASK,
3883	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
3884	/flags / 0, 0 },
3885	{ { /src2 / { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
3886	{ /src1 / { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
3887	{ /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
3888	/mask / ~X86_MXCSR_XCPT_MASK,
3889	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
3890	/flags / 0, 0 },
3891	{ { /src2 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
3892	{ /src1 / { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
3893	{ /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
3894	/mask / ~X86_MXCSR_XCPT_MASK,
3895	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3896	/flags / 0, 0 },
3897	{ { /src2 / { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
3898	{ /src1 / { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
3899	{ /* => */ { FP32_0(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
3900	/mask / X86_MXCSR_XCPT_MASK,
3901	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
3902	/flags / 0, 0 },
3903	/*
3904	* Infinity.
3905	*/
3906	/* 6/{ { /src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3907	{ /src1 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3908	{ /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3909	/mask / ~X86_MXCSR_IM,
3910	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3911	/flags / 0, 0 },
3912	{ { /src2 / { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
3913	{ /src1 / { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3914	{ /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3915	/mask / ~X86_MXCSR_IM,
3916	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3917	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3918	{ { /src2 / { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
3919	{ /src1 / { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3920	{ /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
3921	/mask / X86_MXCSR_XCPT_MASK,
3922	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3923	/flags / 0, 0 },
3924	{ { /src2 / { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
3925	{ /src1 / { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
3926	{ /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
3927	/mask / X86_MXCSR_XCPT_MASK,
3928	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3929	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
3930	{ { /src2 / { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
3931	{ /src1 / { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
3932	{ /* => */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
3933	/mask / ~X86_MXCSR_XCPT_MASK,
3934	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3935	/flags / 0, 0 },
3936	{ { /src2 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
3937	{ /src1 / { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
3938	{ /* => */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
3939	/mask / X86_MXCSR_XCPT_MASK,
3940	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3941	/flags / 0, 0 },
3942	/*
3943	* Overflow, Precision.
3944	*/
3945	/12/{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3946	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
3947	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3948	/mask / ~X86_MXCSR_XCPT_MASK,
3949	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
3950	/flags / 0, X86_MXCSR_PE },
3951	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
3952	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3953	{ /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0) } },
3954	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3955	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3956	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3957	{ { /src2 / { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
3958	{ /src1 / { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
3959	{ /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3960	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3961	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3962	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3963	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3964	{ /src1 / { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3965	{ /* => */ { FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3966	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3967	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
3968	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3969	{ { /src2 / { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3970	{ /src1 / { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3971	{ /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3972	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
3973	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
3974	/flags / X86_MXCSR_PE, X86_MXCSR_PE },
3975	{ { /src2 / { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3976	{ /src1 / { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3977	{ /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3978	/mask / X86_MXCSR_XCPT_MASK,
3979	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3980	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
3981	{ { /src2 / { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3982	{ /src1 / { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3983	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3984	/mask / ~(X86_MXCSR_OM \| X86_MXCSR_PM),
3985	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3986	/flags / X86_MXCSR_PE, X86_MXCSR_PE },
3987	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3988	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3989	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3990	/mask / ~X86_MXCSR_XCPT_MASK,
3991	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3992	/flags / X86_MXCSR_PE, X86_MXCSR_PE },
3993	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3994	{ /src1 / { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3995	{ /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3996	/mask / ~X86_MXCSR_XCPT_MASK,
3997	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
3998	/flags / X86_MXCSR_PE, X86_MXCSR_PE },
3999	/*
4000	* Normals.
4001	*/
4002	/18/{ { /src2 / { FP32_V(0, 0x600000, 0x7f)/1.75/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4003	{ /src1 / { FP32_V(0, 0, 0x7d)/0.25/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
4004	{ /* => / { FP32_V(1, 0x400000, 0x7f)/1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
4005	/mask / X86_MXCSR_XCPT_MASK,
4006	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4007	/flags / 0, 0 },
4008	{ { /src2 / { FP32_NORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
4009	{ /src1 / { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4010	{ /* => */ { FP32_0(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4011	/mask / X86_MXCSR_XCPT_MASK,
4012	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4013	/flags / 0, 0 },
4014	{ { /src2 / { FP32_V(0, 0x5ca5b8, 0x93)/1807543/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4015	{ /src1 / { FP32_V(0, 0x669050, 0x93)/1888778/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4016	{ /* => / { FP32_V(0, 0x1ea980, 0x8f)/ 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4017	/mask / X86_MXCSR_XCPT_MASK,
4018	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4019	/flags / 0, 0 },
4020	{ { /src2 / { FP32_V(0, 0x2514d6, 0x93)/1352346.75/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4021	{ /src1 / { FP32_V(0, 0x253468, 0x93)/1353357.00/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4022	{ /* => / { FP32_V(0, 0x7c9000, 0x88)/ 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4023	/mask / X86_MXCSR_XCPT_MASK,
4024	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4025	/flags / 0, 0 },
4026	{ { /src2 / { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4027	{ /src1 / { FP32_V(0, 0x74429f, 0x97)/32015678/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4028	{ /* => / { FP32_V(0, 0x6cb99c, 0x97)/31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4029	/mask / ~X86_MXCSR_XCPT_MASK,
4030	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4031	/flags / 0, 0 },
4032	{ { /src2 / { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4033	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4034	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4035	/mask / X86_MXCSR_XCPT_MASK,
4036	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4037	/flags / 0, 0 },
4038	{ { /src2 / { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4039	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4040	{ /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4041	/mask / X86_MXCSR_XCPT_MASK,
4042	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4043	/flags / 0, 0 },
4044	{ { /src2 / { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4045	{ /src1 / { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4046	{ /* => / { FP32_V(0, 0x769b5e, 0x92)/ 1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4047	/mask / X86_MXCSR_XCPT_MASK,
4048	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4049	/flags / 0, 0 },
4050	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
4051	{ /src1 / { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4052	{ /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4053	/mask / ~X86_MXCSR_XCPT_MASK,
4054	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4055	/flags / 0, 0 },
4056	/*
4057	* Denormals.
4058	*/
4059	/27/{ { /src2 / { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
4060	{ /src1 / { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
4061	{ /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
4062	/mask / ~X86_MXCSR_XCPT_MASK,
4063	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4064	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4065	{ { /src2 / { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
4066	{ /src1 / { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4067	{ /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4068	/mask / X86_MXCSR_XCPT_MASK,
4069	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
4070	/flags / 0, 0 },
4071	{ { /src2 / { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
4072	{ /src1 / { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
4073	{ /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
4074	/mask / X86_MXCSR_XCPT_MASK,
4075	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4076	/flags / 0, 0 },
4077	/** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
4078	};
4079
4080	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4081	{
4082	{ bs3CpuInstr4_subss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4083	{ bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4084
4085	{ bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4086	{ bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4087	};
4088	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4089	{
4090	{ bs3CpuInstr4_subss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4091	{ bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4092
4093	{ bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4094	{ bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4095	};
4096	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4097	{
4098	{ bs3CpuInstr4_subss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4099	{ bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4100
4101	{ bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4102	{ bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4103
4104	{ bs3CpuInstr4_subss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4105	{ bs3CpuInstr4_subss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4106	};
4107
4108	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4109	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4110	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4111	g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
4112	}
4113
4114
4115	/*
4116	* [V]MULPS.
4117	*/
4118	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulps(uint8_t bMode)
4119	{
4120	static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
4121	{
4122	/*
4123	* Zero.
4124	*/
4125	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4126	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4127	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4128	/mask / X86_MXCSR_XCPT_MASK,
4129	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4130	/flags / 0, 0 },
4131	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4132	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4133	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4134	/mask / ~X86_MXCSR_XCPT_MASK,
4135	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4136	/flags / 0, 0 },
4137	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4138	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4139	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4140	/mask / ~X86_MXCSR_XCPT_MASK,
4141	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4142	/flags / 0, 0 },
4143	{ { /src2 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4144	{ /src1 / { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4145	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4146	/mask / ~X86_MXCSR_XCPT_MASK,
4147	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
4148	/flags / 0, 0 },
4149	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
4150	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
4151	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4152	/mask / ~X86_MXCSR_XCPT_MASK,
4153	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4154	/flags / 0, 0 },
4155	{ { /src2 / { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
4156	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } },
4157	{ /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } },
4158	/mask / X86_MXCSR_XCPT_MASK,
4159	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4160	/flags / 0, 0 },
4161	{ { /src2 / { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } },
4162	{ /src1 / { FP32_0(0), FP32_0(0), FP32_NORM_V2(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
4163	{ /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4164	/mask / X86_MXCSR_XCPT_MASK,
4165	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4166	/flags / 0, 0 },
4167	/*
4168	* Infinity.
4169	*/
4170	/* 7/{ { /src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4171	{ /src1 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4172	{ /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4173	/mask / ~X86_MXCSR_IM,
4174	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4175	/flags / 0, 0 },
4176	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4177	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4178	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4179	/mask / X86_MXCSR_XCPT_MASK,
4180	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4181	/flags / 0, 0 },
4182	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
4183	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
4184	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
4185	/mask / X86_MXCSR_XCPT_MASK,
4186	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4187	/flags / 0, 0 },
4188	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
4189	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4190	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4191	/mask / ~X86_MXCSR_XCPT_MASK,
4192	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4193	/flags / 0, 0 },
4194	{ { /src2 / { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
4195	{ /src1 / { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
4196	{ /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
4197	/mask / ~X86_MXCSR_XCPT_MASK,
4198	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4199	/flags / 0, 0 },
4200	/*
4201	* Normals.
4202	*/
4203	/12/{ { /src2 / { FP32_V(0, 0x600000, 0x7f)/1.7500/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/0.250/, FP32_V(0, 0x600000, 0x7f)/* 1.7500/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/0.250*/ } },
4204	{ /src1 / { FP32_V(0, 0, 0x7d)/0.2500/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/0.500/, FP32_V(1, 0, 0x7d)/-0.2500/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/0.500/ } },
4205	{ /* => / { FP32_V(0, 0x600000, 0x7d)/0.4375/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/0.125/, FP32_V(1, 0x600000, 0x7d)/-0.4375/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/0.125*/ } },
4206	/mask / X86_MXCSR_XCPT_MASK,
4207	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4208	/flags / 0, 0 },
4209	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
4210	{ /src1 / { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
4211	{ /* => */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(1), FP32_NORM_V3(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
4212	/mask / ~X86_MXCSR_XCPT_MASK,
4213	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4214	/flags / 0, 0 },
4215	{ { /src2 / { FP32_V(0, 0x61e000, 0x89)/* 1807/, FP32_V(0, 0x4a30b8, 0x8f)/ 103521.4375/, FP32_V(0, 0x1a5200, 0x8c)/ 9876.5/, FP32_V(0, 0x0ba000, 0x86)/ 139.625000/, FP32_V(0, 0x200000, 0x7e)/0.625000/, FP32_V(0, 0x22fae4, 0x93)/1335132.50/, FP32_V(0, 0x23b6a0, 0x8e)/41910.625000/, FP32_V(0, 0x3d400, 0x86)/131.828125*/ } },
4216	{ /src1 / { FP32_V(0, 0x504000, 0x8a)/* 3332/, FP32_V(0, 0x600000, 0x82)/ 14.0000/, FP32_V(1, 0x1a4000, 0x89)/ -1234.0/, FP32_V(0, 0x265000, 0x87)/ 332.625000/, FP32_V(0, 0, 0x7c)/0.125000/, FP32_V(0, 0x200000, 0x80)/ 2.50/, FP32_V(0, 0, 0x7c)/ 0.125000/, FP32_1(1) / -1.000000*/ } },
4217	{ /* => / { FP32_V(0, 0x37be78, 0x95)/6020924/, FP32_V(0, 0x30eaa1, 0x93)/1449300.1250/, FP32_V(1, 0x39f7d1, 0x96)/-12187601.0/, FP32_V(0, 0x356ac4, 0x8e)/46442.765625/, FP32_V(0, 0x200000, 0x7b)/0.078125/, FP32_V(0, 0x4bb99d, 0x94)/3337831.25/, FP32_V(0, 0x23b6a0, 0x8b)/ 5238.828125/, FP32_V(1, 0x3d400, 0x86)/-131.828125*/ } },
4218	/mask / X86_MXCSR_XCPT_MASK,
4219	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4220	/flags / 0, 0 },
4221	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
4222	{ /src1 / { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0) } },
4223	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(0) } },
4224	/mask / X86_MXCSR_XCPT_MASK,
4225	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4226	/flags / 0, 0 },
4227	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } },
4228	{ /src1 / { FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_1(0) } },
4229	{ /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2) } },
4230	/mask / X86_MXCSR_XCPT_MASK,
4231	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4232	/flags / 0, 0 },
4233	/** @todo More Normals. */
4234	/*
4235	* Denormals.
4236	*/
4237	/17/{ { /src2 / { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
4238	{ /src1 / { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
4239	{ /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
4240	/mask / ~X86_MXCSR_XCPT_MASK,
4241	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4242	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4243	{ { /src2 / { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
4244	{ /src1 / { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } },
4245	{ /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
4246	/mask / ~X86_MXCSR_XCPT_MASK,
4247	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4248	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4249	{ { /src2 / { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } },
4250	{ /src1 / { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
4251	{ /* => */ { FP32_0(1), FP32_0(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4252	/mask / X86_MXCSR_XCPT_MASK,
4253	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
4254	/flags / 0, 0 },
4255	{ { /src2 / { FP32_DENORM_MIN(0), FP32_RAND_V4(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } },
4256	{ /src1 / { FP32_DENORM_MAX(0), FP32_1(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
4257	{ /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_0(0), FP32_0(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_0(0), FP32_0(0) } },
4258	/mask / X86_MXCSR_XCPT_MASK,
4259	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4260	/flags / 0, 0 },
4261	/** @todo More Denormals. */
4262	/*
4263	* Overflow, Precision.
4264	*/
4265	/21/{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V7(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4266	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4267	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_NORM_V7(0), FP32_INF(0), FP32_INF(0) } },
4268	/mask / X86_MXCSR_XCPT_MASK,
4269	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4270	/flags / 0, X86_MXCSR_OE \| X86_MXCSR_PE },
4271	{ { /src2 / { FP32_NORM_V5(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_1(0), FP32_0(0) } },
4272	{ /src1 / { FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } },
4273	{ /* => */ { FP32_NORM_V5(0), FP32_INF(0), FP32_INF(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } },
4274	/mask / X86_MXCSR_OM \| X86_MXCSR_PM,
4275	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4276	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
4277	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_V7(0), FP32_NORM_MAX(0) } },
4278	{ /src1 / { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(0) } },
4279	{ /* => */ { FP32_INF(0), FP32_0(0), FP32_1(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_NORM_V7(0), FP32_INF(0) } },
4280	/mask / X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM,
4281	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4282	/flags / X86_MXCSR_OE \| X86_MXCSR_UE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_UE \| X86_MXCSR_PE },
4283	{ { /src2 / { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_V5(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
4284	{ /src1 / { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0) } },
4285	{ /* => */ { FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_V5(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0) } },
4286	/mask / X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM,
4287	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4288	/flags / X86_MXCSR_OE \| X86_MXCSR_UE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_UE \| X86_MXCSR_PE },
4289	{ { /src2 / { FP32_NORM_V6(0), FP32_1(1), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4290	{ /src1 / { FP32_1(0), FP32_NORM_V6(1), FP32_1(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4291	{ /* => */ { FP32_NORM_V6(0), FP32_NORM_V6(0), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
4292	/mask / X86_MXCSR_XCPT_MASK,
4293	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
4294	/flags / 0, X86_MXCSR_OE \| X86_MXCSR_PE },
4295	{ { /src2 / { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
4296	{ /src1 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
4297	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4298	/mask / ~X86_MXCSR_XCPT_MASK,
4299	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
4300	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
4301	/** @todo More Overflow, Precision. */
4302	/*
4303	* Invalids.
4304	*/
4305	/27/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4306	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4307	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4308	/mask / X86_MXCSR_XCPT_MASK,
4309	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4310	/flags / 0, 0 },
4311	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4312	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4313	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4314	/mask / X86_MXCSR_XCPT_MASK,
4315	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4316	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4317	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
4318	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4319	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4320	/mask / X86_MXCSR_XCPT_MASK,
4321	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4322	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4323	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4324	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
4325	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
4326	/mask / X86_MXCSR_XCPT_MASK,
4327	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4328	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4329	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4330	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4331	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4332	/mask / X86_MXCSR_XCPT_MASK,
4333	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4334	/flags / 0, 0 },
4335	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
4336	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4337	{ /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4338	/mask / X86_MXCSR_XCPT_MASK,
4339	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4340	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4341	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4342	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4343	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4344	/mask / ~X86_MXCSR_XCPT_MASK,
4345	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4346	/flags / 0, 0 },
4347	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4348	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4349	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4350	/mask / ~X86_MXCSR_XCPT_MASK,
4351	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4352	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4353	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
4354	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4355	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4356	/mask / ~X86_MXCSR_XCPT_MASK,
4357	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4358	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4359	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4360	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
4361	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
4362	/mask / ~X86_MXCSR_XCPT_MASK,
4363	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_UP,
4364	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4365	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4366	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4367	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4368	/mask / ~X86_MXCSR_XCPT_MASK,
4369	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
4370	/flags / 0, 0 },
4371	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
4372	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4373	{ /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4374	/mask / ~X86_MXCSR_XCPT_MASK,
4375	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
4376	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4377	/** @todo Underflow, Precision; Rounding, FZ etc. */
4378	};
4379
4380	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4381	{
4382	{ bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4383	{ bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4384
4385	{ bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4386	{ bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4387
4388	{ bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4389	{ bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4390	};
4391	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4392	{
4393	{ bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4394	{ bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4395
4396	{ bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4397	{ bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4398
4399	{ bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4400	{ bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4401	};
4402	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4403	{
4404	{ bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4405	{ bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4406
4407	{ bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4408	{ bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4409
4410	{ bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4411	{ bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4412
4413	{ bs3CpuInstr4_mulps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4414	{ bs3CpuInstr4_mulps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4415
4416	{ bs3CpuInstr4_vmulps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4417	{ bs3CpuInstr4_vmulps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4418	};
4419
4420	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4421	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4422	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4423	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4424	}
4425
4426
4427	/*
4428	* [V]MULPD.
4429	*/
4430	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulpd(uint8_t bMode)
4431	{
4432	static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
4433	{
4434	/*
4435	* Zero.
4436	*/
4437	/* 0/{ { /src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4438	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4439	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4440	/mask / X86_MXCSR_XCPT_MASK,
4441	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4442	/flags / 0, 0 },
4443	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4444	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4445	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4446	/mask / ~X86_MXCSR_XCPT_MASK,
4447	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4448	/flags / 0, 0 },
4449	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4450	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4451	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4452	/mask / ~X86_MXCSR_XCPT_MASK,
4453	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4454	/flags / 0, 0 },
4455	{ { /src2 / { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
4456	{ /src1 / { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
4457	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4458	/mask / ~X86_MXCSR_XCPT_MASK,
4459	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
4460	/flags / 0, 0 },
4461	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
4462	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
4463	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4464	/mask / ~X86_MXCSR_XCPT_MASK,
4465	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4466	/flags / 0, 0 },
4467	{ { /src2 / { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
4468	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
4469	{ /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
4470	/mask / X86_MXCSR_XCPT_MASK,
4471	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4472	/flags / 0, 0 },
4473	{ { /src2 / { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } },
4474	{ /src1 / { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } },
4475	{ /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
4476	/mask / X86_MXCSR_XCPT_MASK,
4477	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4478	/flags / 0, 0 },
4479	/*
4480	* Infinity.
4481	*/
4482	/* 7/{ { /src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(1), FP64_0(0) } },
4483	{ /src1 / { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } },
4484	{ /* => */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } },
4485	/mask / ~X86_MXCSR_IM,
4486	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4487	/flags / 0, 0 },
4488	{ { /src2 / { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
4489	{ /src1 / { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
4490	{ /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
4491	/mask / X86_MXCSR_XCPT_MASK,
4492	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4493	/flags / 0, 0 },
4494	{ { /src2 / { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
4495	{ /src1 / { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
4496	{ /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
4497	/mask / ~X86_MXCSR_XCPT_MASK,
4498	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4499	/flags / 0, 0 },
4500	{ { /src2 / { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
4501	{ /src1 / { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
4502	{ /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
4503	/mask / X86_MXCSR_XCPT_MASK,
4504	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4505	/flags / 0, 0 },
4506	{ { /src2 / { FP64_INF(0), FP64_INF(0), FP64_1(0), FP64_INF(0) } },
4507	{ /src1 / { FP64_1(0), FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } },
4508	{ /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
4509	/mask / X86_MXCSR_XCPT_MASK,
4510	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
4511	/flags / 0, 0 },
4512	{ { /src2 / { FP64_INF(1), FP64_INF(0), FP64_NORM_V3(0), FP64_INF(1) } },
4513	{ /src1 / { FP64_1(1), FP64_NORM_V3(1), FP64_INF(1), FP64_NORM_V1(1) } },
4514	{ /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
4515	/mask / X86_MXCSR_XCPT_MASK,
4516	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4517	/flags / 0, 0 },
4518	/*
4519	* Normals.
4520	*/
4521	/13/{ { /src2 / { FP64_V(0, 0xe66f500000000, 0x40d)/31131.828125/, FP64_V(0, 0xaf00000000000, 0x406)/* 215.50/, FP64_V(1, 0x107526e749f80, 0x42b)/-18723145413791.50/, FP64_V(0, 0x6fee0e4bd0000, 0x420)/ 12345678999.62500*/ } },
4522	{ /src1 / { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50/, FP64_V(1, 0x4000000000000, 0x400)/ -2.50/, FP64_V(0, 0xb800000000000, 0x402)/ 13.75000*/ } },
4523	{ /* => / { FP64_V(0, 0xe66f500000000, 0x40d)/31131.828125/, FP64_V(0, 0xfb74e1d800000, 0x41a)/266053390.75/, FP64_V(0, 0x549270a11c760, 0x42c)/ 46807863534478.75/, FP64_V(0, 0x3c30944926c00, 0x424)/169753086244.84375*/ } },
4524	/mask / X86_MXCSR_XCPT_MASK,
4525	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4526	/flags / 0, 0 },
4527	{ { /src2 / { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } },
4528	{ /src1 / { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } },
4529	{ /* => */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } },
4530	/mask / X86_MXCSR_XCPT_MASK,
4531	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
4532	/flags / 0, 0 },
4533	{ { /src2 / { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/244555555308646.00/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/-3025935759.4140625/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/244555555308646/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/121098765432102.75/ } },
4534	{ /src1 / { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75/, FP64_V(1, 0, 0x400)/ -2.0000000/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/ 3.00*/ } },
4535	{ /* => / { FP64_V(0, 0x4da20a80c6990, 0x42e)/183416666481484.50/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/ 6051871518.8281250/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/244555555308646/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/363296296296308.25*/ } },
4536	/mask / X86_MXCSR_XCPT_MASK,
4537	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
4538	/flags / 0, 0 },
4539	{ { /src2 / { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } },
4540	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } },
4541	{ /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
4542	/mask / X86_MXCSR_XCPT_MASK,
4543	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4544	/flags / 0, 0 },
4545	{ { /src2 / { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
4546	{ /src1 / { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } },
4547	{ /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } },
4548	/mask / X86_MXCSR_XCPT_MASK,
4549	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
4550	/flags / 0, 0 },
4551	/** @todo More Normals. */
4552	/*
4553	* Denormals.
4554	*/
4555	/18/{ { /src2 / { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
4556	{ /src1 / { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } },
4557	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4558	/mask / ~X86_MXCSR_XCPT_MASK,
4559	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4560	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4561	{ { /src2 / { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
4562	{ /src1 / { FP64_0(0), FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0) } },
4563	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4564	/mask / ~X86_MXCSR_XCPT_MASK,
4565	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4566	/flags / 0, X86_MXCSR_DE },
4567	{ { /src2 / { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
4568	{ /src1 / { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0) } },
4569	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4570	/mask / X86_MXCSR_XCPT_MASK,
4571	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4572	/flags / 0, 0 },
4573	{ { /src2 / { FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0), FP64_1(0) } },
4574	{ /src1 / { FP64_1(0), FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0) } },
4575	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4576	/mask / X86_MXCSR_XCPT_MASK,
4577	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4578	/flags / 0, 0 },
4579	{ { /src2 / { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
4580	{ /src1 / { FP64_DENORM_MAX(1), FP64_DENORM_MIN(1), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
4581	{ /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
4582	/mask / X86_MXCSR_XCPT_MASK,
4583	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4584	/flags / 0, 0 },
4585	{ { /src2 / { FP64_1(0), FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
4586	{ /src1 / { FP64_NORM_V0(0), FP64_1(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
4587	{ /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } },
4588	/mask / X86_MXCSR_XCPT_MASK,
4589	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4590	/flags / 0, X86_MXCSR_DE \| X86_MXCSR_UE \| X86_MXCSR_PE },
4591	{ { /src2 / { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
4592	{ /src1 / { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
4593	{ /* => */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } },
4594	/mask / ~X86_MXCSR_XCPT_MASK,
4595	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4596	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4597	{ { /src2 / { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
4598	{ /src1 / { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
4599	{ /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
4600	/mask / X86_MXCSR_XCPT_MASK,
4601	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4602	/flags / X86_MXCSR_DE \| X86_MXCSR_UE \| X86_MXCSR_PE, X86_MXCSR_DE \| X86_MXCSR_UE \| X86_MXCSR_PE },
4603	/*
4604	* Overflow, Precision.
4605	*/
4606	/26/{ { /src2 / { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
4607	{ /src1 / { FP64_1(0), FP64_1(0), FP64_1(0), FP64_NORM_MAX(0) } },
4608	{ /* => */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0) } },
4609	/mask / X86_MXCSR_XCPT_MASK,
4610	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4611	/flags / 0, X86_MXCSR_OE \| X86_MXCSR_PE },
4612	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } },
4613	{ /src1 / { FP64_1(0), FP64_NORM_MAX(0), FP64_1(0), FP64_1(0) } },
4614	{ /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_NORM_V3(1), FP64_1(0) } },
4615	/mask / ~X86_MXCSR_XCPT_MASK,
4616	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4617	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
4618	{ { /src2 / { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0) } },
4619	{ /src1 / { FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
4620	{ /* => */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } },
4621	/mask / ~(X86_MXCSR_OE \| X86_MXCSR_PE),
4622	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4623	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
4624	{ { /src2 / { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } },
4625	{ /src1 / { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
4626	{ /* => */ { FP64_INF(0), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0) } },
4627	/mask / X86_MXCSR_OM \| X86_MXCSR_UM \| X86_MXCSR_PM,
4628	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4629	/flags / X86_MXCSR_OE \| X86_MXCSR_UE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_UE \| X86_MXCSR_PE },
4630	{ { /src2 / { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
4631	{ /src1 / { FP64_1(0), FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
4632	{ /* => */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } },
4633	/mask / ~(X86_MXCSR_OE \| X86_MXCSR_PE),
4634	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
4635	/flags / 0, X86_MXCSR_OE \| X86_MXCSR_PE },
4636	{ { /src2 / { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } },
4637	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } },
4638	{ /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
4639	/mask / X86_MXCSR_XCPT_MASK,
4640	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
4641	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
4642	{ { /src2 / { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } },
4643	{ /src1 / { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } },
4644	{ /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
4645	/mask / X86_MXCSR_XCPT_MASK,
4646	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4647	/flags / X86_MXCSR_OE \| X86_MXCSR_PE, X86_MXCSR_OE \| X86_MXCSR_PE },
4648	/*
4649	* Invalids.
4650	*/
4651	/33/{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4652	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4653	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4654	/mask / X86_MXCSR_XCPT_MASK,
4655	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4656	/flags / 0, 0 },
4657	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4658	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4659	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4660	/mask / X86_MXCSR_XCPT_MASK,
4661	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4662	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4663	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4664	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4665	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4666	/mask / X86_MXCSR_XCPT_MASK,
4667	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4668	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4669	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4670	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
4671	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
4672	/mask / X86_MXCSR_XCPT_MASK,
4673	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4674	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4675	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4676	{ /src1 / { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
4677	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4678	/mask / X86_MXCSR_XCPT_MASK,
4679	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4680	/flags / 0, 0 },
4681	{ { /src2 / { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4682	{ /src1 / { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
4683	{ /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4684	/mask / X86_MXCSR_XCPT_MASK,
4685	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4686	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4687	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4688	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4689	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4690	/mask / ~X86_MXCSR_XCPT_MASK,
4691	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4692	/flags / 0, 0 },
4693	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
4694	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
4695	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
4696	/mask / ~X86_MXCSR_XCPT_MASK,
4697	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4698	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4699	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4700	{ /src1 / { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4701	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4702	/mask / ~X86_MXCSR_XCPT_MASK,
4703	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4704	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4705	{ { /src2 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4706	{ /src1 / { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
4707	{ /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4708	/mask / ~X86_MXCSR_XCPT_MASK,
4709	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_UP,
4710	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4711	{ { /src2 / { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4712	{ /src1 / { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
4713	{ /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4714	/mask / ~X86_MXCSR_XCPT_MASK,
4715	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_DOWN,
4716	/flags / 0, 0 },
4717	{ { /src2 / { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4718	{ /src1 / { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
4719	{ /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4720	/mask / ~X86_MXCSR_XCPT_MASK,
4721	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
4722	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4723	/** @todo Underflow, Precision; Rounding, FZ etc. */
4724	};
4725
4726	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4727	{
4728	{ bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4729	{ bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4730
4731	{ bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4732	{ bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4733
4734	{ bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4735	{ bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4736	};
4737	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4738	{
4739	{ bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4740	{ bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4741
4742	{ bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4743	{ bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4744
4745	{ bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4746	{ bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4747	};
4748	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4749	{
4750	{ bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4751	{ bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4752
4753	{ bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4754	{ bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4755
4756	{ bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4757	{ bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4758
4759	{ bs3CpuInstr4_mulpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4760	{ bs3CpuInstr4_mulpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4761
4762	{ bs3CpuInstr4_vmulpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4763	{ bs3CpuInstr4_vmulpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4764	};
4765
4766	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4767	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4768	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4769	g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4770	}
4771
4772
4773	/*
4774	* [V]MULSS.
4775	*/
4776	BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulss(uint8_t bMode)
4777	{
4778	static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
4779	{
4780	/*
4781	* Zero.
4782	*/
4783	/* 0/{ { /src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4784	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4785	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4786	/mask / X86_MXCSR_XCPT_MASK,
4787	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4788	/flags / 0, 0 },
4789	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4790	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4791	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4792	/mask / ~X86_MXCSR_XCPT_MASK,
4793	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4794	/flags / 0, 0 },
4795	{ { /src2 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4796	{ /src1 / { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4797	{ /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4798	/mask / X86_MXCSR_XCPT_MASK,
4799	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4800	/flags / 0, 0 },
4801	{ { /src2 / { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0) } },
4802	{ /src1 / { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } },
4803	{ /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } },
4804	/mask / X86_MXCSR_XCPT_MASK,
4805	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4806	/flags / 0, 0 },
4807	{ { /src2 / { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4808	{ /src1 / { FP32_0(1), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4809	{ /* => */ { FP32_0(0), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4810	/mask / ~X86_MXCSR_XCPT_MASK,
4811	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4812	/flags / 0, 0 },
4813	{ { /src2 / { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4814	{ /src1 / { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4815	{ /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4816	/mask / ~X86_MXCSR_XCPT_MASK,
4817	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
4818	/flags / 0, 0 },
4819	{ { /src2 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4820	{ /src1 / { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
4821	{ /* => */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
4822	/mask / X86_MXCSR_XCPT_MASK,
4823	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
4824	/flags / 0, 0 },
4825	{ { /src2 / { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4826	{ /src1 / { FP32_1(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
4827	{ /* => */ { FP32_0(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
4828	/mask / X86_MXCSR_XCPT_MASK,
4829	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4830	/flags / 0, 0 },
4831	/*
4832	* Infinity.
4833	*/
4834	/* 8/{ { /src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4835	{ /src1 / { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4836	{ /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4837	/mask / ~X86_MXCSR_IM,
4838	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4839	/flags / 0, 0 },
4840	{ { /src2 / { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4841	{ /src1 / { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4842	{ /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4843	/mask / X86_MXCSR_XCPT_MASK,
4844	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4845	/flags / 0, 0 },
4846	{ { /src2 / { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4847	{ /src1 / { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4848	{ /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4849	/mask / ~X86_MXCSR_IM,
4850	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4851	/flags / 0, 0 },
4852	{ { /src2 / { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4853	{ /src1 / { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4854	{ /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4855	/mask / X86_MXCSR_XCPT_MASK,
4856	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
4857	/flags / 0, 0 },
4858	{ { /src2 / { FP32_1(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4859	{ /src1 / { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
4860	{ /* => */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
4861	/mask / X86_MXCSR_XCPT_MASK,
4862	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4863	/flags / 0, 0 },
4864	{ { /src2 / { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },
4865	{ /src1 / { FP32_1(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
4866	{ /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
4867	/mask / ~X86_MXCSR_XCPT_MASK,
4868	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4869	/flags / 0, 0 },
4870	{ { /src2 / { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
4871	{ /src1 / { FP32_INF(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
4872	{ /* => */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
4873	/mask / ~X86_MXCSR_XCPT_MASK,
4874	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4875	/flags / 0, 0 },
4876	/*
4877	* Normals.
4878	*/
4879	/15/{ { /src2 / { FP32_V(0, 0x600000, 0x7f)/1.7500/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4880	{ /src1 / { FP32_V(0, 0, 0x7d)/0.2500/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
4881	{ /* => / { FP32_V(0, 0x600000, 0x7d)/0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
4882	/mask / X86_MXCSR_XCPT_MASK,
4883	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4884	/flags / 0, 0 },
4885	{ { /src2 / { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4886	{ /src1 / { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4887	{ /* => / { FP32_V(0, 0x37be78, 0x95)/6020924*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4888	/mask / X86_MXCSR_XCPT_MASK,
4889	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4890	/flags / 0, 0 },
4891	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4892	{ /src1 / { FP32_1(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4893	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4894	/mask / X86_MXCSR_XCPT_MASK,
4895	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4896	/flags / 0, 0 },
4897	{ { /src2 / { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4898	{ /src1 / { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4899	{ /* => / { FP32_V(0, 0x37be78, 0x95)/6020924*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4900	/mask / X86_MXCSR_XCPT_MASK,
4901	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_UP,
4902	/flags / 0, 0 },
4903	{ { /src2 / { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4904	{ /src1 / { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
4905	{ /* => / { FP32_V(0, 0x30eaa1, 0x93)/1449300.1250*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
4906	/mask / X86_MXCSR_XCPT_MASK,
4907	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4908	/flags / 0, 0 },
4909	{ { /src2 / { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } },
4910	{ /src1 / { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V6(0), FP32_RAND_V1(1) } },
4911	{ /* => / { FP32_V(1, 0x39f7d1, 0x96)/-12187601.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V1(1) } },
4912	/mask / ~X86_MXCSR_XCPT_MASK,
4913	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4914	/flags / 0, 0 },
4915	{ { /src2 / { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
4916	{ /src1 / { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
4917	{ /* => */ { FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
4918	/mask / ~X86_MXCSR_XCPT_MASK,
4919	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4920	/flags / 0, 0 },
4921	{ { /src2 / { FP32_V(0, 0x23b6a0, 0x8e)/41910.625000/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
4922	{ /src1 / { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
4923	{ /* => / { FP32_V(0, 0x23b6a0, 0x8b)/ 5238.828125*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
4924	/mask / ~X86_MXCSR_XCPT_MASK,
4925	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4926	/flags / 0, 0 },
4927	{ { /src2 / { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
4928	{ /src1 / { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } },
4929	{ /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } },
4930	/mask / X86_MXCSR_XCPT_MASK,
4931	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4932	/flags / 0, 0 },
4933	/** @todo More Normals. */
4934	/*
4935	* Denormals.
4936	*/
4937	/24/{ { /src2 / { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
4938	{ /src1 / { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
4939	{ /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
4940	/mask / ~X86_MXCSR_XCPT_MASK,
4941	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4942	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4943	{ { /src2 / { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
4944	{ /src1 / { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
4945	{ /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
4946	/mask / ~X86_MXCSR_XCPT_MASK,
4947	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4948	/flags / X86_MXCSR_DE, X86_MXCSR_DE },
4949	{ { /src2 / { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } },
4950	{ /src1 / { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
4951	{ /* => */ { FP32_0(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
4952	/mask / X86_MXCSR_XCPT_MASK,
4953	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
4954	/flags / 0, 0 },
4955	{ { /src2 / { FP32_DENORM_MIN(0), FP32_1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } },
4956	{ /src1 / { FP32_DENORM_MAX(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
4957	{ /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
4958	/mask / X86_MXCSR_XCPT_MASK,
4959	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4960	/flags / 0, 0 },
4961	/** @todo More Denormals. */
4962	/*
4963	* Invalids.
4964	*/
4965	/* QNan, QNan (Masked). */
4966	/28/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4967	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4968	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4969	/mask / X86_MXCSR_XCPT_MASK,
4970	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4971	/flags / 0, 0 },
4972	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4973	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4974	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4975	/mask / X86_MXCSR_XCPT_MASK,
4976	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4977	/flags / 0, 0 },
4978	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4979	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4980	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4981	/mask / X86_MXCSR_XCPT_MASK,
4982	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4983	/flags / 0, 0 },
4984	/* QNan, SNan (Masked). */
4985	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4986	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4987	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4988	/mask / X86_MXCSR_XCPT_MASK,
4989	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4990	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4991	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4992	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4993	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4994	/mask / X86_MXCSR_XCPT_MASK,
4995	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
4996	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
4997	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4998	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4999	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5000	/mask / X86_MXCSR_XCPT_MASK,
5001	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5002	/flags / 0, 0 },
5003	/* SNan, QNan (Masked). */
5004	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5005	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5006	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5007	/mask / X86_MXCSR_XCPT_MASK,
5008	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5009	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5010	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5011	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5012	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5013	/mask / X86_MXCSR_XCPT_MASK,
5014	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5015	/flags / 0, 0 },
5016	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5017	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5018	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5019	/mask / X86_MXCSR_XCPT_MASK,
5020	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5021	/flags / 0, 0 },
5022	/* SNan, SNan (Masked). */
5023	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5024	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5025	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5026	/mask / X86_MXCSR_XCPT_MASK,
5027	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5028	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5029	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5030	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5031	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5032	/mask / X86_MXCSR_XCPT_MASK,
5033	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5034	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5035	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5036	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5037	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5038	/mask / X86_MXCSR_XCPT_MASK,
5039	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5040	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5041	/* QNan, Norm FP (Masked). */
5042	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5043	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5044	{ /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5045	/mask / X86_MXCSR_XCPT_MASK,
5046	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5047	/flags / 0, 0 },
5048	/* SNan, Norm FP (Masked). */
5049	{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
5050	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5051	{ /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5052	/mask / X86_MXCSR_XCPT_MASK,
5053	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5054	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5055	/* QNan, QNan (Unmasked). */
5056	/44/{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5057	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5058	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5059	/mask / ~X86_MXCSR_XCPT_MASK,
5060	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5061	/flags / 0, 0 },
5062	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5063	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5064	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5065	/mask / ~X86_MXCSR_XCPT_MASK,
5066	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5067	/flags / 0, 0 },
5068	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5069	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5070	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5071	/mask / ~X86_MXCSR_XCPT_MASK,
5072	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5073	/flags / 0, 0 },
5074
5075	/* QNan, SNan (Unmasked). */
5076	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5077	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5078	{ /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5079	/mask / ~X86_MXCSR_XCPT_MASK,
5080	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_NEAREST,
5081	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5082	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5083	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5084	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5085	/mask / ~X86_MXCSR_XCPT_MASK,
5086	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
5087	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5088	{ { /src2 / { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5089	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5090	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5091	/mask / ~X86_MXCSR_XCPT_MASK,
5092	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5093	/flags / 0, 0 },
5094	/* SNan, QNan (Unmasked). */
5095	{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5096	{ /src1 / { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5097	{ /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5098	/mask / ~X86_MXCSR_XCPT_MASK,
5099	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
5100	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5101	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5102	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5103	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5104	/mask / ~X86_MXCSR_XCPT_MASK,
5105	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_UP,
5106	/flags / 0, 0 },
5107	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5108	{ /src1 / { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5109	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5110	/mask / ~X86_MXCSR_XCPT_MASK,
5111	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
5112	/flags / 0, 0 },
5113	/* SNan, SNan (Unmasked). */
5114	/54/{ { /src2 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5115	{ /src1 / { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5116	{ /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5117	/mask / ~X86_MXCSR_XCPT_MASK,
5118	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
5119	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5120	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5121	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5122	{ /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5123	/mask / ~X86_MXCSR_XCPT_MASK,
5124	/daz,fz,rc/ 0, 0, X86_MXCSR_RC_ZERO,
5125	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5126	{ { /src2 / { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5127	{ /src1 / { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5128	{ /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5129	/mask / ~X86_MXCSR_XCPT_MASK,
5130	/daz,fz,rc/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
5131	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5132	/* QNan, Norm FP (Unmasked). */
5133	{ { /src2 / { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5134	{ /src1 / { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5135	{ /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5136	/mask / ~X86_MXCSR_XCPT_MASK,
5137	/daz,fz,rc/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
5138	/flags / 0, 0 },
5139	/* SNan, Norm FP (Unmasked). */
5140	/58/{ { /src2 / { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
5141	{ /src1 / { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5142	{ /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5143	/mask / ~X86_MXCSR_XCPT_MASK,
5144	/daz,fz,rc/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5145	/flags / X86_MXCSR_IE, X86_MXCSR_IE },
5146	/** @todo Underflow, Precision; Rounding, FZ etc. */
5147	};
5148
5149	static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
5150	{
5151	{ bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5152	{ bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5153
5154	{ bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5155	{ bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5156	};
5157	static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
5158	{
5159	{ bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5160	{ bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5161
5162	{ bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5163	{ bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5164	};
5165	static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
5166	{
5167	{ bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5168	{ bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5169
5170	{ bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5171	{ bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5172
5173	{ bs3CpuInstr4_mulss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5174	{ bs3CpuInstr4_mulss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5175	};
5176
5177	static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5178	unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
5179	return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5180	g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
5181	}
5182	#endif
5183
5184
5185	/**
5186	* The 32-bit protected mode main function.
5187	*
5188	* The tests a driven by 32-bit test drivers, even for real-mode tests (though
5189	* we'll switch between PE32 and RM for each test step we perform). Given that
5190	* we test SSE and AVX here, we don't need to worry about 286 or 8086.
5191	*
5192	* Some extra steps needs to be taken to properly handle extended state in LM64
5193	* (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode
5194	* (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm).
5195	*/
5196	BS3_DECL(void) Main_pe32()
5197	{
5198	static const BS3TESTMODEBYONEENTRY g_aTests[] =
5199	{
5200	#if 1 /ndef DEBUG_bird/
5201	# define ALL_TESTS
5202	#endif
5203	#if defined(ALL_TESTS)
5204	{ "[v]addps", bs3CpuInstr4_v_addps, 0 },
5205	{ "[v]addpd", bs3CpuInstr4_v_addpd, 0 },
5206	{ "[v]addss", bs3CpuInstr4_v_addss, 0 },
5207	{ "[v]haddps", bs3CpuInstr4_v_haddps, 0 },
5208	{ "[v]subps", bs3CpuInstr4_v_subps, 0 },
5209	# if 0
5210	{ "[v]subpd", bs3CpuInstr4_v_subpd, 0 },
5211	{ "[v]subss", bs3CpuInstr4_v_subss, 0 },
5212	{ "[v]mulps", bs3CpuInstr4_v_mulps, 0 },
5213	{ "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 },
5214	{ "[v]mulss", bs3CpuInstr4_v_mulss, 0 },
5215	# endif
5216	#endif
5217	};
5218	Bs3TestInit("bs3-cpu-instr-4");
5219
5220	/*
5221	* Initialize globals.
5222	*/
5223	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
5224	{
5225	uint32_t fEbx, fEcx, fEdx;
5226	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
5227	g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX);
5228	g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
5229	g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
5230	g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3);
5231	g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
5232	g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
5233	g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3);
5234	g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3);
5235	g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
5236	g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
5237	g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
5238	g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
5239	g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
5240	g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL)
5241	&& RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
5242
5243	if (ASMCpuId_EAX(0) >= 7)
5244	{
5245	ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL);
5246	g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
5247	g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
5248	g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA);
5249	}
5250
5251	if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES)
5252	{
5253	ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
5254	g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5255	g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5256	g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5257	}
5258	g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] \|\| g_afTypeSupports[T_SSE];
5259
5260	/*
5261	* Figure out FPU save/restore method and support for DAZ bit.
5262	*/
5263	{
5264	/** @todo Add bs3kit API to just get the ext ctx method without needing to
5265	* alloc/free a context. Replicating the logic in the bs3kit here, though
5266	* doable, runs a risk of not updating this when the other logic is
5267	* changed. */
5268	uint64_t fFlags;
5269	uint16_t const cbExtCtx = Bs3ExtCtxGetSize(&fFlags);
5270	PBS3EXTCTX pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cbExtCtx);
5271	if (pExtCtx)
5272	{
5273	Bs3ExtCtxInit(pExtCtx, cbExtCtx, fFlags);
5274	g_enmExtCtxMethod = pExtCtx->enmMethod;
5275	if ( ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_XSAVE
5276	&& (pExtCtx->Ctx.x.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
5277	\|\| ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_FXSAVE)
5278	&& (pExtCtx->Ctx.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
5279	g_fMxCsrDazSupported = true;
5280	}
5281	else
5282	Bs3TestFailedF("Failed to allocate %u bytes for extended CPU context (tiled addressable)\n", cbExtCtx);
5283	}
5284
5285	/*
5286	* Allocate a buffer for testing.
5287	*/
5288	g_cbBuf = X86_PAGE_SIZE * 4;
5289	g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf);
5290	if (g_pbBuf)
5291	{
5292	g_pbBufAliasAlloc = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_TILED, g_cbBuf);
5293	if (g_pbBufAliasAlloc)
5294	{
5295	/*
5296	* Do the tests.
5297	*/
5298	Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY);
5299	#ifdef BS3_SKIPIT_DO_SKIP
5300	bs3CpuInstrX_ShowTallies();
5301	#endif
5302	}
5303	else
5304	Bs3TestFailed("Failed to allocate 16K alias buffer (tiled addressable)");
5305	}
5306	else
5307	Bs3TestFailed("Failed to allocate 16K buffer (real mode addressable)");
5308	}
5309
5310	Bs3TestTerm();
5311	}
5312

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