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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32@ 105614

Last change on this file since 105614 was 105614, checked in by vboxsync, 6 months ago

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]addsd.
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1/* $Id: bs3-cpu-instr-4.c32 105614 2024-08-07 14:37:58Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-instr-4 - SSE, AVX FPU instructions, C code template.
4 */
5
6/*
7 * Copyright (C) 2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
41#include <bs3kit.h>
42#include "bs3-cpu-instr-4-asm-auto.h"
43
44#include <iprt/asm.h>
45#include <iprt/asm-amd64-x86.h>
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51/** Converts an execution mode (BS3_MODE_XXX) into an index into an array
52 * initialized by BS3CPUINSTR4_TEST1_MODES_INIT etc. */
53#define BS3CPUINSTR4_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2)
54
55/** Maximum length for the names of all SIMD FP exception flags combined. */
56#define FP_XCPT_FLAGS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
57/** Maximum length for the names of all SIMD FP exception masks combined. */
58#define FP_XCPT_MASKS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
59/** Maximum length for the names of all SIMD FP exception other bits combined. */
60#define FP_XCPT_OTHERS_NAMES_MAXLEN sizeof(" DAZ FZ MM RC=NEAREST ")
61
62/*
63 * Single-precision (32 bits) floating-point defines.
64 */
65/** The max exponent value for a single-precision floating-point normal. */
66#define FP32_EXP_NORM_MAX 254
67/** The min exponent value for a single-precision floating-point normal. */
68#define FP32_EXP_NORM_MIN 1
69/** The max fraction value for a single-precision floating-point normal. */
70#define FP32_FRAC_NORM_MAX 0x7fffff
71/** The min fraction value for a single-precision floating-point normal. */
72#define FP32_FRAC_NORM_MIN 0
73/** The exponent bias for the single-precision floating-point format. */
74#define FP32_EXP_BIAS RTFLOAT32U_EXP_BIAS
75/** Fraction width (in bits) for the single-precision floating-point format. */
76#define FP32_FRAC_BITS RTFLOAT32U_FRACTION_BITS
77/** The max exponent value for a single-precision floating-point integer without
78 * losing precision. */
79#define FP32_EXP_SAFE_INT_MAX FP32_EXP_BIAS + FP32_FRAC_BITS
80/** The min exponent value for a single-precision floating-point integer without
81 * losing precision. */
82#define FP32_EXP_SAFE_INT_MIN 1
83/** The max fraction value for a double-precision floating-point denormal. */
84#define FP32_FRAC_DENORM_MAX 0x7fffff
85/** The min fraction value for a double-precision floating-point denormal. */
86#define FP32_FRAC_DENORM_MIN 1
87
88#define FP32_NORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_NORM_MAX)
89#define FP32_NORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN)
90#define FP32_0(a_Sign) RTFLOAT32U_INIT_ZERO(a_Sign)
91#define FP32_1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0, RTFLOAT32U_EXP_BIAS)
92#define FP32_V(a_Sign, a_Frac, a_Exp) RTFLOAT32U_INIT_C(a_Sign, a_Frac, a_Exp)
93#define FP32_INF(a_Sign) RTFLOAT32U_INIT_INF(a_Sign)
94#define FP32_QNAN(a_Sign) RTFLOAT32U_INIT_QNAN(a_Sign)
95#define FP32_QNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val)
96#define FP32_SNAN(a_Sign) RTFLOAT32U_INIT_SNAN(a_Sign)
97#define FP32_SNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_SNAN_EX(a_Sign, a_Val)
98
99/*
100 * Single-precision floating normals.
101 * Fraction - 23 bits, all usable.
102 * Exponent - 8 bits, least significant bit MBZ.
103 */
104#define FP32_FRAC_V0 0x401ac0
105#define FP32_FRAC_V1 0x5fcabd
106#define FP32_FRAC_V2 0x7e117a
107#define FP32_FRAC_V3 0x5b5b5b
108#define FP32_FRAC_V4 0x1e0f1f
109#define FP32_FRAC_V5 0x012345
110#define FP32_FRAC_V6 0x330b3b
111#define FP32_FRAC_V7 0x4ebeb4
112#define FP32_EXP_V0 0x78
113#define FP32_EXP_V1 0xbc
114#define FP32_EXP_V2 0x7e
115#define FP32_EXP_V3 0x9a
116#define FP32_EXP_V4 0x32
117#define FP32_EXP_V5 0x56
118#define FP32_EXP_V6 0x90
119#define FP32_EXP_V7 0x30
120AssertCompile(!(FP32_EXP_V0 & RT_BIT(0)));
121AssertCompile(!(FP32_EXP_V1 & RT_BIT(0)));
122AssertCompile(!(FP32_EXP_V2 & RT_BIT(0)));
123AssertCompile(!(FP32_EXP_V3 & RT_BIT(0)));
124AssertCompile(!(FP32_EXP_V4 & RT_BIT(0)));
125AssertCompile(!(FP32_EXP_V5 & RT_BIT(0)));
126AssertCompile(!(FP32_EXP_V6 & RT_BIT(0)));
127AssertCompile(!(FP32_EXP_V7 & RT_BIT(0)));
128#define FP32_NORM_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V0, FP32_EXP_V0)
129#define FP32_NORM_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V1, FP32_EXP_V1)
130#define FP32_NORM_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V2, FP32_EXP_V2)
131#define FP32_NORM_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V3, FP32_EXP_V3)
132#define FP32_NORM_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V4, FP32_EXP_V4)
133#define FP32_NORM_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V5, FP32_EXP_V5)
134#define FP32_NORM_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V6, FP32_EXP_V6)
135#define FP32_NORM_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V7, FP32_EXP_V7)
136/* The maximum integer value (all 23 + 1 implied bit of the fraction part set) without losing precision. */
137#define FP32_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX)
138/* The minimum integer value without losing precision. */
139#define FP32_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_SAFE_INT_MIN)
140
141/*
142 * Single-precision floating-point denormals.
143 */
144/** The maximum denormal value. */
145#define FP32_DENORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MAX, 0)
146/** The maximum denormal value. */
147#define FP32_DENORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MIN, 0)
148
149/*
150 * Single-precision random values (incl. potentially invalid values).
151 * We don't care what the exact values are as these are meant to populate
152 * unmodified parts of operands and be compared bitwise.
153 */
154#define FP32_RAND_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7bacda, 0x55)
155#define FP32_RAND_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7010f0, 0xc0)
156#define FP32_RAND_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x4ffcbe, 0xf1)
157#define FP32_RAND_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x2fd7c8, 0x1f)
158#define FP32_RAND_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5b5b5b, 0x09)
159#define FP32_RAND_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x3d2d1d, 0x99)
160#define FP32_RAND_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x123456, 0x5e)
161#define FP32_RAND_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x05432f, 0xd7)
162
163/*
164 * Double-precision (64 bits) floating-point defines.
165 */
166/** The max exponent value for a double-precision floating-point normal. */
167#define FP64_EXP_NORM_MAX 2046
168/** The min exponent value for a double-precision floating-point normal. */
169#define FP64_EXP_NORM_MIN 1
170/** The max fraction value for a double-precision floating-point normal. */
171#define FP64_FRAC_NORM_MAX 0xfffffffffffff
172/** The min fraction value for a double-precision floating-point normal. */
173#define FP64_FRAC_NORM_MIN 0
174/** The exponent bias for the double-precision floating-point format. */
175#define FP64_EXP_BIAS RTFLOAT64U_EXP_BIAS
176/** Fraction width (in bits) for the double-precision floating-point format. */
177#define FP64_FRAC_BITS RTFLOAT64U_FRACTION_BITS
178/** The max exponent value for a double-precision floating-point integer without
179 * losing precision. */
180#define FP64_EXP_SAFE_INT_MAX FP64_EXP_BIAS + FP64_FRAC_BITS
181/** The min exponent value for a double-precision floating-point integer without
182 * losing precision. */
183#define FP64_EXP_SAFE_INT_MIN 1
184/** The max fraction value for a double-precision floating-point denormal. */
185#define FP64_FRAC_DENORM_MAX 0xfffffffffffff
186/** The min fraction value for a double-precision floating-point denormal. */
187#define FP64_FRAC_DENORM_MIN 1
188
189#define FP64_NORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX)
190#define FP64_NORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_NORM_MIN)
191#define FP64_0(a_Sign) RTFLOAT64U_INIT_ZERO(a_Sign)
192#define FP64_1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0, RTFLOAT64U_EXP_BIAS)
193#define FP64_V(a_Sign, a_Frac, a_Exp) RTFLOAT64U_INIT_C(a_Sign, a_Frac, a_Exp)
194#define FP64_INF(a_Sign) RTFLOAT64U_INIT_INF(a_Sign)
195#define FP64_QNAN(a_Sign) RTFLOAT64U_INIT_QNAN(a_Sign)
196#define FP64_QNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val)
197#define FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign)
198#define FP64_SNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val)
199
200/*
201 * Double-precision random values (incl. potentially invalid values).
202 * We don't care what the exact values are as these are meant to populate
203 * unmodified parts of operands and be compared bitwise.
204 */
205#define FP64_RAND_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xab07eb7bcebce, 0x777)
206#define FP64_RAND_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x2fa17e10b3c7c, 0x6b6)
207#define FP64_RAND_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xceb1703cbe310, 0x100)
208#define FP64_RAND_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x7134abcdef10f, 0x70f)
209
210/*
211 * Double-precision floating-point normals.
212 * Fraction - 52 bits, all usable.
213 * Exponent - 11 bits, least significant bit MBZ.
214 */
215#define FP64_FRAC_V0 0xacc01adec0de5
216#define FP64_FRAC_V1 0xf10a7ab1ec01a
217#define FP64_FRAC_V2 0xca5cadea1b1ed
218#define FP64_FRAC_V3 0xb5b5b5b5b5b5b
219#define FP64_EXP_V0 0x30c
220#define FP64_EXP_V1 0x4bc
221#define FP64_EXP_V2 0x3ae
222#define FP64_EXP_V3 0x7fe
223AssertCompile(!(FP64_EXP_V0 & RT_BIT(0)));
224AssertCompile(!(FP64_EXP_V1 & RT_BIT(0)));
225AssertCompile(!(FP64_EXP_V2 & RT_BIT(0)));
226AssertCompile(!(FP64_EXP_V3 & RT_BIT(0)));
227#define FP64_NORM_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V0, FP64_EXP_V0)
228#define FP64_NORM_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V1, FP64_EXP_V1)
229#define FP64_NORM_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V2, FP64_EXP_V2)
230#define FP64_NORM_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V3, FP64_EXP_V3)
231/* The maximum integer value (all 52 + 1 implied bit of the fraction part set) without losing precision. */
232#define FP64_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX)
233/* The minimum integer value without losing precision. */
234#define FP64_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_SAFE_INT_MIN)
235
236/*
237 * Double-precision floating-point denormals.
238 */
239/** The maximum denormal value. */
240#define FP64_DENORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MAX, 0)
241/** The maximum denormal value. */
242#define FP64_DENORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MIN, 0)
243
244
245/*********************************************************************************************************************************
246* Structures and Typedefs *
247*********************************************************************************************************************************/
248/** Instruction set type and operand width. */
249typedef enum BS3CPUINSTRX_INSTRTYPE_T
250{
251 T_INVALID,
252 T_MMX,
253 T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */
254 T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */
255 T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */
256 T_AXMMX,
257 T_AXMMX_OR_SSE,
258 T_SSE,
259 T_128BITS = T_SSE,
260 T_SSE2,
261 T_SSE3,
262 T_SSSE3,
263 T_SSE4_1,
264 T_SSE4_2,
265 T_SSE4A,
266 T_PCLMUL,
267 T_SHA,
268 T_AVX_128,
269 T_AVX2_128,
270 T_AVX_PCLMUL,
271 T_AVX_256,
272 T_256BITS = T_AVX_256,
273 T_AVX2_256,
274 T_MAX
275} BS3CPUINSTRX_INSTRTYPE_T;
276
277/** Memory or register rm variant. */
278enum {
279 RM_REG = 0,
280 RM_MEM,
281 RM_MEM8, /**< Memory operand is 8 bytes. Hack for movss and similar. */
282 RM_MEM16, /**< Memory operand is 16 bytes. Hack for movss and similar. */
283 RM_MEM32, /**< Memory operand is 32 bytes. Hack for movss and similar. */
284 RM_MEM64 /**< Memory operand is 64 bytes. Hack for movss and similar. */
285};
286
287/**
288 * Execution environment configuration.
289 */
290typedef struct BS3CPUINSTR4_CONFIG_T
291{
292 uint16_t fCr0Mp : 1;
293 uint16_t fCr0Em : 1;
294 uint16_t fCr0Ts : 1;
295 uint16_t fCr4OsFxSR : 1;
296 uint16_t fCr4OsXSave : 1;
297 uint16_t fCr4OsXmmExcpt : 1;
298 uint16_t fXcr0Sse : 1;
299 uint16_t fXcr0Avx : 1;
300 uint16_t fAligned : 1; /**< Aligned mem operands. If 0, they will be misaligned and tests w/o mem operands skipped. */
301 uint16_t fAlignCheck : 1;
302 uint16_t fMxCsrMM : 1; /**< AMD only */
303 uint8_t bXcptSse;
304 uint8_t bXcptAvx;
305} BS3CPUINSTR4_CONFIG_T;
306/** Pointer to an execution environment configuration. */
307typedef BS3CPUINSTR4_CONFIG_T const BS3_FAR *PCBS3CPUINSTR4_CONFIG_T;
308
309/** State saved by bs3CpuInstr4ConfigReconfigure. */
310typedef struct BS3CPUINSTRX_CONFIG_SAVED_T
311{
312 uint32_t uCr0;
313 uint32_t uCr4;
314 uint32_t uEfl;
315 uint16_t uFcw;
316 uint16_t uFsw;
317 uint32_t uMxCsr;
318} BS3CPUINSTRX_CONFIG_SAVED_T;
319typedef BS3CPUINSTRX_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTRX_CONFIG_SAVED_T;
320typedef BS3CPUINSTRX_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTRX_CONFIG_SAVED_T;
321
322/**
323 * YMM packed single-precision floating-point register.
324 * @todo move to x86.h?
325 */
326typedef union X86YMMFLOATPSREG
327{
328 /** Packed single-precision floating-point view. */
329 RTFLOAT32U ar32[8];
330 /** 256-bit integer view. */
331 RTUINT256U ymm;
332} X86YMMFLOATPSREG;
333# ifndef VBOX_FOR_DTRACE_LIB
334AssertCompileSize(X86YMMFLOATPSREG, 32);
335AssertCompileSize(X86YMMFLOATPSREG, sizeof(X86YMMREG));
336# endif
337/** Pointer to a YMM packed single-precision floating-point register. */
338typedef X86YMMFLOATPSREG BS3_FAR *PX86YMMFLOATPSREG;
339/** Pointer to a const YMM single-precision packed floating-point register. */
340typedef X86YMMFLOATPSREG const BS3_FAR *PCX86YMMFLOATPSREG;
341
342/**
343 * YMM packed double-precision floating-point register.
344 * @todo move to x86.h?
345 */
346typedef union X86YMMFLOATPDREG
347{
348 /** Packed double-precision floating-point view. */
349 RTFLOAT64U ar64[4];
350 /** 256-bit integer view. */
351 RTUINT256U ymm;
352} X86YMMFLOATPDREG;
353# ifndef VBOX_FOR_DTRACE_LIB
354AssertCompileSize(X86YMMFLOATPDREG, 32);
355AssertCompileSize(X86YMMFLOATPDREG, sizeof(X86YMMREG));
356# endif
357/** Pointer to a YMM packed floating-point register. */
358typedef X86YMMFLOATPDREG BS3_FAR *PX86YMMFLOATPDREG;
359/** Pointer to a const YMM packed floating-point register. */
360typedef X86YMMFLOATPDREG const BS3_FAR *PCX86YMMFLOATPDREG;
361
362/**
363 * YMM scalar single-precision floating-point register.
364 * @todo move to x86.h?
365 */
366typedef union X86YMMFLOATSSREG
367{
368 /** Scalar single-precision floating-point view. */
369 RTFLOAT32U ar32[8];
370 /** 256-bit integer view. */
371 RTUINT256U ymm;
372} X86YMMFLOATSSREG;
373# ifndef VBOX_FOR_DTRACE_LIB
374AssertCompileSize(X86YMMFLOATSSREG, 32);
375AssertCompileSize(X86YMMFLOATSSREG, sizeof(X86YMMREG));
376# endif
377/** Pointer to a YMM scalar single-precision floating-point register. */
378typedef X86YMMFLOATSSREG BS3_FAR *PX86YMMFLOATSSREG;
379/** Pointer to a const YMM scalar single-precision floating-point register. */
380typedef X86YMMFLOATSSREG const BS3_FAR *PCX86YMMFLOATSSREG;
381
382/**
383 * YMM scalar double-precision floating-point register.
384 * @todo move to x86.h?
385 */
386typedef union X86YMMFLOATSDREG
387{
388 /** Scalar double-precision floating-point view. */
389 RTFLOAT64U ar64[4];
390 /** 256-bit integer view. */
391 RTUINT256U ymm;
392} X86YMMFLOATSDREG;
393# ifndef VBOX_FOR_DTRACE_LIB
394AssertCompileSize(X86YMMFLOATSDREG, 32);
395AssertCompileSize(X86YMMFLOATSDREG, sizeof(X86YMMREG));
396# endif
397/** Pointer to a YMM scalar double-precision floating-point register. */
398typedef X86YMMFLOATSDREG BS3_FAR *PX86YMMFLOATSDREG;
399/** Pointer to a const YMM scalar double-precision floating-point register. */
400typedef X86YMMFLOATSDREG const BS3_FAR *PCX86YMMFLOATSDREG;
401
402/**
403 * YMM scalar quadruple-precision floating-point register.
404 * @todo move to x86.h?
405 */
406typedef union X86YMMFLOATSQREG
407{
408 /** Scalar quadruple-precision floating point view. */
409 RTFLOAT128U ar128[2];
410 /** 256-bit integer view. */
411 RTUINT256U ymm;
412} X86YMMFLOATSQREG;
413# ifndef VBOX_FOR_DTRACE_LIB
414AssertCompileSize(X86YMMFLOATSQREG, 32);
415AssertCompileSize(X86YMMFLOATSQREG, sizeof(X86YMMREG));
416# endif
417/** Pointer to a YMM scalar quadruple-precision floating-point register. */
418typedef X86YMMFLOATSQREG *PX86YMMFLOATSQREG;
419/** Pointer to a const YMM scalar quadruple-precision floating-point register. */
420typedef X86YMMFLOATSQREG const *PCX86YMMFLOATSQREG;
421
422
423/*********************************************************************************************************************************
424* Global Variables *
425*********************************************************************************************************************************/
426static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false };
427static bool g_fAmdMisalignedSse = false;
428static uint8_t g_enmExtCtxMethod = BS3EXTCTXMETHOD_INVALID;
429static bool g_fMxCsrDazSupported = false;
430
431/** Size of g_pbBuf - at least three pages. */
432static uint32_t g_cbBuf;
433/** Buffer of g_cbBuf size. */
434static uint8_t BS3_FAR *g_pbBuf;
435/** RW alias for the buffer memory at g_pbBuf. Set up by bs3CpuInstrXBufSetup. */
436static uint8_t BS3_FAR *g_pbBufAlias;
437/** RW alias for the memory at g_pbBuf. */
438static uint8_t BS3_FAR *g_pbBufAliasAlloc;
439
440/** Exception type \#2 test configurations, 16 & 32 bytes strictly aligned. */
441static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig2[] =
442{
443/*
444 * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
445 * +AVX +AVX +AMD/SSE +AMD/SSE
446 * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
447 * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
448 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
449 { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
450 { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
451 { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
452 { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
453 { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
454 { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
455 { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
456 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
457 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
458 /* Memory misalignment and alignment checks: */
459 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
460 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #11 */
461 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
462 /* AMD only: */
463 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
464 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
465};
466
467/** Exception type \#3 test configurations (< 16-byte memory argument). */
468static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig3[] =
469{
470/*
471 * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
472 * +AVX +AVX +AMD/SSE +AMD/SSE
473 * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
474 * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
475 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
476 { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
477 { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
478 { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
479 { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
480 { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
481 { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
482 { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
483 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
484 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
485 /* Memory misalignment and alignment checks: */
486 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* [Avx]:DB */
487 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */ /* [Avx]:AC */
488 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
489 /* AMD only: */
490 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
491 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
492};
493
494
495/**
496 * Returns the name of an X86 exception given the vector.
497 *
498 * @returns Name of the exception.
499 * @param uVector The exception vector.
500 */
501static const char BS3_FAR *bs3CpuInstr4XcptName(uint8_t uVector)
502{
503 switch (uVector)
504 {
505 case X86_XCPT_DE: return "#DE";
506 case X86_XCPT_DB: return "#DB";
507 case X86_XCPT_NMI: return "#NMI";
508 case X86_XCPT_BP: return "#BP";
509 case X86_XCPT_OF: return "#OF";
510 case X86_XCPT_BR: return "#BR";
511 case X86_XCPT_UD: return "#UD";
512 case X86_XCPT_NM: return "#NM";
513 case X86_XCPT_DF: return "#DF";
514 case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
515 case X86_XCPT_TS: return "#TS";
516 case X86_XCPT_NP: return "#NP";
517 case X86_XCPT_SS: return "#SS";
518 case X86_XCPT_GP: return "#GP";
519 case X86_XCPT_PF: return "#PF";
520 case X86_XCPT_MF: return "#MF";
521 case X86_XCPT_AC: return "#AC";
522 case X86_XCPT_MC: return "#MC";
523 case X86_XCPT_XF: return "#XF";
524 case X86_XCPT_VE: return "#VE";
525 case X86_XCPT_CP: return "#CP";
526 case X86_XCPT_VC: return "#VC";
527 case X86_XCPT_SX: return "#SX";
528 }
529 return "UNKNOWN";
530}
531
532
533DECL_FORCE_INLINE(bool) bs3CpuInstr4IsSse(uint8_t enmType)
534{
535 return enmType >= T_SSE && enmType < T_AVX_128;
536}
537
538
539DECL_FORCE_INLINE(bool) bs3CpuInstr4IsAvx(uint8_t enmType)
540{
541 return enmType >= T_AVX_128;
542}
543
544
545DECL_FORCE_INLINE(uint8_t) bs3CpuInstr4GetOperandSize(uint8_t enmType)
546{
547 return enmType < T_128BITS ? 64/8
548 : enmType < T_256BITS ? 128/8 : 256/8;
549}
550
551
552/**
553 * Gets the names of floating-point exception flags that are set for a given MXCSR.
554 *
555 * @returns Names of floating-point exception flags that are set.
556 * @param pszBuf Where to store the floating-point exception flags.
557 * @param cchBuf The size of the buffer.
558 * @param uMxCsr The MXCSR value.
559 */
560static size_t bs3CpuInstr4GetXcptFlags(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
561{
562 BS3_ASSERT(cchBuf >= FP_XCPT_FLAGS_NAMES_MAXLEN);
563 return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IE ? " IE" : "", uMxCsr & X86_MXCSR_DE ? " DE" : "",
564 uMxCsr & X86_MXCSR_ZE ? " ZE" : "", uMxCsr & X86_MXCSR_OE ? " OE" : "",
565 uMxCsr & X86_MXCSR_UE ? " UE" : "", uMxCsr & X86_MXCSR_PE ? " PE" : "");
566}
567
568/**
569 * Gets the names of floating-point exception mask that are set for a given MXCSR.
570 *
571 * @returns Names of floating-point exception flags that are set.
572 * @param pszBuf Where to store the floating-point exception flags.
573 * @param cchBuf The size of the buffer.
574 * @param uMxCsr The MXCSR value.
575 */
576static size_t bs3CpuInstr4GetXcptMasks(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
577{
578 BS3_ASSERT(cchBuf >= FP_XCPT_MASKS_NAMES_MAXLEN);
579 return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IM ? " IM" : "", uMxCsr & X86_MXCSR_DM ? " DM" : "",
580 uMxCsr & X86_MXCSR_ZM ? " ZM" : "", uMxCsr & X86_MXCSR_OM ? " OM" : "",
581 uMxCsr & X86_MXCSR_UM ? " UM" : "", uMxCsr & X86_MXCSR_PM ? " PM" : "");
582}
583
584
585/**
586 * Gets the names of floating-point bits other than flags and masks that are set for
587 * a given MXCSR.
588 *
589 * @returns Names of floating-point exception flags that are set.
590 * @param pszBuf Where to store the floating-point exception flags.
591 * @param cchBuf The size of the buffer.
592 * @param uMxCsr The MXCSR value.
593 */
594static size_t bs3CpuInstr4GetXcptOthers(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
595{
596 uint32_t const fMxCsrRc = uMxCsr & X86_MXCSR_RC_MASK;
597 BS3_ASSERT(cchBuf >= FP_XCPT_OTHERS_NAMES_MAXLEN);
598 return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s", uMxCsr & X86_MXCSR_DAZ ? " DAZ" : "",
599 uMxCsr & X86_MXCSR_FZ ? " FZ" : "",
600 uMxCsr & X86_MXCSR_MM ? " MM" : "",
601 fMxCsrRc == X86_MXCSR_RC_NEAREST ? " RC=NEAREST" :
602 fMxCsrRc == X86_MXCSR_RC_DOWN ? " RC=DOWN" :
603 fMxCsrRc == X86_MXCSR_RC_UP ? " RC=UP" :
604 fMxCsrRc == X86_MXCSR_RC_ZERO ? " RC=ZERO" : "");
605}
606
607
608/**
609 * Reconfigures the execution environment according to @a pConfig.
610 *
611 * Call bs3CpuInstrXConfigRestore to undo the changes.
612 *
613 * @returns true on success, false if the configuration cannot be applied. In
614 * the latter case, no context changes are made.
615 * @param pSavedCfg Where to save state we modify.
616 * @param pCtx The register context to modify.
617 * @param pExtCtx The extended register context to modify.
618 * @param pConfig The configuration to apply.
619 * @param bMode The target mode.
620 */
621static bool bs3CpuInstr4ConfigReconfigure(PBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx,
622 PCBS3CPUINSTR4_CONFIG_T pConfig, uint8_t bMode)
623{
624 /*
625 * Save context bits we may change here
626 */
627 pSavedCfg->uCr0 = pCtx->cr0.u32;
628 pSavedCfg->uCr4 = pCtx->cr4.u32;
629 pSavedCfg->uEfl = pCtx->rflags.u32;
630 pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx);
631 pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx);
632 pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx);
633
634 /*
635 * Can we make these changes?
636 */
637 if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse)
638 return false;
639
640 /*
641 * Modify the test context.
642 */
643 if (pConfig->fCr0Mp)
644 pCtx->cr0.u32 |= X86_CR0_MP;
645 else
646 pCtx->cr0.u32 &= ~X86_CR0_MP;
647 if (pConfig->fCr0Em)
648 pCtx->cr0.u32 |= X86_CR0_EM;
649 else
650 pCtx->cr0.u32 &= ~X86_CR0_EM;
651 if (pConfig->fCr0Ts)
652 pCtx->cr0.u32 |= X86_CR0_TS;
653 else
654 pCtx->cr0.u32 &= ~X86_CR0_TS;
655
656 if (pConfig->fCr4OsFxSR)
657 pCtx->cr4.u32 |= X86_CR4_OSFXSR;
658 else
659 pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
660
661 if (pConfig->fCr4OsXmmExcpt && g_afTypeSupports[T_SSE])
662 pCtx->cr4.u32 |= X86_CR4_OSXMMEEXCPT;
663 else
664 pCtx->cr4.u32 &= ~X86_CR4_OSXMMEEXCPT;
665
666 if (pConfig->fCr4OsFxSR)
667 pCtx->cr4.u32 |= X86_CR4_OSFXSR;
668 else
669 pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
670
671 if (pConfig->fCr4OsXSave)
672 pCtx->cr4.u32 |= X86_CR4_OSXSAVE;
673 else
674 pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE;
675
676 if (pConfig->fXcr0Sse)
677 pExtCtx->fXcr0Saved |= XSAVE_C_SSE;
678 else
679 pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE;
680 if (pConfig->fXcr0Avx && g_afTypeSupports[T_AVX_256])
681 pExtCtx->fXcr0Saved |= XSAVE_C_YMM;
682 else
683 pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM;
684
685 if (pConfig->fAlignCheck)
686 {
687 pCtx->rflags.u32 |= X86_EFL_AC;
688 pCtx->cr0.u32 |= X86_CR0_AM;
689 }
690 else
691 {
692 pCtx->rflags.u32 &= ~X86_EFL_AC;
693 pCtx->cr0.u32 &= ~X86_CR0_AM;
694 }
695
696 /** @todo Can we remove this? x87 FPU and SIMD are independent. */
697 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B));
698
699 if (pConfig->fMxCsrMM)
700 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM);
701 else
702 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM);
703 return true;
704}
705
706
707/**
708 * Undoes changes made by bs3CpuInstr4ConfigReconfigure.
709 */
710static void bs3CpuInstrXConfigRestore(PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx)
711{
712 pCtx->cr0.u32 = pSavedCfg->uCr0;
713 pCtx->cr4.u32 = pSavedCfg->uCr4;
714 pCtx->rflags.u32 = pSavedCfg->uEfl;
715 pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal;
716 Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw);
717 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw);
718 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr);
719}
720
721
722/**
723 * Allocates three extended CPU contexts and initializes the first one
724 * with random data.
725 * @returns First extended context, initialized with randomish data. NULL on
726 * failure (complained).
727 * @param ppExtCtx2 Where to return the 2nd context.
728 */
729static PBS3EXTCTX bs3CpuInstrXAllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2)
730{
731 /* Allocate extended context structures. */
732 uint64_t fFlags;
733 uint16_t cb = Bs3ExtCtxGetSize(&fFlags);
734 PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2);
735 PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb);
736 if (pExtCtx1)
737 {
738 Bs3ExtCtxInit(pExtCtx1, cb, fFlags);
739 /** @todo populate with semi-random stuff. */
740
741 Bs3ExtCtxInit(pExtCtx2, cb, fFlags);
742 *ppExtCtx2 = pExtCtx2;
743 return pExtCtx1;
744 }
745 Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2);
746 *ppExtCtx2 = NULL;
747 return NULL;
748}
749
750
751/**
752 * Frees the extended CPU contexts allocated by bs3CpuInstrXAllocExtCtxs.
753 *
754 * @param pExtCtx1 The first extended context.
755 * @param pExtCtx2 The second extended context.
756 */
757static void bs3CpuInstrXFreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
758{
759 RT_NOREF_PV(pExtCtx2);
760 Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2);
761}
762
763
764/**
765 * Sets up SSE and AVX bits relevant for FPU instructions.
766 */
767static void bs3CpuInstr4SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx)
768{
769 /* CR0: */
770 uint32_t cr0 = Bs3RegGetCr0();
771 cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
772 cr0 |= X86_CR0_NE;
773 Bs3RegSetCr0(cr0);
774
775 /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */
776 pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
777 pCtx->cr0.u32 |= X86_CR0_NE;
778
779 /* CR4: */
780 BS3_ASSERT( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
781 || pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE);
782 {
783 uint32_t cr4 = Bs3RegGetCr4();
784 if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
785 {
786 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE;
787 Bs3RegSetCr4(cr4);
788 Bs3RegSetXcr0(pExtCtx->fXcr0Nominal);
789 }
790 else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
791 {
792 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT;
793 Bs3RegSetCr4(cr4);
794 }
795 pCtx->cr4.u32 = cr4;
796 }
797}
798
799
800/**
801 * Configures the buffer with electric fences in paged modes.
802 *
803 * @returns Adjusted buffer pointer.
804 * @param pbBuf The buffer pointer.
805 * @param pcbBuf Pointer to the buffer size (input & output).
806 * @param bMode The testing target mode.
807 */
808DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode)
809{
810 if (BS3_MODE_IS_PAGED(bMode))
811 {
812 int rc;
813 uint32_t cbBuf = *pcbBuf;
814 Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P);
815 Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P);
816 pbBuf += X86_PAGE_SIZE;
817 cbBuf -= X86_PAGE_SIZE * 2;
818 *pcbBuf = cbBuf;
819
820 g_pbBufAlias = g_pbBufAliasAlloc;
821 rc = Bs3PagingAlias((uintptr_t)g_pbBufAlias, (uintptr_t)pbBuf, cbBuf + X86_PAGE_SIZE, /* must include the tail guard pg */
822 X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
823 if (RT_FAILURE(rc))
824 Bs3TestFailedF("Bs3PagingAlias failed on %p/%p LB %#x: %d", g_pbBufAlias, pbBuf, cbBuf, rc);
825 }
826 else
827 g_pbBufAlias = pbBuf;
828 return pbBuf;
829}
830
831
832/**
833 * Undoes what bs3CpuInstrXBufSetup did.
834 *
835 * @param pbBuf The buffer pointer.
836 * @param cbBuf The buffer size.
837 * @param bMode The testing target mode.
838 */
839DECLINLINE(void) bs3CpuInstrXBufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode)
840{
841 if (BS3_MODE_IS_PAGED(bMode))
842 {
843 Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0);
844 Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0);
845 }
846}
847
848
849/**
850 * Gets a buffer of a @a cbMemOp sized operand according to the given
851 * configuration and alignment restrictions.
852 *
853 * @returns Pointer to the buffer.
854 * @param pbBuf The buffer pointer.
855 * @param cbBuf The buffer size.
856 * @param cbMemOp The operand size.
857 * @param cbAlign The operand alignment restriction.
858 * @param pConfig The configuration.
859 * @param fPageFault The \#PF test setting.
860 */
861DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign,
862 PCBS3CPUINSTR4_CONFIG_T pConfig, unsigned fPageFault)
863{
864 /* All allocations are at the tail end of the buffer, so that we've got a
865 guard page following the operand. When asked to consistenly trigger
866 a #PF, we slide the buffer into that guard page. */
867 if (fPageFault)
868 cbBuf += X86_PAGE_SIZE;
869
870 if (pConfig->fAligned)
871 {
872 if (!pConfig->fAlignCheck)
873 return &pbBuf[cbBuf - cbMemOp];
874 return &pbBuf[cbBuf - cbMemOp - cbAlign];
875 }
876 return &pbBuf[cbBuf - cbMemOp - 1];
877}
878
879
880/**
881 * Determines the size of memory operands.
882 */
883DECLINLINE(uint8_t) bs3CpuInstrXMemOpSize(uint8_t cbOperand, uint8_t enmRm)
884{
885 if (enmRm <= RM_MEM)
886 return cbOperand;
887 if (enmRm == RM_MEM8)
888 return sizeof(uint8_t);
889 if (enmRm == RM_MEM16)
890 return sizeof(uint16_t);
891 if (enmRm == RM_MEM32)
892 return sizeof(uint32_t);
893 if (enmRm == RM_MEM64)
894 return sizeof(uint64_t);
895 BS3_ASSERT(0);
896 return cbOperand;
897}
898
899
900/*
901 * Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly
902 * skips a large fraction of the micro-tests. It is sufficiently random
903 * that over a large number of runs, all micro-tests will be hit.
904 *
905 * This improves the runtime of the worst case (`#define ALL_TESTS' on a
906 * debug build, run with '--execute-all-in-iem') from ~9000 to ~800 seconds
907 * (on an Intel Core i7-10700, fwiw).
908 *
909 * To activate this 'developer's speed-testing mode', turn on
910 * `#define BS3_SKIPIT_DO_SKIP' here.
911 *
912 * BS3_SKIPIT_AVG_SKIP governs approximately how many micro-tests are
913 * skipped in a row; e.g. the default of 26 means about every 27th
914 * micro-test is run during a particular test run. (This is not 27x
915 * faster due to other activities which are not skipped!) Note this is
916 * only an average; the actual skips are random.
917 *
918 * You can also modify bs3CpuInstrX_SkipIt() to focus on specific sub-tests,
919 * using its (currently ignored) `bRing, iCfg, iTest, iVal, iVariant' args
920 * (to enable this: turn on `#define BS3_SKIPIT_DO_ARGS': which costs about
921 * 3% performance).
922 *
923 * Note! The skipping is not compatible with testing the native recompiler as
924 * it requires the test code to be run a number of times before it kicks
925 * in and does the native recompilation (currently around 16 times).
926 */
927#define BS3_SKIPIT_AVG_SKIP 26
928#define BS3_SKIPIT_REPORT_COUNT 150000
929#undef BS3_SKIPIT_DO_SKIP
930#undef BS3_SKIPIT_DO_ARGS
931
932#ifndef BS3_SKIPIT_DO_SKIP
933# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) (false)
934#else
935# include <iprt/asm-amd64-x86.h>
936# include <iprt/asm-math.h>
937
938DECLINLINE(uint32_t) bs3CpuInstrX_SimpleRand(void)
939{
940 /*
941 * A simple Lehmer linear congruential pseudo-random number
942 * generator using the constants suggested by Park & Miller:
943 *
944 * modulus = 2^31 - 1 (INT32_MAX)
945 * multiplier = 7^5 (16807)
946 *
947 * It produces numbers in the range [1..INT32_MAX-1] and is
948 * more chaotic in the higher bits.
949 *
950 * Note! Runtime/common/rand/randparkmiller.cpp is also use this algorithm,
951 * though the zero handling is different.
952 */
953 static uint32_t s_uSeedMemory = 0;
954 uint32_t uVal = s_uSeedMemory;
955 if (!uVal)
956 uVal = (uint32_t)ASMReadTSC();
957 uVal = ASMModU64ByU32RetU32(ASMMult2xU32RetU64(uVal, 16807), INT32_MAX);
958 s_uSeedMemory = uVal;
959 return uVal;
960}
961
962static unsigned g_cSeen, g_cSkipped;
963
964static void bs3CpuInstrX_ShowTallies(void)
965{
966 Bs3TestPrintf("Micro-tests %d: tested %d / skipped %d\n", g_cSeen, g_cSeen - g_cSkipped, g_cSkipped);
967}
968
969# ifdef BS3_SKIPIT_DO_ARGS
970# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt(bRing, iCfg, iTest, iVal, iVariant)
971static bool bs3CpuInstrX_SkipIt(uint8_t bRing, unsigned iCfg, unsigned iTest, unsigned iVal, unsigned iVariant)
972# else
973# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt()
974static bool bs3CpuInstrX_SkipIt(void)
975# endif
976{
977 static unsigned s_uTimes = 0;
978 bool fSkip;
979
980 /* Cache calls to the relatively expensive random routine */
981 if (!s_uTimes)
982 s_uTimes = bs3CpuInstrX_SimpleRand() % (BS3_SKIPIT_AVG_SKIP * 2 + 1) + 1;
983 fSkip = --s_uTimes > 0;
984 if (fSkip)
985 ++g_cSkipped;
986
987 if (++g_cSeen % BS3_SKIPIT_REPORT_COUNT == 0)
988 bs3CpuInstrX_ShowTallies();
989 return fSkip;
990}
991
992#endif /* BS3_SKIPIT_DO_SKIP */
993
994/*
995 * Test type #1.
996 * Generic YMM registers.
997 */
998typedef struct BS3CPUINSTR4_TEST1_VALUES_T
999{
1000 X86YMMREG uSrc2; /**< Second source operand. */
1001 X86YMMREG uSrc1; /**< uDstIn for SSE */
1002 X86YMMREG uDstOut; /**< Destination output. */
1003 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1004 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1005 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1006 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1007 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1008 uint8_t afPadding[2]; /**< Alignment padding. */
1009} BS3CPUINSTR4_TEST1_VALUES_T;
1010
1011/*
1012 * Test type #1.
1013 * Packed single-precision.
1014 */
1015typedef struct BS3CPUINSTR4_TEST1_VALUES_PS_T
1016{
1017 X86YMMFLOATPSREG uSrc2; /**< Second source operand. */
1018 X86YMMFLOATPSREG uSrc1; /**< uDstIn for SSE */
1019 X86YMMFLOATPSREG uDstOut; /**< Destination output. */
1020 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1021 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1022 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1023 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1024 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1025 uint8_t afPadding[2]; /**< Alignment padding. */
1026} BS3CPUINSTR4_TEST1_VALUES_PS_T;
1027AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1028AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1029AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1030AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1031AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1032AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1033AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1034AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1035AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1036
1037/*
1038 * Test type #1.
1039 * Packed double-precision.
1040 */
1041typedef struct BS3CPUINSTR4_TEST1_VALUES_PD_T
1042{
1043 X86YMMFLOATPDREG uSrc2; /**< Second source operand. */
1044 X86YMMFLOATPDREG uSrc1; /**< uDstIn for SSE */
1045 X86YMMFLOATPDREG uDstOut; /**< Destination output. */
1046 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1047 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1048 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1049 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1050 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1051 uint8_t afPadding[2]; /**< Alignment padding. */
1052} BS3CPUINSTR4_TEST1_VALUES_PD_T;
1053AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1054AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1055AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1056AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1057AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1058AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1059AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1060AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1061AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1062
1063/*
1064 * Test type #1.
1065 * Scalar single-precision.
1066 */
1067typedef struct BS3CPUINSTR4_TEST1_VALUES_SS_T
1068{
1069 X86YMMFLOATSSREG uSrc2; /**< Second source operand. */
1070 X86YMMFLOATSSREG uSrc1; /**< uDstIn for SSE */
1071 X86YMMFLOATSSREG uDstOut; /**< Destination output. */
1072 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1073 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1074 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1075 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1076 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1077 uint8_t afPadding[2]; /**< Alignment padding. */
1078} BS3CPUINSTR4_TEST1_VALUES_SS_T;
1079AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1080AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1081AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1082AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1083AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1084AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1085AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1086AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1087AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1088
1089/*
1090 * Test type #1.
1091 * Scalar double-precision.
1092 */
1093typedef struct BS3CPUINSTR4_TEST1_VALUES_SD_T
1094{
1095 X86YMMFLOATSDREG uSrc2; /**< Second source operand. */
1096 X86YMMFLOATSDREG uSrc1; /**< uDstIn for SSE */
1097 X86YMMFLOATSDREG uDstOut; /**< Destination output. */
1098 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1099 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1100 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1101 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1102 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1103 uint8_t afPadding[2]; /**< Alignment padding. */
1104} BS3CPUINSTR4_TEST1_VALUES_SD_T;
1105AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1106AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1107AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1108AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1109AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1110AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1111AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1112AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1113AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1114
1115/*
1116 * Test type #1.
1117 * Scalar quadruple-precision.
1118 */
1119typedef struct BS3CPUINSTR4_TEST1_VALUES_SQ_T
1120{
1121 X86YMMFLOATSQREG uSrc2; /**< Second source operand. */
1122 X86YMMFLOATSQREG uSrc1; /**< uDstIn for SSE */
1123 X86YMMFLOATSQREG uDstOut; /**< Destination output. */
1124 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1125 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1126 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1127 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1128 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1129 uint8_t afPadding[2]; /**< Alignment padding. */
1130} BS3CPUINSTR4_TEST1_VALUES_SQ_T;
1131AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SQ_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1132AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1133AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1134AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1135AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1136AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1137AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1138AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1139AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1140
1141typedef struct BS3CPUINSTR4_TEST1_T
1142{
1143 FPFNBS3FAR pfnWorker; /**< Test function worker. */
1144 uint8_t bAvxMisalignXcpt; /**< AVX misalignment exception. */
1145 uint8_t enmRm; /**< R/M type. */
1146 uint8_t enmType; /**< CPU instruction type (see T_XXX). */
1147 uint8_t iRegDst; /**< Index of destination register, UINT8_MAX if N/A. */
1148 uint8_t iRegSrc1; /**< Index of first source register, UINT8_MAX if N/A. */
1149 uint8_t iRegSrc2; /**< Index of second source register, UINT8_MAX if N/A. */
1150 uint8_t cValues; /**< Number of test values in @c paValues. */
1151 BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *paValues; /**< Test values. */
1152} BS3CPUINSTR4_TEST1_T;
1153
1154typedef struct BS3CPUINSTR4_TEST1_MODE_T
1155{
1156 BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests;
1157 unsigned cTests;
1158} BS3CPUINSTR4_TEST1_MODE_T;
1159
1160/** Initializer for a BS3CPUINSTR4_TEST1_MODE_T array (three entries). */
1161#define BS3CPUINSTR4_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
1162 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
1163
1164typedef struct BS3CPUINSTR4_TEST1_CTX_T
1165{
1166 BS3CPUINSTR4_CONFIG_T const BS3_FAR *pConfig; /**< The test execution environment configuration. */
1167 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest; /**< The instruction being tested. */
1168 unsigned iVal; /**< Which iteration of the test value is this. */
1169 const char BS3_FAR *pszMode; /**< The testing mode (e.g. real, protected, paged and permutations). */
1170 PBS3TRAPFRAME pTrapFrame; /**< The exception (trap) frame. */
1171 PBS3REGCTX pCtx; /**< The general-purpose register context. */
1172 PBS3EXTCTX pExtCtx; /**< The extended (FPU) register context. */
1173 PBS3EXTCTX pExtCtxOut; /**< The output extended (FPU) register context. */
1174 uint8_t BS3_FAR *puMemOp; /**< The memory operand buffer. */
1175 uint8_t BS3_FAR *puMemOpAlias; /**< The memory operand alias buffer for comparing result. */
1176 uint8_t cbMemOp; /**< Size of the memory operand (and alias) buffer in bytes. */
1177 uint8_t cbOperand; /**< Size of the instruction operand (8 for MMX, 16 for SSE etc). */
1178 uint8_t cbInstr; /**< Size of the instruction opcode. */
1179 uint8_t bXcptExpect; /**< The expected exception while/after executing the instruction. */
1180 uint16_t idTestStep; /**< The test iteration step. */
1181} BS3CPUINSTR4_TEST1_CTX_T;
1182/** Pointer to a test 1 context. */
1183typedef BS3CPUINSTR4_TEST1_CTX_T BS3_FAR *PBS3CPUINSTR4_TEST1_CTX_T;
1184
1185
1186/**
1187 * Worker for bs3CpuInstr4_WorkerTestType1.
1188 */
1189static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
1190 PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
1191{
1192 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = pTestCtx->pTest;
1193 BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
1194 PBS3TRAPFRAME pTrapFrame = pTestCtx->pTrapFrame;
1195 PBS3REGCTX pCtx = pTestCtx->pCtx;
1196 PBS3EXTCTX pExtCtx = pTestCtx->pExtCtx;
1197 PBS3EXTCTX pExtCtxOut = pTestCtx->pExtCtxOut;
1198 uint8_t BS3_FAR *puMemOp = pTestCtx->puMemOp;
1199 uint8_t BS3_FAR *puMemOpAlias = pTestCtx->puMemOpAlias;
1200 uint8_t cbMemOp = pTestCtx->cbMemOp;
1201 uint8_t const cbOperand = pTestCtx->cbOperand;
1202 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)pTestCtx->pTest->pfnWorker)[-1];
1203 uint8_t bXcptExpect = pTestCtx->bXcptExpect;
1204 uint8_t const bFpXcpt = pTestCtx->pConfig->fCr4OsXmmExcpt ? X86_XCPT_XF : X86_XCPT_UD;
1205 bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
1206 uint32_t uMxCsr;
1207 X86YMMREG MemOpExpect;
1208 uint16_t cErrors;
1209 uint32_t uExpectedMxCsr;
1210 bool fFpXcptExpected;
1211
1212 /*
1213 * An exception may be raised based on the test value (128 vs 256 bits).
1214 * In addition, we allow setting the exception flags (and mask) prior to
1215 * executing the instruction, so we cannot use the exception flags to figure
1216 * out if an exception will be raised. Hence, the input values provide us
1217 * explicitly whether an exception is expected for 128 and 256-bit variants.
1218 */
1219 if (pTestCtx->cbOperand > 16)
1220 {
1221 uExpectedMxCsr = pValues->u256ExpectedMxCsr;
1222 fFpXcptExpected = pValues->f256FpXcptExpected;
1223 }
1224 else
1225 {
1226 uExpectedMxCsr = pValues->u128ExpectedMxCsr;
1227 fFpXcptExpected = pValues->f128FpXcptExpected;
1228 }
1229
1230 /*
1231 * Set up the context and some expectations.
1232 */
1233 /* Destination. */
1234 Bs3MemZero(&MemOpExpect, sizeof(MemOpExpect));
1235 if (pTest->iRegDst == UINT8_MAX)
1236 {
1237 BS3_ASSERT(pTest->enmRm >= RM_MEM);
1238 Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp);
1239 if (bXcptExpect == X86_XCPT_DB)
1240 MemOpExpect.ymm = pValues->uDstOut.ymm;
1241 else
1242 Bs3MemSet(&MemOpExpect, 0xcc, sizeof(MemOpExpect));
1243 }
1244
1245 /* Source #1 (/ destination for SSE). */
1246 if (pTest->iRegSrc1 == UINT8_MAX)
1247 {
1248 BS3_ASSERT(pTest->enmRm >= RM_MEM);
1249 Bs3MemCpy(puMemOpAlias, &pValues->uSrc1, cbMemOp);
1250 if (pTest->iRegDst == UINT8_MAX)
1251 BS3_ASSERT(fSseInstr);
1252 else
1253 MemOpExpect.ymm = pValues->uSrc1.ymm;
1254 }
1255 else if (fSseInstr)
1256 Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm.DQWords.dqw0);
1257 else
1258 Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm, 32);
1259
1260 /* Source #2. */
1261 if (pTest->iRegSrc2 == UINT8_MAX)
1262 {
1263 BS3_ASSERT(pTest->enmRm >= RM_MEM);
1264 BS3_ASSERT(pTest->iRegDst != UINT8_MAX && pTest->iRegSrc1 != UINT8_MAX);
1265 Bs3MemCpy(puMemOpAlias, &pValues->uSrc2, cbMemOp);
1266 MemOpExpect.ymm = pValues->uSrc2.ymm;
1267 }
1268 else if (fSseInstr)
1269 Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm.DQWords.dqw0);
1270 else
1271 Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm, 32);
1272
1273 /* Memory pointer. */
1274 if (pTest->enmRm >= RM_MEM)
1275 {
1276 BS3_ASSERT( pTest->iRegDst == UINT8_MAX
1277 || pTest->iRegSrc1 == UINT8_MAX
1278 || pTest->iRegSrc2 == UINT8_MAX);
1279 Bs3RegCtxSetGrpSegFromCurPtr(pCtx, &pCtx->rbx, &pCtx->fs, puMemOp);
1280 }
1281
1282 /* Setup MXCSR for the current test. */
1283 uMxCsr = (pSavedCfg->uMxCsr & X86_MXCSR_MM) | pValues->uMxCsr;
1284 BS3_ASSERT(!(uMxCsr & X86_MXCSR_MM));
1285 BS3_ASSERT(!(uMxCsr & X86_MXCSR_DAZ) || g_fMxCsrDazSupported);
1286 Bs3ExtCtxSetMxCsr(pExtCtx, uMxCsr);
1287
1288 /*
1289 * Prepare globals and execute.
1290 */
1291 g_uBs3TrapEipHint = pCtx->rip.u32;
1292 if ( bXcptExpect == X86_XCPT_DB
1293 && !fFpXcptExpected)
1294 g_uBs3TrapEipHint += cbInstr + 1;
1295 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut);
1296
1297 /*
1298 * Check the result.
1299 *
1300 * If a floating-point exception is expected, the destination is not updated by the instruction.
1301 * In the case of SSE instructions, updating the destination here will work because it is the same
1302 * as the source, but for AVX++ it won't because the destination is different and would contain 0s.
1303 */
1304 cErrors = Bs3TestSubErrorCount();
1305 if ( bXcptExpect == X86_XCPT_DB
1306 && !fFpXcptExpected
1307 && pTest->iRegDst != UINT8_MAX)
1308 {
1309 if (fSseInstr)
1310 Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm.DQWords.dqw0);
1311 else
1312 Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm, cbOperand);
1313 }
1314#if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */
1315 if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE
1316 && pExtCtx->Ctx.x.Hdr.bmXState == 0x7
1317 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3)
1318 pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7;
1319#endif
1320 if (bXcptExpect == X86_XCPT_DB)
1321 Bs3ExtCtxSetMxCsr(pExtCtx, uExpectedMxCsr | (pSavedCfg->uMxCsr & X86_MXCSR_MM));
1322 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pTestCtx->pszMode, pTestCtx->idTestStep);
1323
1324 if (bXcptExpect == X86_XCPT_DB)
1325 {
1326 uint32_t const uGotMxCsr = Bs3ExtCtxGetMxCsr(pExtCtxOut) & ~X86_MXCSR_MM;
1327
1328 /* Check if the SIMD FP exception flags and mask (or lack of) are as expected. */
1329 if (uGotMxCsr != uExpectedMxCsr)
1330 {
1331 char szExpectFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
1332 char szExpectMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
1333 char szExpectOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
1334 char szGotFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
1335 char szGotMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
1336 char szGotOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
1337 bs3CpuInstr4GetXcptFlags(&szExpectFlags[0], sizeof(szExpectFlags), uExpectedMxCsr);
1338 bs3CpuInstr4GetXcptMasks(&szExpectMasks[0], sizeof(szExpectMasks), uExpectedMxCsr);
1339 bs3CpuInstr4GetXcptOthers(&szExpectOthers[0], sizeof(szExpectOthers), uExpectedMxCsr);
1340 bs3CpuInstr4GetXcptFlags(&szGotFlags[0], sizeof(szGotFlags), uGotMxCsr);
1341 bs3CpuInstr4GetXcptMasks(&szGotMasks[0], sizeof(szGotMasks), uGotMxCsr);
1342 bs3CpuInstr4GetXcptOthers(&szGotOthers[0], sizeof(szGotOthers), uGotMxCsr);
1343 Bs3TestFailedF("Expected MXCSR %#RX32 (%s%s%s ) got MXCSR %#RX32 (%s%s%s )", uExpectedMxCsr,
1344 szExpectFlags, szExpectMasks, szExpectOthers, uGotMxCsr, szGotFlags, szGotMasks, szGotOthers);
1345 }
1346
1347 /* Check if the SIMD FP exception (or lack of) is as expected. */
1348 if (fFpXcptExpected)
1349 {
1350 if (pTrapFrame->bXcpt == bFpXcpt)
1351 { /* likely */ }
1352 else
1353 Bs3TestFailedF("Expected floating-point xcpt %s, got %s", bs3CpuInstr4XcptName(bFpXcpt),
1354 bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1355 }
1356 else if (pTrapFrame->bXcpt == X86_XCPT_DB)
1357 { /* likely */ }
1358 else
1359 Bs3TestFailedF("Expected no xcpt, got %s", bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1360 }
1361 /* Check if non-FP exception is as expected. */
1362 else if (pTrapFrame->bXcpt != bXcptExpect)
1363 Bs3TestFailedF("Expected xcpt %s, got %s", bs3CpuInstr4XcptName(bXcptExpect), bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1364
1365 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
1366 if (bMode == BS3_MODE_RM && (pCtx->rflags.u32 & X86_EFL_AC))
1367 {
1368 if (pTrapFrame->Ctx.rflags.u32 & X86_EFL_AC)
1369 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", pTrapFrame->bXcpt);
1370 pTrapFrame->Ctx.rflags.u32 |= X86_EFL_AC;
1371 }
1372 if (bXcptExpect == X86_XCPT_PF)
1373 pCtx->cr2.u = (uintptr_t)puMemOp;
1374 Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, bXcptExpect == X86_XCPT_DB && !fFpXcptExpected ? cbInstr + 1 : 0, 0 /*cbSpAdjust*/,
1375 (bXcptExpect == X86_XCPT_DB && !fFpXcptExpected) || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
1376 pTestCtx->pszMode, pTestCtx->idTestStep);
1377 pCtx->cr2.u = 0;
1378
1379 if ( pTest->enmRm >= RM_MEM
1380 && Bs3MemCmp(puMemOpAlias, &MemOpExpect, cbMemOp) != 0)
1381 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &MemOpExpect, cbMemOp, puMemOpAlias);
1382
1383 return cErrors;
1384}
1385
1386
1387/**
1388 * Test type #1 worker.
1389 */
1390static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
1391 PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs)
1392{
1393 BS3REGCTX Ctx;
1394 BS3TRAPFRAME TrapFrame;
1395 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
1396 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
1397 uint8_t BS3_FAR *pbBuf = g_pbBuf;
1398 uint32_t cbBuf = g_cbBuf;
1399 PBS3EXTCTX pExtCtxOut;
1400 PBS3EXTCTX pExtCtx = bs3CpuInstrXAllocExtCtxs(&pExtCtxOut);
1401 if (pExtCtx)
1402 { /* likely */ }
1403 else
1404 return 0;
1405 if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
1406 { /* likely */ }
1407 else
1408 {
1409 Bs3TestPrintf("Skipped due to ancient FPU state format\n");
1410 return 0;
1411 }
1412
1413 /* Ensure the structures are allocated before we sample the stack pointer. */
1414 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
1415 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
1416
1417 /*
1418 * Create test context.
1419 */
1420 pbBuf = bs3CpuInstrXBufSetup(pbBuf, &cbBuf, bMode);
1421 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
1422 bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx);
1423
1424 /*
1425 * Run the tests in all rings since alignment issues may behave
1426 * differently in ring-3 compared to ring-0.
1427 */
1428 for (;;)
1429 {
1430 unsigned fPf = 0;
1431 do
1432 {
1433 unsigned iCfg;
1434 for (iCfg = 0; iCfg < cConfigs; iCfg++)
1435 {
1436 unsigned iTest;
1437 BS3CPUINSTRX_CONFIG_SAVED_T SavedCfg;
1438 if (!bs3CpuInstr4ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
1439 continue; /* unsupported config */
1440
1441 /*
1442 * Iterate the tests.
1443 */
1444 for (iTest = 0; iTest < cTests; iTest++)
1445 {
1446 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = &paTests[iTest];
1447 unsigned const cValues = pTest->cValues;
1448 bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
1449 bool const fAvxInstr = bs3CpuInstr4IsAvx(pTest->enmType);
1450 uint8_t const cbOperand = bs3CpuInstr4GetOperandSize(pTest->enmType);
1451 uint8_t const cbMemOp = bs3CpuInstrXMemOpSize(cbOperand, pTest->enmRm);
1452 uint8_t const cbAlign = cbMemOp;
1453 uint8_t BS3_FAR *puMemOp = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf);
1454 uint8_t *puMemOpAlias = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf];
1455 uint8_t bXcptExpect = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD
1456 : fSseInstr ? paConfigs[iCfg].bXcptSse
1457 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
1458 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
1459 unsigned cRecompRuns = 0;
1460 unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues;
1461 unsigned iVal;
1462
1463 /* If testing unaligned memory accesses (or #PF), skip register-only tests. This
1464 allows setting bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
1465 if ( (pTest->enmRm == RM_REG || pTest->enmRm == RM_MEM8)
1466 && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf))
1467 continue;
1468
1469 /* #AC is only raised in ring-3. */
1470 if (bXcptExpect == X86_XCPT_AC)
1471 {
1472 if (bRing != 3)
1473 bXcptExpect = X86_XCPT_DB;
1474 else if (fAvxInstr)
1475 bXcptExpect = pTest->bAvxMisalignXcpt; /* they generally don't raise #AC */
1476 }
1477
1478 if (fPf && bXcptExpect == X86_XCPT_DB)
1479 bXcptExpect = X86_XCPT_PF;
1480
1481 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, pTest->pfnWorker);
1482
1483 /*
1484 * Iterate the test values and do the actual testing.
1485 */
1486 while (cRecompRuns < cMaxRecompRuns)
1487 {
1488 for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
1489 {
1490 uint16_t cErrors;
1491 BS3CPUINSTR4_TEST1_CTX_T TestCtx;
1492
1493 if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0))
1494 continue;
1495
1496 /*
1497 * If the hardware does not support DAZ bit skip test values that set it.
1498 */
1499 if ( !g_fMxCsrDazSupported
1500 && (pTest->paValues[iVal].uMxCsr & X86_MXCSR_DAZ))
1501 continue;
1502
1503 /*
1504 * Setup the test instruction context and pass it to the worker.
1505 * A few of these can be figured out by the worker but initializing
1506 * it outside the inner most loop is more optimal.
1507 */
1508 TestCtx.pConfig = &paConfigs[iCfg];
1509 TestCtx.pTest = pTest;
1510 TestCtx.iVal = iVal;
1511 TestCtx.pszMode = pszMode;
1512 TestCtx.pTrapFrame = &TrapFrame;
1513 TestCtx.pCtx = &Ctx;
1514 TestCtx.pExtCtx = pExtCtx;
1515 TestCtx.pExtCtxOut = pExtCtxOut;
1516 TestCtx.puMemOp = (uint8_t *)puMemOp;
1517 TestCtx.puMemOpAlias = puMemOpAlias;
1518 TestCtx.cbMemOp = cbMemOp;
1519 TestCtx.cbOperand = cbOperand;
1520 TestCtx.bXcptExpect = bXcptExpect;
1521 TestCtx.idTestStep = idTestStep;
1522 cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
1523 if (cErrors != Bs3TestSubErrorCount())
1524 {
1525 if (paConfigs[iCfg].fAligned)
1526 Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, %s %u-bit)",
1527 Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
1528 bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), fSseInstr ? "SSE" : "AVX", cbOperand * 8);
1529 else
1530 Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, puMemOp=%p, EFLAGS=%#RX32, %s %u-bit)",
1531 Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
1532 bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), puMemOp,
1533 TrapFrame.Ctx.rflags.u32, fSseInstr ? "SSE" : "AVX", cbOperand * 8);
1534 Bs3TestPrintf("\n");
1535 }
1536 }
1537 }
1538 }
1539 bs3CpuInstrXConfigRestore(&SavedCfg, &Ctx, pExtCtx);
1540 }
1541 } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode));
1542
1543 /*
1544 * Next ring.
1545 */
1546 bRing++;
1547 if (bRing > 3 || bMode == BS3_MODE_RM)
1548 break;
1549 Bs3RegCtxConvertToRingX(&Ctx, bRing);
1550 }
1551
1552 /*
1553 * Cleanup.
1554 */
1555 bs3CpuInstrXBufCleanup(pbBuf, cbBuf, bMode);
1556 bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut);
1557 return 0;
1558}
1559
1560
1561/*
1562 * [V]ADDPS.
1563 */
1564BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addps(uint8_t bMode)
1565{
1566 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
1567 {
1568 /*
1569 * Zero.
1570 */
1571 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1572 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1573 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1574 /*mxcsr:in */ 0,
1575 /*128:out */ 0,
1576 /*256:out */ 0,
1577 /*xcpt? */ false, false },
1578 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1579 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1580 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1581 /*mxcsr:in */ 0,
1582 /*128:out */ 0,
1583 /*256:out */ 0,
1584 /*xcpt? */ false, false },
1585 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1586 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1587 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1588 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
1589 /*128:out */ X86_MXCSR_RC_ZERO,
1590 /*256:out */ X86_MXCSR_RC_ZERO,
1591 /*xcpt? */ false, false },
1592 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1593 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1594 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1595 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1596 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1597 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1598 /*xcpt? */ false, false },
1599 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1600 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1601 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1602 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1603 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1604 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1605 /*xcpt? */ false, false },
1606 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1607 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1608 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1609 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1610 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1611 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1612 /*xcpt? */ false, false },
1613 /*
1614 * Infinity.
1615 */
1616 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1617 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1618 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1619 /*mxcsr:in */ X86_MXCSR_IM,
1620 /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE,
1621 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE,
1622 /*xcpt? */ false, false },
1623 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1624 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1625 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1626 /*mxcsr:in */ 0,
1627 /*128:out */ X86_MXCSR_IE,
1628 /*256:out */ X86_MXCSR_IE,
1629 /*xcpt? */ true, true },
1630 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
1631 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
1632 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
1633 /*mxcsr:in */ X86_MXCSR_FZ,
1634 /*128:out */ X86_MXCSR_FZ,
1635 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
1636 /*xcpt? */ false, true },
1637 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
1638 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
1639 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(0) } },
1640 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1641 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1642 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1643 /*xcpt? */ false, true },
1644 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
1645 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
1646 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
1647 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1648 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1649 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1650 /*xcpt? */ true, true },
1651 /*
1652 * Overflow, Precision.
1653 */
1654 /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1655 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1656 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), } },
1657 /*mxcsr:in */ 0,
1658 /*128:out */ 0,
1659 /*256:out */ X86_MXCSR_OE,
1660 /*xcpt? */ false, true },
1661 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } },
1662 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0) } },
1663 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } },
1664 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
1665 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1666 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1667 /*xcpt? */ false, false },
1668 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
1669 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
1670 { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0) } },
1671 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1672 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
1673 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
1674 /*xcpt? */ false, false },
1675 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
1676 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
1677 { /* => */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },
1678 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1679 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
1680 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
1681 /*xcpt? */ false, false },
1682 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1683 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1684 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1685 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1686 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1687 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE,
1688 /*xcpt? */ false, true },
1689 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1690 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1691 { /* => */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1692 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
1693 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1694 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1695 /*xcpt? */ false, false },
1696 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
1697 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
1698 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_NORM_MAX(1), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1) } },
1699 /*mxcsr:in */ 0,
1700 /*128:out */ X86_MXCSR_PE,
1701 /*256:out */ X86_MXCSR_PE,
1702 /*xcpt? */ true, true },
1703 /*
1704 * Normals.
1705 */
1706 /*18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.25*/ } },
1707 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/ } },
1708 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/ } },
1709 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1710 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1711 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1712 /*xcpt? */ false, false },
1713 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
1714 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0) } },
1715 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1716 /*mxcsr:in */ 0,
1717 /*128:out */ 0,
1718 /*256:out */ 0,
1719 /*xcpt? */ false, false },
1720 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_0(0) } },
1721 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_1(1) /*- 1.00*/, FP32_0(0) } },
1722 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_0(0) } },
1723 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
1724 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
1725 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
1726 /*xcpt? */ false, false },
1727 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1), FP32_0(0) } },
1728 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_1(0), FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } },
1729 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_0(0), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_0(0), FP32_1(0) } },
1730 /*mxcsr:in */ X86_MXCSR_FZ,
1731 /*128:out */ X86_MXCSR_FZ,
1732 /*256:out */ X86_MXCSR_FZ,
1733 /*xcpt? */ false, false },
1734 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } },
1735 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_0(1), FP32_0(0) } },
1736 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(1), FP32_0(0) } },
1737 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1738 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1739 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1740 /*xcpt? */ false, false },
1741 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), } },
1742 { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), } },
1743 { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
1744 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1745 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1746 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1747 /*xcpt? */ false, false },
1748 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0) } },
1749 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0) } },
1750 { /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } },
1751 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1752 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1753 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1754 /*xcpt? */ false, false },
1755 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
1756 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
1757 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
1758 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
1759 /*128:out */ X86_MXCSR_RC_DOWN,
1760 /*256:out */ X86_MXCSR_RC_DOWN,
1761 /*xcpt? */ false, false },
1762 /*
1763 * Denormals.
1764 */
1765 /*26*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1766 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1767 { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1768 /*mxcsr:in */ 0,
1769 /*128:out */ X86_MXCSR_DE,
1770 /*256:out */ X86_MXCSR_DE,
1771 /*xcpt? */ true, true },
1772 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1773 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
1774 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
1775 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1776 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
1777 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
1778 /*xcpt? */ false, false },
1779 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
1780 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
1781 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1782 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1783 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1784 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1785 /*xcpt? */ false, false },
1786 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1787 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1788 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1789 /*mxcsr:in */ 0,
1790 /*128:out */ X86_MXCSR_DE,
1791 /*256:out */ X86_MXCSR_DE,
1792 /*xcpt? */ true, true },
1793 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1794 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1795 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1796 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
1797 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
1798 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
1799 /*xcpt? */ false, false },
1800 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
1801 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
1802 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1803 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1804 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1805 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1806 /*xcpt? */ false, false },
1807 /** @todo More Denormals. */
1808 /*
1809 * Invalids.
1810 */
1811 /*32*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1812 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1813 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1814 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1815 /*128:out */ X86_MXCSR_XCPT_MASK,
1816 /*256:out */ X86_MXCSR_XCPT_MASK,
1817 /*xcpt? */ false, false },
1818 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1819 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
1820 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1821 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1822 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1823 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1824 /*xcpt? */ false, false },
1825 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
1826 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1827 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1828 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
1829 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
1830 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
1831 /*xcpt? */ false, false },
1832 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
1833 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
1834 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
1835 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1836 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1837 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1838 /*xcpt? */ false, false },
1839 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1840 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1841 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1842 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,
1843 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,
1844 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,
1845 /*xcpt? */ false, false },
1846 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
1847 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1848 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1849 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1850 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1851 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1852 /*xcpt? */ false, false },
1853 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1854 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1855 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1856 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1857 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1858 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1859 /*xcpt? */ false, false },
1860 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1861 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
1862 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1863 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1864 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1865 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1866 /*xcpt? */ true, true },
1867 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
1868 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1869 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1870 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1871 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
1872 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
1873 /*xcpt? */ true, true },
1874 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
1875 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
1876 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
1877 /*mxcsr:in */ X86_MXCSR_RC_UP,
1878 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
1879 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
1880 /*xcpt? */ true, true },
1881 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1882 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1883 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1884 /*mxcsr:in */ 0,
1885 /*128:out */ 0,
1886 /*256:out */ 0,
1887 /*xcpt? */ false, false },
1888 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
1889 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1890 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1891 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1892 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1893 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1894 /*xcpt? */ true, true },
1895 /** @todo Underflow, Precision; Rounding, FZ etc. */
1896 };
1897
1898 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
1899 {
1900 { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1901 { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1902
1903 { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1904 { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1905
1906 { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1907 { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1908 };
1909 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
1910 {
1911 { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1912 { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1913
1914 { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1915 { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1916
1917 { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1918 { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1919 };
1920 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
1921 {
1922 { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1923 { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1924
1925 { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1926 { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1927
1928 { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1929 { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1930
1931 { bs3CpuInstr4_addps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1932 { bs3CpuInstr4_addps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1933
1934 { bs3CpuInstr4_vaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1935 { bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1936 };
1937
1938 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1939 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
1940 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1941 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
1942}
1943
1944
1945/*
1946 * [V]ADDPD.
1947 */
1948BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addpd(uint8_t bMode)
1949{
1950 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
1951 {
1952 /*
1953 * Zero.
1954 */
1955 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1956 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1957 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1958 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1959 /*128:out */ X86_MXCSR_XCPT_MASK,
1960 /*256:out */ X86_MXCSR_XCPT_MASK,
1961 /*xcpt? */ false, false },
1962 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1963 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1964 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1965 /*mxcsr:in */ X86_MXCSR_FZ,
1966 /*128:out */ X86_MXCSR_FZ,
1967 /*256:out */ X86_MXCSR_FZ,
1968 /*xcpt? */ false, false },
1969 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1970 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1971 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1972 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
1973 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
1974 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
1975 /*xcpt? */ false, false },
1976 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1977 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1978 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1979 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1980 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1981 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1982 /*xcpt? */ false, false },
1983 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1984 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1985 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1986 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1987 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1988 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1989 /*xcpt? */ false, false },
1990 /*
1991 * Infinity.
1992 */
1993 /* 5*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1994 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
1995 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
1996 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
1997 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
1998 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
1999 /*xcpt? */ true, true },
2000 { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } },
2001 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2002 { /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2003 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2004 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2005 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2006 /*xcpt? */ true, true },
2007 { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } },
2008 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2009 { /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2010 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2011 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
2012 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
2013 /*xcpt? */ true, true },
2014 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(0), FP64_INF(1) } },
2015 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } },
2016 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } },
2017 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2018 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2019 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2020 /*xcpt? */ false, false },
2021 { { /*src2 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_0(1), FP64_0(0), FP64_INF(1) } },
2022 { /*src1 */ { FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_0(1), FP64_0(0), FP64_INF(0) } },
2023 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/, FP64_0(1), FP64_0(0), FP64_QNAN(1) } },
2024 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2025 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2026 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2027 /*xcpt? */ false, false },
2028 /*
2029 * Overflow, Precision.
2030 */
2031 /*10*/{ { /*src2 */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } },
2032 { /*src1 */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } },
2033 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2034 /*mxcsr:in */ 0,
2035 /*128:out */ X86_MXCSR_OE,
2036 /*256:out */ X86_MXCSR_OE,
2037 /*xcpt? */ true, true },
2038 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } },
2039 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } },
2040 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } },
2041 /*mxcsr:in */ 0,
2042 /*128:out */ X86_MXCSR_OE,
2043 /*256:out */ X86_MXCSR_OE,
2044 /*xcpt? */ true, true },
2045 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
2046 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
2047 { /* => */ { FP64_INF(0), FP64_V(1, 0, 2), FP64_0(0), FP64_INF(0) } },
2048 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ,
2049 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2050 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2051 /*xcpt? */ false, false },
2052 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
2053 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },
2054 { /* => */ { FP64_V(1, 0, 2), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2055 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
2056 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2057 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2058 /*xcpt? */ false, false },
2059 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2060 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2061 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2062 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2063 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
2064 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
2065 /*xcpt? */ false, false },
2066 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },
2067 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },
2068 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } },
2069 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2070 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2071 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2072 /*xcpt? */ true, true },
2073 /** @todo Why does the below on cause PE?! */
2074 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/* 1.75*/, FP64_NORM_MAX(0), FP64_0(0), FP64_V(0, 0, 0x3fd)/*0.25*/ } },
2075 { /*src1 */ { FP64_V(1, 0, 0x07d)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0, 0x3fe)/*0.50*/ } },
2076 { /* => */ { FP64_V(0, 0xbffffffffffff, 0x3ff)/* 1.50*/, FP64_0(1), FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } },
2077 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2078 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
2079 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
2080 /*xcpt? */ false, false },
2081 /*
2082 * Normals.
2083 */
2084 /*17*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } },
2085 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_0(0) } },
2086 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2087 /*mxcsr:in */ 0,
2088 /*128:out */ 0,
2089 /*256:out */ 0,
2090 /*xcpt? */ false, false },
2091 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_0(0), FP64_0(0) } },
2092 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_0(0), FP64_0(0) } },
2093 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_0(0), FP64_0(0) } },
2094 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2095 /*128:out */ X86_MXCSR_XCPT_MASK,
2096 /*256:out */ X86_MXCSR_XCPT_MASK,
2097 /*xcpt? */ false, false },
2098 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
2099 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } },
2100 { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
2101 /*mxcsr:in */ 0,
2102 /*128:out */ 0,
2103 /*256:out */ 0,
2104 /*xcpt? */ false, false },
2105 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } },
2106 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_0(0), FP64_0(0) } },
2107 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
2108 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2109 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2110 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2111 /*xcpt? */ false, false },
2112 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_0(0), FP64_0(0) } },
2113 { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_0(0) } },
2114 { /* => */ { FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_0(0), FP64_0(0) } },
2115 /*mxcsr:in */ X86_MXCSR_FZ,
2116 /*128:out */ X86_MXCSR_FZ,
2117 /*256:out */ X86_MXCSR_FZ,
2118 /*xcpt? */ false, false },
2119 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
2120 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },
2121 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2) } },
2122 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2123 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2124 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2125 /*xcpt? */ false, false },
2126 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
2127 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
2128 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2) } },
2129 /*mxcsr:in */ X86_MXCSR_RC_UP,
2130 /*128:out */ X86_MXCSR_RC_UP,
2131 /*256:out */ X86_MXCSR_RC_UP,
2132 /*xcpt? */ false, false },
2133 /*
2134 * Denormals.
2135 */
2136 /*24*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2137 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2138 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2139 /*mxcsr:in */ 0,
2140 /*128:out */ X86_MXCSR_DE,
2141 /*256:out */ X86_MXCSR_DE,
2142 /*xcpt? */ true, true },
2143 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2144 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
2145 { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
2146 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2147 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
2148 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
2149 /*xcpt? */ false, false },
2150 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
2151 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
2152 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2153 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2154 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2155 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2156 /*xcpt? */ false, false },
2157 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
2158 /*
2159 * Invalids.
2160 */
2161 /*27*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2162 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2163 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2164 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2165 /*128:out */ X86_MXCSR_XCPT_MASK,
2166 /*256:out */ X86_MXCSR_XCPT_MASK,
2167 /*xcpt? */ false, false },
2168 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2169 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2170 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2171 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2172 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2173 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2174 /*xcpt? */ false, false },
2175 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2176 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2177 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2178 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2179 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2180 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2181 /*xcpt? */ false, false },
2182 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2183 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
2184 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
2185 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2186 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2187 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2188 /*xcpt? */ false, false },
2189 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2190 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
2191 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2192 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2193 /*128:out */ X86_MXCSR_XCPT_MASK,
2194 /*256:out */ X86_MXCSR_XCPT_MASK,
2195 /*xcpt? */ false, false },
2196 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2197 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
2198 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2199 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2200 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2201 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2202 /*xcpt? */ false, false },
2203 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2204 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2205 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2206 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2207 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2208 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2209 /*xcpt? */ false, false },
2210 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
2211 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
2212 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
2213 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2214 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2215 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2216 /*xcpt? */ true, true },
2217 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2218 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2219 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2220 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2221 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2222 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2223 /*xcpt? */ true, true },
2224 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2225 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
2226 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2227 /*mxcsr:in */ X86_MXCSR_RC_UP,
2228 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
2229 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
2230 /*xcpt? */ true, true },
2231 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2232 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
2233 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2234 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
2235 /*128:out */ X86_MXCSR_RC_DOWN,
2236 /*256:out */ X86_MXCSR_RC_DOWN,
2237 /*xcpt? */ false, false },
2238 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2239 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
2240 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2241 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2242 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2243 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2244 /*xcpt? */ true, true },
2245 };
2246
2247 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2248 {
2249 { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2250 { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2251
2252 { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2253 { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2254
2255 { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2256 { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2257 };
2258 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2259 {
2260 { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2261 { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2262
2263 { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2264 { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2265
2266 { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2267 { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2268 };
2269 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2270 {
2271 { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2272 { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2273
2274 { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2275 { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2276
2277 { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2278 { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2279
2280 { bs3CpuInstr4_addpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2281 { bs3CpuInstr4_addpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2282
2283 { bs3CpuInstr4_vaddpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2284 { bs3CpuInstr4_vaddpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2285 };
2286
2287 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2288 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2289 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2290 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
2291}
2292
2293
2294/*
2295 * [V]ADDSS.
2296 */
2297BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addss(uint8_t bMode)
2298{
2299 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
2300 {
2301 /*
2302 * Zero.
2303 */
2304 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2305 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2306 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2307 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2308 /*128:out */ X86_MXCSR_XCPT_MASK,
2309 /*256:out */ X86_MXCSR_XCPT_MASK,
2310 /*xcpt? */ false, false },
2311 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2312 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2313 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2314 /*mxcsr:in */ 0,
2315 /*128:out */ 0,
2316 /*256:out */ 0,
2317 /*xcpt? */ false, false },
2318 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2319 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2320 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2321 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2322 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2323 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2324 /*xcpt? */ false, false },
2325 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2326 { /*src1 */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2327 { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2328 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2329 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2330 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2331 /*xcpt? */ false, false },
2332 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2333 { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2334 { /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2335 /*mxcsr:in */ X86_MXCSR_FZ,
2336 /*128:out */ X86_MXCSR_FZ,
2337 /*256:out */ X86_MXCSR_FZ,
2338 /*xcpt? */ false, false },
2339 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2340 { /*src1 */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2341 { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2342 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2343 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2344 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2345 /*xcpt? */ false, false },
2346 /*
2347 * Infinity.
2348 */
2349 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2350 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2351 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2352 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
2353 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2354 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2355 /*xcpt? */ true, true },
2356 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2357 { /*src1 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2358 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2359 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
2360 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2361 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2362 /*xcpt? */ true, true },
2363 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2364 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2365 { /* => */ { FP32_QNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2366 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
2367 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2368 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2369 /*xcpt? */ false, false },
2370 { { /*src2 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2371 { /*src1 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2372 { /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2373 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
2374 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2375 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2376 /*xcpt? */ false, false },
2377 { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2378 { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2379 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2380 /*mxcsr:in */ X86_MXCSR_FZ,
2381 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2382 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2383 /*xcpt? */ true, true },
2384 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
2385 { /*src1 */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2386 { /* => */ { FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2387 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2388 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2389 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2390 /*xcpt? */ true, true },
2391 /*
2392 * Overflow, Precision.
2393 */
2394 /*12*/{ { /*src2 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
2395 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2396 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2397 /*mxcsr:in */ 0,
2398 /*128:out */ X86_MXCSR_OE,
2399 /*256:out */ X86_MXCSR_OE,
2400 /*xcpt? */ true, true },
2401 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2402 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2403 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2404 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2405 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2406 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2407 /*xcpt? */ false, false },
2408 { { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2409 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2410 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2411 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
2412 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2413 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2414 /*xcpt? */ false, false },
2415 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2416 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2417 { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2418 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2419 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2420 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2421 /*xcpt? */ false, false },
2422 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
2423 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2424 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2425 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2426 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2427 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2428 /*xcpt? */ true, true },
2429 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2430 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2431 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2432 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2433 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2434 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2435 /*xcpt? */ true, true },
2436 /*
2437 * Normals.
2438 */
2439 /*18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2440 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2441 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2442 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2443 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2444 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2445 /*xcpt? */ false, false },
2446 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
2447 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2448 { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2449 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2450 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2451 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2452 /*xcpt? */ false, false },
2453 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2454 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2455 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2456 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2457 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2458 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2459 /*xcpt? */ false, false },
2460 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2461 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2462 { /* => */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2463 /*mxcsr:in */ 0,
2464 /*128:out */ 0,
2465 /*256:out */ 0,
2466 /*xcpt? */ false, false },
2467 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2468 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2469 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2470 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2471 /*128:out */ X86_MXCSR_RC_ZERO,
2472 /*256:out */ X86_MXCSR_RC_ZERO,
2473 /*xcpt? */ false, false },
2474 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2475 { /*src1 */ { FP32_1(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2476 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2477 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2478 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2479 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2480 /*xcpt? */ false, false },
2481 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2482 { /*src1 */ { FP32_1(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2483 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2484 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2485 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2486 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2487 /*xcpt? */ false, false },
2488 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2489 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2490 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2491 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2492 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2493 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2494 /*xcpt? */ false, false },
2495 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
2496 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2497 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2498 /*mxcsr:in */ X86_MXCSR_FZ,
2499 /*128:out */ X86_MXCSR_FZ,
2500 /*256:out */ X86_MXCSR_FZ,
2501 /*xcpt? */ false, false },
2502 /*
2503 * Denormals.
2504 */
2505 /*27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
2506 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
2507 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
2508 /*mxcsr:in */ X86_MXCSR_DE,
2509 /*128:out */ X86_MXCSR_DE,
2510 /*256:out */ X86_MXCSR_DE,
2511 /*xcpt? */ true, true },
2512 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
2513 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2514 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2515 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2516 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2517 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2518 /*xcpt? */ false, false },
2519 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
2520 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
2521 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
2522 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
2523 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
2524 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
2525 /*xcpt? */ true, true },
2526 /** @todo More denormals etc. */
2527 /*
2528 * Invalids.
2529 */
2530 /* QNan, QNan (Masked). */
2531 /*30*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2532 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2533 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2534 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2535 /*128:out */ X86_MXCSR_XCPT_MASK,
2536 /*256:out */ X86_MXCSR_XCPT_MASK,
2537 /*xcpt? */ false, false },
2538 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2539 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2540 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2541 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2542 /*128:out */ X86_MXCSR_XCPT_MASK,
2543 /*256:out */ X86_MXCSR_XCPT_MASK,
2544 /*xcpt? */ false, false },
2545 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2546 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2547 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2548 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2549 /*128:out */ X86_MXCSR_XCPT_MASK,
2550 /*256:out */ X86_MXCSR_XCPT_MASK,
2551 /*xcpt? */ false, false },
2552 /* QNan, SNan (Masked). */
2553 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2554 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2555 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2556 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2557 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2558 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2559 /*xcpt? */ false, false },
2560 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2561 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2562 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2563 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2564 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2565 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2566 /*xcpt? */ false, false },
2567 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2568 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2569 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2570 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2571 /*128:out */ X86_MXCSR_XCPT_MASK,
2572 /*256:out */ X86_MXCSR_XCPT_MASK,
2573 /*xcpt? */ false, false },
2574 /* SNan, QNan (Masked). */
2575 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2576 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2577 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2578 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2579 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2580 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2581 /*xcpt? */ false, false },
2582 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2583 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2584 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2585 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2586 /*128:out */ X86_MXCSR_XCPT_MASK,
2587 /*256:out */ X86_MXCSR_XCPT_MASK,
2588 /*xcpt? */ false, false },
2589 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2590 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2591 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2592 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2593 /*128:out */ X86_MXCSR_XCPT_MASK,
2594 /*256:out */ X86_MXCSR_XCPT_MASK,
2595 /*xcpt? */ false, false },
2596 /* SNan, SNan (Masked). */
2597 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2598 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2599 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2600 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2601 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2602 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2603 /*xcpt? */ false, false },
2604 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2605 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2606 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2607 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2608 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2609 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2610 /*xcpt? */ false, false },
2611 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2612 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2613 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2614 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2615 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2616 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2617 /*xcpt? */ false, false },
2618 /* QNan, Norm FP (Masked). */
2619 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
2620 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2621 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2622 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2623 /*128:out */ X86_MXCSR_XCPT_MASK,
2624 /*256:out */ X86_MXCSR_XCPT_MASK,
2625 /*xcpt? */ false, false },
2626 /* SNan, Norm FP (Masked). */
2627 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
2628 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2629 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2630 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2631 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2632 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2633 /*xcpt? */ false, false },
2634 /* QNan, QNan (Unmasked). */
2635 /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2636 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2637 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2638 /*mxcsr:in */ 0,
2639 /*128:out */ 0,
2640 /*256:out */ 0,
2641 /*xcpt? */ false, false },
2642 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2643 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2644 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2645 /*mxcsr:in */ 0,
2646 /*128:out */ 0,
2647 /*256:out */ 0,
2648 /*xcpt? */ false, false },
2649 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2650 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2651 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2652 /*mxcsr:in */ 0,
2653 /*128:out */ 0,
2654 /*256:out */ 0,
2655 /*xcpt? */ false, false },
2656
2657 /* QNan, SNan (Unmasked). */
2658 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2659 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2660 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2661 /*mxcsr:in */ 0,
2662 /*128:out */ X86_MXCSR_IE,
2663 /*256:out */ X86_MXCSR_IE,
2664 /*xcpt? */ true, true },
2665 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2666 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2667 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2668 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2669 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2670 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2671 /*xcpt? */ true, true },
2672 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2673 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2674 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2675 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2676 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2677 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2678 /*xcpt? */ false, false },
2679 /* SNan, QNan (Unmasked). */
2680 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2681 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2682 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2683 /*mxcsr:in */ X86_MXCSR_DAZ,
2684 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
2685 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
2686 /*xcpt? */ true, true },
2687 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2688 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2689 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2690 /*mxcsr:in */ X86_MXCSR_RC_UP,
2691 /*128:out */ X86_MXCSR_RC_UP,
2692 /*256:out */ X86_MXCSR_RC_UP,
2693 /*xcpt? */ false, false },
2694 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2695 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2696 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2697 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2698 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2699 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2700 /*xcpt? */ false, false },
2701 /* SNan, SNan (Unmasked). */
2702 /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2703 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2704 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2705 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
2706 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
2707 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
2708 /*xcpt? */ true, true },
2709 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2710 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2711 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2712 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2713 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2714 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2715 /*xcpt? */ true, true },
2716 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2717 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2718 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2719 /*mxcsr:in */ 0,
2720 /*128:out */ X86_MXCSR_IE,
2721 /*256:out */ X86_MXCSR_IE,
2722 /*xcpt? */ true, true },
2723 /* QNan, Norm FP (Unmasked). */
2724 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
2725 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2726 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2727 /*mxcsr:in */ X86_MXCSR_FZ,
2728 /*128:out */ X86_MXCSR_FZ,
2729 /*256:out */ X86_MXCSR_FZ,
2730 /*xcpt? */ false, false },
2731 /* SNan, Norm FP (Unmasked). */
2732 /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
2733 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2734 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2735 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2736 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2737 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2738 /*xcpt? */ true, true },
2739 /** @todo Underflow, Precision; Rounding, FZ etc. */
2740 };
2741
2742 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2743 {
2744 { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2745 { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2746
2747 { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2748 { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2749 };
2750 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2751 {
2752 { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2753 { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2754
2755 { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2756 { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2757 };
2758 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2759 {
2760 { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2761 { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2762
2763 { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2764 { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2765
2766 { bs3CpuInstr4_addss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2767 { bs3CpuInstr4_addss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2768 };
2769
2770 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2771 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2772 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2773 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
2774}
2775
2776
2777/*
2778 * [V]ADDSD.
2779 */
2780BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addsd(uint8_t bMode)
2781{
2782 static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] =
2783 {
2784 /*
2785 * Zero.
2786 */
2787 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2788 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2789 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2790 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2791 /*128:out */ X86_MXCSR_XCPT_MASK,
2792 /*256:out */ X86_MXCSR_XCPT_MASK,
2793 /*xcpt? */ false, false },
2794 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2795 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2796 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2797 /*mxcsr:in */ 0,
2798 /*128:out */ 0,
2799 /*256:out */ 0,
2800 /*xcpt? */ false, false },
2801 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2802 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2803 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2804 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2805 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2806 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2807 /*xcpt? */ false, false },
2808 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2809 { /*src1 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
2810 { /* => */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
2811 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2812 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2813 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2814 /*xcpt? */ false, false },
2815 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2816 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } },
2817 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } },
2818 /*mxcsr:in */ X86_MXCSR_FZ,
2819 /*128:out */ X86_MXCSR_FZ,
2820 /*256:out */ X86_MXCSR_FZ,
2821 /*xcpt? */ false, false },
2822 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2823 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
2824 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(1) } },
2825 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2826 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2827 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2828 /*xcpt? */ false, false },
2829 /*
2830 * Infinity.
2831 */
2832 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2833 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
2834 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2835 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
2836 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2837 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2838 /*xcpt? */ true, true },
2839 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } },
2840 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
2841 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
2842 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
2843 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2844 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2845 /*xcpt? */ true, true },
2846 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2847 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
2848 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
2849 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
2850 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2851 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2852 /*xcpt? */ false, false },
2853 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2854 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
2855 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
2856 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
2857 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2858 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2859 /*xcpt? */ false, false },
2860 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
2861 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
2862 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
2863 /*mxcsr:in */ X86_MXCSR_FZ,
2864 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2865 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2866 /*xcpt? */ true, true },
2867 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
2868 { /*src1 */ { FP64_INF(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2869 { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2870 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2871 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2872 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2873 /*xcpt? */ true, true },
2874 /** @todo Normals, Denormals, Overflow/Precision, Invalids etc. */
2875 /*
2876 * Overflow, Precision.
2877 */
2878 /*12*/{ { /*src2 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
2879 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2880 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2881 /*mxcsr:in */ 0,
2882 /*128:out */ X86_MXCSR_OE,
2883 /*256:out */ X86_MXCSR_OE,
2884 /*xcpt? */ true, true },
2885 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2886 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2887 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2888 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2889 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2890 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2891 /*xcpt? */ false, false },
2892 { { /*src2 */ { FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
2893 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2894 { /* => */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2895 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
2896 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2897 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2898 /*xcpt? */ false, false },
2899 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2900 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2901 { /* => */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2902 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2903 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2904 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2905 /*xcpt? */ false, false },
2906 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
2907 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2908 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2909 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2910 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2911 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2912 /*xcpt? */ true, true },
2913 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
2914 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2915 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2916 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2917 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2918 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2919 /*xcpt? */ true, true },
2920 };
2921
2922 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2923 {
2924 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2925 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2926
2927 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2928 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2929 };
2930 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2931 {
2932 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2933 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2934
2935 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2936 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2937 };
2938 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2939 {
2940 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2941 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2942
2943 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2944 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2945
2946 { bs3CpuInstr4_addsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2947 { bs3CpuInstr4_addsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2948 };
2949
2950 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2951 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2952 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2953 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
2954}
2955
2956
2957/*
2958 * [V]HADDPS.
2959 */
2960BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddps(uint8_t bMode)
2961{
2962 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
2963 {
2964 /*
2965 * Zero.
2966 */
2967 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2968 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2969 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2970 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2971 /*128:out */ X86_MXCSR_XCPT_MASK,
2972 /*256:out */ X86_MXCSR_XCPT_MASK,
2973 /*xcpt? */ false, false },
2974 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2975 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2976 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2977 /*mxcsr:in */ 0,
2978 /*128:out */ 0,
2979 /*256:out */ 0,
2980 /*xcpt? */ false, false },
2981 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2982 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2983 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2984 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2985 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2986 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2987 /*xcpt? */ false, false },
2988 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
2989 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
2990 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2991 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2992 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2993 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2994 /*xcpt? */ false, false },
2995 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
2996 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
2997 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
2998 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2999 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3000 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3001 /*xcpt? */ false, false },
3002 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3003 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3004 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
3005 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3006 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3007 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3008 /*xcpt? */ false, false },
3009 /*
3010 * Infinity.
3011 */
3012 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
3013 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3014 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1) } },
3015 /*mxcsr:in */ X86_MXCSR_IM,
3016 /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE,
3017 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE,
3018 /*xcpt? */ false, false },
3019 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3020 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
3021 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
3022 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3023 /*128:out */ X86_MXCSR_XCPT_MASK,
3024 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3025 /*xcpt? */ false, false },
3026 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3027 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
3028 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
3029 /*mxcsr:in */ X86_MXCSR_FZ,
3030 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3031 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3032 /*xcpt? */ true, true },
3033 { { /*src2 */ { FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0) } },
3034 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3035 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0) } },
3036 /*mxcsr:in */ 0,
3037 /*128:out */ 0,
3038 /*256:out */ 0,
3039 /*xcpt? */ false, false },
3040 { { /*src2 */ { FP32_INF(0), FP32_QNAN(1), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3041 { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } },
3042 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
3043 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3044 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3045 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3046 /*xcpt? */ false, false },
3047 /*
3048 * Overflow, Precision.
3049 */
3050 /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
3051 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
3052 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3053 /*mxcsr:in */ 0,
3054 /*128:out */ 0,
3055 /*256:out */ X86_MXCSR_OE,
3056 /*xcpt? */ false, true },
3057 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3058 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3059 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3060 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
3061 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3062 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3063 /*xcpt? */ false, false },
3064 { { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
3065 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
3066 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3067 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3068 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3069 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3070 /*xcpt? */ false, false },
3071 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3072 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1) } },
3073 { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0), FP32_NORM_MAX(0) } },
3074 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
3075 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3076 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3077 /*xcpt? */ false, false },
3078 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3079 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
3080 { /* => */ { FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(0) } },
3081 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3082 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3083 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3084 /*xcpt? */ false, false },
3085 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
3086 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
3087 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } },
3088 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3089 /*128:out */ X86_MXCSR_RC_ZERO,
3090 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE,
3091 /*xcpt? */ false, true },
3092 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3093 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3094 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } },
3095 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3096 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3097 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3098 /*xcpt? */ false, false },
3099 /*
3100 * Normals.
3101 */
3102 /*18*/{ { /*src2 */ { FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_V(0, 0, 0x7d)/*0.25*/ } },
3103 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_0(0), FP32_0(0) } },
3104 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x600000, 0x7f)/*1.75*/ } },
3105 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3106 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3107 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3108 /*xcpt? */ false, false },
3109 { { /*src2 */ { FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V4(1), FP32_NORM_V4(0), FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V2(0) } },
3110 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_V3(0), FP32_NORM_V3(1) } },
3111 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3112 /*mxcsr:in */ 0,
3113 /*128:out */ 0,
3114 /*256:out */ 0,
3115 /*xcpt? */ false, false },
3116 { { /*src2 */ { FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/* 7.00*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_0(0), FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
3117 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(1, 0x1ea980, 0x8f)/* -81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/*7*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_1(1) } },
3118 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
3119 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3120 /*128:out */ X86_MXCSR_XCPT_MASK,
3121 /*256:out */ X86_MXCSR_XCPT_MASK,
3122 /*xcpt? */ false, false },
3123 { { /*src2 */ { FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_1(1) } },
3124 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_NORM_V3(1), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_0(0), FP32_1(0) } },
3125 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V3(1), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_NORM_V1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(0), FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1) } },
3126 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3127 /*128:out */ X86_MXCSR_XCPT_MASK,
3128 /*256:out */ X86_MXCSR_XCPT_MASK,
3129 /*xcpt? */ false, false },
3130 { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0), FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0) } },
3131 { /*src1 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } },
3132 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1) } },
3133 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3134 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3135 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3136 /*xcpt? */ false, false },
3137 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } },
3138 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } },
3139 { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } },
3140 /*mxcsr:in */ 0,
3141 /*128:out */ 0,
3142 /*256:out */ 0,
3143 /*xcpt? */ false, false },
3144 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } },
3145 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } },
3146 { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } },
3147 /*mxcsr:in */ X86_MXCSR_FZ,
3148 /*128:out */ X86_MXCSR_FZ,
3149 /*256:out */ X86_MXCSR_FZ,
3150 /*xcpt? */ false, false },
3151 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
3152 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } },
3153 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, 2), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
3154 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3155 /*128:out */ X86_MXCSR_XCPT_MASK,
3156 /*256:out */ X86_MXCSR_XCPT_MASK,
3157 /*xcpt? */ false, false },
3158 /*
3159 * Denormals.
3160 */
3161 /*26*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3162 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3163 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3164 /*mxcsr:in */ 0,
3165 /*128:out */ X86_MXCSR_DE,
3166 /*256:out */ X86_MXCSR_DE,
3167 /*xcpt? */ true, true },
3168 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3169 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
3170 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3171 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3172 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3173 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3174 /*xcpt? */ false, false },
3175 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
3176 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
3177 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), } },
3178 /*mxcsr:in */ X86_MXCSR_DAZ,
3179 /*128:out */ X86_MXCSR_DAZ,
3180 /*256:out */ X86_MXCSR_DAZ,
3181 /*xcpt? */ false, false },
3182 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3183 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3184 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3185 /*mxcsr:in */ 0,
3186 /*128:out */ X86_MXCSR_DE,
3187 /*256:out */ X86_MXCSR_DE,
3188 /*xcpt? */ true, true },
3189 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3190 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3191 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3192 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3193 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3194 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3195 /*xcpt? */ false, false },
3196 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
3197 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
3198 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3199 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3200 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3201 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3202 /*xcpt? */ false, false },
3203 /** @todo Denormals; Rounding, FZ etc. */
3204 /*
3205 * Invalids.
3206 */
3207 /*32*/{ { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3208 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3209 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },
3210 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3211 /*128:out */ X86_MXCSR_XCPT_MASK,
3212 /*256:out */ X86_MXCSR_XCPT_MASK,
3213 /*xcpt? */ false, false },
3214 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },
3215 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3216 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3217 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3218 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3219 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3220 /*xcpt? */ false, false },
3221 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3222 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3223 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3224 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3225 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3226 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3227 /*xcpt? */ false, false },
3228 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3229 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3230 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3231 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3232 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3233 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3234 /*xcpt? */ false, false },
3235 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },
3236 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3237 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3238 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3239 /*128:out */ X86_MXCSR_XCPT_MASK,
3240 /*256:out */ X86_MXCSR_XCPT_MASK,
3241 /*xcpt? */ false, false },
3242 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },
3243 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3244 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3245 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3246 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3247 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3248 /*xcpt? */ false, false },
3249 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3250 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3251 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },
3252 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3253 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3254 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3255 /*xcpt? */ false, false },
3256 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },
3257 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3258 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3259 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
3260 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3261 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3262 /*xcpt? */ true, true },
3263 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3264 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3265 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3266 /*mxcsr:in */ 0,
3267 /*128:out */ X86_MXCSR_IE,
3268 /*256:out */ X86_MXCSR_IE,
3269 /*xcpt? */ true, true },
3270 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3271 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3272 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3273 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3274 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3275 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3276 /*xcpt? */ true, true },
3277 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },
3278 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3279 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3280 /*mxcsr:in */ 0,
3281 /*128:out */ 0,
3282 /*256:out */ 0,
3283 /*xcpt? */ false, false },
3284 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },
3285 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3286 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3287 /*mxcsr:in */ X86_MXCSR_RC_UP,
3288 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
3289 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
3290 /*xcpt? */ true, true },
3291 /** @todo Underflow, Precision; Rounding, FZ etc. */
3292 };
3293
3294 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3295 {
3296 { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3297 { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3298
3299 { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3300 { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3301
3302 { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3303 { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3304 };
3305 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3306 {
3307 { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3308 { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3309
3310 { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3311 { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3312
3313 { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3314 { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3315 };
3316 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3317 {
3318 { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3319 { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3320
3321 { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3322 { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3323
3324 { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3325 { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3326
3327 { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3328 { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3329
3330 { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3331 { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3332 };
3333
3334 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3335 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3336 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3337 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
3338}
3339
3340
3341/*
3342 * [V]SUBPS.
3343 */
3344BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subps(uint8_t bMode)
3345{
3346 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
3347 {
3348 /*
3349 * Zero.
3350 */
3351 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3352 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3353 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3354 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3355 /*128:out */ X86_MXCSR_XCPT_MASK,
3356 /*256:out */ X86_MXCSR_XCPT_MASK,
3357 /*xcpt? */ false, false },
3358 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3359 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3360 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3361 /*mxcsr:in */ 0,
3362 /*128:out */ 0,
3363 /*256:out */ 0,
3364 /*xcpt? */ false, false },
3365 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3366 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3367 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3368 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3369 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3370 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3371 /*xcpt? */ false, false },
3372 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
3373 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
3374 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3375 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3376 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3377 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3378 /*xcpt? */ false, false },
3379 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
3380 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
3381 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
3382 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
3383 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
3384 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
3385 /*xcpt? */ false, false },
3386 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3387 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3388 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3389 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS,
3390 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS,
3391 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS,
3392 /*xcpt? */ false, false },
3393 /*
3394 * Infinity.
3395 */
3396 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3397 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3398 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3399 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3400 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3401 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3402 /*xcpt? */ false, false },
3403 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3404 { /*src1 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3405 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
3406 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3407 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3408 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3409 /*xcpt? */ false, false },
3410 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3411 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3412 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
3413 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3414 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3415 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3416 /*xcpt? */ false, false },
3417 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
3418 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
3419 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
3420 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3421 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3422 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
3423 /*xcpt? */ false, false },
3424 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3425 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
3426 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
3427 /*mxcsr:in */ X86_MXCSR_FZ,
3428 /*128:out */ X86_MXCSR_FZ,
3429 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3430 /*xcpt? */ false, true },
3431 { { /*src2 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
3432 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
3433 { /* => */ { FP32_INF(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
3434 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3435 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3436 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3437 /*xcpt? */ true, true },
3438 /*
3439 * Overflow, Precision.
3440 */
3441 /*12*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3442 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
3443 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3444 /*mxcsr:in */ 0,
3445 /*128:out */ 0,
3446 /*256:out */ X86_MXCSR_PE,
3447 /*xcpt? */ false, true },
3448 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
3449 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3450 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0) } },
3451 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
3452 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3453 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3454 /*xcpt? */ false, false },
3455 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
3456 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
3457 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
3458 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
3459 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3460 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3461 /*xcpt? */ false, false },
3462 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, 2), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
3463 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
3464 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0) } },
3465 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
3466 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3467 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3468 /*xcpt? */ false, false },
3469 { { /*src2 */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },
3470 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },
3471 { /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
3472 /*mxcsr:in */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
3473 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3474 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3475 /*xcpt? */ false, false },
3476 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3477 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3478 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } },
3479 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3480 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3481 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3482 /*xcpt? */ false, false },
3483 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3484 { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3485 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3486 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3487 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3488 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3489 /*xcpt? */ true, true },
3490 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3491 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3492 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3493 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
3494 /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
3495 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
3496 /*xcpt? */ true, true },
3497 /*
3498 * Normals.
3499 */
3500 /*20*/{ { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_0(0), FP32_0(1), FP32_V(0, 0x400000, 0x7e)/* 0.75*/ } },
3501 { /*src1 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_0(0), FP32_0(0), FP32_0(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(0), FP32_0(1), FP32_V(0, 0, 0x7e)/* 0.50*/ } },
3502 { /* => */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/*-0.25*/ } },
3503 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3504 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3505 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3506 /*xcpt? */ false, false },
3507 { { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
3508 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
3509 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3510 /*mxcsr:in */ 0,
3511 /*128:out */ 0,
3512 /*256:out */ 0,
3513 /*xcpt? */ false, false },
3514 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x2514d6, 0x93)/* 1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_0(0) } },
3515 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(1, 0x7c9000, 0x88)/* -1010.25*/, FP32_1(0) /* 1.00*/, FP32_0(0) } },
3516 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_0(0), FP32_V(1, 0x780000, 0x84)/*-62*/, FP32_V(1, 0x253468, 0x93)/*-1353357.00*/, FP32_V(1, 0x524000, 0x86)/*210.25*/, FP32_0(0) } },
3517 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ,
3518 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ,
3519 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ,
3520 /*xcpt? */ false, false },
3521 { { /*src2 */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0) } },
3522 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/* 12345678*/, FP32_0(0), FP32_1(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_1(0), FP32_1(0) } },
3523 { /* => */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_V(0, 0x3c614e, 0x97)/* 24691356*/, FP32_0(1), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } },
3524 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
3525 /*128:out */ X86_MXCSR_RC_DOWN,
3526 /*256:out */ X86_MXCSR_RC_DOWN,
3527 /*xcpt? */ false, false },
3528 { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } },
3529 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_0(1), FP32_0(0) } },
3530 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0) } },
3531 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3532 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3533 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3534 /*xcpt? */ false, false },
3535 { { /*src2 */ { FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0) } },
3536 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
3537 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(0), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(0) } },
3538 /*mxcsr:in */ X86_MXCSR_RC_UP,
3539 /*128:out */ X86_MXCSR_RC_UP,
3540 /*256:out */ X86_MXCSR_RC_UP,
3541 /*xcpt? */ false, false },
3542 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },
3543 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } },
3544 { /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0) } },
3545 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3546 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3547 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3548 /*xcpt? */ false, false },
3549 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
3550 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },
3551 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, 2), FP32_V(1, 0, 2), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } },
3552 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3553 /*128:out */ X86_MXCSR_XCPT_MASK,
3554 /*256:out */ X86_MXCSR_XCPT_MASK,
3555 /*xcpt? */ false, false },
3556 /*
3557 * Denormals.
3558 */
3559 /*28*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3560 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3561 { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3562 /*mxcsr:in */ 0,
3563 /*128:out */ X86_MXCSR_DE,
3564 /*256:out */ X86_MXCSR_DE,
3565 /*xcpt? */ true, true },
3566 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3567 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
3568 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
3569 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3570 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
3571 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
3572 /*xcpt? */ false, false },
3573 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
3574 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
3575 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3576 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3577 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3578 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3579 /*xcpt? */ false, false },
3580 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3581 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3582 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3583 /*mxcsr:in */ 0,
3584 /*128:out */ X86_MXCSR_DE,
3585 /*256:out */ X86_MXCSR_DE,
3586 /*xcpt? */ true, true },
3587 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3588 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3589 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0) } },
3590 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3591 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
3592 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
3593 /*xcpt? */ false, false },
3594 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0) } },
3595 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } },
3596 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3597 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3598 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3599 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3600 /*xcpt? */ false, false },
3601 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
3602 /*
3603 * Invalids.
3604 */
3605 /*34*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3606 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3607 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3608 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3609 /*128:out */ X86_MXCSR_XCPT_MASK,
3610 /*256:out */ X86_MXCSR_XCPT_MASK,
3611 /*xcpt? */ false, false },
3612 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3613 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3614 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3615 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3616 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3617 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3618 /*xcpt? */ false, false },
3619 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
3620 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3621 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3622 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3623 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
3624 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
3625 /*xcpt? */ false, false },
3626 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3627 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3628 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
3629 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3630 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3631 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3632 /*xcpt? */ false, false },
3633 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3634 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3635 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3636 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3637 /*128:out */ X86_MXCSR_XCPT_MASK,
3638 /*256:out */ X86_MXCSR_XCPT_MASK,
3639 /*xcpt? */ false, false },
3640 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
3641 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3642 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3643 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3644 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3645 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3646 /*xcpt? */ false, false },
3647 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3648 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3649 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3650 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3651 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3652 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3653 /*xcpt? */ false, false },
3654 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3655 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3656 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3657 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3658 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3659 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3660 /*xcpt? */ true, true },
3661 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
3662 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3663 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3664 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3665 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3666 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3667 /*xcpt? */ true, true },
3668 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3669 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3670 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
3671 /*mxcsr:in */ X86_MXCSR_RC_UP,
3672 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
3673 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
3674 /*xcpt? */ true, true },
3675 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3676 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3677 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3678 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
3679 /*128:out */ X86_MXCSR_RC_DOWN,
3680 /*256:out */ X86_MXCSR_RC_DOWN,
3681 /*xcpt? */ false, false },
3682 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
3683 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3684 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
3685 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3686 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3687 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3688 /*xcpt? */ true, true },
3689 };
3690
3691 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3692 {
3693 { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3694 { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3695
3696 { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3697 { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3698
3699 { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3700 { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3701 };
3702 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3703 {
3704 { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3705 { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3706
3707 { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3708 { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3709
3710 { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3711 { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3712 };
3713 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3714 {
3715 { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3716 { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3717
3718 { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3719 { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3720
3721 { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3722 { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3723
3724 { bs3CpuInstr4_subps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3725 { bs3CpuInstr4_subps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3726
3727 { bs3CpuInstr4_vsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3728 { bs3CpuInstr4_vsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3729 };
3730
3731 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3732 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3733 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3734 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
3735}
3736
3737
3738/*
3739 * [V]SUBPD.
3740 */
3741BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subpd(uint8_t bMode)
3742{
3743 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
3744 {
3745 /*
3746 * Zero.
3747 */
3748 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3749 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3750 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3751 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3752 /*128:out */ X86_MXCSR_XCPT_MASK,
3753 /*256:out */ X86_MXCSR_XCPT_MASK,
3754 /*xcpt? */ false, false },
3755 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3756 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3757 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3758 /*mxcsr:in */ 0,
3759 /*128:out */ 0,
3760 /*256:out */ 0,
3761 /*xcpt? */ false, false },
3762 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3763 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3764 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3765 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3766 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3767 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3768 /*xcpt? */ false, false },
3769 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
3770 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
3771 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3772 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3773 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3774 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3775 /*xcpt? */ false, false },
3776 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
3777 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
3778 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
3779 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3780 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3781 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3782 /*xcpt? */ false, false },
3783 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3784 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } },
3785 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
3786 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3787 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3788 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3789 /*xcpt? */ false, false },
3790 /*
3791 * Infinity.
3792 */
3793 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_INF(1) } },
3794 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3795 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3796 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3797 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3798 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
3799 /*xcpt? */ false, false },
3800 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } },
3801 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
3802 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(0), FP64_QNAN(1) } },
3803 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3804 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3805 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3806 /*xcpt? */ false, false },
3807 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
3808 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
3809 { /* => */ { FP64_QNAN(1), FP64_INF(1), FP64_INF(0), FP64_QNAN(1) } },
3810 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3811 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3812 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3813 /*xcpt? */ false, false },
3814 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } },
3815 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(1) } },
3816 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_QNAN(1) } },
3817 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3818 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
3819 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
3820 /*xcpt? */ false, false },
3821 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3822 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } },
3823 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_QNAN(1) } },
3824 /*mxcsr:in */ X86_MXCSR_FZ,
3825 /*128:out */ X86_MXCSR_FZ,
3826 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3827 /*xcpt? */ false, true },
3828 { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
3829 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
3830 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_0(1), FP64_0(1) } },
3831 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3832 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3833 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3834 /*xcpt? */ true, true },
3835 /*
3836 * Overflow, Precision.
3837 */
3838 /*12*/{ { /*src2 */ { FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3839 { /*src1 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
3840 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3841 /*mxcsr:in */ 0,
3842 /*128:out */ X86_MXCSR_PE,
3843 /*256:out */ X86_MXCSR_PE,
3844 /*xcpt? */ true, true },
3845 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3846 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
3847 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3848 /*mxcsr:in */ 0,
3849 /*128:out */ 0,
3850 /*256:out */ X86_MXCSR_PE,
3851 /*xcpt? */ false, true },
3852 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
3853 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
3854 { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } },
3855 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3856 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3857 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3858 /*xcpt? */ false, false },
3859 { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } },
3860 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
3861 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } },
3862 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
3863 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
3864 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
3865 /*xcpt? */ false, false },
3866 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },
3867 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
3868 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } },
3869 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
3870 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3871 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3872 /*xcpt? */ false, false },
3873 { { /*src2 */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } },
3874 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },
3875 { /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
3876 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
3877 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3878 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3879 /*xcpt? */ false, false },
3880 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
3881 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
3882 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
3883 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3884 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3885 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3886 /*xcpt? */ false, false },
3887 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3888 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
3889 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3890 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
3891 /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3892 /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3893 /*xcpt? */ true, true },
3894 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
3895 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
3896 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3897 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3898 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3899 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3900 /*xcpt? */ true, true },
3901 /*
3902 * Normals.
3903 */
3904 /*21*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
3905 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
3906 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3907 /*mxcsr:in */ 0,
3908 /*128:out */ 0,
3909 /*256:out */ 0,
3910 /*xcpt? */ false, false },
3911 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/ } },
3912 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0, 0x409)/*1024*/ } },
3913 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(1, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(1, 0, 0x408)/* 512*/ } },
3914 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3915 /*128:out */ X86_MXCSR_XCPT_MASK,
3916 /*256:out */ X86_MXCSR_XCPT_MASK,
3917 /*xcpt? */ false, false },
3918 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } },
3919 { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
3920 { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
3921 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3922 /*128:out */ X86_MXCSR_XCPT_MASK,
3923 /*256:out */ X86_MXCSR_XCPT_MASK,
3924 /*xcpt? */ false, false },
3925 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } },
3926 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_0(0), FP64_0(0) } },
3927 { /* => */ { FP64_1(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
3928 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3929 /*128:out */ X86_MXCSR_XCPT_MASK,
3930 /*256:out */ X86_MXCSR_XCPT_MASK,
3931 /*xcpt? */ false, false },
3932 { { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_NORM_SAFE_INT_MAX(0) } },
3933 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0) } },
3934 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } },
3935 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
3936 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
3937 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
3938 /*xcpt? */ false, false },
3939 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
3940 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },
3941 { /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, 2) } },
3942 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3943 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3944 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3945 /*xcpt? */ false, false },
3946 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } },
3947 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } },
3948 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, 2) } },
3949 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
3950 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
3951 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
3952 /*xcpt? */ false, false },
3953 /*
3954 * Denormals.
3955 */
3956 /*28*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3957 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3958 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3959 /*mxcsr:in */ 0,
3960 /*128:out */ X86_MXCSR_DE,
3961 /*256:out */ X86_MXCSR_DE,
3962 /*xcpt? */ true, true },
3963 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3964 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
3965 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3966 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3967 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3968 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3969 /*xcpt? */ false, false },
3970 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
3971 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
3972 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3973 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3974 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3975 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
3976 /*xcpt? */ false, false },
3977 /** @todo More denormals. */
3978 /*
3979 * Invalids.
3980 */
3981 /*31*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3982 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3983 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3984 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3985 /*128:out */ X86_MXCSR_XCPT_MASK,
3986 /*256:out */ X86_MXCSR_XCPT_MASK,
3987 /*xcpt? */ false, false },
3988 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3989 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0) } },
3990 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3991 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3992 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3993 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3994 /*xcpt? */ false, false },
3995 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3996 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3997 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3998 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3999 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4000 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4001 /*xcpt? */ false, false },
4002 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4003 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
4004 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
4005 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4006 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4007 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4008 /*xcpt? */ false, false },
4009 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4010 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
4011 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4012 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4013 /*128:out */ X86_MXCSR_XCPT_MASK,
4014 /*256:out */ X86_MXCSR_XCPT_MASK,
4015 /*xcpt? */ false, false },
4016 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4017 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
4018 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4019 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4020 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4021 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4022 /*xcpt? */ false, false },
4023 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) , FP64_QNAN_V(0, FP64_FRAC_V1) } },
4024 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4025 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4026 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4027 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4028 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4029 /*xcpt? */ false, false },
4030 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
4031 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
4032 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
4033 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4034 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4035 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4036 /*xcpt? */ true, true },
4037 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4038 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4039 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4040 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4041 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
4042 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
4043 /*xcpt? */ true, true },
4044 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4045 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
4046 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4047 /*mxcsr:in */ X86_MXCSR_RC_UP,
4048 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
4049 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
4050 /*xcpt? */ true, true },
4051 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4052 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
4053 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4054 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
4055 /*128:out */ X86_MXCSR_RC_DOWN,
4056 /*256:out */ X86_MXCSR_RC_DOWN,
4057 /*xcpt? */ false, false },
4058 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4059 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
4060 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4061 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4062 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4063 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4064 /*xcpt? */ true, true },
4065 /** @todo Underflow, Precision; Rounding, FZ etc. */
4066 };
4067
4068 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4069 {
4070 { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4071 { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4072
4073 { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4074 { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4075
4076 { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4077 { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4078 };
4079 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4080 {
4081 { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4082 { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4083
4084 { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4085 { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4086
4087 { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4088 { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4089 };
4090 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4091 {
4092 { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4093 { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4094
4095 { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4096 { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4097
4098 { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4099 { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4100
4101 { bs3CpuInstr4_subpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4102 { bs3CpuInstr4_subpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4103
4104 { bs3CpuInstr4_vsubpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4105 { bs3CpuInstr4_vsubpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4106 };
4107
4108 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4109 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4110 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4111 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4112}
4113
4114
4115/*
4116 * [V]SUBSS.
4117 */
4118BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subss(uint8_t bMode)
4119{
4120 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
4121 {
4122 /*
4123 * Zero.
4124 */
4125 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4126 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4127 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4128 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4129 /*128:out */ X86_MXCSR_XCPT_MASK,
4130 /*256:out */ X86_MXCSR_XCPT_MASK,
4131 /*xcpt? */ false, false },
4132 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4133 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4134 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4135 /*mxcsr:in */ 0,
4136 /*128:out */ 0,
4137 /*256:out */ 0,
4138 /*xcpt? */ false, false },
4139 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4140 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4141 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4142 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4143 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4144 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4145 /*xcpt? */ false, false },
4146 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4147 { /*src1 */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4148 { /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4149 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4150 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4151 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4152 /*xcpt? */ false, false },
4153 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4154 { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4155 { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4156 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4157 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4158 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4159 /*xcpt? */ false, false },
4160 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4161 { /*src1 */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4162 { /* => */ { FP32_0(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4163 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4164 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4165 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4166 /*xcpt? */ false, false },
4167 /*
4168 * Infinity.
4169 */
4170 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4171 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4172 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4173 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4174 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4175 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4176 /*xcpt? */ false, false },
4177 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4178 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4179 { /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4180 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM),
4181 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
4182 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
4183 /*xcpt? */ true, true },
4184 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4185 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4186 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4187 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4188 /*128:out */ X86_MXCSR_XCPT_MASK,
4189 /*256:out */ X86_MXCSR_XCPT_MASK,
4190 /*xcpt? */ false, false },
4191 { { /*src2 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4192 { /*src1 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4193 { /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4194 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4195 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4196 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4197 /*xcpt? */ false, false },
4198 { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4199 { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4200 { /* => */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4201 /*mxcsr:in */ X86_MXCSR_FZ,
4202 /*128:out */ X86_MXCSR_FZ,
4203 /*256:out */ X86_MXCSR_FZ,
4204 /*xcpt? */ false, false },
4205 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
4206 { /*src1 */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
4207 { /* => */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
4208 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4209 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4210 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4211 /*xcpt? */ false, false },
4212 /*
4213 * Overflow, Precision.
4214 */
4215 /*12*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4216 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
4217 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4218 /*mxcsr:in */ 0,
4219 /*128:out */ 0,
4220 /*256:out */ X86_MXCSR_PE,
4221 /*xcpt? */ false, true },
4222 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
4223 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
4224 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0) } },
4225 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
4226 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4227 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4228 /*xcpt? */ false, false },
4229 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
4230 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
4231 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4232 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
4233 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4234 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4235 /*xcpt? */ false, false },
4236 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4237 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4238 { /* => */ { FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4239 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
4240 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4241 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4242 /*xcpt? */ false, false },
4243 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4244 { /*src1 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4245 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4246 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
4247 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
4248 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4249 /*xcpt? */ false, false },
4250 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4251 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4252 { /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4253 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4254 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4255 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4256 /*xcpt? */ false, false },
4257 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4258 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4259 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4260 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4261 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4262 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4263 /*xcpt? */ true, true },
4264 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4265 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4266 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4267 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4268 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4269 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4270 /*xcpt? */ true, true },
4271 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4272 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4273 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4274 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4275 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4276 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4277 /*xcpt? */ true, true },
4278 /*
4279 * Normals.
4280 */
4281 /*21*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4282 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
4283 { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
4284 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4285 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4286 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4287 /*xcpt? */ false, false },
4288 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
4289 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4290 { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4291 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4292 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4293 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4294 /*xcpt? */ false, false },
4295 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4296 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4297 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4298 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4299 /*128:out */ X86_MXCSR_XCPT_MASK,
4300 /*256:out */ X86_MXCSR_XCPT_MASK,
4301 /*xcpt? */ false, false },
4302 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4303 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4304 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4305 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4306 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4307 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4308 /*xcpt? */ false, false },
4309 { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4310 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4311 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4312 /*mxcsr:in */ 0,
4313 /*128:out */ 0,
4314 /*256:out */ 0,
4315 /*xcpt? */ false, false },
4316 { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4317 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4318 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4319 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4320 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4321 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4322 /*xcpt? */ false, false },
4323 { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4324 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4325 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4326 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4327 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4328 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4329 /*xcpt? */ false, false },
4330 { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4331 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4332 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4333 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4334 /*128:out */ X86_MXCSR_XCPT_MASK,
4335 /*256:out */ X86_MXCSR_XCPT_MASK,
4336 /*xcpt? */ false, false },
4337 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
4338 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4339 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4340 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
4341 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
4342 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
4343 /*xcpt? */ false, false },
4344 /*
4345 * Denormals.
4346 */
4347 /*27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
4348 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
4349 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
4350 /*mxcsr:in */ 0,
4351 /*128:out */ X86_MXCSR_DE,
4352 /*256:out */ X86_MXCSR_DE,
4353 /*xcpt? */ true, true },
4354 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
4355 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4356 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
4357 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
4358 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
4359 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
4360 /*xcpt? */ false, false },
4361 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
4362 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
4363 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
4364 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4365 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4366 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4367 /*xcpt? */ false, false },
4368 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
4369 };
4370
4371 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4372 {
4373 { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4374 { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4375
4376 { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4377 { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4378 };
4379 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4380 {
4381 { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4382 { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4383
4384 { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4385 { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4386 };
4387 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4388 {
4389 { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4390 { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4391
4392 { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4393 { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4394
4395 { bs3CpuInstr4_subss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4396 { bs3CpuInstr4_subss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4397 };
4398
4399 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4400 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4401 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4402 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
4403}
4404
4405
4406/*
4407 * [V]MULPS.
4408 */
4409BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulps(uint8_t bMode)
4410{
4411 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
4412 {
4413 /*
4414 * Zero.
4415 */
4416 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4417 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4418 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4419 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4420 /*128:out */ X86_MXCSR_XCPT_MASK,
4421 /*256:out */ X86_MXCSR_XCPT_MASK,
4422 /*xcpt? */ false, false },
4423 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4424 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4425 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4426 /*mxcsr:in */ 0,
4427 /*128:out */ 0,
4428 /*256:out */ 0,
4429 /*xcpt? */ false, false },
4430 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4431 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4432 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4433 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4434 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4435 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4436 /*xcpt? */ false, false },
4437 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4438 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4439 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4440 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4441 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4442 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4443 /*xcpt? */ false, false },
4444 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
4445 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
4446 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4447 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4448 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4449 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4450 /*xcpt? */ false, false },
4451 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
4452 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } },
4453 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } },
4454 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4455 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4456 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4457 /*xcpt? */ false, false },
4458 { { /*src2 */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } },
4459 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_NORM_V2(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
4460 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4461 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4462 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4463 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4464 /*xcpt? */ false, false },
4465 /*
4466 * Infinity.
4467 */
4468 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4469 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4470 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4471 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4472 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4473 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4474 /*xcpt? */ false, false },
4475 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4476 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4477 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4478 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4479 /*128:out */ X86_MXCSR_XCPT_MASK,
4480 /*256:out */ X86_MXCSR_XCPT_MASK,
4481 /*xcpt? */ false, false },
4482 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
4483 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
4484 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
4485 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
4486 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
4487 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
4488 /*xcpt? */ false, false },
4489 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
4490 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4491 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4492 /*mxcsr:in */ X86_MXCSR_FZ,
4493 /*128:out */ X86_MXCSR_FZ,
4494 /*256:out */ X86_MXCSR_FZ,
4495 /*xcpt? */ false, false },
4496 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
4497 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
4498 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
4499 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4500 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4501 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4502 /*xcpt? */ false, false },
4503#if 0
4504 /*
4505 * Normals.
4506 */
4507 /*12*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.250*/, FP32_V(0, 0x600000, 0x7f)/* 1.7500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.250*/ } },
4508 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.500*/, FP32_V(1, 0, 0x7d)/*-0.2500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.500*/ } },
4509 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/*0.125*/, FP32_V(1, 0x600000, 0x7d)/*-0.4375*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/*0.125*/ } },
4510 /*mask */ X86_MXCSR_XCPT_MASK,
4511 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4512 /*flags */ 0, 0 },
4513 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
4514 { /*src1 */ { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
4515 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(1), FP32_NORM_V3(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
4516 /*mask */ ~X86_MXCSR_XCPT_MASK,
4517 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4518 /*flags */ 0, 0 },
4519 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_V(0, 0x0ba000, 0x86)/* 139.625000*/, FP32_V(0, 0x200000, 0x7e)/*0.625000*/, FP32_V(0, 0x22fae4, 0x93)/*1335132.50*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x3d400, 0x86)/*131.828125*/ } },
4520 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_V(0, 0x265000, 0x87)/* 332.625000*/, FP32_V(0, 0, 0x7c)/*0.125000*/, FP32_V(0, 0x200000, 0x80)/* 2.50*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_1(1) /* -1.000000*/ } },
4521 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x356ac4, 0x8e)/*46442.765625*/, FP32_V(0, 0x200000, 0x7b)/*0.078125*/, FP32_V(0, 0x4bb99d, 0x94)/*3337831.25*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(1, 0x3d400, 0x86)/*-131.828125*/ } },
4522 /*mask */ X86_MXCSR_XCPT_MASK,
4523 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4524 /*flags */ 0, 0 },
4525 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
4526 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0) } },
4527 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(0) } },
4528 /*mask */ X86_MXCSR_XCPT_MASK,
4529 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4530 /*flags */ 0, 0 },
4531 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } },
4532 { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_1(0) } },
4533 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2) } },
4534 /*mask */ X86_MXCSR_XCPT_MASK,
4535 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4536 /*flags */ 0, 0 },
4537 /** @todo More Normals. */
4538 /*
4539 * Denormals.
4540 */
4541 /*17*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
4542 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
4543 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
4544 /*mask */ ~X86_MXCSR_XCPT_MASK,
4545 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4546 /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
4547 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
4548 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } },
4549 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
4550 /*mask */ ~X86_MXCSR_XCPT_MASK,
4551 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4552 /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
4553 { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } },
4554 { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
4555 { /* => */ { FP32_0(1), FP32_0(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4556 /*mask */ X86_MXCSR_XCPT_MASK,
4557 /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
4558 /*flags */ 0, 0 },
4559 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V4(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } },
4560 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
4561 { /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_0(0), FP32_0(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_0(0), FP32_0(0) } },
4562 /*mask */ X86_MXCSR_XCPT_MASK,
4563 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
4564 /*flags */ 0, 0 },
4565 /** @todo More Denormals. */
4566 /*
4567 * Overflow, Precision.
4568 */
4569 /*21*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V7(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4570 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4571 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_NORM_V7(0), FP32_INF(0), FP32_INF(0) } },
4572 /*mask */ X86_MXCSR_XCPT_MASK,
4573 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4574 /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
4575 { { /*src2 */ { FP32_NORM_V5(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_1(0), FP32_0(0) } },
4576 { /*src1 */ { FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } },
4577 { /* => */ { FP32_NORM_V5(0), FP32_INF(0), FP32_INF(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } },
4578 /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
4579 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4580 /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
4581 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_V7(0), FP32_NORM_MAX(0) } },
4582 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(0) } },
4583 { /* => */ { FP32_INF(0), FP32_0(0), FP32_1(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_NORM_V7(0), FP32_INF(0) } },
4584 /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
4585 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
4586 /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
4587 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_V5(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
4588 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0) } },
4589 { /* => */ { FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_V5(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0) } },
4590 /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
4591 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4592 /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
4593 { { /*src2 */ { FP32_NORM_V6(0), FP32_1(1), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4594 { /*src1 */ { FP32_1(0), FP32_NORM_V6(1), FP32_1(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
4595 { /* => */ { FP32_NORM_V6(0), FP32_NORM_V6(0), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
4596 /*mask */ X86_MXCSR_XCPT_MASK,
4597 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
4598 /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
4599 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
4600 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
4601 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4602 /*mask */ ~X86_MXCSR_XCPT_MASK,
4603 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
4604 /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
4605 /** @todo More Overflow, Precision. */
4606 /*
4607 * Invalids.
4608 */
4609 /*27*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4610 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4611 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4612 /*mask */ X86_MXCSR_XCPT_MASK,
4613 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4614 /*flags */ 0, 0 },
4615 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4616 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4617 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4618 /*mask */ X86_MXCSR_XCPT_MASK,
4619 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4620 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4621 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
4622 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4623 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4624 /*mask */ X86_MXCSR_XCPT_MASK,
4625 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4626 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4627 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4628 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
4629 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
4630 /*mask */ X86_MXCSR_XCPT_MASK,
4631 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4632 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4633 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4634 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4635 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4636 /*mask */ X86_MXCSR_XCPT_MASK,
4637 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4638 /*flags */ 0, 0 },
4639 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
4640 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4641 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4642 /*mask */ X86_MXCSR_XCPT_MASK,
4643 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
4644 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4645 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4646 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4647 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4648 /*mask */ ~X86_MXCSR_XCPT_MASK,
4649 /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
4650 /*flags */ 0, 0 },
4651 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4652 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4653 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4654 /*mask */ ~X86_MXCSR_XCPT_MASK,
4655 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4656 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4657 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
4658 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4659 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4660 /*mask */ ~X86_MXCSR_XCPT_MASK,
4661 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
4662 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4663 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4664 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
4665 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
4666 /*mask */ ~X86_MXCSR_XCPT_MASK,
4667 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_UP,
4668 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4669 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4670 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4671 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4672 /*mask */ ~X86_MXCSR_XCPT_MASK,
4673 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_DOWN,
4674 /*flags */ 0, 0 },
4675 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
4676 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4677 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4678 /*mask */ ~X86_MXCSR_XCPT_MASK,
4679 /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
4680 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
4681 /** @todo Underflow, Precision; Rounding, FZ etc. */
4682#endif
4683 };
4684
4685 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4686 {
4687 { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4688 { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4689
4690 { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4691 { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4692
4693 { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4694 { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4695 };
4696 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4697 {
4698 { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4699 { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4700
4701 { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4702 { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4703
4704 { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4705 { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4706 };
4707 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4708 {
4709 { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4710 { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4711
4712 { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4713 { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4714
4715 { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4716 { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4717
4718 { bs3CpuInstr4_mulps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4719 { bs3CpuInstr4_mulps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4720
4721 { bs3CpuInstr4_vmulps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4722 { bs3CpuInstr4_vmulps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4723 };
4724
4725 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4726 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4727 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4728 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4729}
4730
4731
4732/*
4733 * [V]MULPD.
4734 */
4735BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulpd(uint8_t bMode)
4736{
4737 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
4738 {
4739 /*
4740 * Zero.
4741 */
4742 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4743 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4744 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4745 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4746 /*128:out */ X86_MXCSR_XCPT_MASK,
4747 /*256:out */ X86_MXCSR_XCPT_MASK,
4748 /*xcpt? */ false, false },
4749 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4750 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4751 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4752 /*mxcsr:in */ 0,
4753 /*128:out */ 0,
4754 /*256:out */ 0,
4755 /*xcpt? */ false, false },
4756 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4757 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4758 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4759 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4760 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4761 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4762 /*xcpt? */ false, false },
4763 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
4764 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
4765 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4766 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4767 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4768 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4769 /*xcpt? */ false, false },
4770 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
4771 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
4772 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4773 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4774 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4775 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4776 /*xcpt? */ false, false },
4777 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
4778 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
4779 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
4780 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4781 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4782 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4783 /*xcpt? */ false, false },
4784 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } },
4785 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } },
4786 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
4787 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4788 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4789 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4790 /*xcpt? */ false, false },
4791 /*
4792 * Infinity.
4793 */
4794 /* 7*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(1), FP64_0(0) } },
4795 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } },
4796 { /* => */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } },
4797 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4798 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4799 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4800 /*xcpt? */ false, false },
4801 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
4802 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
4803 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
4804 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4805 /*128:out */ X86_MXCSR_XCPT_MASK,
4806 /*256:out */ X86_MXCSR_XCPT_MASK,
4807 /*xcpt? */ false, false },
4808 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
4809 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
4810 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
4811 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4812 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4813 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4814 /*xcpt? */ false, false },
4815 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
4816 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
4817 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
4818 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4819 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4820 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4821 /*xcpt? */ false, false },
4822 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(0), FP64_INF(0) } },
4823 { /*src1 */ { FP64_1(0), FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } },
4824 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
4825 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4826 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4827 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4828 /*xcpt? */ false, false },
4829 { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_NORM_V3(0), FP64_INF(1) } },
4830 { /*src1 */ { FP64_1(1), FP64_NORM_V3(1), FP64_INF(1), FP64_NORM_V1(1) } },
4831 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
4832 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4833 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4834 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4835 /*xcpt? */ false, false },
4836 /*
4837 * Normals.
4838 */
4839 /*13*/{ { /*src2 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/ } },
4840 { /*src1 */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } },
4841 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } },
4842 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4843 /*128:out */ X86_MXCSR_XCPT_MASK,
4844 /*256:out */ X86_MXCSR_XCPT_MASK,
4845 /*xcpt? */ false, false },
4846 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } },
4847 { /*src1 */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } },
4848 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } },
4849 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4850 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4851 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4852 /*xcpt? */ false, false },
4853 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } },
4854 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } },
4855 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } },
4856 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4857 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4858 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4859 /*xcpt? */ false, false },
4860 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } },
4861 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } },
4862 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
4863 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4864 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4865 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4866 /*xcpt? */ false, false },
4867 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
4868 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } },
4869 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } },
4870 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4871 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4872 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4873 /*xcpt? */ false, false },
4874 /** @todo More Normals. */
4875 /*
4876 * Denormals.
4877 */
4878 /*18*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
4879 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } },
4880 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4881 /*mxcsr:in */ 0,
4882 /*128:out */ X86_MXCSR_DE,
4883 /*256:out */ X86_MXCSR_DE,
4884 /*xcpt? */ true, true },
4885 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
4886 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0) } },
4887 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4888 /*mxcsr:in */ X86_MXCSR_FZ,
4889 /*128:out */ X86_MXCSR_FZ,
4890 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,
4891 /*xcpt? */ false, true },
4892 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
4893 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0) } },
4894 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4895 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
4896 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
4897 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
4898 /*xcpt? */ false, false },
4899 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0), FP64_1(0) } },
4900 { /*src1 */ { FP64_1(0), FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0) } },
4901 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4902 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
4903 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
4904 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
4905 /*xcpt? */ false, false },
4906 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
4907 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(1), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
4908 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
4909 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4910 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4911 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4912 /*xcpt? */ false, false },
4913 { { /*src2 */ { FP64_1(0), FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
4914 { /*src1 */ { FP64_NORM_V0(0), FP64_1(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
4915 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } },
4916 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4917 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4918 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE,
4919 /*xcpt? */ false, false },
4920 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
4921 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
4922 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } },
4923 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4924 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
4925 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
4926 /*xcpt? */ true, true },
4927 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
4928 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
4929 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
4930 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4931 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
4932 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
4933 /*xcpt? */ true, true },
4934 /*
4935 * Overflow, Precision.
4936 */
4937 /*26*/{ { /*src2 */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
4938 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_NORM_MAX(0) } },
4939 { /* => */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0) } },
4940 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4941 /*128:out */ X86_MXCSR_XCPT_MASK,
4942 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
4943 /*xcpt? */ false, false },
4944 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } },
4945 { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_1(0), FP64_1(0) } },
4946 { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_NORM_V3(1), FP64_1(0) } },
4947 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4948 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
4949 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
4950 /*xcpt? */ false, false },
4951 { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0) } },
4952 { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
4953 { /* => */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } },
4954 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4955 /*128:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4956 /*256:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4957 /*xcpt? */ false, false },
4958 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } },
4959 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
4960 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0) } },
4961 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
4962 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
4963 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
4964 /*xcpt? */ false, false },
4965 { { /*src2 */ { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
4966 { /*src1 */ { FP64_1(0), FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
4967 { /* => */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } },
4968 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO,
4969 /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO,
4970 /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4971 /*xcpt? */ false, false },
4972 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } },
4973 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } },
4974 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
4975 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4976 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4977 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4978 /*xcpt? */ false, false },
4979 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } },
4980 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } },
4981 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
4982 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4983 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
4984 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
4985 /*xcpt? */ false, false },
4986 /*
4987 * Invalids.
4988 */
4989 /*33*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4990 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4991 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4992 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4993 /*128:out */ X86_MXCSR_XCPT_MASK,
4994 /*256:out */ X86_MXCSR_XCPT_MASK,
4995 /*xcpt? */ false, false },
4996 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4997 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4998 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4999 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5000 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5001 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5002 /*xcpt? */ false, false },
5003 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5004 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5005 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5006 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5007 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5008 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5009 /*xcpt? */ false, false },
5010 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5011 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
5012 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
5013 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5014 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5015 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5016 /*xcpt? */ false, false },
5017 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5018 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5019 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5020 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5021 /*128:out */ X86_MXCSR_XCPT_MASK,
5022 /*256:out */ X86_MXCSR_XCPT_MASK,
5023 /*xcpt? */ false, false },
5024 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5025 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5026 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5027 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5028 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5029 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5030 /*xcpt? */ false, false },
5031 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5032 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5033 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5034 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5035 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5036 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5037 /*xcpt? */ false, false },
5038 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
5039 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
5040 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
5041 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5042 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5043 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5044 /*xcpt? */ true, true },
5045 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5046 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5047 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5048 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5049 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5050 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5051 /*xcpt? */ true, true },
5052 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5053 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5054 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5055 /*mxcsr:in */ X86_MXCSR_RC_UP,
5056 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
5057 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
5058 /*xcpt? */ true, true },
5059 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5060 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
5061 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5062 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
5063 /*128:out */ X86_MXCSR_RC_DOWN,
5064 /*256:out */ X86_MXCSR_RC_DOWN,
5065 /*xcpt? */ false, false },
5066 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5067 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
5068 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5069 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5070 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5071 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5072 /*xcpt? */ true, true },
5073 /** @todo Underflow, Precision; Rounding, FZ etc. */
5074 };
5075
5076 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
5077 {
5078 { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5079 { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5080
5081 { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5082 { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5083
5084 { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5085 { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5086 };
5087 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
5088 {
5089 { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5090 { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5091
5092 { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5093 { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5094
5095 { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5096 { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5097 };
5098 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
5099 {
5100 { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5101 { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5102
5103 { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5104 { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5105
5106 { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5107 { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5108
5109 { bs3CpuInstr4_mulpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5110 { bs3CpuInstr4_mulpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5111
5112 { bs3CpuInstr4_vmulpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5113 { bs3CpuInstr4_vmulpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5114 };
5115
5116 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5117 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
5118 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5119 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
5120}
5121
5122
5123/*
5124 * [V]MULSS.
5125 */
5126BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulss(uint8_t bMode)
5127{
5128 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
5129 {
5130 /*
5131 * Zero.
5132 */
5133 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5134 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5135 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5136 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5137 /*128:out */ X86_MXCSR_XCPT_MASK,
5138 /*256:out */ X86_MXCSR_XCPT_MASK,
5139 /*xcpt? */ false, false },
5140 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5141 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5142 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5143 /*mxcsr:in */ 0,
5144 /*128:out */ 0,
5145 /*256:out */ 0,
5146 /*xcpt? */ false, false },
5147 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5148 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5149 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5150 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5151 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5152 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5153 /*xcpt? */ false, false },
5154 { { /*src2 */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0) } },
5155 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } },
5156 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } },
5157 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5158 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5159 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5160 /*xcpt? */ false, false },
5161 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5162 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5163 { /* => */ { FP32_0(0), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5164 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5165 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5166 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5167 /*xcpt? */ false, false },
5168 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5169 { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
5170 { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
5171 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5172 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5173 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5174 /*xcpt? */ false, false },
5175 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5176 { /*src1 */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
5177 { /* => */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
5178 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
5179 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
5180 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
5181 /*xcpt? */ false, false },
5182 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5183 { /*src1 */ { FP32_1(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
5184 { /* => */ { FP32_0(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
5185 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5186 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5187 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5188 /*xcpt? */ false, false },
5189 /*
5190 * Infinity.
5191 */
5192 /* 8*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5193 { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5194 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5195 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
5196 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
5197 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
5198 /*xcpt? */ false, false },
5199 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5200 { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5201 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5202 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5203 /*128:out */ X86_MXCSR_XCPT_MASK,
5204 /*256:out */ X86_MXCSR_XCPT_MASK,
5205 /*xcpt? */ false, false },
5206 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5207 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5208 { /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5209 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
5210 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
5211 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
5212 /*xcpt? */ false, false },
5213 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5214 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5215 { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5216 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5217 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5218 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5219 /*xcpt? */ false, false },
5220 { { /*src2 */ { FP32_1(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5221 { /*src1 */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
5222 { /* => */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
5223 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
5224 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
5225 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
5226 /*xcpt? */ false, false },
5227 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },
5228 { /*src1 */ { FP32_1(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
5229 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
5230 /*mxcsr:in */ X86_MXCSR_FZ,
5231 /*128:out */ X86_MXCSR_FZ,
5232 /*256:out */ X86_MXCSR_FZ,
5233 /*xcpt? */ false, false },
5234 { { /*src2 */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
5235 { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
5236 { /* => */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
5237 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5238 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5239 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5240 /*xcpt? */ false, false },
5241 /*
5242 * Normals.
5243 */
5244 /*15*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5245 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
5246 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
5247 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5248 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5249 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5250 /*xcpt? */ false, false },
5251 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5252 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5253 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5254 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5255 /*128:out */ X86_MXCSR_XCPT_MASK,
5256 /*256:out */ X86_MXCSR_XCPT_MASK,
5257 /*xcpt? */ false, false },
5258 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5259 { /*src1 */ { FP32_1(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5260 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5261 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5262 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5263 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5264 /*xcpt? */ false, false },
5265 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5266 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
5267 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
5268 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5269 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5270 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5271 /*xcpt? */ false, false },
5272 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
5273 { /*src1 */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
5274 { /* => */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
5275 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5276 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5277 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5278 /*xcpt? */ false, false },
5279 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } },
5280 { /*src1 */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V6(0), FP32_RAND_V1(1) } },
5281 { /* => */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V1(1) } },
5282 /*mxcsr:in */ 0,
5283 /*128:out */ 0,
5284 /*256:out */ 0,
5285 /*xcpt? */ false, false },
5286 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
5287 { /*src1 */ { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
5288 { /* => */ { FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
5289 /*mxcsr:in */ 0,
5290 /*128:out */ 0,
5291 /*256:out */ 0,
5292 /*xcpt? */ false, false },
5293 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
5294 { /*src1 */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
5295 { /* => */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
5296 /*mxcsr:in */ 0,
5297 /*128:out */ 0,
5298 /*256:out */ 0,
5299 /*xcpt? */ false, false },
5300 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
5301 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } },
5302 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } },
5303 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5304 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5305 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5306 /*xcpt? */ false, false },
5307 /** @todo More Normals. */
5308 /*
5309 * Denormals.
5310 */
5311 /*24*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
5312 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
5313 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
5314 /*mxcsr:in */ 0,
5315 /*128:out */ X86_MXCSR_DE,
5316 /*256:out */ X86_MXCSR_DE,
5317 /*xcpt? */ true, true },
5318 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
5319 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
5320 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
5321 /*mxcsr:in */ 0,
5322 /*128:out */ X86_MXCSR_DE,
5323 /*256:out */ X86_MXCSR_DE,
5324 /*xcpt? */ true, true },
5325 { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } },
5326 { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
5327 { /* => */ { FP32_0(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
5328 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5329 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
5330 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
5331 /*xcpt? */ false, false },
5332 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } },
5333 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
5334 { /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
5335 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5336 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5337 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5338 /*xcpt? */ false, false },
5339 /** @todo More Denormals. */
5340 /*
5341 * Invalids.
5342 */
5343 /* QNan, QNan (Masked). */
5344 /*28*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5345 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5346 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5347 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5348 /*128:out */ X86_MXCSR_XCPT_MASK,
5349 /*256:out */ X86_MXCSR_XCPT_MASK,
5350 /*xcpt? */ false, false },
5351 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5352 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5353 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5354 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5355 /*128:out */ X86_MXCSR_XCPT_MASK,
5356 /*256:out */ X86_MXCSR_XCPT_MASK,
5357 /*xcpt? */ false, false },
5358 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5359 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5360 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5361 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5362 /*128:out */ X86_MXCSR_XCPT_MASK,
5363 /*256:out */ X86_MXCSR_XCPT_MASK,
5364 /*xcpt? */ false, false },
5365 /* QNan, SNan (Masked). */
5366 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5367 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5368 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5369 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5370 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5371 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5372 /*xcpt? */ false, false },
5373 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5374 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5375 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5376 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5377 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5378 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5379 /*xcpt? */ false, false },
5380 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5381 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5382 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5383 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5384 /*128:out */ X86_MXCSR_XCPT_MASK,
5385 /*256:out */ X86_MXCSR_XCPT_MASK,
5386 /*xcpt? */ false, false },
5387 /* SNan, QNan (Masked). */
5388 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5389 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5390 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5391 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5392 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5393 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5394 /*xcpt? */ false, false },
5395 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5396 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5397 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5398 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5399 /*128:out */ X86_MXCSR_XCPT_MASK,
5400 /*256:out */ X86_MXCSR_XCPT_MASK,
5401 /*xcpt? */ false, false },
5402 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5403 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5404 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5405 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5406 /*128:out */ X86_MXCSR_XCPT_MASK,
5407 /*256:out */ X86_MXCSR_XCPT_MASK,
5408 /*xcpt? */ false, false },
5409 /* SNan, SNan (Masked). */
5410 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5411 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5412 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5413 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5414 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5415 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5416 /*xcpt? */ false, false },
5417 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5418 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5419 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5420 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5421 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5422 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5423 /*xcpt? */ false, false },
5424 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5425 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5426 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5427 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5428 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5429 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5430 /*xcpt? */ false, false },
5431 /* QNan, Norm FP (Masked). */
5432 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5433 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5434 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5435 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5436 /*128:out */ X86_MXCSR_XCPT_MASK,
5437 /*256:out */ X86_MXCSR_XCPT_MASK,
5438 /*xcpt? */ false, false },
5439 /* SNan, Norm FP (Masked). */
5440 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
5441 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5442 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5443 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5444 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5445 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5446 /*xcpt? */ false, false },
5447 /* QNan, QNan (Unmasked). */
5448 /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5449 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5450 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5451 /*mxcsr:in */ 0,
5452 /*128:out */ 0,
5453 /*256:out */ 0,
5454 /*xcpt? */ false, false },
5455 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5456 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5457 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5458 /*mxcsr:in */ 0,
5459 /*128:out */ 0,
5460 /*256:out */ 0,
5461 /*xcpt? */ false, false },
5462 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5463 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5464 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5465 /*mxcsr:in */ 0,
5466 /*128:out */ 0,
5467 /*256:out */ 0,
5468 /*xcpt? */ false, false },
5469
5470 /* QNan, SNan (Unmasked). */
5471 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5472 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5473 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5474 /*mxcsr:in */ 0,
5475 /*128:out */ X86_MXCSR_IE,
5476 /*256:out */ X86_MXCSR_IE,
5477 /*xcpt? */ true, true },
5478 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5479 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5480 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5481 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5482 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
5483 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
5484 /*xcpt? */ true, true },
5485 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5486 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5487 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5488 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5489 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5490 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5491 /*xcpt? */ false, false },
5492 /* SNan, QNan (Unmasked). */
5493 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5494 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5495 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5496 /*mxcsr:in */ X86_MXCSR_DAZ,
5497 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
5498 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
5499 /*xcpt? */ true, true },
5500 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5501 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5502 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5503 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
5504 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
5505 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
5506 /*xcpt? */ false, false },
5507 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5508 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5509 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5510 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5511 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5512 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5513 /*xcpt? */ false, false },
5514 /* SNan, SNan (Unmasked). */
5515 /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5516 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5517 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5518 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
5519 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
5520 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
5521 /*xcpt? */ true, true },
5522 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5523 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5524 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5525 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
5526 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5527 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5528 /*xcpt? */ true, true },
5529 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5530 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5531 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
5532 /*mxcsr:in */ X86_MXCSR_FZ,
5533 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
5534 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
5535 /*xcpt? */ true, true },
5536 /* QNan, Norm FP (Unmasked). */
5537 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5538 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5539 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5540 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5541 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5542 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5543 /*xcpt? */ false, false },
5544 /* SNan, Norm FP (Unmasked). */
5545 /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
5546 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5547 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5548 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5549 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5550 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5551 /*xcpt? */ true, true },
5552 /** @todo Underflow, Precision; Rounding, FZ etc. */
5553 };
5554
5555 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
5556 {
5557 { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5558 { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5559
5560 { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5561 { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5562 };
5563 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
5564 {
5565 { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5566 { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5567
5568 { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5569 { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5570 };
5571 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
5572 {
5573 { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5574 { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5575
5576 { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5577 { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5578
5579 { bs3CpuInstr4_mulss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5580 { bs3CpuInstr4_mulss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5581 };
5582
5583 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5584 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
5585 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5586 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
5587}
5588
5589
5590/**
5591 * The 32-bit protected mode main function.
5592 *
5593 * The tests a driven by 32-bit test drivers, even for real-mode tests (though
5594 * we'll switch between PE32 and RM for each test step we perform). Given that
5595 * we test SSE and AVX here, we don't need to worry about 286 or 8086.
5596 *
5597 * Some extra steps needs to be taken to properly handle extended state in LM64
5598 * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode
5599 * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm).
5600 */
5601BS3_DECL(void) Main_pe32()
5602{
5603 static const BS3TESTMODEBYONEENTRY g_aTests[] =
5604 {
5605#if 1 /*ndef DEBUG_bird*/
5606# define ALL_TESTS
5607#endif
5608#if defined(ALL_TESTS)
5609 { "[v]addps", bs3CpuInstr4_v_addps, 0 },
5610 { "[v]addpd", bs3CpuInstr4_v_addpd, 0 },
5611 { "[v]addss", bs3CpuInstr4_v_addss, 0 },
5612 { "[v]addsd", bs3CpuInstr4_v_addsd, 0 },
5613 { "[v]haddps", bs3CpuInstr4_v_haddps, 0 },
5614 { "[v]subps", bs3CpuInstr4_v_subps, 0 },
5615 { "[v]subpd", bs3CpuInstr4_v_subpd, 0 },
5616 { "[v]subss", bs3CpuInstr4_v_subss, 0 },
5617 { "[v]mulps", bs3CpuInstr4_v_mulps, 0 },
5618 { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 },
5619 { "[v]mulss", bs3CpuInstr4_v_mulss, 0 },
5620#endif
5621 };
5622 Bs3TestInit("bs3-cpu-instr-4");
5623
5624 /*
5625 * Initialize globals.
5626 */
5627 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
5628 {
5629 uint32_t fEbx, fEcx, fEdx;
5630 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
5631 g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX);
5632 g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
5633 g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
5634 g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3);
5635 g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
5636 g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
5637 g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3);
5638 g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3);
5639 g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
5640 g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
5641 g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
5642 g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
5643 g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
5644 g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL)
5645 && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
5646
5647 if (ASMCpuId_EAX(0) >= 7)
5648 {
5649 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL);
5650 g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
5651 g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
5652 g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA);
5653 }
5654
5655 if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES)
5656 {
5657 ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
5658 g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5659 g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5660 g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5661 }
5662 g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE];
5663
5664 /*
5665 * Figure out FPU save/restore method and support for DAZ bit.
5666 */
5667 {
5668 /** @todo Add bs3kit API to just get the ext ctx method without needing to
5669 * alloc/free a context. Replicating the logic in the bs3kit here, though
5670 * doable, runs a risk of not updating this when the other logic is
5671 * changed. */
5672 uint64_t fFlags;
5673 uint16_t const cbExtCtx = Bs3ExtCtxGetSize(&fFlags);
5674 PBS3EXTCTX pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cbExtCtx);
5675 if (pExtCtx)
5676 {
5677 Bs3ExtCtxInit(pExtCtx, cbExtCtx, fFlags);
5678 g_enmExtCtxMethod = pExtCtx->enmMethod;
5679 if ( ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_XSAVE
5680 && (pExtCtx->Ctx.x.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
5681 || ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_FXSAVE)
5682 && (pExtCtx->Ctx.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
5683 g_fMxCsrDazSupported = true;
5684 }
5685 else
5686 Bs3TestFailedF("Failed to allocate %u bytes for extended CPU context (tiled addressable)\n", cbExtCtx);
5687 }
5688
5689 /*
5690 * Allocate a buffer for testing.
5691 */
5692 g_cbBuf = X86_PAGE_SIZE * 4;
5693 g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf);
5694 if (g_pbBuf)
5695 {
5696 g_pbBufAliasAlloc = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_TILED, g_cbBuf);
5697 if (g_pbBufAliasAlloc)
5698 {
5699 /*
5700 * Do the tests.
5701 */
5702 Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY);
5703#ifdef BS3_SKIPIT_DO_SKIP
5704 bs3CpuInstrX_ShowTallies();
5705#endif
5706 }
5707 else
5708 Bs3TestFailed("Failed to allocate 16K alias buffer (tiled addressable)");
5709 }
5710 else
5711 Bs3TestFailed("Failed to allocate 16K buffer (real mode addressable)");
5712 }
5713
5714 Bs3TestTerm();
5715}
5716
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