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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32@ 105722

Last change on this file since 105722 was 105722, checked in by vboxsync, 4 months ago

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]mulsd.
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1/* $Id: bs3-cpu-instr-4.c32 105722 2024-08-19 11:39:56Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-instr-4 - SSE, AVX FPU instructions, C code template.
4 */
5
6/*
7 * Copyright (C) 2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
41#include <bs3kit.h>
42#include "bs3-cpu-instr-4-asm-auto.h"
43
44#include <iprt/asm.h>
45#include <iprt/asm-amd64-x86.h>
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51/** Converts an execution mode (BS3_MODE_XXX) into an index into an array
52 * initialized by BS3CPUINSTR4_TEST1_MODES_INIT etc. */
53#define BS3CPUINSTR4_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2)
54
55/** Maximum length for the names of all SIMD FP exception flags combined. */
56#define FP_XCPT_FLAGS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
57/** Maximum length for the names of all SIMD FP exception masks combined. */
58#define FP_XCPT_MASKS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ")
59/** Maximum length for the names of all SIMD FP exception other bits combined. */
60#define FP_XCPT_OTHERS_NAMES_MAXLEN sizeof(" DAZ FZ MM RC=NEAREST ")
61
62/*
63 * Single-precision (32 bits) floating-point defines.
64 */
65/** The max exponent value for a single-precision floating-point normal. */
66#define FP32_EXP_NORM_MAX 254
67/** The min exponent value for a single-precision floating-point normal. */
68#define FP32_EXP_NORM_MIN 1
69/** The max fraction value for a single-precision floating-point normal. */
70#define FP32_FRAC_NORM_MAX 0x7fffff
71/** The min fraction value for a single-precision floating-point normal. */
72#define FP32_FRAC_NORM_MIN 0
73/** The exponent bias for the single-precision floating-point format. */
74#define FP32_EXP_BIAS RTFLOAT32U_EXP_BIAS
75/** Fraction width (in bits) for the single-precision floating-point format. */
76#define FP32_FRAC_BITS RTFLOAT32U_FRACTION_BITS
77/** The max exponent value for a single-precision floating-point integer without
78 * losing precision. */
79#define FP32_EXP_SAFE_INT_MAX FP32_EXP_BIAS + FP32_FRAC_BITS
80/** The min exponent value for a single-precision floating-point integer without
81 * losing precision. */
82#define FP32_EXP_SAFE_INT_MIN 1
83/** The max fraction value for a double-precision floating-point denormal. */
84#define FP32_FRAC_DENORM_MAX 0x7fffff
85/** The min fraction value for a double-precision floating-point denormal. */
86#define FP32_FRAC_DENORM_MIN 1
87
88#define FP32_NORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_NORM_MAX)
89#define FP32_NORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN)
90#define FP32_0(a_Sign) RTFLOAT32U_INIT_ZERO(a_Sign)
91#define FP32_1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0, RTFLOAT32U_EXP_BIAS)
92#define FP32_V(a_Sign, a_Frac, a_Exp) RTFLOAT32U_INIT_C(a_Sign, a_Frac, a_Exp)
93#define FP32_INF(a_Sign) RTFLOAT32U_INIT_INF(a_Sign)
94#define FP32_QNAN(a_Sign) RTFLOAT32U_INIT_QNAN(a_Sign)
95#define FP32_QNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val)
96#define FP32_SNAN(a_Sign) RTFLOAT32U_INIT_SNAN(a_Sign)
97#define FP32_SNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_SNAN_EX(a_Sign, a_Val)
98
99/*
100 * Single-precision floating normals.
101 * Fraction - 23 bits, all usable.
102 * Exponent - 8 bits, least significant bit MBZ.
103 */
104#define FP32_FRAC_V0 0x401ac0
105#define FP32_FRAC_V1 0x5fcabd
106#define FP32_FRAC_V2 0x7e117a
107#define FP32_FRAC_V3 0x5b5b5b
108#define FP32_FRAC_V4 0x1e0f1f
109#define FP32_FRAC_V5 0x012345
110#define FP32_FRAC_V6 0x330b3b
111#define FP32_FRAC_V7 0x4ebeb4
112#define FP32_EXP_V0 0x78
113#define FP32_EXP_V1 0xbc
114#define FP32_EXP_V2 0x7e
115#define FP32_EXP_V3 0x9a
116#define FP32_EXP_V4 0x32
117#define FP32_EXP_V5 0x56
118#define FP32_EXP_V6 0x90
119#define FP32_EXP_V7 0x30
120AssertCompile(!(FP32_EXP_V0 & RT_BIT(0)));
121AssertCompile(!(FP32_EXP_V1 & RT_BIT(0)));
122AssertCompile(!(FP32_EXP_V2 & RT_BIT(0)));
123AssertCompile(!(FP32_EXP_V3 & RT_BIT(0)));
124AssertCompile(!(FP32_EXP_V4 & RT_BIT(0)));
125AssertCompile(!(FP32_EXP_V5 & RT_BIT(0)));
126AssertCompile(!(FP32_EXP_V6 & RT_BIT(0)));
127AssertCompile(!(FP32_EXP_V7 & RT_BIT(0)));
128#define FP32_NORM_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V0, FP32_EXP_V0)
129#define FP32_NORM_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V1, FP32_EXP_V1)
130#define FP32_NORM_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V2, FP32_EXP_V2)
131#define FP32_NORM_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V3, FP32_EXP_V3)
132#define FP32_NORM_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V4, FP32_EXP_V4)
133#define FP32_NORM_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V5, FP32_EXP_V5)
134#define FP32_NORM_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V6, FP32_EXP_V6)
135#define FP32_NORM_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V7, FP32_EXP_V7)
136/* The maximum integer value (all 23 + 1 implied bit of the fraction part set) without losing precision. */
137#define FP32_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX)
138/* The minimum integer value without losing precision. */
139#define FP32_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_SAFE_INT_MIN)
140
141/*
142 * Single-precision floating-point denormals.
143 */
144/** The maximum denormal value. */
145#define FP32_DENORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MAX, 0)
146/** The maximum denormal value. */
147#define FP32_DENORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MIN, 0)
148
149/*
150 * Single-precision random values (incl. potentially invalid values).
151 * We don't care what the exact values are as these are meant to populate
152 * unmodified parts of operands and be compared bitwise.
153 */
154#define FP32_RAND_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7bacda, 0x55)
155#define FP32_RAND_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7010f0, 0xc0)
156#define FP32_RAND_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x4ffcbe, 0xf1)
157#define FP32_RAND_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x2fd7c8, 0x1f)
158#define FP32_RAND_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5b5b5b, 0x09)
159#define FP32_RAND_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x3d2d1d, 0x99)
160#define FP32_RAND_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x123456, 0x5e)
161#define FP32_RAND_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x05432f, 0xd7)
162
163/*
164 * Double-precision (64 bits) floating-point defines.
165 */
166/** The max exponent value for a double-precision floating-point normal. */
167#define FP64_EXP_NORM_MAX 2046
168/** The min exponent value for a double-precision floating-point normal. */
169#define FP64_EXP_NORM_MIN 1
170/** The max fraction value for a double-precision floating-point normal. */
171#define FP64_FRAC_NORM_MAX 0xfffffffffffff
172/** The min fraction value for a double-precision floating-point normal. */
173#define FP64_FRAC_NORM_MIN 0
174/** The exponent bias for the double-precision floating-point format. */
175#define FP64_EXP_BIAS RTFLOAT64U_EXP_BIAS
176/** Fraction width (in bits) for the double-precision floating-point format. */
177#define FP64_FRAC_BITS RTFLOAT64U_FRACTION_BITS
178/** The max exponent value for a double-precision floating-point integer without
179 * losing precision. */
180#define FP64_EXP_SAFE_INT_MAX FP64_EXP_BIAS + FP64_FRAC_BITS
181/** The min exponent value for a double-precision floating-point integer without
182 * losing precision. */
183#define FP64_EXP_SAFE_INT_MIN 1
184/** The max fraction value for a double-precision floating-point denormal. */
185#define FP64_FRAC_DENORM_MAX 0xfffffffffffff
186/** The min fraction value for a double-precision floating-point denormal. */
187#define FP64_FRAC_DENORM_MIN 1
188
189#define FP64_NORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX)
190#define FP64_NORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_NORM_MIN)
191#define FP64_0(a_Sign) RTFLOAT64U_INIT_ZERO(a_Sign)
192#define FP64_1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0, RTFLOAT64U_EXP_BIAS)
193#define FP64_V(a_Sign, a_Frac, a_Exp) RTFLOAT64U_INIT_C(a_Sign, a_Frac, a_Exp)
194#define FP64_INF(a_Sign) RTFLOAT64U_INIT_INF(a_Sign)
195#define FP64_QNAN(a_Sign) RTFLOAT64U_INIT_QNAN(a_Sign)
196#define FP64_QNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val)
197#define FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign)
198#define FP64_SNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val)
199
200/*
201 * Double-precision random values (incl. potentially invalid values).
202 * We don't care what the exact values are as these are meant to populate
203 * unmodified parts of operands and be compared bitwise.
204 */
205#define FP64_RAND_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xab07eb7bcebce, 0x777)
206#define FP64_RAND_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x2fa17e10b3c7c, 0x6b6)
207#define FP64_RAND_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xceb1703cbe310, 0x100)
208#define FP64_RAND_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x7134abcdef10f, 0x70f)
209
210/*
211 * Double-precision floating-point normals.
212 * Fraction - 52 bits, all usable.
213 * Exponent - 11 bits, least significant bit MBZ.
214 */
215#define FP64_FRAC_V0 0xacc01adec0de5
216#define FP64_FRAC_V1 0xf10a7ab1ec01a
217#define FP64_FRAC_V2 0xca5cadea1b1ed
218#define FP64_FRAC_V3 0xb5b5b5b5b5b5b
219#define FP64_EXP_V0 0x30c
220#define FP64_EXP_V1 0x4bc
221#define FP64_EXP_V2 0x3ae
222#define FP64_EXP_V3 0x7fe
223AssertCompile(!(FP64_EXP_V0 & RT_BIT(0)));
224AssertCompile(!(FP64_EXP_V1 & RT_BIT(0)));
225AssertCompile(!(FP64_EXP_V2 & RT_BIT(0)));
226AssertCompile(!(FP64_EXP_V3 & RT_BIT(0)));
227#define FP64_NORM_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V0, FP64_EXP_V0)
228#define FP64_NORM_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V1, FP64_EXP_V1)
229#define FP64_NORM_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V2, FP64_EXP_V2)
230#define FP64_NORM_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V3, FP64_EXP_V3)
231/* The maximum integer value (all 52 + 1 implied bit of the fraction part set) without losing precision. */
232#define FP64_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX)
233/* The minimum integer value without losing precision. */
234#define FP64_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_SAFE_INT_MIN)
235
236/*
237 * Double-precision floating-point denormals.
238 */
239/** The maximum denormal value. */
240#define FP64_DENORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MAX, 0)
241/** The maximum denormal value. */
242#define FP64_DENORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MIN, 0)
243
244
245/*********************************************************************************************************************************
246* Structures and Typedefs *
247*********************************************************************************************************************************/
248/** Instruction set type and operand width. */
249typedef enum BS3CPUINSTRX_INSTRTYPE_T
250{
251 T_INVALID,
252 T_MMX,
253 T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */
254 T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */
255 T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */
256 T_AXMMX,
257 T_AXMMX_OR_SSE,
258 T_SSE,
259 T_128BITS = T_SSE,
260 T_SSE2,
261 T_SSE3,
262 T_SSSE3,
263 T_SSE4_1,
264 T_SSE4_2,
265 T_SSE4A,
266 T_PCLMUL,
267 T_SHA,
268 T_AVX_128,
269 T_AVX2_128,
270 T_AVX_PCLMUL,
271 T_AVX_256,
272 T_256BITS = T_AVX_256,
273 T_AVX2_256,
274 T_MAX
275} BS3CPUINSTRX_INSTRTYPE_T;
276
277/** Memory or register rm variant. */
278enum {
279 RM_REG = 0,
280 RM_MEM,
281 RM_MEM8, /**< Memory operand is 8 bytes. Hack for movss and similar. */
282 RM_MEM16, /**< Memory operand is 16 bytes. Hack for movss and similar. */
283 RM_MEM32, /**< Memory operand is 32 bytes. Hack for movss and similar. */
284 RM_MEM64 /**< Memory operand is 64 bytes. Hack for movss and similar. */
285};
286
287/**
288 * Execution environment configuration.
289 */
290typedef struct BS3CPUINSTR4_CONFIG_T
291{
292 uint16_t fCr0Mp : 1;
293 uint16_t fCr0Em : 1;
294 uint16_t fCr0Ts : 1;
295 uint16_t fCr4OsFxSR : 1;
296 uint16_t fCr4OsXSave : 1;
297 uint16_t fCr4OsXmmExcpt : 1;
298 uint16_t fXcr0Sse : 1;
299 uint16_t fXcr0Avx : 1;
300 uint16_t fAligned : 1; /**< Aligned mem operands. If 0, they will be misaligned and tests w/o mem operands skipped. */
301 uint16_t fAlignCheck : 1;
302 uint16_t fMxCsrMM : 1; /**< AMD only */
303 uint8_t bXcptSse;
304 uint8_t bXcptAvx;
305} BS3CPUINSTR4_CONFIG_T;
306/** Pointer to an execution environment configuration. */
307typedef BS3CPUINSTR4_CONFIG_T const BS3_FAR *PCBS3CPUINSTR4_CONFIG_T;
308
309/** State saved by bs3CpuInstr4ConfigReconfigure. */
310typedef struct BS3CPUINSTRX_CONFIG_SAVED_T
311{
312 uint32_t uCr0;
313 uint32_t uCr4;
314 uint32_t uEfl;
315 uint16_t uFcw;
316 uint16_t uFsw;
317 uint32_t uMxCsr;
318} BS3CPUINSTRX_CONFIG_SAVED_T;
319typedef BS3CPUINSTRX_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTRX_CONFIG_SAVED_T;
320typedef BS3CPUINSTRX_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTRX_CONFIG_SAVED_T;
321
322/**
323 * YMM packed single-precision floating-point register.
324 * @todo move to x86.h?
325 */
326typedef union X86YMMFLOATPSREG
327{
328 /** Packed single-precision floating-point view. */
329 RTFLOAT32U ar32[8];
330 /** 256-bit integer view. */
331 RTUINT256U ymm;
332} X86YMMFLOATPSREG;
333# ifndef VBOX_FOR_DTRACE_LIB
334AssertCompileSize(X86YMMFLOATPSREG, 32);
335AssertCompileSize(X86YMMFLOATPSREG, sizeof(X86YMMREG));
336# endif
337/** Pointer to a YMM packed single-precision floating-point register. */
338typedef X86YMMFLOATPSREG BS3_FAR *PX86YMMFLOATPSREG;
339/** Pointer to a const YMM single-precision packed floating-point register. */
340typedef X86YMMFLOATPSREG const BS3_FAR *PCX86YMMFLOATPSREG;
341
342/**
343 * YMM packed double-precision floating-point register.
344 * @todo move to x86.h?
345 */
346typedef union X86YMMFLOATPDREG
347{
348 /** Packed double-precision floating-point view. */
349 RTFLOAT64U ar64[4];
350 /** 256-bit integer view. */
351 RTUINT256U ymm;
352} X86YMMFLOATPDREG;
353# ifndef VBOX_FOR_DTRACE_LIB
354AssertCompileSize(X86YMMFLOATPDREG, 32);
355AssertCompileSize(X86YMMFLOATPDREG, sizeof(X86YMMREG));
356# endif
357/** Pointer to a YMM packed floating-point register. */
358typedef X86YMMFLOATPDREG BS3_FAR *PX86YMMFLOATPDREG;
359/** Pointer to a const YMM packed floating-point register. */
360typedef X86YMMFLOATPDREG const BS3_FAR *PCX86YMMFLOATPDREG;
361
362/**
363 * YMM scalar single-precision floating-point register.
364 * @todo move to x86.h?
365 */
366typedef union X86YMMFLOATSSREG
367{
368 /** Scalar single-precision floating-point view. */
369 RTFLOAT32U ar32[8];
370 /** 256-bit integer view. */
371 RTUINT256U ymm;
372} X86YMMFLOATSSREG;
373# ifndef VBOX_FOR_DTRACE_LIB
374AssertCompileSize(X86YMMFLOATSSREG, 32);
375AssertCompileSize(X86YMMFLOATSSREG, sizeof(X86YMMREG));
376# endif
377/** Pointer to a YMM scalar single-precision floating-point register. */
378typedef X86YMMFLOATSSREG BS3_FAR *PX86YMMFLOATSSREG;
379/** Pointer to a const YMM scalar single-precision floating-point register. */
380typedef X86YMMFLOATSSREG const BS3_FAR *PCX86YMMFLOATSSREG;
381
382/**
383 * YMM scalar double-precision floating-point register.
384 * @todo move to x86.h?
385 */
386typedef union X86YMMFLOATSDREG
387{
388 /** Scalar double-precision floating-point view. */
389 RTFLOAT64U ar64[4];
390 /** 256-bit integer view. */
391 RTUINT256U ymm;
392} X86YMMFLOATSDREG;
393# ifndef VBOX_FOR_DTRACE_LIB
394AssertCompileSize(X86YMMFLOATSDREG, 32);
395AssertCompileSize(X86YMMFLOATSDREG, sizeof(X86YMMREG));
396# endif
397/** Pointer to a YMM scalar double-precision floating-point register. */
398typedef X86YMMFLOATSDREG BS3_FAR *PX86YMMFLOATSDREG;
399/** Pointer to a const YMM scalar double-precision floating-point register. */
400typedef X86YMMFLOATSDREG const BS3_FAR *PCX86YMMFLOATSDREG;
401
402/**
403 * YMM scalar quadruple-precision floating-point register.
404 * @todo move to x86.h?
405 */
406typedef union X86YMMFLOATSQREG
407{
408 /** Scalar quadruple-precision floating point view. */
409 RTFLOAT128U ar128[2];
410 /** 256-bit integer view. */
411 RTUINT256U ymm;
412} X86YMMFLOATSQREG;
413# ifndef VBOX_FOR_DTRACE_LIB
414AssertCompileSize(X86YMMFLOATSQREG, 32);
415AssertCompileSize(X86YMMFLOATSQREG, sizeof(X86YMMREG));
416# endif
417/** Pointer to a YMM scalar quadruple-precision floating-point register. */
418typedef X86YMMFLOATSQREG *PX86YMMFLOATSQREG;
419/** Pointer to a const YMM scalar quadruple-precision floating-point register. */
420typedef X86YMMFLOATSQREG const *PCX86YMMFLOATSQREG;
421
422
423/*********************************************************************************************************************************
424* Global Variables *
425*********************************************************************************************************************************/
426static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false };
427static bool g_fAmdMisalignedSse = false;
428static uint8_t g_enmExtCtxMethod = BS3EXTCTXMETHOD_INVALID;
429static bool g_fMxCsrDazSupported = false;
430
431/** Size of g_pbBuf - at least three pages. */
432static uint32_t g_cbBuf;
433/** Buffer of g_cbBuf size. */
434static uint8_t BS3_FAR *g_pbBuf;
435/** RW alias for the buffer memory at g_pbBuf. Set up by bs3CpuInstrXBufSetup. */
436static uint8_t BS3_FAR *g_pbBufAlias;
437/** RW alias for the memory at g_pbBuf. */
438static uint8_t BS3_FAR *g_pbBufAliasAlloc;
439
440/** Exception type \#2 test configurations, 16 & 32 bytes strictly aligned. */
441static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig2[] =
442{
443/*
444 * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
445 * +AVX +AVX +AMD/SSE +AMD/SSE
446 * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
447 * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
448 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
449 { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
450 { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
451 { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
452 { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
453 { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
454 { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
455 { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
456 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
457 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
458 /* Memory misalignment and alignment checks: */
459 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
460 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #11 */
461 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
462 /* AMD only: */
463 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
464 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
465};
466
467/** Exception type \#3 test configurations (< 16-byte memory argument). */
468static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig3[] =
469{
470/*
471 * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to
472 * +AVX +AVX +AMD/SSE +AMD/SSE
473 * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR
474 * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */
475 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
476 { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
477 { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
478 { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
479 { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
480 { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
481 { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
482 { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
483 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
484 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
485 /* Memory misalignment and alignment checks: */
486 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* [Avx]:DB */
487 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */ /* [Avx]:AC */
488 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
489 /* AMD only: */
490 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
491 { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
492};
493
494
495/**
496 * Returns the name of an X86 exception given the vector.
497 *
498 * @returns Name of the exception.
499 * @param uVector The exception vector.
500 */
501static const char BS3_FAR *bs3CpuInstr4XcptName(uint8_t uVector)
502{
503 switch (uVector)
504 {
505 case X86_XCPT_DE: return "#DE";
506 case X86_XCPT_DB: return "#DB";
507 case X86_XCPT_NMI: return "#NMI";
508 case X86_XCPT_BP: return "#BP";
509 case X86_XCPT_OF: return "#OF";
510 case X86_XCPT_BR: return "#BR";
511 case X86_XCPT_UD: return "#UD";
512 case X86_XCPT_NM: return "#NM";
513 case X86_XCPT_DF: return "#DF";
514 case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
515 case X86_XCPT_TS: return "#TS";
516 case X86_XCPT_NP: return "#NP";
517 case X86_XCPT_SS: return "#SS";
518 case X86_XCPT_GP: return "#GP";
519 case X86_XCPT_PF: return "#PF";
520 case X86_XCPT_MF: return "#MF";
521 case X86_XCPT_AC: return "#AC";
522 case X86_XCPT_MC: return "#MC";
523 case X86_XCPT_XF: return "#XF";
524 case X86_XCPT_VE: return "#VE";
525 case X86_XCPT_CP: return "#CP";
526 case X86_XCPT_VC: return "#VC";
527 case X86_XCPT_SX: return "#SX";
528 }
529 return "UNKNOWN";
530}
531
532
533DECL_FORCE_INLINE(bool) bs3CpuInstr4IsSse(uint8_t enmType)
534{
535 return enmType >= T_SSE && enmType < T_AVX_128;
536}
537
538
539DECL_FORCE_INLINE(bool) bs3CpuInstr4IsAvx(uint8_t enmType)
540{
541 return enmType >= T_AVX_128;
542}
543
544
545DECL_FORCE_INLINE(uint8_t) bs3CpuInstr4GetOperandSize(uint8_t enmType)
546{
547 return enmType < T_128BITS ? 64/8
548 : enmType < T_256BITS ? 128/8 : 256/8;
549}
550
551
552/**
553 * Gets the names of floating-point exception flags that are set for a given MXCSR.
554 *
555 * @returns Names of floating-point exception flags that are set.
556 * @param pszBuf Where to store the floating-point exception flags.
557 * @param cchBuf The size of the buffer.
558 * @param uMxCsr The MXCSR value.
559 */
560static size_t bs3CpuInstr4GetXcptFlags(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
561{
562 BS3_ASSERT(cchBuf >= FP_XCPT_FLAGS_NAMES_MAXLEN);
563 return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IE ? " IE" : "", uMxCsr & X86_MXCSR_DE ? " DE" : "",
564 uMxCsr & X86_MXCSR_ZE ? " ZE" : "", uMxCsr & X86_MXCSR_OE ? " OE" : "",
565 uMxCsr & X86_MXCSR_UE ? " UE" : "", uMxCsr & X86_MXCSR_PE ? " PE" : "");
566}
567
568/**
569 * Gets the names of floating-point exception mask that are set for a given MXCSR.
570 *
571 * @returns Names of floating-point exception flags that are set.
572 * @param pszBuf Where to store the floating-point exception flags.
573 * @param cchBuf The size of the buffer.
574 * @param uMxCsr The MXCSR value.
575 */
576static size_t bs3CpuInstr4GetXcptMasks(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
577{
578 BS3_ASSERT(cchBuf >= FP_XCPT_MASKS_NAMES_MAXLEN);
579 return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IM ? " IM" : "", uMxCsr & X86_MXCSR_DM ? " DM" : "",
580 uMxCsr & X86_MXCSR_ZM ? " ZM" : "", uMxCsr & X86_MXCSR_OM ? " OM" : "",
581 uMxCsr & X86_MXCSR_UM ? " UM" : "", uMxCsr & X86_MXCSR_PM ? " PM" : "");
582}
583
584
585/**
586 * Gets the names of floating-point bits other than flags and masks that are set for
587 * a given MXCSR.
588 *
589 * @returns Names of floating-point exception flags that are set.
590 * @param pszBuf Where to store the floating-point exception flags.
591 * @param cchBuf The size of the buffer.
592 * @param uMxCsr The MXCSR value.
593 */
594static size_t bs3CpuInstr4GetXcptOthers(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr)
595{
596 uint32_t const fMxCsrRc = uMxCsr & X86_MXCSR_RC_MASK;
597 BS3_ASSERT(cchBuf >= FP_XCPT_OTHERS_NAMES_MAXLEN);
598 return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s", uMxCsr & X86_MXCSR_DAZ ? " DAZ" : "",
599 uMxCsr & X86_MXCSR_FZ ? " FZ" : "",
600 uMxCsr & X86_MXCSR_MM ? " MM" : "",
601 fMxCsrRc == X86_MXCSR_RC_NEAREST ? " RC=NEAREST" :
602 fMxCsrRc == X86_MXCSR_RC_DOWN ? " RC=DOWN" :
603 fMxCsrRc == X86_MXCSR_RC_UP ? " RC=UP" :
604 fMxCsrRc == X86_MXCSR_RC_ZERO ? " RC=ZERO" : "");
605}
606
607
608/**
609 * Reconfigures the execution environment according to @a pConfig.
610 *
611 * Call bs3CpuInstrXConfigRestore to undo the changes.
612 *
613 * @returns true on success, false if the configuration cannot be applied. In
614 * the latter case, no context changes are made.
615 * @param pSavedCfg Where to save state we modify.
616 * @param pCtx The register context to modify.
617 * @param pExtCtx The extended register context to modify.
618 * @param pConfig The configuration to apply.
619 * @param bMode The target mode.
620 */
621static bool bs3CpuInstr4ConfigReconfigure(PBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx,
622 PCBS3CPUINSTR4_CONFIG_T pConfig, uint8_t bMode)
623{
624 /*
625 * Save context bits we may change here
626 */
627 pSavedCfg->uCr0 = pCtx->cr0.u32;
628 pSavedCfg->uCr4 = pCtx->cr4.u32;
629 pSavedCfg->uEfl = pCtx->rflags.u32;
630 pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx);
631 pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx);
632 pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx);
633
634 /*
635 * Can we make these changes?
636 */
637 if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse)
638 return false;
639
640 /*
641 * Modify the test context.
642 */
643 if (pConfig->fCr0Mp)
644 pCtx->cr0.u32 |= X86_CR0_MP;
645 else
646 pCtx->cr0.u32 &= ~X86_CR0_MP;
647 if (pConfig->fCr0Em)
648 pCtx->cr0.u32 |= X86_CR0_EM;
649 else
650 pCtx->cr0.u32 &= ~X86_CR0_EM;
651 if (pConfig->fCr0Ts)
652 pCtx->cr0.u32 |= X86_CR0_TS;
653 else
654 pCtx->cr0.u32 &= ~X86_CR0_TS;
655
656 if (pConfig->fCr4OsFxSR)
657 pCtx->cr4.u32 |= X86_CR4_OSFXSR;
658 else
659 pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
660
661 if (pConfig->fCr4OsXmmExcpt && g_afTypeSupports[T_SSE])
662 pCtx->cr4.u32 |= X86_CR4_OSXMMEEXCPT;
663 else
664 pCtx->cr4.u32 &= ~X86_CR4_OSXMMEEXCPT;
665
666 if (pConfig->fCr4OsFxSR)
667 pCtx->cr4.u32 |= X86_CR4_OSFXSR;
668 else
669 pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
670
671 if (pConfig->fCr4OsXSave)
672 pCtx->cr4.u32 |= X86_CR4_OSXSAVE;
673 else
674 pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE;
675
676 if (pConfig->fXcr0Sse)
677 pExtCtx->fXcr0Saved |= XSAVE_C_SSE;
678 else
679 pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE;
680 if (pConfig->fXcr0Avx && g_afTypeSupports[T_AVX_256])
681 pExtCtx->fXcr0Saved |= XSAVE_C_YMM;
682 else
683 pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM;
684
685 if (pConfig->fAlignCheck)
686 {
687 pCtx->rflags.u32 |= X86_EFL_AC;
688 pCtx->cr0.u32 |= X86_CR0_AM;
689 }
690 else
691 {
692 pCtx->rflags.u32 &= ~X86_EFL_AC;
693 pCtx->cr0.u32 &= ~X86_CR0_AM;
694 }
695
696 /** @todo Can we remove this? x87 FPU and SIMD are independent. */
697 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B));
698
699 if (pConfig->fMxCsrMM)
700 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM);
701 else
702 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM);
703 return true;
704}
705
706
707/**
708 * Undoes changes made by bs3CpuInstr4ConfigReconfigure.
709 */
710static void bs3CpuInstrXConfigRestore(PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx)
711{
712 pCtx->cr0.u32 = pSavedCfg->uCr0;
713 pCtx->cr4.u32 = pSavedCfg->uCr4;
714 pCtx->rflags.u32 = pSavedCfg->uEfl;
715 pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal;
716 Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw);
717 Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw);
718 Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr);
719}
720
721
722/**
723 * Allocates three extended CPU contexts and initializes the first one
724 * with random data.
725 * @returns First extended context, initialized with randomish data. NULL on
726 * failure (complained).
727 * @param ppExtCtx2 Where to return the 2nd context.
728 */
729static PBS3EXTCTX bs3CpuInstrXAllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2)
730{
731 /* Allocate extended context structures. */
732 uint64_t fFlags;
733 uint16_t cb = Bs3ExtCtxGetSize(&fFlags);
734 PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2);
735 PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb);
736 if (pExtCtx1)
737 {
738 Bs3ExtCtxInit(pExtCtx1, cb, fFlags);
739 /** @todo populate with semi-random stuff. */
740
741 Bs3ExtCtxInit(pExtCtx2, cb, fFlags);
742 *ppExtCtx2 = pExtCtx2;
743 return pExtCtx1;
744 }
745 Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2);
746 *ppExtCtx2 = NULL;
747 return NULL;
748}
749
750
751/**
752 * Frees the extended CPU contexts allocated by bs3CpuInstrXAllocExtCtxs.
753 *
754 * @param pExtCtx1 The first extended context.
755 * @param pExtCtx2 The second extended context.
756 */
757static void bs3CpuInstrXFreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
758{
759 RT_NOREF_PV(pExtCtx2);
760 Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2);
761}
762
763
764/**
765 * Sets up SSE and AVX bits relevant for FPU instructions.
766 */
767static void bs3CpuInstr4SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx)
768{
769 /* CR0: */
770 uint32_t cr0 = Bs3RegGetCr0();
771 cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
772 cr0 |= X86_CR0_NE;
773 Bs3RegSetCr0(cr0);
774
775 /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */
776 pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
777 pCtx->cr0.u32 |= X86_CR0_NE;
778
779 /* CR4: */
780 BS3_ASSERT( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
781 || pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE);
782 {
783 uint32_t cr4 = Bs3RegGetCr4();
784 if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
785 {
786 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE;
787 Bs3RegSetCr4(cr4);
788 Bs3RegSetXcr0(pExtCtx->fXcr0Nominal);
789 }
790 else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
791 {
792 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT;
793 Bs3RegSetCr4(cr4);
794 }
795 pCtx->cr4.u32 = cr4;
796 }
797}
798
799
800/**
801 * Configures the buffer with electric fences in paged modes.
802 *
803 * @returns Adjusted buffer pointer.
804 * @param pbBuf The buffer pointer.
805 * @param pcbBuf Pointer to the buffer size (input & output).
806 * @param bMode The testing target mode.
807 */
808DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode)
809{
810 if (BS3_MODE_IS_PAGED(bMode))
811 {
812 int rc;
813 uint32_t cbBuf = *pcbBuf;
814 Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P);
815 Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P);
816 pbBuf += X86_PAGE_SIZE;
817 cbBuf -= X86_PAGE_SIZE * 2;
818 *pcbBuf = cbBuf;
819
820 g_pbBufAlias = g_pbBufAliasAlloc;
821 rc = Bs3PagingAlias((uintptr_t)g_pbBufAlias, (uintptr_t)pbBuf, cbBuf + X86_PAGE_SIZE, /* must include the tail guard pg */
822 X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
823 if (RT_FAILURE(rc))
824 Bs3TestFailedF("Bs3PagingAlias failed on %p/%p LB %#x: %d", g_pbBufAlias, pbBuf, cbBuf, rc);
825 }
826 else
827 g_pbBufAlias = pbBuf;
828 return pbBuf;
829}
830
831
832/**
833 * Undoes what bs3CpuInstrXBufSetup did.
834 *
835 * @param pbBuf The buffer pointer.
836 * @param cbBuf The buffer size.
837 * @param bMode The testing target mode.
838 */
839DECLINLINE(void) bs3CpuInstrXBufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode)
840{
841 if (BS3_MODE_IS_PAGED(bMode))
842 {
843 Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0);
844 Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0);
845 }
846}
847
848
849/**
850 * Gets a buffer of a @a cbMemOp sized operand according to the given
851 * configuration and alignment restrictions.
852 *
853 * @returns Pointer to the buffer.
854 * @param pbBuf The buffer pointer.
855 * @param cbBuf The buffer size.
856 * @param cbMemOp The operand size.
857 * @param cbAlign The operand alignment restriction.
858 * @param pConfig The configuration.
859 * @param fPageFault The \#PF test setting.
860 */
861DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign,
862 PCBS3CPUINSTR4_CONFIG_T pConfig, unsigned fPageFault)
863{
864 /* All allocations are at the tail end of the buffer, so that we've got a
865 guard page following the operand. When asked to consistenly trigger
866 a #PF, we slide the buffer into that guard page. */
867 if (fPageFault)
868 cbBuf += X86_PAGE_SIZE;
869
870 if (pConfig->fAligned)
871 {
872 if (!pConfig->fAlignCheck)
873 return &pbBuf[cbBuf - cbMemOp];
874 return &pbBuf[cbBuf - cbMemOp - cbAlign];
875 }
876 return &pbBuf[cbBuf - cbMemOp - 1];
877}
878
879
880/**
881 * Determines the size of memory operands.
882 */
883DECLINLINE(uint8_t) bs3CpuInstrXMemOpSize(uint8_t cbOperand, uint8_t enmRm)
884{
885 if (enmRm <= RM_MEM)
886 return cbOperand;
887 if (enmRm == RM_MEM8)
888 return sizeof(uint8_t);
889 if (enmRm == RM_MEM16)
890 return sizeof(uint16_t);
891 if (enmRm == RM_MEM32)
892 return sizeof(uint32_t);
893 if (enmRm == RM_MEM64)
894 return sizeof(uint64_t);
895 BS3_ASSERT(0);
896 return cbOperand;
897}
898
899
900/*
901 * Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly
902 * skips a large fraction of the micro-tests. It is sufficiently random
903 * that over a large number of runs, all micro-tests will be hit.
904 *
905 * This improves the runtime of the worst case (`#define ALL_TESTS' on a
906 * debug build, run with '--execute-all-in-iem') from ~9000 to ~800 seconds
907 * (on an Intel Core i7-10700, fwiw).
908 *
909 * To activate this 'developer's speed-testing mode', turn on
910 * `#define BS3_SKIPIT_DO_SKIP' here.
911 *
912 * BS3_SKIPIT_AVG_SKIP governs approximately how many micro-tests are
913 * skipped in a row; e.g. the default of 26 means about every 27th
914 * micro-test is run during a particular test run. (This is not 27x
915 * faster due to other activities which are not skipped!) Note this is
916 * only an average; the actual skips are random.
917 *
918 * You can also modify bs3CpuInstrX_SkipIt() to focus on specific sub-tests,
919 * using its (currently ignored) `bRing, iCfg, iTest, iVal, iVariant' args
920 * (to enable this: turn on `#define BS3_SKIPIT_DO_ARGS': which costs about
921 * 3% performance).
922 *
923 * Note! The skipping is not compatible with testing the native recompiler as
924 * it requires the test code to be run a number of times before it kicks
925 * in and does the native recompilation (currently around 16 times).
926 */
927#define BS3_SKIPIT_AVG_SKIP 26
928#define BS3_SKIPIT_REPORT_COUNT 150000
929#undef BS3_SKIPIT_DO_SKIP
930#undef BS3_SKIPIT_DO_ARGS
931
932#ifndef BS3_SKIPIT_DO_SKIP
933# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) (false)
934#else
935# include <iprt/asm-amd64-x86.h>
936# include <iprt/asm-math.h>
937
938DECLINLINE(uint32_t) bs3CpuInstrX_SimpleRand(void)
939{
940 /*
941 * A simple Lehmer linear congruential pseudo-random number
942 * generator using the constants suggested by Park & Miller:
943 *
944 * modulus = 2^31 - 1 (INT32_MAX)
945 * multiplier = 7^5 (16807)
946 *
947 * It produces numbers in the range [1..INT32_MAX-1] and is
948 * more chaotic in the higher bits.
949 *
950 * Note! Runtime/common/rand/randparkmiller.cpp is also use this algorithm,
951 * though the zero handling is different.
952 */
953 static uint32_t s_uSeedMemory = 0;
954 uint32_t uVal = s_uSeedMemory;
955 if (!uVal)
956 uVal = (uint32_t)ASMReadTSC();
957 uVal = ASMModU64ByU32RetU32(ASMMult2xU32RetU64(uVal, 16807), INT32_MAX);
958 s_uSeedMemory = uVal;
959 return uVal;
960}
961
962static unsigned g_cSeen, g_cSkipped;
963
964static void bs3CpuInstrX_ShowTallies(void)
965{
966 Bs3TestPrintf("Micro-tests %d: tested %d / skipped %d\n", g_cSeen, g_cSeen - g_cSkipped, g_cSkipped);
967}
968
969# ifdef BS3_SKIPIT_DO_ARGS
970# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt(bRing, iCfg, iTest, iVal, iVariant)
971static bool bs3CpuInstrX_SkipIt(uint8_t bRing, unsigned iCfg, unsigned iTest, unsigned iVal, unsigned iVariant)
972# else
973# define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt()
974static bool bs3CpuInstrX_SkipIt(void)
975# endif
976{
977 static unsigned s_uTimes = 0;
978 bool fSkip;
979
980 /* Cache calls to the relatively expensive random routine */
981 if (!s_uTimes)
982 s_uTimes = bs3CpuInstrX_SimpleRand() % (BS3_SKIPIT_AVG_SKIP * 2 + 1) + 1;
983 fSkip = --s_uTimes > 0;
984 if (fSkip)
985 ++g_cSkipped;
986
987 if (++g_cSeen % BS3_SKIPIT_REPORT_COUNT == 0)
988 bs3CpuInstrX_ShowTallies();
989 return fSkip;
990}
991
992#endif /* BS3_SKIPIT_DO_SKIP */
993
994/*
995 * Test type #1.
996 * Generic YMM registers.
997 */
998typedef struct BS3CPUINSTR4_TEST1_VALUES_T
999{
1000 X86YMMREG uSrc2; /**< Second source operand. */
1001 X86YMMREG uSrc1; /**< uDstIn for SSE */
1002 X86YMMREG uDstOut; /**< Destination output. */
1003 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1004 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1005 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1006 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1007 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1008 uint8_t afPadding[2]; /**< Alignment padding. */
1009} BS3CPUINSTR4_TEST1_VALUES_T;
1010
1011/*
1012 * Test type #1.
1013 * Packed single-precision.
1014 */
1015typedef struct BS3CPUINSTR4_TEST1_VALUES_PS_T
1016{
1017 X86YMMFLOATPSREG uSrc2; /**< Second source operand. */
1018 X86YMMFLOATPSREG uSrc1; /**< uDstIn for SSE */
1019 X86YMMFLOATPSREG uDstOut; /**< Destination output. */
1020 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1021 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1022 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1023 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1024 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1025 uint8_t afPadding[2]; /**< Alignment padding. */
1026} BS3CPUINSTR4_TEST1_VALUES_PS_T;
1027AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1028AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1029AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1030AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1031AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1032AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1033AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1034AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1035AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1036
1037/*
1038 * Test type #1.
1039 * Packed double-precision.
1040 */
1041typedef struct BS3CPUINSTR4_TEST1_VALUES_PD_T
1042{
1043 X86YMMFLOATPDREG uSrc2; /**< Second source operand. */
1044 X86YMMFLOATPDREG uSrc1; /**< uDstIn for SSE */
1045 X86YMMFLOATPDREG uDstOut; /**< Destination output. */
1046 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1047 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1048 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1049 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1050 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1051 uint8_t afPadding[2]; /**< Alignment padding. */
1052} BS3CPUINSTR4_TEST1_VALUES_PD_T;
1053AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1054AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1055AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1056AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1057AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1058AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1059AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1060AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1061AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1062
1063/*
1064 * Test type #1.
1065 * Scalar single-precision.
1066 */
1067typedef struct BS3CPUINSTR4_TEST1_VALUES_SS_T
1068{
1069 X86YMMFLOATSSREG uSrc2; /**< Second source operand. */
1070 X86YMMFLOATSSREG uSrc1; /**< uDstIn for SSE */
1071 X86YMMFLOATSSREG uDstOut; /**< Destination output. */
1072 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1073 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1074 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1075 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1076 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1077 uint8_t afPadding[2]; /**< Alignment padding. */
1078} BS3CPUINSTR4_TEST1_VALUES_SS_T;
1079AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1080AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1081AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1082AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1083AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1084AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1085AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1086AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1087AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1088
1089/*
1090 * Test type #1.
1091 * Scalar double-precision.
1092 */
1093typedef struct BS3CPUINSTR4_TEST1_VALUES_SD_T
1094{
1095 X86YMMFLOATSDREG uSrc2; /**< Second source operand. */
1096 X86YMMFLOATSDREG uSrc1; /**< uDstIn for SSE */
1097 X86YMMFLOATSDREG uDstOut; /**< Destination output. */
1098 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1099 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1100 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1101 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1102 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1103 uint8_t afPadding[2]; /**< Alignment padding. */
1104} BS3CPUINSTR4_TEST1_VALUES_SD_T;
1105AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1106AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1107AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1108AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1109AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1110AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1111AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1112AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1113AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1114
1115/*
1116 * Test type #1.
1117 * Scalar quadruple-precision.
1118 */
1119typedef struct BS3CPUINSTR4_TEST1_VALUES_SQ_T
1120{
1121 X86YMMFLOATSQREG uSrc2; /**< Second source operand. */
1122 X86YMMFLOATSQREG uSrc1; /**< uDstIn for SSE */
1123 X86YMMFLOATSQREG uDstOut; /**< Destination output. */
1124 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */
1125 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */
1126 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */
1127 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */
1128 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */
1129 uint8_t afPadding[2]; /**< Alignment padding. */
1130} BS3CPUINSTR4_TEST1_VALUES_SQ_T;
1131AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SQ_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
1132AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
1133AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
1134AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
1135AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr);
1136AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr);
1137AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr);
1138AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected);
1139AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected);
1140
1141typedef struct BS3CPUINSTR4_TEST1_T
1142{
1143 FPFNBS3FAR pfnWorker; /**< Test function worker. */
1144 uint8_t bAvxMisalignXcpt; /**< AVX misalignment exception. */
1145 uint8_t enmRm; /**< R/M type. */
1146 uint8_t enmType; /**< CPU instruction type (see T_XXX). */
1147 uint8_t iRegDst; /**< Index of destination register, UINT8_MAX if N/A. */
1148 uint8_t iRegSrc1; /**< Index of first source register, UINT8_MAX if N/A. */
1149 uint8_t iRegSrc2; /**< Index of second source register, UINT8_MAX if N/A. */
1150 uint8_t cValues; /**< Number of test values in @c paValues. */
1151 BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *paValues; /**< Test values. */
1152} BS3CPUINSTR4_TEST1_T;
1153
1154typedef struct BS3CPUINSTR4_TEST1_MODE_T
1155{
1156 BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests;
1157 unsigned cTests;
1158} BS3CPUINSTR4_TEST1_MODE_T;
1159
1160/** Initializer for a BS3CPUINSTR4_TEST1_MODE_T array (three entries). */
1161#define BS3CPUINSTR4_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
1162 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
1163
1164typedef struct BS3CPUINSTR4_TEST1_CTX_T
1165{
1166 BS3CPUINSTR4_CONFIG_T const BS3_FAR *pConfig; /**< The test execution environment configuration. */
1167 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest; /**< The instruction being tested. */
1168 unsigned iVal; /**< Which iteration of the test value is this. */
1169 const char BS3_FAR *pszMode; /**< The testing mode (e.g. real, protected, paged and permutations). */
1170 PBS3TRAPFRAME pTrapFrame; /**< The exception (trap) frame. */
1171 PBS3REGCTX pCtx; /**< The general-purpose register context. */
1172 PBS3EXTCTX pExtCtx; /**< The extended (FPU) register context. */
1173 PBS3EXTCTX pExtCtxOut; /**< The output extended (FPU) register context. */
1174 uint8_t BS3_FAR *puMemOp; /**< The memory operand buffer. */
1175 uint8_t BS3_FAR *puMemOpAlias; /**< The memory operand alias buffer for comparing result. */
1176 uint8_t cbMemOp; /**< Size of the memory operand (and alias) buffer in bytes. */
1177 uint8_t cbOperand; /**< Size of the instruction operand (8 for MMX, 16 for SSE etc). */
1178 uint8_t cbInstr; /**< Size of the instruction opcode. */
1179 uint8_t bXcptExpect; /**< The expected exception while/after executing the instruction. */
1180 uint16_t idTestStep; /**< The test iteration step. */
1181} BS3CPUINSTR4_TEST1_CTX_T;
1182/** Pointer to a test 1 context. */
1183typedef BS3CPUINSTR4_TEST1_CTX_T BS3_FAR *PBS3CPUINSTR4_TEST1_CTX_T;
1184
1185
1186/**
1187 * Worker for bs3CpuInstr4_WorkerTestType1.
1188 */
1189static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
1190 PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
1191{
1192 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = pTestCtx->pTest;
1193 BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
1194 PBS3TRAPFRAME pTrapFrame = pTestCtx->pTrapFrame;
1195 PBS3REGCTX pCtx = pTestCtx->pCtx;
1196 PBS3EXTCTX pExtCtx = pTestCtx->pExtCtx;
1197 PBS3EXTCTX pExtCtxOut = pTestCtx->pExtCtxOut;
1198 uint8_t BS3_FAR *puMemOp = pTestCtx->puMemOp;
1199 uint8_t BS3_FAR *puMemOpAlias = pTestCtx->puMemOpAlias;
1200 uint8_t cbMemOp = pTestCtx->cbMemOp;
1201 uint8_t const cbOperand = pTestCtx->cbOperand;
1202 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)pTestCtx->pTest->pfnWorker)[-1];
1203 uint8_t bXcptExpect = pTestCtx->bXcptExpect;
1204 uint8_t const bFpXcpt = pTestCtx->pConfig->fCr4OsXmmExcpt ? X86_XCPT_XF : X86_XCPT_UD;
1205 bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
1206 uint32_t uMxCsr;
1207 X86YMMREG MemOpExpect;
1208 uint16_t cErrors;
1209 uint32_t uExpectedMxCsr;
1210 bool fFpXcptExpected;
1211
1212 /*
1213 * An exception may be raised based on the test value (128 vs 256 bits).
1214 * In addition, we allow setting the exception flags (and mask) prior to
1215 * executing the instruction, so we cannot use the exception flags to figure
1216 * out if an exception will be raised. Hence, the input values provide us
1217 * explicitly whether an exception is expected for 128 and 256-bit variants.
1218 */
1219 if (pTestCtx->cbOperand > 16)
1220 {
1221 uExpectedMxCsr = pValues->u256ExpectedMxCsr;
1222 fFpXcptExpected = pValues->f256FpXcptExpected;
1223 }
1224 else
1225 {
1226 uExpectedMxCsr = pValues->u128ExpectedMxCsr;
1227 fFpXcptExpected = pValues->f128FpXcptExpected;
1228 }
1229
1230 /*
1231 * Set up the context and some expectations.
1232 */
1233 /* Destination. */
1234 Bs3MemZero(&MemOpExpect, sizeof(MemOpExpect));
1235 if (pTest->iRegDst == UINT8_MAX)
1236 {
1237 BS3_ASSERT(pTest->enmRm >= RM_MEM);
1238 Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp);
1239 if (bXcptExpect == X86_XCPT_DB)
1240 MemOpExpect.ymm = pValues->uDstOut.ymm;
1241 else
1242 Bs3MemSet(&MemOpExpect, 0xcc, sizeof(MemOpExpect));
1243 }
1244
1245 /* Source #1 (/ destination for SSE). */
1246 if (pTest->iRegSrc1 == UINT8_MAX)
1247 {
1248 BS3_ASSERT(pTest->enmRm >= RM_MEM);
1249 Bs3MemCpy(puMemOpAlias, &pValues->uSrc1, cbMemOp);
1250 if (pTest->iRegDst == UINT8_MAX)
1251 BS3_ASSERT(fSseInstr);
1252 else
1253 MemOpExpect.ymm = pValues->uSrc1.ymm;
1254 }
1255 else if (fSseInstr)
1256 Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm.DQWords.dqw0);
1257 else
1258 Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm, 32);
1259
1260 /* Source #2. */
1261 if (pTest->iRegSrc2 == UINT8_MAX)
1262 {
1263 BS3_ASSERT(pTest->enmRm >= RM_MEM);
1264 BS3_ASSERT(pTest->iRegDst != UINT8_MAX && pTest->iRegSrc1 != UINT8_MAX);
1265 Bs3MemCpy(puMemOpAlias, &pValues->uSrc2, cbMemOp);
1266 MemOpExpect.ymm = pValues->uSrc2.ymm;
1267 }
1268 else if (fSseInstr)
1269 Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm.DQWords.dqw0);
1270 else
1271 Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm, 32);
1272
1273 /* Memory pointer. */
1274 if (pTest->enmRm >= RM_MEM)
1275 {
1276 BS3_ASSERT( pTest->iRegDst == UINT8_MAX
1277 || pTest->iRegSrc1 == UINT8_MAX
1278 || pTest->iRegSrc2 == UINT8_MAX);
1279 Bs3RegCtxSetGrpSegFromCurPtr(pCtx, &pCtx->rbx, &pCtx->fs, puMemOp);
1280 }
1281
1282 /* Setup MXCSR for the current test. */
1283 uMxCsr = (pSavedCfg->uMxCsr & X86_MXCSR_MM) | pValues->uMxCsr;
1284 BS3_ASSERT(!(uMxCsr & X86_MXCSR_MM));
1285 BS3_ASSERT(!(uMxCsr & X86_MXCSR_DAZ) || g_fMxCsrDazSupported);
1286 Bs3ExtCtxSetMxCsr(pExtCtx, uMxCsr);
1287
1288 /*
1289 * Prepare globals and execute.
1290 */
1291 g_uBs3TrapEipHint = pCtx->rip.u32;
1292 if ( bXcptExpect == X86_XCPT_DB
1293 && !fFpXcptExpected)
1294 g_uBs3TrapEipHint += cbInstr + 1;
1295 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut);
1296
1297 /*
1298 * Check the result.
1299 *
1300 * If a floating-point exception is expected, the destination is not updated by the instruction.
1301 * In the case of SSE instructions, updating the destination here will work because it is the same
1302 * as the source, but for AVX++ it won't because the destination is different and would contain 0s.
1303 */
1304 cErrors = Bs3TestSubErrorCount();
1305 if ( bXcptExpect == X86_XCPT_DB
1306 && !fFpXcptExpected
1307 && pTest->iRegDst != UINT8_MAX)
1308 {
1309 if (fSseInstr)
1310 Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm.DQWords.dqw0);
1311 else
1312 Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm, cbOperand);
1313 }
1314#if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */
1315 if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE
1316 && pExtCtx->Ctx.x.Hdr.bmXState == 0x7
1317 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3)
1318 pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7;
1319#endif
1320 if (bXcptExpect == X86_XCPT_DB)
1321 Bs3ExtCtxSetMxCsr(pExtCtx, uExpectedMxCsr | (pSavedCfg->uMxCsr & X86_MXCSR_MM));
1322 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pTestCtx->pszMode, pTestCtx->idTestStep);
1323
1324 if (bXcptExpect == X86_XCPT_DB)
1325 {
1326 uint32_t const uGotMxCsr = Bs3ExtCtxGetMxCsr(pExtCtxOut) & ~X86_MXCSR_MM;
1327
1328 /* Check if the SIMD FP exception flags and mask (or lack of) are as expected. */
1329 if (uGotMxCsr != uExpectedMxCsr)
1330 {
1331 char szExpectFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
1332 char szExpectMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
1333 char szExpectOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
1334 char szGotFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
1335 char szGotMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
1336 char szGotOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
1337 bs3CpuInstr4GetXcptFlags(&szExpectFlags[0], sizeof(szExpectFlags), uExpectedMxCsr);
1338 bs3CpuInstr4GetXcptMasks(&szExpectMasks[0], sizeof(szExpectMasks), uExpectedMxCsr);
1339 bs3CpuInstr4GetXcptOthers(&szExpectOthers[0], sizeof(szExpectOthers), uExpectedMxCsr);
1340 bs3CpuInstr4GetXcptFlags(&szGotFlags[0], sizeof(szGotFlags), uGotMxCsr);
1341 bs3CpuInstr4GetXcptMasks(&szGotMasks[0], sizeof(szGotMasks), uGotMxCsr);
1342 bs3CpuInstr4GetXcptOthers(&szGotOthers[0], sizeof(szGotOthers), uGotMxCsr);
1343 Bs3TestFailedF("Expected MXCSR %#RX32 (%s%s%s ) got MXCSR %#RX32 (%s%s%s )", uExpectedMxCsr,
1344 szExpectFlags, szExpectMasks, szExpectOthers, uGotMxCsr, szGotFlags, szGotMasks, szGotOthers);
1345 }
1346
1347 /* Check if the SIMD FP exception (or lack of) is as expected. */
1348 if (fFpXcptExpected)
1349 {
1350 if (pTrapFrame->bXcpt == bFpXcpt)
1351 { /* likely */ }
1352 else
1353 Bs3TestFailedF("Expected floating-point xcpt %s, got %s", bs3CpuInstr4XcptName(bFpXcpt),
1354 bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1355 }
1356 else if (pTrapFrame->bXcpt == X86_XCPT_DB)
1357 { /* likely */ }
1358 else
1359 Bs3TestFailedF("Expected no xcpt, got %s", bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1360 }
1361 /* Check if non-FP exception is as expected. */
1362 else if (pTrapFrame->bXcpt != bXcptExpect)
1363 Bs3TestFailedF("Expected xcpt %s, got %s", bs3CpuInstr4XcptName(bXcptExpect), bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
1364
1365 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
1366 if (bMode == BS3_MODE_RM && (pCtx->rflags.u32 & X86_EFL_AC))
1367 {
1368 if (pTrapFrame->Ctx.rflags.u32 & X86_EFL_AC)
1369 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", pTrapFrame->bXcpt);
1370 pTrapFrame->Ctx.rflags.u32 |= X86_EFL_AC;
1371 }
1372 if (bXcptExpect == X86_XCPT_PF)
1373 pCtx->cr2.u = (uintptr_t)puMemOp;
1374 Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, bXcptExpect == X86_XCPT_DB && !fFpXcptExpected ? cbInstr + 1 : 0, 0 /*cbSpAdjust*/,
1375 (bXcptExpect == X86_XCPT_DB && !fFpXcptExpected) || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
1376 pTestCtx->pszMode, pTestCtx->idTestStep);
1377 pCtx->cr2.u = 0;
1378
1379 if ( pTest->enmRm >= RM_MEM
1380 && Bs3MemCmp(puMemOpAlias, &MemOpExpect, cbMemOp) != 0)
1381 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &MemOpExpect, cbMemOp, puMemOpAlias);
1382
1383 return cErrors;
1384}
1385
1386
1387/**
1388 * Test type #1 worker.
1389 */
1390static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
1391 PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs)
1392{
1393 BS3REGCTX Ctx;
1394 BS3TRAPFRAME TrapFrame;
1395 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode);
1396 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
1397 uint8_t BS3_FAR *pbBuf = g_pbBuf;
1398 uint32_t cbBuf = g_cbBuf;
1399 PBS3EXTCTX pExtCtxOut;
1400 PBS3EXTCTX pExtCtx = bs3CpuInstrXAllocExtCtxs(&pExtCtxOut);
1401 if (pExtCtx)
1402 { /* likely */ }
1403 else
1404 return 0;
1405 if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
1406 { /* likely */ }
1407 else
1408 {
1409 Bs3TestPrintf("Skipped due to ancient FPU state format\n");
1410 return 0;
1411 }
1412
1413 /* Ensure the structures are allocated before we sample the stack pointer. */
1414 Bs3MemSet(&Ctx, 0, sizeof(Ctx));
1415 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
1416
1417 /*
1418 * Create test context.
1419 */
1420 pbBuf = bs3CpuInstrXBufSetup(pbBuf, &cbBuf, bMode);
1421 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
1422 bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx);
1423
1424 /*
1425 * Run the tests in all rings since alignment issues may behave
1426 * differently in ring-3 compared to ring-0.
1427 */
1428 for (;;)
1429 {
1430 unsigned fPf = 0;
1431 do
1432 {
1433 unsigned iCfg;
1434 for (iCfg = 0; iCfg < cConfigs; iCfg++)
1435 {
1436 unsigned iTest;
1437 BS3CPUINSTRX_CONFIG_SAVED_T SavedCfg;
1438 if (!bs3CpuInstr4ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
1439 continue; /* unsupported config */
1440
1441 /*
1442 * Iterate the tests.
1443 */
1444 for (iTest = 0; iTest < cTests; iTest++)
1445 {
1446 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = &paTests[iTest];
1447 unsigned const cValues = pTest->cValues;
1448 bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType);
1449 bool const fAvxInstr = bs3CpuInstr4IsAvx(pTest->enmType);
1450 uint8_t const cbOperand = bs3CpuInstr4GetOperandSize(pTest->enmType);
1451 uint8_t const cbMemOp = bs3CpuInstrXMemOpSize(cbOperand, pTest->enmRm);
1452 uint8_t const cbAlign = cbMemOp;
1453 uint8_t BS3_FAR *puMemOp = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf);
1454 uint8_t *puMemOpAlias = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf];
1455 uint8_t bXcptExpect = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD
1456 : fSseInstr ? paConfigs[iCfg].bXcptSse
1457 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
1458 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10;
1459 unsigned cRecompRuns = 0;
1460 unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues;
1461 unsigned iVal;
1462
1463 /* If testing unaligned memory accesses (or #PF), skip register-only tests. This
1464 allows setting bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
1465 if ( (pTest->enmRm == RM_REG || pTest->enmRm == RM_MEM8)
1466 && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf))
1467 continue;
1468
1469 /* #AC is only raised in ring-3. */
1470 if (bXcptExpect == X86_XCPT_AC)
1471 {
1472 if (bRing != 3)
1473 bXcptExpect = X86_XCPT_DB;
1474 else if (fAvxInstr)
1475 bXcptExpect = pTest->bAvxMisalignXcpt; /* they generally don't raise #AC */
1476 }
1477
1478 if (fPf && bXcptExpect == X86_XCPT_DB)
1479 bXcptExpect = X86_XCPT_PF;
1480
1481 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, pTest->pfnWorker);
1482
1483 /*
1484 * Iterate the test values and do the actual testing.
1485 */
1486 while (cRecompRuns < cMaxRecompRuns)
1487 {
1488 for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
1489 {
1490 uint16_t cErrors;
1491 BS3CPUINSTR4_TEST1_CTX_T TestCtx;
1492
1493 if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0))
1494 continue;
1495
1496 /*
1497 * If the hardware does not support DAZ bit skip test values that set it.
1498 */
1499 if ( !g_fMxCsrDazSupported
1500 && (pTest->paValues[iVal].uMxCsr & X86_MXCSR_DAZ))
1501 continue;
1502
1503 /*
1504 * Setup the test instruction context and pass it to the worker.
1505 * A few of these can be figured out by the worker but initializing
1506 * it outside the inner most loop is more optimal.
1507 */
1508 TestCtx.pConfig = &paConfigs[iCfg];
1509 TestCtx.pTest = pTest;
1510 TestCtx.iVal = iVal;
1511 TestCtx.pszMode = pszMode;
1512 TestCtx.pTrapFrame = &TrapFrame;
1513 TestCtx.pCtx = &Ctx;
1514 TestCtx.pExtCtx = pExtCtx;
1515 TestCtx.pExtCtxOut = pExtCtxOut;
1516 TestCtx.puMemOp = (uint8_t *)puMemOp;
1517 TestCtx.puMemOpAlias = puMemOpAlias;
1518 TestCtx.cbMemOp = cbMemOp;
1519 TestCtx.cbOperand = cbOperand;
1520 TestCtx.bXcptExpect = bXcptExpect;
1521 TestCtx.idTestStep = idTestStep;
1522 cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
1523 if (cErrors != Bs3TestSubErrorCount())
1524 {
1525 if (paConfigs[iCfg].fAligned)
1526 Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, %s %u-bit)",
1527 Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
1528 bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), fSseInstr ? "SSE" : "AVX", cbOperand * 8);
1529 else
1530 Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, puMemOp=%p, EFLAGS=%#RX32, %s %u-bit)",
1531 Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
1532 bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), puMemOp,
1533 TrapFrame.Ctx.rflags.u32, fSseInstr ? "SSE" : "AVX", cbOperand * 8);
1534 Bs3TestPrintf("\n");
1535 }
1536 }
1537 }
1538 }
1539 bs3CpuInstrXConfigRestore(&SavedCfg, &Ctx, pExtCtx);
1540 }
1541 } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode));
1542
1543 /*
1544 * Next ring.
1545 */
1546 bRing++;
1547 if (bRing > 3 || bMode == BS3_MODE_RM)
1548 break;
1549 Bs3RegCtxConvertToRingX(&Ctx, bRing);
1550 }
1551
1552 /*
1553 * Cleanup.
1554 */
1555 bs3CpuInstrXBufCleanup(pbBuf, cbBuf, bMode);
1556 bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut);
1557 return 0;
1558}
1559
1560
1561/*
1562 * [V]ADDPS.
1563 */
1564BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addps(uint8_t bMode)
1565{
1566 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
1567 {
1568 /*
1569 * Zero.
1570 */
1571 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1572 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1573 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1574 /*mxcsr:in */ 0,
1575 /*128:out */ 0,
1576 /*256:out */ 0,
1577 /*xcpt? */ false, false },
1578 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1579 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1580 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1581 /*mxcsr:in */ 0,
1582 /*128:out */ 0,
1583 /*256:out */ 0,
1584 /*xcpt? */ false, false },
1585 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1586 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1587 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1588 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
1589 /*128:out */ X86_MXCSR_RC_ZERO,
1590 /*256:out */ X86_MXCSR_RC_ZERO,
1591 /*xcpt? */ false, false },
1592 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1593 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1594 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
1595 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1596 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1597 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1598 /*xcpt? */ false, false },
1599 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1600 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1601 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
1602 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1603 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1604 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1605 /*xcpt? */ false, false },
1606 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1607 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1608 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
1609 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1610 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1611 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1612 /*xcpt? */ false, false },
1613 /*
1614 * Infinity.
1615 */
1616 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1617 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1618 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1619 /*mxcsr:in */ X86_MXCSR_IM,
1620 /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE,
1621 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE,
1622 /*xcpt? */ false, false },
1623 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1624 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1625 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1626 /*mxcsr:in */ 0,
1627 /*128:out */ X86_MXCSR_IE,
1628 /*256:out */ X86_MXCSR_IE,
1629 /*xcpt? */ true, true },
1630 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
1631 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
1632 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
1633 /*mxcsr:in */ X86_MXCSR_FZ,
1634 /*128:out */ X86_MXCSR_FZ,
1635 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
1636 /*xcpt? */ false, true },
1637 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
1638 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
1639 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(0) } },
1640 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1641 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1642 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1643 /*xcpt? */ false, true },
1644 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
1645 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
1646 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
1647 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1648 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1649 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1650 /*xcpt? */ true, true },
1651 /*
1652 * Overflow, Precision.
1653 */
1654 /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1655 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1656 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), } },
1657 /*mxcsr:in */ 0,
1658 /*128:out */ 0,
1659 /*256:out */ X86_MXCSR_OE,
1660 /*xcpt? */ false, true },
1661 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } },
1662 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0) } },
1663 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } },
1664 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
1665 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1666 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1667 /*xcpt? */ false, false },
1668 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
1669 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
1670 { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0) } },
1671 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1672 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
1673 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
1674 /*xcpt? */ false, false },
1675 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
1676 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
1677 { /* => */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },
1678 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1679 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
1680 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
1681 /*xcpt? */ false, false },
1682 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1683 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1684 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1685 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1686 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1687 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE,
1688 /*xcpt? */ false, true },
1689 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1690 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1691 { /* => */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
1692 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
1693 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1694 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
1695 /*xcpt? */ false, false },
1696 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
1697 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
1698 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_NORM_MAX(1), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1) } },
1699 /*mxcsr:in */ 0,
1700 /*128:out */ X86_MXCSR_PE,
1701 /*256:out */ X86_MXCSR_PE,
1702 /*xcpt? */ true, true },
1703 /*
1704 * Normals.
1705 */
1706 /*18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.25*/ } },
1707 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/ } },
1708 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/ } },
1709 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1710 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1711 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1712 /*xcpt? */ false, false },
1713 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
1714 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0) } },
1715 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1716 /*mxcsr:in */ 0,
1717 /*128:out */ 0,
1718 /*256:out */ 0,
1719 /*xcpt? */ false, false },
1720 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_0(0) } },
1721 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_1(1) /*- 1.00*/, FP32_0(0) } },
1722 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_0(0) } },
1723 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
1724 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
1725 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
1726 /*xcpt? */ false, false },
1727 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1), FP32_0(0) } },
1728 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_1(0), FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } },
1729 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_0(0), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_0(0), FP32_1(0) } },
1730 /*mxcsr:in */ X86_MXCSR_FZ,
1731 /*128:out */ X86_MXCSR_FZ,
1732 /*256:out */ X86_MXCSR_FZ,
1733 /*xcpt? */ false, false },
1734 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } },
1735 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_0(1), FP32_0(0) } },
1736 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(1), FP32_0(0) } },
1737 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1738 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1739 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1740 /*xcpt? */ false, false },
1741 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), } },
1742 { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), } },
1743 { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
1744 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1745 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1746 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1747 /*xcpt? */ false, false },
1748 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0) } },
1749 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0) } },
1750 { /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } },
1751 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1752 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1753 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1754 /*xcpt? */ false, false },
1755 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
1756 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
1757 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
1758 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
1759 /*128:out */ X86_MXCSR_RC_DOWN,
1760 /*256:out */ X86_MXCSR_RC_DOWN,
1761 /*xcpt? */ false, false },
1762 /*
1763 * Denormals.
1764 */
1765 /*26*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1766 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1767 { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1768 /*mxcsr:in */ 0,
1769 /*128:out */ X86_MXCSR_DE,
1770 /*256:out */ X86_MXCSR_DE,
1771 /*xcpt? */ true, true },
1772 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1773 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
1774 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
1775 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1776 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
1777 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
1778 /*xcpt? */ false, false },
1779 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
1780 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
1781 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1782 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1783 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1784 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
1785 /*xcpt? */ false, false },
1786 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1787 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1788 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1789 /*mxcsr:in */ 0,
1790 /*128:out */ X86_MXCSR_DE,
1791 /*256:out */ X86_MXCSR_DE,
1792 /*xcpt? */ true, true },
1793 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
1794 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1795 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1796 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
1797 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
1798 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
1799 /*xcpt? */ false, false },
1800 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
1801 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
1802 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
1803 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1804 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1805 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1806 /*xcpt? */ false, false },
1807 /** @todo More Denormals. */
1808 /*
1809 * Invalids.
1810 */
1811 /*32*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1812 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1813 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1814 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1815 /*128:out */ X86_MXCSR_XCPT_MASK,
1816 /*256:out */ X86_MXCSR_XCPT_MASK,
1817 /*xcpt? */ false, false },
1818 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1819 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
1820 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1821 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1822 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1823 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1824 /*xcpt? */ false, false },
1825 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
1826 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1827 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1828 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
1829 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
1830 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
1831 /*xcpt? */ false, false },
1832 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
1833 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
1834 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
1835 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1836 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1837 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1838 /*xcpt? */ false, false },
1839 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1840 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1841 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1842 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,
1843 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,
1844 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,
1845 /*xcpt? */ false, false },
1846 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
1847 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1848 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1849 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1850 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1851 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
1852 /*xcpt? */ false, false },
1853 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1854 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1855 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1856 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1857 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1858 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
1859 /*xcpt? */ false, false },
1860 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
1861 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
1862 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
1863 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1864 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1865 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1866 /*xcpt? */ true, true },
1867 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
1868 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1869 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
1870 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
1871 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
1872 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
1873 /*xcpt? */ true, true },
1874 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
1875 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
1876 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
1877 /*mxcsr:in */ X86_MXCSR_RC_UP,
1878 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
1879 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
1880 /*xcpt? */ true, true },
1881 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1882 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1883 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1884 /*mxcsr:in */ 0,
1885 /*128:out */ 0,
1886 /*256:out */ 0,
1887 /*xcpt? */ false, false },
1888 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
1889 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
1890 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
1891 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
1892 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1893 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
1894 /*xcpt? */ true, true },
1895 /** @todo Underflow, Precision; Rounding, FZ etc. */
1896 };
1897
1898 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
1899 {
1900 { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1901 { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1902
1903 { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1904 { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1905
1906 { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1907 { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1908 };
1909 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
1910 {
1911 { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1912 { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1913
1914 { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1915 { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1916
1917 { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1918 { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1919 };
1920 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
1921 {
1922 { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1923 { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1924
1925 { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1926 { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1927
1928 { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1929 { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1930
1931 { bs3CpuInstr4_addps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1932 { bs3CpuInstr4_addps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1933
1934 { bs3CpuInstr4_vaddps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1935 { bs3CpuInstr4_vaddps_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1936 { bs3CpuInstr4_vaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1937 { bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
1938 };
1939
1940 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
1941 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
1942 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
1943 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
1944}
1945
1946
1947/*
1948 * [V]ADDPD.
1949 */
1950BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addpd(uint8_t bMode)
1951{
1952 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
1953 {
1954 /*
1955 * Zero.
1956 */
1957 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1958 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1959 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1960 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
1961 /*128:out */ X86_MXCSR_XCPT_MASK,
1962 /*256:out */ X86_MXCSR_XCPT_MASK,
1963 /*xcpt? */ false, false },
1964 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1965 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1966 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1967 /*mxcsr:in */ X86_MXCSR_FZ,
1968 /*128:out */ X86_MXCSR_FZ,
1969 /*256:out */ X86_MXCSR_FZ,
1970 /*xcpt? */ false, false },
1971 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1972 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1973 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
1974 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
1975 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
1976 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
1977 /*xcpt? */ false, false },
1978 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1979 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1980 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
1981 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1982 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1983 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
1984 /*xcpt? */ false, false },
1985 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1986 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1987 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
1988 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1989 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1990 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
1991 /*xcpt? */ false, false },
1992 /*
1993 * Infinity.
1994 */
1995 /* 5*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
1996 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
1997 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
1998 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
1999 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2000 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2001 /*xcpt? */ true, true },
2002 { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } },
2003 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2004 { /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2005 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2006 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2007 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2008 /*xcpt? */ true, true },
2009 { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } },
2010 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2011 { /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2012 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2013 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
2014 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
2015 /*xcpt? */ true, true },
2016 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(0), FP64_INF(1) } },
2017 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } },
2018 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } },
2019 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2020 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2021 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2022 /*xcpt? */ false, false },
2023 { { /*src2 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_0(1), FP64_0(0), FP64_INF(1) } },
2024 { /*src1 */ { FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_0(1), FP64_0(0), FP64_INF(0) } },
2025 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/, FP64_0(1), FP64_0(0), FP64_QNAN(1) } },
2026 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2027 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2028 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2029 /*xcpt? */ false, false },
2030 /*
2031 * Overflow, Precision.
2032 */
2033 /*10*/{ { /*src2 */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } },
2034 { /*src1 */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } },
2035 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2036 /*mxcsr:in */ 0,
2037 /*128:out */ X86_MXCSR_OE,
2038 /*256:out */ X86_MXCSR_OE,
2039 /*xcpt? */ true, true },
2040 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } },
2041 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } },
2042 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } },
2043 /*mxcsr:in */ 0,
2044 /*128:out */ X86_MXCSR_OE,
2045 /*256:out */ X86_MXCSR_OE,
2046 /*xcpt? */ true, true },
2047 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
2048 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
2049 { /* => */ { FP64_INF(0), FP64_V(1, 0, 2), FP64_0(0), FP64_INF(0) } },
2050 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ,
2051 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2052 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2053 /*xcpt? */ false, false },
2054 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
2055 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },
2056 { /* => */ { FP64_V(1, 0, 2), FP64_INF(0), FP64_0(0), FP64_0(0) } },
2057 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
2058 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2059 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
2060 /*xcpt? */ false, false },
2061 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2062 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2063 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
2064 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2065 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
2066 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
2067 /*xcpt? */ false, false },
2068 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },
2069 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },
2070 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } },
2071 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2072 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2073 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2074 /*xcpt? */ true, true },
2075 /** @todo Why does the below on cause PE?! */
2076 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/* 1.75*/, FP64_NORM_MAX(0), FP64_0(0), FP64_V(0, 0, 0x3fd)/*0.25*/ } },
2077 { /*src1 */ { FP64_V(1, 0, 0x07d)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0, 0x3fe)/*0.50*/ } },
2078 { /* => */ { FP64_V(0, 0xbffffffffffff, 0x3ff)/* 1.50*/, FP64_0(1), FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } },
2079 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2080 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
2081 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
2082 /*xcpt? */ false, false },
2083 /*
2084 * Normals.
2085 */
2086 /*17*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } },
2087 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_0(0) } },
2088 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2089 /*mxcsr:in */ 0,
2090 /*128:out */ 0,
2091 /*256:out */ 0,
2092 /*xcpt? */ false, false },
2093 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_0(0), FP64_0(0) } },
2094 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_0(0), FP64_0(0) } },
2095 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_0(0), FP64_0(0) } },
2096 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2097 /*128:out */ X86_MXCSR_XCPT_MASK,
2098 /*256:out */ X86_MXCSR_XCPT_MASK,
2099 /*xcpt? */ false, false },
2100 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
2101 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } },
2102 { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
2103 /*mxcsr:in */ 0,
2104 /*128:out */ 0,
2105 /*256:out */ 0,
2106 /*xcpt? */ false, false },
2107 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } },
2108 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_0(0), FP64_0(0) } },
2109 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
2110 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2111 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2112 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2113 /*xcpt? */ false, false },
2114 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_0(0), FP64_0(0) } },
2115 { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_0(0) } },
2116 { /* => */ { FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_0(0), FP64_0(0) } },
2117 /*mxcsr:in */ X86_MXCSR_FZ,
2118 /*128:out */ X86_MXCSR_FZ,
2119 /*256:out */ X86_MXCSR_FZ,
2120 /*xcpt? */ false, false },
2121 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
2122 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },
2123 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2) } },
2124 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2125 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2126 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2127 /*xcpt? */ false, false },
2128 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
2129 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
2130 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2) } },
2131 /*mxcsr:in */ X86_MXCSR_RC_UP,
2132 /*128:out */ X86_MXCSR_RC_UP,
2133 /*256:out */ X86_MXCSR_RC_UP,
2134 /*xcpt? */ false, false },
2135 /*
2136 * Denormals.
2137 */
2138 /*24*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2139 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2140 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2141 /*mxcsr:in */ 0,
2142 /*128:out */ X86_MXCSR_DE,
2143 /*256:out */ X86_MXCSR_DE,
2144 /*xcpt? */ true, true },
2145 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2146 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
2147 { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
2148 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2149 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
2150 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
2151 /*xcpt? */ false, false },
2152 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
2153 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
2154 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2155 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2156 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2157 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2158 /*xcpt? */ false, false },
2159 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
2160 /*
2161 * Invalids.
2162 */
2163 /*27*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2164 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2165 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2166 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2167 /*128:out */ X86_MXCSR_XCPT_MASK,
2168 /*256:out */ X86_MXCSR_XCPT_MASK,
2169 /*xcpt? */ false, false },
2170 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2171 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2172 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2173 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2174 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2175 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2176 /*xcpt? */ false, false },
2177 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2178 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2179 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2180 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2181 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2182 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2183 /*xcpt? */ false, false },
2184 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2185 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
2186 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
2187 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2188 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2189 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2190 /*xcpt? */ false, false },
2191 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2192 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
2193 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2194 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2195 /*128:out */ X86_MXCSR_XCPT_MASK,
2196 /*256:out */ X86_MXCSR_XCPT_MASK,
2197 /*xcpt? */ false, false },
2198 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2199 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
2200 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2201 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2202 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2203 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2204 /*xcpt? */ false, false },
2205 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2206 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2207 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2208 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2209 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2210 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2211 /*xcpt? */ false, false },
2212 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
2213 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
2214 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
2215 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2216 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2217 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2218 /*xcpt? */ true, true },
2219 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
2220 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2221 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2222 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2223 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2224 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2225 /*xcpt? */ true, true },
2226 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2227 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
2228 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
2229 /*mxcsr:in */ X86_MXCSR_RC_UP,
2230 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
2231 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
2232 /*xcpt? */ true, true },
2233 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2234 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
2235 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
2236 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
2237 /*128:out */ X86_MXCSR_RC_DOWN,
2238 /*256:out */ X86_MXCSR_RC_DOWN,
2239 /*xcpt? */ false, false },
2240 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
2241 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
2242 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
2243 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2244 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2245 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2246 /*xcpt? */ true, true },
2247 };
2248
2249 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2250 {
2251 { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2252 { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2253
2254 { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2255 { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2256
2257 { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2258 { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2259 };
2260 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2261 {
2262 { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2263 { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2264
2265 { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2266 { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2267
2268 { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2269 { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2270 };
2271 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2272 {
2273 { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2274 { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2275
2276 { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2277 { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2278
2279 { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2280 { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2281
2282 { bs3CpuInstr4_addpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2283 { bs3CpuInstr4_addpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2284
2285 { bs3CpuInstr4_vaddpd_XMM8_XMM9_XMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2286 { bs3CpuInstr4_vaddpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2287 { bs3CpuInstr4_vaddpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2288 { bs3CpuInstr4_vaddpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2289 };
2290
2291 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2292 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2293 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2294 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
2295}
2296
2297
2298/*
2299 * [V]ADDSS.
2300 */
2301BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addss(uint8_t bMode)
2302{
2303 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
2304 {
2305 /*
2306 * Zero.
2307 */
2308 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2309 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2310 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2311 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2312 /*128:out */ X86_MXCSR_XCPT_MASK,
2313 /*256:out */ X86_MXCSR_XCPT_MASK,
2314 /*xcpt? */ false, false },
2315 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2316 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2317 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2318 /*mxcsr:in */ 0,
2319 /*128:out */ 0,
2320 /*256:out */ 0,
2321 /*xcpt? */ false, false },
2322 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2323 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2324 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2325 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2326 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2327 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2328 /*xcpt? */ false, false },
2329 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2330 { /*src1 */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2331 { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2332 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2333 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2334 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2335 /*xcpt? */ false, false },
2336 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2337 { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2338 { /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2339 /*mxcsr:in */ X86_MXCSR_FZ,
2340 /*128:out */ X86_MXCSR_FZ,
2341 /*256:out */ X86_MXCSR_FZ,
2342 /*xcpt? */ false, false },
2343 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2344 { /*src1 */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2345 { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2346 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2347 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2348 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2349 /*xcpt? */ false, false },
2350 /*
2351 * Infinity.
2352 */
2353 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2354 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2355 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
2356 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
2357 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2358 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2359 /*xcpt? */ true, true },
2360 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2361 { /*src1 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2362 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2363 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
2364 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2365 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2366 /*xcpt? */ true, true },
2367 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2368 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2369 { /* => */ { FP32_QNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2370 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
2371 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2372 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2373 /*xcpt? */ false, false },
2374 { { /*src2 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
2375 { /*src1 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2376 { /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
2377 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
2378 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2379 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2380 /*xcpt? */ false, false },
2381 { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2382 { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2383 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2384 /*mxcsr:in */ X86_MXCSR_FZ,
2385 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2386 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2387 /*xcpt? */ true, true },
2388 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
2389 { /*src1 */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2390 { /* => */ { FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2391 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2392 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2393 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2394 /*xcpt? */ true, true },
2395 /*
2396 * Overflow, Precision.
2397 */
2398 /*12*/{ { /*src2 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
2399 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2400 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
2401 /*mxcsr:in */ 0,
2402 /*128:out */ X86_MXCSR_OE,
2403 /*256:out */ X86_MXCSR_OE,
2404 /*xcpt? */ true, true },
2405 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2406 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2407 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2408 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2409 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2410 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2411 /*xcpt? */ false, false },
2412 { { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2413 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2414 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2415 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
2416 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2417 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2418 /*xcpt? */ false, false },
2419 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2420 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2421 { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2422 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2423 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2424 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2425 /*xcpt? */ false, false },
2426 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
2427 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2428 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2429 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2430 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2431 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2432 /*xcpt? */ true, true },
2433 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2434 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2435 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2436 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2437 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2438 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2439 /*xcpt? */ true, true },
2440 /*
2441 * Normals.
2442 */
2443 /*18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2444 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2445 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
2446 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2447 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2448 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2449 /*xcpt? */ false, false },
2450 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
2451 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2452 { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2453 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2454 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2455 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2456 /*xcpt? */ false, false },
2457 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2458 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2459 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2460 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2461 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2462 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
2463 /*xcpt? */ false, false },
2464 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
2465 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2466 { /* => */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
2467 /*mxcsr:in */ 0,
2468 /*128:out */ 0,
2469 /*256:out */ 0,
2470 /*xcpt? */ false, false },
2471 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2472 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2473 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2474 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2475 /*128:out */ X86_MXCSR_RC_ZERO,
2476 /*256:out */ X86_MXCSR_RC_ZERO,
2477 /*xcpt? */ false, false },
2478 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2479 { /*src1 */ { FP32_1(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2480 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2481 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2482 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2483 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2484 /*xcpt? */ false, false },
2485 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2486 { /*src1 */ { FP32_1(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2487 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2488 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2489 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2490 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2491 /*xcpt? */ false, false },
2492 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
2493 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2494 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
2495 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2496 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2497 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2498 /*xcpt? */ false, false },
2499 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
2500 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2501 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2502 /*mxcsr:in */ X86_MXCSR_FZ,
2503 /*128:out */ X86_MXCSR_FZ,
2504 /*256:out */ X86_MXCSR_FZ,
2505 /*xcpt? */ false, false },
2506 /*
2507 * Denormals.
2508 */
2509 /*27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
2510 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
2511 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
2512 /*mxcsr:in */ X86_MXCSR_DE,
2513 /*128:out */ X86_MXCSR_DE,
2514 /*256:out */ X86_MXCSR_DE,
2515 /*xcpt? */ true, true },
2516 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
2517 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2518 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
2519 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2520 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2521 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2522 /*xcpt? */ false, false },
2523 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
2524 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
2525 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
2526 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
2527 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
2528 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
2529 /*xcpt? */ true, true },
2530 /** @todo More denormals etc. */
2531 /*
2532 * Invalids.
2533 */
2534 /* QNan, QNan (Masked). */
2535 /*30*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2536 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2537 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2538 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2539 /*128:out */ X86_MXCSR_XCPT_MASK,
2540 /*256:out */ X86_MXCSR_XCPT_MASK,
2541 /*xcpt? */ false, false },
2542 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2543 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2544 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2545 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2546 /*128:out */ X86_MXCSR_XCPT_MASK,
2547 /*256:out */ X86_MXCSR_XCPT_MASK,
2548 /*xcpt? */ false, false },
2549 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2550 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2551 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2552 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2553 /*128:out */ X86_MXCSR_XCPT_MASK,
2554 /*256:out */ X86_MXCSR_XCPT_MASK,
2555 /*xcpt? */ false, false },
2556 /* QNan, SNan (Masked). */
2557 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2558 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2559 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2560 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2561 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2562 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2563 /*xcpt? */ false, false },
2564 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2565 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2566 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2567 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2568 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2569 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2570 /*xcpt? */ false, false },
2571 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2572 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2573 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2574 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2575 /*128:out */ X86_MXCSR_XCPT_MASK,
2576 /*256:out */ X86_MXCSR_XCPT_MASK,
2577 /*xcpt? */ false, false },
2578 /* SNan, QNan (Masked). */
2579 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2580 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2581 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2582 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2583 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2584 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2585 /*xcpt? */ false, false },
2586 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2587 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2588 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2589 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2590 /*128:out */ X86_MXCSR_XCPT_MASK,
2591 /*256:out */ X86_MXCSR_XCPT_MASK,
2592 /*xcpt? */ false, false },
2593 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2594 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2595 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2596 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2597 /*128:out */ X86_MXCSR_XCPT_MASK,
2598 /*256:out */ X86_MXCSR_XCPT_MASK,
2599 /*xcpt? */ false, false },
2600 /* SNan, SNan (Masked). */
2601 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2602 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2603 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2604 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2605 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2606 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2607 /*xcpt? */ false, false },
2608 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2609 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2610 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2611 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2612 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2613 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2614 /*xcpt? */ false, false },
2615 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2616 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2617 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2618 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2619 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2620 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2621 /*xcpt? */ false, false },
2622 /* QNan, Norm FP (Masked). */
2623 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
2624 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2625 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2626 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2627 /*128:out */ X86_MXCSR_XCPT_MASK,
2628 /*256:out */ X86_MXCSR_XCPT_MASK,
2629 /*xcpt? */ false, false },
2630 /* SNan, Norm FP (Masked). */
2631 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
2632 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2633 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2634 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2635 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2636 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
2637 /*xcpt? */ false, false },
2638 /* QNan, QNan (Unmasked). */
2639 /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2640 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2641 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2642 /*mxcsr:in */ 0,
2643 /*128:out */ 0,
2644 /*256:out */ 0,
2645 /*xcpt? */ false, false },
2646 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2647 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2648 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2649 /*mxcsr:in */ 0,
2650 /*128:out */ 0,
2651 /*256:out */ 0,
2652 /*xcpt? */ false, false },
2653 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2654 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2655 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2656 /*mxcsr:in */ 0,
2657 /*128:out */ 0,
2658 /*256:out */ 0,
2659 /*xcpt? */ false, false },
2660
2661 /* QNan, SNan (Unmasked). */
2662 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2663 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2664 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2665 /*mxcsr:in */ 0,
2666 /*128:out */ X86_MXCSR_IE,
2667 /*256:out */ X86_MXCSR_IE,
2668 /*xcpt? */ true, true },
2669 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2670 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2671 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
2672 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2673 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2674 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2675 /*xcpt? */ true, true },
2676 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
2677 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2678 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
2679 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2680 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2681 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2682 /*xcpt? */ false, false },
2683 /* SNan, QNan (Unmasked). */
2684 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2685 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2686 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2687 /*mxcsr:in */ X86_MXCSR_DAZ,
2688 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
2689 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
2690 /*xcpt? */ true, true },
2691 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2692 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2693 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2694 /*mxcsr:in */ X86_MXCSR_RC_UP,
2695 /*128:out */ X86_MXCSR_RC_UP,
2696 /*256:out */ X86_MXCSR_RC_UP,
2697 /*xcpt? */ false, false },
2698 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
2699 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2700 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
2701 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2702 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2703 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2704 /*xcpt? */ false, false },
2705 /* SNan, SNan (Unmasked). */
2706 /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2707 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2708 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2709 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
2710 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
2711 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
2712 /*xcpt? */ true, true },
2713 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2714 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2715 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
2716 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2717 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2718 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2719 /*xcpt? */ true, true },
2720 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
2721 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2722 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
2723 /*mxcsr:in */ 0,
2724 /*128:out */ X86_MXCSR_IE,
2725 /*256:out */ X86_MXCSR_IE,
2726 /*xcpt? */ true, true },
2727 /* QNan, Norm FP (Unmasked). */
2728 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
2729 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2730 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2731 /*mxcsr:in */ X86_MXCSR_FZ,
2732 /*128:out */ X86_MXCSR_FZ,
2733 /*256:out */ X86_MXCSR_FZ,
2734 /*xcpt? */ false, false },
2735 /* SNan, Norm FP (Unmasked). */
2736 /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
2737 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2738 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
2739 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2740 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2741 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2742 /*xcpt? */ true, true },
2743 /** @todo Underflow, Precision; Rounding, FZ etc. */
2744 };
2745
2746 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
2747 {
2748 { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2749 { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2750
2751 { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2752 { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2753 };
2754 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
2755 {
2756 { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2757 { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2758
2759 { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2760 { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2761 };
2762 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
2763 {
2764 { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2765 { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2766
2767 { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2768 { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2769
2770 { bs3CpuInstr4_addss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2771 { bs3CpuInstr4_addss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2772
2773 { bs3CpuInstr4_vaddss_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2774 { bs3CpuInstr4_vaddss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
2775 };
2776
2777 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
2778 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
2779 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
2780 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
2781}
2782
2783
2784/*
2785 * [V]ADDSD.
2786 */
2787BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addsd(uint8_t bMode)
2788{
2789 static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] =
2790 {
2791 /*
2792 * Zero.
2793 */
2794 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2795 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2796 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2797 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2798 /*128:out */ X86_MXCSR_XCPT_MASK,
2799 /*256:out */ X86_MXCSR_XCPT_MASK,
2800 /*xcpt? */ false, false },
2801 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2802 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2803 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2804 /*mxcsr:in */ 0,
2805 /*128:out */ 0,
2806 /*256:out */ 0,
2807 /*xcpt? */ false, false },
2808 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2809 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2810 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
2811 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2812 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2813 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
2814 /*xcpt? */ false, false },
2815 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2816 { /*src1 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
2817 { /* => */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
2818 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2819 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2820 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
2821 /*xcpt? */ false, false },
2822 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2823 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } },
2824 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } },
2825 /*mxcsr:in */ X86_MXCSR_FZ,
2826 /*128:out */ X86_MXCSR_FZ,
2827 /*256:out */ X86_MXCSR_FZ,
2828 /*xcpt? */ false, false },
2829 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2830 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
2831 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(1) } },
2832 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2833 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2834 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
2835 /*xcpt? */ false, false },
2836 /*
2837 * Infinity.
2838 */
2839 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2840 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
2841 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
2842 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
2843 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2844 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
2845 /*xcpt? */ true, true },
2846 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } },
2847 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
2848 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
2849 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
2850 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2851 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2852 /*xcpt? */ true, true },
2853 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2854 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
2855 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
2856 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
2857 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2858 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
2859 /*xcpt? */ false, false },
2860 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2861 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
2862 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
2863 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
2864 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2865 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
2866 /*xcpt? */ false, false },
2867 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
2868 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
2869 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
2870 /*mxcsr:in */ X86_MXCSR_FZ,
2871 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2872 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
2873 /*xcpt? */ true, true },
2874 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
2875 { /*src1 */ { FP64_INF(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2876 { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2877 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2878 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2879 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
2880 /*xcpt? */ true, true },
2881 /*
2882 * Overflow, Precision.
2883 */
2884 /*12*/{ { /*src2 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
2885 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2886 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
2887 /*mxcsr:in */ 0,
2888 /*128:out */ X86_MXCSR_OE,
2889 /*256:out */ X86_MXCSR_OE,
2890 /*xcpt? */ true, true },
2891 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2892 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2893 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2894 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2895 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2896 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2897 /*xcpt? */ false, false },
2898 { { /*src2 */ { FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
2899 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2900 { /* => */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2901 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
2902 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2903 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
2904 /*xcpt? */ false, false },
2905 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2906 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2907 { /* => */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2908 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
2909 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2910 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
2911 /*xcpt? */ false, false },
2912 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
2913 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2914 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2915 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2916 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2917 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2918 /*xcpt? */ true, true },
2919 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
2920 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2921 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
2922 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
2923 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2924 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
2925 /*xcpt? */ true, true },
2926 /*
2927 * Normals.
2928 */
2929 /*18*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_SNAN(0) } },
2930 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_SNAN(1) } },
2931 { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_SNAN(1) } },
2932 /*mxcsr:in */ 0,
2933 /*128:out */ 0,
2934 /*256:out */ 0,
2935 /*xcpt? */ false, false },
2936 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, } },
2937 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, } },
2938 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, } },
2939 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2940 /*128:out */ X86_MXCSR_XCPT_MASK,
2941 /*256:out */ X86_MXCSR_XCPT_MASK,
2942 /*xcpt? */ false, false },
2943 { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
2944 { /*src1 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
2945 { /* => */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
2946 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
2947 /*128:out */ X86_MXCSR_XCPT_MASK,
2948 /*256:out */ X86_MXCSR_XCPT_MASK,
2949 /*xcpt? */ false, false },
2950 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
2951 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
2952 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
2953 /*mxcsr:in */ 0,
2954 /*128:out */ 0,
2955 /*256:out */ 0,
2956 /*xcpt? */ false, false },
2957 { { /*src2 */ { FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
2958 { /*src1 */ { FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
2959 { /* => */ { FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
2960 /*mxcsr:in */ 0,
2961 /*128:out */ 0,
2962 /*256:out */ 0,
2963 /*xcpt? */ false, false },
2964 { { /*src2 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
2965 { /*src1 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(0) } },
2966 { /* => */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(0) } },
2967 /*mxcsr:in */ 0,
2968 /*128:out */ 0,
2969 /*256:out */ 0,
2970 /*xcpt? */ false, false },
2971 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
2972 { /*src1 */ { FP64_1(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2973 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
2974 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2975 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2976 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
2977 /*xcpt? */ false, false },
2978 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
2979 { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
2980 { /* => */ { FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
2981 /*mxcsr:in */ X86_MXCSR_FZ,
2982 /*128:out */ X86_MXCSR_FZ,
2983 /*256:out */ X86_MXCSR_FZ,
2984 /*xcpt? */ false, false },
2985 { { /*src2 */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
2986 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
2987 { /* => */ { FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
2988 /*mxcsr:in */ X86_MXCSR_FZ,
2989 /*128:out */ X86_MXCSR_FZ,
2990 /*256:out */ X86_MXCSR_FZ,
2991 /*xcpt? */ false, false },
2992 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
2993 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
2994 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
2995 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2996 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2997 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
2998 /*xcpt? */ false, false },
2999 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
3000 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V1(1) } },
3001 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V1(1) } },
3002 /*mxcsr:in */ X86_MXCSR_RC_UP,
3003 /*128:out */ X86_MXCSR_RC_UP,
3004 /*256:out */ X86_MXCSR_RC_UP,
3005 /*xcpt? */ false, false },
3006 /*
3007 * Denormals.
3008 */
3009 /*29*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN(0) } },
3010 { /*src1 */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } },
3011 { /* => */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } },
3012 /*mxcsr:in */ 0,
3013 /*128:out */ X86_MXCSR_DE,
3014 /*256:out */ X86_MXCSR_DE,
3015 /*xcpt? */ true, true },
3016 { { /*src2 */ { FP64_0(0), FP64_SNAN(1), FP64_INF(0), FP64_SNAN(0) } },
3017 { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } },
3018 { /* => */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } },
3019 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3020 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
3021 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
3022 /*xcpt? */ false, false },
3023 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
3024 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
3025 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
3026 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3027 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3028 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3029 /*xcpt? */ false, false },
3030 /** @todo More Denormals. */
3031 /*
3032 * Invalids.
3033 */
3034 /* QNan, QNan (Masked). */
3035 /*32*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3036 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3037 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3038 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3039 /*128:out */ X86_MXCSR_XCPT_MASK,
3040 /*256:out */ X86_MXCSR_XCPT_MASK,
3041 /*xcpt? */ false, false },
3042 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } },
3043 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },
3044 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },
3045 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3046 /*128:out */ X86_MXCSR_XCPT_MASK,
3047 /*256:out */ X86_MXCSR_XCPT_MASK,
3048 /*xcpt? */ false, false },
3049 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } },
3050 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },
3051 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },
3052 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3053 /*128:out */ X86_MXCSR_XCPT_MASK,
3054 /*256:out */ X86_MXCSR_XCPT_MASK,
3055 /*xcpt? */ false, false },
3056 /* QNan, SNan (Masked). */
3057 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3058 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },
3059 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },
3060 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3061 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3062 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3063 /*xcpt? */ false, false },
3064 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3065 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3066 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3067 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3068 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3069 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3070 /*xcpt? */ false, false },
3071 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } },
3072 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },
3073 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },
3074 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3075 /*128:out */ X86_MXCSR_XCPT_MASK,
3076 /*256:out */ X86_MXCSR_XCPT_MASK,
3077 /*xcpt? */ false, false },
3078 /* SNan, QNan (Masked). */
3079 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
3080 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },
3081 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },
3082 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3083 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3084 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3085 /*xcpt? */ false, false },
3086 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3087 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3088 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3089 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3090 /*128:out */ X86_MXCSR_XCPT_MASK,
3091 /*256:out */ X86_MXCSR_XCPT_MASK,
3092 /*xcpt? */ false, false },
3093 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3094 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
3095 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
3096 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3097 /*128:out */ X86_MXCSR_XCPT_MASK,
3098 /*256:out */ X86_MXCSR_XCPT_MASK,
3099 /*xcpt? */ false, false },
3100 /* SNan, SNan (Masked). */
3101 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3102 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3103 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3104 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3105 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3106 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3107 /*xcpt? */ false, false },
3108 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3109 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },
3110 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },
3111 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3112 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3113 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3114 /*xcpt? */ false, false },
3115 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3116 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3117 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3118 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3119 /*128:out */ X86_MXCSR_XCPT_MASK,
3120 /*256:out */ X86_MXCSR_XCPT_MASK,
3121 /*xcpt? */ false, false },
3122 /* QNan, Norm FP (Masked). */
3123 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3124 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3125 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3126 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3127 /*128:out */ X86_MXCSR_XCPT_MASK,
3128 /*256:out */ X86_MXCSR_XCPT_MASK,
3129 /*xcpt? */ false, false },
3130 /* SNan, Norm FP (Masked). */
3131 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3132 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3133 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3134 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3135 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3136 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3137 /*xcpt? */ false, false },
3138 /* QNan, QNan (Unmasked). */
3139 /*46*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3140 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3141 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3142 /*mxcsr:in */ 0,
3143 /*128:out */ 0,
3144 /*256:out */ 0,
3145 /*xcpt? */ false, false },
3146 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3147 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3148 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3149 /*mxcsr:in */ 0,
3150 /*128:out */ 0,
3151 /*256:out */ 0,
3152 /*xcpt? */ false, false },
3153 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3154 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },
3155 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },
3156 /*mxcsr:in */ 0,
3157 /*128:out */ 0,
3158 /*256:out */ 0,
3159 /*xcpt? */ false, false },
3160
3161 /* QNan, SNan (Unmasked). */
3162 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3163 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3164 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3165 /*mxcsr:in */ 0,
3166 /*128:out */ X86_MXCSR_IE,
3167 /*256:out */ X86_MXCSR_IE,
3168 /*xcpt? */ true, true },
3169 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3170 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3171 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3172 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3173 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
3174 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
3175 /*xcpt? */ true, true },
3176 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3177 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3178 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3179 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3180 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3181 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3182 /*xcpt? */ false, false },
3183 /* SNan, QNan (Unmasked). */
3184 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3185 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3186 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3187 /*mxcsr:in */ X86_MXCSR_DAZ,
3188 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
3189 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
3190 /*xcpt? */ true, true },
3191 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
3192 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },
3193 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },
3194 /*mxcsr:in */ X86_MXCSR_RC_UP,
3195 /*128:out */ X86_MXCSR_RC_UP,
3196 /*256:out */ X86_MXCSR_RC_UP,
3197 /*xcpt? */ false, false },
3198 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
3199 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
3200 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
3201 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3202 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3203 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3204 /*xcpt? */ false, false },
3205 /* SNan, SNan (Unmasked). */
3206 /*55*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3207 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },
3208 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },
3209 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
3210 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
3211 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
3212 /*xcpt? */ true, true },
3213 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } },
3214 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },
3215 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },
3216 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3217 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3218 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3219 /*xcpt? */ true, true },
3220 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3221 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3222 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },
3223 /*mxcsr:in */ 0,
3224 /*128:out */ 0,
3225 /*256:out */ 0,
3226 /*xcpt? */ false, false },
3227 /* QNan, Norm FP (Unmasked). */
3228 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3229 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3230 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3231 /*mxcsr:in */ X86_MXCSR_FZ,
3232 /*128:out */ X86_MXCSR_FZ,
3233 /*256:out */ X86_MXCSR_FZ,
3234 /*xcpt? */ false, false },
3235 /* SNan, Norm FP (Unmasked). */
3236 /*59*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
3237 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3238 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
3239 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3240 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3241 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
3242 /*xcpt? */ true, true },
3243 /** @todo Underflow, Precision; Rounding, FZ etc. */
3244 };
3245
3246
3247 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3248 {
3249 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3250 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3251
3252 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3253 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3254 };
3255 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3256 {
3257 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3258 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3259
3260 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3261 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3262 };
3263 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3264 {
3265 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3266 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3267
3268 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3269 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3270
3271 { bs3CpuInstr4_addsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3272 { bs3CpuInstr4_addsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3273
3274 { bs3CpuInstr4_vaddsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3275 { bs3CpuInstr4_vaddsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3276 };
3277
3278 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3279 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3280 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3281 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
3282}
3283
3284
3285/*
3286 * [V]HADDPS.
3287 */
3288BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddps(uint8_t bMode)
3289{
3290 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
3291 {
3292 /*
3293 * Zero.
3294 */
3295 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3296 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3297 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3298 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3299 /*128:out */ X86_MXCSR_XCPT_MASK,
3300 /*256:out */ X86_MXCSR_XCPT_MASK,
3301 /*xcpt? */ false, false },
3302 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3303 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3304 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3305 /*mxcsr:in */ 0,
3306 /*128:out */ 0,
3307 /*256:out */ 0,
3308 /*xcpt? */ false, false },
3309 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3310 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3311 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3312 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3313 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3314 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3315 /*xcpt? */ false, false },
3316 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
3317 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
3318 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3319 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3320 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3321 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3322 /*xcpt? */ false, false },
3323 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
3324 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
3325 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3326 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3327 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3328 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3329 /*xcpt? */ false, false },
3330 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3331 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
3332 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
3333 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3334 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3335 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3336 /*xcpt? */ false, false },
3337 /*
3338 * Infinity.
3339 */
3340 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
3341 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3342 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1) } },
3343 /*mxcsr:in */ X86_MXCSR_IM,
3344 /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE,
3345 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE,
3346 /*xcpt? */ false, false },
3347 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3348 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
3349 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
3350 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3351 /*128:out */ X86_MXCSR_XCPT_MASK,
3352 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3353 /*xcpt? */ false, false },
3354 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3355 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
3356 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
3357 /*mxcsr:in */ X86_MXCSR_FZ,
3358 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3359 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3360 /*xcpt? */ true, true },
3361 { { /*src2 */ { FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0) } },
3362 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3363 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0) } },
3364 /*mxcsr:in */ 0,
3365 /*128:out */ 0,
3366 /*256:out */ 0,
3367 /*xcpt? */ false, false },
3368 { { /*src2 */ { FP32_INF(0), FP32_QNAN(1), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } },
3369 { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } },
3370 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } },
3371 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3372 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3373 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3374 /*xcpt? */ false, false },
3375 /*
3376 * Overflow, Precision.
3377 */
3378 /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
3379 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
3380 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3381 /*mxcsr:in */ 0,
3382 /*128:out */ 0,
3383 /*256:out */ X86_MXCSR_OE,
3384 /*xcpt? */ false, true },
3385 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3386 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3387 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3388 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
3389 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3390 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3391 /*xcpt? */ false, false },
3392 { { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
3393 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
3394 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3395 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3396 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3397 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3398 /*xcpt? */ false, false },
3399 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
3400 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1) } },
3401 { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0), FP32_NORM_MAX(0) } },
3402 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
3403 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3404 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3405 /*xcpt? */ false, false },
3406 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
3407 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
3408 { /* => */ { FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(0) } },
3409 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3410 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3411 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3412 /*xcpt? */ false, false },
3413 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
3414 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
3415 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } },
3416 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3417 /*128:out */ X86_MXCSR_RC_ZERO,
3418 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE,
3419 /*xcpt? */ false, true },
3420 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3421 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
3422 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } },
3423 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3424 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3425 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3426 /*xcpt? */ false, false },
3427 /*
3428 * Normals.
3429 */
3430 /*18*/{ { /*src2 */ { FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_V(0, 0, 0x7d)/*0.25*/ } },
3431 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_0(0), FP32_0(0) } },
3432 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x600000, 0x7f)/*1.75*/ } },
3433 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3434 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3435 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3436 /*xcpt? */ false, false },
3437 { { /*src2 */ { FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V4(1), FP32_NORM_V4(0), FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V2(0) } },
3438 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_V3(0), FP32_NORM_V3(1) } },
3439 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3440 /*mxcsr:in */ 0,
3441 /*128:out */ 0,
3442 /*256:out */ 0,
3443 /*xcpt? */ false, false },
3444 { { /*src2 */ { FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/* 7.00*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_0(0), FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
3445 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(1, 0x1ea980, 0x8f)/* -81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/*7*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_1(1) } },
3446 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
3447 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3448 /*128:out */ X86_MXCSR_XCPT_MASK,
3449 /*256:out */ X86_MXCSR_XCPT_MASK,
3450 /*xcpt? */ false, false },
3451 { { /*src2 */ { FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_1(1) } },
3452 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_NORM_V3(1), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_0(0), FP32_1(0) } },
3453 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V3(1), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_NORM_V1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(0), FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1) } },
3454 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3455 /*128:out */ X86_MXCSR_XCPT_MASK,
3456 /*256:out */ X86_MXCSR_XCPT_MASK,
3457 /*xcpt? */ false, false },
3458 { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0), FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0) } },
3459 { /*src1 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } },
3460 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1) } },
3461 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3462 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3463 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3464 /*xcpt? */ false, false },
3465 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } },
3466 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } },
3467 { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } },
3468 /*mxcsr:in */ 0,
3469 /*128:out */ 0,
3470 /*256:out */ 0,
3471 /*xcpt? */ false, false },
3472 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } },
3473 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } },
3474 { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } },
3475 /*mxcsr:in */ X86_MXCSR_FZ,
3476 /*128:out */ X86_MXCSR_FZ,
3477 /*256:out */ X86_MXCSR_FZ,
3478 /*xcpt? */ false, false },
3479 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
3480 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } },
3481 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, 2), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
3482 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3483 /*128:out */ X86_MXCSR_XCPT_MASK,
3484 /*256:out */ X86_MXCSR_XCPT_MASK,
3485 /*xcpt? */ false, false },
3486 /*
3487 * Denormals.
3488 */
3489 /*26*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3490 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3491 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3492 /*mxcsr:in */ 0,
3493 /*128:out */ X86_MXCSR_DE,
3494 /*256:out */ X86_MXCSR_DE,
3495 /*xcpt? */ true, true },
3496 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3497 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
3498 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3499 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3500 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3501 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3502 /*xcpt? */ false, false },
3503 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
3504 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
3505 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), } },
3506 /*mxcsr:in */ X86_MXCSR_DAZ,
3507 /*128:out */ X86_MXCSR_DAZ,
3508 /*256:out */ X86_MXCSR_DAZ,
3509 /*xcpt? */ false, false },
3510 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3511 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3512 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3513 /*mxcsr:in */ 0,
3514 /*128:out */ X86_MXCSR_DE,
3515 /*256:out */ X86_MXCSR_DE,
3516 /*xcpt? */ true, true },
3517 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
3518 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3519 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3520 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3521 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3522 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3523 /*xcpt? */ false, false },
3524 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
3525 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
3526 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
3527 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3528 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3529 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
3530 /*xcpt? */ false, false },
3531 /** @todo Denormals; Rounding, FZ etc. */
3532 /*
3533 * Invalids.
3534 */
3535 /*32*/{ { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3536 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3537 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },
3538 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3539 /*128:out */ X86_MXCSR_XCPT_MASK,
3540 /*256:out */ X86_MXCSR_XCPT_MASK,
3541 /*xcpt? */ false, false },
3542 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },
3543 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3544 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3545 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3546 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3547 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3548 /*xcpt? */ false, false },
3549 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3550 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3551 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3552 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3553 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3554 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3555 /*xcpt? */ false, false },
3556 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3557 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3558 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3559 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3560 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3561 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3562 /*xcpt? */ false, false },
3563 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },
3564 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3565 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3566 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3567 /*128:out */ X86_MXCSR_XCPT_MASK,
3568 /*256:out */ X86_MXCSR_XCPT_MASK,
3569 /*xcpt? */ false, false },
3570 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },
3571 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3572 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3573 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3574 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3575 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3576 /*xcpt? */ false, false },
3577 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3578 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3579 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },
3580 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3581 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3582 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3583 /*xcpt? */ false, false },
3584 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },
3585 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
3586 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },
3587 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
3588 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3589 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3590 /*xcpt? */ true, true },
3591 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3592 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
3593 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3594 /*mxcsr:in */ 0,
3595 /*128:out */ X86_MXCSR_IE,
3596 /*256:out */ X86_MXCSR_IE,
3597 /*xcpt? */ true, true },
3598 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
3599 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
3600 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3601 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3602 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3603 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3604 /*xcpt? */ true, true },
3605 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },
3606 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3607 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },
3608 /*mxcsr:in */ 0,
3609 /*128:out */ 0,
3610 /*256:out */ 0,
3611 /*xcpt? */ false, false },
3612 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },
3613 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
3614 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },
3615 /*mxcsr:in */ X86_MXCSR_RC_UP,
3616 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
3617 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
3618 /*xcpt? */ true, true },
3619 /** @todo Underflow, Precision; Rounding, FZ etc. */
3620 };
3621
3622 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3623 {
3624 { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3625 { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3626
3627 { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3628 { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3629
3630 { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3631 { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3632 };
3633 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
3634 {
3635 { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3636 { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3637
3638 { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3639 { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3640
3641 { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3642 { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3643 };
3644 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
3645 {
3646 { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3647 { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3648
3649 { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3650 { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3651
3652 { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3653 { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3654
3655 { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3656 { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3657
3658 { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3659 { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
3660 };
3661
3662 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
3663 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
3664 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
3665 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
3666}
3667
3668
3669/*
3670 * [V]HADDPD.
3671 */
3672BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddpd(uint8_t bMode)
3673{
3674 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
3675 {
3676 /*
3677 * Zero.
3678 */
3679 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3680 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3681 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3682 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3683 /*128:out */ X86_MXCSR_XCPT_MASK,
3684 /*256:out */ X86_MXCSR_XCPT_MASK,
3685 /*xcpt? */ false, false },
3686 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3687 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3688 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3689 /*mxcsr:in */ 0,
3690 /*128:out */ 0,
3691 /*256:out */ 0,
3692 /*xcpt? */ false, false },
3693 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3694 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3695 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3696 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3697 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3698 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3699 /*xcpt? */ false, false },
3700 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
3701 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
3702 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3703 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3704 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3705 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
3706 /*xcpt? */ false, false },
3707 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
3708 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
3709 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } },
3710 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3711 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3712 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3713 /*xcpt? */ false, false },
3714 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
3715 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
3716 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
3717 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3718 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3719 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3720 /*xcpt? */ false, false },
3721 /*
3722 * Infinity.
3723 */
3724 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
3725 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } },
3726 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } },
3727 /*mxcsr:in */ X86_MXCSR_IM,
3728 /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE,
3729 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE,
3730 /*xcpt? */ false, false },
3731 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } },
3732 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } },
3733 { /* => */ { FP64_0(0), FP64_0(0), FP64_QNAN(1), FP64_INF(1) } },
3734 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3735 /*128:out */ X86_MXCSR_XCPT_MASK,
3736 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3737 /*xcpt? */ false, false },
3738 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
3739 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } },
3740 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_QNAN(1), FP64_QNAN(1) } },
3741 /*mxcsr:in */ X86_MXCSR_FZ,
3742 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3743 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
3744 /*xcpt? */ true, true },
3745 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(0), FP64_0(0) } },
3746 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_0(0) } },
3747 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
3748 /*mxcsr:in */ 0,
3749 /*128:out */ 0,
3750 /*256:out */ 0,
3751 /*xcpt? */ false, false },
3752 { { /*src2 */ { FP64_INF(0), FP64_QNAN(1), FP64_INF(1), FP64_QNAN(0) } },
3753 { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_INF(1), FP64_QNAN(0) } },
3754 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } },
3755 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3756 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3757 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3758 /*xcpt? */ false, false },
3759 /*
3760 * Overflow, Precision.
3761 */
3762 /*11*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
3763 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
3764 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3765 /*mxcsr:in */ 0,
3766 /*128:out */ 0,
3767 /*256:out */ X86_MXCSR_OE,
3768 /*xcpt? */ false, true },
3769 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
3770 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
3771 { /* => */ { FP64_INF(1), FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1), FP64_INF(0), } },
3772 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
3773 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3774 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
3775 /*xcpt? */ false, false },
3776 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } },
3777 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
3778 { /* => */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(1), FP64_0(0) } },
3779 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3780 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3781 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3782 /*xcpt? */ false, false },
3783 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } },
3784 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
3785 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },
3786 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
3787 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3788 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3789 /*xcpt? */ false, false },
3790 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } },
3791 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
3792 { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } },
3793 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
3794 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3795 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
3796 /*xcpt? */ false, false },
3797 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
3798 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } },
3799 { /* => */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_V(0, 0, 2), FP64_NORM_MAX(0) } },
3800 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3801 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3802 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3803 /*xcpt? */ false, false },
3804 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
3805 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
3806 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2), FP64_0(0) } },
3807 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
3808 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3809 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
3810 /*xcpt? */ false, false },
3811 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
3812 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
3813 { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
3814 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
3815 /*128:out */ X86_MXCSR_RC_ZERO,
3816 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE,
3817 /*xcpt? */ false, true },
3818 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } },
3819 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },
3820 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } },
3821 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
3822 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3823 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
3824 /*xcpt? */ false, false },
3825 /*
3826 * Normals.
3827 */
3828 /*20*/{ { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_V2(1), FP64_NORM_V2(0) } },
3829 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_V1(1) } },
3830 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
3831 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3832 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3833 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3834 /*xcpt? */ false, false },
3835 { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/* 55*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/ } },
3836 { /*src1 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0, 0x408)/*512*/, FP64_V(0, 0xd6f3458800000, 0x41c)/* 987654321*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/ } },
3837 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/, FP64_V(0, 0xd6f3426800000, 0x41c)/* 987654221*/, FP64_0(0) } },
3838 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3839 /*128:out */ X86_MXCSR_XCPT_MASK,
3840 /*256:out */ X86_MXCSR_XCPT_MASK,
3841 /*xcpt? */ false, false },
3842 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_NORM_V2(1), FP64_NORM_V2(0) } },
3843 { /*src1 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.50*/, FP64_NORM_V0(1), FP64_NORM_V0(0) } },
3844 { /* => */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0) } },
3845 /*mxcsr:in */ 0,
3846 /*128:out */ 0,
3847 /*256:out */ 0,
3848 /*xcpt? */ false, false },
3849 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_NORM_V3(1), FP64_NORM_V3(0) } },
3850 { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_V1(1) } },
3851 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
3852 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3853 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3854 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3855 /*xcpt? */ false, false },
3856 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },
3857 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
3858 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2), FP64_V(1, 0, 2) } },
3859 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3860 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3861 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
3862 /*xcpt? */ false, false },
3863 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },
3864 { /*src1 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0), FP64_NORM_V0(1) } },
3865 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2) } },
3866 /*mxcsr:in */ X86_MXCSR_RC_UP,
3867 /*128:out */ X86_MXCSR_RC_UP,
3868 /*256:out */ X86_MXCSR_RC_UP,
3869 /*xcpt? */ false, false },
3870 /*
3871 * Denormals.
3872 */
3873 /*26*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } },
3874 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } },
3875 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3876 /*mxcsr:in */ 0,
3877 /*128:out */ X86_MXCSR_DE,
3878 /*256:out */ X86_MXCSR_DE,
3879 /*xcpt? */ true, true },
3880 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
3881 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } },
3882 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
3883 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3884 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3885 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
3886 /*xcpt? */ false, false },
3887 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3888 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
3889 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
3890 /*mxcsr:in */ 0,
3891 /*128:out */ X86_MXCSR_DE,
3892 /*256:out */ X86_MXCSR_DE,
3893 /*xcpt? */ true, true },
3894 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } },
3895 { /*src1 */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0) } },
3896 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } },
3897 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
3898 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
3899 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
3900 /*xcpt? */ false, false },
3901 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
3902 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
3903 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } },
3904 /*mxcsr:in */ 0,
3905 /*128:out */ 0,
3906 /*256:out */ X86_MXCSR_DE,
3907 /*xcpt? */ false, true },
3908 /*
3909 * Invalids.
3910 */
3911 /*31*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3912 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3913 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3914 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3915 /*128:out */ X86_MXCSR_XCPT_MASK,
3916 /*256:out */ X86_MXCSR_XCPT_MASK,
3917 /*xcpt? */ false, false },
3918 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3919 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3920 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3921 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3922 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3923 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3924 /*xcpt? */ false, false },
3925 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3926 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3927 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3928 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3929 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3930 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3931 /*xcpt? */ false, false },
3932 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } },
3933 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } },
3934 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3935 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3936 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3937 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3938 /*xcpt? */ false, false },
3939 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3940 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } },
3941 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3942 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3943 /*128:out */ X86_MXCSR_XCPT_MASK,
3944 /*256:out */ X86_MXCSR_XCPT_MASK,
3945 /*xcpt? */ false, false },
3946 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } },
3947 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } },
3948 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3949 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
3950 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3951 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
3952 /*xcpt? */ false, false },
3953 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3954 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3955 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } },
3956 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3957 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3958 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
3959 /*xcpt? */ false, false },
3960 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3961 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } },
3962 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3963 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
3964 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3965 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3966 /*xcpt? */ true, true },
3967 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } },
3968 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } },
3969 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3970 /*mxcsr:in */ 0,
3971 /*128:out */ X86_MXCSR_IE,
3972 /*256:out */ X86_MXCSR_IE,
3973 /*xcpt? */ true, true },
3974 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } },
3975 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } },
3976 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3977 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
3978 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3979 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
3980 /*xcpt? */ true, true },
3981 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3982 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } },
3983 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
3984 /*mxcsr:in */ 0,
3985 /*128:out */ 0,
3986 /*256:out */ 0,
3987 /*xcpt? */ false, false },
3988 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0), } },
3989 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1), } },
3990 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
3991 /*mxcsr:in */ X86_MXCSR_RC_UP,
3992 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
3993 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
3994 /*xcpt? */ true, true },
3995 /** @todo Underflow, Precision; Rounding, FZ etc. */
3996 };
3997
3998 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
3999 {
4000 { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4001 { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4002
4003 { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4004 { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4005
4006 { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4007 { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4008 };
4009 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4010 {
4011 { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4012 { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4013
4014 { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4015 { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4016
4017 { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4018 { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4019 };
4020 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4021 {
4022 { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4023 { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4024
4025 { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4026 { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4027
4028 { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4029 { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4030
4031 { bs3CpuInstr4_haddpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4032 { bs3CpuInstr4_haddpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4033
4034 { bs3CpuInstr4_vhaddpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4035 { bs3CpuInstr4_vhaddpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4036 };
4037
4038 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4039 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4040 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4041 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4042}
4043
4044
4045/*
4046 * [V]SUBPS.
4047 */
4048BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subps(uint8_t bMode)
4049{
4050 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
4051 {
4052 /*
4053 * Zero.
4054 */
4055 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4056 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4057 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4058 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4059 /*128:out */ X86_MXCSR_XCPT_MASK,
4060 /*256:out */ X86_MXCSR_XCPT_MASK,
4061 /*xcpt? */ false, false },
4062 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4063 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4064 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4065 /*mxcsr:in */ 0,
4066 /*128:out */ 0,
4067 /*256:out */ 0,
4068 /*xcpt? */ false, false },
4069 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4070 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4071 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4072 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4073 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4074 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4075 /*xcpt? */ false, false },
4076 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4077 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
4078 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4079 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4080 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4081 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4082 /*xcpt? */ false, false },
4083 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
4084 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
4085 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
4086 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4087 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4088 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4089 /*xcpt? */ false, false },
4090 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
4091 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
4092 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4093 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS,
4094 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS,
4095 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS,
4096 /*xcpt? */ false, false },
4097 /*
4098 * Infinity.
4099 */
4100 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4101 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
4102 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
4103 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4104 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4105 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4106 /*xcpt? */ false, false },
4107 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4108 { /*src1 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4109 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
4110 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4111 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4112 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4113 /*xcpt? */ false, false },
4114 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4115 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4116 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
4117 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4118 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4119 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4120 /*xcpt? */ false, false },
4121 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
4122 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
4123 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
4124 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4125 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4126 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4127 /*xcpt? */ false, false },
4128 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
4129 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
4130 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
4131 /*mxcsr:in */ X86_MXCSR_FZ,
4132 /*128:out */ X86_MXCSR_FZ,
4133 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
4134 /*xcpt? */ false, true },
4135 { { /*src2 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
4136 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
4137 { /* => */ { FP32_INF(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
4138 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4139 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4140 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4141 /*xcpt? */ true, true },
4142 /*
4143 * Overflow, Precision.
4144 */
4145 /*12*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4146 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
4147 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4148 /*mxcsr:in */ 0,
4149 /*128:out */ 0,
4150 /*256:out */ X86_MXCSR_PE,
4151 /*xcpt? */ false, true },
4152 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
4153 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
4154 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0) } },
4155 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
4156 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4157 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4158 /*xcpt? */ false, false },
4159 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
4160 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
4161 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4162 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
4163 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4164 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4165 /*xcpt? */ false, false },
4166 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, 2), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
4167 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
4168 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0) } },
4169 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
4170 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4171 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4172 /*xcpt? */ false, false },
4173 { { /*src2 */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },
4174 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },
4175 { /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
4176 /*mxcsr:in */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
4177 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4178 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4179 /*xcpt? */ false, false },
4180 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4181 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4182 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } },
4183 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4184 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4185 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
4186 /*xcpt? */ false, false },
4187 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4188 { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4189 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4190 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4191 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4192 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4193 /*xcpt? */ true, true },
4194 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
4195 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
4196 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4197 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
4198 /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
4199 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
4200 /*xcpt? */ true, true },
4201 /*
4202 * Normals.
4203 */
4204 /*20*/{ { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_0(0), FP32_0(1), FP32_V(0, 0x400000, 0x7e)/* 0.75*/ } },
4205 { /*src1 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_0(0), FP32_0(0), FP32_0(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(0), FP32_0(1), FP32_V(0, 0, 0x7e)/* 0.50*/ } },
4206 { /* => */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/*-0.25*/ } },
4207 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4208 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4209 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4210 /*xcpt? */ false, false },
4211 { { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
4212 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
4213 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4214 /*mxcsr:in */ 0,
4215 /*128:out */ 0,
4216 /*256:out */ 0,
4217 /*xcpt? */ false, false },
4218 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x2514d6, 0x93)/* 1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_0(0) } },
4219 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(1, 0x7c9000, 0x88)/* -1010.25*/, FP32_1(0) /* 1.00*/, FP32_0(0) } },
4220 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_0(0), FP32_V(1, 0x780000, 0x84)/*-62*/, FP32_V(1, 0x253468, 0x93)/*-1353357.00*/, FP32_V(1, 0x524000, 0x86)/*210.25*/, FP32_0(0) } },
4221 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ,
4222 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ,
4223 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ,
4224 /*xcpt? */ false, false },
4225 { { /*src2 */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0) } },
4226 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/* 12345678*/, FP32_0(0), FP32_1(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_1(0), FP32_1(0) } },
4227 { /* => */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_V(0, 0x3c614e, 0x97)/* 24691356*/, FP32_0(1), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } },
4228 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
4229 /*128:out */ X86_MXCSR_RC_DOWN,
4230 /*256:out */ X86_MXCSR_RC_DOWN,
4231 /*xcpt? */ false, false },
4232 { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } },
4233 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_0(1), FP32_0(0) } },
4234 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0) } },
4235 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4236 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4237 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4238 /*xcpt? */ false, false },
4239 { { /*src2 */ { FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0) } },
4240 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
4241 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(0), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(0) } },
4242 /*mxcsr:in */ X86_MXCSR_RC_UP,
4243 /*128:out */ X86_MXCSR_RC_UP,
4244 /*256:out */ X86_MXCSR_RC_UP,
4245 /*xcpt? */ false, false },
4246 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },
4247 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } },
4248 { /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0) } },
4249 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4250 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4251 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4252 /*xcpt? */ false, false },
4253 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
4254 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },
4255 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, 2), FP32_V(1, 0, 2), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } },
4256 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4257 /*128:out */ X86_MXCSR_XCPT_MASK,
4258 /*256:out */ X86_MXCSR_XCPT_MASK,
4259 /*xcpt? */ false, false },
4260 /*
4261 * Denormals.
4262 */
4263 /*28*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4264 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
4265 { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
4266 /*mxcsr:in */ 0,
4267 /*128:out */ X86_MXCSR_DE,
4268 /*256:out */ X86_MXCSR_DE,
4269 /*xcpt? */ true, true },
4270 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4271 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
4272 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
4273 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4274 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
4275 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
4276 /*xcpt? */ false, false },
4277 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
4278 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
4279 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4280 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4281 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4282 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
4283 /*xcpt? */ false, false },
4284 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4285 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4286 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4287 /*mxcsr:in */ 0,
4288 /*128:out */ X86_MXCSR_DE,
4289 /*256:out */ X86_MXCSR_DE,
4290 /*xcpt? */ true, true },
4291 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
4292 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4293 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0) } },
4294 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4295 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
4296 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
4297 /*xcpt? */ false, false },
4298 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0) } },
4299 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } },
4300 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4301 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4302 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4303 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4304 /*xcpt? */ false, false },
4305 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
4306 /*
4307 * Invalids.
4308 */
4309 /*34*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4310 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4311 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4312 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4313 /*128:out */ X86_MXCSR_XCPT_MASK,
4314 /*256:out */ X86_MXCSR_XCPT_MASK,
4315 /*xcpt? */ false, false },
4316 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4317 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4318 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4319 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4320 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4321 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4322 /*xcpt? */ false, false },
4323 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
4324 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4325 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4326 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4327 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4328 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4329 /*xcpt? */ false, false },
4330 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4331 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
4332 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
4333 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4334 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4335 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4336 /*xcpt? */ false, false },
4337 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4338 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4339 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4340 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4341 /*128:out */ X86_MXCSR_XCPT_MASK,
4342 /*256:out */ X86_MXCSR_XCPT_MASK,
4343 /*xcpt? */ false, false },
4344 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
4345 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4346 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4347 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4348 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4349 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4350 /*xcpt? */ false, false },
4351 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4352 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4353 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4354 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4355 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4356 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4357 /*xcpt? */ false, false },
4358 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
4359 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
4360 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
4361 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4362 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4363 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4364 /*xcpt? */ true, true },
4365 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
4366 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4367 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
4368 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4369 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4370 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4371 /*xcpt? */ true, true },
4372 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
4373 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
4374 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
4375 /*mxcsr:in */ X86_MXCSR_RC_UP,
4376 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
4377 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
4378 /*xcpt? */ true, true },
4379 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4380 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4381 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4382 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
4383 /*128:out */ X86_MXCSR_RC_DOWN,
4384 /*256:out */ X86_MXCSR_RC_DOWN,
4385 /*xcpt? */ false, false },
4386 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
4387 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
4388 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
4389 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4390 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4391 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4392 /*xcpt? */ true, true },
4393 };
4394
4395 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4396 {
4397 { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4398 { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4399
4400 { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4401 { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4402
4403 { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4404 { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4405 };
4406 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4407 {
4408 { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4409 { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4410
4411 { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4412 { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4413
4414 { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4415 { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4416 };
4417 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4418 {
4419 { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4420 { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4421
4422 { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4423 { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4424
4425 { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4426 { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4427
4428 { bs3CpuInstr4_subps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4429 { bs3CpuInstr4_subps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4430
4431 { bs3CpuInstr4_vsubps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4432 { bs3CpuInstr4_vsubps_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4433 { bs3CpuInstr4_vsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4434 { bs3CpuInstr4_vsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4435 };
4436
4437 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4438 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4439 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4440 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4441}
4442
4443
4444/*
4445 * [V]SUBPD.
4446 */
4447BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subpd(uint8_t bMode)
4448{
4449 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
4450 {
4451 /*
4452 * Zero.
4453 */
4454 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4455 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4456 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4457 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4458 /*128:out */ X86_MXCSR_XCPT_MASK,
4459 /*256:out */ X86_MXCSR_XCPT_MASK,
4460 /*xcpt? */ false, false },
4461 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4462 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4463 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4464 /*mxcsr:in */ 0,
4465 /*128:out */ 0,
4466 /*256:out */ 0,
4467 /*xcpt? */ false, false },
4468 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4469 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4470 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4471 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4472 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4473 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4474 /*xcpt? */ false, false },
4475 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
4476 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
4477 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4478 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4479 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4480 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4481 /*xcpt? */ false, false },
4482 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
4483 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
4484 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
4485 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4486 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4487 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4488 /*xcpt? */ false, false },
4489 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4490 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } },
4491 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
4492 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4493 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4494 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4495 /*xcpt? */ false, false },
4496 /*
4497 * Infinity.
4498 */
4499 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_INF(1) } },
4500 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
4501 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
4502 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4503 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4504 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4505 /*xcpt? */ false, false },
4506 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } },
4507 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
4508 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(0), FP64_QNAN(1) } },
4509 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4510 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4511 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4512 /*xcpt? */ false, false },
4513 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
4514 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
4515 { /* => */ { FP64_QNAN(1), FP64_INF(1), FP64_INF(0), FP64_QNAN(1) } },
4516 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4517 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4518 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4519 /*xcpt? */ false, false },
4520 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } },
4521 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(1) } },
4522 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_QNAN(1) } },
4523 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4524 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4525 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4526 /*xcpt? */ false, false },
4527 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } },
4528 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } },
4529 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_QNAN(1) } },
4530 /*mxcsr:in */ X86_MXCSR_FZ,
4531 /*128:out */ X86_MXCSR_FZ,
4532 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
4533 /*xcpt? */ false, true },
4534 { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
4535 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
4536 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_0(1), FP64_0(1) } },
4537 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4538 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4539 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4540 /*xcpt? */ true, true },
4541 /*
4542 * Overflow, Precision.
4543 */
4544 /*12*/{ { /*src2 */ { FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
4545 { /*src1 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
4546 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4547 /*mxcsr:in */ 0,
4548 /*128:out */ X86_MXCSR_PE,
4549 /*256:out */ X86_MXCSR_PE,
4550 /*xcpt? */ true, true },
4551 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
4552 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
4553 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4554 /*mxcsr:in */ 0,
4555 /*128:out */ 0,
4556 /*256:out */ X86_MXCSR_PE,
4557 /*xcpt? */ false, true },
4558 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
4559 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
4560 { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } },
4561 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
4562 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4563 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4564 /*xcpt? */ false, false },
4565 { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } },
4566 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
4567 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } },
4568 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
4569 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
4570 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
4571 /*xcpt? */ false, false },
4572 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },
4573 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
4574 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } },
4575 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
4576 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4577 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4578 /*xcpt? */ false, false },
4579 { { /*src2 */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } },
4580 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },
4581 { /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
4582 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
4583 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4584 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4585 /*xcpt? */ false, false },
4586 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
4587 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
4588 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
4589 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4590 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4591 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4592 /*xcpt? */ false, false },
4593 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
4594 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
4595 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4596 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
4597 /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4598 /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4599 /*xcpt? */ true, true },
4600 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
4601 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
4602 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4603 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4604 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4605 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4606 /*xcpt? */ true, true },
4607 /*
4608 * Normals.
4609 */
4610 /*21*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
4611 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
4612 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4613 /*mxcsr:in */ 0,
4614 /*128:out */ 0,
4615 /*256:out */ 0,
4616 /*xcpt? */ false, false },
4617 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/ } },
4618 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0, 0x409)/*1024*/ } },
4619 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(1, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(1, 0, 0x408)/* 512*/ } },
4620 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4621 /*128:out */ X86_MXCSR_XCPT_MASK,
4622 /*256:out */ X86_MXCSR_XCPT_MASK,
4623 /*xcpt? */ false, false },
4624 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } },
4625 { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
4626 { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
4627 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4628 /*128:out */ X86_MXCSR_XCPT_MASK,
4629 /*256:out */ X86_MXCSR_XCPT_MASK,
4630 /*xcpt? */ false, false },
4631 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } },
4632 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_0(0), FP64_0(0) } },
4633 { /* => */ { FP64_1(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
4634 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4635 /*128:out */ X86_MXCSR_XCPT_MASK,
4636 /*256:out */ X86_MXCSR_XCPT_MASK,
4637 /*xcpt? */ false, false },
4638 { { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_NORM_SAFE_INT_MAX(0) } },
4639 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0) } },
4640 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } },
4641 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
4642 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
4643 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
4644 /*xcpt? */ false, false },
4645 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
4646 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },
4647 { /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, 2) } },
4648 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4649 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4650 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4651 /*xcpt? */ false, false },
4652 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } },
4653 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } },
4654 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, 2) } },
4655 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
4656 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
4657 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
4658 /*xcpt? */ false, false },
4659 /*
4660 * Denormals.
4661 */
4662 /*28*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4663 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4664 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4665 /*mxcsr:in */ 0,
4666 /*128:out */ X86_MXCSR_DE,
4667 /*256:out */ X86_MXCSR_DE,
4668 /*xcpt? */ true, true },
4669 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4670 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
4671 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4672 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
4673 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
4674 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
4675 /*xcpt? */ false, false },
4676 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
4677 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
4678 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
4679 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4680 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4681 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
4682 /*xcpt? */ false, false },
4683 /** @todo More denormals. */
4684 /*
4685 * Invalids.
4686 */
4687 /*31*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V0) } },
4688 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4689 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4690 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4691 /*128:out */ X86_MXCSR_XCPT_MASK,
4692 /*256:out */ X86_MXCSR_XCPT_MASK,
4693 /*xcpt? */ false, false },
4694 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4695 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0) } },
4696 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) } },
4697 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4698 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4699 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4700 /*xcpt? */ false, false },
4701 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4702 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4703 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4704 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4705 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4706 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4707 /*xcpt? */ false, false },
4708 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4709 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
4710 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
4711 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4712 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4713 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4714 /*xcpt? */ false, false },
4715 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4716 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
4717 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4718 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4719 /*128:out */ X86_MXCSR_XCPT_MASK,
4720 /*256:out */ X86_MXCSR_XCPT_MASK,
4721 /*xcpt? */ false, false },
4722 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4723 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
4724 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4725 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4726 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4727 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
4728 /*xcpt? */ false, false },
4729 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) , FP64_QNAN_V(0, FP64_FRAC_V1) } },
4730 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4731 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4732 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4733 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4734 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4735 /*xcpt? */ false, false },
4736 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
4737 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
4738 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
4739 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4740 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4741 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4742 /*xcpt? */ true, true },
4743 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
4744 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4745 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4746 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4747 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
4748 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
4749 /*xcpt? */ true, true },
4750 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4751 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
4752 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
4753 /*mxcsr:in */ X86_MXCSR_RC_UP,
4754 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
4755 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
4756 /*xcpt? */ true, true },
4757 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4758 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
4759 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
4760 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
4761 /*128:out */ X86_MXCSR_RC_DOWN,
4762 /*256:out */ X86_MXCSR_RC_DOWN,
4763 /*xcpt? */ false, false },
4764 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
4765 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
4766 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
4767 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4768 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4769 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
4770 /*xcpt? */ true, true },
4771 /** @todo Underflow, Precision; Rounding, FZ etc. */
4772 };
4773
4774 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
4775 {
4776 { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4777 { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4778
4779 { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4780 { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4781
4782 { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4783 { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4784 };
4785 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
4786 {
4787 { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4788 { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4789
4790 { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4791 { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4792
4793 { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4794 { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4795 };
4796 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
4797 {
4798 { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4799 { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4800
4801 { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4802 { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4803
4804 { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4805 { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4806
4807 { bs3CpuInstr4_subpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4808 { bs3CpuInstr4_subpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4809
4810 { bs3CpuInstr4_vsubpd_XMM8_XMM9_XMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4811 { bs3CpuInstr4_vsubpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4812 { bs3CpuInstr4_vsubpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4813 { bs3CpuInstr4_vsubpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
4814 };
4815
4816 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
4817 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
4818 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
4819 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
4820}
4821
4822
4823/*
4824 * [V]SUBSS.
4825 */
4826BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subss(uint8_t bMode)
4827{
4828 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
4829 {
4830 /*
4831 * Zero.
4832 */
4833 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4834 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4835 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4836 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4837 /*128:out */ X86_MXCSR_XCPT_MASK,
4838 /*256:out */ X86_MXCSR_XCPT_MASK,
4839 /*xcpt? */ false, false },
4840 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4841 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4842 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4843 /*mxcsr:in */ 0,
4844 /*128:out */ 0,
4845 /*256:out */ 0,
4846 /*xcpt? */ false, false },
4847 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4848 { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4849 { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4850 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4851 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4852 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
4853 /*xcpt? */ false, false },
4854 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4855 { /*src1 */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4856 { /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4857 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4858 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4859 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
4860 /*xcpt? */ false, false },
4861 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4862 { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4863 { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4864 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4865 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4866 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4867 /*xcpt? */ false, false },
4868 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4869 { /*src1 */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4870 { /* => */ { FP32_0(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4871 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4872 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4873 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
4874 /*xcpt? */ false, false },
4875 /*
4876 * Infinity.
4877 */
4878 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4879 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4880 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4881 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4882 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4883 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
4884 /*xcpt? */ false, false },
4885 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4886 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4887 { /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4888 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM),
4889 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
4890 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
4891 /*xcpt? */ true, true },
4892 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4893 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4894 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4895 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
4896 /*128:out */ X86_MXCSR_XCPT_MASK,
4897 /*256:out */ X86_MXCSR_XCPT_MASK,
4898 /*xcpt? */ false, false },
4899 { { /*src2 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
4900 { /*src1 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4901 { /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
4902 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
4903 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4904 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
4905 /*xcpt? */ false, false },
4906 { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
4907 { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4908 { /* => */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
4909 /*mxcsr:in */ X86_MXCSR_FZ,
4910 /*128:out */ X86_MXCSR_FZ,
4911 /*256:out */ X86_MXCSR_FZ,
4912 /*xcpt? */ false, false },
4913 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
4914 { /*src1 */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
4915 { /* => */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
4916 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4917 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4918 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
4919 /*xcpt? */ false, false },
4920 /*
4921 * Overflow, Precision.
4922 */
4923 /*12*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
4924 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
4925 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4926 /*mxcsr:in */ 0,
4927 /*128:out */ 0,
4928 /*256:out */ X86_MXCSR_PE,
4929 /*xcpt? */ false, true },
4930 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
4931 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
4932 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0) } },
4933 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
4934 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4935 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4936 /*xcpt? */ false, false },
4937 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
4938 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
4939 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
4940 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
4941 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4942 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4943 /*xcpt? */ false, false },
4944 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4945 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4946 { /* => */ { FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4947 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
4948 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4949 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4950 /*xcpt? */ false, false },
4951 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4952 { /*src1 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4953 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4954 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
4955 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
4956 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
4957 /*xcpt? */ false, false },
4958 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4959 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4960 { /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4961 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
4962 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4963 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
4964 /*xcpt? */ false, false },
4965 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4966 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4967 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4968 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4969 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4970 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4971 /*xcpt? */ true, true },
4972 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4973 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4974 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4975 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4976 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4977 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4978 /*xcpt? */ true, true },
4979 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4980 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4981 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
4982 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
4983 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4984 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
4985 /*xcpt? */ true, true },
4986 /*
4987 * Normals.
4988 */
4989 /*21*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
4990 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
4991 { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
4992 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4993 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4994 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
4995 /*xcpt? */ false, false },
4996 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
4997 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4998 { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
4999 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5000 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5001 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5002 /*xcpt? */ false, false },
5003 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5004 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5005 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5006 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5007 /*128:out */ X86_MXCSR_XCPT_MASK,
5008 /*256:out */ X86_MXCSR_XCPT_MASK,
5009 /*xcpt? */ false, false },
5010 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
5011 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5012 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
5013 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5014 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5015 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5016 /*xcpt? */ false, false },
5017 { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
5018 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5019 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5020 /*mxcsr:in */ 0,
5021 /*128:out */ 0,
5022 /*256:out */ 0,
5023 /*xcpt? */ false, false },
5024 { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
5025 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5026 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5027 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5028 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5029 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5030 /*xcpt? */ false, false },
5031 { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
5032 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5033 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5034 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5035 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5036 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5037 /*xcpt? */ false, false },
5038 { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
5039 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5040 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
5041 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5042 /*128:out */ X86_MXCSR_XCPT_MASK,
5043 /*256:out */ X86_MXCSR_XCPT_MASK,
5044 /*xcpt? */ false, false },
5045 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
5046 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
5047 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
5048 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
5049 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
5050 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
5051 /*xcpt? */ false, false },
5052 /*
5053 * Denormals.
5054 */
5055 /*27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
5056 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
5057 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
5058 /*mxcsr:in */ 0,
5059 /*128:out */ X86_MXCSR_DE,
5060 /*256:out */ X86_MXCSR_DE,
5061 /*xcpt? */ true, true },
5062 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
5063 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
5064 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
5065 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
5066 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
5067 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
5068 /*xcpt? */ false, false },
5069 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
5070 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
5071 { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
5072 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5073 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5074 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
5075 /*xcpt? */ false, false },
5076 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */
5077 };
5078
5079 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
5080 {
5081 { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5082 { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5083
5084 { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5085 { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5086 };
5087 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
5088 {
5089 { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5090 { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5091
5092 { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5093 { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5094 };
5095 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
5096 {
5097 { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5098 { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5099
5100 { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5101 { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5102
5103 { bs3CpuInstr4_subss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5104 { bs3CpuInstr4_subss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5105
5106 { bs3CpuInstr4_vsubss_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5107 { bs3CpuInstr4_vsubss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5108 };
5109
5110 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5111 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
5112 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5113 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
5114}
5115
5116
5117/*
5118 * [V]SUBSD.
5119 */
5120BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subsd(uint8_t bMode)
5121{
5122 static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] =
5123 {
5124 /*
5125 * Zero.
5126 */
5127 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5128 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5129 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5130 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5131 /*128:out */ X86_MXCSR_XCPT_MASK,
5132 /*256:out */ X86_MXCSR_XCPT_MASK,
5133 /*xcpt? */ false, false },
5134 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
5135 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
5136 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
5137 /*mxcsr:in */ 0,
5138 /*128:out */ 0,
5139 /*256:out */ 0,
5140 /*xcpt? */ false, false },
5141 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
5142 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
5143 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
5144 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5145 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5146 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5147 /*xcpt? */ false, false },
5148 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
5149 { /*src1 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
5150 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
5151 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5152 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5153 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5154 /*xcpt? */ false, false },
5155 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
5156 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } },
5157 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } },
5158 /*mxcsr:in */ X86_MXCSR_FZ,
5159 /*128:out */ X86_MXCSR_FZ,
5160 /*256:out */ X86_MXCSR_FZ,
5161 /*xcpt? */ false, false },
5162 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
5163 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
5164 { /* => */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(1) } },
5165 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
5166 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
5167 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
5168 /*xcpt? */ false, false },
5169 /*
5170 * Infinity.
5171 */
5172 /* 6*/{ { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
5173 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
5174 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5175 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
5176 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
5177 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
5178 /*xcpt? */ true, true },
5179 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } },
5180 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
5181 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
5182 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
5183 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5184 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5185 /*xcpt? */ true, true },
5186 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
5187 { /*src1 */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
5188 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
5189 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
5190 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
5191 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
5192 /*xcpt? */ false, false },
5193 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
5194 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
5195 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
5196 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
5197 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
5198 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
5199 /*xcpt? */ false, false },
5200 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
5201 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5202 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5203 /*mxcsr:in */ X86_MXCSR_FZ,
5204 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
5205 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
5206 /*xcpt? */ true, true },
5207 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
5208 { /*src1 */ { FP64_INF(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
5209 { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
5210 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5211 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5212 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5213 /*xcpt? */ true, true },
5214 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
5215 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5216 { /* => */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5217 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5218 /*128:out */ X86_MXCSR_XCPT_MASK,
5219 /*256:out */ X86_MXCSR_XCPT_MASK,
5220 /*xcpt? */ false, false },
5221 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },
5222 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5223 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5224 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5225 /*128:out */ X86_MXCSR_XCPT_MASK,
5226 /*256:out */ X86_MXCSR_XCPT_MASK,
5227 /*xcpt? */ false, false },
5228 /*
5229 * Overflow, Precision.
5230 */
5231 /*14*/{ { /*src2 */ { FP64_NORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },
5232 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5233 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
5234 /*mxcsr:in */ 0,
5235 /*128:out */ X86_MXCSR_PE,
5236 /*256:out */ X86_MXCSR_PE,
5237 /*xcpt? */ true, true },
5238 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V3(1) } },
5239 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } },
5240 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } },
5241 /*mxcsr:in */ 0,
5242 /*128:out */ X86_MXCSR_PE,
5243 /*256:out */ X86_MXCSR_PE,
5244 /*xcpt? */ true, true },
5245 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
5246 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
5247 { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } },
5248 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
5249 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
5250 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
5251 /*xcpt? */ false, false },
5252 { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } },
5253 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
5254 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } },
5255 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
5256 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
5257 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
5258 /*xcpt? */ false, false },
5259 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },
5260 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
5261 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } },
5262 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
5263 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
5264 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
5265 /*xcpt? */ false, false },
5266 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } },
5267 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
5268 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
5269 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
5270 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
5271 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
5272 /*xcpt? */ false, false },
5273 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
5274 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
5275 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
5276 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5277 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
5278 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
5279 /*xcpt? */ false, false },
5280 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
5281 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
5282 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5283 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
5284 /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
5285 /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
5286 /*xcpt? */ true, true },
5287 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
5288 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
5289 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5290 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
5291 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
5292 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
5293 /*xcpt? */ true, true },
5294 /*
5295 * Normals.
5296 */
5297 /*23*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(0), FP64_NORM_V2(0) } },
5298 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
5299 { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
5300 /*mxcsr:in */ 0,
5301 /*128:out */ 0,
5302 /*256:out */ 0,
5303 /*xcpt? */ false, false },
5304 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
5305 { /*src1 */ { FP64_NORM_MIN(0), FP64_NORM_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
5306 { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
5307 /*mxcsr:in */ 0,
5308 /*128:out */ 0,
5309 /*256:out */ 0,
5310 /*xcpt? */ false, false },
5311 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
5312 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
5313 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
5314 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5315 /*128:out */ X86_MXCSR_XCPT_MASK,
5316 /*256:out */ X86_MXCSR_XCPT_MASK,
5317 /*xcpt? */ false, false },
5318 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
5319 { /*src1 */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
5320 { /* => */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
5321 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5322 /*128:out */ X86_MXCSR_XCPT_MASK,
5323 /*256:out */ X86_MXCSR_XCPT_MASK,
5324 /*xcpt? */ false, false },
5325 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(0), FP64_RAND_V0(0), FP64_RAND_V1(1) } },
5326 { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
5327 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
5328 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5329 /*128:out */ X86_MXCSR_XCPT_MASK,
5330 /*256:out */ X86_MXCSR_XCPT_MASK,
5331 /*xcpt? */ false, false },
5332 { { /*src2 */ { FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
5333 { /*src1 */ { FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
5334 { /* => */ { FP64_V(1, 0xd6f3458800000, 0x41c)/*-987654321*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
5335 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5336 /*128:out */ X86_MXCSR_XCPT_MASK,
5337 /*256:out */ X86_MXCSR_XCPT_MASK,
5338 /*xcpt? */ false, false },
5339 { { /*src2 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } },
5340 { /*src1 */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
5341 { /* => */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
5342 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5343 /*128:out */ X86_MXCSR_XCPT_MASK,
5344 /*256:out */ X86_MXCSR_XCPT_MASK,
5345 /*xcpt? */ false, false },
5346 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
5347 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
5348 { /* => */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
5349 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5350 /*128:out */ X86_MXCSR_XCPT_MASK,
5351 /*256:out */ X86_MXCSR_XCPT_MASK,
5352 /*xcpt? */ false, false },
5353 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
5354 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } },
5355 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } },
5356 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
5357 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
5358 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
5359 /*xcpt? */ false, false },
5360 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } },
5361 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
5362 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
5363 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
5364 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
5365 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
5366 /*xcpt? */ false, false },
5367 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } },
5368 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
5369 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
5370 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
5371 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
5372 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
5373 /*xcpt? */ false, false },
5374 /*
5375 * Denormals.
5376 */
5377 /*34*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5378 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5379 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5380 /*mxcsr:in */ 0,
5381 /*128:out */ X86_MXCSR_DE,
5382 /*256:out */ X86_MXCSR_DE,
5383 /*xcpt? */ true, true },
5384 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5385 { /*src1 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
5386 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
5387 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
5388 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
5389 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
5390 /*xcpt? */ false, false },
5391 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
5392 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
5393 { /* => */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
5394 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
5395 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
5396 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
5397 /*xcpt? */ false, false },
5398 /** @todo More Denormals. */
5399 /*
5400 * Invalids.
5401 */
5402 /* QNan, QNan (Masked). */
5403 /*32*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5404 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5405 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5406 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5407 /*128:out */ X86_MXCSR_XCPT_MASK,
5408 /*256:out */ X86_MXCSR_XCPT_MASK,
5409 /*xcpt? */ false, false },
5410 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } },
5411 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },
5412 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },
5413 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5414 /*128:out */ X86_MXCSR_XCPT_MASK,
5415 /*256:out */ X86_MXCSR_XCPT_MASK,
5416 /*xcpt? */ false, false },
5417 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } },
5418 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },
5419 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },
5420 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5421 /*128:out */ X86_MXCSR_XCPT_MASK,
5422 /*256:out */ X86_MXCSR_XCPT_MASK,
5423 /*xcpt? */ false, false },
5424 /* QNan, SNan (Masked). */
5425 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5426 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },
5427 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },
5428 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5429 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5430 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5431 /*xcpt? */ false, false },
5432 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5433 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5434 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5435 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5436 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5437 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5438 /*xcpt? */ false, false },
5439 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } },
5440 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },
5441 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },
5442 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5443 /*128:out */ X86_MXCSR_XCPT_MASK,
5444 /*256:out */ X86_MXCSR_XCPT_MASK,
5445 /*xcpt? */ false, false },
5446 /* SNan, QNan (Masked). */
5447 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
5448 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },
5449 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },
5450 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5451 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5452 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5453 /*xcpt? */ false, false },
5454 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5455 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5456 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5457 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5458 /*128:out */ X86_MXCSR_XCPT_MASK,
5459 /*256:out */ X86_MXCSR_XCPT_MASK,
5460 /*xcpt? */ false, false },
5461 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5462 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
5463 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
5464 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5465 /*128:out */ X86_MXCSR_XCPT_MASK,
5466 /*256:out */ X86_MXCSR_XCPT_MASK,
5467 /*xcpt? */ false, false },
5468 /* SNan, SNan (Masked). */
5469 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5470 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5471 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5472 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5473 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5474 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5475 /*xcpt? */ false, false },
5476 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5477 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },
5478 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },
5479 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5480 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5481 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5482 /*xcpt? */ false, false },
5483 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5484 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5485 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5486 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5487 /*128:out */ X86_MXCSR_XCPT_MASK,
5488 /*256:out */ X86_MXCSR_XCPT_MASK,
5489 /*xcpt? */ false, false },
5490 /* QNan, Norm FP (Masked). */
5491 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5492 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5493 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5494 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5495 /*128:out */ X86_MXCSR_XCPT_MASK,
5496 /*256:out */ X86_MXCSR_XCPT_MASK,
5497 /*xcpt? */ false, false },
5498 /* SNan, Norm FP (Masked). */
5499 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5500 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5501 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5502 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5503 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5504 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
5505 /*xcpt? */ false, false },
5506 /* QNan, QNan (Unmasked). */
5507 /*46*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5508 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5509 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5510 /*mxcsr:in */ 0,
5511 /*128:out */ 0,
5512 /*256:out */ 0,
5513 /*xcpt? */ false, false },
5514 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5515 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5516 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5517 /*mxcsr:in */ 0,
5518 /*128:out */ 0,
5519 /*256:out */ 0,
5520 /*xcpt? */ false, false },
5521 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5522 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },
5523 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },
5524 /*mxcsr:in */ 0,
5525 /*128:out */ 0,
5526 /*256:out */ 0,
5527 /*xcpt? */ false, false },
5528
5529 /* QNan, SNan (Unmasked). */
5530 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
5531 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5532 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5533 /*mxcsr:in */ 0,
5534 /*128:out */ X86_MXCSR_IE,
5535 /*256:out */ X86_MXCSR_IE,
5536 /*xcpt? */ true, true },
5537 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5538 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5539 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5540 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5541 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
5542 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
5543 /*xcpt? */ true, true },
5544 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5545 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5546 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5547 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5548 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5549 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5550 /*xcpt? */ false, false },
5551 /* SNan, QNan (Unmasked). */
5552 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5553 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5554 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
5555 /*mxcsr:in */ X86_MXCSR_DAZ,
5556 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
5557 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
5558 /*xcpt? */ true, true },
5559 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
5560 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },
5561 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },
5562 /*mxcsr:in */ X86_MXCSR_RC_UP,
5563 /*128:out */ X86_MXCSR_RC_UP,
5564 /*256:out */ X86_MXCSR_RC_UP,
5565 /*xcpt? */ false, false },
5566 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
5567 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
5568 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
5569 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5570 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5571 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5572 /*xcpt? */ false, false },
5573 /* SNan, SNan (Unmasked). */
5574 /*55*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5575 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },
5576 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },
5577 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
5578 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
5579 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
5580 /*xcpt? */ true, true },
5581 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } },
5582 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },
5583 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },
5584 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
5585 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5586 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5587 /*xcpt? */ true, true },
5588 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } },
5589 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5590 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },
5591 /*mxcsr:in */ 0,
5592 /*128:out */ 0,
5593 /*256:out */ 0,
5594 /*xcpt? */ false, false },
5595 /* QNan, Norm FP (Unmasked). */
5596 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
5597 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5598 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5599 /*mxcsr:in */ X86_MXCSR_FZ,
5600 /*128:out */ X86_MXCSR_FZ,
5601 /*256:out */ X86_MXCSR_FZ,
5602 /*xcpt? */ false, false },
5603 /* SNan, Norm FP (Unmasked). */
5604 /*59*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
5605 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5606 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
5607 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5608 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5609 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
5610 /*xcpt? */ true, true },
5611 /** @todo Underflow, Precision; Rounding, FZ etc. */
5612 };
5613
5614
5615 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
5616 {
5617 { bs3CpuInstr4_subsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5618 { bs3CpuInstr4_subsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5619
5620 { bs3CpuInstr4_vsubsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5621 { bs3CpuInstr4_vsubsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5622 };
5623 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
5624 {
5625 { bs3CpuInstr4_subsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5626 { bs3CpuInstr4_subsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5627
5628 { bs3CpuInstr4_vsubsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5629 { bs3CpuInstr4_vsubsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5630 };
5631 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
5632 {
5633 { bs3CpuInstr4_subsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5634 { bs3CpuInstr4_subsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5635
5636 { bs3CpuInstr4_vsubsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5637 { bs3CpuInstr4_vsubsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5638
5639 { bs3CpuInstr4_subsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5640 { bs3CpuInstr4_subsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5641
5642 { bs3CpuInstr4_vsubsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5643 { bs3CpuInstr4_vsubsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5644 };
5645
5646 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5647 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
5648 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5649 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
5650}
5651
5652
5653/*
5654 * [V]MULPS.
5655 */
5656BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulps(uint8_t bMode)
5657{
5658 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
5659 {
5660 /*
5661 * Zero.
5662 */
5663 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5664 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5665 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5666 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5667 /*128:out */ X86_MXCSR_XCPT_MASK,
5668 /*256:out */ X86_MXCSR_XCPT_MASK,
5669 /*xcpt? */ false, false },
5670 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5671 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5672 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5673 /*mxcsr:in */ 0,
5674 /*128:out */ 0,
5675 /*256:out */ 0,
5676 /*xcpt? */ false, false },
5677 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5678 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5679 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5680 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5681 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5682 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
5683 /*xcpt? */ false, false },
5684 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
5685 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
5686 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5687 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5688 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5689 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5690 /*xcpt? */ false, false },
5691 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
5692 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
5693 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5694 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5695 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5696 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5697 /*xcpt? */ false, false },
5698 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
5699 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } },
5700 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } },
5701 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5702 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5703 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
5704 /*xcpt? */ false, false },
5705 { { /*src2 */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } },
5706 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_NORM_V2(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
5707 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },
5708 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5709 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5710 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
5711 /*xcpt? */ false, false },
5712 /*
5713 * Infinity.
5714 */
5715 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5716 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5717 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5718 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
5719 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
5720 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
5721 /*xcpt? */ false, false },
5722 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5723 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5724 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5725 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5726 /*128:out */ X86_MXCSR_XCPT_MASK,
5727 /*256:out */ X86_MXCSR_XCPT_MASK,
5728 /*xcpt? */ false, false },
5729 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
5730 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
5731 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
5732 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
5733 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
5734 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
5735 /*xcpt? */ false, false },
5736 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
5737 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
5738 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
5739 /*mxcsr:in */ X86_MXCSR_FZ,
5740 /*128:out */ X86_MXCSR_FZ,
5741 /*256:out */ X86_MXCSR_FZ,
5742 /*xcpt? */ false, false },
5743 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
5744 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
5745 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
5746 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5747 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5748 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
5749 /*xcpt? */ false, false },
5750#if 0
5751 /*
5752 * Normals.
5753 */
5754 /*12*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.250*/, FP32_V(0, 0x600000, 0x7f)/* 1.7500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.250*/ } },
5755 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.500*/, FP32_V(1, 0, 0x7d)/*-0.2500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.500*/ } },
5756 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/*0.125*/, FP32_V(1, 0x600000, 0x7d)/*-0.4375*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/*0.125*/ } },
5757 /*mask */ X86_MXCSR_XCPT_MASK,
5758 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
5759 /*flags */ 0, 0 },
5760 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
5761 { /*src1 */ { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
5762 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(1), FP32_NORM_V3(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
5763 /*mask */ ~X86_MXCSR_XCPT_MASK,
5764 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5765 /*flags */ 0, 0 },
5766 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_V(0, 0x0ba000, 0x86)/* 139.625000*/, FP32_V(0, 0x200000, 0x7e)/*0.625000*/, FP32_V(0, 0x22fae4, 0x93)/*1335132.50*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x3d400, 0x86)/*131.828125*/ } },
5767 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_V(0, 0x265000, 0x87)/* 332.625000*/, FP32_V(0, 0, 0x7c)/*0.125000*/, FP32_V(0, 0x200000, 0x80)/* 2.50*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_1(1) /* -1.000000*/ } },
5768 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x356ac4, 0x8e)/*46442.765625*/, FP32_V(0, 0x200000, 0x7b)/*0.078125*/, FP32_V(0, 0x4bb99d, 0x94)/*3337831.25*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(1, 0x3d400, 0x86)/*-131.828125*/ } },
5769 /*mask */ X86_MXCSR_XCPT_MASK,
5770 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5771 /*flags */ 0, 0 },
5772 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
5773 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0) } },
5774 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(0) } },
5775 /*mask */ X86_MXCSR_XCPT_MASK,
5776 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5777 /*flags */ 0, 0 },
5778 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } },
5779 { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_1(0) } },
5780 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2) } },
5781 /*mask */ X86_MXCSR_XCPT_MASK,
5782 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5783 /*flags */ 0, 0 },
5784 /** @todo More Normals. */
5785 /*
5786 * Denormals.
5787 */
5788 /*17*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
5789 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
5790 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
5791 /*mask */ ~X86_MXCSR_XCPT_MASK,
5792 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5793 /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
5794 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
5795 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } },
5796 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
5797 /*mask */ ~X86_MXCSR_XCPT_MASK,
5798 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5799 /*flags */ X86_MXCSR_DE, X86_MXCSR_DE },
5800 { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } },
5801 { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
5802 { /* => */ { FP32_0(1), FP32_0(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5803 /*mask */ X86_MXCSR_XCPT_MASK,
5804 /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
5805 /*flags */ 0, 0 },
5806 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V4(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } },
5807 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
5808 { /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_0(0), FP32_0(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_0(0), FP32_0(0) } },
5809 /*mask */ X86_MXCSR_XCPT_MASK,
5810 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
5811 /*flags */ 0, 0 },
5812 /** @todo More Denormals. */
5813 /*
5814 * Overflow, Precision.
5815 */
5816 /*21*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V7(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
5817 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
5818 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_NORM_V7(0), FP32_INF(0), FP32_INF(0) } },
5819 /*mask */ X86_MXCSR_XCPT_MASK,
5820 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5821 /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
5822 { { /*src2 */ { FP32_NORM_V5(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_1(0), FP32_0(0) } },
5823 { /*src1 */ { FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } },
5824 { /* => */ { FP32_NORM_V5(0), FP32_INF(0), FP32_INF(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } },
5825 /*mask */ X86_MXCSR_OM | X86_MXCSR_PM,
5826 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5827 /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
5828 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_V7(0), FP32_NORM_MAX(0) } },
5829 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(0) } },
5830 { /* => */ { FP32_INF(0), FP32_0(0), FP32_1(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_NORM_V7(0), FP32_INF(0) } },
5831 /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
5832 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
5833 /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
5834 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_V5(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
5835 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0) } },
5836 { /* => */ { FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_V5(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0) } },
5837 /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
5838 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5839 /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
5840 { { /*src2 */ { FP32_NORM_V6(0), FP32_1(1), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
5841 { /*src1 */ { FP32_1(0), FP32_NORM_V6(1), FP32_1(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
5842 { /* => */ { FP32_NORM_V6(0), FP32_NORM_V6(0), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
5843 /*mask */ X86_MXCSR_XCPT_MASK,
5844 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
5845 /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
5846 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
5847 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
5848 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
5849 /*mask */ ~X86_MXCSR_XCPT_MASK,
5850 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
5851 /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
5852 /** @todo More Overflow, Precision. */
5853 /*
5854 * Invalids.
5855 */
5856 /*27*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5857 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5858 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5859 /*mask */ X86_MXCSR_XCPT_MASK,
5860 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5861 /*flags */ 0, 0 },
5862 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5863 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5864 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5865 /*mask */ X86_MXCSR_XCPT_MASK,
5866 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5867 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5868 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5869 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5870 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5871 /*mask */ X86_MXCSR_XCPT_MASK,
5872 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5873 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5874 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5875 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5876 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
5877 /*mask */ X86_MXCSR_XCPT_MASK,
5878 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5879 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5880 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5881 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5882 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5883 /*mask */ X86_MXCSR_XCPT_MASK,
5884 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5885 /*flags */ 0, 0 },
5886 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
5887 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5888 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5889 /*mask */ X86_MXCSR_XCPT_MASK,
5890 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
5891 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5892 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5893 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5894 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5895 /*mask */ ~X86_MXCSR_XCPT_MASK,
5896 /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
5897 /*flags */ 0, 0 },
5898 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
5899 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
5900 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
5901 /*mask */ ~X86_MXCSR_XCPT_MASK,
5902 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5903 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5904 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
5905 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5906 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
5907 /*mask */ ~X86_MXCSR_XCPT_MASK,
5908 /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
5909 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5910 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
5911 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
5912 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },
5913 /*mask */ ~X86_MXCSR_XCPT_MASK,
5914 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_UP,
5915 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5916 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5917 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5918 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5919 /*mask */ ~X86_MXCSR_XCPT_MASK,
5920 /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_DOWN,
5921 /*flags */ 0, 0 },
5922 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
5923 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
5924 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },
5925 /*mask */ ~X86_MXCSR_XCPT_MASK,
5926 /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
5927 /*flags */ X86_MXCSR_IE, X86_MXCSR_IE },
5928 /** @todo Underflow, Precision; Rounding, FZ etc. */
5929#endif
5930 };
5931
5932 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
5933 {
5934 { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5935 { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5936
5937 { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5938 { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5939
5940 { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5941 { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5942 };
5943 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
5944 {
5945 { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5946 { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5947
5948 { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5949 { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5950
5951 { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5952 { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5953 };
5954 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
5955 {
5956 { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5957 { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5958
5959 { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5960 { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5961
5962 { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5963 { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5964
5965 { bs3CpuInstr4_mulps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5966 { bs3CpuInstr4_mulps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5967
5968 { bs3CpuInstr4_vmulps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5969 { bs3CpuInstr4_vmulps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
5970 };
5971
5972 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
5973 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
5974 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
5975 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
5976}
5977
5978
5979/*
5980 * [V]MULPD.
5981 */
5982BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulpd(uint8_t bMode)
5983{
5984 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
5985 {
5986 /*
5987 * Zero.
5988 */
5989 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5990 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5991 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5992 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
5993 /*128:out */ X86_MXCSR_XCPT_MASK,
5994 /*256:out */ X86_MXCSR_XCPT_MASK,
5995 /*xcpt? */ false, false },
5996 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5997 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5998 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
5999 /*mxcsr:in */ 0,
6000 /*128:out */ 0,
6001 /*256:out */ 0,
6002 /*xcpt? */ false, false },
6003 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6004 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6005 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6006 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6007 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6008 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6009 /*xcpt? */ false, false },
6010 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
6011 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
6012 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6013 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6014 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6015 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6016 /*xcpt? */ false, false },
6017 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
6018 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
6019 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6020 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6021 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6022 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6023 /*xcpt? */ false, false },
6024 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
6025 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
6026 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
6027 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6028 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6029 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6030 /*xcpt? */ false, false },
6031 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } },
6032 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } },
6033 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
6034 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6035 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6036 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6037 /*xcpt? */ false, false },
6038 /*
6039 * Infinity.
6040 */
6041 /* 7*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(1), FP64_0(0) } },
6042 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } },
6043 { /* => */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } },
6044 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6045 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6046 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6047 /*xcpt? */ false, false },
6048 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
6049 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
6050 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
6051 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6052 /*128:out */ X86_MXCSR_XCPT_MASK,
6053 /*256:out */ X86_MXCSR_XCPT_MASK,
6054 /*xcpt? */ false, false },
6055 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
6056 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
6057 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
6058 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6059 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6060 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6061 /*xcpt? */ false, false },
6062 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
6063 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
6064 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
6065 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6066 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6067 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6068 /*xcpt? */ false, false },
6069 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(0), FP64_INF(0) } },
6070 { /*src1 */ { FP64_1(0), FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } },
6071 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
6072 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6073 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6074 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6075 /*xcpt? */ false, false },
6076 { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_NORM_V3(0), FP64_INF(1) } },
6077 { /*src1 */ { FP64_1(1), FP64_NORM_V3(1), FP64_INF(1), FP64_NORM_V1(1) } },
6078 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
6079 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6080 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6081 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6082 /*xcpt? */ false, false },
6083 /*
6084 * Normals.
6085 */
6086 /*13*/{ { /*src2 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/ } },
6087 { /*src1 */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } },
6088 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } },
6089 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6090 /*128:out */ X86_MXCSR_XCPT_MASK,
6091 /*256:out */ X86_MXCSR_XCPT_MASK,
6092 /*xcpt? */ false, false },
6093 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } },
6094 { /*src1 */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } },
6095 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } },
6096 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6097 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6098 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6099 /*xcpt? */ false, false },
6100 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } },
6101 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } },
6102 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } },
6103 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6104 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6105 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6106 /*xcpt? */ false, false },
6107 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } },
6108 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } },
6109 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
6110 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6111 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6112 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6113 /*xcpt? */ false, false },
6114 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
6115 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } },
6116 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } },
6117 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6118 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6119 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6120 /*xcpt? */ false, false },
6121 /** @todo More Normals. */
6122 /*
6123 * Denormals.
6124 */
6125 /*18*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
6126 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } },
6127 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6128 /*mxcsr:in */ 0,
6129 /*128:out */ X86_MXCSR_DE,
6130 /*256:out */ X86_MXCSR_DE,
6131 /*xcpt? */ true, true },
6132 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
6133 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0) } },
6134 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6135 /*mxcsr:in */ X86_MXCSR_FZ,
6136 /*128:out */ X86_MXCSR_FZ,
6137 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,
6138 /*xcpt? */ false, true },
6139 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
6140 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0) } },
6141 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6142 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
6143 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
6144 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
6145 /*xcpt? */ false, false },
6146 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0), FP64_1(0) } },
6147 { /*src1 */ { FP64_1(0), FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0) } },
6148 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6149 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6150 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6151 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6152 /*xcpt? */ false, false },
6153 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
6154 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(1), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
6155 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
6156 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6157 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6158 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6159 /*xcpt? */ false, false },
6160 { { /*src2 */ { FP64_1(0), FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
6161 { /*src1 */ { FP64_NORM_V0(0), FP64_1(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
6162 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } },
6163 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6164 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6165 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE,
6166 /*xcpt? */ false, false },
6167 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
6168 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
6169 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } },
6170 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6171 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
6172 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
6173 /*xcpt? */ true, true },
6174 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
6175 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
6176 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
6177 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6178 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
6179 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
6180 /*xcpt? */ true, true },
6181 /*
6182 * Overflow, Precision.
6183 */
6184 /*26*/{ { /*src2 */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
6185 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_NORM_MAX(0) } },
6186 { /* => */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0) } },
6187 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6188 /*128:out */ X86_MXCSR_XCPT_MASK,
6189 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
6190 /*xcpt? */ false, false },
6191 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } },
6192 { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_1(0), FP64_1(0) } },
6193 { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_NORM_V3(1), FP64_1(0) } },
6194 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6195 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
6196 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
6197 /*xcpt? */ false, false },
6198 { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0) } },
6199 { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
6200 { /* => */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } },
6201 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6202 /*128:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
6203 /*256:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
6204 /*xcpt? */ false, false },
6205 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } },
6206 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
6207 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0) } },
6208 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
6209 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
6210 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
6211 /*xcpt? */ false, false },
6212 { { /*src2 */ { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
6213 { /*src1 */ { FP64_1(0), FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
6214 { /* => */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } },
6215 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO,
6216 /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO,
6217 /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
6218 /*xcpt? */ false, false },
6219 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } },
6220 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } },
6221 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
6222 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6223 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
6224 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
6225 /*xcpt? */ false, false },
6226 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } },
6227 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } },
6228 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
6229 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6230 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
6231 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
6232 /*xcpt? */ false, false },
6233 /*
6234 * Invalids.
6235 */
6236 /*33*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6237 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6238 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6239 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6240 /*128:out */ X86_MXCSR_XCPT_MASK,
6241 /*256:out */ X86_MXCSR_XCPT_MASK,
6242 /*xcpt? */ false, false },
6243 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6244 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } },
6245 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6246 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6247 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6248 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6249 /*xcpt? */ false, false },
6250 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },
6251 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
6252 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
6253 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6254 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6255 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6256 /*xcpt? */ false, false },
6257 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
6258 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },
6259 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },
6260 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6261 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6262 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6263 /*xcpt? */ false, false },
6264 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6265 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
6266 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6267 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6268 /*128:out */ X86_MXCSR_XCPT_MASK,
6269 /*256:out */ X86_MXCSR_XCPT_MASK,
6270 /*xcpt? */ false, false },
6271 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
6272 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
6273 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6274 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6275 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6276 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6277 /*xcpt? */ false, false },
6278 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6279 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
6280 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },
6281 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6282 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6283 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6284 /*xcpt? */ false, false },
6285 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } },
6286 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } },
6287 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } },
6288 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6289 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6290 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6291 /*xcpt? */ true, true },
6292 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
6293 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6294 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6295 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6296 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6297 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6298 /*xcpt? */ true, true },
6299 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
6300 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
6301 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },
6302 /*mxcsr:in */ X86_MXCSR_RC_UP,
6303 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
6304 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,
6305 /*xcpt? */ true, true },
6306 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6307 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
6308 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },
6309 /*mxcsr:in */ X86_MXCSR_RC_DOWN,
6310 /*128:out */ X86_MXCSR_RC_DOWN,
6311 /*256:out */ X86_MXCSR_RC_DOWN,
6312 /*xcpt? */ false, false },
6313 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
6314 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },
6315 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
6316 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6317 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6318 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6319 /*xcpt? */ true, true },
6320 /** @todo Underflow, Precision; Rounding, FZ etc. */
6321 };
6322
6323 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
6324 {
6325 { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6326 { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6327
6328 { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6329 { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6330
6331 { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6332 { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6333 };
6334 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
6335 {
6336 { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6337 { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6338
6339 { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6340 { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6341
6342 { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6343 { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6344 };
6345 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
6346 {
6347 { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6348 { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6349
6350 { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6351 { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6352
6353 { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6354 { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6355
6356 { bs3CpuInstr4_mulpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6357 { bs3CpuInstr4_mulpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6358
6359 { bs3CpuInstr4_vmulpd_XMM8_XMM9_XMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6360 { bs3CpuInstr4_vmulpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6361 { bs3CpuInstr4_vmulpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6362 { bs3CpuInstr4_vmulpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6363 };
6364
6365 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6366 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
6367 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6368 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
6369}
6370
6371
6372/*
6373 * [V]MULSS.
6374 */
6375BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulss(uint8_t bMode)
6376{
6377 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
6378 {
6379 /*
6380 * Zero.
6381 */
6382 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6383 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6384 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6385 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6386 /*128:out */ X86_MXCSR_XCPT_MASK,
6387 /*256:out */ X86_MXCSR_XCPT_MASK,
6388 /*xcpt? */ false, false },
6389 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6390 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6391 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6392 /*mxcsr:in */ 0,
6393 /*128:out */ 0,
6394 /*256:out */ 0,
6395 /*xcpt? */ false, false },
6396 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6397 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6398 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6399 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6400 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6401 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6402 /*xcpt? */ false, false },
6403 { { /*src2 */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0) } },
6404 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } },
6405 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } },
6406 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6407 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6408 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6409 /*xcpt? */ false, false },
6410 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
6411 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6412 { /* => */ { FP32_0(0), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6413 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6414 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6415 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6416 /*xcpt? */ false, false },
6417 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6418 { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
6419 { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
6420 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6421 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6422 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6423 /*xcpt? */ false, false },
6424 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6425 { /*src1 */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
6426 { /* => */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
6427 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
6428 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
6429 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
6430 /*xcpt? */ false, false },
6431 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6432 { /*src1 */ { FP32_1(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
6433 { /* => */ { FP32_0(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
6434 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6435 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6436 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6437 /*xcpt? */ false, false },
6438 /*
6439 * Infinity.
6440 */
6441 /* 8*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6442 { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6443 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6444 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6445 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6446 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6447 /*xcpt? */ false, false },
6448 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6449 { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6450 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
6451 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6452 /*128:out */ X86_MXCSR_XCPT_MASK,
6453 /*256:out */ X86_MXCSR_XCPT_MASK,
6454 /*xcpt? */ false, false },
6455 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
6456 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6457 { /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6458 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6459 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6460 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6461 /*xcpt? */ false, false },
6462 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
6463 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6464 { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6465 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6466 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6467 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6468 /*xcpt? */ false, false },
6469 { { /*src2 */ { FP32_1(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6470 { /*src1 */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
6471 { /* => */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
6472 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
6473 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
6474 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
6475 /*xcpt? */ false, false },
6476 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },
6477 { /*src1 */ { FP32_1(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
6478 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
6479 /*mxcsr:in */ X86_MXCSR_FZ,
6480 /*128:out */ X86_MXCSR_FZ,
6481 /*256:out */ X86_MXCSR_FZ,
6482 /*xcpt? */ false, false },
6483 { { /*src2 */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
6484 { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
6485 { /* => */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
6486 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6487 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6488 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6489 /*xcpt? */ false, false },
6490 /*
6491 * Normals.
6492 */
6493 /*15*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6494 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
6495 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
6496 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6497 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6498 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6499 /*xcpt? */ false, false },
6500 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
6501 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6502 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6503 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6504 /*128:out */ X86_MXCSR_XCPT_MASK,
6505 /*256:out */ X86_MXCSR_XCPT_MASK,
6506 /*xcpt? */ false, false },
6507 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
6508 { /*src1 */ { FP32_1(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6509 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
6510 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6511 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6512 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6513 /*xcpt? */ false, false },
6514 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6515 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
6516 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
6517 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
6518 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
6519 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
6520 /*xcpt? */ false, false },
6521 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
6522 { /*src1 */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
6523 { /* => */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
6524 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6525 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6526 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6527 /*xcpt? */ false, false },
6528 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } },
6529 { /*src1 */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V6(0), FP32_RAND_V1(1) } },
6530 { /* => */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V1(1) } },
6531 /*mxcsr:in */ 0,
6532 /*128:out */ 0,
6533 /*256:out */ 0,
6534 /*xcpt? */ false, false },
6535 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } },
6536 { /*src1 */ { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
6537 { /* => */ { FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } },
6538 /*mxcsr:in */ 0,
6539 /*128:out */ 0,
6540 /*256:out */ 0,
6541 /*xcpt? */ false, false },
6542 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
6543 { /*src1 */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
6544 { /* => */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
6545 /*mxcsr:in */ 0,
6546 /*128:out */ 0,
6547 /*256:out */ 0,
6548 /*xcpt? */ false, false },
6549 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
6550 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } },
6551 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } },
6552 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6553 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6554 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6555 /*xcpt? */ false, false },
6556 /** @todo More Normals. */
6557 /*
6558 * Denormals.
6559 */
6560 /*24*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
6561 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
6562 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
6563 /*mxcsr:in */ 0,
6564 /*128:out */ X86_MXCSR_DE,
6565 /*256:out */ X86_MXCSR_DE,
6566 /*xcpt? */ true, true },
6567 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },
6568 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } },
6569 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
6570 /*mxcsr:in */ 0,
6571 /*128:out */ X86_MXCSR_DE,
6572 /*256:out */ X86_MXCSR_DE,
6573 /*xcpt? */ true, true },
6574 { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } },
6575 { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
6576 { /* => */ { FP32_0(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } },
6577 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6578 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
6579 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
6580 /*xcpt? */ false, false },
6581 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } },
6582 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
6583 { /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } },
6584 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6585 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6586 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6587 /*xcpt? */ false, false },
6588 /** @todo More Denormals. */
6589 /*
6590 * Invalids.
6591 */
6592 /* QNan, QNan (Masked). */
6593 /*28*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
6594 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6595 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6596 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6597 /*128:out */ X86_MXCSR_XCPT_MASK,
6598 /*256:out */ X86_MXCSR_XCPT_MASK,
6599 /*xcpt? */ false, false },
6600 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6601 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6602 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6603 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6604 /*128:out */ X86_MXCSR_XCPT_MASK,
6605 /*256:out */ X86_MXCSR_XCPT_MASK,
6606 /*xcpt? */ false, false },
6607 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6608 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6609 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6610 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6611 /*128:out */ X86_MXCSR_XCPT_MASK,
6612 /*256:out */ X86_MXCSR_XCPT_MASK,
6613 /*xcpt? */ false, false },
6614 /* QNan, SNan (Masked). */
6615 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6616 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6617 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6618 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6619 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6620 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6621 /*xcpt? */ false, false },
6622 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
6623 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
6624 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
6625 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6626 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6627 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6628 /*xcpt? */ false, false },
6629 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
6630 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6631 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6632 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6633 /*128:out */ X86_MXCSR_XCPT_MASK,
6634 /*256:out */ X86_MXCSR_XCPT_MASK,
6635 /*xcpt? */ false, false },
6636 /* SNan, QNan (Masked). */
6637 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
6638 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6639 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6640 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6641 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6642 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6643 /*xcpt? */ false, false },
6644 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
6645 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6646 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6647 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6648 /*128:out */ X86_MXCSR_XCPT_MASK,
6649 /*256:out */ X86_MXCSR_XCPT_MASK,
6650 /*xcpt? */ false, false },
6651 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
6652 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6653 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6654 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6655 /*128:out */ X86_MXCSR_XCPT_MASK,
6656 /*256:out */ X86_MXCSR_XCPT_MASK,
6657 /*xcpt? */ false, false },
6658 /* SNan, SNan (Masked). */
6659 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6660 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6661 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6662 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6663 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6664 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6665 /*xcpt? */ false, false },
6666 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6667 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6668 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6669 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6670 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6671 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6672 /*xcpt? */ false, false },
6673 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6674 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
6675 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
6676 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6677 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6678 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6679 /*xcpt? */ false, false },
6680 /* QNan, Norm FP (Masked). */
6681 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
6682 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6683 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6684 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6685 /*128:out */ X86_MXCSR_XCPT_MASK,
6686 /*256:out */ X86_MXCSR_XCPT_MASK,
6687 /*xcpt? */ false, false },
6688 /* SNan, Norm FP (Masked). */
6689 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
6690 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6691 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6692 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6693 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6694 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
6695 /*xcpt? */ false, false },
6696 /* QNan, QNan (Unmasked). */
6697 /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
6698 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6699 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6700 /*mxcsr:in */ 0,
6701 /*128:out */ 0,
6702 /*256:out */ 0,
6703 /*xcpt? */ false, false },
6704 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6705 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6706 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6707 /*mxcsr:in */ 0,
6708 /*128:out */ 0,
6709 /*256:out */ 0,
6710 /*xcpt? */ false, false },
6711 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6712 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6713 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6714 /*mxcsr:in */ 0,
6715 /*128:out */ 0,
6716 /*256:out */ 0,
6717 /*xcpt? */ false, false },
6718
6719 /* QNan, SNan (Unmasked). */
6720 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6721 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6722 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6723 /*mxcsr:in */ 0,
6724 /*128:out */ X86_MXCSR_IE,
6725 /*256:out */ X86_MXCSR_IE,
6726 /*xcpt? */ true, true },
6727 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
6728 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
6729 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },
6730 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6731 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
6732 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
6733 /*xcpt? */ true, true },
6734 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },
6735 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6736 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },
6737 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6738 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6739 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6740 /*xcpt? */ false, false },
6741 /* SNan, QNan (Unmasked). */
6742 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
6743 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6744 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6745 /*mxcsr:in */ X86_MXCSR_DAZ,
6746 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
6747 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
6748 /*xcpt? */ true, true },
6749 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
6750 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6751 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6752 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
6753 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
6754 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
6755 /*xcpt? */ false, false },
6756 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },
6757 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6758 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },
6759 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6760 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6761 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6762 /*xcpt? */ false, false },
6763 /* SNan, SNan (Unmasked). */
6764 /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6765 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6766 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6767 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
6768 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
6769 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
6770 /*xcpt? */ true, true },
6771 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6772 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6773 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },
6774 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
6775 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6776 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6777 /*xcpt? */ true, true },
6778 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },
6779 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
6780 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },
6781 /*mxcsr:in */ X86_MXCSR_FZ,
6782 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
6783 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,
6784 /*xcpt? */ true, true },
6785 /* QNan, Norm FP (Unmasked). */
6786 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },
6787 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6788 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6789 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6790 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6791 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6792 /*xcpt? */ false, false },
6793 /* SNan, Norm FP (Unmasked). */
6794 /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },
6795 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6796 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },
6797 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6798 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6799 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
6800 /*xcpt? */ true, true },
6801 /** @todo Underflow, Precision; Rounding, FZ etc. */
6802 };
6803
6804 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
6805 {
6806 { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6807 { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6808
6809 { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6810 { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6811 };
6812 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
6813 {
6814 { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6815 { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6816
6817 { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6818 { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6819 };
6820 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
6821 {
6822 { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6823 { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6824
6825 { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6826 { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6827
6828 { bs3CpuInstr4_mulss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6829 { bs3CpuInstr4_mulss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6830
6831 { bs3CpuInstr4_vmulss_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6832 { bs3CpuInstr4_vmulss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
6833 };
6834
6835 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
6836 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
6837 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
6838 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
6839}
6840
6841
6842/*
6843 * [V]MULSD.
6844 */
6845BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulsd(uint8_t bMode)
6846{
6847 static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] =
6848 {
6849 /*
6850 * Zero.
6851 */
6852 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6853 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6854 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6855 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6856 /*128:out */ X86_MXCSR_XCPT_MASK,
6857 /*256:out */ X86_MXCSR_XCPT_MASK,
6858 /*xcpt? */ false, false },
6859 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6860 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6861 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6862 /*mxcsr:in */ 0,
6863 /*128:out */ 0,
6864 /*256:out */ 0,
6865 /*xcpt? */ false, false },
6866 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6867 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6868 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6869 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6870 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6871 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6872 /*xcpt? */ false, false },
6873 { { /*src2 */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0) } },
6874 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } },
6875 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } },
6876 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6877 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6878 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6879 /*xcpt? */ false, false },
6880 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
6881 { /*src1 */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
6882 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
6883 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6884 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6885 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
6886 /*xcpt? */ false, false },
6887 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
6888 { /*src1 */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
6889 { /* => */ { FP64_0(1), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
6890 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6891 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6892 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
6893 /*xcpt? */ false, false },
6894 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
6895 { /*src1 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
6896 { /* => */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
6897 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
6898 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
6899 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
6900 /*xcpt? */ false, false },
6901 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
6902 { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
6903 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
6904 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6905 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6906 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
6907 /*xcpt? */ false, false },
6908 /*
6909 * Infinity.
6910 */
6911 /* 8*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6912 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
6913 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
6914 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6915 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6916 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
6917 /*xcpt? */ false, false },
6918 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
6919 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
6920 { /* => */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
6921 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6922 /*128:out */ X86_MXCSR_XCPT_MASK,
6923 /*256:out */ X86_MXCSR_XCPT_MASK,
6924 /*xcpt? */ false, false },
6925 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
6926 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
6927 { /* => */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
6928 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6929 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6930 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
6931 /*xcpt? */ false, false },
6932 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
6933 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },
6934 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },
6935 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6936 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6937 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
6938 /*xcpt? */ false, false },
6939 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
6940 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
6941 { /* => */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
6942 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
6943 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
6944 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
6945 /*xcpt? */ false, false },
6946 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
6947 { /*src1 */ { FP64_1(1), FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
6948 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
6949 /*mxcsr:in */ X86_MXCSR_FZ,
6950 /*128:out */ X86_MXCSR_FZ,
6951 /*256:out */ X86_MXCSR_FZ,
6952 /*xcpt? */ false, false },
6953 { { /*src2 */ { FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } },
6954 { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } },
6955 { /* => */ { FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } },
6956 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6957 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6958 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
6959 /*xcpt? */ false, false },
6960 /*
6961 * Normals.
6962 */
6963 /*15*/{ { /*src2 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
6964 { /*src1 */ { FP64_1(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
6965 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
6966 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6967 /*128:out */ X86_MXCSR_XCPT_MASK,
6968 /*256:out */ X86_MXCSR_XCPT_MASK,
6969 /*xcpt? */ false, false },
6970 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },
6971 { /*src1 */ { FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
6972 { /* => */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
6973 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6974 /*128:out */ X86_MXCSR_XCPT_MASK,
6975 /*256:out */ X86_MXCSR_XCPT_MASK,
6976 /*xcpt? */ false, false },
6977 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
6978 { /*src1 */ { FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } },
6979 { /* => */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } },
6980 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6981 /*128:out */ X86_MXCSR_XCPT_MASK,
6982 /*256:out */ X86_MXCSR_XCPT_MASK,
6983 /*xcpt? */ false, false },
6984 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
6985 { /*src1 */ { FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
6986 { /* => */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
6987 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
6988 /*128:out */ X86_MXCSR_XCPT_MASK,
6989 /*256:out */ X86_MXCSR_XCPT_MASK,
6990 /*xcpt? */ false, false },
6991 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
6992 { /*src1 */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } },
6993 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } },
6994 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6995 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6996 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
6997 /*xcpt? */ false, false },
6998 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
6999 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
7000 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
7001 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7002 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7003 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7004 /*xcpt? */ false, false },
7005 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
7006 { /*src1 */ { FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
7007 { /* => */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
7008 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7009 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7010 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7011 /*xcpt? */ false, false },
7012 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
7013 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
7014 { /* => */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
7015 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7016 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7017 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7018 /*xcpt? */ false, false },
7019 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } },
7020 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } },
7021 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } },
7022 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7023 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7024 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7025 /*xcpt? */ false, false },
7026 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
7027 { /*src1 */ { FP64_1(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } },
7028 { /* => */ { FP64_NORM_V0(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } },
7029 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7030 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7031 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
7032 /*xcpt? */ false, false },
7033 /*
7034 * Denormals.
7035 */
7036 /*25*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
7037 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } },
7038 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } },
7039 /*mxcsr:in */ 0,
7040 /*128:out */ X86_MXCSR_DE,
7041 /*256:out */ X86_MXCSR_DE,
7042 /*xcpt? */ true, true },
7043 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
7044 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
7045 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
7046 /*mxcsr:in */ X86_MXCSR_FZ,
7047 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE,
7048 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,
7049 /*xcpt? */ true, true },
7050 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
7051 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
7052 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
7053 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
7054 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
7055 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
7056 /*xcpt? */ false, false },
7057 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
7058 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
7059 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
7060 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
7061 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
7062 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
7063 /*xcpt? */ false, false },
7064 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
7065 { /*src1 */ { FP64_DENORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
7066 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
7067 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
7068 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
7069 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
7070 /*xcpt? */ false, false },
7071 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
7072 { /*src1 */ { FP64_NORM_V0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
7073 { /* => */ { FP64_NORM_V0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
7074 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
7075 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
7076 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE,
7077 /*xcpt? */ false, false },
7078 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
7079 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
7080 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
7081 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7082 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
7083 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
7084 /*xcpt? */ true, true },
7085 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
7086 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
7087 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
7088 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7089 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
7090 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
7091 /*xcpt? */ true, true },
7092 /** @todo Invalids, Underflow, Precision; Rounding, FZ etc. */
7093 /*
7094 * Invalids.
7095 */
7096 /* QNan, QNan (Masked). */
7097 /*33*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7098 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7099 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7100 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7101 /*128:out */ X86_MXCSR_XCPT_MASK,
7102 /*256:out */ X86_MXCSR_XCPT_MASK,
7103 /*xcpt? */ false, false },
7104 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } },
7105 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },
7106 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },
7107 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7108 /*128:out */ X86_MXCSR_XCPT_MASK,
7109 /*256:out */ X86_MXCSR_XCPT_MASK,
7110 /*xcpt? */ false, false },
7111 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } },
7112 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },
7113 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },
7114 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7115 /*128:out */ X86_MXCSR_XCPT_MASK,
7116 /*256:out */ X86_MXCSR_XCPT_MASK,
7117 /*xcpt? */ false, false },
7118 /* QNan, SNan (Masked). */
7119 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
7120 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },
7121 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },
7122 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7123 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7124 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7125 /*xcpt? */ false, false },
7126 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7127 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7128 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7129 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7130 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7131 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7132 /*xcpt? */ false, false },
7133 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } },
7134 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },
7135 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },
7136 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7137 /*128:out */ X86_MXCSR_XCPT_MASK,
7138 /*256:out */ X86_MXCSR_XCPT_MASK,
7139 /*xcpt? */ false, false },
7140 /* SNan, QNan (Masked). */
7141 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
7142 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },
7143 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },
7144 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7145 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7146 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7147 /*xcpt? */ false, false },
7148 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
7149 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7150 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7151 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7152 /*128:out */ X86_MXCSR_XCPT_MASK,
7153 /*256:out */ X86_MXCSR_XCPT_MASK,
7154 /*xcpt? */ false, false },
7155 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
7156 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
7157 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
7158 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7159 /*128:out */ X86_MXCSR_XCPT_MASK,
7160 /*256:out */ X86_MXCSR_XCPT_MASK,
7161 /*xcpt? */ false, false },
7162 /* SNan, SNan (Masked). */
7163 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7164 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
7165 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
7166 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7167 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7168 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7169 /*xcpt? */ false, false },
7170 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7171 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },
7172 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },
7173 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7174 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7175 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7176 /*xcpt? */ false, false },
7177 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7178 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
7179 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },
7180 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7181 /*128:out */ X86_MXCSR_XCPT_MASK,
7182 /*256:out */ X86_MXCSR_XCPT_MASK,
7183 /*xcpt? */ false, false },
7184 /* QNan, Norm FP (Masked). */
7185 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7186 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7187 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7188 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7189 /*128:out */ X86_MXCSR_XCPT_MASK,
7190 /*256:out */ X86_MXCSR_XCPT_MASK,
7191 /*xcpt? */ false, false },
7192 /* SNan, Norm FP (Masked). */
7193 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
7194 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7195 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7196 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
7197 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7198 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
7199 /*xcpt? */ false, false },
7200 /* QNan, QNan (Unmasked). */
7201 /*47*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7202 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7203 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7204 /*mxcsr:in */ 0,
7205 /*128:out */ 0,
7206 /*256:out */ 0,
7207 /*xcpt? */ false, false },
7208 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
7209 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7210 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7211 /*mxcsr:in */ 0,
7212 /*128:out */ 0,
7213 /*256:out */ 0,
7214 /*xcpt? */ false, false },
7215 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
7216 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },
7217 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },
7218 /*mxcsr:in */ 0,
7219 /*128:out */ 0,
7220 /*256:out */ 0,
7221 /*xcpt? */ false, false },
7222
7223 /* QNan, SNan (Unmasked). */
7224 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },
7225 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7226 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7227 /*mxcsr:in */ 0,
7228 /*128:out */ X86_MXCSR_IE,
7229 /*256:out */ X86_MXCSR_IE,
7230 /*xcpt? */ true, true },
7231 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7232 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7233 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7234 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
7235 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
7236 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
7237 /*xcpt? */ true, true },
7238 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7239 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7240 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7241 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7242 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7243 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7244 /*xcpt? */ false, false },
7245 /* SNan, QNan (Unmasked). */
7246 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
7247 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7248 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },
7249 /*mxcsr:in */ X86_MXCSR_DAZ,
7250 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
7251 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,
7252 /*xcpt? */ true, true },
7253 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
7254 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },
7255 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },
7256 /*mxcsr:in */ X86_MXCSR_RC_UP,
7257 /*128:out */ X86_MXCSR_RC_UP,
7258 /*256:out */ X86_MXCSR_RC_UP,
7259 /*xcpt? */ false, false },
7260 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },
7261 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
7262 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },
7263 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
7264 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
7265 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
7266 /*xcpt? */ false, false },
7267 /* SNan, SNan (Unmasked). */
7268 /*56*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7269 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },
7270 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },
7271 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
7272 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
7273 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
7274 /*xcpt? */ true, true },
7275 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } },
7276 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },
7277 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },
7278 /*mxcsr:in */ X86_MXCSR_RC_ZERO,
7279 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
7280 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
7281 /*xcpt? */ true, true },
7282 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } },
7283 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },
7284 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },
7285 /*mxcsr:in */ 0,
7286 /*128:out */ 0,
7287 /*256:out */ 0,
7288 /*xcpt? */ false, false },
7289 /* QNan, Norm FP (Unmasked). */
7290 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },
7291 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7292 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7293 /*mxcsr:in */ X86_MXCSR_FZ,
7294 /*128:out */ X86_MXCSR_FZ,
7295 /*256:out */ X86_MXCSR_FZ,
7296 /*xcpt? */ false, false },
7297 /* SNan, Norm FP (Unmasked). */
7298 /*60*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },
7299 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7300 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },
7301 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
7302 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
7303 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
7304 /*xcpt? */ true, true },
7305 };
7306
7307 static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
7308 {
7309 { bs3CpuInstr4_mulsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7310 { bs3CpuInstr4_mulsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7311
7312 { bs3CpuInstr4_vmulsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7313 { bs3CpuInstr4_vmulsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7314 };
7315 static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
7316 {
7317 { bs3CpuInstr4_mulsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7318 { bs3CpuInstr4_mulsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7319
7320 { bs3CpuInstr4_vmulsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7321 { bs3CpuInstr4_vmulsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7322 };
7323 static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
7324 {
7325 { bs3CpuInstr4_mulsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7326 { bs3CpuInstr4_mulsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7327
7328 { bs3CpuInstr4_vmulsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7329 { bs3CpuInstr4_vmulsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7330
7331 { bs3CpuInstr4_mulsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7332 { bs3CpuInstr4_mulsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7333
7334 { bs3CpuInstr4_vmulsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7335 { bs3CpuInstr4_vmulsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
7336 };
7337
7338 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
7339 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
7340 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
7341 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
7342}
7343
7344
7345/**
7346 * The 32-bit protected mode main function.
7347 *
7348 * The tests a driven by 32-bit test drivers, even for real-mode tests (though
7349 * we'll switch between PE32 and RM for each test step we perform). Given that
7350 * we test SSE and AVX here, we don't need to worry about 286 or 8086.
7351 *
7352 * Some extra steps needs to be taken to properly handle extended state in LM64
7353 * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode
7354 * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm).
7355 */
7356BS3_DECL(void) Main_pe32()
7357{
7358 static const BS3TESTMODEBYONEENTRY g_aTests[] =
7359 {
7360#if 1 /*ndef DEBUG_bird*/
7361# define ALL_TESTS
7362#endif
7363#if defined(ALL_TESTS)
7364 { "[v]addps", bs3CpuInstr4_v_addps, 0 },
7365 { "[v]addpd", bs3CpuInstr4_v_addpd, 0 },
7366 { "[v]addss", bs3CpuInstr4_v_addss, 0 },
7367 { "[v]addsd", bs3CpuInstr4_v_addsd, 0 },
7368 { "[v]haddps", bs3CpuInstr4_v_haddps, 0 },
7369 { "[v]haddpd", bs3CpuInstr4_v_haddpd, 0 },
7370 { "[v]subps", bs3CpuInstr4_v_subps, 0 },
7371 { "[v]subpd", bs3CpuInstr4_v_subpd, 0 },
7372 { "[v]subss", bs3CpuInstr4_v_subss, 0 },
7373 { "[v]subsd", bs3CpuInstr4_v_subsd, 0 },
7374 { "[v]mulps", bs3CpuInstr4_v_mulps, 0 },
7375 { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 },
7376 { "[v]mulss", bs3CpuInstr4_v_mulss, 0 },
7377 { "[v]mulsd", bs3CpuInstr4_v_mulsd, 0 },
7378#endif
7379 };
7380 Bs3TestInit("bs3-cpu-instr-4");
7381
7382 /*
7383 * Initialize globals.
7384 */
7385 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
7386 {
7387 uint32_t fEbx, fEcx, fEdx;
7388 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
7389 g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX);
7390 g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
7391 g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
7392 g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3);
7393 g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE);
7394 g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2);
7395 g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3);
7396 g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3);
7397 g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
7398 g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
7399 g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
7400 g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
7401 g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
7402 g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL)
7403 && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX);
7404
7405 if (ASMCpuId_EAX(0) >= 7)
7406 {
7407 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL);
7408 g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
7409 g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
7410 g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA);
7411 }
7412
7413 if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES)
7414 {
7415 ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
7416 g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
7417 g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A);
7418 g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
7419 }
7420 g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE];
7421
7422 /*
7423 * Figure out FPU save/restore method and support for DAZ bit.
7424 */
7425 {
7426 /** @todo Add bs3kit API to just get the ext ctx method without needing to
7427 * alloc/free a context. Replicating the logic in the bs3kit here, though
7428 * doable, runs a risk of not updating this when the other logic is
7429 * changed. */
7430 uint64_t fFlags;
7431 uint16_t const cbExtCtx = Bs3ExtCtxGetSize(&fFlags);
7432 PBS3EXTCTX pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cbExtCtx);
7433 if (pExtCtx)
7434 {
7435 Bs3ExtCtxInit(pExtCtx, cbExtCtx, fFlags);
7436 g_enmExtCtxMethod = pExtCtx->enmMethod;
7437 if ( ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_XSAVE
7438 && (pExtCtx->Ctx.x.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
7439 || ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_FXSAVE)
7440 && (pExtCtx->Ctx.x87.MXCSR_MASK & X86_MXCSR_DAZ)))
7441 g_fMxCsrDazSupported = true;
7442 }
7443 else
7444 Bs3TestFailedF("Failed to allocate %u bytes for extended CPU context (tiled addressable)\n", cbExtCtx);
7445 }
7446
7447 /*
7448 * Allocate a buffer for testing.
7449 */
7450 g_cbBuf = X86_PAGE_SIZE * 4;
7451 g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf);
7452 if (g_pbBuf)
7453 {
7454 g_pbBufAliasAlloc = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_TILED, g_cbBuf);
7455 if (g_pbBufAliasAlloc)
7456 {
7457 /*
7458 * Do the tests.
7459 */
7460 Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY);
7461#ifdef BS3_SKIPIT_DO_SKIP
7462 bs3CpuInstrX_ShowTallies();
7463#endif
7464 }
7465 else
7466 Bs3TestFailed("Failed to allocate 16K alias buffer (tiled addressable)");
7467 }
7468 else
7469 Bs3TestFailed("Failed to allocate 16K buffer (real mode addressable)");
7470 }
7471
7472 Bs3TestTerm();
7473}
7474
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