bs3-cpu-instr-x-regs.c32

Last change on this file was 106871, checked in by vboxsync, 3 months ago

ValidationKit/bootsectors: update instr-3 worker #1 to new SetReg scheme; bugref:9898; bugref:10658; jiraref:VBP-1306

define and use PASS_ELEMENTS() macro to reduce clutter
update bs3-cpu-instr-3 worker #1 to use new SetReg scheme
update 74 calling functions to use the new scheme
make Bs3ExtCtxSetReg() aware of MMX tag word control
update the other 7 workers for MMX tag word control

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

File size: 32.6 KB

Line
1	/* $Id: bs3-cpu-instr-x-regs.c32 106871 2024-11-07 15:41:52Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-instr-x - register reference constants & functions.
4	*/
5
6	/*
7	* Copyright (C) 2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* The contents of this file may alternatively be used under the terms
26	* of the Common Development and Distribution License Version 1.0
27	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	* in the VirtualBox distribution, in which case the provisions of the
29	* CDDL are applicable instead of those of the GPL.
30	*
31	* You may elect to license modified versions of this file under the
32	* terms and conditions of either the GPL or the CDDL or both.
33	*
34	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	*/
36
37	/**
38	* Includes preliminary / placeholder support (in terms of knowing their
39	* names and having space set aside) for AVX-512 registers ([XY]MM16..31,
40	* ZMM, and k0..7), which VirtualBox does not yet support; and Intel APX
41	* (R16..31) extended x86 general purpose registers -- which VirtualBox
42	* does not yet support and Intel are not yet shipping.
43	*
44	* 8-bit 'hi' register support not yet implemented (no clients).
45	*
46	* GPR register sizes returned by the size functions and set by the set
47	* function are 8 bytes in long mode, 4 bytes in other modes.
48	*
49	* Setting an 8, 16, or 32-bit GPR zeros out the higher bits.
50	*
51	* Setting a 128-bit XMM register zeros out the higher bits only if the
52	* fZeroYMMHi flag is set.
53	*/
54
55	/** Simple unadorned x86 family register names to be used in instruction test value tables. */
56
57	/** x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
58	* /====== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ======\
59	* 8-bit-L \| 0y \| AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B \|
60	* 8-bit-L-APX \| 1y \| R16B R17B R18B R19B R20B R21B R22B R23B R24B R25B R26B R27B R28B R29B R30B R31B \|
61	* 16-bit \| 2y \| AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W \|
62	* 16-bit-APX \| 3y \| R16W R17W R18W R19W R20W R21W R22W R23W R24W R25W R26W R27W R28W R29W R30W R31W \|
63	* 32-bit \| 4y \| EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D \|
64	* 32-bit-APX \| 5y \| R16D R17D R18D R19D R20D R21D R22D R23D R24D R25D R26D R27D R28D R29D R30D R31D \|
65	* 64-bit \| 6y \| RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 \|
66	* 64-bit-APX \| 7y \| R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 \|
67	* XMM \| 8y \| XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 \|
68	* XMM-AVX512 \| 9y \| XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 \|
69	* YMM \| Ay \| YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 \|
70	* YMM-AVX512 \| By \| YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 \|
71	* ZMM \| Cy \| ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 \|
72	* ZMM-AVX512 \| Dy \| ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 \|
73	* MMX / STn \| Ey/\| MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 --- --- --- --- --- --- --- --- \|
74	* OpMask-kx \| Ey\\| --- --- --- --- --- --- --- --- k0 k1 k2 k3 k4 k5 k6 k7 \|
75	* SEGREG \| Fy/\| CS DS ES FS GS SS --- --- --- --- --- --- --- --- --- --- \|
76	* 8-bit-H \| Fy\|\| --- --- --- --- --- --- --- --- AH CH DH BH --- --- --- --- \|
77	* Other/MEMREF \| Fy\\| --- --- --- --- --- --- xIP xFL --- --- --- --- NOREG (avail) FSxDI FSxBX \|
78	* \====== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== =====*/
79
80	/** These values are used in uint8_t fields; the TODO values are intended to break compilation. */
81
82	#define BS3_REGISTER_FAMILY_AVX512_TODO 0x1000
83	#define BS3_REGISTER_FAMILY_APX_TODO 0x2000
84	#define BS3_REGISTER_FAMILY_OTHER_TODO 0x3000
85
86	#define BS3_REGISTER_FAMILY_MASK 0xE0
87	#define BS3_REGISTER_REGISTER_MASK 0x1F
88	#define BS3_REGISTER_MASK (BS3_REGISTER_FAMILY_MASK \| BS3_REGISTER_REGISTER_MASK)
89
90	#define BS3_REGISTER_FAMILY_8BIT_L 0x00
91	#define AL (BS3_REGISTER_FAMILY_8BIT_L \| 0)
92	#define CL (BS3_REGISTER_FAMILY_8BIT_L \| 1)
93	#define DL (BS3_REGISTER_FAMILY_8BIT_L \| 2)
94	#define BL (BS3_REGISTER_FAMILY_8BIT_L \| 3)
95	#define SPL (BS3_REGISTER_FAMILY_8BIT_L \| 4)
96	#define BPL (BS3_REGISTER_FAMILY_8BIT_L \| 5)
97	#define SIL (BS3_REGISTER_FAMILY_8BIT_L \| 6)
98	#define DIL (BS3_REGISTER_FAMILY_8BIT_L \| 7)
99	#define R8B (BS3_REGISTER_FAMILY_8BIT_L \| 8)
100	#define R9B (BS3_REGISTER_FAMILY_8BIT_L \| 9)
101	#define R10B (BS3_REGISTER_FAMILY_8BIT_L \| 10)
102	#define R11B (BS3_REGISTER_FAMILY_8BIT_L \| 11)
103	#define R12B (BS3_REGISTER_FAMILY_8BIT_L \| 12)
104	#define R13B (BS3_REGISTER_FAMILY_8BIT_L \| 13)
105	#define R14B (BS3_REGISTER_FAMILY_8BIT_L \| 14)
106	#define R15B (BS3_REGISTER_FAMILY_8BIT_L \| 15)
107	#define BS3_REGISTER_FAMILY_8BIT_L_APX (0x10 \| BS3_REGISTER_FAMILY_APX_TODO)
108	#define R16B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 16)
109	#define R17B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 17)
110	#define R18B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 18)
111	#define R19B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 19)
112	#define R20B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 20)
113	#define R21B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 21)
114	#define R22B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 22)
115	#define R23B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 23)
116	#define R24B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 24)
117	#define R25B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 25)
118	#define R26B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 26)
119	#define R27B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 27)
120	#define R28B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 28)
121	#define R29B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 29)
122	#define R30B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 30)
123	#define R31B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 31)
124
125	#define BS3_REGISTER_FAMILY_16BIT 0x20
126	#define AX (BS3_REGISTER_FAMILY_16BIT \| 0)
127	#define CX (BS3_REGISTER_FAMILY_16BIT \| 1)
128	#define DX (BS3_REGISTER_FAMILY_16BIT \| 2)
129	#define BX (BS3_REGISTER_FAMILY_16BIT \| 3)
130	#define SP (BS3_REGISTER_FAMILY_16BIT \| 4)
131	#define BP (BS3_REGISTER_FAMILY_16BIT \| 5)
132	#define SI (BS3_REGISTER_FAMILY_16BIT \| 6)
133	#define DI (BS3_REGISTER_FAMILY_16BIT \| 7)
134	#define R8W (BS3_REGISTER_FAMILY_16BIT \| 8)
135	#define R9W (BS3_REGISTER_FAMILY_16BIT \| 9)
136	#define R10W (BS3_REGISTER_FAMILY_16BIT \| 10)
137	#define R11W (BS3_REGISTER_FAMILY_16BIT \| 11)
138	#define R12W (BS3_REGISTER_FAMILY_16BIT \| 12)
139	#define R13W (BS3_REGISTER_FAMILY_16BIT \| 13)
140	#define R14W (BS3_REGISTER_FAMILY_16BIT \| 14)
141	#define R15W (BS3_REGISTER_FAMILY_16BIT \| 15)
142	#define BS3_REGISTER_FAMILY_16BIT_APX (0x30 \| BS3_REGISTER_FAMILY_APX_TODO)
143	#define R16W (BS3_REGISTER_FAMILY_16BIT_APX \| 16)
144	#define R17W (BS3_REGISTER_FAMILY_16BIT_APX \| 17)
145	#define R18W (BS3_REGISTER_FAMILY_16BIT_APX \| 18)
146	#define R19W (BS3_REGISTER_FAMILY_16BIT_APX \| 19)
147	#define R20W (BS3_REGISTER_FAMILY_16BIT_APX \| 20)
148	#define R21W (BS3_REGISTER_FAMILY_16BIT_APX \| 21)
149	#define R22W (BS3_REGISTER_FAMILY_16BIT_APX \| 22)
150	#define R23W (BS3_REGISTER_FAMILY_16BIT_APX \| 23)
151	#define R24W (BS3_REGISTER_FAMILY_16BIT_APX \| 24)
152	#define R25W (BS3_REGISTER_FAMILY_16BIT_APX \| 25)
153	#define R26W (BS3_REGISTER_FAMILY_16BIT_APX \| 26)
154	#define R27W (BS3_REGISTER_FAMILY_16BIT_APX \| 27)
155	#define R28W (BS3_REGISTER_FAMILY_16BIT_APX \| 28)
156	#define R29W (BS3_REGISTER_FAMILY_16BIT_APX \| 29)
157	#define R30W (BS3_REGISTER_FAMILY_16BIT_APX \| 30)
158	#define R31W (BS3_REGISTER_FAMILY_16BIT_APX \| 31)
159
160	#define BS3_REGISTER_FAMILY_32BIT 0x40
161	#define EAX (BS3_REGISTER_FAMILY_32BIT \| 0)
162	#define ECX (BS3_REGISTER_FAMILY_32BIT \| 1)
163	#define EDX (BS3_REGISTER_FAMILY_32BIT \| 2)
164	#define EBX (BS3_REGISTER_FAMILY_32BIT \| 3)
165	#define ESP (BS3_REGISTER_FAMILY_32BIT \| 4)
166	#define EBP (BS3_REGISTER_FAMILY_32BIT \| 5)
167	#define ESI (BS3_REGISTER_FAMILY_32BIT \| 6)
168	#define EDI (BS3_REGISTER_FAMILY_32BIT \| 7)
169	#define R8D (BS3_REGISTER_FAMILY_32BIT \| 8)
170	#define R9D (BS3_REGISTER_FAMILY_32BIT \| 9)
171	#define R10D (BS3_REGISTER_FAMILY_32BIT \| 10)
172	#define R11D (BS3_REGISTER_FAMILY_32BIT \| 11)
173	#define R12D (BS3_REGISTER_FAMILY_32BIT \| 12)
174	#define R13D (BS3_REGISTER_FAMILY_32BIT \| 13)
175	#define R14D (BS3_REGISTER_FAMILY_32BIT \| 14)
176	#define R15D (BS3_REGISTER_FAMILY_32BIT \| 15)
177	#define BS3_REGISTER_FAMILY_32BIT_APX (0x50 \| BS3_REGISTER_FAMILY_APX_TODO)
178	#define R16D (BS3_REGISTER_FAMILY_32BIT_APX \| 16)
179	#define R17D (BS3_REGISTER_FAMILY_32BIT_APX \| 17)
180	#define R18D (BS3_REGISTER_FAMILY_32BIT_APX \| 18)
181	#define R19D (BS3_REGISTER_FAMILY_32BIT_APX \| 19)
182	#define R20D (BS3_REGISTER_FAMILY_32BIT_APX \| 20)
183	#define R21D (BS3_REGISTER_FAMILY_32BIT_APX \| 21)
184	#define R22D (BS3_REGISTER_FAMILY_32BIT_APX \| 22)
185	#define R23D (BS3_REGISTER_FAMILY_32BIT_APX \| 23)
186	#define R24D (BS3_REGISTER_FAMILY_32BIT_APX \| 24)
187	#define R25D (BS3_REGISTER_FAMILY_32BIT_APX \| 25)
188	#define R26D (BS3_REGISTER_FAMILY_32BIT_APX \| 26)
189	#define R27D (BS3_REGISTER_FAMILY_32BIT_APX \| 27)
190	#define R28D (BS3_REGISTER_FAMILY_32BIT_APX \| 28)
191	#define R29D (BS3_REGISTER_FAMILY_32BIT_APX \| 29)
192	#define R30D (BS3_REGISTER_FAMILY_32BIT_APX \| 30)
193	#define R31D (BS3_REGISTER_FAMILY_32BIT_APX \| 31)
194
195	#define BS3_REGISTER_FAMILY_64BIT 0x60
196	#define RAX (BS3_REGISTER_FAMILY_64BIT \| 0)
197	#define RCX (BS3_REGISTER_FAMILY_64BIT \| 1)
198	#define RDX (BS3_REGISTER_FAMILY_64BIT \| 2)
199	#define RBX (BS3_REGISTER_FAMILY_64BIT \| 3)
200	#define RSP (BS3_REGISTER_FAMILY_64BIT \| 4)
201	#define RBP (BS3_REGISTER_FAMILY_64BIT \| 5)
202	#define RSI (BS3_REGISTER_FAMILY_64BIT \| 6)
203	#define RDI (BS3_REGISTER_FAMILY_64BIT \| 7)
204	#define R8 (BS3_REGISTER_FAMILY_64BIT \| 8)
205	#define R9 (BS3_REGISTER_FAMILY_64BIT \| 9)
206	#define R10 (BS3_REGISTER_FAMILY_64BIT \| 10)
207	#define R11 (BS3_REGISTER_FAMILY_64BIT \| 11)
208	#define R12 (BS3_REGISTER_FAMILY_64BIT \| 12)
209	#define R13 (BS3_REGISTER_FAMILY_64BIT \| 13)
210	#define R14 (BS3_REGISTER_FAMILY_64BIT \| 14)
211	#define R15 (BS3_REGISTER_FAMILY_64BIT \| 15)
212	#define BS3_REGISTER_FAMILY_64BIT_APX (0x70 \| BS3_REGISTER_FAMILY_APX_TODO)
213	#define R16 (BS3_REGISTER_FAMILY_64BIT_APX \| 16)
214	#define R17 (BS3_REGISTER_FAMILY_64BIT_APX \| 17)
215	#define R18 (BS3_REGISTER_FAMILY_64BIT_APX \| 18)
216	#define R19 (BS3_REGISTER_FAMILY_64BIT_APX \| 19)
217	#define R20 (BS3_REGISTER_FAMILY_64BIT_APX \| 20)
218	#define R21 (BS3_REGISTER_FAMILY_64BIT_APX \| 21)
219	#define R22 (BS3_REGISTER_FAMILY_64BIT_APX \| 22)
220	#define R23 (BS3_REGISTER_FAMILY_64BIT_APX \| 23)
221	#define R24 (BS3_REGISTER_FAMILY_64BIT_APX \| 24)
222	#define R25 (BS3_REGISTER_FAMILY_64BIT_APX \| 25)
223	#define R26 (BS3_REGISTER_FAMILY_64BIT_APX \| 26)
224	#define R27 (BS3_REGISTER_FAMILY_64BIT_APX \| 27)
225	#define R28 (BS3_REGISTER_FAMILY_64BIT_APX \| 28)
226	#define R29 (BS3_REGISTER_FAMILY_64BIT_APX \| 29)
227	#define R30 (BS3_REGISTER_FAMILY_64BIT_APX \| 30)
228	#define R31 (BS3_REGISTER_FAMILY_64BIT_APX \| 31)
229
230	#define BS3_REGISTER_IS_GPR(reg) (((reg) & BS3_REGISTER_FAMILY_MASK) <= BS3_REGISTER_FAMILY_64BIT)
231
232	#define BS3_REGISTER_FAMILY_XMM 0x80
233	#define XMM0 (BS3_REGISTER_FAMILY_XMM \| 0)
234	#define XMM1 (BS3_REGISTER_FAMILY_XMM \| 1)
235	#define XMM2 (BS3_REGISTER_FAMILY_XMM \| 2)
236	#define XMM3 (BS3_REGISTER_FAMILY_XMM \| 3)
237	#define XMM4 (BS3_REGISTER_FAMILY_XMM \| 4)
238	#define XMM5 (BS3_REGISTER_FAMILY_XMM \| 5)
239	#define XMM6 (BS3_REGISTER_FAMILY_XMM \| 6)
240	#define XMM7 (BS3_REGISTER_FAMILY_XMM \| 7)
241	#define XMM8 (BS3_REGISTER_FAMILY_XMM \| 8)
242	#define XMM9 (BS3_REGISTER_FAMILY_XMM \| 9)
243	#define XMM10 (BS3_REGISTER_FAMILY_XMM \| 10)
244	#define XMM11 (BS3_REGISTER_FAMILY_XMM \| 11)
245	#define XMM12 (BS3_REGISTER_FAMILY_XMM \| 12)
246	#define XMM13 (BS3_REGISTER_FAMILY_XMM \| 13)
247	#define XMM14 (BS3_REGISTER_FAMILY_XMM \| 14)
248	#define XMM15 (BS3_REGISTER_FAMILY_XMM \| 15)
249	#define BS3_REGISTER_FAMILY_XMM_512 (0x90 \| BS3_REGISTER_FAMILY_AVX512_TODO)
250	#define XMM16 (BS3_REGISTER_FAMILY_XMM_512 \| 16)
251	#define XMM17 (BS3_REGISTER_FAMILY_XMM_512 \| 17)
252	#define XMM18 (BS3_REGISTER_FAMILY_XMM_512 \| 18)
253	#define XMM19 (BS3_REGISTER_FAMILY_XMM_512 \| 19)
254	#define XMM20 (BS3_REGISTER_FAMILY_XMM_512 \| 20)
255	#define XMM21 (BS3_REGISTER_FAMILY_XMM_512 \| 21)
256	#define XMM22 (BS3_REGISTER_FAMILY_XMM_512 \| 22)
257	#define XMM23 (BS3_REGISTER_FAMILY_XMM_512 \| 23)
258	#define XMM24 (BS3_REGISTER_FAMILY_XMM_512 \| 24)
259	#define XMM25 (BS3_REGISTER_FAMILY_XMM_512 \| 25)
260	#define XMM26 (BS3_REGISTER_FAMILY_XMM_512 \| 26)
261	#define XMM27 (BS3_REGISTER_FAMILY_XMM_512 \| 27)
262	#define XMM28 (BS3_REGISTER_FAMILY_XMM_512 \| 28)
263	#define XMM29 (BS3_REGISTER_FAMILY_XMM_512 \| 29)
264	#define XMM30 (BS3_REGISTER_FAMILY_XMM_512 \| 30)
265	#define XMM31 (BS3_REGISTER_FAMILY_XMM_512 \| 31)
266
267	#define BS3_REGISTER_FAMILY_YMM 0xA0
268	#define YMM0 (BS3_REGISTER_FAMILY_YMM \| 0)
269	#define YMM1 (BS3_REGISTER_FAMILY_YMM \| 1)
270	#define YMM2 (BS3_REGISTER_FAMILY_YMM \| 2)
271	#define YMM3 (BS3_REGISTER_FAMILY_YMM \| 3)
272	#define YMM4 (BS3_REGISTER_FAMILY_YMM \| 4)
273	#define YMM5 (BS3_REGISTER_FAMILY_YMM \| 5)
274	#define YMM6 (BS3_REGISTER_FAMILY_YMM \| 6)
275	#define YMM7 (BS3_REGISTER_FAMILY_YMM \| 7)
276	#define YMM8 (BS3_REGISTER_FAMILY_YMM \| 8)
277	#define YMM9 (BS3_REGISTER_FAMILY_YMM \| 9)
278	#define YMM10 (BS3_REGISTER_FAMILY_YMM \| 10)
279	#define YMM11 (BS3_REGISTER_FAMILY_YMM \| 11)
280	#define YMM12 (BS3_REGISTER_FAMILY_YMM \| 12)
281	#define YMM13 (BS3_REGISTER_FAMILY_YMM \| 13)
282	#define YMM14 (BS3_REGISTER_FAMILY_YMM \| 14)
283	#define YMM15 (BS3_REGISTER_FAMILY_YMM \| 15)
284	#define BS3_REGISTER_FAMILY_YMM_512 (0xB0 \| BS3_REGISTER_FAMILY_AVX512_TODO)
285	#define YMM16 (BS3_REGISTER_FAMILY_YMM_512 \| 16)
286	#define YMM17 (BS3_REGISTER_FAMILY_YMM_512 \| 17)
287	#define YMM18 (BS3_REGISTER_FAMILY_YMM_512 \| 18)
288	#define YMM19 (BS3_REGISTER_FAMILY_YMM_512 \| 19)
289	#define YMM20 (BS3_REGISTER_FAMILY_YMM_512 \| 20)
290	#define YMM21 (BS3_REGISTER_FAMILY_YMM_512 \| 21)
291	#define YMM22 (BS3_REGISTER_FAMILY_YMM_512 \| 22)
292	#define YMM23 (BS3_REGISTER_FAMILY_YMM_512 \| 23)
293	#define YMM24 (BS3_REGISTER_FAMILY_YMM_512 \| 24)
294	#define YMM25 (BS3_REGISTER_FAMILY_YMM_512 \| 25)
295	#define YMM26 (BS3_REGISTER_FAMILY_YMM_512 \| 26)
296	#define YMM27 (BS3_REGISTER_FAMILY_YMM_512 \| 27)
297	#define YMM28 (BS3_REGISTER_FAMILY_YMM_512 \| 28)
298	#define YMM29 (BS3_REGISTER_FAMILY_YMM_512 \| 29)
299	#define YMM30 (BS3_REGISTER_FAMILY_YMM_512 \| 30)
300	#define YMM31 (BS3_REGISTER_FAMILY_YMM_512 \| 31)
301
302	#define BS3_REGISTER_FAMILY_ZMM 0xC0
303	#define BS3_REGISTER_FAMILY_ZMM_LOW (0xC0 \| BS3_REGISTER_FAMILY_AVX512_TODO)
304	#define ZMM0 (BS3_REGISTER_FAMILY_ZMM_LOW \| 0)
305	#define ZMM1 (BS3_REGISTER_FAMILY_ZMM_LOW \| 1)
306	#define ZMM2 (BS3_REGISTER_FAMILY_ZMM_LOW \| 2)
307	#define ZMM3 (BS3_REGISTER_FAMILY_ZMM_LOW \| 3)
308	#define ZMM4 (BS3_REGISTER_FAMILY_ZMM_LOW \| 4)
309	#define ZMM5 (BS3_REGISTER_FAMILY_ZMM_LOW \| 5)
310	#define ZMM6 (BS3_REGISTER_FAMILY_ZMM_LOW \| 6)
311	#define ZMM7 (BS3_REGISTER_FAMILY_ZMM_LOW \| 7)
312	#define ZMM8 (BS3_REGISTER_FAMILY_ZMM_LOW \| 8)
313	#define ZMM9 (BS3_REGISTER_FAMILY_ZMM_LOW \| 9)
314	#define ZMM10 (BS3_REGISTER_FAMILY_ZMM_LOW \| 10)
315	#define ZMM11 (BS3_REGISTER_FAMILY_ZMM_LOW \| 11)
316	#define ZMM12 (BS3_REGISTER_FAMILY_ZMM_LOW \| 12)
317	#define ZMM13 (BS3_REGISTER_FAMILY_ZMM_LOW \| 13)
318	#define ZMM14 (BS3_REGISTER_FAMILY_ZMM_LOW \| 14)
319	#define ZMM15 (BS3_REGISTER_FAMILY_ZMM_LOW \| 15)
320	#define BS3_REGISTER_FAMILY_ZMM_512 (0xD0 \| BS3_REGISTER_FAMILY_AVX512_TODO)
321	#define ZMM16 (BS3_REGISTER_FAMILY_ZMM_512 \| 16)
322	#define ZMM17 (BS3_REGISTER_FAMILY_ZMM_512 \| 17)
323	#define ZMM18 (BS3_REGISTER_FAMILY_ZMM_512 \| 18)
324	#define ZMM19 (BS3_REGISTER_FAMILY_ZMM_512 \| 19)
325	#define ZMM20 (BS3_REGISTER_FAMILY_ZMM_512 \| 20)
326	#define ZMM21 (BS3_REGISTER_FAMILY_ZMM_512 \| 21)
327	#define ZMM22 (BS3_REGISTER_FAMILY_ZMM_512 \| 22)
328	#define ZMM23 (BS3_REGISTER_FAMILY_ZMM_512 \| 23)
329	#define ZMM24 (BS3_REGISTER_FAMILY_ZMM_512 \| 24)
330	#define ZMM25 (BS3_REGISTER_FAMILY_ZMM_512 \| 25)
331	#define ZMM26 (BS3_REGISTER_FAMILY_ZMM_512 \| 26)
332	#define ZMM27 (BS3_REGISTER_FAMILY_ZMM_512 \| 27)
333	#define ZMM28 (BS3_REGISTER_FAMILY_ZMM_512 \| 28)
334	#define ZMM29 (BS3_REGISTER_FAMILY_ZMM_512 \| 29)
335	#define ZMM30 (BS3_REGISTER_FAMILY_ZMM_512 \| 30)
336	#define ZMM31 (BS3_REGISTER_FAMILY_ZMM_512 \| 31)
337
338	#define BS3_REGISTER_FAMILY_OTHER 0xE0
339	#define BS3_REGISTER_FAMILY_MMX 0xE0
340	#define MM0 (BS3_REGISTER_FAMILY_MMX \| 0)
341	#define MM1 (BS3_REGISTER_FAMILY_MMX \| 1)
342	#define MM2 (BS3_REGISTER_FAMILY_MMX \| 2)
343	#define MM3 (BS3_REGISTER_FAMILY_MMX \| 3)
344	#define MM4 (BS3_REGISTER_FAMILY_MMX \| 4)
345	#define MM5 (BS3_REGISTER_FAMILY_MMX \| 5)
346	#define MM6 (BS3_REGISTER_FAMILY_MMX \| 6)
347	#define MM7 (BS3_REGISTER_FAMILY_MMX \| 7)
348	#define BS3_REGISTER_IS_MMX(uReg) ((uReg) >= MM0 && (uReg) <= MM7)
349
350	#define BS3_REGISTER_FAMILY_OPMASK (0xE8 \| BS3_REGISTER_FAMILY_AVX512_TODO)
351	#define k0 (BS3_REGISTER_FAMILY_OPMASK \| 0)
352	#define k1 (BS3_REGISTER_FAMILY_OPMASK \| 1)
353	#define k2 (BS3_REGISTER_FAMILY_OPMASK \| 2)
354	#define k3 (BS3_REGISTER_FAMILY_OPMASK \| 3)
355	#define k4 (BS3_REGISTER_FAMILY_OPMASK \| 4)
356	#define k5 (BS3_REGISTER_FAMILY_OPMASK \| 5)
357	#define k6 (BS3_REGISTER_FAMILY_OPMASK \| 6)
358	#define k7 (BS3_REGISTER_FAMILY_OPMASK \| 7)
359
360	#define BS3_REGISTER_FAMILY_SEGREG (0xF0 \| BS3_REGISTER_FAMILY_OTHER_TODO)
361	#define ES (BS3_REGISTER_FAMILY_SEGREG \| 0)
362	#define CS (BS3_REGISTER_FAMILY_SEGREG \| 1)
363	#define SS (BS3_REGISTER_FAMILY_SEGREG \| 2)
364	#define DS (BS3_REGISTER_FAMILY_SEGREG \| 3)
365	#define FS (BS3_REGISTER_FAMILY_SEGREG \| 4)
366	#define GS (BS3_REGISTER_FAMILY_SEGREG \| 5)
367
368	#define BS3_REGISTER_FAMILY_IP (0xF5 \| BS3_REGISTER_FAMILY_OTHER_TODO)
369	#define IP BS3_REGISTER_FAMILY_IP
370	#define EIP BS3_REGISTER_FAMILY_IP
371	#define RIP BS3_REGISTER_FAMILY_IP
372	#define xIP BS3_REGISTER_FAMILY_IP
373
374	#define BS3_REGISTER_FAMILY_FL (0xF6 \| BS3_REGISTER_FAMILY_OTHER_TODO)
375	#define FL BS3_REGISTER_FAMILY_FL
376	#define EFL BS3_REGISTER_FAMILY_FL
377	#define RFL BS3_REGISTER_FAMILY_FL
378	#define xFL BS3_REGISTER_FAMILY_FL
379
380	#define BS3_REGISTER_FAMILY_8BIT_H (0xE8 \| BS3_REGISTER_FAMILY_OTHER_TODO)
381	#define AH (BS3_REGISTER_FAMILY_8BIT_H \| 0)
382	#define CH (BS3_REGISTER_FAMILY_8BIT_H \| 1)
383	#define DH (BS3_REGISTER_FAMILY_8BIT_H \| 2)
384	#define BH (BS3_REGISTER_FAMILY_8BIT_H \| 3)
385
386	#define NOREG 0xFC
387
388	#define BS3_REGISTER_FAMILY_MEMREF 0xFE
389	#define FSxDI (BS3_REGISTER_FAMILY_MEMREF \| 0)
390	#define FSxBX (BS3_REGISTER_FAMILY_MEMREF \| 1)
391
392	#define BS3_REGISTER_FLAG_MEMREF 0x100
393	#define BS3_FSxREG(reg) (((reg) == FSxBX \|\| (reg) == FSxDI) ? reg : ((reg) & BS3_REGISTER_REGISTER_MASK) \| BS3_REGISTER_FLAG_MEMREF)
394	#define BS3_REGISTER_IS_MEMREF(reg) (((reg) & BS3_REGISTER_FLAG_MEMREF) \|\| (((reg) & BS3_REGISTER_FAMILY_MEMREF) == BS3_REGISTER_FAMILY_MEMREF))
395	#define BS3_REGISTER_MEMREF_TO(reg) (((reg) == FSxBX ? BX : (reg) == FSxDI ? DI : (reg)) & BS3_REGISTER_REGISTER_MASK)
396
397	#define BS3_REGISTER_NAME_MAXSIZE sizeof("FSx(avail)")
398
399	/**
400	* Get the name of a register from its identity value used in instruction test value tables.
401	*
402	* @returns Name of register.
403	* @param pszBuf Where to store the name.
404	* @param cchBuf The size of the buffer.
405	* @param uReg The register identity value.
406	*/
407	static size_t bs3CpuInstrXGetRegisterName(char BS3_FAR *pszBuf, size_t cchBuf, uint16_t uReg)
408	{
409	const uint8_t uRegNum = uReg & BS3_REGISTER_REGISTER_MASK;
410	const uint8_t uRegSet = uReg & BS3_REGISTER_FAMILY_MASK;
411	static const char * const s_apsz8bitLNames[] = { "AL", "CL", "DL", "BL", "SPL", "BPL", "SIL", "DIL" };
412	static const char * const s_apsz16bitNames[] = { "AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI" };
413	static const char * const s_apszOtherNames[] = { "MM0", "MM1", "MM2", "MM3", "MM4", "MM5", "MM6", "MM7",
414	"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
415	"CS", "DS", "ES", "FS", "GS", "SS",
416	"xIP", "xFL",
417	"AH", "CH", "DH", "BH",
418	"NOREG", "(avail)", "FSxDI", "FSxBX" };
419	BS3_ASSERT(cchBuf >= BS3_REGISTER_NAME_MAXSIZE);
420
421	if (uReg & BS3_REGISTER_FLAG_MEMREF)
422	{
423	char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
424
425	bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg & BS3_REGISTER_MASK);
426	return Bs3StrPrintf(pszBuf, cchBuf, "FSx%s", pszRegName);
427	}
428
429	switch (uRegSet) {
430	case BS3_REGISTER_FAMILY_8BIT_L:
431	if (uRegNum < RT_ELEMENTS(s_apsz8bitLNames))
432	return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apsz8bitLNames[uRegNum]);
433	else
434	return Bs3StrPrintf(pszBuf, cchBuf, "R%dB", uRegNum);
435	case BS3_REGISTER_FAMILY_16BIT:
436	if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
437	return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apsz16bitNames[uRegNum]);
438	else
439	return Bs3StrPrintf(pszBuf, cchBuf, "R%dW", uRegNum);
440	case BS3_REGISTER_FAMILY_32BIT:
441	if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
442	return Bs3StrPrintf(pszBuf, cchBuf, "E%s", s_apsz16bitNames[uRegNum]);
443	else
444	return Bs3StrPrintf(pszBuf, cchBuf, "R%dD", uRegNum);
445	case BS3_REGISTER_FAMILY_64BIT:
446	if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
447	return Bs3StrPrintf(pszBuf, cchBuf, "R%s", s_apsz16bitNames[uRegNum]);
448	else
449	return Bs3StrPrintf(pszBuf, cchBuf, "R%d", uRegNum);
450	case BS3_REGISTER_FAMILY_XMM:
451	return Bs3StrPrintf(pszBuf, cchBuf, "XMM%d", uRegNum);
452	case BS3_REGISTER_FAMILY_YMM:
453	return Bs3StrPrintf(pszBuf, cchBuf, "YMM%d", uRegNum);
454	case BS3_REGISTER_FAMILY_ZMM:
455	return Bs3StrPrintf(pszBuf, cchBuf, "ZMM%d", uRegNum);
456	case BS3_REGISTER_FAMILY_OTHER:
457	return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apszOtherNames[uRegNum]);
458	}
459	return Bs3StrPrintf(pszBuf, cchBuf, "(?%02X?)", uReg);
460	}
461
462	typedef struct BS3SETREGCTX
463	{
464	/** Pointer to test context. */
465	PBS3EXTCTX pExtCtx;
466	/** Pointer to register context; for BS3_REGISTER_FAMILY_MEMREF, all GPR families */
467	PBS3REGCTX pCtx;
468	/** Whether to zero YMM-high bits when setting XMM; for BS3_REGISTER_FAMILY_XMM */
469	bool fZeroYMMHi;
470	/** Tag word control: BS3EXTCTXTOPMM_{ZERO,SET,AS_IS}; for BS3_REGISTER_FAMILY_MMX */
471	BS3EXTCTXTOPMM enmTop;
472	/** Current execution mode; for BS3_REGISTER_FAMILY_64BIT */
473	uint8_t bMode;
474	} BS3SETREGCTX;
475	typedef BS3SETREGCTX BS3_FAR *PBS3SETREGCTX;
476
477	/**
478	* Initialize a SetReg context to reasonable values.
479	*
480	* @param pSetRegCtx The context to initialize.
481	* @param pExtCtx Pointer to test context.
482	* @param pCtx Pointer to register context.
483	* @param bMode Current execution mode.
484	*/
485	static void bs3CpuInstrXGetRegisterInit(PBS3SETREGCTX pSetRegCtx, PBS3EXTCTX pExtCtx, PBS3REGCTX pCtx, uint8_t bMode)
486	{
487	pSetRegCtx->pExtCtx = pExtCtx;
488	pSetRegCtx->pCtx = pCtx;
489	pSetRegCtx->bMode = bMode;
490	pSetRegCtx->fZeroYMMHi = false;
491	pSetRegCtx->enmTop = BS3EXTCTXTOPMM_ZERO;
492	}
493
494	/**
495	* Get the size of a register from its identity value used in instruction test value tables.
496	* This returns the size of sub-registers, e.g. AL = 1.
497	*
498	* @param pSetRegCtx Arguments to this function (see below).
499	* @param uReg The register identity value to report on.
500	* @returns size_t Size of register in bytes; 0 for currently unsupported registers.
501	*/
502	static size_t bs3CpuInstrXGetRegisterSize(PBS3SETREGCTX pSetRegCtx, uint16_t uReg)
503	{
504	switch (uReg & BS3_REGISTER_FAMILY_MASK)
505	{
506	case BS3_REGISTER_FAMILY_8BIT_L:
507	return 1;
508	case BS3_REGISTER_FAMILY_16BIT:
509	return 2;
510	case BS3_REGISTER_FAMILY_32BIT:
511	return 4;
512	case BS3_REGISTER_FAMILY_64BIT:
513	return 8;
514	case BS3_REGISTER_FAMILY_XMM:
515	return 16;
516	case BS3_REGISTER_FAMILY_YMM:
517	return 32;
518	case BS3_REGISTER_FAMILY_OTHER:
519	if (BS3_REGISTER_IS_MMX(uReg))
520	return 8;
521	}
522	return 0;
523	}
524
525	/**
526	* Get the full size of a register from its identity value used in instruction test value tables.
527	* This returns the full size of the register containing a sub-register, e.g. AL = 4 or 8.
528	*
529	* @param pSetRegCtx Arguments to this function (see below).
530	* @param uReg The register identity value to report on.
531	* @returns size_t Size of register in bytes; 0 for currently unsupported registers.
532	*/
533	static size_t bs3CpuInstrXGetRegisterFullSize(PBS3SETREGCTX pSetRegCtx, uint16_t uReg)
534	{
535	if (BS3_REGISTER_IS_GPR(uReg))
536	return BS3_MODE_IS_64BIT_CODE(pSetRegCtx->bMode) ? 8 : 4;
537	return bs3CpuInstrXGetRegisterSize(pSetRegCtx, uReg);
538	}
539
540	/**
541	* Set a register within a testing context. Intended to support a broad
542	* range of register types; currently supports MMX, XMM, YMM, and general
543	* purpose registers (except 8-bit sub-registers); and setting up FS:xGPR
544	* for memory reference operations.
545	*
546	* Other regs known to this subsystem are either so far unused by
547	* VirtualBox (ZMM, k[0-7], GPRs >15); or not used by tests which call
548	* this (8-bit sub-registers, segment registers, xIP, xFL).
549	*
550	* @param pSetRegCtx Arguments to this function (see below).
551	* @param uReg The register identity value to modify within that context.
552	* @param pu256Val Pointer to the data to store there.
553	* @returns bool Whether the store succeeded (currently ignored by callers).
554	*/
555
556	static bool Bs3ExtCtxSetReg_int(PBS3SETREGCTX pSetRegCtx, uint16_t uReg, PCRTUINT256U pu256Val)
557	{
558	uint8_t uRegNum = uReg & BS3_REGISTER_REGISTER_MASK;
559	uint8_t uRegSet = uReg & BS3_REGISTER_FAMILY_MASK;
560	char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
561
562	if (BS3_REGISTER_IS_MEMREF(uReg))
563	{
564	if (uReg == FSxBX \|\| uReg == FSxDI \|\| uRegSet <= BS3_REGISTER_FAMILY_64BIT)
565	uRegNum = BS3_REGISTER_MEMREF_TO(uReg);
566	else
567	uRegNum = 255; /* Fall through to error handling below to complain about 'FSxZMM31' or whatever */
568	uRegSet = BS3_REGISTER_FAMILY_MEMREF;
569	}
570
571	if (uRegNum < 16)
572	{
573	switch (uRegSet)
574	{
575	case BS3_REGISTER_FAMILY_8BIT_L:
576	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au8[0], bs3CpuInstrXGetRegisterFullSize(pSetRegCtx, uReg));
577	case BS3_REGISTER_FAMILY_16BIT:
578	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au16[0], bs3CpuInstrXGetRegisterFullSize(pSetRegCtx, uReg));
579	case BS3_REGISTER_FAMILY_32BIT:
580	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au32[0], bs3CpuInstrXGetRegisterFullSize(pSetRegCtx, uReg));
581	case BS3_REGISTER_FAMILY_64BIT:
582	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au64[0], bs3CpuInstrXGetRegisterFullSize(pSetRegCtx, uReg));
583	case BS3_REGISTER_FAMILY_XMM:
584	if (pSetRegCtx->fZeroYMMHi)
585	return Bs3ExtCtxSetXmm(pSetRegCtx->pExtCtx, uRegNum, &pu256Val->au128[0]);
586	else
587	return Bs3ExtCtxSetYmm(pSetRegCtx->pExtCtx, uRegNum, pu256Val, 16);
588	case BS3_REGISTER_FAMILY_YMM:
589	return Bs3ExtCtxSetYmm(pSetRegCtx->pExtCtx, uRegNum, pu256Val, 32);
590	case BS3_REGISTER_FAMILY_MEMREF:
591	Bs3RegCtxSetGrpSegFromCurPtr(pSetRegCtx->pCtx, (&pSetRegCtx->pCtx->rax) + uRegNum, &pSetRegCtx->pCtx->fs, (void *)pu256Val);
592	return true;
593	case BS3_REGISTER_FAMILY_OTHER:
594	if (BS3_REGISTER_IS_MMX(uReg))
595	return Bs3ExtCtxSetMm(pSetRegCtx->pExtCtx, uRegNum, pu256Val->au64[0], pSetRegCtx->enmTop);
596	break;
597	case BS3_REGISTER_FAMILY_ZMM:
598	default:
599	break;
600
601	}
602	}
603	if (uReg == NOREG)
604	return true;
605
606	bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg);
607	return Bs3TestFailedF("Bs3ExtCtxSetReg() todo: handle register '%s' (%02X)", pszRegName, uReg);
608	}
609
610	static bool g_fSetRegVerbose = false;
611
612	static bool Bs3ExtCtxSetReg(PBS3SETREGCTX pSetRegCtx, uint16_t uReg, PCRTUINT256U pu256Val)
613	{
614	bool fRet = Bs3ExtCtxSetReg_int(pSetRegCtx, uReg, pu256Val);
615
616	if (g_fSetRegVerbose)
617	{
618	char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
619	char pszValBuf[80] = "(not decoded)";
620
621	switch (uReg & BS3_REGISTER_FAMILY_MASK)
622	{
623	case BS3_REGISTER_FAMILY_8BIT_L:
624	Bs3StrPrintf(pszValBuf, 80, "%#04RX8", pu256Val->au8[0]);
625	break;
626	case BS3_REGISTER_FAMILY_16BIT:
627	Bs3StrPrintf(pszValBuf, 80, "%#06RX16", pu256Val->au16[0]);
628	break;
629	case BS3_REGISTER_FAMILY_32BIT:
630	Bs3StrPrintf(pszValBuf, 80, "%#10RX32", pu256Val->au32[0]);
631	break;
632	case BS3_REGISTER_FAMILY_64BIT:
633	Bs3StrPrintf(pszValBuf, 80, "%#18RX64", pu256Val->au64[0]);
634	break;
635	case BS3_REGISTER_FAMILY_XMM:
636	Bs3StrPrintf(pszValBuf, 80, "%#18RX64:%#18RX64", pu256Val->au64[1], pu256Val->au64[0]);
637	break;
638	case BS3_REGISTER_FAMILY_YMM:
639	Bs3StrPrintf(pszValBuf, 80, "%#18RX64:%#18RX64:%#18RX64:%#18RX64", pu256Val->au64[3], pu256Val->au64[2], pu256Val->au64[1], pu256Val->au64[0]);
640	break;
641	case BS3_REGISTER_FAMILY_OTHER:
642	if (BS3_REGISTER_IS_MMX(uReg))
643	Bs3StrPrintf(pszValBuf, 80, "%#18RX64", pu256Val->au64[0]);
644	break;
645	default:
646	break;
647	}
648	bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg);
649	Bs3TestPrintf("Bs3ExtCtxSetReg '%s' to '%s'; %s\n", pszRegName, pszValBuf, fRet ? "worked" : "failed");
650	}
651	return fRet;
652	}

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