bs3-cpu-instr-x-regs.c32@ 106854

Last change on this file since 106854 was 106736, checked in by vboxsync, 3 months ago

ValidationKit/bootsectors: some cleanup; bugref:9898; bugref:10658; jiraref:VBP-1206

update bs3-cpu-instr-3 worker #6 to use new SetReg scheme
replace misnamed _NORM_SAFE_INT_MIN with equivalent _NORM_MIN values
add BS3_REGISTER_IS_MEMREF(), BS3_REGISTER_MEMREF_TO() macros

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

File size: 29.5 KB

Line
1	/* $Id: bs3-cpu-instr-x-regs.c32 106736 2024-10-28 08:11:30Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-instr-x - register reference constants & functions.
4	*/
5
6	/*
7	* Copyright (C) 2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* The contents of this file may alternatively be used under the terms
26	* of the Common Development and Distribution License Version 1.0
27	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	* in the VirtualBox distribution, in which case the provisions of the
29	* CDDL are applicable instead of those of the GPL.
30	*
31	* You may elect to license modified versions of this file under the
32	* terms and conditions of either the GPL or the CDDL or both.
33	*
34	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	*/
36
37	/** Simple unadorned x86 family register names to be used in instruction test value tables. */
38
39	/**
40	* Includes preliminary / placeholder support (in terms of knowing their
41	* names and having space set aside) for AVX-512 registers ([XY]MM16..31,
42	* ZMM, and k0..7), which VirtualBox does not yet support; and Intel APX
43	* (R16..31) extended x86 general purpose registers -- which VirtualBox
44	* does not yet support and Intel are not yet shipping.
45	*/
46
47	/** x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
48	* /====== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ======\
49	* 8-bit-L \| 0y \| AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B \|
50	* 8-bit-L-APX \| 1y \| R16B R17B R18B R19B R20B R21B R22B R23B R24B R25B R26B R27B R28B R29B R30B R31B \|
51	* 16-bit \| 2y \| AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W \|
52	* 16-bit-APX \| 3y \| R16W R17W R18W R19W R20W R21W R22W R23W R24W R25W R26W R27W R28W R29W R30W R31W \|
53	* 32-bit \| 4y \| EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D \|
54	* 32-bit-APX \| 5y \| R16D R17D R18D R19D R20D R21D R22D R23D R24D R25D R26D R27D R28D R29D R30D R31D \|
55	* 64-bit \| 6y \| RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 \|
56	* 64-bit-APX \| 7y \| R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 \|
57	* XMM \| 8y \| XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 \|
58	* XMM-AVX512 \| 9y \| XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 \|
59	* YMM \| Ay \| YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 \|
60	* YMM-AVX512 \| By \| YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 \|
61	* ZMM \| Cy \| ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 \|
62	* ZMM-AVX512 \| Dy \| ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 \|
63	* MMX / STn \| Ey/\| MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 --- --- --- --- --- --- --- --- \|
64	* OpMask-kx \| Ey\\| --- --- --- --- --- --- --- --- k0 k1 k2 k3 k4 k5 k6 k7 \|
65	* SEGREG \| Fy/\| CS DS ES FS GS SS --- --- --- --- --- --- --- --- --- --- \|
66	* 8-bit-H \| Fy\|\| --- --- --- --- --- --- --- --- AH CH DH BH --- --- --- --- \|
67	* Other/MEMREF \| Fy\\| --- --- --- --- --- --- xIP xFL --- --- --- --- NOREG (avail) FSxDI FSxBX \|
68	* \====== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== =====*/
69
70	/** These values are used in uint8_t fields; the TODO values are intended to break compilation. */
71
72	#define BS3_REGISTER_FAMILY_AVX512_TODO 0x1000
73	#define BS3_REGISTER_FAMILY_APX_TODO 0x2000
74	#define BS3_REGISTER_FAMILY_OTHER_TODO 0x3000
75
76	#define BS3_REGISTER_FAMILY_MASK 0xE0
77	#define BS3_REGISTER_REGISTER_MASK 0x1F
78	#define BS3_REGISTER_MASK (BS3_REGISTER_FAMILY_MASK \| BS3_REGISTER_REGISTER_MASK)
79
80	#define BS3_REGISTER_FAMILY_8BIT_L 0x00
81	#define BS3_REGISTER_FAMILY_8BIT_L_LOW (0x00 \| BS3_REGISTER_FAMILY_OTHER_TODO)
82	#define AL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 0)
83	#define CL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 1)
84	#define DL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 2)
85	#define BL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 3)
86	#define SPL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 4)
87	#define BPL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 5)
88	#define SIL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 6)
89	#define DIL (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 7)
90	#define R8B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 8)
91	#define R9B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 9)
92	#define R10B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 10)
93	#define R11B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 11)
94	#define R12B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 12)
95	#define R13B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 13)
96	#define R14B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 14)
97	#define R15B (BS3_REGISTER_FAMILY_8BIT_L_LOW \| 15)
98	#define BS3_REGISTER_FAMILY_8BIT_L_APX (0x10 \| BS3_REGISTER_FAMILY_APX_TODO)
99	#define R16B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 16)
100	#define R17B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 17)
101	#define R18B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 18)
102	#define R19B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 19)
103	#define R20B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 20)
104	#define R21B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 21)
105	#define R22B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 22)
106	#define R23B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 23)
107	#define R24B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 24)
108	#define R25B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 25)
109	#define R26B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 26)
110	#define R27B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 27)
111	#define R28B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 28)
112	#define R29B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 29)
113	#define R30B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 30)
114	#define R31B (BS3_REGISTER_FAMILY_8BIT_L_APX \| 31)
115
116	#define BS3_REGISTER_FAMILY_16BIT 0x20
117	#define AX (BS3_REGISTER_FAMILY_16BIT \| 0)
118	#define CX (BS3_REGISTER_FAMILY_16BIT \| 1)
119	#define DX (BS3_REGISTER_FAMILY_16BIT \| 2)
120	#define BX (BS3_REGISTER_FAMILY_16BIT \| 3)
121	#define SP (BS3_REGISTER_FAMILY_16BIT \| 4)
122	#define BP (BS3_REGISTER_FAMILY_16BIT \| 5)
123	#define SI (BS3_REGISTER_FAMILY_16BIT \| 6)
124	#define DI (BS3_REGISTER_FAMILY_16BIT \| 7)
125	#define R8W (BS3_REGISTER_FAMILY_16BIT \| 8)
126	#define R9W (BS3_REGISTER_FAMILY_16BIT \| 9)
127	#define R10W (BS3_REGISTER_FAMILY_16BIT \| 10)
128	#define R11W (BS3_REGISTER_FAMILY_16BIT \| 11)
129	#define R12W (BS3_REGISTER_FAMILY_16BIT \| 12)
130	#define R13W (BS3_REGISTER_FAMILY_16BIT \| 13)
131	#define R14W (BS3_REGISTER_FAMILY_16BIT \| 14)
132	#define R15W (BS3_REGISTER_FAMILY_16BIT \| 15)
133	#define BS3_REGISTER_FAMILY_16BIT_APX (0x30 \| BS3_REGISTER_FAMILY_APX_TODO)
134	#define R16W (BS3_REGISTER_FAMILY_16BIT_APX \| 16)
135	#define R17W (BS3_REGISTER_FAMILY_16BIT_APX \| 17)
136	#define R18W (BS3_REGISTER_FAMILY_16BIT_APX \| 18)
137	#define R19W (BS3_REGISTER_FAMILY_16BIT_APX \| 19)
138	#define R20W (BS3_REGISTER_FAMILY_16BIT_APX \| 20)
139	#define R21W (BS3_REGISTER_FAMILY_16BIT_APX \| 21)
140	#define R22W (BS3_REGISTER_FAMILY_16BIT_APX \| 22)
141	#define R23W (BS3_REGISTER_FAMILY_16BIT_APX \| 23)
142	#define R24W (BS3_REGISTER_FAMILY_16BIT_APX \| 24)
143	#define R25W (BS3_REGISTER_FAMILY_16BIT_APX \| 25)
144	#define R26W (BS3_REGISTER_FAMILY_16BIT_APX \| 26)
145	#define R27W (BS3_REGISTER_FAMILY_16BIT_APX \| 27)
146	#define R28W (BS3_REGISTER_FAMILY_16BIT_APX \| 28)
147	#define R29W (BS3_REGISTER_FAMILY_16BIT_APX \| 29)
148	#define R30W (BS3_REGISTER_FAMILY_16BIT_APX \| 30)
149	#define R31W (BS3_REGISTER_FAMILY_16BIT_APX \| 31)
150
151	#define BS3_REGISTER_FAMILY_32BIT 0x40
152	#define EAX (BS3_REGISTER_FAMILY_32BIT \| 0)
153	#define ECX (BS3_REGISTER_FAMILY_32BIT \| 1)
154	#define EDX (BS3_REGISTER_FAMILY_32BIT \| 2)
155	#define EBX (BS3_REGISTER_FAMILY_32BIT \| 3)
156	#define ESP (BS3_REGISTER_FAMILY_32BIT \| 4)
157	#define EBP (BS3_REGISTER_FAMILY_32BIT \| 5)
158	#define ESI (BS3_REGISTER_FAMILY_32BIT \| 6)
159	#define EDI (BS3_REGISTER_FAMILY_32BIT \| 7)
160	#define R8D (BS3_REGISTER_FAMILY_32BIT \| 8)
161	#define R9D (BS3_REGISTER_FAMILY_32BIT \| 9)
162	#define R10D (BS3_REGISTER_FAMILY_32BIT \| 10)
163	#define R11D (BS3_REGISTER_FAMILY_32BIT \| 11)
164	#define R12D (BS3_REGISTER_FAMILY_32BIT \| 12)
165	#define R13D (BS3_REGISTER_FAMILY_32BIT \| 13)
166	#define R14D (BS3_REGISTER_FAMILY_32BIT \| 14)
167	#define R15D (BS3_REGISTER_FAMILY_32BIT \| 15)
168	#define BS3_REGISTER_FAMILY_32BIT_APX (0x50 \| BS3_REGISTER_FAMILY_APX_TODO)
169	#define R16D (BS3_REGISTER_FAMILY_32BIT_APX \| 16)
170	#define R17D (BS3_REGISTER_FAMILY_32BIT_APX \| 17)
171	#define R18D (BS3_REGISTER_FAMILY_32BIT_APX \| 18)
172	#define R19D (BS3_REGISTER_FAMILY_32BIT_APX \| 19)
173	#define R20D (BS3_REGISTER_FAMILY_32BIT_APX \| 20)
174	#define R21D (BS3_REGISTER_FAMILY_32BIT_APX \| 21)
175	#define R22D (BS3_REGISTER_FAMILY_32BIT_APX \| 22)
176	#define R23D (BS3_REGISTER_FAMILY_32BIT_APX \| 23)
177	#define R24D (BS3_REGISTER_FAMILY_32BIT_APX \| 24)
178	#define R25D (BS3_REGISTER_FAMILY_32BIT_APX \| 25)
179	#define R26D (BS3_REGISTER_FAMILY_32BIT_APX \| 26)
180	#define R27D (BS3_REGISTER_FAMILY_32BIT_APX \| 27)
181	#define R28D (BS3_REGISTER_FAMILY_32BIT_APX \| 28)
182	#define R29D (BS3_REGISTER_FAMILY_32BIT_APX \| 29)
183	#define R30D (BS3_REGISTER_FAMILY_32BIT_APX \| 30)
184	#define R31D (BS3_REGISTER_FAMILY_32BIT_APX \| 31)
185
186	#define BS3_REGISTER_FAMILY_64BIT 0x60
187	#define RAX (BS3_REGISTER_FAMILY_64BIT \| 0)
188	#define RCX (BS3_REGISTER_FAMILY_64BIT \| 1)
189	#define RDX (BS3_REGISTER_FAMILY_64BIT \| 2)
190	#define RBX (BS3_REGISTER_FAMILY_64BIT \| 3)
191	#define RSP (BS3_REGISTER_FAMILY_64BIT \| 4)
192	#define RBP (BS3_REGISTER_FAMILY_64BIT \| 5)
193	#define RSI (BS3_REGISTER_FAMILY_64BIT \| 6)
194	#define RDI (BS3_REGISTER_FAMILY_64BIT \| 7)
195	#define R8 (BS3_REGISTER_FAMILY_64BIT \| 8)
196	#define R9 (BS3_REGISTER_FAMILY_64BIT \| 9)
197	#define R10 (BS3_REGISTER_FAMILY_64BIT \| 10)
198	#define R11 (BS3_REGISTER_FAMILY_64BIT \| 11)
199	#define R12 (BS3_REGISTER_FAMILY_64BIT \| 12)
200	#define R13 (BS3_REGISTER_FAMILY_64BIT \| 13)
201	#define R14 (BS3_REGISTER_FAMILY_64BIT \| 14)
202	#define R15 (BS3_REGISTER_FAMILY_64BIT \| 15)
203	#define BS3_REGISTER_FAMILY_64BIT_APX (0x70 \| BS3_REGISTER_FAMILY_APX_TODO)
204	#define R16 (BS3_REGISTER_FAMILY_64BIT_APX \| 16)
205	#define R17 (BS3_REGISTER_FAMILY_64BIT_APX \| 17)
206	#define R18 (BS3_REGISTER_FAMILY_64BIT_APX \| 18)
207	#define R19 (BS3_REGISTER_FAMILY_64BIT_APX \| 19)
208	#define R20 (BS3_REGISTER_FAMILY_64BIT_APX \| 20)
209	#define R21 (BS3_REGISTER_FAMILY_64BIT_APX \| 21)
210	#define R22 (BS3_REGISTER_FAMILY_64BIT_APX \| 22)
211	#define R23 (BS3_REGISTER_FAMILY_64BIT_APX \| 23)
212	#define R24 (BS3_REGISTER_FAMILY_64BIT_APX \| 24)
213	#define R25 (BS3_REGISTER_FAMILY_64BIT_APX \| 25)
214	#define R26 (BS3_REGISTER_FAMILY_64BIT_APX \| 26)
215	#define R27 (BS3_REGISTER_FAMILY_64BIT_APX \| 27)
216	#define R28 (BS3_REGISTER_FAMILY_64BIT_APX \| 28)
217	#define R29 (BS3_REGISTER_FAMILY_64BIT_APX \| 29)
218	#define R30 (BS3_REGISTER_FAMILY_64BIT_APX \| 30)
219	#define R31 (BS3_REGISTER_FAMILY_64BIT_APX \| 31)
220
221	#define BS3_REGISTER_FAMILY_XMM 0x80
222	#define XMM0 (BS3_REGISTER_FAMILY_XMM \| 0)
223	#define XMM1 (BS3_REGISTER_FAMILY_XMM \| 1)
224	#define XMM2 (BS3_REGISTER_FAMILY_XMM \| 2)
225	#define XMM3 (BS3_REGISTER_FAMILY_XMM \| 3)
226	#define XMM4 (BS3_REGISTER_FAMILY_XMM \| 4)
227	#define XMM5 (BS3_REGISTER_FAMILY_XMM \| 5)
228	#define XMM6 (BS3_REGISTER_FAMILY_XMM \| 6)
229	#define XMM7 (BS3_REGISTER_FAMILY_XMM \| 7)
230	#define XMM8 (BS3_REGISTER_FAMILY_XMM \| 8)
231	#define XMM9 (BS3_REGISTER_FAMILY_XMM \| 9)
232	#define XMM10 (BS3_REGISTER_FAMILY_XMM \| 10)
233	#define XMM11 (BS3_REGISTER_FAMILY_XMM \| 11)
234	#define XMM12 (BS3_REGISTER_FAMILY_XMM \| 12)
235	#define XMM13 (BS3_REGISTER_FAMILY_XMM \| 13)
236	#define XMM14 (BS3_REGISTER_FAMILY_XMM \| 14)
237	#define XMM15 (BS3_REGISTER_FAMILY_XMM \| 15)
238	#define BS3_REGISTER_FAMILY_XMM_512 (0x90 \| BS3_REGISTER_FAMILY_AVX512_TODO)
239	#define XMM16 (BS3_REGISTER_FAMILY_XMM_512 \| 16)
240	#define XMM17 (BS3_REGISTER_FAMILY_XMM_512 \| 17)
241	#define XMM18 (BS3_REGISTER_FAMILY_XMM_512 \| 18)
242	#define XMM19 (BS3_REGISTER_FAMILY_XMM_512 \| 19)
243	#define XMM20 (BS3_REGISTER_FAMILY_XMM_512 \| 20)
244	#define XMM21 (BS3_REGISTER_FAMILY_XMM_512 \| 21)
245	#define XMM22 (BS3_REGISTER_FAMILY_XMM_512 \| 22)
246	#define XMM23 (BS3_REGISTER_FAMILY_XMM_512 \| 23)
247	#define XMM24 (BS3_REGISTER_FAMILY_XMM_512 \| 24)
248	#define XMM25 (BS3_REGISTER_FAMILY_XMM_512 \| 25)
249	#define XMM26 (BS3_REGISTER_FAMILY_XMM_512 \| 26)
250	#define XMM27 (BS3_REGISTER_FAMILY_XMM_512 \| 27)
251	#define XMM28 (BS3_REGISTER_FAMILY_XMM_512 \| 28)
252	#define XMM29 (BS3_REGISTER_FAMILY_XMM_512 \| 29)
253	#define XMM30 (BS3_REGISTER_FAMILY_XMM_512 \| 30)
254	#define XMM31 (BS3_REGISTER_FAMILY_XMM_512 \| 31)
255
256	#define BS3_REGISTER_FAMILY_YMM 0xA0
257	#define YMM0 (BS3_REGISTER_FAMILY_YMM \| 0)
258	#define YMM1 (BS3_REGISTER_FAMILY_YMM \| 1)
259	#define YMM2 (BS3_REGISTER_FAMILY_YMM \| 2)
260	#define YMM3 (BS3_REGISTER_FAMILY_YMM \| 3)
261	#define YMM4 (BS3_REGISTER_FAMILY_YMM \| 4)
262	#define YMM5 (BS3_REGISTER_FAMILY_YMM \| 5)
263	#define YMM6 (BS3_REGISTER_FAMILY_YMM \| 6)
264	#define YMM7 (BS3_REGISTER_FAMILY_YMM \| 7)
265	#define YMM8 (BS3_REGISTER_FAMILY_YMM \| 8)
266	#define YMM9 (BS3_REGISTER_FAMILY_YMM \| 9)
267	#define YMM10 (BS3_REGISTER_FAMILY_YMM \| 10)
268	#define YMM11 (BS3_REGISTER_FAMILY_YMM \| 11)
269	#define YMM12 (BS3_REGISTER_FAMILY_YMM \| 12)
270	#define YMM13 (BS3_REGISTER_FAMILY_YMM \| 13)
271	#define YMM14 (BS3_REGISTER_FAMILY_YMM \| 14)
272	#define YMM15 (BS3_REGISTER_FAMILY_YMM \| 15)
273	#define BS3_REGISTER_FAMILY_YMM_512 (0xB0 \| BS3_REGISTER_FAMILY_AVX512_TODO)
274	#define YMM16 (BS3_REGISTER_FAMILY_YMM_512 \| 16)
275	#define YMM17 (BS3_REGISTER_FAMILY_YMM_512 \| 17)
276	#define YMM18 (BS3_REGISTER_FAMILY_YMM_512 \| 18)
277	#define YMM19 (BS3_REGISTER_FAMILY_YMM_512 \| 19)
278	#define YMM20 (BS3_REGISTER_FAMILY_YMM_512 \| 20)
279	#define YMM21 (BS3_REGISTER_FAMILY_YMM_512 \| 21)
280	#define YMM22 (BS3_REGISTER_FAMILY_YMM_512 \| 22)
281	#define YMM23 (BS3_REGISTER_FAMILY_YMM_512 \| 23)
282	#define YMM24 (BS3_REGISTER_FAMILY_YMM_512 \| 24)
283	#define YMM25 (BS3_REGISTER_FAMILY_YMM_512 \| 25)
284	#define YMM26 (BS3_REGISTER_FAMILY_YMM_512 \| 26)
285	#define YMM27 (BS3_REGISTER_FAMILY_YMM_512 \| 27)
286	#define YMM28 (BS3_REGISTER_FAMILY_YMM_512 \| 28)
287	#define YMM29 (BS3_REGISTER_FAMILY_YMM_512 \| 29)
288	#define YMM30 (BS3_REGISTER_FAMILY_YMM_512 \| 30)
289	#define YMM31 (BS3_REGISTER_FAMILY_YMM_512 \| 31)
290
291	#define BS3_REGISTER_FAMILY_ZMM 0xC0
292	#define BS3_REGISTER_FAMILY_ZMM_LOW (0xC0 \| BS3_REGISTER_FAMILY_AVX512_TODO)
293	#define ZMM0 (BS3_REGISTER_FAMILY_ZMM_LOW \| 0)
294	#define ZMM1 (BS3_REGISTER_FAMILY_ZMM_LOW \| 1)
295	#define ZMM2 (BS3_REGISTER_FAMILY_ZMM_LOW \| 2)
296	#define ZMM3 (BS3_REGISTER_FAMILY_ZMM_LOW \| 3)
297	#define ZMM4 (BS3_REGISTER_FAMILY_ZMM_LOW \| 4)
298	#define ZMM5 (BS3_REGISTER_FAMILY_ZMM_LOW \| 5)
299	#define ZMM6 (BS3_REGISTER_FAMILY_ZMM_LOW \| 6)
300	#define ZMM7 (BS3_REGISTER_FAMILY_ZMM_LOW \| 7)
301	#define ZMM8 (BS3_REGISTER_FAMILY_ZMM_LOW \| 8)
302	#define ZMM9 (BS3_REGISTER_FAMILY_ZMM_LOW \| 9)
303	#define ZMM10 (BS3_REGISTER_FAMILY_ZMM_LOW \| 10)
304	#define ZMM11 (BS3_REGISTER_FAMILY_ZMM_LOW \| 11)
305	#define ZMM12 (BS3_REGISTER_FAMILY_ZMM_LOW \| 12)
306	#define ZMM13 (BS3_REGISTER_FAMILY_ZMM_LOW \| 13)
307	#define ZMM14 (BS3_REGISTER_FAMILY_ZMM_LOW \| 14)
308	#define ZMM15 (BS3_REGISTER_FAMILY_ZMM_LOW \| 15)
309	#define BS3_REGISTER_FAMILY_ZMM_512 (0xD0 \| BS3_REGISTER_FAMILY_AVX512_TODO)
310	#define ZMM16 (BS3_REGISTER_FAMILY_ZMM_512 \| 16)
311	#define ZMM17 (BS3_REGISTER_FAMILY_ZMM_512 \| 17)
312	#define ZMM18 (BS3_REGISTER_FAMILY_ZMM_512 \| 18)
313	#define ZMM19 (BS3_REGISTER_FAMILY_ZMM_512 \| 19)
314	#define ZMM20 (BS3_REGISTER_FAMILY_ZMM_512 \| 20)
315	#define ZMM21 (BS3_REGISTER_FAMILY_ZMM_512 \| 21)
316	#define ZMM22 (BS3_REGISTER_FAMILY_ZMM_512 \| 22)
317	#define ZMM23 (BS3_REGISTER_FAMILY_ZMM_512 \| 23)
318	#define ZMM24 (BS3_REGISTER_FAMILY_ZMM_512 \| 24)
319	#define ZMM25 (BS3_REGISTER_FAMILY_ZMM_512 \| 25)
320	#define ZMM26 (BS3_REGISTER_FAMILY_ZMM_512 \| 26)
321	#define ZMM27 (BS3_REGISTER_FAMILY_ZMM_512 \| 27)
322	#define ZMM28 (BS3_REGISTER_FAMILY_ZMM_512 \| 28)
323	#define ZMM29 (BS3_REGISTER_FAMILY_ZMM_512 \| 29)
324	#define ZMM30 (BS3_REGISTER_FAMILY_ZMM_512 \| 30)
325	#define ZMM31 (BS3_REGISTER_FAMILY_ZMM_512 \| 31)
326
327	#define BS3_REGISTER_FAMILY_OTHER 0xE0
328	#define BS3_REGISTER_FAMILY_MMX 0xE0
329	#define MM0 (BS3_REGISTER_FAMILY_MMX \| 0)
330	#define MM1 (BS3_REGISTER_FAMILY_MMX \| 1)
331	#define MM2 (BS3_REGISTER_FAMILY_MMX \| 2)
332	#define MM3 (BS3_REGISTER_FAMILY_MMX \| 3)
333	#define MM4 (BS3_REGISTER_FAMILY_MMX \| 4)
334	#define MM5 (BS3_REGISTER_FAMILY_MMX \| 5)
335	#define MM6 (BS3_REGISTER_FAMILY_MMX \| 6)
336	#define MM7 (BS3_REGISTER_FAMILY_MMX \| 7)
337	#define BS3_REGISTER_IS_MMX(uReg) ((uReg) >= MM0 && (uReg) <= MM7)
338
339	#define BS3_REGISTER_FAMILY_OPMASK (0xE8 \| BS3_REGISTER_FAMILY_AVX512_TODO)
340	#define k0 (BS3_REGISTER_FAMILY_OPMASK \| 0)
341	#define k1 (BS3_REGISTER_FAMILY_OPMASK \| 1)
342	#define k2 (BS3_REGISTER_FAMILY_OPMASK \| 2)
343	#define k3 (BS3_REGISTER_FAMILY_OPMASK \| 3)
344	#define k4 (BS3_REGISTER_FAMILY_OPMASK \| 4)
345	#define k5 (BS3_REGISTER_FAMILY_OPMASK \| 5)
346	#define k6 (BS3_REGISTER_FAMILY_OPMASK \| 6)
347	#define k7 (BS3_REGISTER_FAMILY_OPMASK \| 7)
348
349	#define BS3_REGISTER_FAMILY_SEGREG (0xF0 \| BS3_REGISTER_FAMILY_OTHER_TODO)
350	#define ES (BS3_REGISTER_FAMILY_SEGREG \| 0)
351	#define CS (BS3_REGISTER_FAMILY_SEGREG \| 1)
352	#define SS (BS3_REGISTER_FAMILY_SEGREG \| 2)
353	#define DS (BS3_REGISTER_FAMILY_SEGREG \| 3)
354	#define FS (BS3_REGISTER_FAMILY_SEGREG \| 4)
355	#define GS (BS3_REGISTER_FAMILY_SEGREG \| 5)
356
357	#define BS3_REGISTER_FAMILY_IP (0xF5 \| BS3_REGISTER_FAMILY_OTHER_TODO)
358	#define IP BS3_REGISTER_FAMILY_IP
359	#define EIP BS3_REGISTER_FAMILY_IP
360	#define RIP BS3_REGISTER_FAMILY_IP
361	#define xIP BS3_REGISTER_FAMILY_IP
362
363	#define BS3_REGISTER_FAMILY_FL (0xF6 \| BS3_REGISTER_FAMILY_OTHER_TODO)
364	#define FL BS3_REGISTER_FAMILY_FL
365	#define EFL BS3_REGISTER_FAMILY_FL
366	#define RFL BS3_REGISTER_FAMILY_FL
367	#define xFL BS3_REGISTER_FAMILY_FL
368
369	#define BS3_REGISTER_FAMILY_8BIT_H (0xE8 \| BS3_REGISTER_FAMILY_OTHER_TODO)
370	#define AH (BS3_REGISTER_FAMILY_8BIT_H \| 0)
371	#define CH (BS3_REGISTER_FAMILY_8BIT_H \| 1)
372	#define DH (BS3_REGISTER_FAMILY_8BIT_H \| 2)
373	#define BH (BS3_REGISTER_FAMILY_8BIT_H \| 3)
374
375	#define NOREG 0xFC
376
377	#define BS3_REGISTER_FAMILY_MEMREF 0xFE
378	#define FSxDI (BS3_REGISTER_FAMILY_MEMREF \| 0)
379	#define FSxBX (BS3_REGISTER_FAMILY_MEMREF \| 1)
380
381	#define BS3_REGISTER_FLAG_MEMREF 0x100
382	#define BS3_FSxREG(reg) (((reg) == FSxBX \|\| (reg) == FSxDI) ? reg : ((reg) & BS3_REGISTER_REGISTER_MASK) \| BS3_REGISTER_FLAG_MEMREF)
383	#define BS3_REGISTER_IS_MEMREF(reg) (((reg) & BS3_REGISTER_FLAG_MEMREF) \|\| (((reg) & BS3_REGISTER_FAMILY_MEMREF) == BS3_REGISTER_FAMILY_MEMREF))
384	#define BS3_REGISTER_MEMREF_TO(reg) (((reg) == FSxBX ? BX : (reg) == FSxDI ? DI : (reg)) & BS3_REGISTER_REGISTER_MASK)
385
386	#define BS3_REGISTER_NAME_MAXSIZE sizeof("FSx(avail)")
387
388	/**
389	* Get the name of a register from its identity value used in instruction test value tables.
390	*
391	* @returns Name of register.
392	* @param pszBuf Where to store the name.
393	* @param cchBuf The size of the buffer.
394	* @param uReg The register identity value.
395	*/
396	static size_t bs3CpuInstrXGetRegisterName(char BS3_FAR *pszBuf, size_t cchBuf, uint16_t uReg)
397	{
398	const uint8_t uRegNum = uReg & BS3_REGISTER_REGISTER_MASK;
399	const uint8_t uRegSet = uReg & BS3_REGISTER_FAMILY_MASK;
400	static const char * const s_apsz8bitLNames[] = { "AL", "CL", "DL", "BL", "SPL", "BPL", "SIL", "DIL" };
401	static const char * const s_apsz16bitNames[] = { "AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI" };
402	static const char * const s_apszOtherNames[] = { "MM0", "MM1", "MM2", "MM3", "MM4", "MM5", "MM6", "MM7",
403	"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
404	"CS", "DS", "ES", "FS", "GS", "SS",
405	"xIP", "xFL",
406	"AH", "CH", "DH", "BH",
407	"NOREG", "(avail)", "FSxDI", "FSxBX" };
408	BS3_ASSERT(cchBuf >= BS3_REGISTER_NAME_MAXSIZE);
409
410	if (uReg & BS3_REGISTER_FLAG_MEMREF)
411	{
412	char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
413
414	bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg & BS3_REGISTER_MASK);
415	return Bs3StrPrintf(pszBuf, cchBuf, "FSx%s", pszRegName);
416	}
417
418	switch (uRegSet) {
419	case BS3_REGISTER_FAMILY_8BIT_L:
420	if (uRegNum < RT_ELEMENTS(s_apsz8bitLNames))
421	return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apsz8bitLNames[uRegNum]);
422	else
423	return Bs3StrPrintf(pszBuf, cchBuf, "R%dB", uRegNum);
424	case BS3_REGISTER_FAMILY_16BIT:
425	if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
426	return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apsz16bitNames[uRegNum]);
427	else
428	return Bs3StrPrintf(pszBuf, cchBuf, "R%dW", uRegNum);
429	case BS3_REGISTER_FAMILY_32BIT:
430	if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
431	return Bs3StrPrintf(pszBuf, cchBuf, "E%s", s_apsz16bitNames[uRegNum]);
432	else
433	return Bs3StrPrintf(pszBuf, cchBuf, "R%dD", uRegNum);
434	case BS3_REGISTER_FAMILY_64BIT:
435	if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
436	return Bs3StrPrintf(pszBuf, cchBuf, "R%s", s_apsz16bitNames[uRegNum]);
437	else
438	return Bs3StrPrintf(pszBuf, cchBuf, "R%d", uRegNum);
439	case BS3_REGISTER_FAMILY_XMM:
440	return Bs3StrPrintf(pszBuf, cchBuf, "XMM%d", uRegNum);
441	case BS3_REGISTER_FAMILY_YMM:
442	return Bs3StrPrintf(pszBuf, cchBuf, "YMM%d", uRegNum);
443	case BS3_REGISTER_FAMILY_ZMM:
444	return Bs3StrPrintf(pszBuf, cchBuf, "ZMM%d", uRegNum);
445	case BS3_REGISTER_FAMILY_OTHER:
446	return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apszOtherNames[uRegNum]);
447	}
448	return Bs3StrPrintf(pszBuf, cchBuf, "(?%02X?)", uReg);
449	}
450
451	/**
452	* Set a register within a testing context. Intended to support a broad
453	* range of register types; currently supports MMX, XMM, YMM, and general
454	* purpose registers (except 8-bit sub-registers); and setting up FS:xGPR
455	* for memory reference operations.
456	*
457	* Other regs known to this subsystem are either so far unused by
458	* VirtualBox (ZMM, k[0-7], GPRs >15); or not used by tests which call
459	* this (8-bit sub-registers, segment registers, xIP, xFL).
460	*
461	* @param pSetRegCtx Arguments to this function (see below).
462	* @param uReg The register identity value to modify within that context.
463	* @param pu256Val Pointer to the data to store there.
464	* @returns bool Whether the store succeeded (currently ignored by callers).
465	*/
466
467	typedef struct BS3SETREGCTX
468	{
469	/** Pointer to test context. */
470	PBS3EXTCTX pExtCtx;
471	/** Pointer to register context; for BS3_REGISTER_FAMILY_MEMREF, all GPR families */
472	PBS3REGCTX pCtx;
473	/** Whether to zero YMM-high bits when setting XMM; for BS3_REGISTER_FAMILY_XMM */
474	bool fZeroYMMHi;
475	/** Current execution mode; for BS3_REGISTER_FAMILY_64BIT */
476	uint8_t bMode;
477	} BS3SETREGCTX;
478	typedef BS3SETREGCTX BS3_FAR *PBS3SETREGCTX;
479
480	static bool Bs3ExtCtxSetReg_int(PBS3SETREGCTX pSetRegCtx, uint16_t uReg, PCRTUINT256U pu256Val)
481	{
482	uint8_t uRegNum = uReg & BS3_REGISTER_REGISTER_MASK;
483	uint8_t uRegSet = uReg & BS3_REGISTER_FAMILY_MASK;
484	char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
485
486	if (BS3_REGISTER_IS_MEMREF(uReg))
487	{
488	if (uReg == FSxBX \|\| uReg == FSxDI \|\| uRegSet <= BS3_REGISTER_FAMILY_64BIT)
489	uRegNum = BS3_REGISTER_MEMREF_TO(uReg);
490	else
491	uRegNum = 255; /* Fall through to error handling below to complain about 'FSxZMM31' or whatever */
492	uRegSet = BS3_REGISTER_FAMILY_MEMREF;
493	}
494
495	if (uRegNum < 16)
496	{
497	switch (uRegSet)
498	{
499	case BS3_REGISTER_FAMILY_16BIT:
500	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au16[0], 2);
501	case BS3_REGISTER_FAMILY_32BIT:
502	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au32[0], 4);
503	case BS3_REGISTER_FAMILY_64BIT:
504	return Bs3RegCtxSetGpr(pSetRegCtx->pCtx, uRegNum, pu256Val->au64[0], BS3_MODE_IS_64BIT_CODE(pSetRegCtx->bMode) ? 8 : 4);
505	case BS3_REGISTER_FAMILY_XMM:
506	if (pSetRegCtx->fZeroYMMHi)
507	return Bs3ExtCtxSetXmm(pSetRegCtx->pExtCtx, uRegNum, &pu256Val->au128[0]);
508	else
509	return Bs3ExtCtxSetYmm(pSetRegCtx->pExtCtx, uRegNum, pu256Val, 16);
510	case BS3_REGISTER_FAMILY_YMM:
511	return Bs3ExtCtxSetYmm(pSetRegCtx->pExtCtx, uRegNum, pu256Val, 32);
512	case BS3_REGISTER_FAMILY_MEMREF:
513	Bs3RegCtxSetGrpSegFromCurPtr(pSetRegCtx->pCtx, (&pSetRegCtx->pCtx->rax) + uRegNum, &pSetRegCtx->pCtx->fs, (void *)pu256Val);
514	return true;
515	case BS3_REGISTER_FAMILY_OTHER:
516	if (BS3_REGISTER_IS_MMX(uReg))
517	return Bs3ExtCtxSetMm(pSetRegCtx->pExtCtx, uRegNum, pu256Val->au64[0], BS3EXTCTXTOPMM_SET);
518	break;
519	case BS3_REGISTER_FAMILY_8BIT_L:
520	case BS3_REGISTER_FAMILY_ZMM:
521	default:
522	break;
523
524	}
525	}
526	if (uReg == NOREG)
527	return true;
528
529	bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg);
530	return Bs3TestFailedF("Bs3ExtCtxSetReg() todo: handle register '%s' (%02X)", pszRegName, uReg);
531	}
532
533	static bool g_fSetRegVerbose = false;
534
535	static bool Bs3ExtCtxSetReg(PBS3SETREGCTX pSetRegCtx, uint16_t uReg, PCRTUINT256U pu256Val)
536	{
537	bool fRet = Bs3ExtCtxSetReg_int(pSetRegCtx, uReg, pu256Val);
538
539	if (g_fSetRegVerbose)
540	{
541	char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
542	char pszValBuf[80] = "(not decoded)";
543
544	switch (uReg & BS3_REGISTER_FAMILY_MASK)
545	{
546	case BS3_REGISTER_FAMILY_16BIT:
547	Bs3StrPrintf(pszValBuf, 80, "%#06RX16", pu256Val->au16[0]);
548	break;
549	case BS3_REGISTER_FAMILY_32BIT:
550	Bs3StrPrintf(pszValBuf, 80, "%#10RX32", pu256Val->au32[0]);
551	break;
552	case BS3_REGISTER_FAMILY_64BIT:
553	Bs3StrPrintf(pszValBuf, 80, "%#18RX64", pu256Val->au64[0]);
554	break;
555	case BS3_REGISTER_FAMILY_XMM:
556	Bs3StrPrintf(pszValBuf, 80, "%#18RX64:%#18RX64", pu256Val->au64[1], pu256Val->au64[0]);
557	break;
558	case BS3_REGISTER_FAMILY_YMM:
559	Bs3StrPrintf(pszValBuf, 80, "%#18RX64:%#18RX64:%#18RX64:%#18RX64", pu256Val->au64[3], pu256Val->au64[2], pu256Val->au64[1], pu256Val->au64[0]);
560	break;
561	case BS3_REGISTER_FAMILY_OTHER:
562	if (BS3_REGISTER_IS_MMX(uReg))
563	Bs3StrPrintf(pszValBuf, 80, "%#18RX64", pu256Val->au64[0]);
564	break;
565	default:
566	break;
567	}
568	bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg);
569	Bs3TestPrintf("Bs3ExtCtxSetReg '%s' to '%s'; %s\n", pszRegName, pszValBuf, fRet ? "worked" : "failed");
570	}
571	return fRet;
572	}

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format