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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-fpustate-1-template.c@ 106215

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1/* $Id: bs3-fpustate-1-template.c 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-fpustate-1, C code template.
4 */
5
6/*
7 * Copyright (C) 2007-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#include <VBox/VMMDevTesting.h>
44
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49
50
51#ifdef BS3_INSTANTIATING_CMN
52
53/**
54 * Displays the differences between the two states.
55 */
56# define bs3FpuState1_Diff BS3_CMN_NM(bs3FpuState1_Diff)
57BS3_DECL_NEAR(void) bs3FpuState1_Diff(X86FXSTATE const BS3_FAR *pExpected, X86FXSTATE const BS3_FAR *pChecking)
58{
59 unsigned i;
60
61# define CHECK(a_Member, a_Fmt) \
62 if (pExpected->a_Member != pChecking->a_Member) \
63 Bs3TestPrintf(" " #a_Member ": " a_Fmt ", expected " a_Fmt "\n", pChecking->a_Member, pExpected->a_Member); \
64 else do { } while (0)
65 CHECK(FCW, "%#RX16");
66 CHECK(FSW, "%#RX16");
67 CHECK(FTW, "%#RX16");
68 CHECK(FOP, "%#RX16");
69 CHECK(FPUIP, "%#RX32");
70 CHECK(CS, "%#RX16");
71 CHECK(Rsrvd1, "%#RX16");
72 CHECK(FPUDP, "%#RX32");
73 CHECK(DS, "%#RX16");
74 CHECK(Rsrvd2, "%#RX16");
75 CHECK(MXCSR, "%#RX32");
76 CHECK(MXCSR_MASK, "%#RX32");
77# undef CHECK
78 for (i = 0; i < RT_ELEMENTS(pExpected->aRegs); i++)
79 if ( pChecking->aRegs[i].au64[0] != pExpected->aRegs[i].au64[0]
80 || pChecking->aRegs[i].au64[1] != pExpected->aRegs[i].au64[1])
81 Bs3TestPrintf("st%u: %.16Rhxs\n"
82 "exp: %.16Rhxs\n",
83 i, &pChecking->aRegs[i], &pExpected->aRegs[i]);
84 for (i = 0; i < RT_ELEMENTS(pExpected->aXMM); i++)
85 if ( pChecking->aXMM[i].au64[0] != pExpected->aXMM[i].au64[0]
86 || pChecking->aXMM[i].au64[1] != pExpected->aXMM[i].au64[1])
87 Bs3TestPrintf("xmm%u: %.16Rhxs\n"
88 " %sexp: %.16Rhxs\n",
89 i, &pChecking->aRegs[i], &pExpected->aRegs[i], i >= 10 ? " " : "");
90}
91
92
93#endif /* BS3_INSTANTIATING_CMN */
94
95
96/*
97 * Mode specific code.
98 * Mode specific code.
99 * Mode specific code.
100 */
101#ifdef BS3_INSTANTIATING_MODE
102# if TMPL_MODE == BS3_MODE_PE32 \
103 || TMPL_MODE == BS3_MODE_PP32 \
104 || TMPL_MODE == BS3_MODE_PAE32 \
105 || TMPL_MODE == BS3_MODE_LM64 \
106 || TMPL_MODE == BS3_MODE_RM
107
108/* Assembly helpers: */
109BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_InitState)(X86FXSTATE BS3_FAR *pFxState, void BS3_FAR *pvMmioReg);
110BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_Restore)(X86FXSTATE const BS3_FAR *pFxState);
111BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_Save)(X86FXSTATE BS3_FAR *pFxState);
112
113BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_FNStEnv)(void BS3_FAR *pvMmioReg);
114BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovDQU_Read)(void BS3_FAR *pvMmioReg, void BS3_FAR *pvResult);
115BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovDQU_Write)(void BS3_FAR *pvMmioReg);
116BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovUPS_Read)(void BS3_FAR *pvMmioReg, void BS3_FAR *pvResult);
117BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovUPS_Write)(void BS3_FAR *pvMmioReg);
118BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_FMul)(void BS3_FAR *pvMmioReg, void BS3_FAR *pvNoResult);
119
120
121/**
122 * Checks if we're seeing a problem with fnstenv saving zero selectors when
123 * running on the compare area.
124 *
125 * This triggers in NEM mode if the native hypervisor doesn't do a good enough
126 * job at save the FPU state for 16-bit and 32-bit guests. We have heuristics
127 * in CPUMInternal.mac (SAVE_32_OR_64_FPU) for this.
128 *
129 * @returns true if this the zero selector issue.
130 * @param pabReadback The MMIO read buffer containing the fnstenv result
131 * typically produced by IEM.
132 * @param pabCompare The buffer containing the fnstenv result typcially
133 * produced by the CPU itself.
134 */
135static bool TMPL_NM(bs3FpuState1_IsZeroFnStEnvSelectorsProblem)(const uint8_t BS3_FAR *pabReadback,
136 const uint8_t BS3_FAR *pabCompare)
137{
138 unsigned const offCs = ARCH_BITS == 16 ? 8 : 16;
139 unsigned const offDs = ARCH_BITS == 16 ? 12 : 24;
140 if ( *(const uint16_t BS3_FAR *)&pabCompare[offCs] == 0
141 && *(const uint16_t BS3_FAR *)&pabCompare[offDs] == 0)
142 {
143 /* Check the stuff before the CS register: */
144 if (Bs3MemCmp(pabReadback, pabCompare, offCs) == 0)
145 {
146 /* Check the stuff between the DS and CS registers:*/
147 if (Bs3MemCmp(&pabReadback[offCs + 2], &pabCompare[offCs + 2], offDs - offCs - 2) == 0)
148 {
149#if ARCH_BITS != 16
150 /* Check the stuff after the DS register if 32-bit mode: */
151 if ( *(const uint16_t BS3_FAR *)&pabReadback[offDs + 2]
152 == *(const uint16_t BS3_FAR *)&pabCompare[offDs + 2])
153#endif
154 return true;
155 }
156 }
157 }
158 return false;
159}
160
161
162/**
163 * Tests for FPU state corruption.
164 *
165 * First we don't do anything to quit guest context for a while.
166 * Then we start testing weird MMIO accesses, some which amonger other things
167 * forces the use of the FPU state or host FPU to do the emulation. Both are a
168 * little complicated in raw-mode and ring-0 contexts.
169 *
170 * We ASSUME FXSAVE/FXRSTOR support here.
171 */
172BS3_DECL_FAR(uint8_t) TMPL_NM(bs3FpuState1_Corruption)(uint8_t bMode)
173{
174 /* We don't need to test that many modes, probably. */
175
176 uint8_t abBuf[sizeof(X86FXSTATE)*2 + 32];
177 uint8_t BS3_FAR *pbTmp = &abBuf[0x10 - (((uintptr_t)abBuf) & 0x0f)];
178 X86FXSTATE BS3_FAR *pExpected = (X86FXSTATE BS3_FAR *)pbTmp;
179 X86FXSTATE BS3_FAR *pChecking = pExpected + 1;
180 uint32_t iLoop;
181 uint32_t uStartTick;
182 bool fMmioReadback;
183 bool fReadBackError = false;
184 bool fReadError = false;
185 uint32_t cFnStEnvSelectorsZero = 0;
186 BS3PTRUNION MmioReg;
187 BS3CPUVENDOR const enmCpuVendor = Bs3GetCpuVendor();
188 bool const fSkipStorIdt = Bs3TestQueryCfgBool(VMMDEV_TESTING_CFG_IS_NEM_LINUX, false);
189 bool const fMayHaveZeroStEnvSels = Bs3TestQueryCfgBool(VMMDEV_TESTING_CFG_IS_NEM_LINUX, false);
190 bool const fFastFxSaveRestore = RT_BOOL(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_FFXSR);
191 //bool const fFdpXcptOnly = (ASMCpuIdEx_EBX(7, 0) & X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY)
192 // && ASMCpuId_EAX(0) >= 7;
193 RT_NOREF(bMode);
194
195 if (fSkipStorIdt)
196 Bs3TestPrintf("NEM/linux - skipping SIDT\n");
197
198# undef CHECK_STATE
199# define CHECK_STATE(a_Instr, a_fIsFnStEnv) \
200 do { \
201 TMPL_NM(bs3FpuState1_Save)(pChecking); \
202 if (Bs3MemCmp(pExpected, pChecking, sizeof(*pExpected)) != 0) \
203 { \
204 Bs3TestFailedF("State differs after " #a_Instr " (write) in loop #%RU32\n", iLoop); \
205 bs3FpuState1_Diff(pExpected, pChecking); \
206 Bs3PitDisable(); \
207 return 1; \
208 } \
209 } while (0)
210
211
212 /* Make this code executable in raw-mode. A bit tricky. */
213 ASMSetCR0(ASMGetCR0() | X86_CR0_WP);
214 Bs3PitSetupAndEnablePeriodTimer(20);
215 ASMIntEnable();
216# if ARCH_BITS != 64
217 ASMHalt();
218# endif
219
220 /* Figure out which MMIO region we'll be using so we can correctly initialize FPUDS. */
221# if BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
222 MmioReg.pv = BS3_FP_MAKE(VMMDEV_TESTING_MMIO_RM_SEL, VMMDEV_TESTING_MMIO_RM_OFF2(0));
223# elif BS3_MODE_IS_16BIT_CODE(TMPL_MODE)
224 MmioReg.pv = BS3_FP_MAKE(BS3_SEL_VMMDEV_MMIO16, 0);
225# else
226 MmioReg.pv = (uint8_t *)VMMDEV_TESTING_MMIO_BASE;
227# endif
228 if (MmioReg.pu32[VMMDEV_TESTING_MMIO_OFF_NOP / sizeof(uint32_t)] == VMMDEV_TESTING_NOP_RET)
229 {
230 fMmioReadback = true;
231 MmioReg.pb += VMMDEV_TESTING_MMIO_OFF_READBACK;
232 }
233 else
234 {
235 Bs3TestPrintf("VMMDev MMIO not found, using VGA instead\n");
236 fMmioReadback = false;
237 MmioReg.pv = Bs3XptrFlatToCurrent(0xa7800);
238 }
239
240 /* Make 100% sure we don't trap accessing the FPU state and that we can use fxsave/fxrstor. */
241 g_usBs3TestStep = 1;
242 ASMSetCR0((ASMGetCR0() & ~(X86_CR0_TS | X86_CR0_EM)) | X86_CR0_MP);
243 ASMSetCR4(ASMGetCR4() | X86_CR4_OSFXSR /*| X86_CR4_OSXMMEEXCPT*/);
244
245 /* Come up with a distinct state. We do that from assembly (will do FPU in R0/RC). */
246 g_usBs3TestStep = 2;
247 Bs3MemSet(abBuf, 0x42, sizeof(abBuf));
248 TMPL_NM(bs3FpuState1_InitState)(pExpected, MmioReg.pb);
249
250
251 /*
252 * Test #1: Check that we can keep it consistent for a while.
253 */
254 g_usBs3TestStep = 3;
255 uStartTick = g_cBs3PitTicks;
256 for (iLoop = 0; iLoop < _16M; iLoop++)
257 {
258 CHECK_STATE(nop, false);
259 if ( (iLoop & 0xffff) == 0xffff
260 && g_cBs3PitTicks - uStartTick >= 20 * 20) /* 20 seconds*/
261 break;
262 }
263
264 /*
265 * Test #2: Use various FPU, SSE and weird instructions to do MMIO writes.
266 *
267 * We'll use the VMMDev readback register if possible, but make do
268 * with VGA if not configured.
269 */
270# ifdef __WATCOMC__
271# pragma DISABLE_MESSAGE(201) /* Warning! W201: Unreachable code */
272# endif
273 g_usBs3TestStep = 4;
274 uStartTick = g_cBs3PitTicks;
275 for (iLoop = 0; iLoop < _1M; iLoop++)
276 {
277 unsigned off;
278 uint8_t abCompare[64];
279 uint8_t abReadback[64];
280
281 /* Macros */
282# undef CHECK_READBACK_WRITE_RUN
283# define CHECK_READBACK_WRITE_RUN(a_Instr, a_Worker, a_Type, a_fIsFnStEnv) \
284 do { \
285 off = (unsigned)(iLoop & (VMMDEV_TESTING_READBACK_SIZE / 2 - 1)); \
286 if (off + sizeof(a_Type) > VMMDEV_TESTING_READBACK_SIZE) \
287 off = VMMDEV_TESTING_READBACK_SIZE - sizeof(a_Type); \
288 a_Worker((a_Type *)&MmioReg.pb[off]); \
289 if (fMmioReadback && (!fReadBackError || iLoop == 0)) \
290 { \
291 a_Worker((a_Type *)&abCompare[0]); \
292 Bs3MemCpy(abReadback, &MmioReg.pb[off], sizeof(a_Type)); \
293 if (Bs3MemCmp(abReadback, abCompare, sizeof(a_Type)) == 0) \
294 { /* likely */ } \
295 else if ( (a_fIsFnStEnv) \
296 && fMayHaveZeroStEnvSels \
297 && TMPL_NM(bs3FpuState1_IsZeroFnStEnvSelectorsProblem)(abReadback, abCompare)) \
298 cFnStEnvSelectorsZero += 1; \
299 else \
300 { \
301 Bs3TestFailedF("Read back error for " #a_Instr " in loop #%RU32:\n%.*Rhxs expected:\n%.*Rhxs\n", \
302 iLoop, sizeof(a_Type), abReadback, sizeof(a_Type), abCompare); \
303 fReadBackError = true; \
304 } \
305 } \
306 } while (0)
307
308# undef CHECK_READBACK_WRITE
309# define CHECK_READBACK_WRITE(a_Instr, a_Worker, a_Type, a_fIsFnStEnv) \
310 CHECK_READBACK_WRITE_RUN(a_Instr, a_Worker, a_Type, a_fIsFnStEnv); \
311 CHECK_STATE(a_Instr, a_fIsFnStEnv)
312# undef CHECK_READBACK_WRITE_Z
313# define CHECK_READBACK_WRITE_Z(a_Instr, a_Worker, a_Type, a_fIsFnStEnv) \
314 do { \
315 if (fMmioReadback && (!fReadBackError || iLoop == 0)) \
316 { \
317 Bs3MemZero(&abCompare[0], sizeof(a_Type)); \
318 off = (unsigned)(iLoop & (VMMDEV_TESTING_READBACK_SIZE / 2 - 1)); \
319 if (off + sizeof(a_Type) > VMMDEV_TESTING_READBACK_SIZE) \
320 off = VMMDEV_TESTING_READBACK_SIZE - sizeof(a_Type); \
321 Bs3MemZero(&MmioReg.pb[off], sizeof(a_Type)); \
322 } \
323 CHECK_READBACK_WRITE(a_Instr, a_Worker, a_Type, a_fIsFnStEnv); \
324 } while (0)
325
326# undef CHECK_READBACK_READ_RUN
327#define CHECK_READBACK_READ_RUN(a_Instr, a_Worker, a_Type) \
328 do { \
329 off = (unsigned)(iLoop & (VMMDEV_TESTING_READBACK_SIZE / 2 - 1)); \
330 if (off + sizeof(a_Type) > VMMDEV_TESTING_READBACK_SIZE) \
331 off = VMMDEV_TESTING_READBACK_SIZE - sizeof(a_Type); \
332 a_Worker((a_Type *)&MmioReg.pb[off], (a_Type *)&abReadback[0]); \
333 TMPL_NM(bs3FpuState1_Save)(pChecking); \
334 } while (0)
335# undef CHECK_READBACK_READ
336# define CHECK_READBACK_READ(a_Instr, a_Worker, a_Type) \
337 do { \
338 Bs3MemSet(&abReadback[0], 0xcc, sizeof(abReadback)); \
339 CHECK_READBACK_READ_RUN(a_Instr, a_Worker, a_Type); \
340 CHECK_STATE(a_Instr, false); \
341 if (!fReadError || iLoop == 0) \
342 { \
343 Bs3MemZero(&abCompare[0], sizeof(abCompare)); \
344 Bs3MemCpy(&abCompare[0], &MmioReg.pb[off], sizeof(a_Type)); \
345 if (Bs3MemCmp(abReadback, abCompare, sizeof(a_Type)) != 0) \
346 { \
347 Bs3TestFailedF("Read result check for " #a_Instr " in loop #%RU32:\n%.*Rhxs expected:\n%.*Rhxs\n", \
348 iLoop, sizeof(a_Type), abReadback, sizeof(a_Type), abCompare); \
349 fReadError = true; \
350 } \
351 } \
352 } while (0)
353
354 /* The tests. */
355 if (!fSkipStorIdt) /* KVM doesn't advance RIP executing a SIDT [MMIO-memory], it seems. (Linux 5.13.1) */
356 CHECK_READBACK_WRITE_Z(SIDT, ASMGetIDTR, RTIDTR, false);
357 CHECK_READBACK_WRITE_Z(FNSTENV, TMPL_NM(bs3FpuState1_FNStEnv), X86FSTENV32P, true); /** @todo x86.h is missing types */
358 CHECK_READBACK_WRITE( MOVDQU, TMPL_NM(bs3FpuState1_MovDQU_Write), X86XMMREG, false);
359 CHECK_READBACK_READ( MOVDQU, TMPL_NM(bs3FpuState1_MovDQU_Read), X86XMMREG);
360 CHECK_READBACK_WRITE( MOVUPS, TMPL_NM(bs3FpuState1_MovUPS_Write), X86XMMREG, false);
361 CHECK_READBACK_READ( MOVUPS, TMPL_NM(bs3FpuState1_MovUPS_Read), X86XMMREG);
362
363 /* Using the FPU is a little complicated, but we really need to check these things. */
364 CHECK_READBACK_READ_RUN(FMUL, TMPL_NM(bs3FpuState1_FMul), uint64_t);
365 if (enmCpuVendor == BS3CPUVENDOR_INTEL)
366# if BS3_MODE_IS_16BIT_CODE(TMPL_MODE)
367 pExpected->FOP = 0x040f; // skylake 6700k
368# else
369 pExpected->FOP = 0x040b; // skylake 6700k
370# endif
371 else if (enmCpuVendor == BS3CPUVENDOR_AMD && fFastFxSaveRestore)
372 pExpected->FOP = 0x0000; // Zen2 (3990x)
373 else
374 pExpected->FOP = 0x07dc; // dunno where we got this.
375# if ARCH_BITS == 64
376 pExpected->FPUDP = (uint32_t) (uintptr_t)&MmioReg.pb[off];
377 pExpected->DS = (uint16_t)((uintptr_t)&MmioReg.pb[off] >> 32);
378 pExpected->Rsrvd2 = (uint16_t)((uintptr_t)&MmioReg.pb[off] >> 48);
379# elif BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
380 pExpected->FPUDP = Bs3SelPtrToFlat(&MmioReg.pb[off]);
381# else
382 pExpected->FPUDP = BS3_FP_OFF(&MmioReg.pb[off]);
383# endif
384 if (enmCpuVendor == BS3CPUVENDOR_AMD && fFastFxSaveRestore)
385 pExpected->FPUDP = 0; // Zen2 (3990x)
386 CHECK_STATE(FMUL, false);
387
388 /* check for timeout every now an then. */
389 if ( (iLoop & 0xfff) == 0xfff
390 && g_cBs3PitTicks - uStartTick >= 20 * 20) /* 20 seconds*/
391 break;
392 }
393
394 Bs3PitDisable();
395
396# ifdef __WATCOMC__
397# pragma ENABLE_MESSAGE(201) /* Warning! W201: Unreachable code */
398# endif
399
400 /*
401 * Warn if selectors are borked (for real VBox we'll fail and not warn).
402 */
403 if (cFnStEnvSelectorsZero > 0)
404 Bs3TestPrintf("Warning! NEM borked the FPU selectors %u times.\n", cFnStEnvSelectorsZero);
405 return 0;
406}
407# endif
408#endif /* BS3_INSTANTIATING_MODE */
409
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