| 1 | ; $Id: bs3-cmn-RegCtxSave.asm 96407 2022-08-22 17:43:14Z vboxsync $
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| 2 | ;; @file
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| 3 | ; BS3Kit - Bs3RegCtxSave.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2022 Oracle and/or its affiliates.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox base platform packages, as
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| 10 | ; available from https://www.virtualbox.org.
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| 11 | ;
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| 12 | ; This program is free software; you can redistribute it and/or
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| 13 | ; modify it under the terms of the GNU General Public License
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| 14 | ; as published by the Free Software Foundation, in version 3 of the
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| 15 | ; License.
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| 16 | ;
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| 17 | ; This program is distributed in the hope that it will be useful, but
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| 18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | ; General Public License for more details.
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| 21 | ;
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| 22 | ; You should have received a copy of the GNU General Public License
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| 23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | ;
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| 25 | ; The contents of this file may alternatively be used under the terms
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| 26 | ; of the Common Development and Distribution License Version 1.0
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| 27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | ; in the VirtualBox distribution, in which case the provisions of the
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| 29 | ; CDDL are applicable instead of those of the GPL.
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| 30 | ;
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| 31 | ; You may elect to license modified versions of this file under the
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| 32 | ; terms and conditions of either the GPL or the CDDL or both.
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| 33 | ;
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| 34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | ;
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| 36 |
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| 37 | %include "bs3kit-template-header.mac"
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| 38 |
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| 39 |
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| 40 | BS3_EXTERN_SYSTEM16 Bs3Gdt
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| 41 | BS3_EXTERN_DATA16 g_bBs3CurrentMode
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| 42 | %if TMPL_BITS != 64
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| 43 | BS3_EXTERN_DATA16 g_uBs3CpuDetected
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| 44 | %endif
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| 45 | TMPL_BEGIN_TEXT
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| 46 |
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| 47 |
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| 48 |
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| 49 | ;;
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| 50 | ; Saves the current register context.
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| 51 | ;
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| 52 | ; @param pRegCtx
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| 53 | ; @uses None.
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| 54 | ;
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| 55 | BS3_PROC_BEGIN_CMN Bs3RegCtxSave, BS3_PBC_HYBRID_SAFE
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| 56 | TONLY16 CPU 8086
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| 57 | BS3_CALL_CONV_PROLOG 1
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| 58 | push xBP
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| 59 | mov xBP, xSP
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| 60 | xPUSHF ; xBP - xCB*1: save the incoming flags exactly.
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| 61 | push xAX ; xBP - xCB*2: save incoming xAX
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| 62 | push xCX ; xBP - xCB*3: save incoming xCX
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| 63 | push xDI ; xBP - xCB*4: save incoming xDI
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| 64 | BONLY16 push es ; xBP - xCB*5
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| 65 | BONLY16 push ds ; xBP - xCB*6
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| 66 |
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| 67 | ;
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| 68 | ; Clear the whole structure first.
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| 69 | ;
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| 70 | xor xAX, xAX
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| 71 | cld
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| 72 | AssertCompileSizeAlignment(BS3REGCTX, 4)
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| 73 | %if TMPL_BITS == 16
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| 74 | les xDI, [xBP + xCB + cbCurRetAddr]
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| 75 | mov xCX, BS3REGCTX_size / 2
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| 76 | rep stosw
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| 77 | %else
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| 78 | mov xDI, [xBP + xCB + cbCurRetAddr]
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| 79 | mov xCX, BS3REGCTX_size / 4
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| 80 | rep stosd
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| 81 | %endif
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| 82 | mov xDI, [xBP + xCB + cbCurRetAddr]
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| 83 |
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| 84 | ;
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| 85 | ; Save the current mode.
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| 86 | ;
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| 87 | mov cl, [BS3_DATA16_WRT(g_bBs3CurrentMode)]
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| 88 | mov [BS3_ONLY_16BIT(es:) xDI + BS3REGCTX.bMode], cl
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| 89 | %if TMPL_BITS == 16
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| 90 |
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| 91 | ;
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| 92 | ; In 16-bit mode we could be running on really ancient CPUs, so check
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| 93 | ; mode and detected CPU and proceed with care.
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| 94 | ;
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| 95 | cmp cl, BS3_MODE_PP16
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| 96 | jae .save_full
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| 97 |
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| 98 | mov cl, [BS3_DATA16_WRT(g_uBs3CpuDetected)]
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| 99 | cmp cl, BS3CPU_80386
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| 100 | jae .save_full
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| 101 |
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| 102 | ; load ES into DS so we can save some segment prefix bytes.
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| 103 | push es
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| 104 | pop ds
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| 105 |
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| 106 | ; 16-bit GPRs not on the stack.
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| 107 | mov [xDI + BS3REGCTX.rdx], dx
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| 108 | mov [xDI + BS3REGCTX.rbx], bx
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| 109 | mov [xDI + BS3REGCTX.rsi], si
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| 110 |
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| 111 | ; Join the common code.
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| 112 | cmp cl, BS3CPU_80286
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| 113 | jb .common_ancient
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| 114 | CPU 286
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| 115 | smsw [xDI + BS3REGCTX.cr0]
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| 116 |
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| 117 | mov cl, [xDI + BS3REGCTX.bMode] ; assumed by jump destination
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| 118 | jmp .common_80286
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| 119 |
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| 120 | CPU 386
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| 121 | %endif
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| 122 |
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| 123 |
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| 124 | .save_full:
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| 125 | ;
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| 126 | ; 80386 or later.
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| 127 | ;
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| 128 | %if TMPL_BITS != 64
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| 129 | ; Check for CR4 here while we've got a working DS in all contexts.
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| 130 | test byte [1 + BS3_DATA16_WRT(g_uBs3CpuDetected)], (BS3CPU_F_CPUID >> 8)
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| 131 | jnz .save_full_have_cr4
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| 132 | or byte [BS3_ONLY_16BIT(es:) xDI + BS3REGCTX.fbFlags], BS3REG_CTX_F_NO_CR4
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| 133 | .save_full_have_cr4:
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| 134 | %endif
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| 135 | %if TMPL_BITS == 16
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| 136 | ; Load es into ds so we can save ourselves some segment prefix bytes.
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| 137 | push es
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| 138 | pop ds
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| 139 | %endif
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| 140 |
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| 141 | ; GPRs first.
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| 142 | mov [xDI + BS3REGCTX.rdx], sDX
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| 143 | mov [xDI + BS3REGCTX.rbx], sBX
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| 144 | mov [xDI + BS3REGCTX.rsi], sSI
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| 145 | %if TMPL_BITS == 64
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| 146 | mov [xDI + BS3REGCTX.r8], r8
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| 147 | mov [xDI + BS3REGCTX.r9], r9
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| 148 | mov [xDI + BS3REGCTX.r10], r10
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| 149 | mov [xDI + BS3REGCTX.r11], r11
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| 150 | mov [xDI + BS3REGCTX.r12], r12
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| 151 | mov [xDI + BS3REGCTX.r13], r13
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| 152 | mov [xDI + BS3REGCTX.r14], r14
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| 153 | mov [xDI + BS3REGCTX.r15], r15
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| 154 | %else
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| 155 | or byte [xDI + BS3REGCTX.fbFlags], BS3REG_CTX_F_NO_AMD64
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| 156 | %endif
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| 157 | %if TMPL_BITS == 16 ; Save high bits.
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| 158 | mov [xDI + BS3REGCTX.rax], eax
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| 159 | mov [xDI + BS3REGCTX.rcx], ecx
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| 160 | mov [xDI + BS3REGCTX.rdi], edi
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| 161 | mov [xDI + BS3REGCTX.rbp], ebp
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| 162 | mov [xDI + BS3REGCTX.rsp], esp
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| 163 | pushfd
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| 164 | pop dword [xDI + BS3REGCTX.rflags]
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| 165 | %endif
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| 166 | %if TMPL_BITS != 64
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| 167 | ; The VM flag is never on the stack, so derive it from the bMode we saved above.
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| 168 | test byte [xDI + BS3REGCTX.bMode], BS3_MODE_CODE_V86
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| 169 | jz .not_v8086
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| 170 | or byte [xDI + BS3REGCTX.rflags + 2], X86_EFL_VM >> 16
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| 171 | mov byte [xDI + BS3REGCTX.bCpl], 3
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| 172 | .not_v8086:
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| 173 | %endif
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| 174 |
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| 175 | ; 386 segment registers.
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| 176 | mov [xDI + BS3REGCTX.fs], fs
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| 177 | mov [xDI + BS3REGCTX.gs], gs
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| 178 |
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| 179 | %if TMPL_BITS == 16 ; v8086 and real mode woes.
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| 180 | mov cl, [xDI + BS3REGCTX.bMode]
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| 181 | cmp cl, BS3_MODE_RM
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| 182 | je .common_full_control_regs
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| 183 | test cl, BS3_MODE_CODE_V86
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| 184 | jnz .common_full_no_control_regs
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| 185 | %endif
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| 186 | mov ax, ss
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| 187 | test al, 3
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| 188 | jnz .common_full_no_control_regs
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| 189 |
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| 190 | ; Control registers (ring-0 and real-mode only).
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| 191 | .common_full_control_regs:
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| 192 | mov sAX, cr0
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| 193 | mov [xDI + BS3REGCTX.cr0], sAX
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| 194 | mov sAX, cr2
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| 195 | mov [xDI + BS3REGCTX.cr2], sAX
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| 196 | mov sAX, cr3
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| 197 | mov [xDI + BS3REGCTX.cr3], sAX
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| 198 | %if TMPL_BITS != 64
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| 199 | test byte [xDI + BS3REGCTX.fbFlags], BS3REG_CTX_F_NO_CR4
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| 200 | jnz .common_80286
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| 201 | %endif
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| 202 | mov sAX, cr4
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| 203 | mov [xDI + BS3REGCTX.cr4], sAX
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| 204 | jmp .common_80286
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| 205 |
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| 206 | .common_full_no_control_regs:
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| 207 | or byte [xDI + BS3REGCTX.fbFlags], BS3REG_CTX_F_NO_CR0_IS_MSW | BS3REG_CTX_F_NO_CR2_CR3 | BS3REG_CTX_F_NO_CR4
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| 208 | smsw [xDI + BS3REGCTX.cr0]
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| 209 |
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| 210 | ; 80286 control registers.
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| 211 | .common_80286:
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| 212 | TONLY16 CPU 286
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| 213 | %if TMPL_BITS != 64
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| 214 | cmp cl, BS3_MODE_RM
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| 215 | je .no_str_sldt
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| 216 | test cl, BS3_MODE_CODE_V86
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| 217 | jnz .no_str_sldt
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| 218 | %endif
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| 219 | str [xDI + BS3REGCTX.tr]
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| 220 | sldt [xDI + BS3REGCTX.ldtr]
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| 221 | jmp .common_ancient
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| 222 |
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| 223 | .no_str_sldt:
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| 224 | or byte [xDI + BS3REGCTX.fbFlags], BS3REG_CTX_F_NO_TR_LDTR
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| 225 |
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| 226 | ; Common stuff - stuff on the stack, 286 segment registers.
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| 227 | .common_ancient:
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| 228 | TONLY16 CPU 8086
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| 229 | mov xAX, [xBP - xCB*1]
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| 230 | mov [xDI + BS3REGCTX.rflags], xAX
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| 231 | mov xAX, [xBP - xCB*2]
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| 232 | mov [xDI + BS3REGCTX.rax], xAX
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| 233 | mov xAX, [xBP - xCB*3]
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| 234 | mov [xDI + BS3REGCTX.rcx], xAX
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| 235 | mov xAX, [xBP - xCB*4]
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| 236 | mov [xDI + BS3REGCTX.rdi], xAX
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| 237 | mov xAX, [xBP]
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| 238 | mov [xDI + BS3REGCTX.rbp], xAX
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| 239 | mov xAX, [xBP + xCB]
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| 240 | mov [xDI + BS3REGCTX.rip], xAX
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| 241 | lea xAX, [xBP + xCB + cbCurRetAddr]
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| 242 | mov [xDI + BS3REGCTX.rsp], xAX
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| 243 |
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| 244 | %if TMPL_BITS == 16
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| 245 | mov ax, [xBP + xCB + 2]
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| 246 | mov [xDI + BS3REGCTX.cs], ax
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| 247 | mov ax, [xBP - xCB*6]
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| 248 | mov [xDI + BS3REGCTX.ds], ax
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| 249 | mov ax, [xBP - xCB*5]
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| 250 | mov [xDI + BS3REGCTX.es], ax
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| 251 | %else
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| 252 | mov [xDI + BS3REGCTX.cs], cs
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| 253 | mov [xDI + BS3REGCTX.ds], ds
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| 254 | mov [xDI + BS3REGCTX.es], es
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| 255 | %endif
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| 256 | mov [xDI + BS3REGCTX.ss], ss
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| 257 |
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| 258 | ;
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| 259 | ; Return.
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| 260 | ;
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| 261 | .return:
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| 262 | BONLY16 pop ds
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| 263 | BONLY16 pop es
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| 264 | pop xDI
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| 265 | pop xCX
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| 266 | pop xAX
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| 267 | xPOPF
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| 268 | pop xBP
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| 269 | BS3_HYBRID_RET
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| 270 | BS3_PROC_END_CMN Bs3RegCtxSave
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| 271 |
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