| 1 | /* $Id: bs3-cmn-Trap64Init.c 106061 2024-09-16 14:03:52Z vboxsync $ */
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| 2 | /** @file
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| 3 | * BS3Kit - Bs3Trap64Init
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2007-2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * The contents of this file may alternatively be used under the terms
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| 26 | * of the Common Development and Distribution License Version 1.0
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| 27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | * in the VirtualBox distribution, in which case the provisions of the
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| 29 | * CDDL are applicable instead of those of the GPL.
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| 30 | *
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| 31 | * You may elect to license modified versions of this file under the
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| 32 | * terms and conditions of either the GPL or the CDDL or both.
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| 33 | *
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| 34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | */
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| 36 |
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| 37 |
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| 38 | /*********************************************************************************************************************************
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| 39 | * Header Files *
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| 40 | *********************************************************************************************************************************/
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| 41 | #include "bs3kit-template-header.h"
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| 42 |
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| 43 |
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| 44 | #undef Bs3Trap64Init
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| 45 | BS3_CMN_DEF(void, Bs3Trap64Init,(void))
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| 46 | {
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| 47 | Bs3Trap64InitEx(false);
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| 48 | }
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| 49 |
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| 50 | #undef Bs3Trap64InitEx
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| 51 | BS3_CMN_DEF(void, Bs3Trap64InitEx,(bool fMoreIstUsage))
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| 52 | {
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| 53 | static const uint8_t s_aAssignments[] =
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| 54 | {
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| 55 | /* [X86_XCPT_DE] = */ 3,
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| 56 | /* [X86_XCPT_DB] = */ 2,
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| 57 | /* [X86_XCPT_NMI] = */ 0,
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| 58 | /* [X86_XCPT_BP] = */ 2,
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| 59 | /* [X86_XCPT_OF] = */ 3,
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| 60 | /* [X86_XCPT_BR] = */ 3,
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| 61 | /* [X86_XCPT_UD] = */ 4,
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| 62 | /* [X86_XCPT_NM] = */ 3,
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| 63 | /* [X86_XCPT_DF] = */ 1,
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| 64 | /* [0x09] = */ 0,
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| 65 | /* [X86_XCPT_TS] = */ 1,
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| 66 | /* [X86_XCPT_NP] = */ 5,
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| 67 | /* [X86_XCPT_SS] = */ 5,
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| 68 | /* [X86_XCPT_GP] = */ 6,
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| 69 | /* [X86_XCPT_PF] = */ 7,
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| 70 | /* [0x0f] = */ 0,
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| 71 | /* [X86_XCPT_MF] = */ 0,
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| 72 | /* [X86_XCPT_AC] = */ 3,
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| 73 | /* [X86_XCPT_MC] = */ 0,
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| 74 | /* [X86_XCPT_XF] = */ 0,
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| 75 | /* [X86_XCPT_VE] = */ 0,
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| 76 | /* [X86_XCPT_CP] = */ 6,
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| 77 | };
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| 78 | #ifdef _MSC_VER /* No-SSE hack */
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| 79 | X86TSS64 BS3_FAR volatile *pTss;
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| 80 | #else
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| 81 | X86TSS64 BS3_FAR *pTss;
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| 82 | #endif
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| 83 | unsigned iIdt;
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| 84 |
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| 85 | /*
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| 86 | * IDT entries, except the system call gate.
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| 87 | * The #DF entry get IST=1, all others IST=0.
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| 88 | */
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| 89 | for (iIdt = 0; iIdt < BS3_TRAP_SYSCALL; iIdt++)
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| 90 | Bs3Trap64SetGate(iIdt, AMD64_SEL_TYPE_SYS_INT_GATE, 0 /*bDpl*/,
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| 91 | BS3_SEL_R0_CS64, g_Bs3Trap64GenericEntriesFlatAddr + iIdt * 8,
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| 92 | !fMoreIstUsage ? iIdt == X86_XCPT_DF : iIdt < RT_ELEMENTS(s_aAssignments) ? s_aAssignments[iIdt] : 0);
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| 93 | for (iIdt = BS3_TRAP_SYSCALL + 1; iIdt < 256; iIdt++)
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| 94 | Bs3Trap64SetGate(iIdt, AMD64_SEL_TYPE_SYS_INT_GATE, 0 /*bDpl*/,
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| 95 | BS3_SEL_R0_CS64, g_Bs3Trap64GenericEntriesFlatAddr + iIdt * 8, 0);
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| 96 |
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| 97 | /*
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| 98 | * Initialize the normal TSS so we can do ring transitions via the IDT.
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| 99 | */
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| 100 | pTss = &Bs3Tss64;
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| 101 | Bs3MemZero(pTss, sizeof(*pTss));
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| 102 | pTss->rsp0 = BS3_ADDR_STACK_R0;
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| 103 | pTss->rsp1 = BS3_ADDR_STACK_R1;
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| 104 | pTss->rsp2 = BS3_ADDR_STACK_R2;
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| 105 | pTss->ist1 = BS3_ADDR_STACK_R0_IST1;
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| 106 | pTss->ist2 = BS3_ADDR_STACK_R0_IST2;
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| 107 | pTss->ist3 = BS3_ADDR_STACK_R0_IST3;
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| 108 | pTss->ist4 = BS3_ADDR_STACK_R0_IST4;
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| 109 | pTss->ist5 = BS3_ADDR_STACK_R0_IST5;
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| 110 | pTss->ist6 = BS3_ADDR_STACK_R0_IST6;
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| 111 | pTss->ist7 = BS3_ADDR_STACK_R0_IST7;
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| 112 | }
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| 113 |
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