| 1 | ; $Id: bs3-mode-CpuDetect.asm 60556 2016-04-18 19:26:35Z vboxsync $
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| 2 | ;; @file
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| 3 | ; BS3Kit - Bs3CpuDetect
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2016 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; The contents of this file may alternatively be used under the terms
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| 18 | ; of the Common Development and Distribution License Version 1.0
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| 19 | ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | ; VirtualBox OSE distribution, in which case the provisions of the
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| 21 | ; CDDL are applicable instead of those of the GPL.
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| 22 | ;
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| 23 | ; You may elect to license modified versions of this file under the
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| 24 | ; terms and conditions of either the GPL or the CDDL or both.
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| 25 | ;
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| 26 |
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| 27 | %include "bs3kit-template-header.mac"
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| 28 |
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| 29 | BS3_EXTERN_DATA16 g_uBs3CpuDetected
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| 30 |
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| 31 |
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| 32 | ;;
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| 33 | ; Rough CPU detection, mainly for detecting really old CPUs.
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| 34 | ;
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| 35 | ; A Bs3CpuDetectEx can be added if this is insufficient.
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| 36 | ;
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| 37 | ; @returns BS3CPU_xxx in xAX.
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| 38 | ; @cproto BS3_DECL(BS3CPU) Bs3CpuDetect(void);
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| 39 | ;
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| 40 | ; @uses xAX.
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| 41 | ;
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| 42 | ; @remarks ASSUMES we're in ring-0 when not in some kind of real mode.
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| 43 | ;
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| 44 | ; @note We put the real mode version of this code in the RMTEXT16 segment
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| 45 | ; to save space elsewhere. We generate a far call stub that goes
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| 46 | ; to the right segment.
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| 47 | ;
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| 48 | %if TMPL_MODE == BS3_MODE_RM
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| 49 | BS3_BEGIN_RMTEXT16
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| 50 | BS3_PROC_BEGIN_MODE Bs3CpuDetect, BS3_PBC_FAR
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| 51 | %else
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| 52 | TMPL_BEGIN_TEXT
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| 53 | BS3_PROC_BEGIN_MODE Bs3CpuDetect, BS3_PBC_HYBRID
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| 54 | %endif
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| 55 | CPU 8086
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| 56 | push xBP
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| 57 | mov xBP, xSP
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| 58 | pushf
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| 59 | push xCX
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| 60 | push xDX
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| 61 | push xBX
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| 62 |
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| 63 | %ifndef TMPL_CMN_PAGING
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| 64 | %ifdef TMPL_RM
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| 65 | %if 1 ; this is simpler
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| 66 | ;
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| 67 | ; FLAGS bits 15:12 are always set on 8086, 8088, V20, V30, 80186, and
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| 68 | ; 80188. FLAGS bit 15 is always zero on 286+, whereas bit 14 is NT and
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| 69 | ; bits 13:12 are IOPL.
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| 70 | ;
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| 71 | test byte [xBP - xCB + 1], 80h ; Top byte of saved flags.
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| 72 | jz .286plus
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| 73 | %else
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| 74 | ;
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| 75 | ; When executing 'PUSH SP' the 8086, 8088, V20, V30, 80186, and 80188
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| 76 | ; should be pushing the updated SP value instead of the initial one.
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| 77 | ;
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| 78 | push xSP
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| 79 | pop xAX
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| 80 | cmp xAX, xSP
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| 81 | je .286plus
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| 82 | %endif
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| 83 |
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| 84 | ;
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| 85 | ; Older than 286.
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| 86 | ;
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| 87 | ; Detect 8086/8088/V20/V30 vs. 80186/80188 by checking for pre 80186
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| 88 | ; shift behavior. the 80186/188 and later will mask the CL value according
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| 89 | ; to the width of the destination register, whereas 8086/88 and V20/30 will
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| 90 | ; perform the exact number of shifts specified.
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| 91 | ;
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| 92 | mov cl, 20h ; Shift count; 80186/88 and later will mask this by 0x1f (or 0xf)?
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| 93 | mov dx, 7fh
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| 94 | shl dx, cl
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| 95 | cmp dx, 7fh ; If no change, this is a 80186/88.
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| 96 | mov xAX, BS3CPU_80186
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| 97 | je .return
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| 98 |
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| 99 | ;
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| 100 | ; Detect 8086/88 vs V20/30 by exploiting undocumented POP CS encoding
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| 101 | ; that was redefined on V20/30 to SET1.
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| 102 | ;
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| 103 | xor ax, ax ; clear
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| 104 | push cs
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| 105 | db 0fh ; 8086/88: pop cs V20/30: set1 bl,cl
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| 106 | db 14h, 3ch ; 8086/88: add al, 3ch
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| 107 | ; 8086/88: al = 3ch V20/30: al = 0, cs on stack, bl modified.
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| 108 | cmp al, 3ch
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| 109 | jne .is_v20_or_v30
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| 110 | mov xAX, BS3CPU_8086
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| 111 | jmp .return
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| 112 |
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| 113 | .is_v20_or_v30:
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| 114 | pop xCX ; unclaimed CS
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| 115 | mov xAX, BS3CPU_V20
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| 116 | jmp .return
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| 117 |
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| 118 | %endif ; TMPL_RM
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| 119 |
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| 120 | CPU 286
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| 121 | .286plus:
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| 122 | ;
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| 123 | ; The 4th bit of the machine status word / CR0 indicates the precense
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| 124 | ; of a 80387 or later co-processor (a 80287+80386 => ET=0). 486 and
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| 125 | ; later should be hardcoding this to 1, according to the documentation
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| 126 | ; (need to test on 486SX). The initial idea here then would be to
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| 127 | ; assume 386+ if ET=1.
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| 128 | ;
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| 129 | ; However, it turns out the 286 I've got here has bits 4 thru 15 all
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| 130 | ; set. This is very nice though, because only bits 4 and 5 are defined
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| 131 | ; on later CPUs and the remainder MBZ. So, check whether any of the MBZ
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| 132 | ; bits are set, if so, then it's 286.
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| 133 | ;
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| 134 | smsw ax
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| 135 | test ax, ~(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE)
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| 136 | jnz .is_286
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| 137 |
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| 138 | ;
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| 139 | ; Detect 80286 by checking whether the IOPL and NT bits of EFLAGS can be
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| 140 | ; modified or not. There are different accounts of these bits. Dr.Dobb's
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| 141 | ; (http://www.drdobbs.com/embedded-systems/processor-detection-schemes/184409011)
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| 142 | ; say they are undefined on 286es and will always be zero. Whereas Intel
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| 143 | ; iAPX 286 Programmer's Reference Manual (both order #210498-001 and
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| 144 | ; #210498-003) documents both IOPL and NT, but with comment 4 on page
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| 145 | ; C-43 stating that they cannot be POPFed in real mode and will both
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| 146 | ; remain 0. This is different from the 386+, where the NT flag isn't
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| 147 | ; privileged according to page 3-37 in #230985-003. Later Intel docs
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| 148 | ; (#235383-052US, page 4-192) documents real mode as taking both NT and
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| 149 | ; IOPL from what POPF reads off the stack - which is the behavior
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| 150 | ; observed a 386SX here.
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| 151 | ;
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| 152 | test al, X86_CR0_PE ; This flag test doesn't work in protected mode, ...
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| 153 | jnz .386plus ; ... so ASSUME 386plus if in PE for now.
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| 154 |
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| 155 | pushf ; Save a copy of the original flags for restoring IF.
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| 156 | pushf
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| 157 | pop ax
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| 158 | xor ax, X86_EFL_IOPL | X86_EFL_NT ; Try modify IOPL and NT.
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| 159 | and ax, ~X86_EFL_IF ; Try clear IF.
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| 160 | push ax ; Load modified flags.
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| 161 | popf
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| 162 | pushf ; Get actual flags.
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| 163 | pop dx
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| 164 | popf ; Restore IF, IOPL and NT.
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| 165 | cmp ax, dx
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| 166 | je .386plus ; If any of the flags are set, we're on 386+.
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| 167 |
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| 168 | ; While we could in theory be in v8086 mode at this point and be fooled
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| 169 | ; by a flaky POPF implementation, we assume this isn't the case in our
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| 170 | ; execution environment.
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| 171 |
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| 172 | .is_286:
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| 173 | mov ax, BS3CPU_80286
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| 174 | jmp .return
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| 175 | %endif ; !TMPL_CMN_PAGING
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| 176 |
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| 177 | CPU 386
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| 178 | .386plus:
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| 179 | ;
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| 180 | ; Check for CPUID and AC. The former flag indicates CPUID support, the
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| 181 | ; latter was introduced with the 486.
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| 182 | ;
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| 183 | mov ebx, esp ; Save esp.
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| 184 | and esp, 0fffch ; Clear high word and don't trigger ACs.
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| 185 | pushfd
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| 186 | mov eax, [esp] ; eax = original EFLAGS.
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| 187 | xor dword [esp], X86_EFL_ID | X86_EFL_AC ; Flip the ID and AC flags.
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| 188 | popfd ; Load modified flags.
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| 189 | pushfd ; Save actual flags.
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| 190 | xchg eax, [esp] ; Switch, so the stack has the original flags.
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| 191 | xor eax, [esp] ; Calc changed flags.
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| 192 | popf ; Restore EFLAGS.
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| 193 | mov esp, ebx ; Restore possibly unaligned ESP.
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| 194 | test eax, X86_EFL_ID
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| 195 | jnz .have_cpuid ; If ID changed, we've got CPUID.
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| 196 | test eax, X86_EFL_AC
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| 197 | mov xAX, BS3CPU_80486
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| 198 | jnz .return ; If AC changed, we've got a 486 without CPUID (or similar).
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| 199 | mov xAX, BS3CPU_80386
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| 200 | jmp .return
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| 201 |
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| 202 | CPU 586
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| 203 | .have_cpuid:
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| 204 | ;
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| 205 | ; Do a very simple minded check here using the (standard) family field.
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| 206 | ; While here, we also check for PAE.
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| 207 | ;
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| 208 | mov eax, 1
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| 209 | cpuid
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| 210 |
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| 211 | ; Calc the extended family and model values before we mess up EAX.
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| 212 | mov cl, ah
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| 213 | and cl, 0fh
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| 214 | cmp cl, 0fh
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| 215 | jnz .not_extended_family
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| 216 | mov ecx, eax
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| 217 | shr ecx, 20
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| 218 | and cl, 7fh
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| 219 | add cl, 0fh
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| 220 | .not_extended_family: ; cl = family
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| 221 | mov ch, al
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| 222 | shr ch, 4
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| 223 | cmp cl, 0fh
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| 224 | jae .extended_model
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| 225 | cmp cl, 06h ; actually only intel, but we'll let this slip for now.
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| 226 | jne .done_model
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| 227 | .extended_model:
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| 228 | shr eax, 12
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| 229 | and al, 0f0h
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| 230 | or ch, al
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| 231 | .done_model: ; ch = model
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| 232 |
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| 233 | ; Start assembling return flags, checking for PSE + PAE.
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| 234 | mov eax, X86_CPUID_FEATURE_EDX_PSE | X86_CPUID_FEATURE_EDX_PAE
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| 235 | and eax, edx
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| 236 | mov ah, al
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| 237 | AssertCompile(X86_CPUID_FEATURE_EDX_PAE_BIT > BS3CPU_F_PAE_BIT - 8) ; 6 vs 10-8=2
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| 238 | and al, X86_CPUID_FEATURE_EDX_PAE
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| 239 | shr al, X86_CPUID_FEATURE_EDX_PAE_BIT - (BS3CPU_F_PAE_BIT - 8)
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| 240 | AssertCompile(X86_CPUID_FEATURE_EDX_PSE_BIT == BS3CPU_F_PSE_BIT - 8) ; 3 vs 11-8=3
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| 241 | and ah, X86_CPUID_FEATURE_EDX_PSE
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| 242 | or ah, al
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| 243 | or ah, (BS3CPU_F_CPUID >> 8)
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| 244 |
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| 245 | ; Add the CPU type based on the family and model values.
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| 246 | cmp cl, 6
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| 247 | jne .not_family_06h
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| 248 | mov al, BS3CPU_PPro
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| 249 | cmp ch, 1
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| 250 | jbe .return
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| 251 | mov al, BS3CPU_PProOrNewer
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| 252 | jmp .NewerThanPPro
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| 253 |
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| 254 | .not_family_06h:
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| 255 | mov al, BS3CPU_PProOrNewer
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| 256 | ja .NewerThanPPro
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| 257 | cmp cl, 5
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| 258 | mov al, BS3CPU_Pentium
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| 259 | je .return
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| 260 | cmp cl, 4
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| 261 | mov al, BS3CPU_80486
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| 262 | je .return
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| 263 | cmp cl, 3
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| 264 | mov al, BS3CPU_80386
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| 265 | je .return
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| 266 |
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| 267 | .NewerThanPPro:
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| 268 |
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| 269 | ; Check for extended leaves and long mode.
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| 270 | push xAX ; save PAE+PProOrNewer
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| 271 | mov eax, 0x80000000
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| 272 | cpuid
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| 273 | sub eax, 0x80000001 ; Minimum leaf 0x80000001
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| 274 | cmp eax, 0x00010000 ; At most 0x10000 leaves.
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| 275 | ja .no_ext_leaves
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| 276 |
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| 277 | mov eax, 0x80000001
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| 278 | cpuid
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| 279 | pop xAX ; restore PAE+PProOrNewer
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| 280 | test edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
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| 281 | jz .no_long_mode
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| 282 | or ax, BS3CPU_F_CPUID_EXT_LEAVES | BS3CPU_F_LONG_MODE
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| 283 | jmp .return
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| 284 | .no_long_mode:
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| 285 | or ax, BS3CPU_F_CPUID_EXT_LEAVES
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| 286 | jmp .return
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| 287 | .no_ext_leaves:
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| 288 | pop xAX ; restore PAE+PProOrNewer
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| 289 |
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| 290 | CPU 8086
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| 291 | .return:
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| 292 | ;
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| 293 | ; Save the return value.
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| 294 | ;
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| 295 | mov [BS3_DATA16_WRT(g_uBs3CpuDetected)], ax
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| 296 |
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| 297 | ;
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| 298 | ; Epilogue.
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| 299 | ;
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| 300 | pop xBX
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| 301 | pop xDX
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| 302 | pop xCX
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| 303 | popf
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| 304 | pop xBP
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| 305 | BS3_HYBRID_RET
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| 306 |
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| 307 | BS3_PROC_END_MODE Bs3CpuDetect
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| 308 |
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| 309 |
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| 310 | %if TMPL_MODE == BS3_MODE_RM
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| 311 | BS3_BEGIN_TEXT16_NEARSTUBS
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| 312 | BS3_PROC_BEGIN_MODE Bs3CpuDetect, BS3_PBC_NEAR
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| 313 | call far TMPL_FAR_NM(Bs3CpuDetect)
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| 314 | ret
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| 315 | BS3_PROC_END_MODE Bs3CpuDetect
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| 316 | %endif
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| 317 |
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