VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/utils/cpu/cidet.h@ 76553

Last change on this file since 76553 was 76553, checked in by vboxsync, 6 years ago

scm --update-copyright-year

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 43.0 KB
Line 
1/* $Id: cidet.h 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * CPU Instruction Decoding & Execution Tests - C/C++ Header.
4 */
5
6/*
7 * Copyright (C) 2014-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27#ifndef ___cidet_h___
28#define ___cidet_h___
29#ifndef RT_WITHOUT_PRAGMA_ONCE
30# pragma once
31#endif
32
33#include <iprt/types.h>
34#include <iprt/x86.h>
35
36
37/** @name CIDET - Operand flags.
38 * @{ */
39#define CIDET_OF_FIXED_MASK UINT32_C(0x0000001f) /**< Fixed register/whatever mask. */
40
41#define CIDET_OF_Z_SHIFT 8 /**< Size shift. */
42#define CIDET_OF_Z_MASK UINT32_C(0x00000f00) /**< Size mask. */
43#define CIDET_OF_Z_NONE UINT32_C(0x00000000) /**< Unused zero value. */
44#define CIDET_OF_Z_BYTE UINT32_C(0x00000100) /**< Byte size. */
45#define CIDET_OF_Z_WORD UINT32_C(0x00000200) /**< Word (2 bytes) size. */
46#define CIDET_OF_Z_DWORD UINT32_C(0x00000300) /**< Double word (4 bytes) size. */
47#define CIDET_OF_Z_QWORD UINT32_C(0x00000400) /**< Quad word (8 bytes) size. */
48#define CIDET_OF_Z_TBYTE UINT32_C(0x00000500) /**< Ten byte (10 bytes) size - aka TWORD. */
49#define CIDET_OF_Z_OWORD UINT32_C(0x00000600) /**< Octa word (16 bytes) size - aka DQWORD. */
50#define CIDET_OF_Z_YWORD UINT32_C(0x00000700) /**< Yxx sized, i.e. 32 bytes. */
51#define CIDET_OF_Z_ZWORD UINT32_C(0x00000800) /**< Zxx sized, i.e. 64 bytes. */
52#define CIDET_OF_Z_VAR_WDQ UINT32_C(0x00000900) /**< Variable size depending on size prefix (2, 4, or 8 bytes). */
53#define CIDET_OF_Z_SPECIAL UINT32_C(0x00000f00) /**< Special size, see instruction flags or smth. */
54
55#define CIDET_OF_K_MASK UINT32_C(0x0000f000) /**< Kind of operand. */
56#define CIDET_OF_K_NONE UINT32_C(0x00000000) /**< Unused zero value. */
57#define CIDET_OF_K_GPR UINT32_C(0x00001000) /**< General purpose register. Includes memory when used with CIDET_OF_M_RM. */
58#define CIDET_OF_K_SREG UINT32_C(0x00002000) /**< Segment register. */
59#define CIDET_OF_K_CR UINT32_C(0x00003000) /**< Control register. */
60#define CIDET_OF_K_SSE UINT32_C(0x00004000) /**< SSE register. */
61#define CIDET_OF_K_AVX UINT32_C(0x00005000) /**< AVX register. */
62#define CIDET_OF_K_AVX512 UINT32_C(0x00006000) /**< AVX-512 register. */
63#define CIDET_OF_K_AVXFUTURE UINT32_C(0x00007000) /**< Reserved for future AVX register set. */
64#define CIDET_OF_K_VRX_TST_MASK UINT32_C(0x0000c000) /**< Used for testing for VRX register kind, see CIDET_OF_K_IS_VRX. */
65#define CIDET_OF_K_VRX_TST_RES UINT32_C(0x00004000) /**< Used for testing for VRX register kind, see CIDET_OF_K_IS_VRX. */
66#define CIDET_OF_K_FPU UINT32_C(0x00008000) /**< FPU register. */
67#define CIDET_OF_K_MMX UINT32_C(0x00009000) /**< MMX register. */
68#define CIDET_OF_K_TEST UINT32_C(0x0000a000) /**< Test register. */
69#define CIDET_OF_K_IMM UINT32_C(0x0000d000) /**< Immediate. */
70#define CIDET_OF_K_MEM UINT32_C(0x0000e000) /**< Memory. */
71#define CIDET_OF_K_SPECIAL UINT32_C(0x0000f000) /**< Special. */
72/** Check if @a a_fOp is a general purpose register. */
73#define CIDET_OF_K_IS_GPR(a_fOp) ( ((a_fOp) & CIDET_OF_K_MASK) == CIDET_OF_K_GPR )
74/** Check if @a a_fOp is a XMM (SSE), YMM (AVX), ZMM (AVX-512) or similar register. */
75#define CIDET_OF_K_IS_VRX(a_fOp) ( ((a_fOp) & CIDET_OF_K_VRX_TST_MASK) == CIDET_OF_K_VRX_TST_RES )
76/** Check if @a a_fOp1 and @a a_fOp2 specify the same kind of register,
77 * treating SSE, AVX, AVX-512 and AVX-future as the same kind and ignoring the
78 * special register kind. */
79#define CIDET_OF_K_IS_SAME(a_fOp1, a_fOp2) \
80 ( ((a_fOp1) & CIDET_OF_K_MASK) == ((a_fOp2) & CIDET_OF_K_MASK) \
81 ? ((a_fOp1) & CIDET_OF_K_MASK) != CIDET_OF_K_SPECIAL \
82 : (CIDET_OF_K_IS_VRX(a_fOp1) && CIDET_OF_K_IS_VRX(a_fOp2)) )
83
84#define CIDET_OF_M_RM_ONLY_R UINT32_C(0x00010000)
85#define CIDET_OF_M_RM_ONLY_M UINT32_C(0x00020000)
86#define CIDET_OF_M_RM (CIDET_OF_M_RM_ONLY_R | CIDET_OF_M_RM_ONLY_M)
87#define CIDET_OF_M_REG UINT32_C(0x00040000)
88
89#define CIDET_OF_A_R UINT32_C(0x00080000) /**< Read access. */
90#define CIDET_OF_A_W UINT32_C(0x00100000) /**< Write access. */
91#define CIDET_OF_A_RW UINT32_C(0x00180000) /**< Read & write access. */
92
93/** The operand defaults to 64-bit width in 64-bit mode, making 32-bit width
94 * inaccessible. */
95#define CIDET_OF_DEFAULT_64BIT UINT32_C(0x40000000)
96/** Operand always uses the ES segment for memory accesses. */
97#define CIDET_OF_ALWAYS_SEG_ES UINT32_C(0x80000000)
98/** @} */
99
100
101/** @name CIDET - Instruction flags.
102 * @{ */
103#define CIDET_IF_MODRM RT_BIT_64(0) /**< ModR/M encoded. */
104#define CIDET_IF_PRIVILEGED RT_BIT_64(1) /**< Privileged. */
105/** @} */
106
107
108/**
109 * Callback function for setting up the input and expected output CPU contexts.
110 *
111 * @returns VBox status code.
112 * @retval VINF_EOF when static test data wraps (first entry is returned).
113 * @retval VERR_NO_DATA if @a fInvalid is set and there are no invalid operand
114 * values for this instruction.
115 * @retval VERR_NOT_SUPPORTED if something in the setup prevents us from
116 * comming up with working set of inputs and outputs.
117 *
118 * @param pThis The core CIDET state structure. The InCtx
119 * and ExpectedCtx members will be modified.
120 * @param fInvalid When set, get the next invalid operands that will
121 * cause exceptions/faults.
122 */
123typedef DECLCALLBACK(int) FNCIDETSETUPINOUT(struct CIDETCORE *pThis, bool fInvalid);
124/** Pointer to a FNCIDETSETUPINOUT function. */
125typedef FNCIDETSETUPINOUT *PFNCIDETSETUPINOUT;
126
127
128/**
129 * Instruction test descriptor.
130 */
131typedef struct CIDETINSTR
132{
133 /** The mnemonic (kind of). */
134 const char *pszMnemonic;
135 /** Setup input and outputs. */
136 PFNCIDETSETUPINOUT pfnSetupInOut;
137 /** Number of opcode bytes. */
138 uint8_t cbOpcode;
139 /** Opcode byte(s). */
140 uint8_t abOpcode[3];
141 /** Mandatory prefix (zero if not applicable). */
142 uint8_t bMandatoryPrefix;
143 /** Number of operands. */
144 uint8_t cOperands;
145 /** Operand flags. */
146 uint32_t afOperands[4];
147 /** Flags. */
148 uint64_t fFlags;
149} CIDETINSTR;
150/** Pointer to an instruction test descriptor. */
151typedef CIDETINSTR const *PCCIDETINSTR;
152
153
154/**
155 * CPU Context with a few extra bits for expectations and results.
156 */
157typedef struct CIDETCPUCTX
158{
159 uint64_t rip;
160 uint64_t rfl;
161 uint64_t aGRegs[16];
162 uint16_t aSRegs[6];
163
164#ifndef CIDET_REDUCED_CTX
165 uint16_t tr;
166 uint16_t ldtr;
167 uint64_t cr0;
168#else
169 uint16_t au16Padding[2];
170#endif
171 uint64_t cr2;
172#ifndef CIDET_REDUCED_CTX
173 uint64_t cr3;
174 uint64_t cr4;
175 uint64_t cr8;
176 uint64_t dr0;
177 uint64_t dr1;
178 uint64_t dr2;
179 uint64_t dr3;
180 uint64_t dr6;
181 uint64_t dr7;
182#endif
183
184 uint64_t uErr; /**< Exception error code. UINT64_MAX if not applicable. (Not for input context.) */
185 uint32_t uXcpt; /**< Exception number. UINT32_MAX if no exception. (Not for input context.) */
186
187 uint32_t fIgnoredRFlags; /**< Only for expected result. */
188 bool fTrickyStack; /**< Set if the stack might be bad. May come at the cost of accurate flags (32-bit). */
189} CIDETCPUCTX;
190typedef CIDETCPUCTX *PCIDETCPUCTX;
191typedef CIDETCPUCTX const *PCCIDETCPUCTX;
192
193/** Number of bytes of CIDETCPUCTX that can be compared quickly using memcmp.
194 * Anything following these bytes are not relevant to the compare. */
195#define CIDETCPUCTX_COMPARE_SIZE RT_UOFFSETOF(CIDETCPUCTX, fIgnoredRFlags)
196
197
198/** @name CPU mode + bits + environment.
199 * @{ */
200#define CIDETMODE_BIT_MASK UINT8_C(0x0e) /**< The instruction bit count. Results in byte size when masked. */
201#define CIDETMODE_BIT_16 UINT8_C(0x02) /**< 16-bit instructions. */
202#define CIDETMODE_BIT_32 UINT8_C(0x04) /**< 32-bit instructions. */
203#define CIDETMODE_BIT_64 UINT8_C(0x08) /**< 64-bit instructions. */
204#define CIDETMODE_MODE_MASK UINT8_C(0x70) /**< CPU mode mask. */
205#define CIDETMODE_MODE_RM UINT8_C(0x00) /**< Real mode. */
206#define CIDETMODE_MODE_PE UINT8_C(0x10) /**< Protected mode without paging. */
207#define CIDETMODE_MODE_PP UINT8_C(0x20) /**< Paged protected mode. */
208#define CIDETMODE_MODE_PAE UINT8_C(0x30) /**< PAE protected mode (paged). */
209#define CIDETMODE_MODE_LM UINT8_C(0x40) /**< Long mode (paged). */
210#define CIDETMODE_ENV_MASK UINT8_C(0x81) /**< Execution environment. */
211#define CIDETMODE_ENV_NORMAL UINT8_C(0x01) /**< Normal environment. */
212#define CIDETMODE_ENV_V86 UINT8_C(0x80) /**< V8086 environment. */
213#define CIDETMODE_RM (CIDETMODE_MODE_RM | CIDETMODE_BIT_16 | CIDETMODE_ENV_NORMAL)
214#define CIDETMODE_PE_16 (CIDETMODE_MODE_PE | CIDETMODE_BIT_16 | CIDETMODE_ENV_NORMAL)
215#define CIDETMODE_PE_32 (CIDETMODE_MODE_PE | CIDETMODE_BIT_32 | CIDETMODE_ENV_NORMAL)
216#define CIDETMODE_PE_V86 (CIDETMODE_MODE_PE | CIDETMODE_BIT_16 | CIDETMODE_ENV_V86)
217#define CIDETMODE_PP_16 (CIDETMODE_MODE_PP | CIDETMODE_BIT_16 | CIDETMODE_ENV_NORMAL)
218#define CIDETMODE_PP_32 (CIDETMODE_MODE_PP | CIDETMODE_BIT_32 | CIDETMODE_ENV_NORMAL)
219#define CIDETMODE_PP_V86 (CIDETMODE_MODE_PP | CIDETMODE_BIT_16 | CIDETMODE_ENV_V86)
220#define CIDETMODE_PAE_16 (CIDETMODE_MODE_PAE | CIDETMODE_BIT_16 | CIDETMODE_ENV_NORMAL)
221#define CIDETMODE_PAE_32 (CIDETMODE_MODE_PAE | CIDETMODE_BIT_32 | CIDETMODE_ENV_NORMAL)
222#define CIDETMODE_PAE_V86 (CIDETMODE_MODE_PAE | CIDETMODE_BIT_16 | CIDETMODE_ENV_V86)
223#define CIDETMODE_LM_16 (CIDETMODE_MODE_LM | CIDETMODE_BIT_16 | CIDETMODE_ENV_NORMAL)
224#define CIDETMODE_LM_32 (CIDETMODE_MODE_LM | CIDETMODE_BIT_32 | CIDETMODE_ENV_NORMAL)
225#define CIDETMODE_LM_64 (CIDETMODE_MODE_LM | CIDETMODE_BIT_64 | CIDETMODE_ENV_NORMAL)
226/** Test if @a a_bMode is a 16-bit mode. */
227#define CIDETMODE_IS_16BIT(a_bMode) ( ((a_bMode) & CIDETMODE_BIT_MASK) == CIDETMODE_BIT_16 )
228/** Test if @a a_bMode is a 32-bit mode. */
229#define CIDETMODE_IS_32BIT(a_bMode) ( ((a_bMode) & CIDETMODE_BIT_MASK) == CIDETMODE_BIT_32 )
230/** Test if @a a_bMode is a 64-bit mode. */
231#define CIDETMODE_IS_64BIT(a_bMode) ( ((a_bMode) & CIDETMODE_BIT_MASK) == CIDETMODE_BIT_64 )
232/** Get the instruction bit count. */
233#define CIDETMODE_GET_BIT_COUNT(a_bMode) ( CIDETMODE_GET_BYTE_COUNT(a_bMode) * 8 )
234/** Get the instruction byte count. */
235#define CIDETMODE_GET_BYTE_COUNT(a_bMode) ( (a_bMode) & CIDETMODE_BIT_MASK )
236/** Test if @a a_bMode long mode. */
237#define CIDETMODE_IS_LM(a_bMode) ( ((a_bMode) & CIDETMODE_MODE_MASK) == CIDETMODE_MODE_LM )
238/** Test if @a a_bMode some kind of protected mode. */
239#define CIDETMODE_IS_PROT(a_bMode) ( ((a_bMode) & CIDETMODE_MODE_MASK) >= CIDETMODE_MODE_PE )
240
241/** @} */
242
243
244/** @name Test Configuration Flags.
245 * @{ */
246#define CIDET_TESTCFG_SEG_PRF_CS UINT64_C(0x0000000000000001)
247#define CIDET_TESTCFG_SEG_PRF_SS UINT64_C(0x0000000000000002)
248#define CIDET_TESTCFG_SEG_PRF_DS UINT64_C(0x0000000000000004)
249#define CIDET_TESTCFG_SEG_PRF_ES UINT64_C(0x0000000000000008)
250#define CIDET_TESTCFG_SEG_PRF_FS UINT64_C(0x0000000000000010)
251#define CIDET_TESTCFG_SEG_PRF_GS UINT64_C(0x0000000000000020)
252#define CIDET_TESTCFG_SEG_PRF_MASK UINT64_C(0x000000000000003f)
253/** @} */
254
255/** */
256typedef enum CIDETREG
257{
258 kCidetReg_Gpr_Invalid = 0,
259
260 kCidetReg_Gpr_al,
261 kCidetReg_Gpr_cl,
262 kCidetReg_Gpr_dl,
263 kCidetReg_Gpr_bl,
264 kCidetReg_Gpr_spl,
265 kCidetReg_Gpr_bpl,
266 kCidetReg_Gpr_sil,
267 kCidetReg_Gpr_dil,
268 kCidetReg_Gpr_r8b,
269 kCidetReg_Gpr_r9b,
270 kCidetReg_Gpr_r10b,
271 kCidetReg_Gpr_r11b,
272 kCidetReg_Gpr_r12b,
273 kCidetReg_Gpr_r13b,
274 kCidetReg_Gpr_r14b,
275 kCidetReg_Gpr_r15b,
276 kCidetReg_Gpr_ah,
277 kCidetReg_Gpr_ch,
278 kCidetReg_Gpr_dh,
279 kCidetReg_Gpr_bh,
280#define kCidetReg_Gpr_Byte_First kCidetReg_Gpr_al
281#define kCidetReg_Gpr_Byte_First_Upper kCidetReg_Gpr_ah
282#define kCidetReg_Gpr_Byte_Last kCidetReg_Gpr_bh
283
284 kCidetReg_Gpr_ax,
285 kCidetReg_Gpr_cx,
286 kCidetReg_Gpr_dx,
287 kCidetReg_Gpr_bx,
288 kCidetReg_Gpr_sp,
289 kCidetReg_Gpr_bp,
290 kCidetReg_Gpr_si,
291 kCidetReg_Gpr_di,
292 kCidetReg_Gpr_r8w,
293 kCidetReg_Gpr_r9w,
294 kCidetReg_Gpr_r10w,
295 kCidetReg_Gpr_r11w,
296 kCidetReg_Gpr_r12w,
297 kCidetReg_Gpr_r13w,
298 kCidetReg_Gpr_r14w,
299 kCidetReg_Gpr_r15w,
300#define kCidetReg_Gpr_Word_First kCidetReg_Gpr_ax
301#define kCidetReg_Gpr_Word_Last kCidetReg_Gpr_r15w
302
303 kCidetReg_Gpr_eax,
304 kCidetReg_Gpr_ecx,
305 kCidetReg_Gpr_edx,
306 kCidetReg_Gpr_ebx,
307 kCidetReg_Gpr_esp,
308 kCidetReg_Gpr_ebp,
309 kCidetReg_Gpr_esi,
310 kCidetReg_Gpr_edi,
311 kCidetReg_Gpr_r8d,
312 kCidetReg_Gpr_r9d,
313 kCidetReg_Gpr_r10d,
314 kCidetReg_Gpr_r11d,
315 kCidetReg_Gpr_r12d,
316 kCidetReg_Gpr_r13d,
317 kCidetReg_Gpr_r14d,
318 kCidetReg_Gpr_r15d,
319#define kCidetReg_Gpr_DWord_First kCidetReg_Gpr_eax
320#define kCidetReg_Gpr_DWord_Last kCidetReg_Gpr_r15d
321
322 kCidetReg_Gpr_rax,
323 kCidetReg_Gpr_rcx,
324 kCidetReg_Gpr_rdx,
325 kCidetReg_Gpr_rbx,
326 kCidetReg_Gpr_rsp,
327 kCidetReg_Gpr_rbp,
328 kCidetReg_Gpr_rsi,
329 kCidetReg_Gpr_rdi,
330 kCidetReg_Gpr_r8,
331 kCidetReg_Gpr_r9,
332 kCidetReg_Gpr_r10,
333 kCidetReg_Gpr_r11,
334 kCidetReg_Gpr_r12,
335 kCidetReg_Gpr_r13,
336 kCidetReg_Gpr_r14,
337 kCidetReg_Gpr_r15,
338#define kCidetReg_Gpr_QWord_First kCidetReg_Gpr_rax
339#define kCidetReg_Gpr_QWord_Last kCidetReg_Gpr_r15
340
341 kCidetReg_Seg_es,
342 kCidetReg_Seg_cs,
343 kCidetReg_Seg_ss,
344 kCidetReg_Seg_ds,
345 kCidetReg_Seg_fs,
346 kCidetReg_Seg_gs,
347 kCidetReg_Seg_Inv6,
348 kCidetReg_Seg_Inv7,
349#define kCidetReg_Seg_First kCidetReg_Seg_es
350#define kCidetReg_Seg_Last kCidetReg_Seg_gs
351#define kCidetReg_Seg_Last_Inv kCidetReg_Seg_Inv7
352
353 kCidetReg_Misc_ip,
354 kCidetReg_Misc_eip,
355 kCidetReg_Misc_rip,
356 kCidetReg_Misc_flags,
357 kCidetReg_Misc_eflags,
358 kCidetReg_Misc_rflags,
359 kCidetReg_Misc_tr,
360 kCidetReg_Misc_ldtr,
361 kCidetReg_Misc_gdtr,
362 kCidetReg_Misc_idtr,
363
364 kCidetReg_Ctrl_cr0,
365 kCidetReg_Ctrl_cr1,
366 kCidetReg_Ctrl_cr2,
367 kCidetReg_Ctrl_cr3,
368 kCidetReg_Ctrl_cr4,
369 kCidetReg_Ctrl_cr5,
370 kCidetReg_Ctrl_cr6,
371 kCidetReg_Ctrl_cr7,
372 kCidetReg_Ctrl_cr8,
373 kCidetReg_Ctrl_cr9,
374 kCidetReg_Ctrl_cr10,
375 kCidetReg_Ctrl_cr11,
376 kCidetReg_Ctrl_cr12,
377 kCidetReg_Ctrl_cr13,
378 kCidetReg_Ctrl_cr14,
379 kCidetReg_Ctrl_cr15,
380#define kCidetReg_Ctrl_First kCidetReg_Ctrl_cr0
381#define kCidetReg_Ctrl_Last kCidetReg_Ctrl_cr15
382#define CIDETREG_CTRL_IS_VALID(a_iReg) ( (a_iReg) == kCidetReg_Ctrl_cr0 \
383 && (a_iReg) == kCidetReg_Ctrl_cr2 \
384 && (a_iReg) == kCidetReg_Ctrl_cr3 \
385 && (a_iReg) == kCidetReg_Ctrl_cr4 \
386 && (a_iReg) == kCidetReg_Ctrl_cr8 )
387
388 kCidetReg_Dbg_dr0,
389 kCidetReg_Dbg_dr1,
390 kCidetReg_Dbg_dr2,
391 kCidetReg_Dbg_dr3,
392 kCidetReg_Dbg_dr4,
393 kCidetReg_Dbg_dr5,
394 kCidetReg_Dbg_dr6,
395 kCidetReg_Dbg_dr7,
396 kCidetReg_Dbg_dr8,
397 kCidetReg_Dbg_dr9,
398 kCidetReg_Dbg_dr10,
399 kCidetReg_Dbg_dr11,
400 kCidetReg_Dbg_dr12,
401 kCidetReg_Dbg_dr13,
402 kCidetReg_Dbg_dr14,
403 kCidetReg_Dbg_dr15,
404#define kCidetReg_Dbg_First kCidetReg_Dbg_dr0
405#define kCidetReg_Dbg_Last kCidetReg_Dbg_dr15
406#define CIDETREG_DBG_IS_VALID(a_iReg) ((a_iReg) < kCidetReg_Dbg_dr8 && (a_iReg) >= kCidetReg_Dbg_First)
407
408 kCidetReg_Test_tr0,
409 kCidetReg_Test_tr1,
410 kCidetReg_Test_tr2,
411 kCidetReg_Test_tr3,
412 kCidetReg_Test_tr4,
413 kCidetReg_Test_tr5,
414 kCidetReg_Test_tr6,
415 kCidetReg_Test_tr7,
416 kCidetReg_Test_tr8,
417 kCidetReg_Test_tr9,
418 kCidetReg_Test_tr10,
419 kCidetReg_Test_tr11,
420 kCidetReg_Test_tr12,
421 kCidetReg_Test_tr13,
422 kCidetReg_Test_tr14,
423 kCidetReg_Test_tr15,
424#define kCidetReg_Test_First kCidetReg_Test_tr0
425#define kCidetReg_Test_Last kCidetReg_Test_tr15
426
427 kCidetReg_Fpu_st0,
428 kCidetReg_Fpu_st1,
429 kCidetReg_Fpu_st2,
430 kCidetReg_Fpu_st3,
431 kCidetReg_Fpu_st4,
432 kCidetReg_Fpu_st5,
433 kCidetReg_Fpu_st6,
434 kCidetReg_Fpu_st7,
435#define kCidetReg_Fpu_First kCidetReg_Mmx_st0
436#define kCidetReg_Fpu_Last kCidetReg_Mmx_st7
437
438 kCidetReg_FpuMisc_cs,
439 kCidetReg_FpuMisc_ip,
440 kCidetReg_FpuMisc_ds,
441 kCidetReg_FpuMisc_dp,
442 kCidetReg_FpuMisc_fop,
443 kCidetReg_FpuMisc_ftw,
444 kCidetReg_FpuMisc_fsw,
445 kCidetReg_FpuMisc_fcw,
446 kCidetReg_FpuMisc_mxcsr_mask,
447 kCidetReg_FpuMisc_mxcsr,
448
449 kCidetReg_Mmx_mm0,
450 kCidetReg_Mmx_mm1,
451 kCidetReg_Mmx_mm2,
452 kCidetReg_Mmx_mm3,
453 kCidetReg_Mmx_mm4,
454 kCidetReg_Mmx_mm5,
455 kCidetReg_Mmx_mm6,
456 kCidetReg_Mmx_mm7,
457#define kCidetReg_Mmx_First kCidetReg_Mmx_mm0
458#define kCidetReg_Mmx_Last kCidetReg_Mmx_mm7
459
460 kCidetReg_Sse_xmm0,
461 kCidetReg_Sse_xmm1,
462 kCidetReg_Sse_xmm2,
463 kCidetReg_Sse_xmm3,
464 kCidetReg_Sse_xmm4,
465 kCidetReg_Sse_xmm5,
466 kCidetReg_Sse_xmm6,
467 kCidetReg_Sse_xmm7,
468 kCidetReg_Sse_xmm8,
469 kCidetReg_Sse_xmm9,
470 kCidetReg_Sse_xmm10,
471 kCidetReg_Sse_xmm11,
472 kCidetReg_Sse_xmm12,
473 kCidetReg_Sse_xmm13,
474 kCidetReg_Sse_xmm14,
475 kCidetReg_Sse_xmm15,
476 kCidetReg_Sse_xmm16,
477 kCidetReg_Sse_xmm17,
478 kCidetReg_Sse_xmm18,
479 kCidetReg_Sse_xmm19,
480 kCidetReg_Sse_xmm20,
481 kCidetReg_Sse_xmm21,
482 kCidetReg_Sse_xmm22,
483 kCidetReg_Sse_xmm23,
484 kCidetReg_Sse_xmm24,
485 kCidetReg_Sse_xmm25,
486 kCidetReg_Sse_xmm26,
487 kCidetReg_Sse_xmm27,
488 kCidetReg_Sse_xmm28,
489 kCidetReg_Sse_xmm29,
490 kCidetReg_Sse_xmm30,
491 kCidetReg_Sse_xmm31,
492#define kCidetReg_Sse_First kCidetReg_Mmx_Xmm0
493#define kCidetReg_Sse_Last kCidetReg_Mmx_Xmm15
494#define kCidetReg_Sse_Last_Avx512 kCidetReg_Mmx_Xmm31
495
496 kCidetReg_Avx_Ymm0,
497 kCidetReg_Avx_Ymm1,
498 kCidetReg_Avx_Ymm2,
499 kCidetReg_Avx_Ymm3,
500 kCidetReg_Avx_Ymm4,
501 kCidetReg_Avx_Ymm5,
502 kCidetReg_Avx_Ymm6,
503 kCidetReg_Avx_Ymm7,
504 kCidetReg_Avx_Ymm8,
505 kCidetReg_Avx_Ymm9,
506 kCidetReg_Avx_Ymm10,
507 kCidetReg_Avx_Ymm11,
508 kCidetReg_Avx_Ymm12,
509 kCidetReg_Avx_Ymm13,
510 kCidetReg_Avx_Ymm14,
511 kCidetReg_Avx_Ymm15,
512 kCidetReg_Avx_Ymm16,
513 kCidetReg_Avx_Ymm17,
514 kCidetReg_Avx_Ymm18,
515 kCidetReg_Avx_Ymm19,
516 kCidetReg_Avx_Ymm20,
517 kCidetReg_Avx_Ymm21,
518 kCidetReg_Avx_Ymm22,
519 kCidetReg_Avx_Ymm23,
520 kCidetReg_Avx_Ymm24,
521 kCidetReg_Avx_Ymm25,
522 kCidetReg_Avx_Ymm26,
523 kCidetReg_Avx_Ymm27,
524 kCidetReg_Avx_Ymm28,
525 kCidetReg_Avx_Ymm29,
526 kCidetReg_Avx_Ymm30,
527 kCidetReg_Avx_Ymm31,
528#define kCidetReg_Avx_First kCidetReg_Avx_Ymm0
529#define kCidetReg_Avx_Last kCidetReg_Avx_Ymm15
530#define kCidetReg_Avx_Last_Avx512 kCidetReg_Avx_Ymm31
531
532 kCidetReg_Avx512_Zmm0,
533 kCidetReg_Avx512_Zmm1,
534 kCidetReg_Avx512_Zmm2,
535 kCidetReg_Avx512_Zmm3,
536 kCidetReg_Avx512_Zmm4,
537 kCidetReg_Avx512_Zmm5,
538 kCidetReg_Avx512_Zmm6,
539 kCidetReg_Avx512_Zmm7,
540 kCidetReg_Avx512_Zmm8,
541 kCidetReg_Avx512_Zmm9,
542 kCidetReg_Avx512_Zmm10,
543 kCidetReg_Avx512_Zmm11,
544 kCidetReg_Avx512_Zmm12,
545 kCidetReg_Avx512_Zmm13,
546 kCidetReg_Avx512_Zmm14,
547 kCidetReg_Avx512_Zmm15,
548 kCidetReg_Avx512_Zmm16,
549 kCidetReg_Avx512_Zmm17,
550 kCidetReg_Avx512_Zmm18,
551 kCidetReg_Avx512_Zmm19,
552 kCidetReg_Avx512_Zmm20,
553 kCidetReg_Avx512_Zmm21,
554 kCidetReg_Avx512_Zmm22,
555 kCidetReg_Avx512_Zmm23,
556 kCidetReg_Avx512_Zmm24,
557 kCidetReg_Avx512_Zmm25,
558 kCidetReg_Avx512_Zmm26,
559 kCidetReg_Avx512_Zmm27,
560 kCidetReg_Avx512_Zmm28,
561 kCidetReg_Avx512_Zmm29,
562 kCidetReg_Avx512_Zmm30,
563 kCidetReg_Avx512_Zmm31,
564#define kCidetReg_Avx512_First kCidetReg_Avx512_Zmm0
565#define kCidetReg_Avx512_Last kCidetReg_Avx512_Zmm31
566
567 kCidetReg_End
568} CIDETREG;
569
570
571/** @name CIDETBUF_XXX - buffer flags.
572 * @{ */
573#define CIDETBUF_PROT_MASK UINT32_C(0x0000000f) /**< Page protection mask. */
574#define CIDETBUF_PROT_RWX UINT32_C(0x00000001) /**< Read + write + execute. */
575#define CIDETBUF_PROT_RWNX UINT32_C(0x00000002) /**< Read + write + no execute. */
576#define CIDETBUF_PROT_RX UINT32_C(0x00000003) /**< Read + execute. */
577#define CIDETBUF_PROT_RNX UINT32_C(0x00000004) /**< Read + no execute. */
578#define CIDETBUF_PROT_RWX_1NP UINT32_C(0x00000005) /**< Read + write + execute; 1 page not present. */
579#define CIDETBUF_PROT_RWX_1RWNX UINT32_C(0x00000006) /**< Read + write + execute; 1 page read + write + no execute. */
580#define CIDETBUF_PROT_RWX_1RNX UINT32_C(0x00000007) /**< Read + write + execute; 1 page read + no execute. */
581#define CIDETBUF_PROT_RWX_1RWXS UINT32_C(0x00000008) /**< Read + write + execute; 1 page read + execute + supervisor. */
582
583#define CIDETBUF_LOC_MASK UINT32_C(0x000000f0) /**< Location mask. */
584/** Buffer located at top and start of the 32-bit address space. */
585#define CIDETBUF_LOC_32BIT_WRAP UINT32_C(0x00000010)
586/** Buffer located at the low canonical boundrary (AMD64). */
587#define CIDETBUF_LOC_CANON_LO UINT32_C(0x00000020)
588/** Buffer located at the high canonical boundrary (AMD64). */
589#define CIDETBUF_LOC_CANON_HI UINT32_C(0x00000030)
590
591/** Segment protection mask. */
592#define CIDETBUF_SEG_MASK UINT32_C(0x00000f00)
593#define CIDETBUF_SEG_EO UINT32_C(0x00000100) /**< Execute only */
594#define CIDETBUF_SEG_ER UINT32_C(0x00000200) /**< Execute + read */
595#define CIDETBUF_SEG_EO_CONF UINT32_C(0x00000300) /**< Execute only + conforming. */
596#define CIDETBUF_SEG_ER_CONF UINT32_C(0x00000400) /**< Execute + read + conforming. */
597#define CIDETBUF_SEG_RO UINT32_C(0x00000500) /**< Read only. */
598#define CIDETBUF_SEG_RW UINT32_C(0x00000600) /**< Read + write. */
599#define CIDETBUF_SEG_RO_DOWN UINT32_C(0x00000700) /**< Read only + expand down. */
600#define CIDETBUF_SEG_RW_DOWN UINT32_C(0x00000800) /**< Read + write + expand down. */
601
602#define CIDETBUF_DPL_MASK UINT32_C(0x00003000) /**< DPL mask. */
603#define CIDETBUF_DPL_0 UINT32_C(0x00000000) /**< DPL=0. */
604#define CIDETBUF_DPL_1 UINT32_C(0x00001000) /**< DPL=1. */
605#define CIDETBUF_DPL_2 UINT32_C(0x00002000) /**< DPL=2. */
606#define CIDETBUF_DPL_3 UINT32_C(0x00003000) /**< DPL=3. */
607#define CIDETBUF_DPL_SAME UINT32_C(0x00004000) /**< Same DPL as the execution environment. */
608
609#define CIDETBUF_SEG_LIMIT_BASE_CAP UINT32_C(0x00008000) /**< Capability to change segment limit and base. */
610
611#define CIDETBUF_KIND_DATA UINT32_C(0x00000000) /**< Data buffer. */
612#define CIDETBUF_KIND_CODE UINT32_C(0x80000000) /**< Code buffer. */
613/** Checks if @a a_fFlags describes a code buffer. */
614#define CIDETBUF_IS_CODE(a_fFlags) (((a_fFlags) & CIDETBUF_KIND_CODE) != 0)
615/** Checks if @a a_fFlags describes a data buffer. */
616#define CIDETBUF_IS_DATA(a_fFlags) (((a_fFlags) & CIDETBUF_KIND_CODE) == 0)
617/** @} */
618
619/** Code buffer size. (At least two pages.) */
620#define CIDET_CODE_BUF_SIZE (PAGE_SIZE * 2)
621/** Data buffer size. (At least two pages.) */
622#define CIDET_DATA_BUF_SIZE (PAGE_SIZE * 3)
623
624
625/**
626 * Detailed expected exception.
627 *
628 * This is used to internally in the core to calculate the expected exception
629 * considering all the things that may cause exceptions.
630 */
631typedef enum CIDETEXPECTXCPT
632{
633 kCidetExpectXcpt_Invalid = 0,
634 /** No exception expected. */
635 kCidetExpectXcpt_None,
636
637 /** Page not present. */
638 kCidetExpectXcpt_PageNotPresent,
639 /** Write access to a non-writable page. */
640 kCidetExpectXcpt_PageNotWritable,
641 /** Executable access to a non-executable page. */
642 kCidetExpectXcpt_PageNotExecutable,
643 /** Access to supervisor page from user mode code. */
644 kCidetExpectXcpt_PagePrivileged,
645#define kCidetExpectXcpt_First_PageFault kCidetExpectXcpt_PageNotPresent
646#define kCidetExpectXcpt_Last_PageFault kCidetExpectXcpt_PagePrivileged
647
648 /** Read or write access to an execute only segment. */
649 kCidetExpectXcpt_SegExecuteOnly,
650 /** Write to a read only or execute+read segment. */
651 kCidetExpectXcpt_SegNotWritable,
652 /** Exceeded the limit of a non-stack access. */
653 kCidetExpectXcpt_SegExceededLimit,
654 /** Non-canonical address via any segment other than the stack. */
655 kCidetExpectXcpt_AddrNotCanonical,
656 /** Misaligned 16 or 32 byte SSE or AVX operand. */
657 kCidetExpectXcpt_MisalignedSseAvx,
658 /** Privileged instruction. */
659 kCidetExpectXcpt_PrivilegedInstruction,
660#define kCidetExpectXcpt_First_GeneralProtectionFault kCidetExpectXcpt_SegExecuteOnly
661#define kCidetExpectXcpt_Last_GeneralProtectionFault kCidetExpectXcpt_PrivilegedInstruction
662
663 /** Exceeded the limit of a stack access. */
664 kCidetExpectXcpt_StackExceededLimit,
665 /** Non-canonical stack address. */
666 kCidetExpectXcpt_StackAddrNotCanonical,
667#define kCidetExpectXcpt_First_StackFault kCidetExpectXcpt_StackExceededLimit
668#define kCidetExpectXcpt_Last_StackFault kCidetExpectXcpt_StackAddrNotCanonical
669
670 /** Misaligned memory operand (and alignment checking is in effect) if AC is
671 * enabled (executing in ring-3). */
672 kCidetExpectXcpt_MisalignedIfAcEnabled,
673 /** Misaligned 16 byte memory operand resulting in \#AC if ring-3 and
674 * enable, otherwise \#GP(0). */
675 kCidetExpectXcpt_Misaligned16ByteAcEnabledOrGp,
676#define kCidetExpectXcpt_First_AlignmentCheckFault kCidetExpectXcpt_MisalignedIfAcEnabled
677#define kCidetExpectXcpt_Last_AlignmentCheckFault kCidetExpectXcpt_Misaligned16ByteAcEnabledOrGp
678
679 kCidetExpectXcpt_End
680} CIDETEXPECTXCPT;
681
682
683/**
684 * Buffer configuration.
685 */
686typedef struct CIDETBUFCFG
687{
688 /** The name of this buffer configuration. */
689 const char *pszName;
690 /** The buffer flags (CIDETBUF_XXX) */
691 uint32_t fFlags;
692} CIDETBUFCFG;
693/** Pointer to a constant buffer configuration. */
694typedef CIDETBUFCFG const *PCCIDETBUFCFG;
695
696
697/**
698 * CIDET buffer for code or data.
699 *
700 * ASSUMES page aligned buffers.
701 */
702typedef struct CIDETBUF
703{
704 /** @name Owned & modified by the front end.
705 * @{ */
706 /** Effective buffer address. */
707 uint64_t uEffBufAddr;
708 /** The segment base address. */
709 uint64_t uSegBase;
710 /** The active segment limit (see also cbSegLimit). UINT64_MAX if flat. */
711 uint64_t cbActiveSegLimit;
712 /** This specifies the selector to use if a non-flat segment limit or special
713 * segment flags was requested via pfnSetupBuf. UINT32_MAX if any segment is
714 * selector works. */
715 uint32_t uSeg;
716 /** The off value at the last pfnReinitBuf call. */
717 uint16_t offActive;
718 /** The cb value at the last pfnReinitBuf call. */
719 uint16_t cbActive;
720 /** Prologue (or front fence) size. */
721 uint16_t cbPrologue;
722 /** Epilogue (or tail fence) size. */
723 uint16_t cbEpilogue;
724 /** @} */
725
726 /** @name Set by the core before pfnReinitBuf call.
727 * @{ */
728 /** Pointer to the buffer config. */
729 PCCIDETBUFCFG pCfg;
730 /** The configuration index. */
731 uint32_t idxCfg;
732 /** The offset into the buffer of the data / code. */
733 uint16_t off;
734 /** The number of bytes of data / code. */
735 uint16_t cb;
736 /** The segment limit relative to the start of the buffer (last byte included
737 * in count). UINT16_MAX if maximum segment size should be used. */
738 uint16_t cbSegLimit;
739 /** Desired segment base offset.
740 * This is for checking where the alignment checks are performed. */
741 uint8_t offSegBase;
742
743 /** Set if this buffer is actively being used. */
744 bool fActive : 1;
745 /** The operand index (if data), 7 if not active. */
746 uint8_t idxOp : 3;
747 /** Code: Set if the expected exception is supposed to occur on the
748 * following insturction, not the instruction unter test. */
749 bool fXcptAfterInstruction : 1;
750 /** Set if the instruction will read from the buffer. */
751 bool fRead : 1;
752 /** Set if the instruction will write to the buffer. */
753 bool fWrite : 1;
754 /** The expected exception. */
755 CIDETEXPECTXCPT enmExpectXcpt;
756 /** @} */
757} CIDETBUF;
758/** Pointer to a CIDET buffer for code or data. */
759typedef CIDETBUF *PCIDETBUF;
760
761
762/**
763 * CPU Instruction Decoding & Execution Testing (CIDET) state.
764 */
765typedef struct CIDETCORE
766{
767 /** Magic number (CIDETCORE_MAGIC). */
768 uint32_t u32Magic;
769
770 /** The target CPU mode / environment. */
771 uint8_t bMode;
772 /** The target ring. */
773 uint8_t iRing;
774 /** Unused padding bytes. */
775 uint8_t abPadding1[2];
776
777 /** Test configuration. */
778 uint64_t fTestCfg;
779
780 /** Code buffer configurations to test.
781 * The first buffer must be a normal buffer that does not cause any problems. */
782 PCCIDETBUFCFG paCodeBufConfigs;
783 /** The number of code buffer configurations to test (pafCodeBufConfigs). */
784 uint32_t cCodeBufConfigs;
785 /** The number of data buffer configurations to test (pafDataBufConfigs). */
786 uint32_t cDataBufConfigs;
787 /** Data buffer configurations to test.
788 * The first buffer must be a normal buffer that does not cause any problems. */
789 PCCIDETBUFCFG paDataBufConfigs;
790
791 /** The instruction currently under testing. */
792 PCCIDETINSTR pCurInstr;
793
794 /** Primary data buffer. */
795 CIDETBUF DataBuf;
796 /** Secondary data buffer. */
797 CIDETBUF DataBuf2;
798
799 /** Handle to the random number source. */
800 RTRAND hRand;
801
802 /**
803 * Re-initializes one of the data buffers.
804 *
805 * @returns true on succes, false if the request cannot be satisfied.
806 * @param pThis The core state.
807 * @param pBuf Pointer to the buffer structure.
808 */
809 DECLCALLBACKMEMBER(bool, pfnReInitDataBuf)(struct CIDETCORE *pThis, PCIDETBUF pBuf);
810
811 /**
812 * Copies bytes into the data buffer and sets it up for execution.
813 *
814 * @returns true on succes, false if the request cannot be satisfied.
815 * @param pThis The core state.
816 * @param pBuf Pointer to the buffer structure.
817 * @param pvSrc The source bytes (size and destination offset
818 * given in pfnReinitBuf call).
819 */
820 DECLCALLBACKMEMBER(bool, pfnSetupDataBuf)(struct CIDETCORE *pThis, PCIDETBUF pBuf, void const *pvSrc);
821
822 /**
823 * Compares buffer content after test execution.
824 *
825 * This also checks any fill bytes in the buffer that the front end may
826 * have put up. The front end will double buffer the content of supposedly
827 * inaccessible pages as well as non-existing pages to simplify things for
828 * the core code.
829 *
830 * @returns true if equal, false if not.
831 * @param pThis The core state.
832 * @param pBuf Pointer to the buffer structure.
833 * @param pvExpected Pointer to the expected source bytes (size and
834 * buffer offset given in pfnReinitBuf call).
835 */
836 DECLCALLBACKMEMBER(bool, pfnIsBufEqual)(struct CIDETCORE *pThis, struct CIDETBUF *pBuf, void const *pvExpected);
837
838 /**
839 * Re-initializes the code buffer.
840 *
841 * @returns true on succes, false if the request cannot be satisfied.
842 * @param pThis The core state.
843 * @param pBuf Pointer to the CodeBuf member. The off and cb
844 * members represent what the core wants to
845 * execute.
846 */
847 DECLCALLBACKMEMBER(bool, pfnReInitCodeBuf)(struct CIDETCORE *pThis, PCIDETBUF pBuf);
848
849 /**
850 * Emit code into the code buffer, making everything ready for pfnExecute.
851 *
852 * @returns VBox status code.
853 * @param pThis Pointer to the core structure.
854 * @param pBuf Pointer to the CodeBuf member.
855 * @param pvInstr Pointer to the encoded instruction bytes.
856 */
857 DECLCALLBACKMEMBER(bool, pfnSetupCodeBuf)(struct CIDETCORE *pThis, PCIDETBUF pBuf, void const *pvInstr);
858
859 /**
860 * Executes the code indicated by InCtx, returning the result in ActualCtx.
861 *
862 * @returns true if execute, false if skipped.
863 * @param pThis Pointer to the core structure.
864 */
865 DECLCALLBACKMEMBER(bool, pfnExecute)(struct CIDETCORE *pThis);
866
867 /**
868 * Report a test failure.
869 *
870 * @param pThis Pointer to the core structure.
871 * @param pszFormat Format string containing failure details.
872 * @param va Arguments referenced in @a pszFormat.
873 */
874 DECLCALLBACKMEMBER(void, pfnFailure)(struct CIDETCORE *pThis, const char *pszFormat, va_list va);
875
876 /** Array of indexes for use by FNCIDETSETUPINOUT.
877 * Reset when changing instruction or switching between valid and invalid
878 * inputs. */
879 uint32_t aiInOut[4];
880
881 /** @name Copyied and extracted instruction information.
882 * @{ */
883 /** The flags (CIDET_OF_XXX) for the MODRM.REG operand, 0 if not applicable. */
884 uint32_t fMrmRegOp;
885 /** The flags (CIDET_OF_XXX) for the MODRM.RM operand, 0 if not applicable. */
886 uint32_t fMrmRmOp;
887 /** Instruction flags (CIDETINSTR::fFlags). */
888 uint64_t fInstrFlags;
889 /** Number of operands (CIDETINSTR::cOperands). */
890 uint8_t cOperands;
891 /** Number of memory operands (set by CidetCoreSetupFirstMemoryOperandConfig). */
892 uint8_t cMemoryOperands : 3;
893 /** Set if we're working on a MOD R/M byte. */
894 bool fUsesModRm : 1;
895 /** The index of the MODRM.REG operand, 7 if not applicable. */
896 uint8_t idxMrmRegOp : 3;
897 /** The index of the MODRM.RM operand, 7 if not applicable. */
898 uint8_t idxMrmRmOp : 3;
899 /** Set if the SIB byte uses VEX registers for indexing. */
900 bool fUsesVexIndexRegs : 1;
901 /** @} */
902
903 /** @name Basic encoding knobs, wheels and indicators.
904 * @{ */
905 /** Set if we're working on a SIB byte. */
906 bool fSib : 1;
907 /** Required segment prefix (X86_SREG_XXX), X86_SREG_COUNT if not. */
908 uint8_t uSegPrf : 3;
909 /** The address size prefix. */
910 bool fAddrSizePrf : 1;
911 /** The operand size prefix. */
912 bool fOpSizePrf : 1;
913 /** The REX.W prefix value. */
914 bool fRexW : 1;
915 /** The REX.R prefix value. */
916 bool fRexR : 1;
917 /** The REX.X prefix value. */
918 bool fRexX : 1;
919 /** The REX.B prefix value. */
920 bool fRexB : 1;
921 /** Set if a REX prefix is required with or without flags (for byte regs). */
922 bool fRex : 1;
923 /** Use VEX encoding. */
924 bool fVex : 1;
925 /** Use EVEX encoding. */
926 bool fEvex : 1;
927 /** Indicator: Effective addressing mode in bytes (2, 4, 8). */
928 uint8_t cbAddrMode : 4;
929 /** Indicator: Set if there is an operand accessing memory. */
930 bool fHasMemoryOperand : 1;
931 /** Indicator: Set if a register is used in two or more operands, and one of
932 * them being for addressing. */
933 bool fHasRegCollisionMem : 1;
934 /** Indicator: Helper indicator for tracking SIB.BASE collision. */
935 bool fHasRegCollisionMemBase : 1;
936 /** Indicator: Helper indicator for tracking SIB.INDEX collision. */
937 bool fHasRegCollisionMemIndex : 1;
938 /** Indicator: Set if a register is used directly in more than one operand. */
939 bool fHasRegCollisionDirect : 1;
940
941 /** Indicator: Set if MODRM.REG is the stack register. */
942 bool fHasStackRegInMrmReg : 1;
943 /** Indicator: Set if MODRM.RM or SIB.BASE is the stack register. */
944 bool fHasStackRegInMrmRmBase: 1;
945
946 /** Indicator: High byte-register specified by MODRM.REG. */
947 bool fHasHighByteRegInMrmReg : 1;
948 /** Indicator: High byte-register specified by MODRM.RM. */
949 bool fHasHighByteRegInMrmRm : 1;
950 /** Indicator: Set if REX prefixes are incompatible with the byte-register
951 * specified by MODRM.REG. */
952 bool fNoRexPrefixMrmReg : 1;
953 /** Indicator: Set if REX prefixes are incompatible with the byte-register
954 * specified by MODRM.RM. */
955 bool fNoRexPrefixMrmRm : 1;
956 /** Indicator: fNoRexPrefixMrmReg || fNoRexPrefixMrmMr. */
957 bool fNoRexPrefix : 1;
958 /** The MOD R/M byte we're working on (if fUsesModRm is set). */
959 uint8_t bModRm;
960 /** The SIB/VSIB byte we're working on (if fSib is set). */
961 uint8_t bSib;
962 /** @} */
963
964 /** The effective instruction address. (See InCtx.rip and InCtx.cs for the
965 * rest of the instruction addressing stuff.) */
966 uint64_t uInstrEffAddr;
967
968 /** Operand information, mainly for the FNCIDETSETUPINOUT and similar. */
969 struct
970 {
971 /** The operand flags copied from (CIDETINSTR::afOperands). */
972 uint32_t fFlags;
973 /** The encoded register number, if register, UINT8_MAX if not. */
974 uint8_t iReg;
975 /** The actual operand size (encoded). */
976 uint8_t cb;
977 /** Set if immediate value. */
978 bool fIsImmediate : 1;
979 /** Set if memory access. */
980 bool fIsMem : 1;
981 /** Set if addressing is relative to RIP. */
982 bool fIsRipRelative : 1;
983 /** Set if it's a high byte register. */
984 bool fIsHighByteRegister : 1;
985 /** Size of the disposition, 0 if none. */
986 uint8_t cbMemDisp;
987 /** Base register, UINT8_MAX if not applicable. */
988 uint8_t iMemBaseReg;
989 /** Index register, UINT8_MAX if not applicable. */
990 uint8_t iMemIndexReg;
991 /** Index register, 1 if not applicable. */
992 uint8_t uMemScale;
993 /** Effective segment register, UINT8_MAX if not memory access. */
994 uint8_t iEffSeg;
995 /** Segment offset if memory access. Undefined if not memory access. */
996 uint64_t offSeg;
997 /** The effective address if memory access. */
998 uint64_t uEffAddr;
999 /** Immediate or displacement value. */
1000 uint64_t uImmDispValue;
1001 /** Base register value, undefined if irrelevant. */
1002 uint64_t uMemBaseRegValue;
1003 /** Index register value, undefined if irrelevant. */
1004 uint64_t uMemIndexRegValue;
1005 /** Points to where the input data for this operand should be placed,
1006 * when possible. In the fIsMem = true case, it either points directly
1007 * to the input buffer or to a temporary one. While in the other case,
1008 * it'll point into InCtx when possible. */
1009 RTPTRUNION In;
1010 /** Points to where the expected output data for this operand should be
1011 * stored, when possible. In the fIsMem = false case, it'll point into
1012 * ExpectedCtx when possible. */
1013 RTPTRUNION Expected;
1014 /** Pointer to the data buffer for this operand. */
1015 PCIDETBUF pDataBuf;
1016 } aOperands[4];
1017
1018 /** Buffer where we assemble the instruction. */
1019 uint8_t abInstr[45];
1020 /** The size of the instruction in abInstr. */
1021 uint8_t cbInstr;
1022 /** Offset of the instruction into the buffer. */
1023 uint16_t offInstr;
1024 /** Current code buffer. */
1025 CIDETBUF CodeBuf;
1026
1027 /** The input context. Initalized by driver and FNCIDETSETUPINOUT. */
1028 CIDETCPUCTX InCtx;
1029 /** The expected output context. */
1030 CIDETCPUCTX ExpectedCtx;
1031 /** The actual output context. */
1032 CIDETCPUCTX ActualCtx;
1033 /** Template input context, initialized when setting the mode. */
1034 CIDETCPUCTX InTemplateCtx;
1035
1036 /** Input and expected output temporary memory buffers. */
1037 uint8_t abBuf[0x2000];
1038
1039
1040 /** Number of skipped tests because of pfnSetupInOut failures. */
1041 uint32_t cSkippedSetupInOut;
1042 /** Number of skipped tests because of pfnReInitDataBuf failures. */
1043 uint32_t cSkippedReInitDataBuf;
1044 /** Number of skipped tests because of pfnSetupDataBuf failures. */
1045 uint32_t cSkippedSetupDataBuf;
1046 /** Number of skipped tests because RIP relative addressing constraints. */
1047 uint32_t cSkippedDataBufWrtRip;
1048 /** Number of skipped tests because of assemble failures. */
1049 uint32_t cSkippedAssemble;
1050 /** Number of skipped tests because of pfnReInitCodeBuf failures. */
1051 uint32_t cSkippedReInitCodeBuf;
1052 /** Number of skipped tests because of pfnSetupCodeBuf failures. */
1053 uint32_t cSkippedSetupCodeBuf;
1054 /** Number of skipped tests because the base and index registers are the same
1055 * one and there was a remainder when trying to point to the data buffer. */
1056 uint32_t cSkippedSameBaseIndexRemainder;
1057 /** Number of skipped tests because index-only addressing left a remainder. */
1058 uint32_t cSkippedOnlyIndexRemainder;
1059 /** Number of skipped tests because of direct addressing overflowed. */
1060 uint32_t cSkippedDirectAddressingOverflow;
1061
1062
1063} CIDETCORE;
1064/** Pointer to the CIDET core state. */
1065typedef CIDETCORE *PCIDETCORE;
1066
1067/** Magic number for CIDETCORE (Lee Konitz). */
1068#define CIDETCORE_MAGIC UINT32_C(0x19271013)
1069
1070
1071int CidetCoreInit(PCIDETCORE pThis, RTRAND hRand);
1072void CidetCoreDelete(PCIDETCORE pThis);
1073int CidetCoreSetTargetMode(PCIDETCORE pThis, uint8_t bMode);
1074uint32_t CidetCoreGetOperandSize(PCIDETCORE pThis, uint8_t iOp);
1075bool CidetCoreTestInstruction(PCIDETCORE pThis, PCCIDETINSTR pInstr);
1076
1077
1078extern const CIDETINSTR g_aCidetInstructions1[];
1079extern const uint32_t g_cCidetInstructions1;
1080
1081#endif
1082
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette