| 1 | ;; Copyright 2012-2016 The OpenSSL Project Authors. All Rights Reserved.
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| 2 | ;;
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| 3 | ;; Licensed under the OpenSSL license (the "License"). You may not use
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| 4 | ;; this file except in compliance with the License. You can obtain a copy
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| 5 | ;; in the file LICENSE in the source distribution or at
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| 6 | ;; https://www.openssl.org/source/license.html
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| 7 | ;;
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| 8 | ;;====================================================================
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| 9 | ;; Written by Andy Polyakov <[email protected]> for the OpenSSL
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| 10 | ;; project.
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| 11 | ;;
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| 12 | ;; Rights for redistribution and usage in source and binary forms are
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| 13 | ;; granted according to the OpenSSL license. Warranty of any kind is
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| 14 | ;; disclaimed.
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| 15 | ;;====================================================================
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| 16 | ;; Compiler-generated multiply-n-add SPLOOP runs at 12*n cycles, n
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| 17 | ;; being the number of 32-bit words, addition - 8*n. Corresponding 4x
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| 18 | ;; unrolled SPLOOP-free loops - at ~8*n and ~5*n. Below assembler
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| 19 | ;; SPLOOPs spin at ... 2*n cycles [plus epilogue].
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| 20 | ;;====================================================================
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| 21 | .text
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| 22 |
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| 23 | .if .ASSEMBLER_VERSION<7000000
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| 24 | .asg 0,__TI_EABI__
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| 25 | .endif
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| 26 | .if __TI_EABI__
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| 27 | .asg bn_mul_add_words,_bn_mul_add_words
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| 28 | .asg bn_mul_words,_bn_mul_words
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| 29 | .asg bn_sqr_words,_bn_sqr_words
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| 30 | .asg bn_add_words,_bn_add_words
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| 31 | .asg bn_sub_words,_bn_sub_words
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| 32 | .asg bn_div_words,_bn_div_words
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| 33 | .asg bn_sqr_comba8,_bn_sqr_comba8
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| 34 | .asg bn_mul_comba8,_bn_mul_comba8
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| 35 | .asg bn_sqr_comba4,_bn_sqr_comba4
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| 36 | .asg bn_mul_comba4,_bn_mul_comba4
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| 37 | .endif
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| 38 |
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| 39 | .asg B3,RA
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| 40 | .asg A4,ARG0
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| 41 | .asg B4,ARG1
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| 42 | .asg A6,ARG2
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| 43 | .asg B6,ARG3
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| 44 | .asg A8,ARG4
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| 45 | .asg B8,ARG5
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| 46 | .asg A4,RET
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| 47 | .asg A15,FP
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| 48 | .asg B14,DP
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| 49 | .asg B15,SP
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| 50 |
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| 51 | .global _bn_mul_add_words
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| 52 | _bn_mul_add_words:
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| 53 | .asmfunc
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| 54 | MV ARG2,B0
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| 55 | [!B0] BNOP RA
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| 56 | ||[!B0] MVK 0,RET
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| 57 | [B0] MVC B0,ILC
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| 58 | [B0] ZERO A19 ; high part of accumulator
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| 59 | || [B0] MV ARG0,A2
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| 60 | || [B0] MV ARG3,A3
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| 61 | NOP 3
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| 62 |
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| 63 | SPLOOP 2 ; 2*n+10
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| 64 | ;;====================================================================
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| 65 | LDW *ARG1++,B7 ; ap[i]
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| 66 | NOP 3
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| 67 | LDW *ARG0++,A7 ; rp[i]
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| 68 | MPY32U B7,A3,A17:A16
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| 69 | NOP 3 ; [2,0] in epilogue
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| 70 | ADDU A16,A7,A21:A20
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| 71 | ADDU A19,A21:A20,A19:A18
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| 72 | || MV.S A17,A23
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| 73 | SPKERNEL 2,1 ; leave slot for "return value"
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| 74 | || STW A18,*A2++ ; rp[i]
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| 75 | || ADD A19,A23,A19
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| 76 | ;;====================================================================
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| 77 | BNOP RA,4
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| 78 | MV A19,RET ; return value
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| 79 | .endasmfunc
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| 80 |
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| 81 | .global _bn_mul_words
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| 82 | _bn_mul_words:
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| 83 | .asmfunc
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| 84 | MV ARG2,B0
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| 85 | [!B0] BNOP RA
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| 86 | ||[!B0] MVK 0,RET
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| 87 | [B0] MVC B0,ILC
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| 88 | [B0] ZERO A19 ; high part of accumulator
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| 89 | NOP 3
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| 90 |
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| 91 | SPLOOP 2 ; 2*n+10
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| 92 | ;;====================================================================
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| 93 | LDW *ARG1++,A7 ; ap[i]
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| 94 | NOP 4
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| 95 | MPY32U A7,ARG3,A17:A16
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| 96 | NOP 4 ; [2,0] in epiloque
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| 97 | ADDU A19,A16,A19:A18
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| 98 | || MV.S A17,A21
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| 99 | SPKERNEL 2,1 ; leave slot for "return value"
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| 100 | || STW A18,*ARG0++ ; rp[i]
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| 101 | || ADD.L A19,A21,A19
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| 102 | ;;====================================================================
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| 103 | BNOP RA,4
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| 104 | MV A19,RET ; return value
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| 105 | .endasmfunc
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| 106 |
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| 107 | .global _bn_sqr_words
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| 108 | _bn_sqr_words:
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| 109 | .asmfunc
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| 110 | MV ARG2,B0
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| 111 | [!B0] BNOP RA
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| 112 | ||[!B0] MVK 0,RET
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| 113 | [B0] MVC B0,ILC
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| 114 | [B0] MV ARG0,B2
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| 115 | || [B0] ADD 4,ARG0,ARG0
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| 116 | NOP 3
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| 117 |
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| 118 | SPLOOP 2 ; 2*n+10
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| 119 | ;;====================================================================
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| 120 | LDW *ARG1++,B7 ; ap[i]
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| 121 | NOP 4
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| 122 | MPY32U B7,B7,B1:B0
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| 123 | NOP 3 ; [2,0] in epilogue
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| 124 | STW B0,*B2++(8) ; rp[2*i]
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| 125 | MV B1,A1
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| 126 | SPKERNEL 2,0 ; fully overlap BNOP RA,5
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| 127 | || STW A1,*ARG0++(8) ; rp[2*i+1]
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| 128 | ;;====================================================================
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| 129 | BNOP RA,5
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| 130 | .endasmfunc
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| 131 |
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| 132 | .global _bn_add_words
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| 133 | _bn_add_words:
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| 134 | .asmfunc
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| 135 | MV ARG3,B0
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| 136 | [!B0] BNOP RA
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| 137 | ||[!B0] MVK 0,RET
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| 138 | [B0] MVC B0,ILC
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| 139 | [B0] ZERO A1 ; carry flag
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| 140 | || [B0] MV ARG0,A3
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| 141 | NOP 3
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| 142 |
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| 143 | SPLOOP 2 ; 2*n+6
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| 144 | ;;====================================================================
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| 145 | LDW *ARG2++,A7 ; bp[i]
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| 146 | || LDW *ARG1++,B7 ; ap[i]
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| 147 | NOP 4
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| 148 | ADDU A7,B7,A9:A8
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| 149 | ADDU A1,A9:A8,A1:A0
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| 150 | SPKERNEL 0,0 ; fully overlap BNOP RA,5
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| 151 | || STW A0,*A3++ ; write result
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| 152 | || MV A1,RET ; keep carry flag in RET
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| 153 | ;;====================================================================
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| 154 | BNOP RA,5
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| 155 | .endasmfunc
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| 156 |
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| 157 | .global _bn_sub_words
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| 158 | _bn_sub_words:
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| 159 | .asmfunc
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| 160 | MV ARG3,B0
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| 161 | [!B0] BNOP RA
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| 162 | ||[!B0] MVK 0,RET
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| 163 | [B0] MVC B0,ILC
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| 164 | [B0] ZERO A2 ; borrow flag
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| 165 | || [B0] MV ARG0,A3
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| 166 | NOP 3
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| 167 |
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| 168 | SPLOOP 2 ; 2*n+6
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| 169 | ;;====================================================================
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| 170 | LDW *ARG2++,A7 ; bp[i]
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| 171 | || LDW *ARG1++,B7 ; ap[i]
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| 172 | NOP 4
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| 173 | SUBU B7,A7,A1:A0
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| 174 | [A2] SUB A1:A0,1,A1:A0
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| 175 | SPKERNEL 0,1 ; leave slot for "return borrow flag"
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| 176 | || STW A0,*A3++ ; write result
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| 177 | || AND 1,A1,A2 ; pass on borrow flag
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| 178 | ;;====================================================================
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| 179 | BNOP RA,4
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| 180 | AND 1,A1,RET ; return borrow flag
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| 181 | .endasmfunc
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| 182 |
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| 183 | .global _bn_div_words
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| 184 | _bn_div_words:
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| 185 | .asmfunc
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| 186 | LMBD 1,A6,A0 ; leading zero bits in dv
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| 187 | LMBD 1,A4,A1 ; leading zero bits in hi
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| 188 | || MVK 32,B0
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| 189 | CMPLTU A1,A0,A2
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| 190 | || ADD A0,B0,B0
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| 191 | [ A2] BNOP RA
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| 192 | ||[ A2] MVK -1,A4 ; return overflow
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| 193 | ||[!A2] MV A4,A3 ; reassign hi
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| 194 | [!A2] MV B4,A4 ; reassign lo, will be quotient
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| 195 | ||[!A2] MVC B0,ILC
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| 196 | [!A2] SHL A6,A0,A6 ; normalize dv
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| 197 | || MVK 1,A1
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| 198 |
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| 199 | [!A2] CMPLTU A3,A6,A1 ; hi<dv?
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| 200 | ||[!A2] SHL A4,1,A5:A4 ; lo<<1
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| 201 | [!A1] SUB A3,A6,A3 ; hi-=dv
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| 202 | ||[!A1] OR 1,A4,A4
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| 203 | [!A2] SHRU A3,31,A1 ; upper bit
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| 204 | ||[!A2] ADDAH A5,A3,A3 ; hi<<1|lo>>31
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| 205 |
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| 206 | SPLOOP 3
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| 207 | [!A1] CMPLTU A3,A6,A1 ; hi<dv?
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| 208 | ||[ A1] ZERO A1
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| 209 | || SHL A4,1,A5:A4 ; lo<<1
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| 210 | [!A1] SUB A3,A6,A3 ; hi-=dv
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| 211 | ||[!A1] OR 1,A4,A4 ; quotient
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| 212 | SHRU A3,31,A1 ; upper bit
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| 213 | || ADDAH A5,A3,A3 ; hi<<1|lo>>31
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| 214 | SPKERNEL
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| 215 |
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| 216 | BNOP RA,5
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| 217 | .endasmfunc
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| 218 |
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| 219 | ;;====================================================================
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| 220 | ;; Not really Comba algorithm, just straightforward NxM... Dedicated
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| 221 | ;; fully unrolled real Comba implementations are asymptotically 2x
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| 222 | ;; faster, but naturally larger undertaking. Purpose of this exercise
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| 223 | ;; was rather to learn to master nested SPLOOPs...
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| 224 | ;;====================================================================
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| 225 | .global _bn_sqr_comba8
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| 226 | .global _bn_mul_comba8
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| 227 | _bn_sqr_comba8:
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| 228 | MV ARG1,ARG2
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| 229 | _bn_mul_comba8:
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| 230 | .asmfunc
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| 231 | MVK 8,B0 ; N, RILC
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| 232 | || MVK 8,A0 ; M, outer loop counter
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| 233 | || MV ARG1,A5 ; copy ap
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| 234 | || MV ARG0,B4 ; copy rp
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| 235 | || ZERO B19 ; high part of accumulator
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| 236 | MVC B0,RILC
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| 237 | || SUB B0,2,B1 ; N-2, initial ILC
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| 238 | || SUB B0,1,B2 ; const B2=N-1
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| 239 | || LDW *A5++,B6 ; ap[0]
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| 240 | || MV A0,A3 ; const A3=M
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| 241 | sploopNxM?: ; for best performance arrange M<=N
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| 242 | [A0] SPLOOPD 2 ; 2*n+10
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| 243 | || MVC B1,ILC
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| 244 | || ADDAW B4,B0,B5
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| 245 | || ZERO B7
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| 246 | || LDW *A5++,A9 ; pre-fetch ap[1]
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| 247 | || ZERO A1
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| 248 | || SUB A0,1,A0
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| 249 | ;;====================================================================
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| 250 | ;; SPLOOP from bn_mul_add_words, but with flipped A<>B register files.
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| 251 | ;; This is because of Advisory 15 from TI publication SPRZ247I.
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| 252 | LDW *ARG2++,A7 ; bp[i]
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| 253 | NOP 3
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| 254 | [A1] LDW *B5++,B7 ; rp[i]
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| 255 | MPY32U A7,B6,B17:B16
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| 256 | NOP 3
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| 257 | ADDU B16,B7,B21:B20
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| 258 | ADDU B19,B21:B20,B19:B18
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| 259 | || MV.S B17,B23
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| 260 | SPKERNEL
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| 261 | || STW B18,*B4++ ; rp[i]
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| 262 | || ADD.S B19,B23,B19
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| 263 | ;;====================================================================
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| 264 | outer?: ; m*2*(n+1)+10
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| 265 | SUBAW ARG2,A3,ARG2 ; rewind bp to bp[0]
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| 266 | SPMASKR
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| 267 | || CMPGT A0,1,A2 ; done pre-fetching ap[i+1]?
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| 268 | MVD A9,B6 ; move through .M unit(*)
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| 269 | [A2] LDW *A5++,A9 ; pre-fetch ap[i+1]
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| 270 | SUBAW B5,B2,B5 ; rewind rp to rp[1]
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| 271 | MVK 1,A1
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| 272 | [A0] BNOP.S1 outer?,4
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| 273 | || [A0] SUB.L A0,1,A0
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| 274 | STW B19,*B4--[B2] ; rewind rp tp rp[1]
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| 275 | || ZERO.S B19 ; high part of accumulator
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| 276 | ;; end of outer?
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| 277 | BNOP RA,5 ; return
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| 278 | .endasmfunc
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| 279 | ;; (*) It should be noted that B6 is used as input to MPY32U in
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| 280 | ;; chronologically next cycle in *preceding* SPLOOP iteration.
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| 281 | ;; Normally such arrangement would require DINT, but at this
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| 282 | ;; point SPLOOP is draining and interrupts are disabled
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| 283 | ;; implicitly.
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| 284 |
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| 285 | .global _bn_sqr_comba4
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| 286 | .global _bn_mul_comba4
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| 287 | _bn_sqr_comba4:
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| 288 | MV ARG1,ARG2
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| 289 | _bn_mul_comba4:
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| 290 | .asmfunc
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| 291 | .if 0
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| 292 | BNOP sploopNxM?,3
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| 293 | ;; Above mentioned m*2*(n+1)+10 does not apply in n=m=4 case,
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| 294 | ;; because of low-counter effect, when prologue phase finishes
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| 295 | ;; before SPKERNEL instruction is reached. As result it's 25%
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| 296 | ;; slower than expected...
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| 297 | MVK 4,B0 ; N, RILC
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| 298 | || MVK 4,A0 ; M, outer loop counter
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| 299 | || MV ARG1,A5 ; copy ap
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| 300 | || MV ARG0,B4 ; copy rp
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| 301 | || ZERO B19 ; high part of accumulator
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| 302 | MVC B0,RILC
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| 303 | || SUB B0,2,B1 ; first ILC
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| 304 | || SUB B0,1,B2 ; const B2=N-1
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| 305 | || LDW *A5++,B6 ; ap[0]
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| 306 | || MV A0,A3 ; const A3=M
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| 307 | .else
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| 308 | ;; This alternative is an exercise in fully unrolled Comba
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| 309 | ;; algorithm implementation that operates at n*(n+1)+12, or
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| 310 | ;; as little as 32 cycles...
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| 311 | LDW *ARG1[0],B16 ; a[0]
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| 312 | || LDW *ARG2[0],A16 ; b[0]
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| 313 | LDW *ARG1[1],B17 ; a[1]
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| 314 | || LDW *ARG2[1],A17 ; b[1]
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| 315 | LDW *ARG1[2],B18 ; a[2]
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| 316 | || LDW *ARG2[2],A18 ; b[2]
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| 317 | LDW *ARG1[3],B19 ; a[3]
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| 318 | || LDW *ARG2[3],A19 ; b[3]
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| 319 | NOP
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| 320 | MPY32U A16,B16,A1:A0 ; a[0]*b[0]
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| 321 | MPY32U A17,B16,A23:A22 ; a[0]*b[1]
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| 322 | MPY32U A16,B17,A25:A24 ; a[1]*b[0]
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| 323 | MPY32U A16,B18,A27:A26 ; a[2]*b[0]
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| 324 | STW A0,*ARG0[0]
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| 325 | || MPY32U A17,B17,A29:A28 ; a[1]*b[1]
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| 326 | MPY32U A18,B16,A31:A30 ; a[0]*b[2]
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| 327 | || ADDU A22,A1,A1:A0
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| 328 | MV A23,B0
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| 329 | || MPY32U A19,B16,A21:A20 ; a[3]*b[0]
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| 330 | || ADDU A24,A1:A0,A1:A0
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| 331 | ADDU A25,B0,B1:B0
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| 332 | || STW A0,*ARG0[1]
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| 333 | || MPY32U A18,B17,A23:A22 ; a[2]*b[1]
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| 334 | || ADDU A26,A1,A9:A8
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| 335 | ADDU A27,B1,B9:B8
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| 336 | || MPY32U A17,B18,A25:A24 ; a[1]*b[2]
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| 337 | || ADDU A28,A9:A8,A9:A8
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| 338 | ADDU A29,B9:B8,B9:B8
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| 339 | || MPY32U A16,B19,A27:A26 ; a[0]*b[3]
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| 340 | || ADDU A30,A9:A8,A9:A8
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| 341 | ADDU A31,B9:B8,B9:B8
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| 342 | || ADDU B0,A9:A8,A9:A8
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| 343 | STW A8,*ARG0[2]
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| 344 | || ADDU A20,A9,A1:A0
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| 345 | ADDU A21,B9,B1:B0
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| 346 | || MPY32U A19,B17,A21:A20 ; a[3]*b[1]
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| 347 | || ADDU A22,A1:A0,A1:A0
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| 348 | ADDU A23,B1:B0,B1:B0
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| 349 | || MPY32U A18,B18,A23:A22 ; a[2]*b[2]
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| 350 | || ADDU A24,A1:A0,A1:A0
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| 351 | ADDU A25,B1:B0,B1:B0
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| 352 | || MPY32U A17,B19,A25:A24 ; a[1]*b[3]
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| 353 | || ADDU A26,A1:A0,A1:A0
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| 354 | ADDU A27,B1:B0,B1:B0
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| 355 | || ADDU B8,A1:A0,A1:A0
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| 356 | STW A0,*ARG0[3]
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| 357 | || MPY32U A19,B18,A27:A26 ; a[3]*b[2]
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| 358 | || ADDU A20,A1,A9:A8
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|---|
| 359 | ADDU A21,B1,B9:B8
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|---|
| 360 | || MPY32U A18,B19,A29:A28 ; a[2]*b[3]
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|---|
| 361 | || ADDU A22,A9:A8,A9:A8
|
|---|
| 362 | ADDU A23,B9:B8,B9:B8
|
|---|
| 363 | || MPY32U A19,B19,A31:A30 ; a[3]*b[3]
|
|---|
| 364 | || ADDU A24,A9:A8,A9:A8
|
|---|
| 365 | ADDU A25,B9:B8,B9:B8
|
|---|
| 366 | || ADDU B0,A9:A8,A9:A8
|
|---|
| 367 | STW A8,*ARG0[4]
|
|---|
| 368 | || ADDU A26,A9,A1:A0
|
|---|
| 369 | ADDU A27,B9,B1:B0
|
|---|
| 370 | || ADDU A28,A1:A0,A1:A0
|
|---|
| 371 | ADDU A29,B1:B0,B1:B0
|
|---|
| 372 | || BNOP RA
|
|---|
| 373 | || ADDU B8,A1:A0,A1:A0
|
|---|
| 374 | STW A0,*ARG0[5]
|
|---|
| 375 | || ADDU A30,A1,A9:A8
|
|---|
| 376 | ADD A31,B1,B8
|
|---|
| 377 | ADDU B0,A9:A8,A9:A8 ; removed || to avoid cross-path stall below
|
|---|
| 378 | ADD B8,A9,A9
|
|---|
| 379 | || STW A8,*ARG0[6]
|
|---|
| 380 | STW A9,*ARG0[7]
|
|---|
| 381 | .endif
|
|---|
| 382 | .endasmfunc
|
|---|
