| 1 | #! /usr/bin/env perl
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| 2 | # Copyright 2010-2016 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | #
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| 4 | # Licensed under the OpenSSL license (the "License"). You may not use
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| 5 | # this file except in compliance with the License. You can obtain a copy
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| 6 | # in the file LICENSE in the source distribution or at
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| 7 | # https://www.openssl.org/source/license.html
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| 8 |
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| 9 | #
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| 10 | # ====================================================================
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| 11 | # Written by Andy Polyakov <[email protected]> for the OpenSSL
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| 12 | # project. The module is, however, dual licensed under OpenSSL and
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| 13 | # CRYPTOGAMS licenses depending on where you obtain it. For further
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| 14 | # details see http://www.openssl.org/~appro/cryptogams/.
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| 15 | # ====================================================================
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| 16 | #
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| 17 | # April 2010
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| 18 | #
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| 19 | # The module implements "4-bit" GCM GHASH function and underlying
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| 20 | # single multiplication operation in GF(2^128). "4-bit" means that it
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| 21 | # uses 256 bytes per-key table [+32 bytes shared table]. There is no
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| 22 | # experimental performance data available yet. The only approximation
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| 23 | # that can be made at this point is based on code size. Inner loop is
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| 24 | # 32 instructions long and on single-issue core should execute in <40
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| 25 | # cycles. Having verified that gcc 3.4 didn't unroll corresponding
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| 26 | # loop, this assembler loop body was found to be ~3x smaller than
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| 27 | # compiler-generated one...
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| 28 | #
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| 29 | # July 2010
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| 30 | #
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| 31 | # Rescheduling for dual-issue pipeline resulted in 8.5% improvement on
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| 32 | # Cortex A8 core and ~25 cycles per processed byte (which was observed
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| 33 | # to be ~3 times faster than gcc-generated code:-)
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| 34 | #
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| 35 | # February 2011
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| 36 | #
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| 37 | # Profiler-assisted and platform-specific optimization resulted in 7%
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| 38 | # improvement on Cortex A8 core and ~23.5 cycles per byte.
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| 39 | #
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| 40 | # March 2011
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| 41 | #
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| 42 | # Add NEON implementation featuring polynomial multiplication, i.e. no
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| 43 | # lookup tables involved. On Cortex A8 it was measured to process one
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| 44 | # byte in 15 cycles or 55% faster than integer-only code.
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| 45 | #
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| 46 | # April 2014
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| 47 | #
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| 48 | # Switch to multiplication algorithm suggested in paper referred
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| 49 | # below and combine it with reduction algorithm from x86 module.
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| 50 | # Performance improvement over previous version varies from 65% on
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| 51 | # Snapdragon S4 to 110% on Cortex A9. In absolute terms Cortex A8
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| 52 | # processes one byte in 8.45 cycles, A9 - in 10.2, A15 - in 7.63,
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| 53 | # Snapdragon S4 - in 9.33.
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| 54 | #
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| 55 | # Câmara, D.; Gouvêa, C. P. L.; López, J. & Dahab, R.: Fast Software
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| 56 | # Polynomial Multiplication on ARM Processors using the NEON Engine.
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| 57 | #
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| 58 | # http://conradoplg.cryptoland.net/files/2010/12/mocrysen13.pdf
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| 59 |
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| 60 | # ====================================================================
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| 61 | # Note about "528B" variant. In ARM case it makes lesser sense to
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| 62 | # implement it for following reasons:
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| 63 | #
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| 64 | # - performance improvement won't be anywhere near 50%, because 128-
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| 65 | # bit shift operation is neatly fused with 128-bit xor here, and
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| 66 | # "538B" variant would eliminate only 4-5 instructions out of 32
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| 67 | # in the inner loop (meaning that estimated improvement is ~15%);
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| 68 | # - ARM-based systems are often embedded ones and extra memory
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| 69 | # consumption might be unappreciated (for so little improvement);
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| 70 | #
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| 71 | # Byte order [in]dependence. =========================================
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| 72 | #
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| 73 | # Caller is expected to maintain specific *dword* order in Htable,
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| 74 | # namely with *least* significant dword of 128-bit value at *lower*
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| 75 | # address. This differs completely from C code and has everything to
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| 76 | # do with ldm instruction and order in which dwords are "consumed" by
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| 77 | # algorithm. *Byte* order within these dwords in turn is whatever
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| 78 | # *native* byte order on current platform. See gcm128.c for working
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| 79 | # example...
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| 80 |
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| 81 | $flavour = shift;
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| 82 | if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
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| 83 | else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
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| 84 |
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| 85 | if ($flavour && $flavour ne "void") {
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| 86 | $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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| 87 | ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
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| 88 | ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
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| 89 | die "can't locate arm-xlate.pl";
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| 90 |
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| 91 | open STDOUT,"| \"$^X\" $xlate $flavour $output";
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| 92 | } else {
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| 93 | open STDOUT,">$output";
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| 94 | }
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| 95 |
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| 96 | $Xi="r0"; # argument block
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| 97 | $Htbl="r1";
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| 98 | $inp="r2";
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| 99 | $len="r3";
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| 100 |
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| 101 | $Zll="r4"; # variables
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| 102 | $Zlh="r5";
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| 103 | $Zhl="r6";
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| 104 | $Zhh="r7";
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| 105 | $Tll="r8";
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| 106 | $Tlh="r9";
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| 107 | $Thl="r10";
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| 108 | $Thh="r11";
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| 109 | $nlo="r12";
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| 110 | ################# r13 is stack pointer
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| 111 | $nhi="r14";
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| 112 | ################# r15 is program counter
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| 113 |
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| 114 | $rem_4bit=$inp; # used in gcm_gmult_4bit
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| 115 | $cnt=$len;
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| 116 |
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| 117 | sub Zsmash() {
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| 118 | my $i=12;
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| 119 | my @args=@_;
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| 120 | for ($Zll,$Zlh,$Zhl,$Zhh) {
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| 121 | $code.=<<___;
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| 122 | #if __ARM_ARCH__>=7 && defined(__ARMEL__)
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| 123 | rev $_,$_
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| 124 | str $_,[$Xi,#$i]
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| 125 | #elif defined(__ARMEB__)
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| 126 | str $_,[$Xi,#$i]
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| 127 | #else
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| 128 | mov $Tlh,$_,lsr#8
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| 129 | strb $_,[$Xi,#$i+3]
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| 130 | mov $Thl,$_,lsr#16
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| 131 | strb $Tlh,[$Xi,#$i+2]
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| 132 | mov $Thh,$_,lsr#24
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| 133 | strb $Thl,[$Xi,#$i+1]
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| 134 | strb $Thh,[$Xi,#$i]
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| 135 | #endif
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| 136 | ___
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| 137 | $code.="\t".shift(@args)."\n";
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| 138 | $i-=4;
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| 139 | }
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| 140 | }
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| 141 |
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| 142 | $code=<<___;
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| 143 | #include "arm_arch.h"
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| 144 |
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| 145 | .text
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| 146 | #if defined(__thumb2__) || defined(__clang__)
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| 147 | .syntax unified
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| 148 | #endif
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| 149 | #if defined(__thumb2__)
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| 150 | .thumb
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| 151 | #else
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| 152 | .code 32
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| 153 | #endif
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| 154 |
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| 155 | #ifdef __clang__
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| 156 | #define ldrplb ldrbpl
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| 157 | #define ldrneb ldrbne
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| 158 | #endif
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| 159 |
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| 160 | .type rem_4bit,%object
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| 161 | .align 5
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| 162 | rem_4bit:
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| 163 | .short 0x0000,0x1C20,0x3840,0x2460
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| 164 | .short 0x7080,0x6CA0,0x48C0,0x54E0
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| 165 | .short 0xE100,0xFD20,0xD940,0xC560
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| 166 | .short 0x9180,0x8DA0,0xA9C0,0xB5E0
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| 167 | .size rem_4bit,.-rem_4bit
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| 168 |
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| 169 | .type rem_4bit_get,%function
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| 170 | rem_4bit_get:
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| 171 | #if defined(__thumb2__)
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| 172 | adr $rem_4bit,rem_4bit
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| 173 | #else
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| 174 | sub $rem_4bit,pc,#8+32 @ &rem_4bit
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| 175 | #endif
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| 176 | b .Lrem_4bit_got
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| 177 | nop
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| 178 | nop
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| 179 | .size rem_4bit_get,.-rem_4bit_get
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| 180 |
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| 181 | .global gcm_ghash_4bit
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| 182 | .type gcm_ghash_4bit,%function
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| 183 | .align 4
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| 184 | gcm_ghash_4bit:
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| 185 | #if defined(__thumb2__)
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| 186 | adr r12,rem_4bit
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| 187 | #else
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| 188 | sub r12,pc,#8+48 @ &rem_4bit
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| 189 | #endif
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| 190 | add $len,$inp,$len @ $len to point at the end
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| 191 | stmdb sp!,{r3-r11,lr} @ save $len/end too
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| 192 |
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| 193 | ldmia r12,{r4-r11} @ copy rem_4bit ...
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| 194 | stmdb sp!,{r4-r11} @ ... to stack
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| 195 |
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| 196 | ldrb $nlo,[$inp,#15]
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| 197 | ldrb $nhi,[$Xi,#15]
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| 198 | .Louter:
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| 199 | eor $nlo,$nlo,$nhi
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| 200 | and $nhi,$nlo,#0xf0
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| 201 | and $nlo,$nlo,#0x0f
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| 202 | mov $cnt,#14
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| 203 |
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| 204 | add $Zhh,$Htbl,$nlo,lsl#4
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| 205 | ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo]
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| 206 | add $Thh,$Htbl,$nhi
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| 207 | ldrb $nlo,[$inp,#14]
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| 208 |
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| 209 | and $nhi,$Zll,#0xf @ rem
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| 210 | ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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| 211 | add $nhi,$nhi,$nhi
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| 212 | eor $Zll,$Tll,$Zll,lsr#4
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| 213 | ldrh $Tll,[sp,$nhi] @ rem_4bit[rem]
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| 214 | eor $Zll,$Zll,$Zlh,lsl#28
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| 215 | ldrb $nhi,[$Xi,#14]
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| 216 | eor $Zlh,$Tlh,$Zlh,lsr#4
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| 217 | eor $Zlh,$Zlh,$Zhl,lsl#28
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| 218 | eor $Zhl,$Thl,$Zhl,lsr#4
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| 219 | eor $Zhl,$Zhl,$Zhh,lsl#28
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| 220 | eor $Zhh,$Thh,$Zhh,lsr#4
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| 221 | eor $nlo,$nlo,$nhi
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| 222 | and $nhi,$nlo,#0xf0
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| 223 | and $nlo,$nlo,#0x0f
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| 224 | eor $Zhh,$Zhh,$Tll,lsl#16
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| 225 |
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| 226 | .Linner:
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| 227 | add $Thh,$Htbl,$nlo,lsl#4
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| 228 | and $nlo,$Zll,#0xf @ rem
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| 229 | subs $cnt,$cnt,#1
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| 230 | add $nlo,$nlo,$nlo
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| 231 | ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo]
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| 232 | eor $Zll,$Tll,$Zll,lsr#4
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| 233 | eor $Zll,$Zll,$Zlh,lsl#28
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| 234 | eor $Zlh,$Tlh,$Zlh,lsr#4
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| 235 | eor $Zlh,$Zlh,$Zhl,lsl#28
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| 236 | ldrh $Tll,[sp,$nlo] @ rem_4bit[rem]
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| 237 | eor $Zhl,$Thl,$Zhl,lsr#4
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| 238 | #ifdef __thumb2__
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| 239 | it pl
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| 240 | #endif
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| 241 | ldrplb $nlo,[$inp,$cnt]
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| 242 | eor $Zhl,$Zhl,$Zhh,lsl#28
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| 243 | eor $Zhh,$Thh,$Zhh,lsr#4
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| 244 |
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| 245 | add $Thh,$Htbl,$nhi
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| 246 | and $nhi,$Zll,#0xf @ rem
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| 247 | eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
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| 248 | add $nhi,$nhi,$nhi
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| 249 | ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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| 250 | eor $Zll,$Tll,$Zll,lsr#4
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| 251 | #ifdef __thumb2__
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| 252 | it pl
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| 253 | #endif
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| 254 | ldrplb $Tll,[$Xi,$cnt]
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| 255 | eor $Zll,$Zll,$Zlh,lsl#28
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| 256 | eor $Zlh,$Tlh,$Zlh,lsr#4
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| 257 | ldrh $Tlh,[sp,$nhi]
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| 258 | eor $Zlh,$Zlh,$Zhl,lsl#28
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| 259 | eor $Zhl,$Thl,$Zhl,lsr#4
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| 260 | eor $Zhl,$Zhl,$Zhh,lsl#28
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| 261 | #ifdef __thumb2__
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| 262 | it pl
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| 263 | #endif
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| 264 | eorpl $nlo,$nlo,$Tll
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| 265 | eor $Zhh,$Thh,$Zhh,lsr#4
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| 266 | #ifdef __thumb2__
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| 267 | itt pl
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| 268 | #endif
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| 269 | andpl $nhi,$nlo,#0xf0
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| 270 | andpl $nlo,$nlo,#0x0f
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| 271 | eor $Zhh,$Zhh,$Tlh,lsl#16 @ ^= rem_4bit[rem]
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| 272 | bpl .Linner
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| 273 |
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| 274 | ldr $len,[sp,#32] @ re-load $len/end
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| 275 | add $inp,$inp,#16
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| 276 | mov $nhi,$Zll
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| 277 | ___
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| 278 | &Zsmash("cmp\t$inp,$len","\n".
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| 279 | "#ifdef __thumb2__\n".
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| 280 | " it ne\n".
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| 281 | "#endif\n".
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| 282 | " ldrneb $nlo,[$inp,#15]");
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| 283 | $code.=<<___;
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| 284 | bne .Louter
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| 285 |
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| 286 | add sp,sp,#36
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| 287 | #if __ARM_ARCH__>=5
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| 288 | ldmia sp!,{r4-r11,pc}
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| 289 | #else
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| 290 | ldmia sp!,{r4-r11,lr}
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| 291 | tst lr,#1
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| 292 | moveq pc,lr @ be binary compatible with V4, yet
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| 293 | bx lr @ interoperable with Thumb ISA:-)
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| 294 | #endif
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| 295 | .size gcm_ghash_4bit,.-gcm_ghash_4bit
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| 296 |
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| 297 | .global gcm_gmult_4bit
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| 298 | .type gcm_gmult_4bit,%function
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| 299 | gcm_gmult_4bit:
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| 300 | stmdb sp!,{r4-r11,lr}
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| 301 | ldrb $nlo,[$Xi,#15]
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| 302 | b rem_4bit_get
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| 303 | .Lrem_4bit_got:
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| 304 | and $nhi,$nlo,#0xf0
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| 305 | and $nlo,$nlo,#0x0f
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| 306 | mov $cnt,#14
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| 307 |
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| 308 | add $Zhh,$Htbl,$nlo,lsl#4
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| 309 | ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo]
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| 310 | ldrb $nlo,[$Xi,#14]
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| 311 |
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| 312 | add $Thh,$Htbl,$nhi
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| 313 | and $nhi,$Zll,#0xf @ rem
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| 314 | ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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| 315 | add $nhi,$nhi,$nhi
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| 316 | eor $Zll,$Tll,$Zll,lsr#4
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| 317 | ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem]
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| 318 | eor $Zll,$Zll,$Zlh,lsl#28
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| 319 | eor $Zlh,$Tlh,$Zlh,lsr#4
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| 320 | eor $Zlh,$Zlh,$Zhl,lsl#28
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| 321 | eor $Zhl,$Thl,$Zhl,lsr#4
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| 322 | eor $Zhl,$Zhl,$Zhh,lsl#28
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| 323 | eor $Zhh,$Thh,$Zhh,lsr#4
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| 324 | and $nhi,$nlo,#0xf0
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| 325 | eor $Zhh,$Zhh,$Tll,lsl#16
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| 326 | and $nlo,$nlo,#0x0f
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| 327 |
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| 328 | .Loop:
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| 329 | add $Thh,$Htbl,$nlo,lsl#4
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| 330 | and $nlo,$Zll,#0xf @ rem
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| 331 | subs $cnt,$cnt,#1
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| 332 | add $nlo,$nlo,$nlo
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| 333 | ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo]
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| 334 | eor $Zll,$Tll,$Zll,lsr#4
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| 335 | eor $Zll,$Zll,$Zlh,lsl#28
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| 336 | eor $Zlh,$Tlh,$Zlh,lsr#4
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| 337 | eor $Zlh,$Zlh,$Zhl,lsl#28
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| 338 | ldrh $Tll,[$rem_4bit,$nlo] @ rem_4bit[rem]
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| 339 | eor $Zhl,$Thl,$Zhl,lsr#4
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| 340 | #ifdef __thumb2__
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| 341 | it pl
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| 342 | #endif
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| 343 | ldrplb $nlo,[$Xi,$cnt]
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| 344 | eor $Zhl,$Zhl,$Zhh,lsl#28
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| 345 | eor $Zhh,$Thh,$Zhh,lsr#4
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| 346 |
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| 347 | add $Thh,$Htbl,$nhi
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| 348 | and $nhi,$Zll,#0xf @ rem
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| 349 | eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
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| 350 | add $nhi,$nhi,$nhi
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| 351 | ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi]
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| 352 | eor $Zll,$Tll,$Zll,lsr#4
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| 353 | eor $Zll,$Zll,$Zlh,lsl#28
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| 354 | eor $Zlh,$Tlh,$Zlh,lsr#4
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| 355 | ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem]
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| 356 | eor $Zlh,$Zlh,$Zhl,lsl#28
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| 357 | eor $Zhl,$Thl,$Zhl,lsr#4
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| 358 | eor $Zhl,$Zhl,$Zhh,lsl#28
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| 359 | eor $Zhh,$Thh,$Zhh,lsr#4
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| 360 | #ifdef __thumb2__
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| 361 | itt pl
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| 362 | #endif
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| 363 | andpl $nhi,$nlo,#0xf0
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| 364 | andpl $nlo,$nlo,#0x0f
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| 365 | eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem]
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| 366 | bpl .Loop
|
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| 367 | ___
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| 368 | &Zsmash();
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| 369 | $code.=<<___;
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| 370 | #if __ARM_ARCH__>=5
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| 371 | ldmia sp!,{r4-r11,pc}
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| 372 | #else
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| 373 | ldmia sp!,{r4-r11,lr}
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| 374 | tst lr,#1
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| 375 | moveq pc,lr @ be binary compatible with V4, yet
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| 376 | bx lr @ interoperable with Thumb ISA:-)
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| 377 | #endif
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| 378 | .size gcm_gmult_4bit,.-gcm_gmult_4bit
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| 379 | ___
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| 380 | {
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| 381 | my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
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| 382 | my ($t0,$t1,$t2,$t3)=map("q$_",(8..12));
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| 383 | my ($Hlo,$Hhi,$Hhl,$k48,$k32,$k16)=map("d$_",(26..31));
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| 384 |
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| 385 | sub clmul64x64 {
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| 386 | my ($r,$a,$b)=@_;
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| 387 | $code.=<<___;
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| 388 | vext.8 $t0#lo, $a, $a, #1 @ A1
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| 389 | vmull.p8 $t0, $t0#lo, $b @ F = A1*B
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| 390 | vext.8 $r#lo, $b, $b, #1 @ B1
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| 391 | vmull.p8 $r, $a, $r#lo @ E = A*B1
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| 392 | vext.8 $t1#lo, $a, $a, #2 @ A2
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| 393 | vmull.p8 $t1, $t1#lo, $b @ H = A2*B
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| 394 | vext.8 $t3#lo, $b, $b, #2 @ B2
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| 395 | vmull.p8 $t3, $a, $t3#lo @ G = A*B2
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| 396 | vext.8 $t2#lo, $a, $a, #3 @ A3
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| 397 | veor $t0, $t0, $r @ L = E + F
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| 398 | vmull.p8 $t2, $t2#lo, $b @ J = A3*B
|
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| 399 | vext.8 $r#lo, $b, $b, #3 @ B3
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| 400 | veor $t1, $t1, $t3 @ M = G + H
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| 401 | vmull.p8 $r, $a, $r#lo @ I = A*B3
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| 402 | veor $t0#lo, $t0#lo, $t0#hi @ t0 = (L) (P0 + P1) << 8
|
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| 403 | vand $t0#hi, $t0#hi, $k48
|
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| 404 | vext.8 $t3#lo, $b, $b, #4 @ B4
|
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| 405 | veor $t1#lo, $t1#lo, $t1#hi @ t1 = (M) (P2 + P3) << 16
|
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| 406 | vand $t1#hi, $t1#hi, $k32
|
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| 407 | vmull.p8 $t3, $a, $t3#lo @ K = A*B4
|
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| 408 | veor $t2, $t2, $r @ N = I + J
|
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| 409 | veor $t0#lo, $t0#lo, $t0#hi
|
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| 410 | veor $t1#lo, $t1#lo, $t1#hi
|
|---|
| 411 | veor $t2#lo, $t2#lo, $t2#hi @ t2 = (N) (P4 + P5) << 24
|
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| 412 | vand $t2#hi, $t2#hi, $k16
|
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| 413 | vext.8 $t0, $t0, $t0, #15
|
|---|
| 414 | veor $t3#lo, $t3#lo, $t3#hi @ t3 = (K) (P6 + P7) << 32
|
|---|
| 415 | vmov.i64 $t3#hi, #0
|
|---|
| 416 | vext.8 $t1, $t1, $t1, #14
|
|---|
| 417 | veor $t2#lo, $t2#lo, $t2#hi
|
|---|
| 418 | vmull.p8 $r, $a, $b @ D = A*B
|
|---|
| 419 | vext.8 $t3, $t3, $t3, #12
|
|---|
| 420 | vext.8 $t2, $t2, $t2, #13
|
|---|
| 421 | veor $t0, $t0, $t1
|
|---|
| 422 | veor $t2, $t2, $t3
|
|---|
| 423 | veor $r, $r, $t0
|
|---|
| 424 | veor $r, $r, $t2
|
|---|
| 425 | ___
|
|---|
| 426 | }
|
|---|
| 427 |
|
|---|
| 428 | $code.=<<___;
|
|---|
| 429 | #if __ARM_MAX_ARCH__>=7
|
|---|
| 430 | .arch armv7-a
|
|---|
| 431 | .fpu neon
|
|---|
| 432 |
|
|---|
| 433 | .global gcm_init_neon
|
|---|
| 434 | .type gcm_init_neon,%function
|
|---|
| 435 | .align 4
|
|---|
| 436 | gcm_init_neon:
|
|---|
| 437 | vld1.64 $IN#hi,[r1]! @ load H
|
|---|
| 438 | vmov.i8 $t0,#0xe1
|
|---|
| 439 | vld1.64 $IN#lo,[r1]
|
|---|
| 440 | vshl.i64 $t0#hi,#57
|
|---|
| 441 | vshr.u64 $t0#lo,#63 @ t0=0xc2....01
|
|---|
| 442 | vdup.8 $t1,$IN#hi[7]
|
|---|
| 443 | vshr.u64 $Hlo,$IN#lo,#63
|
|---|
| 444 | vshr.s8 $t1,#7 @ broadcast carry bit
|
|---|
| 445 | vshl.i64 $IN,$IN,#1
|
|---|
| 446 | vand $t0,$t0,$t1
|
|---|
| 447 | vorr $IN#hi,$Hlo @ H<<<=1
|
|---|
| 448 | veor $IN,$IN,$t0 @ twisted H
|
|---|
| 449 | vstmia r0,{$IN}
|
|---|
| 450 |
|
|---|
| 451 | ret @ bx lr
|
|---|
| 452 | .size gcm_init_neon,.-gcm_init_neon
|
|---|
| 453 |
|
|---|
| 454 | .global gcm_gmult_neon
|
|---|
| 455 | .type gcm_gmult_neon,%function
|
|---|
| 456 | .align 4
|
|---|
| 457 | gcm_gmult_neon:
|
|---|
| 458 | vld1.64 $IN#hi,[$Xi]! @ load Xi
|
|---|
| 459 | vld1.64 $IN#lo,[$Xi]!
|
|---|
| 460 | vmov.i64 $k48,#0x0000ffffffffffff
|
|---|
| 461 | vldmia $Htbl,{$Hlo-$Hhi} @ load twisted H
|
|---|
| 462 | vmov.i64 $k32,#0x00000000ffffffff
|
|---|
| 463 | #ifdef __ARMEL__
|
|---|
| 464 | vrev64.8 $IN,$IN
|
|---|
| 465 | #endif
|
|---|
| 466 | vmov.i64 $k16,#0x000000000000ffff
|
|---|
| 467 | veor $Hhl,$Hlo,$Hhi @ Karatsuba pre-processing
|
|---|
| 468 | mov $len,#16
|
|---|
| 469 | b .Lgmult_neon
|
|---|
| 470 | .size gcm_gmult_neon,.-gcm_gmult_neon
|
|---|
| 471 |
|
|---|
| 472 | .global gcm_ghash_neon
|
|---|
| 473 | .type gcm_ghash_neon,%function
|
|---|
| 474 | .align 4
|
|---|
| 475 | gcm_ghash_neon:
|
|---|
| 476 | vld1.64 $Xl#hi,[$Xi]! @ load Xi
|
|---|
| 477 | vld1.64 $Xl#lo,[$Xi]!
|
|---|
| 478 | vmov.i64 $k48,#0x0000ffffffffffff
|
|---|
| 479 | vldmia $Htbl,{$Hlo-$Hhi} @ load twisted H
|
|---|
| 480 | vmov.i64 $k32,#0x00000000ffffffff
|
|---|
| 481 | #ifdef __ARMEL__
|
|---|
| 482 | vrev64.8 $Xl,$Xl
|
|---|
| 483 | #endif
|
|---|
| 484 | vmov.i64 $k16,#0x000000000000ffff
|
|---|
| 485 | veor $Hhl,$Hlo,$Hhi @ Karatsuba pre-processing
|
|---|
| 486 |
|
|---|
| 487 | .Loop_neon:
|
|---|
| 488 | vld1.64 $IN#hi,[$inp]! @ load inp
|
|---|
| 489 | vld1.64 $IN#lo,[$inp]!
|
|---|
| 490 | #ifdef __ARMEL__
|
|---|
| 491 | vrev64.8 $IN,$IN
|
|---|
| 492 | #endif
|
|---|
| 493 | veor $IN,$Xl @ inp^=Xi
|
|---|
| 494 | .Lgmult_neon:
|
|---|
| 495 | ___
|
|---|
| 496 | &clmul64x64 ($Xl,$Hlo,"$IN#lo"); # H.lo·Xi.lo
|
|---|
| 497 | $code.=<<___;
|
|---|
| 498 | veor $IN#lo,$IN#lo,$IN#hi @ Karatsuba pre-processing
|
|---|
| 499 | ___
|
|---|
| 500 | &clmul64x64 ($Xm,$Hhl,"$IN#lo"); # (H.lo+H.hi)·(Xi.lo+Xi.hi)
|
|---|
| 501 | &clmul64x64 ($Xh,$Hhi,"$IN#hi"); # H.hi·Xi.hi
|
|---|
| 502 | $code.=<<___;
|
|---|
| 503 | veor $Xm,$Xm,$Xl @ Karatsuba post-processing
|
|---|
| 504 | veor $Xm,$Xm,$Xh
|
|---|
| 505 | veor $Xl#hi,$Xl#hi,$Xm#lo
|
|---|
| 506 | veor $Xh#lo,$Xh#lo,$Xm#hi @ Xh|Xl - 256-bit result
|
|---|
| 507 |
|
|---|
| 508 | @ equivalent of reduction_avx from ghash-x86_64.pl
|
|---|
| 509 | vshl.i64 $t1,$Xl,#57 @ 1st phase
|
|---|
| 510 | vshl.i64 $t2,$Xl,#62
|
|---|
| 511 | veor $t2,$t2,$t1 @
|
|---|
| 512 | vshl.i64 $t1,$Xl,#63
|
|---|
| 513 | veor $t2, $t2, $t1 @
|
|---|
| 514 | veor $Xl#hi,$Xl#hi,$t2#lo @
|
|---|
| 515 | veor $Xh#lo,$Xh#lo,$t2#hi
|
|---|
| 516 |
|
|---|
| 517 | vshr.u64 $t2,$Xl,#1 @ 2nd phase
|
|---|
| 518 | veor $Xh,$Xh,$Xl
|
|---|
| 519 | veor $Xl,$Xl,$t2 @
|
|---|
| 520 | vshr.u64 $t2,$t2,#6
|
|---|
| 521 | vshr.u64 $Xl,$Xl,#1 @
|
|---|
| 522 | veor $Xl,$Xl,$Xh @
|
|---|
| 523 | veor $Xl,$Xl,$t2 @
|
|---|
| 524 |
|
|---|
| 525 | subs $len,#16
|
|---|
| 526 | bne .Loop_neon
|
|---|
| 527 |
|
|---|
| 528 | #ifdef __ARMEL__
|
|---|
| 529 | vrev64.8 $Xl,$Xl
|
|---|
| 530 | #endif
|
|---|
| 531 | sub $Xi,#16
|
|---|
| 532 | vst1.64 $Xl#hi,[$Xi]! @ write out Xi
|
|---|
| 533 | vst1.64 $Xl#lo,[$Xi]
|
|---|
| 534 |
|
|---|
| 535 | ret @ bx lr
|
|---|
| 536 | .size gcm_ghash_neon,.-gcm_ghash_neon
|
|---|
| 537 | #endif
|
|---|
| 538 | ___
|
|---|
| 539 | }
|
|---|
| 540 | $code.=<<___;
|
|---|
| 541 | .asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
|
|---|
| 542 | .align 2
|
|---|
| 543 | ___
|
|---|
| 544 |
|
|---|
| 545 | foreach (split("\n",$code)) {
|
|---|
| 546 | s/\`([^\`]*)\`/eval $1/geo;
|
|---|
| 547 |
|
|---|
| 548 | s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
|
|---|
| 549 | s/\bret\b/bx lr/go or
|
|---|
| 550 | s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
|
|---|
| 551 |
|
|---|
| 552 | print $_,"\n";
|
|---|
| 553 | }
|
|---|
| 554 | close STDOUT; # enforce flush
|
|---|
