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source: vbox/trunk/src/libs/openssl-1.1.0g/crypto/modes/asm/ghash-x86.pl@ 69881

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Update OpenSSL to 1.1.0g.
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1#! /usr/bin/env perl
2# Copyright 2010-2016 The OpenSSL Project Authors. All Rights Reserved.
3#
4# Licensed under the OpenSSL license (the "License"). You may not use
5# this file except in compliance with the License. You can obtain a copy
6# in the file LICENSE in the source distribution or at
7# https://www.openssl.org/source/license.html
8
9#
10# ====================================================================
11# Written by Andy Polyakov <[email protected]> for the OpenSSL
12# project. The module is, however, dual licensed under OpenSSL and
13# CRYPTOGAMS licenses depending on where you obtain it. For further
14# details see http://www.openssl.org/~appro/cryptogams/.
15# ====================================================================
16#
17# March, May, June 2010
18#
19# The module implements "4-bit" GCM GHASH function and underlying
20# single multiplication operation in GF(2^128). "4-bit" means that it
21# uses 256 bytes per-key table [+64/128 bytes fixed table]. It has two
22# code paths: vanilla x86 and vanilla SSE. Former will be executed on
23# 486 and Pentium, latter on all others. SSE GHASH features so called
24# "528B" variant of "4-bit" method utilizing additional 256+16 bytes
25# of per-key storage [+512 bytes shared table]. Performance results
26# are for streamed GHASH subroutine and are expressed in cycles per
27# processed byte, less is better:
28#
29# gcc 2.95.3(*) SSE assembler x86 assembler
30#
31# Pentium 105/111(**) - 50
32# PIII 68 /75 12.2 24
33# P4 125/125 17.8 84(***)
34# Opteron 66 /70 10.1 30
35# Core2 54 /67 8.4 18
36# Atom 105/105 16.8 53
37# VIA Nano 69 /71 13.0 27
38#
39# (*) gcc 3.4.x was observed to generate few percent slower code,
40# which is one of reasons why 2.95.3 results were chosen,
41# another reason is lack of 3.4.x results for older CPUs;
42# comparison with SSE results is not completely fair, because C
43# results are for vanilla "256B" implementation, while
44# assembler results are for "528B";-)
45# (**) second number is result for code compiled with -fPIC flag,
46# which is actually more relevant, because assembler code is
47# position-independent;
48# (***) see comment in non-MMX routine for further details;
49#
50# To summarize, it's >2-5 times faster than gcc-generated code. To
51# anchor it to something else SHA1 assembler processes one byte in
52# ~7 cycles on contemporary x86 cores. As for choice of MMX/SSE
53# in particular, see comment at the end of the file...
54
55# May 2010
56#
57# Add PCLMULQDQ version performing at 2.10 cycles per processed byte.
58# The question is how close is it to theoretical limit? The pclmulqdq
59# instruction latency appears to be 14 cycles and there can't be more
60# than 2 of them executing at any given time. This means that single
61# Karatsuba multiplication would take 28 cycles *plus* few cycles for
62# pre- and post-processing. Then multiplication has to be followed by
63# modulo-reduction. Given that aggregated reduction method [see
64# "Carry-less Multiplication and Its Usage for Computing the GCM Mode"
65# white paper by Intel] allows you to perform reduction only once in
66# a while we can assume that asymptotic performance can be estimated
67# as (28+Tmod/Naggr)/16, where Tmod is time to perform reduction
68# and Naggr is the aggregation factor.
69#
70# Before we proceed to this implementation let's have closer look at
71# the best-performing code suggested by Intel in their white paper.
72# By tracing inter-register dependencies Tmod is estimated as ~19
73# cycles and Naggr chosen by Intel is 4, resulting in 2.05 cycles per
74# processed byte. As implied, this is quite optimistic estimate,
75# because it does not account for Karatsuba pre- and post-processing,
76# which for a single multiplication is ~5 cycles. Unfortunately Intel
77# does not provide performance data for GHASH alone. But benchmarking
78# AES_GCM_encrypt ripped out of Fig. 15 of the white paper with aadt
79# alone resulted in 2.46 cycles per byte of out 16KB buffer. Note that
80# the result accounts even for pre-computing of degrees of the hash
81# key H, but its portion is negligible at 16KB buffer size.
82#
83# Moving on to the implementation in question. Tmod is estimated as
84# ~13 cycles and Naggr is 2, giving asymptotic performance of ...
85# 2.16. How is it possible that measured performance is better than
86# optimistic theoretical estimate? There is one thing Intel failed
87# to recognize. By serializing GHASH with CTR in same subroutine
88# former's performance is really limited to above (Tmul + Tmod/Naggr)
89# equation. But if GHASH procedure is detached, the modulo-reduction
90# can be interleaved with Naggr-1 multiplications at instruction level
91# and under ideal conditions even disappear from the equation. So that
92# optimistic theoretical estimate for this implementation is ...
93# 28/16=1.75, and not 2.16. Well, it's probably way too optimistic,
94# at least for such small Naggr. I'd argue that (28+Tproc/Naggr),
95# where Tproc is time required for Karatsuba pre- and post-processing,
96# is more realistic estimate. In this case it gives ... 1.91 cycles.
97# Or in other words, depending on how well we can interleave reduction
98# and one of the two multiplications the performance should be between
99# 1.91 and 2.16. As already mentioned, this implementation processes
100# one byte out of 8KB buffer in 2.10 cycles, while x86_64 counterpart
101# - in 2.02. x86_64 performance is better, because larger register
102# bank allows to interleave reduction and multiplication better.
103#
104# Does it make sense to increase Naggr? To start with it's virtually
105# impossible in 32-bit mode, because of limited register bank
106# capacity. Otherwise improvement has to be weighed agiainst slower
107# setup, as well as code size and complexity increase. As even
108# optimistic estimate doesn't promise 30% performance improvement,
109# there are currently no plans to increase Naggr.
110#
111# Special thanks to David Woodhouse <[email protected]> for
112# providing access to a Westmere-based system on behalf of Intel
113# Open Source Technology Centre.
114
115# January 2010
116#
117# Tweaked to optimize transitions between integer and FP operations
118# on same XMM register, PCLMULQDQ subroutine was measured to process
119# one byte in 2.07 cycles on Sandy Bridge, and in 2.12 - on Westmere.
120# The minor regression on Westmere is outweighed by ~15% improvement
121# on Sandy Bridge. Strangely enough attempt to modify 64-bit code in
122# similar manner resulted in almost 20% degradation on Sandy Bridge,
123# where original 64-bit code processes one byte in 1.95 cycles.
124
125#####################################################################
126# For reference, AMD Bulldozer processes one byte in 1.98 cycles in
127# 32-bit mode and 1.89 in 64-bit.
128
129# February 2013
130#
131# Overhaul: aggregate Karatsuba post-processing, improve ILP in
132# reduction_alg9. Resulting performance is 1.96 cycles per byte on
133# Westmere, 1.95 - on Sandy/Ivy Bridge, 1.76 - on Bulldozer.
134
135$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
136push(@INC,"${dir}","${dir}../../perlasm");
137require "x86asm.pl";
138
139$output=pop;
140open STDOUT,">$output";
141
142&asm_init($ARGV[0],"ghash-x86.pl",$x86only = $ARGV[$#ARGV] eq "386");
143
144$sse2=0;
145for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
146
147($Zhh,$Zhl,$Zlh,$Zll) = ("ebp","edx","ecx","ebx");
148$inp = "edi";
149$Htbl = "esi";
150
151
152$unroll = 0; # Affects x86 loop. Folded loop performs ~7% worse
153 # than unrolled, which has to be weighted against
154 # 2.5x x86-specific code size reduction.
155
156sub x86_loop {
157 my $off = shift;
158 my $rem = "eax";
159
160 &mov ($Zhh,&DWP(4,$Htbl,$Zll));
161 &mov ($Zhl,&DWP(0,$Htbl,$Zll));
162 &mov ($Zlh,&DWP(12,$Htbl,$Zll));
163 &mov ($Zll,&DWP(8,$Htbl,$Zll));
164 &xor ($rem,$rem); # avoid partial register stalls on PIII
165
166 # shrd practically kills P4, 2.5x deterioration, but P4 has
167 # MMX code-path to execute. shrd runs tad faster [than twice
168 # the shifts, move's and or's] on pre-MMX Pentium (as well as
169 # PIII and Core2), *but* minimizes code size, spares register
170 # and thus allows to fold the loop...
171 if (!$unroll) {
172 my $cnt = $inp;
173 &mov ($cnt,15);
174 &jmp (&label("x86_loop"));
175 &set_label("x86_loop",16);
176 for($i=1;$i<=2;$i++) {
177 &mov (&LB($rem),&LB($Zll));
178 &shrd ($Zll,$Zlh,4);
179 &and (&LB($rem),0xf);
180 &shrd ($Zlh,$Zhl,4);
181 &shrd ($Zhl,$Zhh,4);
182 &shr ($Zhh,4);
183 &xor ($Zhh,&DWP($off+16,"esp",$rem,4));
184
185 &mov (&LB($rem),&BP($off,"esp",$cnt));
186 if ($i&1) {
187 &and (&LB($rem),0xf0);
188 } else {
189 &shl (&LB($rem),4);
190 }
191
192 &xor ($Zll,&DWP(8,$Htbl,$rem));
193 &xor ($Zlh,&DWP(12,$Htbl,$rem));
194 &xor ($Zhl,&DWP(0,$Htbl,$rem));
195 &xor ($Zhh,&DWP(4,$Htbl,$rem));
196
197 if ($i&1) {
198 &dec ($cnt);
199 &js (&label("x86_break"));
200 } else {
201 &jmp (&label("x86_loop"));
202 }
203 }
204 &set_label("x86_break",16);
205 } else {
206 for($i=1;$i<32;$i++) {
207 &comment($i);
208 &mov (&LB($rem),&LB($Zll));
209 &shrd ($Zll,$Zlh,4);
210 &and (&LB($rem),0xf);
211 &shrd ($Zlh,$Zhl,4);
212 &shrd ($Zhl,$Zhh,4);
213 &shr ($Zhh,4);
214 &xor ($Zhh,&DWP($off+16,"esp",$rem,4));
215
216 if ($i&1) {
217 &mov (&LB($rem),&BP($off+15-($i>>1),"esp"));
218 &and (&LB($rem),0xf0);
219 } else {
220 &mov (&LB($rem),&BP($off+15-($i>>1),"esp"));
221 &shl (&LB($rem),4);
222 }
223
224 &xor ($Zll,&DWP(8,$Htbl,$rem));
225 &xor ($Zlh,&DWP(12,$Htbl,$rem));
226 &xor ($Zhl,&DWP(0,$Htbl,$rem));
227 &xor ($Zhh,&DWP(4,$Htbl,$rem));
228 }
229 }
230 &bswap ($Zll);
231 &bswap ($Zlh);
232 &bswap ($Zhl);
233 if (!$x86only) {
234 &bswap ($Zhh);
235 } else {
236 &mov ("eax",$Zhh);
237 &bswap ("eax");
238 &mov ($Zhh,"eax");
239 }
240}
241
242if ($unroll) {
243 &function_begin_B("_x86_gmult_4bit_inner");
244 &x86_loop(4);
245 &ret ();
246 &function_end_B("_x86_gmult_4bit_inner");
247}
248
249sub deposit_rem_4bit {
250 my $bias = shift;
251
252 &mov (&DWP($bias+0, "esp"),0x0000<<16);
253 &mov (&DWP($bias+4, "esp"),0x1C20<<16);
254 &mov (&DWP($bias+8, "esp"),0x3840<<16);
255 &mov (&DWP($bias+12,"esp"),0x2460<<16);
256 &mov (&DWP($bias+16,"esp"),0x7080<<16);
257 &mov (&DWP($bias+20,"esp"),0x6CA0<<16);
258 &mov (&DWP($bias+24,"esp"),0x48C0<<16);
259 &mov (&DWP($bias+28,"esp"),0x54E0<<16);
260 &mov (&DWP($bias+32,"esp"),0xE100<<16);
261 &mov (&DWP($bias+36,"esp"),0xFD20<<16);
262 &mov (&DWP($bias+40,"esp"),0xD940<<16);
263 &mov (&DWP($bias+44,"esp"),0xC560<<16);
264 &mov (&DWP($bias+48,"esp"),0x9180<<16);
265 &mov (&DWP($bias+52,"esp"),0x8DA0<<16);
266 &mov (&DWP($bias+56,"esp"),0xA9C0<<16);
267 &mov (&DWP($bias+60,"esp"),0xB5E0<<16);
268}
269
270
271$suffix = $x86only ? "" : "_x86";
272
273&function_begin("gcm_gmult_4bit".$suffix);
274 &stack_push(16+4+1); # +1 for stack alignment
275 &mov ($inp,&wparam(0)); # load Xi
276 &mov ($Htbl,&wparam(1)); # load Htable
277
278 &mov ($Zhh,&DWP(0,$inp)); # load Xi[16]
279 &mov ($Zhl,&DWP(4,$inp));
280 &mov ($Zlh,&DWP(8,$inp));
281 &mov ($Zll,&DWP(12,$inp));
282
283 &deposit_rem_4bit(16);
284
285 &mov (&DWP(0,"esp"),$Zhh); # copy Xi[16] on stack
286 &mov (&DWP(4,"esp"),$Zhl);
287 &mov (&DWP(8,"esp"),$Zlh);
288 &mov (&DWP(12,"esp"),$Zll);
289 &shr ($Zll,20);
290 &and ($Zll,0xf0);
291
292 if ($unroll) {
293 &call ("_x86_gmult_4bit_inner");
294 } else {
295 &x86_loop(0);
296 &mov ($inp,&wparam(0));
297 }
298
299 &mov (&DWP(12,$inp),$Zll);
300 &mov (&DWP(8,$inp),$Zlh);
301 &mov (&DWP(4,$inp),$Zhl);
302 &mov (&DWP(0,$inp),$Zhh);
303 &stack_pop(16+4+1);
304&function_end("gcm_gmult_4bit".$suffix);
305
306&function_begin("gcm_ghash_4bit".$suffix);
307 &stack_push(16+4+1); # +1 for 64-bit alignment
308 &mov ($Zll,&wparam(0)); # load Xi
309 &mov ($Htbl,&wparam(1)); # load Htable
310 &mov ($inp,&wparam(2)); # load in
311 &mov ("ecx",&wparam(3)); # load len
312 &add ("ecx",$inp);
313 &mov (&wparam(3),"ecx");
314
315 &mov ($Zhh,&DWP(0,$Zll)); # load Xi[16]
316 &mov ($Zhl,&DWP(4,$Zll));
317 &mov ($Zlh,&DWP(8,$Zll));
318 &mov ($Zll,&DWP(12,$Zll));
319
320 &deposit_rem_4bit(16);
321
322 &set_label("x86_outer_loop",16);
323 &xor ($Zll,&DWP(12,$inp)); # xor with input
324 &xor ($Zlh,&DWP(8,$inp));
325 &xor ($Zhl,&DWP(4,$inp));
326 &xor ($Zhh,&DWP(0,$inp));
327 &mov (&DWP(12,"esp"),$Zll); # dump it on stack
328 &mov (&DWP(8,"esp"),$Zlh);
329 &mov (&DWP(4,"esp"),$Zhl);
330 &mov (&DWP(0,"esp"),$Zhh);
331
332 &shr ($Zll,20);
333 &and ($Zll,0xf0);
334
335 if ($unroll) {
336 &call ("_x86_gmult_4bit_inner");
337 } else {
338 &x86_loop(0);
339 &mov ($inp,&wparam(2));
340 }
341 &lea ($inp,&DWP(16,$inp));
342 &cmp ($inp,&wparam(3));
343 &mov (&wparam(2),$inp) if (!$unroll);
344 &jb (&label("x86_outer_loop"));
345
346 &mov ($inp,&wparam(0)); # load Xi
347 &mov (&DWP(12,$inp),$Zll);
348 &mov (&DWP(8,$inp),$Zlh);
349 &mov (&DWP(4,$inp),$Zhl);
350 &mov (&DWP(0,$inp),$Zhh);
351 &stack_pop(16+4+1);
352&function_end("gcm_ghash_4bit".$suffix);
353
354
355if (!$x86only) {{{
356
357&static_label("rem_4bit");
358
359if (!$sse2) {{ # pure-MMX "May" version...
360
361$S=12; # shift factor for rem_4bit
362
363&function_begin_B("_mmx_gmult_4bit_inner");
364# MMX version performs 3.5 times better on P4 (see comment in non-MMX
365# routine for further details), 100% better on Opteron, ~70% better
366# on Core2 and PIII... In other words effort is considered to be well
367# spent... Since initial release the loop was unrolled in order to
368# "liberate" register previously used as loop counter. Instead it's
369# used to optimize critical path in 'Z.hi ^= rem_4bit[Z.lo&0xf]'.
370# The path involves move of Z.lo from MMX to integer register,
371# effective address calculation and finally merge of value to Z.hi.
372# Reference to rem_4bit is scheduled so late that I had to >>4
373# rem_4bit elements. This resulted in 20-45% procent improvement
374# on contemporary µ-archs.
375{
376 my $cnt;
377 my $rem_4bit = "eax";
378 my @rem = ($Zhh,$Zll);
379 my $nhi = $Zhl;
380 my $nlo = $Zlh;
381
382 my ($Zlo,$Zhi) = ("mm0","mm1");
383 my $tmp = "mm2";
384
385 &xor ($nlo,$nlo); # avoid partial register stalls on PIII
386 &mov ($nhi,$Zll);
387 &mov (&LB($nlo),&LB($nhi));
388 &shl (&LB($nlo),4);
389 &and ($nhi,0xf0);
390 &movq ($Zlo,&QWP(8,$Htbl,$nlo));
391 &movq ($Zhi,&QWP(0,$Htbl,$nlo));
392 &movd ($rem[0],$Zlo);
393
394 for ($cnt=28;$cnt>=-2;$cnt--) {
395 my $odd = $cnt&1;
396 my $nix = $odd ? $nlo : $nhi;
397
398 &shl (&LB($nlo),4) if ($odd);
399 &psrlq ($Zlo,4);
400 &movq ($tmp,$Zhi);
401 &psrlq ($Zhi,4);
402 &pxor ($Zlo,&QWP(8,$Htbl,$nix));
403 &mov (&LB($nlo),&BP($cnt/2,$inp)) if (!$odd && $cnt>=0);
404 &psllq ($tmp,60);
405 &and ($nhi,0xf0) if ($odd);
406 &pxor ($Zhi,&QWP(0,$rem_4bit,$rem[1],8)) if ($cnt<28);
407 &and ($rem[0],0xf);
408 &pxor ($Zhi,&QWP(0,$Htbl,$nix));
409 &mov ($nhi,$nlo) if (!$odd && $cnt>=0);
410 &movd ($rem[1],$Zlo);
411 &pxor ($Zlo,$tmp);
412
413 push (@rem,shift(@rem)); # "rotate" registers
414 }
415
416 &mov ($inp,&DWP(4,$rem_4bit,$rem[1],8)); # last rem_4bit[rem]
417
418 &psrlq ($Zlo,32); # lower part of Zlo is already there
419 &movd ($Zhl,$Zhi);
420 &psrlq ($Zhi,32);
421 &movd ($Zlh,$Zlo);
422 &movd ($Zhh,$Zhi);
423 &shl ($inp,4); # compensate for rem_4bit[i] being >>4
424
425 &bswap ($Zll);
426 &bswap ($Zhl);
427 &bswap ($Zlh);
428 &xor ($Zhh,$inp);
429 &bswap ($Zhh);
430
431 &ret ();
432}
433&function_end_B("_mmx_gmult_4bit_inner");
434
435&function_begin("gcm_gmult_4bit_mmx");
436 &mov ($inp,&wparam(0)); # load Xi
437 &mov ($Htbl,&wparam(1)); # load Htable
438
439 &call (&label("pic_point"));
440 &set_label("pic_point");
441 &blindpop("eax");
442 &lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
443
444 &movz ($Zll,&BP(15,$inp));
445
446 &call ("_mmx_gmult_4bit_inner");
447
448 &mov ($inp,&wparam(0)); # load Xi
449 &emms ();
450 &mov (&DWP(12,$inp),$Zll);
451 &mov (&DWP(4,$inp),$Zhl);
452 &mov (&DWP(8,$inp),$Zlh);
453 &mov (&DWP(0,$inp),$Zhh);
454&function_end("gcm_gmult_4bit_mmx");
455
456
457# Streamed version performs 20% better on P4, 7% on Opteron,
458# 10% on Core2 and PIII...
459&function_begin("gcm_ghash_4bit_mmx");
460 &mov ($Zhh,&wparam(0)); # load Xi
461 &mov ($Htbl,&wparam(1)); # load Htable
462 &mov ($inp,&wparam(2)); # load in
463 &mov ($Zlh,&wparam(3)); # load len
464
465 &call (&label("pic_point"));
466 &set_label("pic_point");
467 &blindpop("eax");
468 &lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
469
470 &add ($Zlh,$inp);
471 &mov (&wparam(3),$Zlh); # len to point at the end of input
472 &stack_push(4+1); # +1 for stack alignment
473
474 &mov ($Zll,&DWP(12,$Zhh)); # load Xi[16]
475 &mov ($Zhl,&DWP(4,$Zhh));
476 &mov ($Zlh,&DWP(8,$Zhh));
477 &mov ($Zhh,&DWP(0,$Zhh));
478 &jmp (&label("mmx_outer_loop"));
479
480 &set_label("mmx_outer_loop",16);
481 &xor ($Zll,&DWP(12,$inp));
482 &xor ($Zhl,&DWP(4,$inp));
483 &xor ($Zlh,&DWP(8,$inp));
484 &xor ($Zhh,&DWP(0,$inp));
485 &mov (&wparam(2),$inp);
486 &mov (&DWP(12,"esp"),$Zll);
487 &mov (&DWP(4,"esp"),$Zhl);
488 &mov (&DWP(8,"esp"),$Zlh);
489 &mov (&DWP(0,"esp"),$Zhh);
490
491 &mov ($inp,"esp");
492 &shr ($Zll,24);
493
494 &call ("_mmx_gmult_4bit_inner");
495
496 &mov ($inp,&wparam(2));
497 &lea ($inp,&DWP(16,$inp));
498 &cmp ($inp,&wparam(3));
499 &jb (&label("mmx_outer_loop"));
500
501 &mov ($inp,&wparam(0)); # load Xi
502 &emms ();
503 &mov (&DWP(12,$inp),$Zll);
504 &mov (&DWP(4,$inp),$Zhl);
505 &mov (&DWP(8,$inp),$Zlh);
506 &mov (&DWP(0,$inp),$Zhh);
507
508 &stack_pop(4+1);
509&function_end("gcm_ghash_4bit_mmx");
510
511
512}} else {{ # "June" MMX version...
513 # ... has slower "April" gcm_gmult_4bit_mmx with folded
514 # loop. This is done to conserve code size...
515$S=16; # shift factor for rem_4bit
516
517sub mmx_loop() {
518# MMX version performs 2.8 times better on P4 (see comment in non-MMX
519# routine for further details), 40% better on Opteron and Core2, 50%
520# better on PIII... In other words effort is considered to be well
521# spent...
522 my $inp = shift;
523 my $rem_4bit = shift;
524 my $cnt = $Zhh;
525 my $nhi = $Zhl;
526 my $nlo = $Zlh;
527 my $rem = $Zll;
528
529 my ($Zlo,$Zhi) = ("mm0","mm1");
530 my $tmp = "mm2";
531
532 &xor ($nlo,$nlo); # avoid partial register stalls on PIII
533 &mov ($nhi,$Zll);
534 &mov (&LB($nlo),&LB($nhi));
535 &mov ($cnt,14);
536 &shl (&LB($nlo),4);
537 &and ($nhi,0xf0);
538 &movq ($Zlo,&QWP(8,$Htbl,$nlo));
539 &movq ($Zhi,&QWP(0,$Htbl,$nlo));
540 &movd ($rem,$Zlo);
541 &jmp (&label("mmx_loop"));
542
543 &set_label("mmx_loop",16);
544 &psrlq ($Zlo,4);
545 &and ($rem,0xf);
546 &movq ($tmp,$Zhi);
547 &psrlq ($Zhi,4);
548 &pxor ($Zlo,&QWP(8,$Htbl,$nhi));
549 &mov (&LB($nlo),&BP(0,$inp,$cnt));
550 &psllq ($tmp,60);
551 &pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
552 &dec ($cnt);
553 &movd ($rem,$Zlo);
554 &pxor ($Zhi,&QWP(0,$Htbl,$nhi));
555 &mov ($nhi,$nlo);
556 &pxor ($Zlo,$tmp);
557 &js (&label("mmx_break"));
558
559 &shl (&LB($nlo),4);
560 &and ($rem,0xf);
561 &psrlq ($Zlo,4);
562 &and ($nhi,0xf0);
563 &movq ($tmp,$Zhi);
564 &psrlq ($Zhi,4);
565 &pxor ($Zlo,&QWP(8,$Htbl,$nlo));
566 &psllq ($tmp,60);
567 &pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
568 &movd ($rem,$Zlo);
569 &pxor ($Zhi,&QWP(0,$Htbl,$nlo));
570 &pxor ($Zlo,$tmp);
571 &jmp (&label("mmx_loop"));
572
573 &set_label("mmx_break",16);
574 &shl (&LB($nlo),4);
575 &and ($rem,0xf);
576 &psrlq ($Zlo,4);
577 &and ($nhi,0xf0);
578 &movq ($tmp,$Zhi);
579 &psrlq ($Zhi,4);
580 &pxor ($Zlo,&QWP(8,$Htbl,$nlo));
581 &psllq ($tmp,60);
582 &pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
583 &movd ($rem,$Zlo);
584 &pxor ($Zhi,&QWP(0,$Htbl,$nlo));
585 &pxor ($Zlo,$tmp);
586
587 &psrlq ($Zlo,4);
588 &and ($rem,0xf);
589 &movq ($tmp,$Zhi);
590 &psrlq ($Zhi,4);
591 &pxor ($Zlo,&QWP(8,$Htbl,$nhi));
592 &psllq ($tmp,60);
593 &pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
594 &movd ($rem,$Zlo);
595 &pxor ($Zhi,&QWP(0,$Htbl,$nhi));
596 &pxor ($Zlo,$tmp);
597
598 &psrlq ($Zlo,32); # lower part of Zlo is already there
599 &movd ($Zhl,$Zhi);
600 &psrlq ($Zhi,32);
601 &movd ($Zlh,$Zlo);
602 &movd ($Zhh,$Zhi);
603
604 &bswap ($Zll);
605 &bswap ($Zhl);
606 &bswap ($Zlh);
607 &bswap ($Zhh);
608}
609
610&function_begin("gcm_gmult_4bit_mmx");
611 &mov ($inp,&wparam(0)); # load Xi
612 &mov ($Htbl,&wparam(1)); # load Htable
613
614 &call (&label("pic_point"));
615 &set_label("pic_point");
616 &blindpop("eax");
617 &lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
618
619 &movz ($Zll,&BP(15,$inp));
620
621 &mmx_loop($inp,"eax");
622
623 &emms ();
624 &mov (&DWP(12,$inp),$Zll);
625 &mov (&DWP(4,$inp),$Zhl);
626 &mov (&DWP(8,$inp),$Zlh);
627 &mov (&DWP(0,$inp),$Zhh);
628&function_end("gcm_gmult_4bit_mmx");
629
630
631######################################################################
632# Below subroutine is "528B" variant of "4-bit" GCM GHASH function
633# (see gcm128.c for details). It provides further 20-40% performance
634# improvement over above mentioned "May" version.
635
636&static_label("rem_8bit");
637
638&function_begin("gcm_ghash_4bit_mmx");
639{ my ($Zlo,$Zhi) = ("mm7","mm6");
640 my $rem_8bit = "esi";
641 my $Htbl = "ebx";
642
643 # parameter block
644 &mov ("eax",&wparam(0)); # Xi
645 &mov ("ebx",&wparam(1)); # Htable
646 &mov ("ecx",&wparam(2)); # inp
647 &mov ("edx",&wparam(3)); # len
648 &mov ("ebp","esp"); # original %esp
649 &call (&label("pic_point"));
650 &set_label ("pic_point");
651 &blindpop ($rem_8bit);
652 &lea ($rem_8bit,&DWP(&label("rem_8bit")."-".&label("pic_point"),$rem_8bit));
653
654 &sub ("esp",512+16+16); # allocate stack frame...
655 &and ("esp",-64); # ...and align it
656 &sub ("esp",16); # place for (u8)(H[]<<4)
657
658 &add ("edx","ecx"); # pointer to the end of input
659 &mov (&DWP(528+16+0,"esp"),"eax"); # save Xi
660 &mov (&DWP(528+16+8,"esp"),"edx"); # save inp+len
661 &mov (&DWP(528+16+12,"esp"),"ebp"); # save original %esp
662
663 { my @lo = ("mm0","mm1","mm2");
664 my @hi = ("mm3","mm4","mm5");
665 my @tmp = ("mm6","mm7");
666 my ($off1,$off2,$i) = (0,0,);
667
668 &add ($Htbl,128); # optimize for size
669 &lea ("edi",&DWP(16+128,"esp"));
670 &lea ("ebp",&DWP(16+256+128,"esp"));
671
672 # decompose Htable (low and high parts are kept separately),
673 # generate Htable[]>>4, (u8)(Htable[]<<4), save to stack...
674 for ($i=0;$i<18;$i++) {
675
676 &mov ("edx",&DWP(16*$i+8-128,$Htbl)) if ($i<16);
677 &movq ($lo[0],&QWP(16*$i+8-128,$Htbl)) if ($i<16);
678 &psllq ($tmp[1],60) if ($i>1);
679 &movq ($hi[0],&QWP(16*$i+0-128,$Htbl)) if ($i<16);
680 &por ($lo[2],$tmp[1]) if ($i>1);
681 &movq (&QWP($off1-128,"edi"),$lo[1]) if ($i>0 && $i<17);
682 &psrlq ($lo[1],4) if ($i>0 && $i<17);
683 &movq (&QWP($off1,"edi"),$hi[1]) if ($i>0 && $i<17);
684 &movq ($tmp[0],$hi[1]) if ($i>0 && $i<17);
685 &movq (&QWP($off2-128,"ebp"),$lo[2]) if ($i>1);
686 &psrlq ($hi[1],4) if ($i>0 && $i<17);
687 &movq (&QWP($off2,"ebp"),$hi[2]) if ($i>1);
688 &shl ("edx",4) if ($i<16);
689 &mov (&BP($i,"esp"),&LB("edx")) if ($i<16);
690
691 unshift (@lo,pop(@lo)); # "rotate" registers
692 unshift (@hi,pop(@hi));
693 unshift (@tmp,pop(@tmp));
694 $off1 += 8 if ($i>0);
695 $off2 += 8 if ($i>1);
696 }
697 }
698
699 &movq ($Zhi,&QWP(0,"eax"));
700 &mov ("ebx",&DWP(8,"eax"));
701 &mov ("edx",&DWP(12,"eax")); # load Xi
702
703&set_label("outer",16);
704 { my $nlo = "eax";
705 my $dat = "edx";
706 my @nhi = ("edi","ebp");
707 my @rem = ("ebx","ecx");
708 my @red = ("mm0","mm1","mm2");
709 my $tmp = "mm3";
710
711 &xor ($dat,&DWP(12,"ecx")); # merge input data
712 &xor ("ebx",&DWP(8,"ecx"));
713 &pxor ($Zhi,&QWP(0,"ecx"));
714 &lea ("ecx",&DWP(16,"ecx")); # inp+=16
715 #&mov (&DWP(528+12,"esp"),$dat); # save inp^Xi
716 &mov (&DWP(528+8,"esp"),"ebx");
717 &movq (&QWP(528+0,"esp"),$Zhi);
718 &mov (&DWP(528+16+4,"esp"),"ecx"); # save inp
719
720 &xor ($nlo,$nlo);
721 &rol ($dat,8);
722 &mov (&LB($nlo),&LB($dat));
723 &mov ($nhi[1],$nlo);
724 &and (&LB($nlo),0x0f);
725 &shr ($nhi[1],4);
726 &pxor ($red[0],$red[0]);
727 &rol ($dat,8); # next byte
728 &pxor ($red[1],$red[1]);
729 &pxor ($red[2],$red[2]);
730
731 # Just like in "May" version modulo-schedule for critical path in
732 # 'Z.hi ^= rem_8bit[Z.lo&0xff^((u8)H[nhi]<<4)]<<48'. Final 'pxor'
733 # is scheduled so late that rem_8bit[] has to be shifted *right*
734 # by 16, which is why last argument to pinsrw is 2, which
735 # corresponds to <<32=<<48>>16...
736 for ($j=11,$i=0;$i<15;$i++) {
737
738 if ($i>0) {
739 &pxor ($Zlo,&QWP(16,"esp",$nlo,8)); # Z^=H[nlo]
740 &rol ($dat,8); # next byte
741 &pxor ($Zhi,&QWP(16+128,"esp",$nlo,8));
742
743 &pxor ($Zlo,$tmp);
744 &pxor ($Zhi,&QWP(16+256+128,"esp",$nhi[0],8));
745 &xor (&LB($rem[1]),&BP(0,"esp",$nhi[0])); # rem^(H[nhi]<<4)
746 } else {
747 &movq ($Zlo,&QWP(16,"esp",$nlo,8));
748 &movq ($Zhi,&QWP(16+128,"esp",$nlo,8));
749 }
750
751 &mov (&LB($nlo),&LB($dat));
752 &mov ($dat,&DWP(528+$j,"esp")) if (--$j%4==0);
753
754 &movd ($rem[0],$Zlo);
755 &movz ($rem[1],&LB($rem[1])) if ($i>0);
756 &psrlq ($Zlo,8); # Z>>=8
757
758 &movq ($tmp,$Zhi);
759 &mov ($nhi[0],$nlo);
760 &psrlq ($Zhi,8);
761
762 &pxor ($Zlo,&QWP(16+256+0,"esp",$nhi[1],8)); # Z^=H[nhi]>>4
763 &and (&LB($nlo),0x0f);
764 &psllq ($tmp,56);
765
766 &pxor ($Zhi,$red[1]) if ($i>1);
767 &shr ($nhi[0],4);
768 &pinsrw ($red[0],&WP(0,$rem_8bit,$rem[1],2),2) if ($i>0);
769
770 unshift (@red,pop(@red)); # "rotate" registers
771 unshift (@rem,pop(@rem));
772 unshift (@nhi,pop(@nhi));
773 }
774
775 &pxor ($Zlo,&QWP(16,"esp",$nlo,8)); # Z^=H[nlo]
776 &pxor ($Zhi,&QWP(16+128,"esp",$nlo,8));
777 &xor (&LB($rem[1]),&BP(0,"esp",$nhi[0])); # rem^(H[nhi]<<4)
778
779 &pxor ($Zlo,$tmp);
780 &pxor ($Zhi,&QWP(16+256+128,"esp",$nhi[0],8));
781 &movz ($rem[1],&LB($rem[1]));
782
783 &pxor ($red[2],$red[2]); # clear 2nd word
784 &psllq ($red[1],4);
785
786 &movd ($rem[0],$Zlo);
787 &psrlq ($Zlo,4); # Z>>=4
788
789 &movq ($tmp,$Zhi);
790 &psrlq ($Zhi,4);
791 &shl ($rem[0],4); # rem<<4
792
793 &pxor ($Zlo,&QWP(16,"esp",$nhi[1],8)); # Z^=H[nhi]
794 &psllq ($tmp,60);
795 &movz ($rem[0],&LB($rem[0]));
796
797 &pxor ($Zlo,$tmp);
798 &pxor ($Zhi,&QWP(16+128,"esp",$nhi[1],8));
799
800 &pinsrw ($red[0],&WP(0,$rem_8bit,$rem[1],2),2);
801 &pxor ($Zhi,$red[1]);
802
803 &movd ($dat,$Zlo);
804 &pinsrw ($red[2],&WP(0,$rem_8bit,$rem[0],2),3); # last is <<48
805
806 &psllq ($red[0],12); # correct by <<16>>4
807 &pxor ($Zhi,$red[0]);
808 &psrlq ($Zlo,32);
809 &pxor ($Zhi,$red[2]);
810
811 &mov ("ecx",&DWP(528+16+4,"esp")); # restore inp
812 &movd ("ebx",$Zlo);
813 &movq ($tmp,$Zhi); # 01234567
814 &psllw ($Zhi,8); # 1.3.5.7.
815 &psrlw ($tmp,8); # .0.2.4.6
816 &por ($Zhi,$tmp); # 10325476
817 &bswap ($dat);
818 &pshufw ($Zhi,$Zhi,0b00011011); # 76543210
819 &bswap ("ebx");
820
821 &cmp ("ecx",&DWP(528+16+8,"esp")); # are we done?
822 &jne (&label("outer"));
823 }
824
825 &mov ("eax",&DWP(528+16+0,"esp")); # restore Xi
826 &mov (&DWP(12,"eax"),"edx");
827 &mov (&DWP(8,"eax"),"ebx");
828 &movq (&QWP(0,"eax"),$Zhi);
829
830 &mov ("esp",&DWP(528+16+12,"esp")); # restore original %esp
831 &emms ();
832}
833&function_end("gcm_ghash_4bit_mmx");
834}}
835
836
837if ($sse2) {{
838######################################################################
839# PCLMULQDQ version.
840
841$Xip="eax";
842$Htbl="edx";
843$const="ecx";
844$inp="esi";
845$len="ebx";
846
847($Xi,$Xhi)=("xmm0","xmm1"); $Hkey="xmm2";
848($T1,$T2,$T3)=("xmm3","xmm4","xmm5");
849($Xn,$Xhn)=("xmm6","xmm7");
850
851&static_label("bswap");
852
853sub clmul64x64_T2 { # minimal "register" pressure
854my ($Xhi,$Xi,$Hkey,$HK)=@_;
855
856 &movdqa ($Xhi,$Xi); #
857 &pshufd ($T1,$Xi,0b01001110);
858 &pshufd ($T2,$Hkey,0b01001110) if (!defined($HK));
859 &pxor ($T1,$Xi); #
860 &pxor ($T2,$Hkey) if (!defined($HK));
861 $HK=$T2 if (!defined($HK));
862
863 &pclmulqdq ($Xi,$Hkey,0x00); #######
864 &pclmulqdq ($Xhi,$Hkey,0x11); #######
865 &pclmulqdq ($T1,$HK,0x00); #######
866 &xorps ($T1,$Xi); #
867 &xorps ($T1,$Xhi); #
868
869 &movdqa ($T2,$T1); #
870 &psrldq ($T1,8);
871 &pslldq ($T2,8); #
872 &pxor ($Xhi,$T1);
873 &pxor ($Xi,$T2); #
874}
875
876sub clmul64x64_T3 {
877# Even though this subroutine offers visually better ILP, it
878# was empirically found to be a tad slower than above version.
879# At least in gcm_ghash_clmul context. But it's just as well,
880# because loop modulo-scheduling is possible only thanks to
881# minimized "register" pressure...
882my ($Xhi,$Xi,$Hkey)=@_;
883
884 &movdqa ($T1,$Xi); #
885 &movdqa ($Xhi,$Xi);
886 &pclmulqdq ($Xi,$Hkey,0x00); #######
887 &pclmulqdq ($Xhi,$Hkey,0x11); #######
888 &pshufd ($T2,$T1,0b01001110); #
889 &pshufd ($T3,$Hkey,0b01001110);
890 &pxor ($T2,$T1); #
891 &pxor ($T3,$Hkey);
892 &pclmulqdq ($T2,$T3,0x00); #######
893 &pxor ($T2,$Xi); #
894 &pxor ($T2,$Xhi); #
895
896 &movdqa ($T3,$T2); #
897 &psrldq ($T2,8);
898 &pslldq ($T3,8); #
899 &pxor ($Xhi,$T2);
900 &pxor ($Xi,$T3); #
901}
902
903
904if (1) { # Algorithm 9 with <<1 twist.
905 # Reduction is shorter and uses only two
906 # temporary registers, which makes it better
907 # candidate for interleaving with 64x64
908 # multiplication. Pre-modulo-scheduled loop
909 # was found to be ~20% faster than Algorithm 5
910 # below. Algorithm 9 was therefore chosen for
911 # further optimization...
912
913sub reduction_alg9 { # 17/11 times faster than Intel version
914my ($Xhi,$Xi) = @_;
915
916 # 1st phase
917 &movdqa ($T2,$Xi); #
918 &movdqa ($T1,$Xi);
919 &psllq ($Xi,5);
920 &pxor ($T1,$Xi); #
921 &psllq ($Xi,1);
922 &pxor ($Xi,$T1); #
923 &psllq ($Xi,57); #
924 &movdqa ($T1,$Xi); #
925 &pslldq ($Xi,8);
926 &psrldq ($T1,8); #
927 &pxor ($Xi,$T2);
928 &pxor ($Xhi,$T1); #
929
930 # 2nd phase
931 &movdqa ($T2,$Xi);
932 &psrlq ($Xi,1);
933 &pxor ($Xhi,$T2); #
934 &pxor ($T2,$Xi);
935 &psrlq ($Xi,5);
936 &pxor ($Xi,$T2); #
937 &psrlq ($Xi,1); #
938 &pxor ($Xi,$Xhi) #
939}
940
941&function_begin_B("gcm_init_clmul");
942 &mov ($Htbl,&wparam(0));
943 &mov ($Xip,&wparam(1));
944
945 &call (&label("pic"));
946&set_label("pic");
947 &blindpop ($const);
948 &lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
949
950 &movdqu ($Hkey,&QWP(0,$Xip));
951 &pshufd ($Hkey,$Hkey,0b01001110);# dword swap
952
953 # <<1 twist
954 &pshufd ($T2,$Hkey,0b11111111); # broadcast uppermost dword
955 &movdqa ($T1,$Hkey);
956 &psllq ($Hkey,1);
957 &pxor ($T3,$T3); #
958 &psrlq ($T1,63);
959 &pcmpgtd ($T3,$T2); # broadcast carry bit
960 &pslldq ($T1,8);
961 &por ($Hkey,$T1); # H<<=1
962
963 # magic reduction
964 &pand ($T3,&QWP(16,$const)); # 0x1c2_polynomial
965 &pxor ($Hkey,$T3); # if(carry) H^=0x1c2_polynomial
966
967 # calculate H^2
968 &movdqa ($Xi,$Hkey);
969 &clmul64x64_T2 ($Xhi,$Xi,$Hkey);
970 &reduction_alg9 ($Xhi,$Xi);
971
972 &pshufd ($T1,$Hkey,0b01001110);
973 &pshufd ($T2,$Xi,0b01001110);
974 &pxor ($T1,$Hkey); # Karatsuba pre-processing
975 &movdqu (&QWP(0,$Htbl),$Hkey); # save H
976 &pxor ($T2,$Xi); # Karatsuba pre-processing
977 &movdqu (&QWP(16,$Htbl),$Xi); # save H^2
978 &palignr ($T2,$T1,8); # low part is H.lo^H.hi
979 &movdqu (&QWP(32,$Htbl),$T2); # save Karatsuba "salt"
980
981 &ret ();
982&function_end_B("gcm_init_clmul");
983
984&function_begin_B("gcm_gmult_clmul");
985 &mov ($Xip,&wparam(0));
986 &mov ($Htbl,&wparam(1));
987
988 &call (&label("pic"));
989&set_label("pic");
990 &blindpop ($const);
991 &lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
992
993 &movdqu ($Xi,&QWP(0,$Xip));
994 &movdqa ($T3,&QWP(0,$const));
995 &movups ($Hkey,&QWP(0,$Htbl));
996 &pshufb ($Xi,$T3);
997 &movups ($T2,&QWP(32,$Htbl));
998
999 &clmul64x64_T2 ($Xhi,$Xi,$Hkey,$T2);
1000 &reduction_alg9 ($Xhi,$Xi);
1001
1002 &pshufb ($Xi,$T3);
1003 &movdqu (&QWP(0,$Xip),$Xi);
1004
1005 &ret ();
1006&function_end_B("gcm_gmult_clmul");
1007
1008&function_begin("gcm_ghash_clmul");
1009 &mov ($Xip,&wparam(0));
1010 &mov ($Htbl,&wparam(1));
1011 &mov ($inp,&wparam(2));
1012 &mov ($len,&wparam(3));
1013
1014 &call (&label("pic"));
1015&set_label("pic");
1016 &blindpop ($const);
1017 &lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1018
1019 &movdqu ($Xi,&QWP(0,$Xip));
1020 &movdqa ($T3,&QWP(0,$const));
1021 &movdqu ($Hkey,&QWP(0,$Htbl));
1022 &pshufb ($Xi,$T3);
1023
1024 &sub ($len,0x10);
1025 &jz (&label("odd_tail"));
1026
1027 #######
1028 # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
1029 # [(H*Ii+1) + (H*Xi+1)] mod P =
1030 # [(H*Ii+1) + H^2*(Ii+Xi)] mod P
1031 #
1032 &movdqu ($T1,&QWP(0,$inp)); # Ii
1033 &movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1034 &pshufb ($T1,$T3);
1035 &pshufb ($Xn,$T3);
1036 &movdqu ($T3,&QWP(32,$Htbl));
1037 &pxor ($Xi,$T1); # Ii+Xi
1038
1039 &pshufd ($T1,$Xn,0b01001110); # H*Ii+1
1040 &movdqa ($Xhn,$Xn);
1041 &pxor ($T1,$Xn); #
1042 &lea ($inp,&DWP(32,$inp)); # i+=2
1043
1044 &pclmulqdq ($Xn,$Hkey,0x00); #######
1045 &pclmulqdq ($Xhn,$Hkey,0x11); #######
1046 &pclmulqdq ($T1,$T3,0x00); #######
1047 &movups ($Hkey,&QWP(16,$Htbl)); # load H^2
1048 &nop ();
1049
1050 &sub ($len,0x20);
1051 &jbe (&label("even_tail"));
1052 &jmp (&label("mod_loop"));
1053
1054&set_label("mod_loop",32);
1055 &pshufd ($T2,$Xi,0b01001110); # H^2*(Ii+Xi)
1056 &movdqa ($Xhi,$Xi);
1057 &pxor ($T2,$Xi); #
1058 &nop ();
1059
1060 &pclmulqdq ($Xi,$Hkey,0x00); #######
1061 &pclmulqdq ($Xhi,$Hkey,0x11); #######
1062 &pclmulqdq ($T2,$T3,0x10); #######
1063 &movups ($Hkey,&QWP(0,$Htbl)); # load H
1064
1065 &xorps ($Xi,$Xn); # (H*Ii+1) + H^2*(Ii+Xi)
1066 &movdqa ($T3,&QWP(0,$const));
1067 &xorps ($Xhi,$Xhn);
1068 &movdqu ($Xhn,&QWP(0,$inp)); # Ii
1069 &pxor ($T1,$Xi); # aggregated Karatsuba post-processing
1070 &movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1071 &pxor ($T1,$Xhi); #
1072
1073 &pshufb ($Xhn,$T3);
1074 &pxor ($T2,$T1); #
1075
1076 &movdqa ($T1,$T2); #
1077 &psrldq ($T2,8);
1078 &pslldq ($T1,8); #
1079 &pxor ($Xhi,$T2);
1080 &pxor ($Xi,$T1); #
1081 &pshufb ($Xn,$T3);
1082 &pxor ($Xhi,$Xhn); # "Ii+Xi", consume early
1083
1084 &movdqa ($Xhn,$Xn); #&clmul64x64_TX ($Xhn,$Xn,$Hkey); H*Ii+1
1085 &movdqa ($T2,$Xi); #&reduction_alg9($Xhi,$Xi); 1st phase
1086 &movdqa ($T1,$Xi);
1087 &psllq ($Xi,5);
1088 &pxor ($T1,$Xi); #
1089 &psllq ($Xi,1);
1090 &pxor ($Xi,$T1); #
1091 &pclmulqdq ($Xn,$Hkey,0x00); #######
1092 &movups ($T3,&QWP(32,$Htbl));
1093 &psllq ($Xi,57); #
1094 &movdqa ($T1,$Xi); #
1095 &pslldq ($Xi,8);
1096 &psrldq ($T1,8); #
1097 &pxor ($Xi,$T2);
1098 &pxor ($Xhi,$T1); #
1099 &pshufd ($T1,$Xhn,0b01001110);
1100 &movdqa ($T2,$Xi); # 2nd phase
1101 &psrlq ($Xi,1);
1102 &pxor ($T1,$Xhn);
1103 &pxor ($Xhi,$T2); #
1104 &pclmulqdq ($Xhn,$Hkey,0x11); #######
1105 &movups ($Hkey,&QWP(16,$Htbl)); # load H^2
1106 &pxor ($T2,$Xi);
1107 &psrlq ($Xi,5);
1108 &pxor ($Xi,$T2); #
1109 &psrlq ($Xi,1); #
1110 &pxor ($Xi,$Xhi) #
1111 &pclmulqdq ($T1,$T3,0x00); #######
1112
1113 &lea ($inp,&DWP(32,$inp));
1114 &sub ($len,0x20);
1115 &ja (&label("mod_loop"));
1116
1117&set_label("even_tail");
1118 &pshufd ($T2,$Xi,0b01001110); # H^2*(Ii+Xi)
1119 &movdqa ($Xhi,$Xi);
1120 &pxor ($T2,$Xi); #
1121
1122 &pclmulqdq ($Xi,$Hkey,0x00); #######
1123 &pclmulqdq ($Xhi,$Hkey,0x11); #######
1124 &pclmulqdq ($T2,$T3,0x10); #######
1125 &movdqa ($T3,&QWP(0,$const));
1126
1127 &xorps ($Xi,$Xn); # (H*Ii+1) + H^2*(Ii+Xi)
1128 &xorps ($Xhi,$Xhn);
1129 &pxor ($T1,$Xi); # aggregated Karatsuba post-processing
1130 &pxor ($T1,$Xhi); #
1131
1132 &pxor ($T2,$T1); #
1133
1134 &movdqa ($T1,$T2); #
1135 &psrldq ($T2,8);
1136 &pslldq ($T1,8); #
1137 &pxor ($Xhi,$T2);
1138 &pxor ($Xi,$T1); #
1139
1140 &reduction_alg9 ($Xhi,$Xi);
1141
1142 &test ($len,$len);
1143 &jnz (&label("done"));
1144
1145 &movups ($Hkey,&QWP(0,$Htbl)); # load H
1146&set_label("odd_tail");
1147 &movdqu ($T1,&QWP(0,$inp)); # Ii
1148 &pshufb ($T1,$T3);
1149 &pxor ($Xi,$T1); # Ii+Xi
1150
1151 &clmul64x64_T2 ($Xhi,$Xi,$Hkey); # H*(Ii+Xi)
1152 &reduction_alg9 ($Xhi,$Xi);
1153
1154&set_label("done");
1155 &pshufb ($Xi,$T3);
1156 &movdqu (&QWP(0,$Xip),$Xi);
1157&function_end("gcm_ghash_clmul");
1158
1159
1160} else { # Algorithm 5. Kept for reference purposes.
1161
1162sub reduction_alg5 { # 19/16 times faster than Intel version
1163my ($Xhi,$Xi)=@_;
1164
1165 # <<1
1166 &movdqa ($T1,$Xi); #
1167 &movdqa ($T2,$Xhi);
1168 &pslld ($Xi,1);
1169 &pslld ($Xhi,1); #
1170 &psrld ($T1,31);
1171 &psrld ($T2,31); #
1172 &movdqa ($T3,$T1);
1173 &pslldq ($T1,4);
1174 &psrldq ($T3,12); #
1175 &pslldq ($T2,4);
1176 &por ($Xhi,$T3); #
1177 &por ($Xi,$T1);
1178 &por ($Xhi,$T2); #
1179
1180 # 1st phase
1181 &movdqa ($T1,$Xi);
1182 &movdqa ($T2,$Xi);
1183 &movdqa ($T3,$Xi); #
1184 &pslld ($T1,31);
1185 &pslld ($T2,30);
1186 &pslld ($Xi,25); #
1187 &pxor ($T1,$T2);
1188 &pxor ($T1,$Xi); #
1189 &movdqa ($T2,$T1); #
1190 &pslldq ($T1,12);
1191 &psrldq ($T2,4); #
1192 &pxor ($T3,$T1);
1193
1194 # 2nd phase
1195 &pxor ($Xhi,$T3); #
1196 &movdqa ($Xi,$T3);
1197 &movdqa ($T1,$T3);
1198 &psrld ($Xi,1); #
1199 &psrld ($T1,2);
1200 &psrld ($T3,7); #
1201 &pxor ($Xi,$T1);
1202 &pxor ($Xhi,$T2);
1203 &pxor ($Xi,$T3); #
1204 &pxor ($Xi,$Xhi); #
1205}
1206
1207&function_begin_B("gcm_init_clmul");
1208 &mov ($Htbl,&wparam(0));
1209 &mov ($Xip,&wparam(1));
1210
1211 &call (&label("pic"));
1212&set_label("pic");
1213 &blindpop ($const);
1214 &lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1215
1216 &movdqu ($Hkey,&QWP(0,$Xip));
1217 &pshufd ($Hkey,$Hkey,0b01001110);# dword swap
1218
1219 # calculate H^2
1220 &movdqa ($Xi,$Hkey);
1221 &clmul64x64_T3 ($Xhi,$Xi,$Hkey);
1222 &reduction_alg5 ($Xhi,$Xi);
1223
1224 &movdqu (&QWP(0,$Htbl),$Hkey); # save H
1225 &movdqu (&QWP(16,$Htbl),$Xi); # save H^2
1226
1227 &ret ();
1228&function_end_B("gcm_init_clmul");
1229
1230&function_begin_B("gcm_gmult_clmul");
1231 &mov ($Xip,&wparam(0));
1232 &mov ($Htbl,&wparam(1));
1233
1234 &call (&label("pic"));
1235&set_label("pic");
1236 &blindpop ($const);
1237 &lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1238
1239 &movdqu ($Xi,&QWP(0,$Xip));
1240 &movdqa ($Xn,&QWP(0,$const));
1241 &movdqu ($Hkey,&QWP(0,$Htbl));
1242 &pshufb ($Xi,$Xn);
1243
1244 &clmul64x64_T3 ($Xhi,$Xi,$Hkey);
1245 &reduction_alg5 ($Xhi,$Xi);
1246
1247 &pshufb ($Xi,$Xn);
1248 &movdqu (&QWP(0,$Xip),$Xi);
1249
1250 &ret ();
1251&function_end_B("gcm_gmult_clmul");
1252
1253&function_begin("gcm_ghash_clmul");
1254 &mov ($Xip,&wparam(0));
1255 &mov ($Htbl,&wparam(1));
1256 &mov ($inp,&wparam(2));
1257 &mov ($len,&wparam(3));
1258
1259 &call (&label("pic"));
1260&set_label("pic");
1261 &blindpop ($const);
1262 &lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1263
1264 &movdqu ($Xi,&QWP(0,$Xip));
1265 &movdqa ($T3,&QWP(0,$const));
1266 &movdqu ($Hkey,&QWP(0,$Htbl));
1267 &pshufb ($Xi,$T3);
1268
1269 &sub ($len,0x10);
1270 &jz (&label("odd_tail"));
1271
1272 #######
1273 # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
1274 # [(H*Ii+1) + (H*Xi+1)] mod P =
1275 # [(H*Ii+1) + H^2*(Ii+Xi)] mod P
1276 #
1277 &movdqu ($T1,&QWP(0,$inp)); # Ii
1278 &movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1279 &pshufb ($T1,$T3);
1280 &pshufb ($Xn,$T3);
1281 &pxor ($Xi,$T1); # Ii+Xi
1282
1283 &clmul64x64_T3 ($Xhn,$Xn,$Hkey); # H*Ii+1
1284 &movdqu ($Hkey,&QWP(16,$Htbl)); # load H^2
1285
1286 &sub ($len,0x20);
1287 &lea ($inp,&DWP(32,$inp)); # i+=2
1288 &jbe (&label("even_tail"));
1289
1290&set_label("mod_loop");
1291 &clmul64x64_T3 ($Xhi,$Xi,$Hkey); # H^2*(Ii+Xi)
1292 &movdqu ($Hkey,&QWP(0,$Htbl)); # load H
1293
1294 &pxor ($Xi,$Xn); # (H*Ii+1) + H^2*(Ii+Xi)
1295 &pxor ($Xhi,$Xhn);
1296
1297 &reduction_alg5 ($Xhi,$Xi);
1298
1299 #######
1300 &movdqa ($T3,&QWP(0,$const));
1301 &movdqu ($T1,&QWP(0,$inp)); # Ii
1302 &movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1303 &pshufb ($T1,$T3);
1304 &pshufb ($Xn,$T3);
1305 &pxor ($Xi,$T1); # Ii+Xi
1306
1307 &clmul64x64_T3 ($Xhn,$Xn,$Hkey); # H*Ii+1
1308 &movdqu ($Hkey,&QWP(16,$Htbl)); # load H^2
1309
1310 &sub ($len,0x20);
1311 &lea ($inp,&DWP(32,$inp));
1312 &ja (&label("mod_loop"));
1313
1314&set_label("even_tail");
1315 &clmul64x64_T3 ($Xhi,$Xi,$Hkey); # H^2*(Ii+Xi)
1316
1317 &pxor ($Xi,$Xn); # (H*Ii+1) + H^2*(Ii+Xi)
1318 &pxor ($Xhi,$Xhn);
1319
1320 &reduction_alg5 ($Xhi,$Xi);
1321
1322 &movdqa ($T3,&QWP(0,$const));
1323 &test ($len,$len);
1324 &jnz (&label("done"));
1325
1326 &movdqu ($Hkey,&QWP(0,$Htbl)); # load H
1327&set_label("odd_tail");
1328 &movdqu ($T1,&QWP(0,$inp)); # Ii
1329 &pshufb ($T1,$T3);
1330 &pxor ($Xi,$T1); # Ii+Xi
1331
1332 &clmul64x64_T3 ($Xhi,$Xi,$Hkey); # H*(Ii+Xi)
1333 &reduction_alg5 ($Xhi,$Xi);
1334
1335 &movdqa ($T3,&QWP(0,$const));
1336&set_label("done");
1337 &pshufb ($Xi,$T3);
1338 &movdqu (&QWP(0,$Xip),$Xi);
1339&function_end("gcm_ghash_clmul");
1340
1341}
1342
1343
1344&set_label("bswap",64);
1345 &data_byte(15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0);
1346 &data_byte(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0xc2); # 0x1c2_polynomial
1347&set_label("rem_8bit",64);
1348 &data_short(0x0000,0x01C2,0x0384,0x0246,0x0708,0x06CA,0x048C,0x054E);
1349 &data_short(0x0E10,0x0FD2,0x0D94,0x0C56,0x0918,0x08DA,0x0A9C,0x0B5E);
1350 &data_short(0x1C20,0x1DE2,0x1FA4,0x1E66,0x1B28,0x1AEA,0x18AC,0x196E);
1351 &data_short(0x1230,0x13F2,0x11B4,0x1076,0x1538,0x14FA,0x16BC,0x177E);
1352 &data_short(0x3840,0x3982,0x3BC4,0x3A06,0x3F48,0x3E8A,0x3CCC,0x3D0E);
1353 &data_short(0x3650,0x3792,0x35D4,0x3416,0x3158,0x309A,0x32DC,0x331E);
1354 &data_short(0x2460,0x25A2,0x27E4,0x2626,0x2368,0x22AA,0x20EC,0x212E);
1355 &data_short(0x2A70,0x2BB2,0x29F4,0x2836,0x2D78,0x2CBA,0x2EFC,0x2F3E);
1356 &data_short(0x7080,0x7142,0x7304,0x72C6,0x7788,0x764A,0x740C,0x75CE);
1357 &data_short(0x7E90,0x7F52,0x7D14,0x7CD6,0x7998,0x785A,0x7A1C,0x7BDE);
1358 &data_short(0x6CA0,0x6D62,0x6F24,0x6EE6,0x6BA8,0x6A6A,0x682C,0x69EE);
1359 &data_short(0x62B0,0x6372,0x6134,0x60F6,0x65B8,0x647A,0x663C,0x67FE);
1360 &data_short(0x48C0,0x4902,0x4B44,0x4A86,0x4FC8,0x4E0A,0x4C4C,0x4D8E);
1361 &data_short(0x46D0,0x4712,0x4554,0x4496,0x41D8,0x401A,0x425C,0x439E);
1362 &data_short(0x54E0,0x5522,0x5764,0x56A6,0x53E8,0x522A,0x506C,0x51AE);
1363 &data_short(0x5AF0,0x5B32,0x5974,0x58B6,0x5DF8,0x5C3A,0x5E7C,0x5FBE);
1364 &data_short(0xE100,0xE0C2,0xE284,0xE346,0xE608,0xE7CA,0xE58C,0xE44E);
1365 &data_short(0xEF10,0xEED2,0xEC94,0xED56,0xE818,0xE9DA,0xEB9C,0xEA5E);
1366 &data_short(0xFD20,0xFCE2,0xFEA4,0xFF66,0xFA28,0xFBEA,0xF9AC,0xF86E);
1367 &data_short(0xF330,0xF2F2,0xF0B4,0xF176,0xF438,0xF5FA,0xF7BC,0xF67E);
1368 &data_short(0xD940,0xD882,0xDAC4,0xDB06,0xDE48,0xDF8A,0xDDCC,0xDC0E);
1369 &data_short(0xD750,0xD692,0xD4D4,0xD516,0xD058,0xD19A,0xD3DC,0xD21E);
1370 &data_short(0xC560,0xC4A2,0xC6E4,0xC726,0xC268,0xC3AA,0xC1EC,0xC02E);
1371 &data_short(0xCB70,0xCAB2,0xC8F4,0xC936,0xCC78,0xCDBA,0xCFFC,0xCE3E);
1372 &data_short(0x9180,0x9042,0x9204,0x93C6,0x9688,0x974A,0x950C,0x94CE);
1373 &data_short(0x9F90,0x9E52,0x9C14,0x9DD6,0x9898,0x995A,0x9B1C,0x9ADE);
1374 &data_short(0x8DA0,0x8C62,0x8E24,0x8FE6,0x8AA8,0x8B6A,0x892C,0x88EE);
1375 &data_short(0x83B0,0x8272,0x8034,0x81F6,0x84B8,0x857A,0x873C,0x86FE);
1376 &data_short(0xA9C0,0xA802,0xAA44,0xAB86,0xAEC8,0xAF0A,0xAD4C,0xAC8E);
1377 &data_short(0xA7D0,0xA612,0xA454,0xA596,0xA0D8,0xA11A,0xA35C,0xA29E);
1378 &data_short(0xB5E0,0xB422,0xB664,0xB7A6,0xB2E8,0xB32A,0xB16C,0xB0AE);
1379 &data_short(0xBBF0,0xBA32,0xB874,0xB9B6,0xBCF8,0xBD3A,0xBF7C,0xBEBE);
1380}} # $sse2
1381
1382&set_label("rem_4bit",64);
1383 &data_word(0,0x0000<<$S,0,0x1C20<<$S,0,0x3840<<$S,0,0x2460<<$S);
1384 &data_word(0,0x7080<<$S,0,0x6CA0<<$S,0,0x48C0<<$S,0,0x54E0<<$S);
1385 &data_word(0,0xE100<<$S,0,0xFD20<<$S,0,0xD940<<$S,0,0xC560<<$S);
1386 &data_word(0,0x9180<<$S,0,0x8DA0<<$S,0,0xA9C0<<$S,0,0xB5E0<<$S);
1387}}} # !$x86only
1388
1389&asciz("GHASH for x86, CRYPTOGAMS by <appro\@openssl.org>");
1390&asm_finish();
1391
1392close STDOUT;
1393
1394# A question was risen about choice of vanilla MMX. Or rather why wasn't
1395# SSE2 chosen instead? In addition to the fact that MMX runs on legacy
1396# CPUs such as PIII, "4-bit" MMX version was observed to provide better
1397# performance than *corresponding* SSE2 one even on contemporary CPUs.
1398# SSE2 results were provided by Peter-Michael Hager. He maintains SSE2
1399# implementation featuring full range of lookup-table sizes, but with
1400# per-invocation lookup table setup. Latter means that table size is
1401# chosen depending on how much data is to be hashed in every given call,
1402# more data - larger table. Best reported result for Core2 is ~4 cycles
1403# per processed byte out of 64KB block. This number accounts even for
1404# 64KB table setup overhead. As discussed in gcm128.c we choose to be
1405# more conservative in respect to lookup table sizes, but how do the
1406# results compare? Minimalistic "256B" MMX version delivers ~11 cycles
1407# on same platform. As also discussed in gcm128.c, next in line "8-bit
1408# Shoup's" or "4KB" method should deliver twice the performance of
1409# "256B" one, in other words not worse than ~6 cycles per byte. It
1410# should be also be noted that in SSE2 case improvement can be "super-
1411# linear," i.e. more than twice, mostly because >>8 maps to single
1412# instruction on SSE2 register. This is unlike "4-bit" case when >>4
1413# maps to same amount of instructions in both MMX and SSE2 cases.
1414# Bottom line is that switch to SSE2 is considered to be justifiable
1415# only in case we choose to implement "8-bit" method...
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