| 1 | #! /usr/bin/env perl
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| 2 | # Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | #
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| 4 | # Licensed under the OpenSSL license (the "License"). You may not use
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| 5 | # this file except in compliance with the License. You can obtain a copy
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| 6 | # in the file LICENSE in the source distribution or at
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| 7 | # https://www.openssl.org/source/license.html
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| 8 |
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| 9 |
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| 10 | # ====================================================================
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| 11 | # Written by Andy Polyakov <[email protected]> for the OpenSSL
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| 12 | # project. The module is, however, dual licensed under OpenSSL and
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| 13 | # CRYPTOGAMS licenses depending on where you obtain it. For further
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| 14 | # details see http://www.openssl.org/~appro/cryptogams/.
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| 15 | #
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| 16 | # Permission to use under GPL terms is granted.
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| 17 | # ====================================================================
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| 18 |
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| 19 | # SHA512 block procedure for ARMv4. September 2007.
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| 20 |
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| 21 | # This code is ~4.5 (four and a half) times faster than code generated
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| 22 | # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
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| 23 | # Xscale PXA250 core].
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| 24 | #
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| 25 | # July 2010.
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| 26 | #
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| 27 | # Rescheduling for dual-issue pipeline resulted in 6% improvement on
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| 28 | # Cortex A8 core and ~40 cycles per processed byte.
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| 29 |
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| 30 | # February 2011.
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| 31 | #
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| 32 | # Profiler-assisted and platform-specific optimization resulted in 7%
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| 33 | # improvement on Coxtex A8 core and ~38 cycles per byte.
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| 34 |
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| 35 | # March 2011.
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| 36 | #
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| 37 | # Add NEON implementation. On Cortex A8 it was measured to process
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| 38 | # one byte in 23.3 cycles or ~60% faster than integer-only code.
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| 39 |
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| 40 | # August 2012.
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| 41 | #
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| 42 | # Improve NEON performance by 12% on Snapdragon S4. In absolute
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| 43 | # terms it's 22.6 cycles per byte, which is disappointing result.
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| 44 | # Technical writers asserted that 3-way S4 pipeline can sustain
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| 45 | # multiple NEON instructions per cycle, but dual NEON issue could
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| 46 | # not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
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| 47 | # for further details. On side note Cortex-A15 processes one byte in
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| 48 | # 16 cycles.
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| 49 |
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| 50 | # Byte order [in]dependence. =========================================
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| 51 | #
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| 52 | # Originally caller was expected to maintain specific *dword* order in
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| 53 | # h[0-7], namely with most significant dword at *lower* address, which
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| 54 | # was reflected in below two parameters as 0 and 4. Now caller is
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| 55 | # expected to maintain native byte order for whole 64-bit values.
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| 56 | $hi="HI";
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| 57 | $lo="LO";
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| 58 | # ====================================================================
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| 59 |
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| 60 | $flavour = shift;
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| 61 | if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
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| 62 | else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
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| 63 |
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| 64 | if ($flavour && $flavour ne "void") {
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| 65 | $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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| 66 | ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
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| 67 | ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
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| 68 | die "can't locate arm-xlate.pl";
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| 69 |
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| 70 | open STDOUT,"| \"$^X\" $xlate $flavour $output";
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| 71 | } else {
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| 72 | open STDOUT,">$output";
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| 73 | }
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| 74 |
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| 75 | $ctx="r0"; # parameter block
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| 76 | $inp="r1";
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| 77 | $len="r2";
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| 78 |
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| 79 | $Tlo="r3";
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| 80 | $Thi="r4";
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| 81 | $Alo="r5";
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| 82 | $Ahi="r6";
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| 83 | $Elo="r7";
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| 84 | $Ehi="r8";
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| 85 | $t0="r9";
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| 86 | $t1="r10";
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| 87 | $t2="r11";
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| 88 | $t3="r12";
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| 89 | ############ r13 is stack pointer
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| 90 | $Ktbl="r14";
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| 91 | ############ r15 is program counter
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| 92 |
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| 93 | $Aoff=8*0;
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| 94 | $Boff=8*1;
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| 95 | $Coff=8*2;
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| 96 | $Doff=8*3;
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| 97 | $Eoff=8*4;
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| 98 | $Foff=8*5;
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| 99 | $Goff=8*6;
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| 100 | $Hoff=8*7;
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| 101 | $Xoff=8*8;
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| 102 |
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| 103 | sub BODY_00_15() {
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| 104 | my $magic = shift;
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| 105 | $code.=<<___;
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| 106 | @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
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| 107 | @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
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| 108 | @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
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| 109 | mov $t0,$Elo,lsr#14
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| 110 | str $Tlo,[sp,#$Xoff+0]
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| 111 | mov $t1,$Ehi,lsr#14
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| 112 | str $Thi,[sp,#$Xoff+4]
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| 113 | eor $t0,$t0,$Ehi,lsl#18
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| 114 | ldr $t2,[sp,#$Hoff+0] @ h.lo
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| 115 | eor $t1,$t1,$Elo,lsl#18
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| 116 | ldr $t3,[sp,#$Hoff+4] @ h.hi
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| 117 | eor $t0,$t0,$Elo,lsr#18
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| 118 | eor $t1,$t1,$Ehi,lsr#18
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| 119 | eor $t0,$t0,$Ehi,lsl#14
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| 120 | eor $t1,$t1,$Elo,lsl#14
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| 121 | eor $t0,$t0,$Ehi,lsr#9
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| 122 | eor $t1,$t1,$Elo,lsr#9
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| 123 | eor $t0,$t0,$Elo,lsl#23
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| 124 | eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
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| 125 | adds $Tlo,$Tlo,$t0
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| 126 | ldr $t0,[sp,#$Foff+0] @ f.lo
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| 127 | adc $Thi,$Thi,$t1 @ T += Sigma1(e)
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| 128 | ldr $t1,[sp,#$Foff+4] @ f.hi
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| 129 | adds $Tlo,$Tlo,$t2
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| 130 | ldr $t2,[sp,#$Goff+0] @ g.lo
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| 131 | adc $Thi,$Thi,$t3 @ T += h
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| 132 | ldr $t3,[sp,#$Goff+4] @ g.hi
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| 133 |
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| 134 | eor $t0,$t0,$t2
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| 135 | str $Elo,[sp,#$Eoff+0]
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| 136 | eor $t1,$t1,$t3
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| 137 | str $Ehi,[sp,#$Eoff+4]
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| 138 | and $t0,$t0,$Elo
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| 139 | str $Alo,[sp,#$Aoff+0]
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| 140 | and $t1,$t1,$Ehi
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| 141 | str $Ahi,[sp,#$Aoff+4]
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| 142 | eor $t0,$t0,$t2
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| 143 | ldr $t2,[$Ktbl,#$lo] @ K[i].lo
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| 144 | eor $t1,$t1,$t3 @ Ch(e,f,g)
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| 145 | ldr $t3,[$Ktbl,#$hi] @ K[i].hi
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| 146 |
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| 147 | adds $Tlo,$Tlo,$t0
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| 148 | ldr $Elo,[sp,#$Doff+0] @ d.lo
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| 149 | adc $Thi,$Thi,$t1 @ T += Ch(e,f,g)
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| 150 | ldr $Ehi,[sp,#$Doff+4] @ d.hi
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| 151 | adds $Tlo,$Tlo,$t2
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| 152 | and $t0,$t2,#0xff
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| 153 | adc $Thi,$Thi,$t3 @ T += K[i]
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| 154 | adds $Elo,$Elo,$Tlo
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| 155 | ldr $t2,[sp,#$Boff+0] @ b.lo
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| 156 | adc $Ehi,$Ehi,$Thi @ d += T
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| 157 | teq $t0,#$magic
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| 158 |
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| 159 | ldr $t3,[sp,#$Coff+0] @ c.lo
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| 160 | #if __ARM_ARCH__>=7
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| 161 | it eq @ Thumb2 thing, sanity check in ARM
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| 162 | #endif
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| 163 | orreq $Ktbl,$Ktbl,#1
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| 164 | @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
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| 165 | @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
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| 166 | @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
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| 167 | mov $t0,$Alo,lsr#28
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| 168 | mov $t1,$Ahi,lsr#28
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| 169 | eor $t0,$t0,$Ahi,lsl#4
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| 170 | eor $t1,$t1,$Alo,lsl#4
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| 171 | eor $t0,$t0,$Ahi,lsr#2
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| 172 | eor $t1,$t1,$Alo,lsr#2
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| 173 | eor $t0,$t0,$Alo,lsl#30
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| 174 | eor $t1,$t1,$Ahi,lsl#30
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| 175 | eor $t0,$t0,$Ahi,lsr#7
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| 176 | eor $t1,$t1,$Alo,lsr#7
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| 177 | eor $t0,$t0,$Alo,lsl#25
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| 178 | eor $t1,$t1,$Ahi,lsl#25 @ Sigma0(a)
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| 179 | adds $Tlo,$Tlo,$t0
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| 180 | and $t0,$Alo,$t2
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| 181 | adc $Thi,$Thi,$t1 @ T += Sigma0(a)
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| 182 |
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| 183 | ldr $t1,[sp,#$Boff+4] @ b.hi
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| 184 | orr $Alo,$Alo,$t2
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| 185 | ldr $t2,[sp,#$Coff+4] @ c.hi
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| 186 | and $Alo,$Alo,$t3
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| 187 | and $t3,$Ahi,$t1
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| 188 | orr $Ahi,$Ahi,$t1
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| 189 | orr $Alo,$Alo,$t0 @ Maj(a,b,c).lo
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| 190 | and $Ahi,$Ahi,$t2
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| 191 | adds $Alo,$Alo,$Tlo
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| 192 | orr $Ahi,$Ahi,$t3 @ Maj(a,b,c).hi
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| 193 | sub sp,sp,#8
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| 194 | adc $Ahi,$Ahi,$Thi @ h += T
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| 195 | tst $Ktbl,#1
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| 196 | add $Ktbl,$Ktbl,#8
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| 197 | ___
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| 198 | }
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| 199 | $code=<<___;
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| 200 | #ifndef __KERNEL__
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| 201 | # include "arm_arch.h"
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| 202 | # define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
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| 203 | # define VFP_ABI_POP vldmia sp!,{d8-d15}
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| 204 | #else
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| 205 | # define __ARM_ARCH__ __LINUX_ARM_ARCH__
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| 206 | # define __ARM_MAX_ARCH__ 7
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| 207 | # define VFP_ABI_PUSH
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| 208 | # define VFP_ABI_POP
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| 209 | #endif
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| 210 |
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| 211 | #ifdef __ARMEL__
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| 212 | # define LO 0
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| 213 | # define HI 4
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| 214 | # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1
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| 215 | #else
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| 216 | # define HI 0
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| 217 | # define LO 4
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| 218 | # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1
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| 219 | #endif
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| 220 |
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| 221 | .text
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| 222 | #if defined(__thumb2__)
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| 223 | .syntax unified
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| 224 | .thumb
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| 225 | # define adrl adr
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| 226 | #else
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| 227 | .code 32
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| 228 | #endif
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| 229 |
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| 230 | .type K512,%object
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| 231 | .align 5
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| 232 | K512:
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| 233 | WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd)
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| 234 | WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc)
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| 235 | WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019)
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| 236 | WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118)
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| 237 | WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe)
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| 238 | WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2)
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| 239 | WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1)
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| 240 | WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694)
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| 241 | WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3)
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| 242 | WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65)
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| 243 | WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483)
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| 244 | WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5)
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| 245 | WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210)
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| 246 | WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4)
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| 247 | WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725)
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| 248 | WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70)
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| 249 | WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926)
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| 250 | WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df)
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| 251 | WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8)
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| 252 | WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b)
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| 253 | WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001)
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| 254 | WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30)
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| 255 | WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910)
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| 256 | WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8)
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| 257 | WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53)
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| 258 | WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8)
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| 259 | WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb)
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| 260 | WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3)
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| 261 | WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60)
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| 262 | WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec)
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| 263 | WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9)
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| 264 | WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b)
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| 265 | WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207)
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| 266 | WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178)
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| 267 | WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6)
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| 268 | WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b)
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| 269 | WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493)
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| 270 | WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
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| 271 | WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
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| 272 | WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
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| 273 | .size K512,.-K512
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| 274 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
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| 275 | .LOPENSSL_armcap:
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| 276 | .word OPENSSL_armcap_P-.Lsha512_block_data_order
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| 277 | .skip 32-4
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| 278 | #else
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| 279 | .skip 32
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| 280 | #endif
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| 281 |
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| 282 | .global sha512_block_data_order
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| 283 | .type sha512_block_data_order,%function
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| 284 | sha512_block_data_order:
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| 285 | .Lsha512_block_data_order:
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| 286 | #if __ARM_ARCH__<7 && !defined(__thumb2__)
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| 287 | sub r3,pc,#8 @ sha512_block_data_order
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| 288 | #else
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| 289 | adr r3,.Lsha512_block_data_order
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| 290 | #endif
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| 291 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
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| 292 | ldr r12,.LOPENSSL_armcap
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| 293 | ldr r12,[r3,r12] @ OPENSSL_armcap_P
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| 294 | #ifdef __APPLE__
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| 295 | ldr r12,[r12]
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| 296 | #endif
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| 297 | tst r12,#ARMV7_NEON
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| 298 | bne .LNEON
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| 299 | #endif
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| 300 | add $len,$inp,$len,lsl#7 @ len to point at the end of inp
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| 301 | stmdb sp!,{r4-r12,lr}
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| 302 | sub $Ktbl,r3,#672 @ K512
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| 303 | sub sp,sp,#9*8
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| 304 |
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| 305 | ldr $Elo,[$ctx,#$Eoff+$lo]
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| 306 | ldr $Ehi,[$ctx,#$Eoff+$hi]
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| 307 | ldr $t0, [$ctx,#$Goff+$lo]
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| 308 | ldr $t1, [$ctx,#$Goff+$hi]
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| 309 | ldr $t2, [$ctx,#$Hoff+$lo]
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| 310 | ldr $t3, [$ctx,#$Hoff+$hi]
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| 311 | .Loop:
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| 312 | str $t0, [sp,#$Goff+0]
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| 313 | str $t1, [sp,#$Goff+4]
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| 314 | str $t2, [sp,#$Hoff+0]
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| 315 | str $t3, [sp,#$Hoff+4]
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| 316 | ldr $Alo,[$ctx,#$Aoff+$lo]
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| 317 | ldr $Ahi,[$ctx,#$Aoff+$hi]
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| 318 | ldr $Tlo,[$ctx,#$Boff+$lo]
|
|---|
| 319 | ldr $Thi,[$ctx,#$Boff+$hi]
|
|---|
| 320 | ldr $t0, [$ctx,#$Coff+$lo]
|
|---|
| 321 | ldr $t1, [$ctx,#$Coff+$hi]
|
|---|
| 322 | ldr $t2, [$ctx,#$Doff+$lo]
|
|---|
| 323 | ldr $t3, [$ctx,#$Doff+$hi]
|
|---|
| 324 | str $Tlo,[sp,#$Boff+0]
|
|---|
| 325 | str $Thi,[sp,#$Boff+4]
|
|---|
| 326 | str $t0, [sp,#$Coff+0]
|
|---|
| 327 | str $t1, [sp,#$Coff+4]
|
|---|
| 328 | str $t2, [sp,#$Doff+0]
|
|---|
| 329 | str $t3, [sp,#$Doff+4]
|
|---|
| 330 | ldr $Tlo,[$ctx,#$Foff+$lo]
|
|---|
| 331 | ldr $Thi,[$ctx,#$Foff+$hi]
|
|---|
| 332 | str $Tlo,[sp,#$Foff+0]
|
|---|
| 333 | str $Thi,[sp,#$Foff+4]
|
|---|
| 334 |
|
|---|
| 335 | .L00_15:
|
|---|
| 336 | #if __ARM_ARCH__<7
|
|---|
| 337 | ldrb $Tlo,[$inp,#7]
|
|---|
| 338 | ldrb $t0, [$inp,#6]
|
|---|
| 339 | ldrb $t1, [$inp,#5]
|
|---|
| 340 | ldrb $t2, [$inp,#4]
|
|---|
| 341 | ldrb $Thi,[$inp,#3]
|
|---|
| 342 | ldrb $t3, [$inp,#2]
|
|---|
| 343 | orr $Tlo,$Tlo,$t0,lsl#8
|
|---|
| 344 | ldrb $t0, [$inp,#1]
|
|---|
| 345 | orr $Tlo,$Tlo,$t1,lsl#16
|
|---|
| 346 | ldrb $t1, [$inp],#8
|
|---|
| 347 | orr $Tlo,$Tlo,$t2,lsl#24
|
|---|
| 348 | orr $Thi,$Thi,$t3,lsl#8
|
|---|
| 349 | orr $Thi,$Thi,$t0,lsl#16
|
|---|
| 350 | orr $Thi,$Thi,$t1,lsl#24
|
|---|
| 351 | #else
|
|---|
| 352 | ldr $Tlo,[$inp,#4]
|
|---|
| 353 | ldr $Thi,[$inp],#8
|
|---|
| 354 | #ifdef __ARMEL__
|
|---|
| 355 | rev $Tlo,$Tlo
|
|---|
| 356 | rev $Thi,$Thi
|
|---|
| 357 | #endif
|
|---|
| 358 | #endif
|
|---|
| 359 | ___
|
|---|
| 360 | &BODY_00_15(0x94);
|
|---|
| 361 | $code.=<<___;
|
|---|
| 362 | tst $Ktbl,#1
|
|---|
| 363 | beq .L00_15
|
|---|
| 364 | ldr $t0,[sp,#`$Xoff+8*(16-1)`+0]
|
|---|
| 365 | ldr $t1,[sp,#`$Xoff+8*(16-1)`+4]
|
|---|
| 366 | bic $Ktbl,$Ktbl,#1
|
|---|
| 367 | .L16_79:
|
|---|
| 368 | @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
|
|---|
| 369 | @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25
|
|---|
| 370 | @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7
|
|---|
| 371 | mov $Tlo,$t0,lsr#1
|
|---|
| 372 | ldr $t2,[sp,#`$Xoff+8*(16-14)`+0]
|
|---|
| 373 | mov $Thi,$t1,lsr#1
|
|---|
| 374 | ldr $t3,[sp,#`$Xoff+8*(16-14)`+4]
|
|---|
| 375 | eor $Tlo,$Tlo,$t1,lsl#31
|
|---|
| 376 | eor $Thi,$Thi,$t0,lsl#31
|
|---|
| 377 | eor $Tlo,$Tlo,$t0,lsr#8
|
|---|
| 378 | eor $Thi,$Thi,$t1,lsr#8
|
|---|
| 379 | eor $Tlo,$Tlo,$t1,lsl#24
|
|---|
| 380 | eor $Thi,$Thi,$t0,lsl#24
|
|---|
| 381 | eor $Tlo,$Tlo,$t0,lsr#7
|
|---|
| 382 | eor $Thi,$Thi,$t1,lsr#7
|
|---|
| 383 | eor $Tlo,$Tlo,$t1,lsl#25
|
|---|
| 384 |
|
|---|
| 385 | @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
|
|---|
| 386 | @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26
|
|---|
| 387 | @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6
|
|---|
| 388 | mov $t0,$t2,lsr#19
|
|---|
| 389 | mov $t1,$t3,lsr#19
|
|---|
| 390 | eor $t0,$t0,$t3,lsl#13
|
|---|
| 391 | eor $t1,$t1,$t2,lsl#13
|
|---|
| 392 | eor $t0,$t0,$t3,lsr#29
|
|---|
| 393 | eor $t1,$t1,$t2,lsr#29
|
|---|
| 394 | eor $t0,$t0,$t2,lsl#3
|
|---|
| 395 | eor $t1,$t1,$t3,lsl#3
|
|---|
| 396 | eor $t0,$t0,$t2,lsr#6
|
|---|
| 397 | eor $t1,$t1,$t3,lsr#6
|
|---|
| 398 | ldr $t2,[sp,#`$Xoff+8*(16-9)`+0]
|
|---|
| 399 | eor $t0,$t0,$t3,lsl#26
|
|---|
| 400 |
|
|---|
| 401 | ldr $t3,[sp,#`$Xoff+8*(16-9)`+4]
|
|---|
| 402 | adds $Tlo,$Tlo,$t0
|
|---|
| 403 | ldr $t0,[sp,#`$Xoff+8*16`+0]
|
|---|
| 404 | adc $Thi,$Thi,$t1
|
|---|
| 405 |
|
|---|
| 406 | ldr $t1,[sp,#`$Xoff+8*16`+4]
|
|---|
| 407 | adds $Tlo,$Tlo,$t2
|
|---|
| 408 | adc $Thi,$Thi,$t3
|
|---|
| 409 | adds $Tlo,$Tlo,$t0
|
|---|
| 410 | adc $Thi,$Thi,$t1
|
|---|
| 411 | ___
|
|---|
| 412 | &BODY_00_15(0x17);
|
|---|
| 413 | $code.=<<___;
|
|---|
| 414 | #if __ARM_ARCH__>=7
|
|---|
| 415 | ittt eq @ Thumb2 thing, sanity check in ARM
|
|---|
| 416 | #endif
|
|---|
| 417 | ldreq $t0,[sp,#`$Xoff+8*(16-1)`+0]
|
|---|
| 418 | ldreq $t1,[sp,#`$Xoff+8*(16-1)`+4]
|
|---|
| 419 | beq .L16_79
|
|---|
| 420 | bic $Ktbl,$Ktbl,#1
|
|---|
| 421 |
|
|---|
| 422 | ldr $Tlo,[sp,#$Boff+0]
|
|---|
| 423 | ldr $Thi,[sp,#$Boff+4]
|
|---|
| 424 | ldr $t0, [$ctx,#$Aoff+$lo]
|
|---|
| 425 | ldr $t1, [$ctx,#$Aoff+$hi]
|
|---|
| 426 | ldr $t2, [$ctx,#$Boff+$lo]
|
|---|
| 427 | ldr $t3, [$ctx,#$Boff+$hi]
|
|---|
| 428 | adds $t0,$Alo,$t0
|
|---|
| 429 | str $t0, [$ctx,#$Aoff+$lo]
|
|---|
| 430 | adc $t1,$Ahi,$t1
|
|---|
| 431 | str $t1, [$ctx,#$Aoff+$hi]
|
|---|
| 432 | adds $t2,$Tlo,$t2
|
|---|
| 433 | str $t2, [$ctx,#$Boff+$lo]
|
|---|
| 434 | adc $t3,$Thi,$t3
|
|---|
| 435 | str $t3, [$ctx,#$Boff+$hi]
|
|---|
| 436 |
|
|---|
| 437 | ldr $Alo,[sp,#$Coff+0]
|
|---|
| 438 | ldr $Ahi,[sp,#$Coff+4]
|
|---|
| 439 | ldr $Tlo,[sp,#$Doff+0]
|
|---|
| 440 | ldr $Thi,[sp,#$Doff+4]
|
|---|
| 441 | ldr $t0, [$ctx,#$Coff+$lo]
|
|---|
| 442 | ldr $t1, [$ctx,#$Coff+$hi]
|
|---|
| 443 | ldr $t2, [$ctx,#$Doff+$lo]
|
|---|
| 444 | ldr $t3, [$ctx,#$Doff+$hi]
|
|---|
| 445 | adds $t0,$Alo,$t0
|
|---|
| 446 | str $t0, [$ctx,#$Coff+$lo]
|
|---|
| 447 | adc $t1,$Ahi,$t1
|
|---|
| 448 | str $t1, [$ctx,#$Coff+$hi]
|
|---|
| 449 | adds $t2,$Tlo,$t2
|
|---|
| 450 | str $t2, [$ctx,#$Doff+$lo]
|
|---|
| 451 | adc $t3,$Thi,$t3
|
|---|
| 452 | str $t3, [$ctx,#$Doff+$hi]
|
|---|
| 453 |
|
|---|
| 454 | ldr $Tlo,[sp,#$Foff+0]
|
|---|
| 455 | ldr $Thi,[sp,#$Foff+4]
|
|---|
| 456 | ldr $t0, [$ctx,#$Eoff+$lo]
|
|---|
| 457 | ldr $t1, [$ctx,#$Eoff+$hi]
|
|---|
| 458 | ldr $t2, [$ctx,#$Foff+$lo]
|
|---|
| 459 | ldr $t3, [$ctx,#$Foff+$hi]
|
|---|
| 460 | adds $Elo,$Elo,$t0
|
|---|
| 461 | str $Elo,[$ctx,#$Eoff+$lo]
|
|---|
| 462 | adc $Ehi,$Ehi,$t1
|
|---|
| 463 | str $Ehi,[$ctx,#$Eoff+$hi]
|
|---|
| 464 | adds $t2,$Tlo,$t2
|
|---|
| 465 | str $t2, [$ctx,#$Foff+$lo]
|
|---|
| 466 | adc $t3,$Thi,$t3
|
|---|
| 467 | str $t3, [$ctx,#$Foff+$hi]
|
|---|
| 468 |
|
|---|
| 469 | ldr $Alo,[sp,#$Goff+0]
|
|---|
| 470 | ldr $Ahi,[sp,#$Goff+4]
|
|---|
| 471 | ldr $Tlo,[sp,#$Hoff+0]
|
|---|
| 472 | ldr $Thi,[sp,#$Hoff+4]
|
|---|
| 473 | ldr $t0, [$ctx,#$Goff+$lo]
|
|---|
| 474 | ldr $t1, [$ctx,#$Goff+$hi]
|
|---|
| 475 | ldr $t2, [$ctx,#$Hoff+$lo]
|
|---|
| 476 | ldr $t3, [$ctx,#$Hoff+$hi]
|
|---|
| 477 | adds $t0,$Alo,$t0
|
|---|
| 478 | str $t0, [$ctx,#$Goff+$lo]
|
|---|
| 479 | adc $t1,$Ahi,$t1
|
|---|
| 480 | str $t1, [$ctx,#$Goff+$hi]
|
|---|
| 481 | adds $t2,$Tlo,$t2
|
|---|
| 482 | str $t2, [$ctx,#$Hoff+$lo]
|
|---|
| 483 | adc $t3,$Thi,$t3
|
|---|
| 484 | str $t3, [$ctx,#$Hoff+$hi]
|
|---|
| 485 |
|
|---|
| 486 | add sp,sp,#640
|
|---|
| 487 | sub $Ktbl,$Ktbl,#640
|
|---|
| 488 |
|
|---|
| 489 | teq $inp,$len
|
|---|
| 490 | bne .Loop
|
|---|
| 491 |
|
|---|
| 492 | add sp,sp,#8*9 @ destroy frame
|
|---|
| 493 | #if __ARM_ARCH__>=5
|
|---|
| 494 | ldmia sp!,{r4-r12,pc}
|
|---|
| 495 | #else
|
|---|
| 496 | ldmia sp!,{r4-r12,lr}
|
|---|
| 497 | tst lr,#1
|
|---|
| 498 | moveq pc,lr @ be binary compatible with V4, yet
|
|---|
| 499 | bx lr @ interoperable with Thumb ISA:-)
|
|---|
| 500 | #endif
|
|---|
| 501 | .size sha512_block_data_order,.-sha512_block_data_order
|
|---|
| 502 | ___
|
|---|
| 503 |
|
|---|
| 504 | {
|
|---|
| 505 | my @Sigma0=(28,34,39);
|
|---|
| 506 | my @Sigma1=(14,18,41);
|
|---|
| 507 | my @sigma0=(1, 8, 7);
|
|---|
| 508 | my @sigma1=(19,61,6);
|
|---|
| 509 |
|
|---|
| 510 | my $Ktbl="r3";
|
|---|
| 511 | my $cnt="r12"; # volatile register known as ip, intra-procedure-call scratch
|
|---|
| 512 |
|
|---|
| 513 | my @X=map("d$_",(0..15));
|
|---|
| 514 | my @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("d$_",(16..23));
|
|---|
| 515 |
|
|---|
| 516 | sub NEON_00_15() {
|
|---|
| 517 | my $i=shift;
|
|---|
| 518 | my ($a,$b,$c,$d,$e,$f,$g,$h)=@_;
|
|---|
| 519 | my ($t0,$t1,$t2,$T1,$K,$Ch,$Maj)=map("d$_",(24..31)); # temps
|
|---|
| 520 |
|
|---|
| 521 | $code.=<<___ if ($i<16 || $i&1);
|
|---|
| 522 | vshr.u64 $t0,$e,#@Sigma1[0] @ $i
|
|---|
| 523 | #if $i<16
|
|---|
| 524 | vld1.64 {@X[$i%16]},[$inp]! @ handles unaligned
|
|---|
| 525 | #endif
|
|---|
| 526 | vshr.u64 $t1,$e,#@Sigma1[1]
|
|---|
| 527 | #if $i>0
|
|---|
| 528 | vadd.i64 $a,$Maj @ h+=Maj from the past
|
|---|
| 529 | #endif
|
|---|
| 530 | vshr.u64 $t2,$e,#@Sigma1[2]
|
|---|
| 531 | ___
|
|---|
| 532 | $code.=<<___;
|
|---|
| 533 | vld1.64 {$K},[$Ktbl,:64]! @ K[i++]
|
|---|
| 534 | vsli.64 $t0,$e,#`64-@Sigma1[0]`
|
|---|
| 535 | vsli.64 $t1,$e,#`64-@Sigma1[1]`
|
|---|
| 536 | vmov $Ch,$e
|
|---|
| 537 | vsli.64 $t2,$e,#`64-@Sigma1[2]`
|
|---|
| 538 | #if $i<16 && defined(__ARMEL__)
|
|---|
| 539 | vrev64.8 @X[$i],@X[$i]
|
|---|
| 540 | #endif
|
|---|
| 541 | veor $t1,$t0
|
|---|
| 542 | vbsl $Ch,$f,$g @ Ch(e,f,g)
|
|---|
| 543 | vshr.u64 $t0,$a,#@Sigma0[0]
|
|---|
| 544 | veor $t2,$t1 @ Sigma1(e)
|
|---|
| 545 | vadd.i64 $T1,$Ch,$h
|
|---|
| 546 | vshr.u64 $t1,$a,#@Sigma0[1]
|
|---|
| 547 | vsli.64 $t0,$a,#`64-@Sigma0[0]`
|
|---|
| 548 | vadd.i64 $T1,$t2
|
|---|
| 549 | vshr.u64 $t2,$a,#@Sigma0[2]
|
|---|
| 550 | vadd.i64 $K,@X[$i%16]
|
|---|
| 551 | vsli.64 $t1,$a,#`64-@Sigma0[1]`
|
|---|
| 552 | veor $Maj,$a,$b
|
|---|
| 553 | vsli.64 $t2,$a,#`64-@Sigma0[2]`
|
|---|
| 554 | veor $h,$t0,$t1
|
|---|
| 555 | vadd.i64 $T1,$K
|
|---|
| 556 | vbsl $Maj,$c,$b @ Maj(a,b,c)
|
|---|
| 557 | veor $h,$t2 @ Sigma0(a)
|
|---|
| 558 | vadd.i64 $d,$T1
|
|---|
| 559 | vadd.i64 $Maj,$T1
|
|---|
| 560 | @ vadd.i64 $h,$Maj
|
|---|
| 561 | ___
|
|---|
| 562 | }
|
|---|
| 563 |
|
|---|
| 564 | sub NEON_16_79() {
|
|---|
| 565 | my $i=shift;
|
|---|
| 566 |
|
|---|
| 567 | if ($i&1) { &NEON_00_15($i,@_); return; }
|
|---|
| 568 |
|
|---|
| 569 | # 2x-vectorized, therefore runs every 2nd round
|
|---|
| 570 | my @X=map("q$_",(0..7)); # view @X as 128-bit vector
|
|---|
| 571 | my ($t0,$t1,$s0,$s1) = map("q$_",(12..15)); # temps
|
|---|
| 572 | my ($d0,$d1,$d2) = map("d$_",(24..26)); # temps from NEON_00_15
|
|---|
| 573 | my $e=@_[4]; # $e from NEON_00_15
|
|---|
| 574 | $i /= 2;
|
|---|
| 575 | $code.=<<___;
|
|---|
| 576 | vshr.u64 $t0,@X[($i+7)%8],#@sigma1[0]
|
|---|
| 577 | vshr.u64 $t1,@X[($i+7)%8],#@sigma1[1]
|
|---|
| 578 | vadd.i64 @_[0],d30 @ h+=Maj from the past
|
|---|
| 579 | vshr.u64 $s1,@X[($i+7)%8],#@sigma1[2]
|
|---|
| 580 | vsli.64 $t0,@X[($i+7)%8],#`64-@sigma1[0]`
|
|---|
| 581 | vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1]
|
|---|
| 582 | vsli.64 $t1,@X[($i+7)%8],#`64-@sigma1[1]`
|
|---|
| 583 | veor $s1,$t0
|
|---|
| 584 | vshr.u64 $t0,$s0,#@sigma0[0]
|
|---|
| 585 | veor $s1,$t1 @ sigma1(X[i+14])
|
|---|
| 586 | vshr.u64 $t1,$s0,#@sigma0[1]
|
|---|
| 587 | vadd.i64 @X[$i%8],$s1
|
|---|
| 588 | vshr.u64 $s1,$s0,#@sigma0[2]
|
|---|
| 589 | vsli.64 $t0,$s0,#`64-@sigma0[0]`
|
|---|
| 590 | vsli.64 $t1,$s0,#`64-@sigma0[1]`
|
|---|
| 591 | vext.8 $s0,@X[($i+4)%8],@X[($i+5)%8],#8 @ X[i+9]
|
|---|
| 592 | veor $s1,$t0
|
|---|
| 593 | vshr.u64 $d0,$e,#@Sigma1[0] @ from NEON_00_15
|
|---|
| 594 | vadd.i64 @X[$i%8],$s0
|
|---|
| 595 | vshr.u64 $d1,$e,#@Sigma1[1] @ from NEON_00_15
|
|---|
| 596 | veor $s1,$t1 @ sigma0(X[i+1])
|
|---|
| 597 | vshr.u64 $d2,$e,#@Sigma1[2] @ from NEON_00_15
|
|---|
| 598 | vadd.i64 @X[$i%8],$s1
|
|---|
| 599 | ___
|
|---|
| 600 | &NEON_00_15(2*$i,@_);
|
|---|
| 601 | }
|
|---|
| 602 |
|
|---|
| 603 | $code.=<<___;
|
|---|
| 604 | #if __ARM_MAX_ARCH__>=7
|
|---|
| 605 | .arch armv7-a
|
|---|
| 606 | .fpu neon
|
|---|
| 607 |
|
|---|
| 608 | .global sha512_block_data_order_neon
|
|---|
| 609 | .type sha512_block_data_order_neon,%function
|
|---|
| 610 | .align 4
|
|---|
| 611 | sha512_block_data_order_neon:
|
|---|
| 612 | .LNEON:
|
|---|
| 613 | dmb @ errata #451034 on early Cortex A8
|
|---|
| 614 | add $len,$inp,$len,lsl#7 @ len to point at the end of inp
|
|---|
| 615 | adr $Ktbl,K512
|
|---|
| 616 | VFP_ABI_PUSH
|
|---|
| 617 | vldmia $ctx,{$A-$H} @ load context
|
|---|
| 618 | .Loop_neon:
|
|---|
| 619 | ___
|
|---|
| 620 | for($i=0;$i<16;$i++) { &NEON_00_15($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 621 | $code.=<<___;
|
|---|
| 622 | mov $cnt,#4
|
|---|
| 623 | .L16_79_neon:
|
|---|
| 624 | subs $cnt,#1
|
|---|
| 625 | ___
|
|---|
| 626 | for(;$i<32;$i++) { &NEON_16_79($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 627 | $code.=<<___;
|
|---|
| 628 | bne .L16_79_neon
|
|---|
| 629 |
|
|---|
| 630 | vadd.i64 $A,d30 @ h+=Maj from the past
|
|---|
| 631 | vldmia $ctx,{d24-d31} @ load context to temp
|
|---|
| 632 | vadd.i64 q8,q12 @ vectorized accumulate
|
|---|
| 633 | vadd.i64 q9,q13
|
|---|
| 634 | vadd.i64 q10,q14
|
|---|
| 635 | vadd.i64 q11,q15
|
|---|
| 636 | vstmia $ctx,{$A-$H} @ save context
|
|---|
| 637 | teq $inp,$len
|
|---|
| 638 | sub $Ktbl,#640 @ rewind K512
|
|---|
| 639 | bne .Loop_neon
|
|---|
| 640 |
|
|---|
| 641 | VFP_ABI_POP
|
|---|
| 642 | ret @ bx lr
|
|---|
| 643 | .size sha512_block_data_order_neon,.-sha512_block_data_order_neon
|
|---|
| 644 | #endif
|
|---|
| 645 | ___
|
|---|
| 646 | }
|
|---|
| 647 | $code.=<<___;
|
|---|
| 648 | .asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
|
|---|
| 649 | .align 2
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| 650 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
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| 651 | .comm OPENSSL_armcap_P,4,4
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| 652 | #endif
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| 653 | ___
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| 654 |
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| 655 | $code =~ s/\`([^\`]*)\`/eval $1/gem;
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| 656 | $code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
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| 657 | $code =~ s/\bret\b/bx lr/gm;
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| 658 |
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| 659 | open SELF,$0;
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| 660 | while(<SELF>) {
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| 661 | next if (/^#!/);
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| 662 | last if (!s/^#/@/ and !/^$/);
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| 663 | print;
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| 664 | }
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| 665 | close SELF;
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| 666 |
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| 667 | print $code;
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| 668 | close STDOUT; # enforce flush
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