| 1 | #! /usr/bin/env perl
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| 2 | # Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | #
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| 4 | # Licensed under the OpenSSL license (the "License"). You may not use
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| 5 | # this file except in compliance with the License. You can obtain a copy
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| 6 | # in the file LICENSE in the source distribution or at
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| 7 | # https://www.openssl.org/source/license.html
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| 8 |
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| 9 | #
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| 10 | # ====================================================================
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| 11 | # Written by Andy Polyakov <[email protected]> for the OpenSSL
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| 12 | # project. The module is, however, dual licensed under OpenSSL and
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| 13 | # CRYPTOGAMS licenses depending on where you obtain it. For further
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| 14 | # details see http://www.openssl.org/~appro/cryptogams/.
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| 15 | # ====================================================================
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| 16 |
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| 17 | # This module doesn't present direct interest for OpenSSL, because it
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| 18 | # doesn't provide better performance for longer keys, at least not on
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| 19 | # in-order-execution cores. While 512-bit RSA sign operations can be
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| 20 | # 65% faster in 64-bit mode, 1024-bit ones are only 15% faster, and
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| 21 | # 4096-bit ones are up to 15% slower. In 32-bit mode it varies from
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| 22 | # 16% improvement for 512-bit RSA sign to -33% for 4096-bit RSA
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| 23 | # verify:-( All comparisons are against bn_mul_mont-free assembler.
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| 24 | # The module might be of interest to embedded system developers, as
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| 25 | # the code is smaller than 1KB, yet offers >3x improvement on MIPS64
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| 26 | # and 75-30% [less for longer keys] on MIPS32 over compiler-generated
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| 27 | # code.
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| 28 |
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| 29 | ######################################################################
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| 30 | # There is a number of MIPS ABI in use, O32 and N32/64 are most
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| 31 | # widely used. Then there is a new contender: NUBI. It appears that if
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| 32 | # one picks the latter, it's possible to arrange code in ABI neutral
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| 33 | # manner. Therefore let's stick to NUBI register layout:
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| 34 | #
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| 35 | ($zero,$at,$t0,$t1,$t2)=map("\$$_",(0..2,24,25));
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| 36 | ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
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| 37 | ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));
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| 38 | ($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));
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| 39 | #
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| 40 | # The return value is placed in $a0. Following coding rules facilitate
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| 41 | # interoperability:
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| 42 | #
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| 43 | # - never ever touch $tp, "thread pointer", former $gp;
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| 44 | # - copy return value to $t0, former $v0 [or to $a0 if you're adapting
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| 45 | # old code];
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| 46 | # - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;
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| 47 | #
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| 48 | # For reference here is register layout for N32/64 MIPS ABIs:
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| 49 | #
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| 50 | # ($zero,$at,$v0,$v1)=map("\$$_",(0..3));
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| 51 | # ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
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| 52 | # ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25));
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| 53 | # ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));
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| 54 | # ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
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| 55 | #
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| 56 | $flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
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| 57 |
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| 58 | if ($flavour =~ /64|n32/i) {
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| 59 | $PTR_ADD="daddu"; # incidentally works even on n32
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| 60 | $PTR_SUB="dsubu"; # incidentally works even on n32
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| 61 | $REG_S="sd";
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| 62 | $REG_L="ld";
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| 63 | $SZREG=8;
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| 64 | } else {
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| 65 | $PTR_ADD="addu";
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| 66 | $PTR_SUB="subu";
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| 67 | $REG_S="sw";
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| 68 | $REG_L="lw";
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| 69 | $SZREG=4;
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| 70 | }
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| 71 | $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? 0x00fff000 : 0x00ff0000;
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| 72 | #
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| 73 | # <[email protected]>
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| 74 | #
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| 75 | ######################################################################
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| 76 |
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| 77 | while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {}
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| 78 | open STDOUT,">$output";
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| 79 |
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| 80 | if ($flavour =~ /64|n32/i) {
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| 81 | $LD="ld";
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| 82 | $ST="sd";
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| 83 | $MULTU="dmultu";
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| 84 | $ADDU="daddu";
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| 85 | $SUBU="dsubu";
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| 86 | $BNSZ=8;
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| 87 | } else {
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| 88 | $LD="lw";
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| 89 | $ST="sw";
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| 90 | $MULTU="multu";
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| 91 | $ADDU="addu";
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| 92 | $SUBU="subu";
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| 93 | $BNSZ=4;
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| 94 | }
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| 95 |
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| 96 | # int bn_mul_mont(
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| 97 | $rp=$a0; # BN_ULONG *rp,
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| 98 | $ap=$a1; # const BN_ULONG *ap,
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| 99 | $bp=$a2; # const BN_ULONG *bp,
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| 100 | $np=$a3; # const BN_ULONG *np,
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| 101 | $n0=$a4; # const BN_ULONG *n0,
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| 102 | $num=$a5; # int num);
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| 103 |
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| 104 | $lo0=$a6;
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| 105 | $hi0=$a7;
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| 106 | $lo1=$t1;
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| 107 | $hi1=$t2;
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| 108 | $aj=$s0;
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| 109 | $bi=$s1;
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| 110 | $nj=$s2;
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| 111 | $tp=$s3;
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| 112 | $alo=$s4;
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| 113 | $ahi=$s5;
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| 114 | $nlo=$s6;
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| 115 | $nhi=$s7;
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| 116 | $tj=$s8;
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| 117 | $i=$s9;
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| 118 | $j=$s10;
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| 119 | $m1=$s11;
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| 120 |
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| 121 | $FRAMESIZE=14;
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| 122 |
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| 123 | $code=<<___;
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| 124 | #include "mips_arch.h"
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| 125 |
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| 126 | .text
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| 127 |
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| 128 | .set noat
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| 129 | .set noreorder
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| 130 |
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| 131 | .align 5
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| 132 | .globl bn_mul_mont
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| 133 | .ent bn_mul_mont
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| 134 | bn_mul_mont:
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| 135 | ___
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| 136 | $code.=<<___ if ($flavour =~ /o32/i);
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| 137 | lw $n0,16($sp)
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| 138 | lw $num,20($sp)
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| 139 | ___
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| 140 | $code.=<<___;
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| 141 | slt $at,$num,4
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| 142 | bnez $at,1f
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| 143 | li $t0,0
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| 144 | slt $at,$num,17 # on in-order CPU
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| 145 | bnez $at,bn_mul_mont_internal
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| 146 | nop
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| 147 | 1: jr $ra
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| 148 | li $a0,0
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| 149 | .end bn_mul_mont
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| 150 |
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| 151 | .align 5
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| 152 | .ent bn_mul_mont_internal
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| 153 | bn_mul_mont_internal:
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| 154 | .frame $fp,$FRAMESIZE*$SZREG,$ra
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| 155 | .mask 0x40000000|$SAVED_REGS_MASK,-$SZREG
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| 156 | $PTR_SUB $sp,$FRAMESIZE*$SZREG
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| 157 | $REG_S $fp,($FRAMESIZE-1)*$SZREG($sp)
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| 158 | $REG_S $s11,($FRAMESIZE-2)*$SZREG($sp)
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| 159 | $REG_S $s10,($FRAMESIZE-3)*$SZREG($sp)
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| 160 | $REG_S $s9,($FRAMESIZE-4)*$SZREG($sp)
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| 161 | $REG_S $s8,($FRAMESIZE-5)*$SZREG($sp)
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| 162 | $REG_S $s7,($FRAMESIZE-6)*$SZREG($sp)
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| 163 | $REG_S $s6,($FRAMESIZE-7)*$SZREG($sp)
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| 164 | $REG_S $s5,($FRAMESIZE-8)*$SZREG($sp)
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| 165 | $REG_S $s4,($FRAMESIZE-9)*$SZREG($sp)
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| 166 | ___
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| 167 | $code.=<<___ if ($flavour =~ /nubi/i);
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| 168 | $REG_S $s3,($FRAMESIZE-10)*$SZREG($sp)
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| 169 | $REG_S $s2,($FRAMESIZE-11)*$SZREG($sp)
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| 170 | $REG_S $s1,($FRAMESIZE-12)*$SZREG($sp)
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| 171 | $REG_S $s0,($FRAMESIZE-13)*$SZREG($sp)
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| 172 | ___
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| 173 | $code.=<<___;
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| 174 | move $fp,$sp
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| 175 |
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| 176 | .set reorder
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| 177 | $LD $n0,0($n0)
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| 178 | $LD $bi,0($bp) # bp[0]
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| 179 | $LD $aj,0($ap) # ap[0]
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| 180 | $LD $nj,0($np) # np[0]
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| 181 |
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| 182 | $PTR_SUB $sp,2*$BNSZ # place for two extra words
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| 183 | sll $num,`log($BNSZ)/log(2)`
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| 184 | li $at,-4096
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| 185 | $PTR_SUB $sp,$num
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| 186 | and $sp,$at
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| 187 |
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| 188 | $MULTU ($aj,$bi)
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| 189 | $LD $ahi,$BNSZ($ap)
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| 190 | $LD $nhi,$BNSZ($np)
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| 191 | mflo ($lo0,$aj,$bi)
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| 192 | mfhi ($hi0,$aj,$bi)
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| 193 | $MULTU ($lo0,$n0)
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| 194 | mflo ($m1,$lo0,$n0)
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| 195 |
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| 196 | $MULTU ($ahi,$bi)
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| 197 | mflo ($alo,$ahi,$bi)
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| 198 | mfhi ($ahi,$ahi,$bi)
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| 199 |
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| 200 | $MULTU ($nj,$m1)
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| 201 | mflo ($lo1,$nj,$m1)
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| 202 | mfhi ($hi1,$nj,$m1)
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| 203 | $MULTU ($nhi,$m1)
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| 204 | $ADDU $lo1,$lo0
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| 205 | sltu $at,$lo1,$lo0
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| 206 | $ADDU $hi1,$at
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| 207 | mflo ($nlo,$nhi,$m1)
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| 208 | mfhi ($nhi,$nhi,$m1)
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| 209 |
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| 210 | move $tp,$sp
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| 211 | li $j,2*$BNSZ
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| 212 | .align 4
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| 213 | .L1st:
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| 214 | .set noreorder
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| 215 | $PTR_ADD $aj,$ap,$j
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| 216 | $PTR_ADD $nj,$np,$j
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| 217 | $LD $aj,($aj)
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| 218 | $LD $nj,($nj)
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| 219 |
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| 220 | $MULTU ($aj,$bi)
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| 221 | $ADDU $lo0,$alo,$hi0
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| 222 | $ADDU $lo1,$nlo,$hi1
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| 223 | sltu $at,$lo0,$hi0
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| 224 | sltu $t0,$lo1,$hi1
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| 225 | $ADDU $hi0,$ahi,$at
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| 226 | $ADDU $hi1,$nhi,$t0
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| 227 | mflo ($alo,$aj,$bi)
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| 228 | mfhi ($ahi,$aj,$bi)
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| 229 |
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| 230 | $ADDU $lo1,$lo0
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| 231 | sltu $at,$lo1,$lo0
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| 232 | $MULTU ($nj,$m1)
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| 233 | $ADDU $hi1,$at
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| 234 | addu $j,$BNSZ
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| 235 | $ST $lo1,($tp)
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| 236 | sltu $t0,$j,$num
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| 237 | mflo ($nlo,$nj,$m1)
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| 238 | mfhi ($nhi,$nj,$m1)
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| 239 |
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| 240 | bnez $t0,.L1st
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| 241 | $PTR_ADD $tp,$BNSZ
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| 242 | .set reorder
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| 243 |
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| 244 | $ADDU $lo0,$alo,$hi0
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| 245 | sltu $at,$lo0,$hi0
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| 246 | $ADDU $hi0,$ahi,$at
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| 247 |
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| 248 | $ADDU $lo1,$nlo,$hi1
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| 249 | sltu $t0,$lo1,$hi1
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| 250 | $ADDU $hi1,$nhi,$t0
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| 251 | $ADDU $lo1,$lo0
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| 252 | sltu $at,$lo1,$lo0
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| 253 | $ADDU $hi1,$at
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| 254 |
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| 255 | $ST $lo1,($tp)
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| 256 |
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| 257 | $ADDU $hi1,$hi0
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| 258 | sltu $at,$hi1,$hi0
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| 259 | $ST $hi1,$BNSZ($tp)
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| 260 | $ST $at,2*$BNSZ($tp)
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| 261 |
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| 262 | li $i,$BNSZ
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| 263 | .align 4
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| 264 | .Louter:
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| 265 | $PTR_ADD $bi,$bp,$i
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| 266 | $LD $bi,($bi)
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| 267 | $LD $aj,($ap)
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| 268 | $LD $ahi,$BNSZ($ap)
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| 269 | $LD $tj,($sp)
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| 270 |
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| 271 | $MULTU ($aj,$bi)
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| 272 | $LD $nj,($np)
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| 273 | $LD $nhi,$BNSZ($np)
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| 274 | mflo ($lo0,$aj,$bi)
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| 275 | mfhi ($hi0,$aj,$bi)
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| 276 | $ADDU $lo0,$tj
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| 277 | $MULTU ($lo0,$n0)
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| 278 | sltu $at,$lo0,$tj
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| 279 | $ADDU $hi0,$at
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| 280 | mflo ($m1,$lo0,$n0)
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| 281 |
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| 282 | $MULTU ($ahi,$bi)
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| 283 | mflo ($alo,$ahi,$bi)
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| 284 | mfhi ($ahi,$ahi,$bi)
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| 285 |
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| 286 | $MULTU ($nj,$m1)
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| 287 | mflo ($lo1,$nj,$m1)
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| 288 | mfhi ($hi1,$nj,$m1)
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| 289 |
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| 290 | $MULTU ($nhi,$m1)
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| 291 | $ADDU $lo1,$lo0
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| 292 | sltu $at,$lo1,$lo0
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| 293 | $ADDU $hi1,$at
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| 294 | mflo ($nlo,$nhi,$m1)
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| 295 | mfhi ($nhi,$nhi,$m1)
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| 296 |
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| 297 | move $tp,$sp
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| 298 | li $j,2*$BNSZ
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| 299 | $LD $tj,$BNSZ($tp)
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| 300 | .align 4
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| 301 | .Linner:
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| 302 | .set noreorder
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| 303 | $PTR_ADD $aj,$ap,$j
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| 304 | $PTR_ADD $nj,$np,$j
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| 305 | $LD $aj,($aj)
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| 306 | $LD $nj,($nj)
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| 307 |
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| 308 | $MULTU ($aj,$bi)
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| 309 | $ADDU $lo0,$alo,$hi0
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| 310 | $ADDU $lo1,$nlo,$hi1
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| 311 | sltu $at,$lo0,$hi0
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| 312 | sltu $t0,$lo1,$hi1
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| 313 | $ADDU $hi0,$ahi,$at
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| 314 | $ADDU $hi1,$nhi,$t0
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| 315 | mflo ($alo,$aj,$bi)
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| 316 | mfhi ($ahi,$aj,$bi)
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| 317 |
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| 318 | $ADDU $lo0,$tj
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| 319 | addu $j,$BNSZ
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| 320 | $MULTU ($nj,$m1)
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| 321 | sltu $at,$lo0,$tj
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| 322 | $ADDU $lo1,$lo0
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| 323 | $ADDU $hi0,$at
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| 324 | sltu $t0,$lo1,$lo0
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| 325 | $LD $tj,2*$BNSZ($tp)
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| 326 | $ADDU $hi1,$t0
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| 327 | sltu $at,$j,$num
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| 328 | mflo ($nlo,$nj,$m1)
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| 329 | mfhi ($nhi,$nj,$m1)
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| 330 | $ST $lo1,($tp)
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| 331 | bnez $at,.Linner
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| 332 | $PTR_ADD $tp,$BNSZ
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| 333 | .set reorder
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| 334 |
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| 335 | $ADDU $lo0,$alo,$hi0
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| 336 | sltu $at,$lo0,$hi0
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| 337 | $ADDU $hi0,$ahi,$at
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| 338 | $ADDU $lo0,$tj
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| 339 | sltu $t0,$lo0,$tj
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| 340 | $ADDU $hi0,$t0
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| 341 |
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| 342 | $LD $tj,2*$BNSZ($tp)
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| 343 | $ADDU $lo1,$nlo,$hi1
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| 344 | sltu $at,$lo1,$hi1
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| 345 | $ADDU $hi1,$nhi,$at
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| 346 | $ADDU $lo1,$lo0
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| 347 | sltu $t0,$lo1,$lo0
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| 348 | $ADDU $hi1,$t0
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| 349 | $ST $lo1,($tp)
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| 350 |
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| 351 | $ADDU $lo1,$hi1,$hi0
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| 352 | sltu $hi1,$lo1,$hi0
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| 353 | $ADDU $lo1,$tj
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| 354 | sltu $at,$lo1,$tj
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| 355 | $ADDU $hi1,$at
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| 356 | $ST $lo1,$BNSZ($tp)
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| 357 | $ST $hi1,2*$BNSZ($tp)
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| 358 |
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| 359 | addu $i,$BNSZ
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| 360 | sltu $t0,$i,$num
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| 361 | bnez $t0,.Louter
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| 362 | |
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| 363 |
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| 364 | .set noreorder
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| 365 | $PTR_ADD $tj,$sp,$num # &tp[num]
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| 366 | move $tp,$sp
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| 367 | move $ap,$sp
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| 368 | li $hi0,0 # clear borrow bit
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| 369 |
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| 370 | .align 4
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| 371 | .Lsub: $LD $lo0,($tp)
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| 372 | $LD $lo1,($np)
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| 373 | $PTR_ADD $tp,$BNSZ
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| 374 | $PTR_ADD $np,$BNSZ
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| 375 | $SUBU $lo1,$lo0,$lo1 # tp[i]-np[i]
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| 376 | sgtu $at,$lo1,$lo0
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| 377 | $SUBU $lo0,$lo1,$hi0
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| 378 | sgtu $hi0,$lo0,$lo1
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| 379 | $ST $lo0,($rp)
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| 380 | or $hi0,$at
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| 381 | sltu $at,$tp,$tj
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| 382 | bnez $at,.Lsub
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| 383 | $PTR_ADD $rp,$BNSZ
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| 384 |
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| 385 | $SUBU $hi0,$hi1,$hi0 # handle upmost overflow bit
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| 386 | move $tp,$sp
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| 387 | $PTR_SUB $rp,$num # restore rp
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| 388 | not $hi1,$hi0
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| 389 |
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| 390 | .Lcopy: $LD $nj,($tp) # conditional move
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| 391 | $LD $aj,($rp)
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| 392 | $ST $zero,($tp)
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| 393 | $PTR_ADD $tp,$BNSZ
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| 394 | and $nj,$hi0
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| 395 | and $aj,$hi1
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| 396 | or $aj,$nj
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| 397 | sltu $at,$tp,$tj
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| 398 | $ST $aj,($rp)
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| 399 | bnez $at,.Lcopy
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| 400 | $PTR_ADD $rp,$BNSZ
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| 401 |
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| 402 | li $a0,1
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| 403 | li $t0,1
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| 404 |
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| 405 | .set noreorder
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| 406 | move $sp,$fp
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| 407 | $REG_L $fp,($FRAMESIZE-1)*$SZREG($sp)
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| 408 | $REG_L $s11,($FRAMESIZE-2)*$SZREG($sp)
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| 409 | $REG_L $s10,($FRAMESIZE-3)*$SZREG($sp)
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| 410 | $REG_L $s9,($FRAMESIZE-4)*$SZREG($sp)
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| 411 | $REG_L $s8,($FRAMESIZE-5)*$SZREG($sp)
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| 412 | $REG_L $s7,($FRAMESIZE-6)*$SZREG($sp)
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| 413 | $REG_L $s6,($FRAMESIZE-7)*$SZREG($sp)
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| 414 | $REG_L $s5,($FRAMESIZE-8)*$SZREG($sp)
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| 415 | $REG_L $s4,($FRAMESIZE-9)*$SZREG($sp)
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| 416 | ___
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| 417 | $code.=<<___ if ($flavour =~ /nubi/i);
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| 418 | $REG_L $s3,($FRAMESIZE-10)*$SZREG($sp)
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| 419 | $REG_L $s2,($FRAMESIZE-11)*$SZREG($sp)
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| 420 | $REG_L $s1,($FRAMESIZE-12)*$SZREG($sp)
|
|---|
| 421 | $REG_L $s0,($FRAMESIZE-13)*$SZREG($sp)
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| 422 | ___
|
|---|
| 423 | $code.=<<___;
|
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| 424 | jr $ra
|
|---|
| 425 | $PTR_ADD $sp,$FRAMESIZE*$SZREG
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| 426 | .end bn_mul_mont_internal
|
|---|
| 427 | .rdata
|
|---|
| 428 | .asciiz "Montgomery Multiplication for MIPS, CRYPTOGAMS by <appro\@openssl.org>"
|
|---|
| 429 | ___
|
|---|
| 430 |
|
|---|
| 431 | $code =~ s/\`([^\`]*)\`/eval $1/gem;
|
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| 432 |
|
|---|
| 433 | print $code;
|
|---|
| 434 | close STDOUT or die "error closing STDOUT: $!";
|
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