| 1 | #! /usr/bin/env perl
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| 2 | # Copyright 1998-2020 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | #
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| 4 | # Licensed under the OpenSSL license (the "License"). You may not use
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| 5 | # this file except in compliance with the License. You can obtain a copy
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| 6 | # in the file LICENSE in the source distribution or at
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| 7 | # https://www.openssl.org/source/license.html
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| 8 |
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| 9 |
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| 10 | # ====================================================================
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| 11 | # [Re]written by Andy Polyakov <[email protected]> for the OpenSSL
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| 12 | # project. The module is, however, dual licensed under OpenSSL and
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| 13 | # CRYPTOGAMS licenses depending on where you obtain it. For further
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| 14 | # details see http://www.openssl.org/~appro/cryptogams/.
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| 15 | # ====================================================================
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| 16 |
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| 17 | # At some point it became apparent that the original SSLeay RC4
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| 18 | # assembler implementation performs suboptimally on latest IA-32
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| 19 | # microarchitectures. After re-tuning performance has changed as
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| 20 | # following:
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| 21 | #
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| 22 | # Pentium -10%
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| 23 | # Pentium III +12%
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| 24 | # AMD +50%(*)
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| 25 | # P4 +250%(**)
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| 26 | #
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| 27 | # (*) This number is actually a trade-off:-) It's possible to
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| 28 | # achieve +72%, but at the cost of -48% off PIII performance.
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| 29 | # In other words code performing further 13% faster on AMD
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| 30 | # would perform almost 2 times slower on Intel PIII...
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| 31 | # For reference! This code delivers ~80% of rc4-amd64.pl
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| 32 | # performance on the same Opteron machine.
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| 33 | # (**) This number requires compressed key schedule set up by
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| 34 | # RC4_set_key [see commentary below for further details].
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| 35 |
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| 36 | # May 2011
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| 37 | #
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| 38 | # Optimize for Core2 and Westmere [and incidentally Opteron]. Current
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| 39 | # performance in cycles per processed byte (less is better) and
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| 40 | # improvement relative to previous version of this module is:
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| 41 | #
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| 42 | # Pentium 10.2 # original numbers
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| 43 | # Pentium III 7.8(*)
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| 44 | # Intel P4 7.5
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| 45 | #
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| 46 | # Opteron 6.1/+20% # new MMX numbers
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| 47 | # Core2 5.3/+67%(**)
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| 48 | # Westmere 5.1/+94%(**)
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| 49 | # Sandy Bridge 5.0/+8%
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| 50 | # Atom 12.6/+6%
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| 51 | # VIA Nano 6.4/+9%
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| 52 | # Ivy Bridge 4.9/±0%
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| 53 | # Bulldozer 4.9/+15%
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| 54 | #
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| 55 | # (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
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| 56 | # but this specific code performs poorly on Core2. And vice
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| 57 | # versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
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| 58 | # poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
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| 59 | # [anymore], I chose to discard PIII-specific code path and opt
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| 60 | # for original IALU-only code, which is why MMX/SSE code path
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| 61 | # is guarded by SSE2 bit (see below), not MMX/SSE.
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| 62 | # (**) Performance vs. block size on Core2 and Westmere had a maximum
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| 63 | # at ... 64 bytes block size. And it was quite a maximum, 40-60%
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| 64 | # in comparison to largest 8KB block size. Above improvement
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| 65 | # coefficients are for the largest block size.
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| 66 |
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| 67 | $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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| 68 | push(@INC,"${dir}","${dir}../../perlasm");
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| 69 | require "x86asm.pl";
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| 70 |
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| 71 | $output=pop;
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| 72 | open STDOUT,">$output";
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| 73 |
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| 74 | &asm_init($ARGV[0],$x86only = $ARGV[$#ARGV] eq "386");
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| 75 |
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| 76 | $xx="eax";
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| 77 | $yy="ebx";
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| 78 | $tx="ecx";
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| 79 | $ty="edx";
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| 80 | $inp="esi";
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| 81 | $out="ebp";
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| 82 | $dat="edi";
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| 83 |
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| 84 | sub RC4_loop {
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| 85 | my $i=shift;
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| 86 | my $func = ($i==0)?*mov:*or;
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| 87 |
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| 88 | &add (&LB($yy),&LB($tx));
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| 89 | &mov ($ty,&DWP(0,$dat,$yy,4));
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| 90 | &mov (&DWP(0,$dat,$yy,4),$tx);
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| 91 | &mov (&DWP(0,$dat,$xx,4),$ty);
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| 92 | &add ($ty,$tx);
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| 93 | &inc (&LB($xx));
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| 94 | &and ($ty,0xff);
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| 95 | &ror ($out,8) if ($i!=0);
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| 96 | if ($i<3) {
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| 97 | &mov ($tx,&DWP(0,$dat,$xx,4));
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| 98 | } else {
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| 99 | &mov ($tx,&wparam(3)); # reload [re-biased] out
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| 100 | }
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| 101 | &$func ($out,&DWP(0,$dat,$ty,4));
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| 102 | }
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| 103 |
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| 104 | if ($alt=0) {
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| 105 | # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
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| 106 | # but ~40% slower on Core2 and Westmere... Attempt to add movz
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| 107 | # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
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| 108 | # on Core2 with movz it's almost 20% slower than below alternative
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| 109 | # code... Yes, it's a total mess...
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| 110 | my @XX=($xx,$out);
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| 111 | $RC4_loop_mmx = sub { # SSE actually...
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| 112 | my $i=shift;
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| 113 | my $j=$i<=0?0:$i>>1;
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| 114 | my $mm=$i<=0?"mm0":"mm".($i&1);
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| 115 |
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| 116 | &add (&LB($yy),&LB($tx));
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| 117 | &lea (@XX[1],&DWP(1,@XX[0]));
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| 118 | &pxor ("mm2","mm0") if ($i==0);
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| 119 | &psllq ("mm1",8) if ($i==0);
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| 120 | &and (@XX[1],0xff);
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| 121 | &pxor ("mm0","mm0") if ($i<=0);
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| 122 | &mov ($ty,&DWP(0,$dat,$yy,4));
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| 123 | &mov (&DWP(0,$dat,$yy,4),$tx);
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| 124 | &pxor ("mm1","mm2") if ($i==0);
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| 125 | &mov (&DWP(0,$dat,$XX[0],4),$ty);
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| 126 | &add (&LB($ty),&LB($tx));
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| 127 | &movd (@XX[0],"mm7") if ($i==0);
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| 128 | &mov ($tx,&DWP(0,$dat,@XX[1],4));
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| 129 | &pxor ("mm1","mm1") if ($i==1);
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| 130 | &movq ("mm2",&QWP(0,$inp)) if ($i==1);
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| 131 | &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
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| 132 | &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
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| 133 |
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| 134 | push (@XX,shift(@XX)) if ($i>=0);
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| 135 | }
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| 136 | } else {
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| 137 | # Using pinsrw here improves performance on Intel CPUs by 2-3%, but
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| 138 | # brings down AMD by 7%...
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| 139 | $RC4_loop_mmx = sub {
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| 140 | my $i=shift;
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| 141 |
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| 142 | &add (&LB($yy),&LB($tx));
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| 143 | &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
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| 144 | &mov ($ty,&DWP(0,$dat,$yy,4));
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| 145 | &mov (&DWP(0,$dat,$yy,4),$tx);
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| 146 | &mov (&DWP(0,$dat,$xx,4),$ty);
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| 147 | &inc ($xx);
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| 148 | &add ($ty,$tx);
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| 149 | &movz ($xx,&LB($xx)); # (*)
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| 150 | &movz ($ty,&LB($ty)); # (*)
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| 151 | &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
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| 152 | &movq ("mm0",&QWP(0,$inp)) if ($i<=0);
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| 153 | &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
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| 154 | &mov ($tx,&DWP(0,$dat,$xx,4));
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| 155 | &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
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| 156 |
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| 157 | # (*) This is the key to Core2 and Westmere performance.
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| 158 | # Without movz out-of-order execution logic confuses
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| 159 | # itself and fails to reorder loads and stores. Problem
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| 160 | # appears to be fixed in Sandy Bridge...
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| 161 | }
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| 162 | }
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| 163 |
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| 164 | &external_label("OPENSSL_ia32cap_P");
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| 165 |
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| 166 | # void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
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| 167 | &function_begin("RC4");
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| 168 | &mov ($dat,&wparam(0)); # load key schedule pointer
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| 169 | &mov ($ty, &wparam(1)); # load len
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| 170 | &mov ($inp,&wparam(2)); # load inp
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| 171 | &mov ($out,&wparam(3)); # load out
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| 172 |
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| 173 | &xor ($xx,$xx); # avoid partial register stalls
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| 174 | &xor ($yy,$yy);
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| 175 |
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| 176 | &cmp ($ty,0); # safety net
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| 177 | &je (&label("abort"));
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| 178 |
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| 179 | &mov (&LB($xx),&BP(0,$dat)); # load key->x
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| 180 | &mov (&LB($yy),&BP(4,$dat)); # load key->y
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| 181 | &add ($dat,8);
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| 182 |
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| 183 | &lea ($tx,&DWP(0,$inp,$ty));
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| 184 | &sub ($out,$inp); # re-bias out
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| 185 | &mov (&wparam(1),$tx); # save input+len
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| 186 |
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| 187 | &inc (&LB($xx));
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| 188 |
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| 189 | # detect compressed key schedule...
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| 190 | &cmp (&DWP(256,$dat),-1);
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| 191 | &je (&label("RC4_CHAR"));
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| 192 |
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| 193 | &mov ($tx,&DWP(0,$dat,$xx,4));
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| 194 |
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| 195 | &and ($ty,-4); # how many 4-byte chunks?
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| 196 | &jz (&label("loop1"));
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| 197 |
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| 198 | &mov (&wparam(3),$out); # $out as accumulator in these loops
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| 199 | if ($x86only) {
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| 200 | &jmp (&label("go4loop4"));
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| 201 | } else {
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| 202 | &test ($ty,-8);
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| 203 | &jz (&label("go4loop4"));
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| 204 |
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| 205 | &picmeup($out,"OPENSSL_ia32cap_P");
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| 206 | &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
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| 207 | &jnc (&label("go4loop4"));
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| 208 |
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| 209 | &mov ($out,&wparam(3)) if (!$alt);
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| 210 | &movd ("mm7",&wparam(3)) if ($alt);
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| 211 | &and ($ty,-8);
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| 212 | &lea ($ty,&DWP(-8,$inp,$ty));
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| 213 | &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
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| 214 |
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| 215 | &$RC4_loop_mmx(-1);
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| 216 | &jmp(&label("loop_mmx_enter"));
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| 217 |
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| 218 | &set_label("loop_mmx",16);
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| 219 | &$RC4_loop_mmx(0);
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| 220 | &set_label("loop_mmx_enter");
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| 221 | for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
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| 222 | &mov ($ty,$yy);
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| 223 | &xor ($yy,$yy); # this is second key to Core2
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| 224 | &mov (&LB($yy),&LB($ty)); # and Westmere performance...
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| 225 | &cmp ($inp,&DWP(-4,$dat));
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| 226 | &lea ($inp,&DWP(8,$inp));
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| 227 | &jb (&label("loop_mmx"));
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| 228 |
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| 229 | if ($alt) {
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| 230 | &movd ($out,"mm7");
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| 231 | &pxor ("mm2","mm0");
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| 232 | &psllq ("mm1",8);
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| 233 | &pxor ("mm1","mm2");
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| 234 | &movq (&QWP(-8,$out,$inp),"mm1");
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| 235 | } else {
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| 236 | &psllq ("mm1",56);
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| 237 | &pxor ("mm2","mm1");
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| 238 | &movq (&QWP(-8,$out,$inp),"mm2");
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| 239 | }
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| 240 | &emms ();
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| 241 |
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| 242 | &cmp ($inp,&wparam(1)); # compare to input+len
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| 243 | &je (&label("done"));
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| 244 | &jmp (&label("loop1"));
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| 245 | }
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| 246 |
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| 247 | &set_label("go4loop4",16);
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| 248 | &lea ($ty,&DWP(-4,$inp,$ty));
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| 249 | &mov (&wparam(2),$ty); # save input+(len/4)*4-4
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| 250 |
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| 251 | &set_label("loop4");
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| 252 | for ($i=0;$i<4;$i++) { RC4_loop($i); }
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| 253 | &ror ($out,8);
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| 254 | &xor ($out,&DWP(0,$inp));
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| 255 | &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
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| 256 | &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
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| 257 | &lea ($inp,&DWP(4,$inp));
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| 258 | &mov ($tx,&DWP(0,$dat,$xx,4));
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| 259 | &jb (&label("loop4"));
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| 260 |
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| 261 | &cmp ($inp,&wparam(1)); # compare to input+len
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| 262 | &je (&label("done"));
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| 263 | &mov ($out,&wparam(3)); # restore $out
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| 264 |
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| 265 | &set_label("loop1",16);
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| 266 | &add (&LB($yy),&LB($tx));
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| 267 | &mov ($ty,&DWP(0,$dat,$yy,4));
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| 268 | &mov (&DWP(0,$dat,$yy,4),$tx);
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| 269 | &mov (&DWP(0,$dat,$xx,4),$ty);
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| 270 | &add ($ty,$tx);
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| 271 | &inc (&LB($xx));
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| 272 | &and ($ty,0xff);
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| 273 | &mov ($ty,&DWP(0,$dat,$ty,4));
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| 274 | &xor (&LB($ty),&BP(0,$inp));
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| 275 | &lea ($inp,&DWP(1,$inp));
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| 276 | &mov ($tx,&DWP(0,$dat,$xx,4));
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| 277 | &cmp ($inp,&wparam(1)); # compare to input+len
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| 278 | &mov (&BP(-1,$out,$inp),&LB($ty));
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| 279 | &jb (&label("loop1"));
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| 280 |
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| 281 | &jmp (&label("done"));
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| 282 |
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| 283 | # this is essentially Intel P4 specific codepath...
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| 284 | &set_label("RC4_CHAR",16);
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| 285 | &movz ($tx,&BP(0,$dat,$xx));
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| 286 | # strangely enough unrolled loop performs over 20% slower...
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| 287 | &set_label("cloop1");
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| 288 | &add (&LB($yy),&LB($tx));
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| 289 | &movz ($ty,&BP(0,$dat,$yy));
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| 290 | &mov (&BP(0,$dat,$yy),&LB($tx));
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| 291 | &mov (&BP(0,$dat,$xx),&LB($ty));
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| 292 | &add (&LB($ty),&LB($tx));
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| 293 | &movz ($ty,&BP(0,$dat,$ty));
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| 294 | &add (&LB($xx),1);
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| 295 | &xor (&LB($ty),&BP(0,$inp));
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| 296 | &lea ($inp,&DWP(1,$inp));
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| 297 | &movz ($tx,&BP(0,$dat,$xx));
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| 298 | &cmp ($inp,&wparam(1));
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| 299 | &mov (&BP(-1,$out,$inp),&LB($ty));
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| 300 | &jb (&label("cloop1"));
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| 301 |
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| 302 | &set_label("done");
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| 303 | &dec (&LB($xx));
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| 304 | &mov (&DWP(-4,$dat),$yy); # save key->y
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| 305 | &mov (&BP(-8,$dat),&LB($xx)); # save key->x
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| 306 | &set_label("abort");
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| 307 | &function_end("RC4");
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| 308 |
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| 309 | ########################################################################
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| 310 |
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| 311 | $inp="esi";
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| 312 | $out="edi";
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| 313 | $idi="ebp";
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| 314 | $ido="ecx";
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| 315 | $idx="edx";
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| 316 |
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| 317 | # void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
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| 318 | &function_begin("RC4_set_key");
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| 319 | &mov ($out,&wparam(0)); # load key
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| 320 | &mov ($idi,&wparam(1)); # load len
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| 321 | &mov ($inp,&wparam(2)); # load data
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| 322 | &picmeup($idx,"OPENSSL_ia32cap_P");
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| 323 |
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| 324 | &lea ($out,&DWP(2*4,$out)); # &key->data
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| 325 | &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
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| 326 | &neg ($idi);
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| 327 | &xor ("eax","eax");
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| 328 | &mov (&DWP(-4,$out),$idi); # borrow key->y
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| 329 |
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| 330 | &bt (&DWP(0,$idx),20); # check for bit#20
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| 331 | &jc (&label("c1stloop"));
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| 332 |
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| 333 | &set_label("w1stloop",16);
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| 334 | &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
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| 335 | &add (&LB("eax"),1); # i++;
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| 336 | &jnc (&label("w1stloop"));
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| 337 |
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| 338 | &xor ($ido,$ido);
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| 339 | &xor ($idx,$idx);
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| 340 |
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| 341 | &set_label("w2ndloop",16);
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| 342 | &mov ("eax",&DWP(0,$out,$ido,4));
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| 343 | &add (&LB($idx),&BP(0,$inp,$idi));
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| 344 | &add (&LB($idx),&LB("eax"));
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| 345 | &add ($idi,1);
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| 346 | &mov ("ebx",&DWP(0,$out,$idx,4));
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| 347 | &jnz (&label("wnowrap"));
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| 348 | &mov ($idi,&DWP(-4,$out));
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| 349 | &set_label("wnowrap");
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| 350 | &mov (&DWP(0,$out,$idx,4),"eax");
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| 351 | &mov (&DWP(0,$out,$ido,4),"ebx");
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| 352 | &add (&LB($ido),1);
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| 353 | &jnc (&label("w2ndloop"));
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| 354 | &jmp (&label("exit"));
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| 355 |
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| 356 | # Unlike all other x86 [and x86_64] implementations, Intel P4 core
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| 357 | # [including EM64T] was found to perform poorly with above "32-bit" key
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| 358 | # schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
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| 359 | # assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
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| 360 | # a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
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| 361 | # schedule for x86[_64], because non-P4 implementations suffer from
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| 362 | # significant performance losses then, e.g. PIII exhibits >2x
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| 363 | # deterioration, and so does Opteron. In order to assure optimal
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| 364 | # all-round performance, we detect P4 at run-time and set up compressed
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| 365 | # key schedule, which is recognized by RC4 procedure.
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| 366 |
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| 367 | &set_label("c1stloop",16);
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| 368 | &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
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| 369 | &add (&LB("eax"),1); # i++;
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| 370 | &jnc (&label("c1stloop"));
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| 371 |
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| 372 | &xor ($ido,$ido);
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| 373 | &xor ($idx,$idx);
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| 374 | &xor ("ebx","ebx");
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| 375 |
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| 376 | &set_label("c2ndloop",16);
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| 377 | &mov (&LB("eax"),&BP(0,$out,$ido));
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| 378 | &add (&LB($idx),&BP(0,$inp,$idi));
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| 379 | &add (&LB($idx),&LB("eax"));
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| 380 | &add ($idi,1);
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| 381 | &mov (&LB("ebx"),&BP(0,$out,$idx));
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| 382 | &jnz (&label("cnowrap"));
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| 383 | &mov ($idi,&DWP(-4,$out));
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| 384 | &set_label("cnowrap");
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| 385 | &mov (&BP(0,$out,$idx),&LB("eax"));
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| 386 | &mov (&BP(0,$out,$ido),&LB("ebx"));
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| 387 | &add (&LB($ido),1);
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| 388 | &jnc (&label("c2ndloop"));
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| 389 |
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| 390 | &mov (&DWP(256,$out),-1); # mark schedule as compressed
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| 391 |
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| 392 | &set_label("exit");
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| 393 | &xor ("eax","eax");
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| 394 | &mov (&DWP(-8,$out),"eax"); # key->x=0;
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| 395 | &mov (&DWP(-4,$out),"eax"); # key->y=0;
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| 396 | &function_end("RC4_set_key");
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| 397 |
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| 398 | # const char *RC4_options(void);
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| 399 | &function_begin_B("RC4_options");
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| 400 | &call (&label("pic_point"));
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| 401 | &set_label("pic_point");
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| 402 | &blindpop("eax");
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| 403 | &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
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| 404 | &picmeup("edx","OPENSSL_ia32cap_P");
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| 405 | &mov ("edx",&DWP(0,"edx"));
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| 406 | &bt ("edx",20);
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| 407 | &jc (&label("1xchar"));
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| 408 | &bt ("edx",26);
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| 409 | &jnc (&label("ret"));
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| 410 | &add ("eax",25);
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| 411 | &ret ();
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| 412 | &set_label("1xchar");
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| 413 | &add ("eax",12);
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| 414 | &set_label("ret");
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| 415 | &ret ();
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| 416 | &set_label("opts",64);
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| 417 | &asciz ("rc4(4x,int)");
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| 418 | &asciz ("rc4(1x,char)");
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| 419 | &asciz ("rc4(8x,mmx)");
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| 420 | &asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
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| 421 | &align (64);
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|---|
| 422 | &function_end_B("RC4_options");
|
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| 423 |
|
|---|
| 424 | &asm_finish();
|
|---|
| 425 |
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| 426 | close STDOUT or die "error closing STDOUT: $!";
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