| 1 | #! /usr/bin/env perl
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| 2 | # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | #
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| 4 | # Licensed under the OpenSSL license (the "License"). You may not use
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| 5 | # this file except in compliance with the License. You can obtain a copy
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| 6 | # in the file LICENSE in the source distribution or at
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| 7 | # https://www.openssl.org/source/license.html
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| 8 |
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| 9 |
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| 10 | # ====================================================================
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| 11 | # Written by Andy Polyakov <[email protected]> for the OpenSSL
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| 12 | # project. The module is, however, dual licensed under OpenSSL and
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| 13 | # CRYPTOGAMS licenses depending on where you obtain it. For further
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| 14 | # details see http://www.openssl.org/~appro/cryptogams/.
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| 15 | # ====================================================================
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| 16 |
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| 17 | # January 2009
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| 18 | #
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| 19 | # Provided that UltraSPARC VIS instructions are pipe-lined(*) and
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| 20 | # pairable(*) with IALU ones, offloading of Xupdate to the UltraSPARC
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| 21 | # Graphic Unit would make it possible to achieve higher instruction-
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| 22 | # level parallelism, ILP, and thus higher performance. It should be
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| 23 | # explicitly noted that ILP is the keyword, and it means that this
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| 24 | # code would be unsuitable for cores like UltraSPARC-Tx. The idea is
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| 25 | # not really novel, Sun had VIS-powered implementation for a while.
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| 26 | # Unlike Sun's implementation this one can process multiple unaligned
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| 27 | # input blocks, and as such works as drop-in replacement for OpenSSL
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| 28 | # sha1_block_data_order. Performance improvement was measured to be
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| 29 | # 40% over pure IALU sha1-sparcv9.pl on UltraSPARC-IIi, but 12% on
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| 30 | # UltraSPARC-III. See below for discussion...
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| 31 | #
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| 32 | # The module does not present direct interest for OpenSSL, because
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| 33 | # it doesn't provide better performance on contemporary SPARCv9 CPUs,
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| 34 | # UltraSPARC-Tx and SPARC64-V[II] to be specific. Those who feel they
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| 35 | # absolutely must score on UltraSPARC-I-IV can simply replace
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| 36 | # crypto/sha/asm/sha1-sparcv9.pl with this module.
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| 37 | #
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| 38 | # (*) "Pipe-lined" means that even if it takes several cycles to
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| 39 | # complete, next instruction using same functional unit [but not
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| 40 | # depending on the result of the current instruction] can start
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| 41 | # execution without having to wait for the unit. "Pairable"
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| 42 | # means that two [or more] independent instructions can be
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| 43 | # issued at the very same time.
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| 44 |
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| 45 | $bits=32;
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| 46 | for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
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| 47 | if ($bits==64) { $bias=2047; $frame=192; }
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| 48 | else { $bias=0; $frame=112; }
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| 49 |
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| 50 | $output=shift;
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| 51 | open STDOUT,">$output";
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| 52 |
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| 53 | $ctx="%i0";
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| 54 | $inp="%i1";
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| 55 | $len="%i2";
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| 56 | $tmp0="%i3";
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| 57 | $tmp1="%i4";
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| 58 | $tmp2="%i5";
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| 59 | $tmp3="%g5";
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| 60 |
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| 61 | $base="%g1";
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| 62 | $align="%g4";
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| 63 | $Xfer="%o5";
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| 64 | $nXfer=$tmp3;
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| 65 | $Xi="%o7";
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| 66 |
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| 67 | $A="%l0";
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| 68 | $B="%l1";
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| 69 | $C="%l2";
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| 70 | $D="%l3";
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| 71 | $E="%l4";
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| 72 | @V=($A,$B,$C,$D,$E);
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| 73 |
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| 74 | $Actx="%o0";
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| 75 | $Bctx="%o1";
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| 76 | $Cctx="%o2";
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| 77 | $Dctx="%o3";
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| 78 | $Ectx="%o4";
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| 79 |
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| 80 | $fmul="%f32";
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| 81 | $VK_00_19="%f34";
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| 82 | $VK_20_39="%f36";
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| 83 | $VK_40_59="%f38";
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| 84 | $VK_60_79="%f40";
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| 85 | @VK=($VK_00_19,$VK_20_39,$VK_40_59,$VK_60_79);
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| 86 | @X=("%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
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| 87 | "%f8", "%f9","%f10","%f11","%f12","%f13","%f14","%f15","%f16");
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| 88 |
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| 89 | # This is reference 2x-parallelized VIS-powered Xupdate procedure. It
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| 90 | # covers even K_NN_MM addition...
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| 91 | sub Xupdate {
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| 92 | my ($i)=@_;
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| 93 | my $K=@VK[($i+16)/20];
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| 94 | my $j=($i+16)%16;
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| 95 |
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| 96 | # [ provided that GSR.alignaddr_offset is 5, $mul contains
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| 97 | # 0x100ULL<<32|0x100 value and K_NN_MM are pre-loaded to
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| 98 | # chosen registers... ]
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| 99 | $code.=<<___;
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| 100 | fxors @X[($j+13)%16],@X[$j],@X[$j] !-1/-1/-1:X[0]^=X[13]
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| 101 | fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
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| 102 | fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
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| 103 | fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
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| 104 | faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
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| 105 | fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
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| 106 | fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
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| 107 | ![fxors %f15,%f2,%f2]
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| 108 | for %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
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| 109 | ![fxors %f0,%f3,%f3] !10/17/12:X[0] dependency
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| 110 | fpadd32 $K,@X[$j],%f20
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| 111 | std %f20,[$Xfer+`4*$j`]
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| 112 | ___
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| 113 | # The numbers delimited with slash are the earliest possible dispatch
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| 114 | # cycles for given instruction assuming 1 cycle latency for simple VIS
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| 115 | # instructions, such as on UltraSPARC-I&II, 3 cycles latency, such as
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| 116 | # on UltraSPARC-III&IV, and 2 cycles latency(*), respectively. Being
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| 117 | # 2x-parallelized the procedure is "worth" 5, 8.5 or 6 ticks per SHA1
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| 118 | # round. As [long as] FPU/VIS instructions are perfectly pairable with
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| 119 | # IALU ones, the round timing is defined by the maximum between VIS
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| 120 | # and IALU timings. The latter varies from round to round and averages
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| 121 | # out at 6.25 ticks. This means that USI&II should operate at IALU
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| 122 | # rate, while USIII&IV - at VIS rate. This explains why performance
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| 123 | # improvement varies among processors. Well, given that pure IALU
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| 124 | # sha1-sparcv9.pl module exhibits virtually uniform performance of
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| 125 | # ~9.3 cycles per SHA1 round. Timings mentioned above are theoretical
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| 126 | # lower limits. Real-life performance was measured to be 6.6 cycles
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| 127 | # per SHA1 round on USIIi and 8.3 on USIII. The latter is lower than
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| 128 | # half-round VIS timing, because there are 16 Xupdate-free rounds,
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| 129 | # which "push down" average theoretical timing to 8 cycles...
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| 130 |
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| 131 | # (*) SPARC64-V[II] was originally believed to have 2 cycles VIS
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| 132 | # latency. Well, it might have, but it doesn't have dedicated
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| 133 | # VIS-unit. Instead, VIS instructions are executed by other
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| 134 | # functional units, ones used here - by IALU. This doesn't
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| 135 | # improve effective ILP...
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| 136 | }
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| 137 |
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| 138 | # The reference Xupdate procedure is then "strained" over *pairs* of
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| 139 | # BODY_NN_MM and kind of modulo-scheduled in respect to X[n]^=X[n+13]
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| 140 | # and K_NN_MM addition. It's "running" 15 rounds ahead, which leaves
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| 141 | # plenty of room to amortize for read-after-write hazard, as well as
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| 142 | # to fetch and align input for the next spin. The VIS instructions are
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| 143 | # scheduled for latency of 2 cycles, because there are not enough IALU
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| 144 | # instructions to schedule for latency of 3, while scheduling for 1
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| 145 | # would give no gain on USI&II anyway.
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| 146 |
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| 147 | sub BODY_00_19 {
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| 148 | my ($i,$a,$b,$c,$d,$e)=@_;
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| 149 | my $j=$i&~1;
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| 150 | my $k=($j+16+2)%16; # ahead reference
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| 151 | my $l=($j+16-2)%16; # behind reference
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| 152 | my $K=@VK[($j+16-2)/20];
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| 153 |
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| 154 | $j=($j+16)%16;
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| 155 |
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| 156 | $code.=<<___ if (!($i&1));
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| 157 | sll $a,5,$tmp0 !! $i
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| 158 | and $c,$b,$tmp3
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| 159 | ld [$Xfer+`4*($i%16)`],$Xi
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| 160 | fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
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| 161 | srl $a,27,$tmp1
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| 162 | add $tmp0,$e,$e
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| 163 | fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
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| 164 | sll $b,30,$tmp2
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| 165 | add $tmp1,$e,$e
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| 166 | andn $d,$b,$tmp1
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| 167 | add $Xi,$e,$e
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| 168 | fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
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| 169 | srl $b,2,$b
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| 170 | or $tmp1,$tmp3,$tmp1
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| 171 | or $tmp2,$b,$b
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| 172 | add $tmp1,$e,$e
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| 173 | faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
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| 174 | ___
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| 175 | $code.=<<___ if ($i&1);
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| 176 | sll $a,5,$tmp0 !! $i
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| 177 | and $c,$b,$tmp3
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| 178 | ld [$Xfer+`4*($i%16)`],$Xi
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| 179 | fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
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| 180 | srl $a,27,$tmp1
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| 181 | add $tmp0,$e,$e
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| 182 | fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
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| 183 | sll $b,30,$tmp2
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| 184 | add $tmp1,$e,$e
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| 185 | fpadd32 $K,@X[$l],%f20 !
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| 186 | andn $d,$b,$tmp1
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| 187 | add $Xi,$e,$e
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| 188 | fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
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| 189 | srl $b,2,$b
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| 190 | or $tmp1,$tmp3,$tmp1
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| 191 | fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
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| 192 | or $tmp2,$b,$b
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| 193 | add $tmp1,$e,$e
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| 194 | ___
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| 195 | $code.=<<___ if ($i&1 && $i>=2);
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| 196 | std %f20,[$Xfer+`4*$l`] !
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| 197 | ___
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| 198 | }
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| 199 |
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| 200 | sub BODY_20_39 {
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| 201 | my ($i,$a,$b,$c,$d,$e)=@_;
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| 202 | my $j=$i&~1;
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| 203 | my $k=($j+16+2)%16; # ahead reference
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| 204 | my $l=($j+16-2)%16; # behind reference
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| 205 | my $K=@VK[($j+16-2)/20];
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| 206 |
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| 207 | $j=($j+16)%16;
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| 208 |
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| 209 | $code.=<<___ if (!($i&1) && $i<64);
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| 210 | sll $a,5,$tmp0 !! $i
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| 211 | ld [$Xfer+`4*($i%16)`],$Xi
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| 212 | fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
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| 213 | srl $a,27,$tmp1
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| 214 | add $tmp0,$e,$e
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| 215 | fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
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| 216 | xor $c,$b,$tmp0
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| 217 | add $tmp1,$e,$e
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| 218 | sll $b,30,$tmp2
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| 219 | xor $d,$tmp0,$tmp1
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| 220 | fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
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| 221 | srl $b,2,$b
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| 222 | add $tmp1,$e,$e
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| 223 | or $tmp2,$b,$b
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| 224 | add $Xi,$e,$e
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| 225 | faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
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| 226 | ___
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| 227 | $code.=<<___ if ($i&1 && $i<64);
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| 228 | sll $a,5,$tmp0 !! $i
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| 229 | ld [$Xfer+`4*($i%16)`],$Xi
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| 230 | fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
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| 231 | srl $a,27,$tmp1
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| 232 | add $tmp0,$e,$e
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| 233 | fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
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| 234 | xor $c,$b,$tmp0
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| 235 | add $tmp1,$e,$e
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| 236 | fpadd32 $K,@X[$l],%f20 !
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| 237 | sll $b,30,$tmp2
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| 238 | xor $d,$tmp0,$tmp1
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| 239 | fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
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| 240 | srl $b,2,$b
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| 241 | add $tmp1,$e,$e
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| 242 | fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
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| 243 | or $tmp2,$b,$b
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| 244 | add $Xi,$e,$e
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| 245 | std %f20,[$Xfer+`4*$l`] !
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| 246 | ___
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| 247 | $code.=<<___ if ($i==64);
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| 248 | sll $a,5,$tmp0 !! $i
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| 249 | ld [$Xfer+`4*($i%16)`],$Xi
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| 250 | fpadd32 $K,@X[$l],%f20
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| 251 | srl $a,27,$tmp1
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| 252 | add $tmp0,$e,$e
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| 253 | xor $c,$b,$tmp0
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| 254 | add $tmp1,$e,$e
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| 255 | sll $b,30,$tmp2
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| 256 | xor $d,$tmp0,$tmp1
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| 257 | std %f20,[$Xfer+`4*$l`]
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| 258 | srl $b,2,$b
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| 259 | add $tmp1,$e,$e
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| 260 | or $tmp2,$b,$b
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| 261 | add $Xi,$e,$e
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| 262 | ___
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| 263 | $code.=<<___ if ($i>64);
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| 264 | sll $a,5,$tmp0 !! $i
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| 265 | ld [$Xfer+`4*($i%16)`],$Xi
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| 266 | srl $a,27,$tmp1
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| 267 | add $tmp0,$e,$e
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| 268 | xor $c,$b,$tmp0
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| 269 | add $tmp1,$e,$e
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| 270 | sll $b,30,$tmp2
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| 271 | xor $d,$tmp0,$tmp1
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| 272 | srl $b,2,$b
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| 273 | add $tmp1,$e,$e
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| 274 | or $tmp2,$b,$b
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| 275 | add $Xi,$e,$e
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| 276 | ___
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| 277 | }
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| 278 |
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| 279 | sub BODY_40_59 {
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| 280 | my ($i,$a,$b,$c,$d,$e)=@_;
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| 281 | my $j=$i&~1;
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| 282 | my $k=($j+16+2)%16; # ahead reference
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| 283 | my $l=($j+16-2)%16; # behind reference
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| 284 | my $K=@VK[($j+16-2)/20];
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| 285 |
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| 286 | $j=($j+16)%16;
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| 287 |
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| 288 | $code.=<<___ if (!($i&1));
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| 289 | sll $a,5,$tmp0 !! $i
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| 290 | ld [$Xfer+`4*($i%16)`],$Xi
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| 291 | fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
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| 292 | srl $a,27,$tmp1
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| 293 | add $tmp0,$e,$e
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| 294 | fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
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| 295 | and $c,$b,$tmp0
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| 296 | add $tmp1,$e,$e
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| 297 | sll $b,30,$tmp2
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| 298 | or $c,$b,$tmp1
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| 299 | fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
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| 300 | srl $b,2,$b
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| 301 | and $d,$tmp1,$tmp1
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| 302 | add $Xi,$e,$e
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| 303 | or $tmp1,$tmp0,$tmp1
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| 304 | faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
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| 305 | or $tmp2,$b,$b
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| 306 | add $tmp1,$e,$e
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| 307 | fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
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| 308 | ___
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| 309 | $code.=<<___ if ($i&1);
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| 310 | sll $a,5,$tmp0 !! $i
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| 311 | ld [$Xfer+`4*($i%16)`],$Xi
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| 312 | srl $a,27,$tmp1
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| 313 | add $tmp0,$e,$e
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| 314 | fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
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| 315 | and $c,$b,$tmp0
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| 316 | add $tmp1,$e,$e
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| 317 | fpadd32 $K,@X[$l],%f20 !
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| 318 | sll $b,30,$tmp2
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| 319 | or $c,$b,$tmp1
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| 320 | fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
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| 321 | srl $b,2,$b
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| 322 | and $d,$tmp1,$tmp1
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| 323 | fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
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| 324 | add $Xi,$e,$e
|
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| 325 | or $tmp1,$tmp0,$tmp1
|
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| 326 | or $tmp2,$b,$b
|
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| 327 | add $tmp1,$e,$e
|
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| 328 | std %f20,[$Xfer+`4*$l`] !
|
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| 329 | ___
|
|---|
| 330 | }
|
|---|
| 331 |
|
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| 332 | # If there is more data to process, then we pre-fetch the data for
|
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| 333 | # next iteration in last ten rounds...
|
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| 334 | sub BODY_70_79 {
|
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| 335 | my ($i,$a,$b,$c,$d,$e)=@_;
|
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| 336 | my $j=$i&~1;
|
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| 337 | my $m=($i%8)*2;
|
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| 338 |
|
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| 339 | $j=($j+16)%16;
|
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| 340 |
|
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| 341 | $code.=<<___ if ($i==70);
|
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| 342 | sll $a,5,$tmp0 !! $i
|
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| 343 | ld [$Xfer+`4*($i%16)`],$Xi
|
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| 344 | srl $a,27,$tmp1
|
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| 345 | add $tmp0,$e,$e
|
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| 346 | ldd [$inp+64],@X[0]
|
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| 347 | xor $c,$b,$tmp0
|
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| 348 | add $tmp1,$e,$e
|
|---|
| 349 | sll $b,30,$tmp2
|
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| 350 | xor $d,$tmp0,$tmp1
|
|---|
| 351 | srl $b,2,$b
|
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| 352 | add $tmp1,$e,$e
|
|---|
| 353 | or $tmp2,$b,$b
|
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| 354 | add $Xi,$e,$e
|
|---|
| 355 |
|
|---|
| 356 | and $inp,-64,$nXfer
|
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| 357 | inc 64,$inp
|
|---|
| 358 | and $nXfer,255,$nXfer
|
|---|
| 359 | alignaddr %g0,$align,%g0
|
|---|
| 360 | add $base,$nXfer,$nXfer
|
|---|
| 361 | ___
|
|---|
| 362 | $code.=<<___ if ($i==71);
|
|---|
| 363 | sll $a,5,$tmp0 !! $i
|
|---|
| 364 | ld [$Xfer+`4*($i%16)`],$Xi
|
|---|
| 365 | srl $a,27,$tmp1
|
|---|
| 366 | add $tmp0,$e,$e
|
|---|
| 367 | xor $c,$b,$tmp0
|
|---|
| 368 | add $tmp1,$e,$e
|
|---|
| 369 | sll $b,30,$tmp2
|
|---|
| 370 | xor $d,$tmp0,$tmp1
|
|---|
| 371 | srl $b,2,$b
|
|---|
| 372 | add $tmp1,$e,$e
|
|---|
| 373 | or $tmp2,$b,$b
|
|---|
| 374 | add $Xi,$e,$e
|
|---|
| 375 | ___
|
|---|
| 376 | $code.=<<___ if ($i>=72);
|
|---|
| 377 | faligndata @X[$m],@X[$m+2],@X[$m]
|
|---|
| 378 | sll $a,5,$tmp0 !! $i
|
|---|
| 379 | ld [$Xfer+`4*($i%16)`],$Xi
|
|---|
| 380 | srl $a,27,$tmp1
|
|---|
| 381 | add $tmp0,$e,$e
|
|---|
| 382 | xor $c,$b,$tmp0
|
|---|
| 383 | add $tmp1,$e,$e
|
|---|
| 384 | fpadd32 $VK_00_19,@X[$m],%f20
|
|---|
| 385 | sll $b,30,$tmp2
|
|---|
| 386 | xor $d,$tmp0,$tmp1
|
|---|
| 387 | srl $b,2,$b
|
|---|
| 388 | add $tmp1,$e,$e
|
|---|
| 389 | or $tmp2,$b,$b
|
|---|
| 390 | add $Xi,$e,$e
|
|---|
| 391 | ___
|
|---|
| 392 | $code.=<<___ if ($i<77);
|
|---|
| 393 | ldd [$inp+`8*($i+1-70)`],@X[2*($i+1-70)]
|
|---|
| 394 | ___
|
|---|
| 395 | $code.=<<___ if ($i==77); # redundant if $inp was aligned
|
|---|
| 396 | add $align,63,$tmp0
|
|---|
| 397 | and $tmp0,-8,$tmp0
|
|---|
| 398 | ldd [$inp+$tmp0],@X[16]
|
|---|
| 399 | ___
|
|---|
| 400 | $code.=<<___ if ($i>=72);
|
|---|
| 401 | std %f20,[$nXfer+`4*$m`]
|
|---|
| 402 | ___
|
|---|
| 403 | }
|
|---|
| 404 |
|
|---|
| 405 | $code.=<<___;
|
|---|
| 406 | .section ".text",#alloc,#execinstr
|
|---|
| 407 |
|
|---|
| 408 | .align 64
|
|---|
| 409 | vis_const:
|
|---|
| 410 | .long 0x5a827999,0x5a827999 ! K_00_19
|
|---|
| 411 | .long 0x6ed9eba1,0x6ed9eba1 ! K_20_39
|
|---|
| 412 | .long 0x8f1bbcdc,0x8f1bbcdc ! K_40_59
|
|---|
| 413 | .long 0xca62c1d6,0xca62c1d6 ! K_60_79
|
|---|
| 414 | .long 0x00000100,0x00000100
|
|---|
| 415 | .align 64
|
|---|
| 416 | .type vis_const,#object
|
|---|
| 417 | .size vis_const,(.-vis_const)
|
|---|
| 418 |
|
|---|
| 419 | .globl sha1_block_data_order
|
|---|
| 420 | sha1_block_data_order:
|
|---|
| 421 | save %sp,-$frame,%sp
|
|---|
| 422 | add %fp,$bias-256,$base
|
|---|
| 423 |
|
|---|
| 424 | 1: call .+8
|
|---|
| 425 | add %o7,vis_const-1b,$tmp0
|
|---|
| 426 |
|
|---|
| 427 | ldd [$tmp0+0],$VK_00_19
|
|---|
| 428 | ldd [$tmp0+8],$VK_20_39
|
|---|
| 429 | ldd [$tmp0+16],$VK_40_59
|
|---|
| 430 | ldd [$tmp0+24],$VK_60_79
|
|---|
| 431 | ldd [$tmp0+32],$fmul
|
|---|
| 432 |
|
|---|
| 433 | ld [$ctx+0],$Actx
|
|---|
| 434 | and $base,-256,$base
|
|---|
| 435 | ld [$ctx+4],$Bctx
|
|---|
| 436 | sub $base,$bias+$frame,%sp
|
|---|
| 437 | ld [$ctx+8],$Cctx
|
|---|
| 438 | and $inp,7,$align
|
|---|
| 439 | ld [$ctx+12],$Dctx
|
|---|
| 440 | and $inp,-8,$inp
|
|---|
| 441 | ld [$ctx+16],$Ectx
|
|---|
| 442 |
|
|---|
| 443 | ! X[16] is maintained in FP register bank
|
|---|
| 444 | alignaddr %g0,$align,%g0
|
|---|
| 445 | ldd [$inp+0],@X[0]
|
|---|
| 446 | sub $inp,-64,$Xfer
|
|---|
| 447 | ldd [$inp+8],@X[2]
|
|---|
| 448 | and $Xfer,-64,$Xfer
|
|---|
| 449 | ldd [$inp+16],@X[4]
|
|---|
| 450 | and $Xfer,255,$Xfer
|
|---|
| 451 | ldd [$inp+24],@X[6]
|
|---|
| 452 | add $base,$Xfer,$Xfer
|
|---|
| 453 | ldd [$inp+32],@X[8]
|
|---|
| 454 | ldd [$inp+40],@X[10]
|
|---|
| 455 | ldd [$inp+48],@X[12]
|
|---|
| 456 | brz,pt $align,.Laligned
|
|---|
| 457 | ldd [$inp+56],@X[14]
|
|---|
| 458 |
|
|---|
| 459 | ldd [$inp+64],@X[16]
|
|---|
| 460 | faligndata @X[0],@X[2],@X[0]
|
|---|
| 461 | faligndata @X[2],@X[4],@X[2]
|
|---|
| 462 | faligndata @X[4],@X[6],@X[4]
|
|---|
| 463 | faligndata @X[6],@X[8],@X[6]
|
|---|
| 464 | faligndata @X[8],@X[10],@X[8]
|
|---|
| 465 | faligndata @X[10],@X[12],@X[10]
|
|---|
| 466 | faligndata @X[12],@X[14],@X[12]
|
|---|
| 467 | faligndata @X[14],@X[16],@X[14]
|
|---|
| 468 |
|
|---|
| 469 | .Laligned:
|
|---|
| 470 | mov 5,$tmp0
|
|---|
| 471 | dec 1,$len
|
|---|
| 472 | alignaddr %g0,$tmp0,%g0
|
|---|
| 473 | fpadd32 $VK_00_19,@X[0],%f16
|
|---|
| 474 | fpadd32 $VK_00_19,@X[2],%f18
|
|---|
| 475 | fpadd32 $VK_00_19,@X[4],%f20
|
|---|
| 476 | fpadd32 $VK_00_19,@X[6],%f22
|
|---|
| 477 | fpadd32 $VK_00_19,@X[8],%f24
|
|---|
| 478 | fpadd32 $VK_00_19,@X[10],%f26
|
|---|
| 479 | fpadd32 $VK_00_19,@X[12],%f28
|
|---|
| 480 | fpadd32 $VK_00_19,@X[14],%f30
|
|---|
| 481 | std %f16,[$Xfer+0]
|
|---|
| 482 | mov $Actx,$A
|
|---|
| 483 | std %f18,[$Xfer+8]
|
|---|
| 484 | mov $Bctx,$B
|
|---|
| 485 | std %f20,[$Xfer+16]
|
|---|
| 486 | mov $Cctx,$C
|
|---|
| 487 | std %f22,[$Xfer+24]
|
|---|
| 488 | mov $Dctx,$D
|
|---|
| 489 | std %f24,[$Xfer+32]
|
|---|
| 490 | mov $Ectx,$E
|
|---|
| 491 | std %f26,[$Xfer+40]
|
|---|
| 492 | fxors @X[13],@X[0],@X[0]
|
|---|
| 493 | std %f28,[$Xfer+48]
|
|---|
| 494 | ba .Loop
|
|---|
| 495 | std %f30,[$Xfer+56]
|
|---|
| 496 | .align 32
|
|---|
| 497 | .Loop:
|
|---|
| 498 | ___
|
|---|
| 499 | for ($i=0;$i<20;$i++) { &BODY_00_19($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 500 | for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 501 | for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 502 | for (;$i<70;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 503 | $code.=<<___;
|
|---|
| 504 | tst $len
|
|---|
| 505 | bz,pn `$bits==32?"%icc":"%xcc"`,.Ltail
|
|---|
| 506 | nop
|
|---|
| 507 | ___
|
|---|
| 508 | for (;$i<80;$i++) { &BODY_70_79($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 509 | $code.=<<___;
|
|---|
| 510 | add $A,$Actx,$Actx
|
|---|
| 511 | add $B,$Bctx,$Bctx
|
|---|
| 512 | add $C,$Cctx,$Cctx
|
|---|
| 513 | add $D,$Dctx,$Dctx
|
|---|
| 514 | add $E,$Ectx,$Ectx
|
|---|
| 515 | mov 5,$tmp0
|
|---|
| 516 | fxors @X[13],@X[0],@X[0]
|
|---|
| 517 | mov $Actx,$A
|
|---|
| 518 | mov $Bctx,$B
|
|---|
| 519 | mov $Cctx,$C
|
|---|
| 520 | mov $Dctx,$D
|
|---|
| 521 | mov $Ectx,$E
|
|---|
| 522 | alignaddr %g0,$tmp0,%g0
|
|---|
| 523 | dec 1,$len
|
|---|
| 524 | ba .Loop
|
|---|
| 525 | mov $nXfer,$Xfer
|
|---|
| 526 |
|
|---|
| 527 | .align 32
|
|---|
| 528 | .Ltail:
|
|---|
| 529 | ___
|
|---|
| 530 | for($i=70;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
|
|---|
| 531 | $code.=<<___;
|
|---|
| 532 | add $A,$Actx,$Actx
|
|---|
| 533 | add $B,$Bctx,$Bctx
|
|---|
| 534 | add $C,$Cctx,$Cctx
|
|---|
| 535 | add $D,$Dctx,$Dctx
|
|---|
| 536 | add $E,$Ectx,$Ectx
|
|---|
| 537 |
|
|---|
| 538 | st $Actx,[$ctx+0]
|
|---|
| 539 | st $Bctx,[$ctx+4]
|
|---|
| 540 | st $Cctx,[$ctx+8]
|
|---|
| 541 | st $Dctx,[$ctx+12]
|
|---|
| 542 | st $Ectx,[$ctx+16]
|
|---|
| 543 |
|
|---|
| 544 | ret
|
|---|
| 545 | restore
|
|---|
| 546 | .type sha1_block_data_order,#function
|
|---|
| 547 | .size sha1_block_data_order,(.-sha1_block_data_order)
|
|---|
| 548 | .asciz "SHA1 block transform for SPARCv9a, CRYPTOGAMS by <appro\@openssl.org>"
|
|---|
| 549 | .align 4
|
|---|
| 550 | ___
|
|---|
| 551 |
|
|---|
| 552 | # Purpose of these subroutines is to explicitly encode VIS instructions,
|
|---|
| 553 | # so that one can compile the module without having to specify VIS
|
|---|
| 554 | # extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
|
|---|
| 555 | # Idea is to reserve for option to produce "universal" binary and let
|
|---|
| 556 | # programmer detect if current CPU is VIS capable at run-time.
|
|---|
| 557 | sub unvis {
|
|---|
| 558 | my ($mnemonic,$rs1,$rs2,$rd)=@_;
|
|---|
| 559 | my ($ref,$opf);
|
|---|
| 560 | my %visopf = ( "fmul8ulx16" => 0x037,
|
|---|
| 561 | "faligndata" => 0x048,
|
|---|
| 562 | "fpadd32" => 0x052,
|
|---|
| 563 | "fxor" => 0x06c,
|
|---|
| 564 | "fxors" => 0x06d );
|
|---|
| 565 |
|
|---|
| 566 | $ref = "$mnemonic\t$rs1,$rs2,$rd";
|
|---|
| 567 |
|
|---|
| 568 | if ($opf=$visopf{$mnemonic}) {
|
|---|
| 569 | foreach ($rs1,$rs2,$rd) {
|
|---|
| 570 | return $ref if (!/%f([0-9]{1,2})/);
|
|---|
| 571 | $_=$1;
|
|---|
| 572 | if ($1>=32) {
|
|---|
| 573 | return $ref if ($1&1);
|
|---|
| 574 | # re-encode for upper double register addressing
|
|---|
| 575 | $_=($1|$1>>5)&31;
|
|---|
| 576 | }
|
|---|
| 577 | }
|
|---|
| 578 |
|
|---|
| 579 | return sprintf ".word\t0x%08x !%s",
|
|---|
| 580 | 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
|
|---|
| 581 | $ref;
|
|---|
| 582 | } else {
|
|---|
| 583 | return $ref;
|
|---|
| 584 | }
|
|---|
| 585 | }
|
|---|
| 586 | sub unalignaddr {
|
|---|
| 587 | my ($mnemonic,$rs1,$rs2,$rd)=@_;
|
|---|
| 588 | my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
|
|---|
| 589 | my $ref="$mnemonic\t$rs1,$rs2,$rd";
|
|---|
| 590 |
|
|---|
| 591 | foreach ($rs1,$rs2,$rd) {
|
|---|
| 592 | if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
|
|---|
| 593 | else { return $ref; }
|
|---|
| 594 | }
|
|---|
| 595 | return sprintf ".word\t0x%08x !%s",
|
|---|
| 596 | 0x81b00300|$rd<<25|$rs1<<14|$rs2,
|
|---|
| 597 | $ref;
|
|---|
| 598 | }
|
|---|
| 599 |
|
|---|
| 600 | $code =~ s/\`([^\`]*)\`/eval $1/gem;
|
|---|
| 601 | $code =~ s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),(%f[0-9]{1,2}),(%f[0-9]{1,2})/
|
|---|
| 602 | &unvis($1,$2,$3,$4)
|
|---|
| 603 | /gem;
|
|---|
| 604 | $code =~ s/\b(alignaddr)\s+(%[goli][0-7]),(%[goli][0-7]),(%[goli][0-7])/
|
|---|
| 605 | &unalignaddr($1,$2,$3,$4)
|
|---|
| 606 | /gem;
|
|---|
| 607 | print $code;
|
|---|
| 608 | close STDOUT or die "error closing STDOUT: $!";
|
|---|
