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source: vbox/trunk/src/libs/openssl-3.0.3/crypto/armcap.c@ 96662

Last change on this file since 96662 was 95197, checked in by vboxsync, 3 years ago

libs/openssl-3.0.2: Addressed potential sigprocmask problem when we go for arm64 assembly routines (code is not compiled at the moment). bugref:9898
File size: 7.5 KB
Line 
1/*
2 * Copyright 2011-2021 The OpenSSL Project Authors. All Rights Reserved.
3 *
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
8 */
9
10#include <stdio.h>
11#include <stdlib.h>
12#include <string.h>
13#include <setjmp.h>
14#include <signal.h>
15#include <openssl/crypto.h>
16#ifdef __APPLE__
17#include <sys/sysctl.h>
18#endif
19#ifdef RT_OS_DARWIN /* VBOX */
20# include <pthread.h> /* VBOX */
21# define sigprocmask pthread_sigmask /* On xnu sigprocmask works on the process, not the calling thread as elsewhere. */
22#endif /* VBOX */
23#include "internal/cryptlib.h"
24
25#include "arm_arch.h"
26
27unsigned int OPENSSL_armcap_P = 0;
28unsigned int OPENSSL_arm_midr = 0;
29unsigned int OPENSSL_armv8_rsa_neonized = 0;
30
31#if __ARM_MAX_ARCH__<7
32void OPENSSL_cpuid_setup(void)
33{
34}
35
36uint32_t OPENSSL_rdtsc(void)
37{
38 return 0;
39}
40#else
41static sigset_t all_masked;
42
43static sigjmp_buf ill_jmp;
44static void ill_handler(int sig)
45{
46 siglongjmp(ill_jmp, sig);
47}
48
49/*
50 * Following subroutines could have been inlined, but it's not all
51 * ARM compilers support inline assembler...
52 */
53void _armv7_neon_probe(void);
54void _armv8_aes_probe(void);
55void _armv8_sha1_probe(void);
56void _armv8_sha256_probe(void);
57void _armv8_pmull_probe(void);
58# ifdef __aarch64__
59void _armv8_sha512_probe(void);
60unsigned int _armv8_cpuid_probe(void);
61# endif
62uint32_t _armv7_tick(void);
63
64uint32_t OPENSSL_rdtsc(void)
65{
66 if (OPENSSL_armcap_P & ARMV7_TICK)
67 return _armv7_tick();
68 else
69 return 0;
70}
71
72# if defined(__GNUC__) && __GNUC__>=2
73void OPENSSL_cpuid_setup(void) __attribute__ ((constructor));
74# endif
75
76# if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
77# if __GLIBC_PREREQ(2, 16)
78# include <sys/auxv.h>
79# define OSSL_IMPLEMENT_GETAUXVAL
80# endif
81# elif defined(__ANDROID_API__)
82/* see https://developer.android.google.cn/ndk/guides/cpu-features */
83# if __ANDROID_API__ >= 18
84# include <sys/auxv.h>
85# define OSSL_IMPLEMENT_GETAUXVAL
86# endif
87# endif
88# if defined(__FreeBSD__)
89# include <sys/param.h>
90# if __FreeBSD_version >= 1200000
91# include <sys/auxv.h>
92# define OSSL_IMPLEMENT_GETAUXVAL
93
94static unsigned long getauxval(unsigned long key)
95{
96 unsigned long val = 0ul;
97
98 if (elf_aux_info((int)key, &val, sizeof(val)) != 0)
99 return 0ul;
100
101 return val;
102}
103# endif
104# endif
105
106/*
107 * Android: according to https://developer.android.com/ndk/guides/cpu-features,
108 * getauxval is supported starting with API level 18
109 */
110# if defined(__ANDROID__) && defined(__ANDROID_API__) && __ANDROID_API__ >= 18
111# include <sys/auxv.h>
112# define OSSL_IMPLEMENT_GETAUXVAL
113# endif
114
115/*
116 * ARM puts the feature bits for Crypto Extensions in AT_HWCAP2, whereas
117 * AArch64 used AT_HWCAP.
118 */
119# ifndef AT_HWCAP
120# define AT_HWCAP 16
121# endif
122# ifndef AT_HWCAP2
123# define AT_HWCAP2 26
124# endif
125# if defined(__arm__) || defined (__arm)
126# define HWCAP AT_HWCAP
127# define HWCAP_NEON (1 << 12)
128
129# define HWCAP_CE AT_HWCAP2
130# define HWCAP_CE_AES (1 << 0)
131# define HWCAP_CE_PMULL (1 << 1)
132# define HWCAP_CE_SHA1 (1 << 2)
133# define HWCAP_CE_SHA256 (1 << 3)
134# elif defined(__aarch64__)
135# define HWCAP AT_HWCAP
136# define HWCAP_NEON (1 << 1)
137
138# define HWCAP_CE HWCAP
139# define HWCAP_CE_AES (1 << 3)
140# define HWCAP_CE_PMULL (1 << 4)
141# define HWCAP_CE_SHA1 (1 << 5)
142# define HWCAP_CE_SHA256 (1 << 6)
143# define HWCAP_CPUID (1 << 11)
144# define HWCAP_CE_SHA512 (1 << 21)
145# endif
146
147void OPENSSL_cpuid_setup(void)
148{
149 const char *e;
150 struct sigaction ill_oact, ill_act;
151 sigset_t oset;
152 static int trigger = 0;
153
154 if (trigger)
155 return;
156 trigger = 1;
157
158 OPENSSL_armcap_P = 0;
159
160 if ((e = getenv("OPENSSL_armcap"))) {
161 OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
162 return;
163 }
164
165# if defined(__APPLE__)
166# if !defined(__aarch64__)
167 /*
168 * Capability probing by catching SIGILL appears to be problematic
169 * on iOS. But since Apple universe is "monocultural", it's actually
170 * possible to simply set pre-defined processor capability mask.
171 */
172 if (1) {
173 OPENSSL_armcap_P = ARMV7_NEON;
174 return;
175 }
176 /*
177 * One could do same even for __aarch64__ iOS builds. It's not done
178 * exclusively for reasons of keeping code unified across platforms.
179 * Unified code works because it never triggers SIGILL on Apple
180 * devices...
181 */
182# else
183 {
184 unsigned int sha512;
185 size_t len = sizeof(sha512);
186
187 if (sysctlbyname("hw.optional.armv8_2_sha512", &sha512, &len, NULL, 0) == 0 && sha512 == 1)
188 OPENSSL_armcap_P |= ARMV8_SHA512;
189 }
190# endif
191# endif
192
193# ifdef OSSL_IMPLEMENT_GETAUXVAL
194 if (getauxval(HWCAP) & HWCAP_NEON) {
195 unsigned long hwcap = getauxval(HWCAP_CE);
196
197 OPENSSL_armcap_P |= ARMV7_NEON;
198
199 if (hwcap & HWCAP_CE_AES)
200 OPENSSL_armcap_P |= ARMV8_AES;
201
202 if (hwcap & HWCAP_CE_PMULL)
203 OPENSSL_armcap_P |= ARMV8_PMULL;
204
205 if (hwcap & HWCAP_CE_SHA1)
206 OPENSSL_armcap_P |= ARMV8_SHA1;
207
208 if (hwcap & HWCAP_CE_SHA256)
209 OPENSSL_armcap_P |= ARMV8_SHA256;
210
211# ifdef __aarch64__
212 if (hwcap & HWCAP_CE_SHA512)
213 OPENSSL_armcap_P |= ARMV8_SHA512;
214
215 if (hwcap & HWCAP_CPUID)
216 OPENSSL_armcap_P |= ARMV8_CPUID;
217# endif
218 }
219# endif
220
221 sigfillset(&all_masked);
222 sigdelset(&all_masked, SIGILL);
223 sigdelset(&all_masked, SIGTRAP);
224 sigdelset(&all_masked, SIGFPE);
225 sigdelset(&all_masked, SIGBUS);
226 sigdelset(&all_masked, SIGSEGV);
227
228 memset(&ill_act, 0, sizeof(ill_act));
229 ill_act.sa_handler = ill_handler;
230 ill_act.sa_mask = all_masked;
231
232 sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
233 sigaction(SIGILL, &ill_act, &ill_oact);
234
235 /* If we used getauxval, we already have all the values */
236# ifndef OSSL_IMPLEMENT_GETAUXVAL
237 if (sigsetjmp(ill_jmp, 1) == 0) {
238 _armv7_neon_probe();
239 OPENSSL_armcap_P |= ARMV7_NEON;
240 if (sigsetjmp(ill_jmp, 1) == 0) {
241 _armv8_pmull_probe();
242 OPENSSL_armcap_P |= ARMV8_PMULL | ARMV8_AES;
243 } else if (sigsetjmp(ill_jmp, 1) == 0) {
244 _armv8_aes_probe();
245 OPENSSL_armcap_P |= ARMV8_AES;
246 }
247 if (sigsetjmp(ill_jmp, 1) == 0) {
248 _armv8_sha1_probe();
249 OPENSSL_armcap_P |= ARMV8_SHA1;
250 }
251 if (sigsetjmp(ill_jmp, 1) == 0) {
252 _armv8_sha256_probe();
253 OPENSSL_armcap_P |= ARMV8_SHA256;
254 }
255# if defined(__aarch64__) && !defined(__APPLE__)
256 if (sigsetjmp(ill_jmp, 1) == 0) {
257 _armv8_sha512_probe();
258 OPENSSL_armcap_P |= ARMV8_SHA512;
259 }
260# endif
261 }
262# endif
263
264 /* Things that getauxval didn't tell us */
265 if (sigsetjmp(ill_jmp, 1) == 0) {
266 _armv7_tick();
267 OPENSSL_armcap_P |= ARMV7_TICK;
268 }
269
270 sigaction(SIGILL, &ill_oact, NULL);
271 sigprocmask(SIG_SETMASK, &oset, NULL);
272
273# ifdef __aarch64__
274 if (OPENSSL_armcap_P & ARMV8_CPUID)
275 OPENSSL_arm_midr = _armv8_cpuid_probe();
276
277 if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) ||
278 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)) &&
279 (OPENSSL_armcap_P & ARMV7_NEON)) {
280 OPENSSL_armv8_rsa_neonized = 1;
281 }
282# endif
283}
284#endif
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