| 1 | /*
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| 2 | * Copyright 2011-2022 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | *
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| 4 | * Licensed under the Apache License 2.0 (the "License"). You may not use
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| 5 | * this file except in compliance with the License. You can obtain a copy
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| 6 | * in the file LICENSE in the source distribution or at
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| 7 | * https://www.openssl.org/source/license.html
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| 8 | */
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| 9 |
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| 10 | #ifndef OSSL_CRYPTO_ARM_ARCH_H
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| 11 | # define OSSL_CRYPTO_ARM_ARCH_H
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| 12 |
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| 13 | # if !defined(__ARM_ARCH__)
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| 14 | # if defined(__CC_ARM)
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| 15 | # define __ARM_ARCH__ __TARGET_ARCH_ARM
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| 16 | # if defined(__BIG_ENDIAN)
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| 17 | # define __ARMEB__
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| 18 | # else
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| 19 | # define __ARMEL__
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| 20 | # endif
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| 21 | # elif defined(__GNUC__)
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| 22 | # if defined(__aarch64__)
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| 23 | # define __ARM_ARCH__ 8
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| 24 | # if __BYTE_ORDER__==__ORDER_BIG_ENDIAN__
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| 25 | # define __ARMEB__
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| 26 | # else
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| 27 | # define __ARMEL__
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| 28 | # endif
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| 29 | /*
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| 30 | * Why doesn't gcc define __ARM_ARCH__? Instead it defines
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| 31 | * bunch of below macros. See all_architectures[] table in
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| 32 | * gcc/config/arm/arm.c. On a side note it defines
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| 33 | * __ARMEL__/__ARMEB__ for little-/big-endian.
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| 34 | */
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| 35 | # elif defined(__ARM_ARCH)
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| 36 | # define __ARM_ARCH__ __ARM_ARCH
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| 37 | # elif defined(__ARM_ARCH_8A__)
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| 38 | # define __ARM_ARCH__ 8
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| 39 | # elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
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| 40 | defined(__ARM_ARCH_7R__)|| defined(__ARM_ARCH_7M__) || \
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| 41 | defined(__ARM_ARCH_7EM__)
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| 42 | # define __ARM_ARCH__ 7
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| 43 | # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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| 44 | defined(__ARM_ARCH_6K__)|| defined(__ARM_ARCH_6M__) || \
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| 45 | defined(__ARM_ARCH_6Z__)|| defined(__ARM_ARCH_6ZK__) || \
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| 46 | defined(__ARM_ARCH_6T2__)
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| 47 | # define __ARM_ARCH__ 6
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| 48 | # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || \
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| 49 | defined(__ARM_ARCH_5E__)|| defined(__ARM_ARCH_5TE__) || \
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| 50 | defined(__ARM_ARCH_5TEJ__)
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| 51 | # define __ARM_ARCH__ 5
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| 52 | # elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
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| 53 | # define __ARM_ARCH__ 4
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| 54 | # else
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| 55 | # error "unsupported ARM architecture"
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| 56 | # endif
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| 57 | # endif
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| 58 | # endif
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| 59 |
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| 60 | # if !defined(__ARM_MAX_ARCH__)
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| 61 | # define __ARM_MAX_ARCH__ __ARM_ARCH__
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| 62 | # endif
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| 63 |
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| 64 | # if __ARM_MAX_ARCH__<__ARM_ARCH__
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| 65 | # error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
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| 66 | # elif __ARM_MAX_ARCH__!=__ARM_ARCH__
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| 67 | # if __ARM_ARCH__<7 && __ARM_MAX_ARCH__>=7 && defined(__ARMEB__)
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| 68 | # error "can't build universal big-endian binary"
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| 69 | # endif
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| 70 | # endif
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| 71 |
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| 72 | # ifndef __ASSEMBLER__
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| 73 | extern unsigned int OPENSSL_armcap_P;
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| 74 | extern unsigned int OPENSSL_arm_midr;
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| 75 | extern unsigned int OPENSSL_armv8_rsa_neonized;
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| 76 | # endif
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| 77 |
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| 78 | # define ARMV7_NEON (1<<0)
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| 79 | # define ARMV7_TICK (1<<1)
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| 80 | # define ARMV8_AES (1<<2)
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| 81 | # define ARMV8_SHA1 (1<<3)
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| 82 | # define ARMV8_SHA256 (1<<4)
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| 83 | # define ARMV8_PMULL (1<<5)
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| 84 | # define ARMV8_SHA512 (1<<6)
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| 85 | # define ARMV8_CPUID (1<<7)
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| 86 |
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| 87 | /*
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| 88 | * MIDR_EL1 system register
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| 89 | *
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| 90 | * 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
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| 91 | * | | | | | | |
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| 92 | * |RES0 | Implementer | Variant | Arch | PartNum |Revision|
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| 93 | * |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
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| 94 | *
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| 95 | */
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| 96 |
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| 97 | # define ARM_CPU_IMP_ARM 0x41
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| 98 |
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| 99 | # define ARM_CPU_PART_CORTEX_A72 0xD08
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| 100 | # define ARM_CPU_PART_N1 0xD0C
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| 101 |
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| 102 | # define MIDR_PARTNUM_SHIFT 4
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| 103 | # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
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| 104 | # define MIDR_PARTNUM(midr) \
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| 105 | (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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| 106 |
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| 107 | # define MIDR_IMPLEMENTER_SHIFT 24
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| 108 | # define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
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| 109 | # define MIDR_IMPLEMENTER(midr) \
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| 110 | (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
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| 111 |
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| 112 | # define MIDR_ARCHITECTURE_SHIFT 16
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| 113 | # define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
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| 114 | # define MIDR_ARCHITECTURE(midr) \
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| 115 | (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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| 116 |
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| 117 | # define MIDR_CPU_MODEL_MASK \
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| 118 | (MIDR_IMPLEMENTER_MASK | \
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| 119 | MIDR_PARTNUM_MASK | \
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| 120 | MIDR_ARCHITECTURE_MASK)
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| 121 |
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| 122 | # define MIDR_CPU_MODEL(imp, partnum) \
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| 123 | (((imp) << MIDR_IMPLEMENTER_SHIFT) | \
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| 124 | (0xfU << MIDR_ARCHITECTURE_SHIFT) | \
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| 125 | ((partnum) << MIDR_PARTNUM_SHIFT))
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| 126 |
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| 127 | # define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
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| 128 | (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
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| 129 | #endif
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