ghash-x86.pl@ 98024

Last change on this file since 98024 was 94082, checked in by vboxsync, 3 years ago
libs/openssl-3.0.1: started applying and adjusting our OpenSSL changes to 3.0.1. bugref:10128
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1	#! /usr/bin/env perl
2	# Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
3	#
4	# Licensed under the Apache License 2.0 (the "License"). You may not use
5	# this file except in compliance with the License. You can obtain a copy
6	# in the file LICENSE in the source distribution or at
7	# https://www.openssl.org/source/license.html
8
9	#
10	# ====================================================================
11	# Written by Andy Polyakov <[email protected]> for the OpenSSL
12	# project. The module is, however, dual licensed under OpenSSL and
13	# CRYPTOGAMS licenses depending on where you obtain it. For further
14	# details see http://www.openssl.org/~appro/cryptogams/.
15	# ====================================================================
16	#
17	# March, May, June 2010
18	#
19	# The module implements "4-bit" GCM GHASH function and underlying
20	# single multiplication operation in GF(2^128). "4-bit" means that it
21	# uses 256 bytes per-key table [+64/128 bytes fixed table]. It has two
22	# code paths: vanilla x86 and vanilla SSE. Former will be executed on
23	# 486 and Pentium, latter on all others. SSE GHASH features so called
24	# "528B" variant of "4-bit" method utilizing additional 256+16 bytes
25	# of per-key storage [+512 bytes shared table]. Performance results
26	# are for streamed GHASH subroutine and are expressed in cycles per
27	# processed byte, less is better:
28	#
29	# gcc 2.95.3(*) SSE assembler x86 assembler
30	#
31	# Pentium 105/111(**) - 50
32	# PIII 68 /75 12.2 24
33	# P4 125/125 17.8 84(***)
34	# Opteron 66 /70 10.1 30
35	# Core2 54 /67 8.4 18
36	# Atom 105/105 16.8 53
37	# VIA Nano 69 /71 13.0 27
38	#
39	# (*) gcc 3.4.x was observed to generate few percent slower code,
40	# which is one of reasons why 2.95.3 results were chosen,
41	# another reason is lack of 3.4.x results for older CPUs;
42	# comparison with SSE results is not completely fair, because C
43	# results are for vanilla "256B" implementation, while
44	# assembler results are for "528B";-)
45	# (**) second number is result for code compiled with -fPIC flag,
46	# which is actually more relevant, because assembler code is
47	# position-independent;
48	# (***) see comment in non-MMX routine for further details;
49	#
50	# To summarize, it's >2-5 times faster than gcc-generated code. To
51	# anchor it to something else SHA1 assembler processes one byte in
52	# ~7 cycles on contemporary x86 cores. As for choice of MMX/SSE
53	# in particular, see comment at the end of the file...
54
55	# May 2010
56	#
57	# Add PCLMULQDQ version performing at 2.10 cycles per processed byte.
58	# The question is how close is it to theoretical limit? The pclmulqdq
59	# instruction latency appears to be 14 cycles and there can't be more
60	# than 2 of them executing at any given time. This means that single
61	# Karatsuba multiplication would take 28 cycles plus few cycles for
62	# pre- and post-processing. Then multiplication has to be followed by
63	# modulo-reduction. Given that aggregated reduction method [see
64	# "Carry-less Multiplication and Its Usage for Computing the GCM Mode"
65	# white paper by Intel] allows you to perform reduction only once in
66	# a while we can assume that asymptotic performance can be estimated
67	# as (28+Tmod/Naggr)/16, where Tmod is time to perform reduction
68	# and Naggr is the aggregation factor.
69	#
70	# Before we proceed to this implementation let's have closer look at
71	# the best-performing code suggested by Intel in their white paper.
72	# By tracing inter-register dependencies Tmod is estimated as ~19
73	# cycles and Naggr chosen by Intel is 4, resulting in 2.05 cycles per
74	# processed byte. As implied, this is quite optimistic estimate,
75	# because it does not account for Karatsuba pre- and post-processing,
76	# which for a single multiplication is ~5 cycles. Unfortunately Intel
77	# does not provide performance data for GHASH alone. But benchmarking
78	# AES_GCM_encrypt ripped out of Fig. 15 of the white paper with aadt
79	# alone resulted in 2.46 cycles per byte of out 16KB buffer. Note that
80	# the result accounts even for pre-computing of degrees of the hash
81	# key H, but its portion is negligible at 16KB buffer size.
82	#
83	# Moving on to the implementation in question. Tmod is estimated as
84	# ~13 cycles and Naggr is 2, giving asymptotic performance of ...
85	# 2.16. How is it possible that measured performance is better than
86	# optimistic theoretical estimate? There is one thing Intel failed
87	# to recognize. By serializing GHASH with CTR in same subroutine
88	# former's performance is really limited to above (Tmul + Tmod/Naggr)
89	# equation. But if GHASH procedure is detached, the modulo-reduction
90	# can be interleaved with Naggr-1 multiplications at instruction level
91	# and under ideal conditions even disappear from the equation. So that
92	# optimistic theoretical estimate for this implementation is ...
93	# 28/16=1.75, and not 2.16. Well, it's probably way too optimistic,
94	# at least for such small Naggr. I'd argue that (28+Tproc/Naggr),
95	# where Tproc is time required for Karatsuba pre- and post-processing,
96	# is more realistic estimate. In this case it gives ... 1.91 cycles.
97	# Or in other words, depending on how well we can interleave reduction
98	# and one of the two multiplications the performance should be between
99	# 1.91 and 2.16. As already mentioned, this implementation processes
100	# one byte out of 8KB buffer in 2.10 cycles, while x86_64 counterpart
101	# - in 2.02. x86_64 performance is better, because larger register
102	# bank allows to interleave reduction and multiplication better.
103	#
104	# Does it make sense to increase Naggr? To start with it's virtually
105	# impossible in 32-bit mode, because of limited register bank
106	# capacity. Otherwise improvement has to be weighed against slower
107	# setup, as well as code size and complexity increase. As even
108	# optimistic estimate doesn't promise 30% performance improvement,
109	# there are currently no plans to increase Naggr.
110	#
111	# Special thanks to David Woodhouse for providing access to a
112	# Westmere-based system on behalf of Intel Open Source Technology Centre.
113
114	# January 2010
115	#
116	# Tweaked to optimize transitions between integer and FP operations
117	# on same XMM register, PCLMULQDQ subroutine was measured to process
118	# one byte in 2.07 cycles on Sandy Bridge, and in 2.12 - on Westmere.
119	# The minor regression on Westmere is outweighed by ~15% improvement
120	# on Sandy Bridge. Strangely enough attempt to modify 64-bit code in
121	# similar manner resulted in almost 20% degradation on Sandy Bridge,
122	# where original 64-bit code processes one byte in 1.95 cycles.
123
124	#####################################################################
125	# For reference, AMD Bulldozer processes one byte in 1.98 cycles in
126	# 32-bit mode and 1.89 in 64-bit.
127
128	# February 2013
129	#
130	# Overhaul: aggregate Karatsuba post-processing, improve ILP in
131	# reduction_alg9. Resulting performance is 1.96 cycles per byte on
132	# Westmere, 1.95 - on Sandy/Ivy Bridge, 1.76 - on Bulldozer.
133
134	$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
135	push(@INC,"${dir}","${dir}../../perlasm");
136	require "x86asm.pl";
137
138	$output=pop and open STDOUT,">$output";
139
140	&asm_init($ARGV[0],$x86only = $ARGV[$#ARGV] eq "386");
141
142	$sse2=0;
143	for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
144
145	($Zhh,$Zhl,$Zlh,$Zll) = ("ebp","edx","ecx","ebx");
146	$inp = "edi";
147	$Htbl = "esi";
148
149
150	$unroll = 0; # Affects x86 loop. Folded loop performs ~7% worse
151	# than unrolled, which has to be weighted against
152	# 2.5x x86-specific code size reduction.
153
154	sub x86_loop {
155	my $off = shift;
156	my $rem = "eax";
157
158	&mov ($Zhh,&DWP(4,$Htbl,$Zll));
159	&mov ($Zhl,&DWP(0,$Htbl,$Zll));
160	&mov ($Zlh,&DWP(12,$Htbl,$Zll));
161	&mov ($Zll,&DWP(8,$Htbl,$Zll));
162	&xor ($rem,$rem); # avoid partial register stalls on PIII
163
164	# shrd practically kills P4, 2.5x deterioration, but P4 has
165	# MMX code-path to execute. shrd runs tad faster [than twice
166	# the shifts, move's and or's] on pre-MMX Pentium (as well as
167	# PIII and Core2), but minimizes code size, spares register
168	# and thus allows to fold the loop...
169	if (!$unroll) {
170	my $cnt = $inp;
171	&mov ($cnt,15);
172	&jmp (&label("x86_loop"));
173	&set_label("x86_loop",16);
174	for($i=1;$i<=2;$i++) {
175	&mov (&LB($rem),&LB($Zll));
176	&shrd ($Zll,$Zlh,4);
177	&and (&LB($rem),0xf);
178	&shrd ($Zlh,$Zhl,4);
179	&shrd ($Zhl,$Zhh,4);
180	&shr ($Zhh,4);
181	&xor ($Zhh,&DWP($off+16,"esp",$rem,4));
182
183	&mov (&LB($rem),&BP($off,"esp",$cnt));
184	if ($i&1) {
185	&and (&LB($rem),0xf0);
186	} else {
187	&shl (&LB($rem),4);
188	}
189
190	&xor ($Zll,&DWP(8,$Htbl,$rem));
191	&xor ($Zlh,&DWP(12,$Htbl,$rem));
192	&xor ($Zhl,&DWP(0,$Htbl,$rem));
193	&xor ($Zhh,&DWP(4,$Htbl,$rem));
194
195	if ($i&1) {
196	&dec ($cnt);
197	&js (&label("x86_break"));
198	} else {
199	&jmp (&label("x86_loop"));
200	}
201	}
202	&set_label("x86_break",16);
203	} else {
204	for($i=1;$i<32;$i++) {
205	&comment($i);
206	&mov (&LB($rem),&LB($Zll));
207	&shrd ($Zll,$Zlh,4);
208	&and (&LB($rem),0xf);
209	&shrd ($Zlh,$Zhl,4);
210	&shrd ($Zhl,$Zhh,4);
211	&shr ($Zhh,4);
212	&xor ($Zhh,&DWP($off+16,"esp",$rem,4));
213
214	if ($i&1) {
215	&mov (&LB($rem),&BP($off+15-($i>>1),"esp"));
216	&and (&LB($rem),0xf0);
217	} else {
218	&mov (&LB($rem),&BP($off+15-($i>>1),"esp"));
219	&shl (&LB($rem),4);
220	}
221
222	&xor ($Zll,&DWP(8,$Htbl,$rem));
223	&xor ($Zlh,&DWP(12,$Htbl,$rem));
224	&xor ($Zhl,&DWP(0,$Htbl,$rem));
225	&xor ($Zhh,&DWP(4,$Htbl,$rem));
226	}
227	}
228	&bswap ($Zll);
229	&bswap ($Zlh);
230	&bswap ($Zhl);
231	if (!$x86only) {
232	&bswap ($Zhh);
233	} else {
234	&mov ("eax",$Zhh);
235	&bswap ("eax");
236	&mov ($Zhh,"eax");
237	}
238	}
239
240	if ($unroll) {
241	&function_begin_B("_x86_gmult_4bit_inner");
242	&x86_loop(4);
243	&ret ();
244	&function_end_B("_x86_gmult_4bit_inner");
245	}
246
247	sub deposit_rem_4bit {
248	my $bias = shift;
249
250	&mov (&DWP($bias+0, "esp"),0x0000<<16);
251	&mov (&DWP($bias+4, "esp"),0x1C20<<16);
252	&mov (&DWP($bias+8, "esp"),0x3840<<16);
253	&mov (&DWP($bias+12,"esp"),0x2460<<16);
254	&mov (&DWP($bias+16,"esp"),0x7080<<16);
255	&mov (&DWP($bias+20,"esp"),0x6CA0<<16);
256	&mov (&DWP($bias+24,"esp"),0x48C0<<16);
257	&mov (&DWP($bias+28,"esp"),0x54E0<<16);
258	&mov (&DWP($bias+32,"esp"),0xE100<<16);
259	&mov (&DWP($bias+36,"esp"),0xFD20<<16);
260	&mov (&DWP($bias+40,"esp"),0xD940<<16);
261	&mov (&DWP($bias+44,"esp"),0xC560<<16);
262	&mov (&DWP($bias+48,"esp"),0x9180<<16);
263	&mov (&DWP($bias+52,"esp"),0x8DA0<<16);
264	&mov (&DWP($bias+56,"esp"),0xA9C0<<16);
265	&mov (&DWP($bias+60,"esp"),0xB5E0<<16);
266	}
267
268
269	$suffix = $x86only ? "" : "_x86";
270
271	&function_begin("gcm_gmult_4bit".$suffix);
272	&stack_push(16+4+1); # +1 for stack alignment
273	&mov ($inp,&wparam(0)); # load Xi
274	&mov ($Htbl,&wparam(1)); # load Htable
275
276	&mov ($Zhh,&DWP(0,$inp)); # load Xi[16]
277	&mov ($Zhl,&DWP(4,$inp));
278	&mov ($Zlh,&DWP(8,$inp));
279	&mov ($Zll,&DWP(12,$inp));
280
281	&deposit_rem_4bit(16);
282
283	&mov (&DWP(0,"esp"),$Zhh); # copy Xi[16] on stack
284	&mov (&DWP(4,"esp"),$Zhl);
285	&mov (&DWP(8,"esp"),$Zlh);
286	&mov (&DWP(12,"esp"),$Zll);
287	&shr ($Zll,20);
288	&and ($Zll,0xf0);
289
290	if ($unroll) {
291	&call ("_x86_gmult_4bit_inner");
292	} else {
293	&x86_loop(0);
294	&mov ($inp,&wparam(0));
295	}
296
297	&mov (&DWP(12,$inp),$Zll);
298	&mov (&DWP(8,$inp),$Zlh);
299	&mov (&DWP(4,$inp),$Zhl);
300	&mov (&DWP(0,$inp),$Zhh);
301	&stack_pop(16+4+1);
302	&function_end("gcm_gmult_4bit".$suffix);
303
304	&function_begin("gcm_ghash_4bit".$suffix);
305	&stack_push(16+4+1); # +1 for 64-bit alignment
306	&mov ($Zll,&wparam(0)); # load Xi
307	&mov ($Htbl,&wparam(1)); # load Htable
308	&mov ($inp,&wparam(2)); # load in
309	&mov ("ecx",&wparam(3)); # load len
310	&add ("ecx",$inp);
311	&mov (&wparam(3),"ecx");
312
313	&mov ($Zhh,&DWP(0,$Zll)); # load Xi[16]
314	&mov ($Zhl,&DWP(4,$Zll));
315	&mov ($Zlh,&DWP(8,$Zll));
316	&mov ($Zll,&DWP(12,$Zll));
317
318	&deposit_rem_4bit(16);
319
320	&set_label("x86_outer_loop",16);
321	&xor ($Zll,&DWP(12,$inp)); # xor with input
322	&xor ($Zlh,&DWP(8,$inp));
323	&xor ($Zhl,&DWP(4,$inp));
324	&xor ($Zhh,&DWP(0,$inp));
325	&mov (&DWP(12,"esp"),$Zll); # dump it on stack
326	&mov (&DWP(8,"esp"),$Zlh);
327	&mov (&DWP(4,"esp"),$Zhl);
328	&mov (&DWP(0,"esp"),$Zhh);
329
330	&shr ($Zll,20);
331	&and ($Zll,0xf0);
332
333	if ($unroll) {
334	&call ("_x86_gmult_4bit_inner");
335	} else {
336	&x86_loop(0);
337	&mov ($inp,&wparam(2));
338	}
339	&lea ($inp,&DWP(16,$inp));
340	&cmp ($inp,&wparam(3));
341	&mov (&wparam(2),$inp) if (!$unroll);
342	&jb (&label("x86_outer_loop"));
343
344	&mov ($inp,&wparam(0)); # load Xi
345	&mov (&DWP(12,$inp),$Zll);
346	&mov (&DWP(8,$inp),$Zlh);
347	&mov (&DWP(4,$inp),$Zhl);
348	&mov (&DWP(0,$inp),$Zhh);
349	&stack_pop(16+4+1);
350	&function_end("gcm_ghash_4bit".$suffix);
351
352
353	if (!$x86only) {{{
354
355	&static_label("rem_4bit");
356
357	if (!$sse2) {{ # pure-MMX "May" version...
358
359	$S=12; # shift factor for rem_4bit
360
361	&function_begin_B("_mmx_gmult_4bit_inner");
362	# MMX version performs 3.5 times better on P4 (see comment in non-MMX
363	# routine for further details), 100% better on Opteron, ~70% better
364	# on Core2 and PIII... In other words effort is considered to be well
365	# spent... Since initial release the loop was unrolled in order to
366	# "liberate" register previously used as loop counter. Instead it's
367	# used to optimize critical path in 'Z.hi ^= rem_4bit[Z.lo&0xf]'.
368	# The path involves move of Z.lo from MMX to integer register,
369	# effective address calculation and finally merge of value to Z.hi.
370	# Reference to rem_4bit is scheduled so late that I had to >>4
371	# rem_4bit elements. This resulted in 20-45% procent improvement
372	# on contemporary µ-archs.
373	{
374	my $cnt;
375	my $rem_4bit = "eax";
376	my @rem = ($Zhh,$Zll);
377	my $nhi = $Zhl;
378	my $nlo = $Zlh;
379
380	my ($Zlo,$Zhi) = ("mm0","mm1");
381	my $tmp = "mm2";
382
383	&xor ($nlo,$nlo); # avoid partial register stalls on PIII
384	&mov ($nhi,$Zll);
385	&mov (&LB($nlo),&LB($nhi));
386	&shl (&LB($nlo),4);
387	&and ($nhi,0xf0);
388	&movq ($Zlo,&QWP(8,$Htbl,$nlo));
389	&movq ($Zhi,&QWP(0,$Htbl,$nlo));
390	&movd ($rem[0],$Zlo);
391
392	for ($cnt=28;$cnt>=-2;$cnt--) {
393	my $odd = $cnt&1;
394	my $nix = $odd ? $nlo : $nhi;
395
396	&shl (&LB($nlo),4) if ($odd);
397	&psrlq ($Zlo,4);
398	&movq ($tmp,$Zhi);
399	&psrlq ($Zhi,4);
400	&pxor ($Zlo,&QWP(8,$Htbl,$nix));
401	&mov (&LB($nlo),&BP($cnt/2,$inp)) if (!$odd && $cnt>=0);
402	&psllq ($tmp,60);
403	&and ($nhi,0xf0) if ($odd);
404	&pxor ($Zhi,&QWP(0,$rem_4bit,$rem[1],8)) if ($cnt<28);
405	&and ($rem[0],0xf);
406	&pxor ($Zhi,&QWP(0,$Htbl,$nix));
407	&mov ($nhi,$nlo) if (!$odd && $cnt>=0);
408	&movd ($rem[1],$Zlo);
409	&pxor ($Zlo,$tmp);
410
411	push (@rem,shift(@rem)); # "rotate" registers
412	}
413
414	&mov ($inp,&DWP(4,$rem_4bit,$rem[1],8)); # last rem_4bit[rem]
415
416	&psrlq ($Zlo,32); # lower part of Zlo is already there
417	&movd ($Zhl,$Zhi);
418	&psrlq ($Zhi,32);
419	&movd ($Zlh,$Zlo);
420	&movd ($Zhh,$Zhi);
421	&shl ($inp,4); # compensate for rem_4bit[i] being >>4
422
423	&bswap ($Zll);
424	&bswap ($Zhl);
425	&bswap ($Zlh);
426	&xor ($Zhh,$inp);
427	&bswap ($Zhh);
428
429	&ret ();
430	}
431	&function_end_B("_mmx_gmult_4bit_inner");
432
433	&function_begin("gcm_gmult_4bit_mmx");
434	&mov ($inp,&wparam(0)); # load Xi
435	&mov ($Htbl,&wparam(1)); # load Htable
436
437	&call (&label("pic_point"));
438	&set_label("pic_point");
439	&blindpop("eax");
440	&lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
441
442	&movz ($Zll,&BP(15,$inp));
443
444	&call ("_mmx_gmult_4bit_inner");
445
446	&mov ($inp,&wparam(0)); # load Xi
447	&emms ();
448	&mov (&DWP(12,$inp),$Zll);
449	&mov (&DWP(4,$inp),$Zhl);
450	&mov (&DWP(8,$inp),$Zlh);
451	&mov (&DWP(0,$inp),$Zhh);
452	&function_end("gcm_gmult_4bit_mmx");
453
454
455	# Streamed version performs 20% better on P4, 7% on Opteron,
456	# 10% on Core2 and PIII...
457	&function_begin("gcm_ghash_4bit_mmx");
458	&mov ($Zhh,&wparam(0)); # load Xi
459	&mov ($Htbl,&wparam(1)); # load Htable
460	&mov ($inp,&wparam(2)); # load in
461	&mov ($Zlh,&wparam(3)); # load len
462
463	&call (&label("pic_point"));
464	&set_label("pic_point");
465	&blindpop("eax");
466	&lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
467
468	&add ($Zlh,$inp);
469	&mov (&wparam(3),$Zlh); # len to point at the end of input
470	&stack_push(4+1); # +1 for stack alignment
471
472	&mov ($Zll,&DWP(12,$Zhh)); # load Xi[16]
473	&mov ($Zhl,&DWP(4,$Zhh));
474	&mov ($Zlh,&DWP(8,$Zhh));
475	&mov ($Zhh,&DWP(0,$Zhh));
476	&jmp (&label("mmx_outer_loop"));
477
478	&set_label("mmx_outer_loop",16);
479	&xor ($Zll,&DWP(12,$inp));
480	&xor ($Zhl,&DWP(4,$inp));
481	&xor ($Zlh,&DWP(8,$inp));
482	&xor ($Zhh,&DWP(0,$inp));
483	&mov (&wparam(2),$inp);
484	&mov (&DWP(12,"esp"),$Zll);
485	&mov (&DWP(4,"esp"),$Zhl);
486	&mov (&DWP(8,"esp"),$Zlh);
487	&mov (&DWP(0,"esp"),$Zhh);
488
489	&mov ($inp,"esp");
490	&shr ($Zll,24);
491
492	&call ("_mmx_gmult_4bit_inner");
493
494	&mov ($inp,&wparam(2));
495	&lea ($inp,&DWP(16,$inp));
496	&cmp ($inp,&wparam(3));
497	&jb (&label("mmx_outer_loop"));
498
499	&mov ($inp,&wparam(0)); # load Xi
500	&emms ();
501	&mov (&DWP(12,$inp),$Zll);
502	&mov (&DWP(4,$inp),$Zhl);
503	&mov (&DWP(8,$inp),$Zlh);
504	&mov (&DWP(0,$inp),$Zhh);
505
506	&stack_pop(4+1);
507	&function_end("gcm_ghash_4bit_mmx");
508
509
510	}} else {{ # "June" MMX version...
511	# ... has slower "April" gcm_gmult_4bit_mmx with folded
512	# loop. This is done to conserve code size...
513	$S=16; # shift factor for rem_4bit
514
515	sub mmx_loop() {
516	# MMX version performs 2.8 times better on P4 (see comment in non-MMX
517	# routine for further details), 40% better on Opteron and Core2, 50%
518	# better on PIII... In other words effort is considered to be well
519	# spent...
520	my $inp = shift;
521	my $rem_4bit = shift;
522	my $cnt = $Zhh;
523	my $nhi = $Zhl;
524	my $nlo = $Zlh;
525	my $rem = $Zll;
526
527	my ($Zlo,$Zhi) = ("mm0","mm1");
528	my $tmp = "mm2";
529
530	&xor ($nlo,$nlo); # avoid partial register stalls on PIII
531	&mov ($nhi,$Zll);
532	&mov (&LB($nlo),&LB($nhi));
533	&mov ($cnt,14);
534	&shl (&LB($nlo),4);
535	&and ($nhi,0xf0);
536	&movq ($Zlo,&QWP(8,$Htbl,$nlo));
537	&movq ($Zhi,&QWP(0,$Htbl,$nlo));
538	&movd ($rem,$Zlo);
539	&jmp (&label("mmx_loop"));
540
541	&set_label("mmx_loop",16);
542	&psrlq ($Zlo,4);
543	&and ($rem,0xf);
544	&movq ($tmp,$Zhi);
545	&psrlq ($Zhi,4);
546	&pxor ($Zlo,&QWP(8,$Htbl,$nhi));
547	&mov (&LB($nlo),&BP(0,$inp,$cnt));
548	&psllq ($tmp,60);
549	&pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
550	&dec ($cnt);
551	&movd ($rem,$Zlo);
552	&pxor ($Zhi,&QWP(0,$Htbl,$nhi));
553	&mov ($nhi,$nlo);
554	&pxor ($Zlo,$tmp);
555	&js (&label("mmx_break"));
556
557	&shl (&LB($nlo),4);
558	&and ($rem,0xf);
559	&psrlq ($Zlo,4);
560	&and ($nhi,0xf0);
561	&movq ($tmp,$Zhi);
562	&psrlq ($Zhi,4);
563	&pxor ($Zlo,&QWP(8,$Htbl,$nlo));
564	&psllq ($tmp,60);
565	&pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
566	&movd ($rem,$Zlo);
567	&pxor ($Zhi,&QWP(0,$Htbl,$nlo));
568	&pxor ($Zlo,$tmp);
569	&jmp (&label("mmx_loop"));
570
571	&set_label("mmx_break",16);
572	&shl (&LB($nlo),4);
573	&and ($rem,0xf);
574	&psrlq ($Zlo,4);
575	&and ($nhi,0xf0);
576	&movq ($tmp,$Zhi);
577	&psrlq ($Zhi,4);
578	&pxor ($Zlo,&QWP(8,$Htbl,$nlo));
579	&psllq ($tmp,60);
580	&pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
581	&movd ($rem,$Zlo);
582	&pxor ($Zhi,&QWP(0,$Htbl,$nlo));
583	&pxor ($Zlo,$tmp);
584
585	&psrlq ($Zlo,4);
586	&and ($rem,0xf);
587	&movq ($tmp,$Zhi);
588	&psrlq ($Zhi,4);
589	&pxor ($Zlo,&QWP(8,$Htbl,$nhi));
590	&psllq ($tmp,60);
591	&pxor ($Zhi,&QWP(0,$rem_4bit,$rem,8));
592	&movd ($rem,$Zlo);
593	&pxor ($Zhi,&QWP(0,$Htbl,$nhi));
594	&pxor ($Zlo,$tmp);
595
596	&psrlq ($Zlo,32); # lower part of Zlo is already there
597	&movd ($Zhl,$Zhi);
598	&psrlq ($Zhi,32);
599	&movd ($Zlh,$Zlo);
600	&movd ($Zhh,$Zhi);
601
602	&bswap ($Zll);
603	&bswap ($Zhl);
604	&bswap ($Zlh);
605	&bswap ($Zhh);
606	}
607
608	&function_begin("gcm_gmult_4bit_mmx");
609	&mov ($inp,&wparam(0)); # load Xi
610	&mov ($Htbl,&wparam(1)); # load Htable
611
612	&call (&label("pic_point"));
613	&set_label("pic_point");
614	&blindpop("eax");
615	&lea ("eax",&DWP(&label("rem_4bit")."-".&label("pic_point"),"eax"));
616
617	&movz ($Zll,&BP(15,$inp));
618
619	&mmx_loop($inp,"eax");
620
621	&emms ();
622	&mov (&DWP(12,$inp),$Zll);
623	&mov (&DWP(4,$inp),$Zhl);
624	&mov (&DWP(8,$inp),$Zlh);
625	&mov (&DWP(0,$inp),$Zhh);
626	&function_end("gcm_gmult_4bit_mmx");
627
628
629	######################################################################
630	# Below subroutine is "528B" variant of "4-bit" GCM GHASH function
631	# (see gcm128.c for details). It provides further 20-40% performance
632	# improvement over above mentioned "May" version.
633
634	&static_label("rem_8bit");
635
636	&function_begin("gcm_ghash_4bit_mmx");
637	{ my ($Zlo,$Zhi) = ("mm7","mm6");
638	my $rem_8bit = "esi";
639	my $Htbl = "ebx";
640
641	# parameter block
642	&mov ("eax",&wparam(0)); # Xi
643	&mov ("ebx",&wparam(1)); # Htable
644	&mov ("ecx",&wparam(2)); # inp
645	&mov ("edx",&wparam(3)); # len
646	&mov ("ebp","esp"); # original %esp
647	&call (&label("pic_point"));
648	&set_label ("pic_point");
649	&blindpop ($rem_8bit);
650	&lea ($rem_8bit,&DWP(&label("rem_8bit")."-".&label("pic_point"),$rem_8bit));
651
652	&sub ("esp",512+16+16); # allocate stack frame...
653	&and ("esp",-64); # ...and align it
654	&sub ("esp",16); # place for (u8)(H[]<<4)
655
656	&add ("edx","ecx"); # pointer to the end of input
657	&mov (&DWP(528+16+0,"esp"),"eax"); # save Xi
658	&mov (&DWP(528+16+8,"esp"),"edx"); # save inp+len
659	&mov (&DWP(528+16+12,"esp"),"ebp"); # save original %esp
660
661	{ my @lo = ("mm0","mm1","mm2");
662	my @hi = ("mm3","mm4","mm5");
663	my @tmp = ("mm6","mm7");
664	my ($off1,$off2,$i) = (0,0,);
665
666	&add ($Htbl,128); # optimize for size
667	&lea ("edi",&DWP(16+128,"esp"));
668	&lea ("ebp",&DWP(16+256+128,"esp"));
669
670	# decompose Htable (low and high parts are kept separately),
671	# generate Htable[]>>4, (u8)(Htable[]<<4), save to stack...
672	for ($i=0;$i<18;$i++) {
673
674	&mov ("edx",&DWP(16*$i+8-128,$Htbl)) if ($i<16);
675	&movq ($lo[0],&QWP(16*$i+8-128,$Htbl)) if ($i<16);
676	&psllq ($tmp[1],60) if ($i>1);
677	&movq ($hi[0],&QWP(16*$i+0-128,$Htbl)) if ($i<16);
678	&por ($lo[2],$tmp[1]) if ($i>1);
679	&movq (&QWP($off1-128,"edi"),$lo[1]) if ($i>0 && $i<17);
680	&psrlq ($lo[1],4) if ($i>0 && $i<17);
681	&movq (&QWP($off1,"edi"),$hi[1]) if ($i>0 && $i<17);
682	&movq ($tmp[0],$hi[1]) if ($i>0 && $i<17);
683	&movq (&QWP($off2-128,"ebp"),$lo[2]) if ($i>1);
684	&psrlq ($hi[1],4) if ($i>0 && $i<17);
685	&movq (&QWP($off2,"ebp"),$hi[2]) if ($i>1);
686	&shl ("edx",4) if ($i<16);
687	&mov (&BP($i,"esp"),&LB("edx")) if ($i<16);
688
689	unshift (@lo,pop(@lo)); # "rotate" registers
690	unshift (@hi,pop(@hi));
691	unshift (@tmp,pop(@tmp));
692	$off1 += 8 if ($i>0);
693	$off2 += 8 if ($i>1);
694	}
695	}
696
697	&movq ($Zhi,&QWP(0,"eax"));
698	&mov ("ebx",&DWP(8,"eax"));
699	&mov ("edx",&DWP(12,"eax")); # load Xi
700
701	&set_label("outer",16);
702	{ my $nlo = "eax";
703	my $dat = "edx";
704	my @nhi = ("edi","ebp");
705	my @rem = ("ebx","ecx");
706	my @red = ("mm0","mm1","mm2");
707	my $tmp = "mm3";
708
709	&xor ($dat,&DWP(12,"ecx")); # merge input data
710	&xor ("ebx",&DWP(8,"ecx"));
711	&pxor ($Zhi,&QWP(0,"ecx"));
712	&lea ("ecx",&DWP(16,"ecx")); # inp+=16
713	#&mov (&DWP(528+12,"esp"),$dat); # save inp^Xi
714	&mov (&DWP(528+8,"esp"),"ebx");
715	&movq (&QWP(528+0,"esp"),$Zhi);
716	&mov (&DWP(528+16+4,"esp"),"ecx"); # save inp
717
718	&xor ($nlo,$nlo);
719	&rol ($dat,8);
720	&mov (&LB($nlo),&LB($dat));
721	&mov ($nhi[1],$nlo);
722	&and (&LB($nlo),0x0f);
723	&shr ($nhi[1],4);
724	&pxor ($red[0],$red[0]);
725	&rol ($dat,8); # next byte
726	&pxor ($red[1],$red[1]);
727	&pxor ($red[2],$red[2]);
728
729	# Just like in "May" version modulo-schedule for critical path in
730	# 'Z.hi ^= rem_8bit[Z.lo&0xff^((u8)H[nhi]<<4)]<<48'. Final 'pxor'
731	# is scheduled so late that rem_8bit[] has to be shifted right
732	# by 16, which is why last argument to pinsrw is 2, which
733	# corresponds to <<32=<<48>>16...
734	for ($j=11,$i=0;$i<15;$i++) {
735
736	if ($i>0) {
737	&pxor ($Zlo,&QWP(16,"esp",$nlo,8)); # Z^=H[nlo]
738	&rol ($dat,8); # next byte
739	&pxor ($Zhi,&QWP(16+128,"esp",$nlo,8));
740
741	&pxor ($Zlo,$tmp);
742	&pxor ($Zhi,&QWP(16+256+128,"esp",$nhi[0],8));
743	&xor (&LB($rem[1]),&BP(0,"esp",$nhi[0])); # rem^(H[nhi]<<4)
744	} else {
745	&movq ($Zlo,&QWP(16,"esp",$nlo,8));
746	&movq ($Zhi,&QWP(16+128,"esp",$nlo,8));
747	}
748
749	&mov (&LB($nlo),&LB($dat));
750	&mov ($dat,&DWP(528+$j,"esp")) if (--$j%4==0);
751
752	&movd ($rem[0],$Zlo);
753	&movz ($rem[1],&LB($rem[1])) if ($i>0);
754	&psrlq ($Zlo,8); # Z>>=8
755
756	&movq ($tmp,$Zhi);
757	&mov ($nhi[0],$nlo);
758	&psrlq ($Zhi,8);
759
760	&pxor ($Zlo,&QWP(16+256+0,"esp",$nhi[1],8)); # Z^=H[nhi]>>4
761	&and (&LB($nlo),0x0f);
762	&psllq ($tmp,56);
763
764	&pxor ($Zhi,$red[1]) if ($i>1);
765	&shr ($nhi[0],4);
766	&pinsrw ($red[0],&WP(0,$rem_8bit,$rem[1],2),2) if ($i>0);
767
768	unshift (@red,pop(@red)); # "rotate" registers
769	unshift (@rem,pop(@rem));
770	unshift (@nhi,pop(@nhi));
771	}
772
773	&pxor ($Zlo,&QWP(16,"esp",$nlo,8)); # Z^=H[nlo]
774	&pxor ($Zhi,&QWP(16+128,"esp",$nlo,8));
775	&xor (&LB($rem[1]),&BP(0,"esp",$nhi[0])); # rem^(H[nhi]<<4)
776
777	&pxor ($Zlo,$tmp);
778	&pxor ($Zhi,&QWP(16+256+128,"esp",$nhi[0],8));
779	&movz ($rem[1],&LB($rem[1]));
780
781	&pxor ($red[2],$red[2]); # clear 2nd word
782	&psllq ($red[1],4);
783
784	&movd ($rem[0],$Zlo);
785	&psrlq ($Zlo,4); # Z>>=4
786
787	&movq ($tmp,$Zhi);
788	&psrlq ($Zhi,4);
789	&shl ($rem[0],4); # rem<<4
790
791	&pxor ($Zlo,&QWP(16,"esp",$nhi[1],8)); # Z^=H[nhi]
792	&psllq ($tmp,60);
793	&movz ($rem[0],&LB($rem[0]));
794
795	&pxor ($Zlo,$tmp);
796	&pxor ($Zhi,&QWP(16+128,"esp",$nhi[1],8));
797
798	&pinsrw ($red[0],&WP(0,$rem_8bit,$rem[1],2),2);
799	&pxor ($Zhi,$red[1]);
800
801	&movd ($dat,$Zlo);
802	&pinsrw ($red[2],&WP(0,$rem_8bit,$rem[0],2),3); # last is <<48
803
804	&psllq ($red[0],12); # correct by <<16>>4
805	&pxor ($Zhi,$red[0]);
806	&psrlq ($Zlo,32);
807	&pxor ($Zhi,$red[2]);
808
809	&mov ("ecx",&DWP(528+16+4,"esp")); # restore inp
810	&movd ("ebx",$Zlo);
811	&movq ($tmp,$Zhi); # 01234567
812	&psllw ($Zhi,8); # 1.3.5.7.
813	&psrlw ($tmp,8); # .0.2.4.6
814	&por ($Zhi,$tmp); # 10325476
815	&bswap ($dat);
816	&pshufw ($Zhi,$Zhi,0b00011011); # 76543210
817	&bswap ("ebx");
818
819	&cmp ("ecx",&DWP(528+16+8,"esp")); # are we done?
820	&jne (&label("outer"));
821	}
822
823	&mov ("eax",&DWP(528+16+0,"esp")); # restore Xi
824	&mov (&DWP(12,"eax"),"edx");
825	&mov (&DWP(8,"eax"),"ebx");
826	&movq (&QWP(0,"eax"),$Zhi);
827
828	&mov ("esp",&DWP(528+16+12,"esp")); # restore original %esp
829	&emms ();
830	}
831	&function_end("gcm_ghash_4bit_mmx");
832	}}
833
834
835	if ($sse2) {{
836	######################################################################
837	# PCLMULQDQ version.
838
839	$Xip="eax";
840	$Htbl="edx";
841	$const="ecx";
842	$inp="esi";
843	$len="ebx";
844
845	($Xi,$Xhi)=("xmm0","xmm1"); $Hkey="xmm2";
846	($T1,$T2,$T3)=("xmm3","xmm4","xmm5");
847	($Xn,$Xhn)=("xmm6","xmm7");
848
849	&static_label("bswap");
850
851	sub clmul64x64_T2 { # minimal "register" pressure
852	my ($Xhi,$Xi,$Hkey,$HK)=@_;
853
854	&movdqa ($Xhi,$Xi); #
855	&pshufd ($T1,$Xi,0b01001110);
856	&pshufd ($T2,$Hkey,0b01001110) if (!defined($HK));
857	&pxor ($T1,$Xi); #
858	&pxor ($T2,$Hkey) if (!defined($HK));
859	$HK=$T2 if (!defined($HK));
860
861	&pclmulqdq ($Xi,$Hkey,0x00); #######
862	&pclmulqdq ($Xhi,$Hkey,0x11); #######
863	&pclmulqdq ($T1,$HK,0x00); #######
864	&xorps ($T1,$Xi); #
865	&xorps ($T1,$Xhi); #
866
867	&movdqa ($T2,$T1); #
868	&psrldq ($T1,8);
869	&pslldq ($T2,8); #
870	&pxor ($Xhi,$T1);
871	&pxor ($Xi,$T2); #
872	}
873
874	sub clmul64x64_T3 {
875	# Even though this subroutine offers visually better ILP, it
876	# was empirically found to be a tad slower than above version.
877	# At least in gcm_ghash_clmul context. But it's just as well,
878	# because loop modulo-scheduling is possible only thanks to
879	# minimized "register" pressure...
880	my ($Xhi,$Xi,$Hkey)=@_;
881
882	&movdqa ($T1,$Xi); #
883	&movdqa ($Xhi,$Xi);
884	&pclmulqdq ($Xi,$Hkey,0x00); #######
885	&pclmulqdq ($Xhi,$Hkey,0x11); #######
886	&pshufd ($T2,$T1,0b01001110); #
887	&pshufd ($T3,$Hkey,0b01001110);
888	&pxor ($T2,$T1); #
889	&pxor ($T3,$Hkey);
890	&pclmulqdq ($T2,$T3,0x00); #######
891	&pxor ($T2,$Xi); #
892	&pxor ($T2,$Xhi); #
893
894	&movdqa ($T3,$T2); #
895	&psrldq ($T2,8);
896	&pslldq ($T3,8); #
897	&pxor ($Xhi,$T2);
898	&pxor ($Xi,$T3); #
899	}
900
901
902	if (1) { # Algorithm 9 with <<1 twist.
903	# Reduction is shorter and uses only two
904	# temporary registers, which makes it better
905	# candidate for interleaving with 64x64
906	# multiplication. Pre-modulo-scheduled loop
907	# was found to be ~20% faster than Algorithm 5
908	# below. Algorithm 9 was therefore chosen for
909	# further optimization...
910
911	sub reduction_alg9 { # 17/11 times faster than Intel version
912	my ($Xhi,$Xi) = @_;
913
914	# 1st phase
915	&movdqa ($T2,$Xi); #
916	&movdqa ($T1,$Xi);
917	&psllq ($Xi,5);
918	&pxor ($T1,$Xi); #
919	&psllq ($Xi,1);
920	&pxor ($Xi,$T1); #
921	&psllq ($Xi,57); #
922	&movdqa ($T1,$Xi); #
923	&pslldq ($Xi,8);
924	&psrldq ($T1,8); #
925	&pxor ($Xi,$T2);
926	&pxor ($Xhi,$T1); #
927
928	# 2nd phase
929	&movdqa ($T2,$Xi);
930	&psrlq ($Xi,1);
931	&pxor ($Xhi,$T2); #
932	&pxor ($T2,$Xi);
933	&psrlq ($Xi,5);
934	&pxor ($Xi,$T2); #
935	&psrlq ($Xi,1); #
936	&pxor ($Xi,$Xhi) #
937	}
938
939	&function_begin_B("gcm_init_clmul");
940	&mov ($Htbl,&wparam(0));
941	&mov ($Xip,&wparam(1));
942
943	&call (&label("pic"));
944	&set_label("pic");
945	&blindpop ($const);
946	&lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
947
948	&movdqu ($Hkey,&QWP(0,$Xip));
949	&pshufd ($Hkey,$Hkey,0b01001110);# dword swap
950
951	# <<1 twist
952	&pshufd ($T2,$Hkey,0b11111111); # broadcast uppermost dword
953	&movdqa ($T1,$Hkey);
954	&psllq ($Hkey,1);
955	&pxor ($T3,$T3); #
956	&psrlq ($T1,63);
957	&pcmpgtd ($T3,$T2); # broadcast carry bit
958	&pslldq ($T1,8);
959	&por ($Hkey,$T1); # H<<=1
960
961	# magic reduction
962	&pand ($T3,&QWP(16,$const)); # 0x1c2_polynomial
963	&pxor ($Hkey,$T3); # if(carry) H^=0x1c2_polynomial
964
965	# calculate H^2
966	&movdqa ($Xi,$Hkey);
967	&clmul64x64_T2 ($Xhi,$Xi,$Hkey);
968	&reduction_alg9 ($Xhi,$Xi);
969
970	&pshufd ($T1,$Hkey,0b01001110);
971	&pshufd ($T2,$Xi,0b01001110);
972	&pxor ($T1,$Hkey); # Karatsuba pre-processing
973	&movdqu (&QWP(0,$Htbl),$Hkey); # save H
974	&pxor ($T2,$Xi); # Karatsuba pre-processing
975	&movdqu (&QWP(16,$Htbl),$Xi); # save H^2
976	&palignr ($T2,$T1,8); # low part is H.lo^H.hi
977	&movdqu (&QWP(32,$Htbl),$T2); # save Karatsuba "salt"
978
979	&ret ();
980	&function_end_B("gcm_init_clmul");
981
982	&function_begin_B("gcm_gmult_clmul");
983	&mov ($Xip,&wparam(0));
984	&mov ($Htbl,&wparam(1));
985
986	&call (&label("pic"));
987	&set_label("pic");
988	&blindpop ($const);
989	&lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
990
991	&movdqu ($Xi,&QWP(0,$Xip));
992	&movdqa ($T3,&QWP(0,$const));
993	&movups ($Hkey,&QWP(0,$Htbl));
994	&pshufb ($Xi,$T3);
995	&movups ($T2,&QWP(32,$Htbl));
996
997	&clmul64x64_T2 ($Xhi,$Xi,$Hkey,$T2);
998	&reduction_alg9 ($Xhi,$Xi);
999
1000	&pshufb ($Xi,$T3);
1001	&movdqu (&QWP(0,$Xip),$Xi);
1002
1003	&ret ();
1004	&function_end_B("gcm_gmult_clmul");
1005
1006	&function_begin("gcm_ghash_clmul");
1007	&mov ($Xip,&wparam(0));
1008	&mov ($Htbl,&wparam(1));
1009	&mov ($inp,&wparam(2));
1010	&mov ($len,&wparam(3));
1011
1012	&call (&label("pic"));
1013	&set_label("pic");
1014	&blindpop ($const);
1015	&lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1016
1017	&movdqu ($Xi,&QWP(0,$Xip));
1018	&movdqa ($T3,&QWP(0,$const));
1019	&movdqu ($Hkey,&QWP(0,$Htbl));
1020	&pshufb ($Xi,$T3);
1021
1022	&sub ($len,0x10);
1023	&jz (&label("odd_tail"));
1024
1025	#######
1026	# Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
1027	# [(HIi+1) + (HXi+1)] mod P =
1028	# [(HIi+1) + H^2(Ii+Xi)] mod P
1029	#
1030	&movdqu ($T1,&QWP(0,$inp)); # Ii
1031	&movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1032	&pshufb ($T1,$T3);
1033	&pshufb ($Xn,$T3);
1034	&movdqu ($T3,&QWP(32,$Htbl));
1035	&pxor ($Xi,$T1); # Ii+Xi
1036
1037	&pshufd ($T1,$Xn,0b01001110); # H*Ii+1
1038	&movdqa ($Xhn,$Xn);
1039	&pxor ($T1,$Xn); #
1040	&lea ($inp,&DWP(32,$inp)); # i+=2
1041
1042	&pclmulqdq ($Xn,$Hkey,0x00); #######
1043	&pclmulqdq ($Xhn,$Hkey,0x11); #######
1044	&pclmulqdq ($T1,$T3,0x00); #######
1045	&movups ($Hkey,&QWP(16,$Htbl)); # load H^2
1046	&nop ();
1047
1048	&sub ($len,0x20);
1049	&jbe (&label("even_tail"));
1050	&jmp (&label("mod_loop"));
1051
1052	&set_label("mod_loop",32);
1053	&pshufd ($T2,$Xi,0b01001110); # H^2*(Ii+Xi)
1054	&movdqa ($Xhi,$Xi);
1055	&pxor ($T2,$Xi); #
1056	&nop ();
1057
1058	&pclmulqdq ($Xi,$Hkey,0x00); #######
1059	&pclmulqdq ($Xhi,$Hkey,0x11); #######
1060	&pclmulqdq ($T2,$T3,0x10); #######
1061	&movups ($Hkey,&QWP(0,$Htbl)); # load H
1062
1063	&xorps ($Xi,$Xn); # (HIi+1) + H^2(Ii+Xi)
1064	&movdqa ($T3,&QWP(0,$const));
1065	&xorps ($Xhi,$Xhn);
1066	&movdqu ($Xhn,&QWP(0,$inp)); # Ii
1067	&pxor ($T1,$Xi); # aggregated Karatsuba post-processing
1068	&movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1069	&pxor ($T1,$Xhi); #
1070
1071	&pshufb ($Xhn,$T3);
1072	&pxor ($T2,$T1); #
1073
1074	&movdqa ($T1,$T2); #
1075	&psrldq ($T2,8);
1076	&pslldq ($T1,8); #
1077	&pxor ($Xhi,$T2);
1078	&pxor ($Xi,$T1); #
1079	&pshufb ($Xn,$T3);
1080	&pxor ($Xhi,$Xhn); # "Ii+Xi", consume early
1081
1082	&movdqa ($Xhn,$Xn); #&clmul64x64_TX ($Xhn,$Xn,$Hkey); H*Ii+1
1083	&movdqa ($T2,$Xi); #&reduction_alg9($Xhi,$Xi); 1st phase
1084	&movdqa ($T1,$Xi);
1085	&psllq ($Xi,5);
1086	&pxor ($T1,$Xi); #
1087	&psllq ($Xi,1);
1088	&pxor ($Xi,$T1); #
1089	&pclmulqdq ($Xn,$Hkey,0x00); #######
1090	&movups ($T3,&QWP(32,$Htbl));
1091	&psllq ($Xi,57); #
1092	&movdqa ($T1,$Xi); #
1093	&pslldq ($Xi,8);
1094	&psrldq ($T1,8); #
1095	&pxor ($Xi,$T2);
1096	&pxor ($Xhi,$T1); #
1097	&pshufd ($T1,$Xhn,0b01001110);
1098	&movdqa ($T2,$Xi); # 2nd phase
1099	&psrlq ($Xi,1);
1100	&pxor ($T1,$Xhn);
1101	&pxor ($Xhi,$T2); #
1102	&pclmulqdq ($Xhn,$Hkey,0x11); #######
1103	&movups ($Hkey,&QWP(16,$Htbl)); # load H^2
1104	&pxor ($T2,$Xi);
1105	&psrlq ($Xi,5);
1106	&pxor ($Xi,$T2); #
1107	&psrlq ($Xi,1); #
1108	&pxor ($Xi,$Xhi) #
1109	&pclmulqdq ($T1,$T3,0x00); #######
1110
1111	&lea ($inp,&DWP(32,$inp));
1112	&sub ($len,0x20);
1113	&ja (&label("mod_loop"));
1114
1115	&set_label("even_tail");
1116	&pshufd ($T2,$Xi,0b01001110); # H^2*(Ii+Xi)
1117	&movdqa ($Xhi,$Xi);
1118	&pxor ($T2,$Xi); #
1119
1120	&pclmulqdq ($Xi,$Hkey,0x00); #######
1121	&pclmulqdq ($Xhi,$Hkey,0x11); #######
1122	&pclmulqdq ($T2,$T3,0x10); #######
1123	&movdqa ($T3,&QWP(0,$const));
1124
1125	&xorps ($Xi,$Xn); # (HIi+1) + H^2(Ii+Xi)
1126	&xorps ($Xhi,$Xhn);
1127	&pxor ($T1,$Xi); # aggregated Karatsuba post-processing
1128	&pxor ($T1,$Xhi); #
1129
1130	&pxor ($T2,$T1); #
1131
1132	&movdqa ($T1,$T2); #
1133	&psrldq ($T2,8);
1134	&pslldq ($T1,8); #
1135	&pxor ($Xhi,$T2);
1136	&pxor ($Xi,$T1); #
1137
1138	&reduction_alg9 ($Xhi,$Xi);
1139
1140	&test ($len,$len);
1141	&jnz (&label("done"));
1142
1143	&movups ($Hkey,&QWP(0,$Htbl)); # load H
1144	&set_label("odd_tail");
1145	&movdqu ($T1,&QWP(0,$inp)); # Ii
1146	&pshufb ($T1,$T3);
1147	&pxor ($Xi,$T1); # Ii+Xi
1148
1149	&clmul64x64_T2 ($Xhi,$Xi,$Hkey); # H*(Ii+Xi)
1150	&reduction_alg9 ($Xhi,$Xi);
1151
1152	&set_label("done");
1153	&pshufb ($Xi,$T3);
1154	&movdqu (&QWP(0,$Xip),$Xi);
1155	&function_end("gcm_ghash_clmul");
1156
1157
1158	} else { # Algorithm 5. Kept for reference purposes.
1159
1160	sub reduction_alg5 { # 19/16 times faster than Intel version
1161	my ($Xhi,$Xi)=@_;
1162
1163	# <<1
1164	&movdqa ($T1,$Xi); #
1165	&movdqa ($T2,$Xhi);
1166	&pslld ($Xi,1);
1167	&pslld ($Xhi,1); #
1168	&psrld ($T1,31);
1169	&psrld ($T2,31); #
1170	&movdqa ($T3,$T1);
1171	&pslldq ($T1,4);
1172	&psrldq ($T3,12); #
1173	&pslldq ($T2,4);
1174	&por ($Xhi,$T3); #
1175	&por ($Xi,$T1);
1176	&por ($Xhi,$T2); #
1177
1178	# 1st phase
1179	&movdqa ($T1,$Xi);
1180	&movdqa ($T2,$Xi);
1181	&movdqa ($T3,$Xi); #
1182	&pslld ($T1,31);
1183	&pslld ($T2,30);
1184	&pslld ($Xi,25); #
1185	&pxor ($T1,$T2);
1186	&pxor ($T1,$Xi); #
1187	&movdqa ($T2,$T1); #
1188	&pslldq ($T1,12);
1189	&psrldq ($T2,4); #
1190	&pxor ($T3,$T1);
1191
1192	# 2nd phase
1193	&pxor ($Xhi,$T3); #
1194	&movdqa ($Xi,$T3);
1195	&movdqa ($T1,$T3);
1196	&psrld ($Xi,1); #
1197	&psrld ($T1,2);
1198	&psrld ($T3,7); #
1199	&pxor ($Xi,$T1);
1200	&pxor ($Xhi,$T2);
1201	&pxor ($Xi,$T3); #
1202	&pxor ($Xi,$Xhi); #
1203	}
1204
1205	&function_begin_B("gcm_init_clmul");
1206	&mov ($Htbl,&wparam(0));
1207	&mov ($Xip,&wparam(1));
1208
1209	&call (&label("pic"));
1210	&set_label("pic");
1211	&blindpop ($const);
1212	&lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1213
1214	&movdqu ($Hkey,&QWP(0,$Xip));
1215	&pshufd ($Hkey,$Hkey,0b01001110);# dword swap
1216
1217	# calculate H^2
1218	&movdqa ($Xi,$Hkey);
1219	&clmul64x64_T3 ($Xhi,$Xi,$Hkey);
1220	&reduction_alg5 ($Xhi,$Xi);
1221
1222	&movdqu (&QWP(0,$Htbl),$Hkey); # save H
1223	&movdqu (&QWP(16,$Htbl),$Xi); # save H^2
1224
1225	&ret ();
1226	&function_end_B("gcm_init_clmul");
1227
1228	&function_begin_B("gcm_gmult_clmul");
1229	&mov ($Xip,&wparam(0));
1230	&mov ($Htbl,&wparam(1));
1231
1232	&call (&label("pic"));
1233	&set_label("pic");
1234	&blindpop ($const);
1235	&lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1236
1237	&movdqu ($Xi,&QWP(0,$Xip));
1238	&movdqa ($Xn,&QWP(0,$const));
1239	&movdqu ($Hkey,&QWP(0,$Htbl));
1240	&pshufb ($Xi,$Xn);
1241
1242	&clmul64x64_T3 ($Xhi,$Xi,$Hkey);
1243	&reduction_alg5 ($Xhi,$Xi);
1244
1245	&pshufb ($Xi,$Xn);
1246	&movdqu (&QWP(0,$Xip),$Xi);
1247
1248	&ret ();
1249	&function_end_B("gcm_gmult_clmul");
1250
1251	&function_begin("gcm_ghash_clmul");
1252	&mov ($Xip,&wparam(0));
1253	&mov ($Htbl,&wparam(1));
1254	&mov ($inp,&wparam(2));
1255	&mov ($len,&wparam(3));
1256
1257	&call (&label("pic"));
1258	&set_label("pic");
1259	&blindpop ($const);
1260	&lea ($const,&DWP(&label("bswap")."-".&label("pic"),$const));
1261
1262	&movdqu ($Xi,&QWP(0,$Xip));
1263	&movdqa ($T3,&QWP(0,$const));
1264	&movdqu ($Hkey,&QWP(0,$Htbl));
1265	&pshufb ($Xi,$T3);
1266
1267	&sub ($len,0x10);
1268	&jz (&label("odd_tail"));
1269
1270	#######
1271	# Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
1272	# [(HIi+1) + (HXi+1)] mod P =
1273	# [(HIi+1) + H^2(Ii+Xi)] mod P
1274	#
1275	&movdqu ($T1,&QWP(0,$inp)); # Ii
1276	&movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1277	&pshufb ($T1,$T3);
1278	&pshufb ($Xn,$T3);
1279	&pxor ($Xi,$T1); # Ii+Xi
1280
1281	&clmul64x64_T3 ($Xhn,$Xn,$Hkey); # H*Ii+1
1282	&movdqu ($Hkey,&QWP(16,$Htbl)); # load H^2
1283
1284	&sub ($len,0x20);
1285	&lea ($inp,&DWP(32,$inp)); # i+=2
1286	&jbe (&label("even_tail"));
1287
1288	&set_label("mod_loop");
1289	&clmul64x64_T3 ($Xhi,$Xi,$Hkey); # H^2*(Ii+Xi)
1290	&movdqu ($Hkey,&QWP(0,$Htbl)); # load H
1291
1292	&pxor ($Xi,$Xn); # (HIi+1) + H^2(Ii+Xi)
1293	&pxor ($Xhi,$Xhn);
1294
1295	&reduction_alg5 ($Xhi,$Xi);
1296
1297	#######
1298	&movdqa ($T3,&QWP(0,$const));
1299	&movdqu ($T1,&QWP(0,$inp)); # Ii
1300	&movdqu ($Xn,&QWP(16,$inp)); # Ii+1
1301	&pshufb ($T1,$T3);
1302	&pshufb ($Xn,$T3);
1303	&pxor ($Xi,$T1); # Ii+Xi
1304
1305	&clmul64x64_T3 ($Xhn,$Xn,$Hkey); # H*Ii+1
1306	&movdqu ($Hkey,&QWP(16,$Htbl)); # load H^2
1307
1308	&sub ($len,0x20);
1309	&lea ($inp,&DWP(32,$inp));
1310	&ja (&label("mod_loop"));
1311
1312	&set_label("even_tail");
1313	&clmul64x64_T3 ($Xhi,$Xi,$Hkey); # H^2*(Ii+Xi)
1314
1315	&pxor ($Xi,$Xn); # (HIi+1) + H^2(Ii+Xi)
1316	&pxor ($Xhi,$Xhn);
1317
1318	&reduction_alg5 ($Xhi,$Xi);
1319
1320	&movdqa ($T3,&QWP(0,$const));
1321	&test ($len,$len);
1322	&jnz (&label("done"));
1323
1324	&movdqu ($Hkey,&QWP(0,$Htbl)); # load H
1325	&set_label("odd_tail");
1326	&movdqu ($T1,&QWP(0,$inp)); # Ii
1327	&pshufb ($T1,$T3);
1328	&pxor ($Xi,$T1); # Ii+Xi
1329
1330	&clmul64x64_T3 ($Xhi,$Xi,$Hkey); # H*(Ii+Xi)
1331	&reduction_alg5 ($Xhi,$Xi);
1332
1333	&movdqa ($T3,&QWP(0,$const));
1334	&set_label("done");
1335	&pshufb ($Xi,$T3);
1336	&movdqu (&QWP(0,$Xip),$Xi);
1337	&function_end("gcm_ghash_clmul");
1338
1339	}
1340
1341
1342	&set_label("bswap",64);
1343	&data_byte(15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0);
1344	&data_byte(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0xc2); # 0x1c2_polynomial
1345	&set_label("rem_8bit",64);
1346	&data_short(0x0000,0x01C2,0x0384,0x0246,0x0708,0x06CA,0x048C,0x054E);
1347	&data_short(0x0E10,0x0FD2,0x0D94,0x0C56,0x0918,0x08DA,0x0A9C,0x0B5E);
1348	&data_short(0x1C20,0x1DE2,0x1FA4,0x1E66,0x1B28,0x1AEA,0x18AC,0x196E);
1349	&data_short(0x1230,0x13F2,0x11B4,0x1076,0x1538,0x14FA,0x16BC,0x177E);
1350	&data_short(0x3840,0x3982,0x3BC4,0x3A06,0x3F48,0x3E8A,0x3CCC,0x3D0E);
1351	&data_short(0x3650,0x3792,0x35D4,0x3416,0x3158,0x309A,0x32DC,0x331E);
1352	&data_short(0x2460,0x25A2,0x27E4,0x2626,0x2368,0x22AA,0x20EC,0x212E);
1353	&data_short(0x2A70,0x2BB2,0x29F4,0x2836,0x2D78,0x2CBA,0x2EFC,0x2F3E);
1354	&data_short(0x7080,0x7142,0x7304,0x72C6,0x7788,0x764A,0x740C,0x75CE);
1355	&data_short(0x7E90,0x7F52,0x7D14,0x7CD6,0x7998,0x785A,0x7A1C,0x7BDE);
1356	&data_short(0x6CA0,0x6D62,0x6F24,0x6EE6,0x6BA8,0x6A6A,0x682C,0x69EE);
1357	&data_short(0x62B0,0x6372,0x6134,0x60F6,0x65B8,0x647A,0x663C,0x67FE);
1358	&data_short(0x48C0,0x4902,0x4B44,0x4A86,0x4FC8,0x4E0A,0x4C4C,0x4D8E);
1359	&data_short(0x46D0,0x4712,0x4554,0x4496,0x41D8,0x401A,0x425C,0x439E);
1360	&data_short(0x54E0,0x5522,0x5764,0x56A6,0x53E8,0x522A,0x506C,0x51AE);
1361	&data_short(0x5AF0,0x5B32,0x5974,0x58B6,0x5DF8,0x5C3A,0x5E7C,0x5FBE);
1362	&data_short(0xE100,0xE0C2,0xE284,0xE346,0xE608,0xE7CA,0xE58C,0xE44E);
1363	&data_short(0xEF10,0xEED2,0xEC94,0xED56,0xE818,0xE9DA,0xEB9C,0xEA5E);
1364	&data_short(0xFD20,0xFCE2,0xFEA4,0xFF66,0xFA28,0xFBEA,0xF9AC,0xF86E);
1365	&data_short(0xF330,0xF2F2,0xF0B4,0xF176,0xF438,0xF5FA,0xF7BC,0xF67E);
1366	&data_short(0xD940,0xD882,0xDAC4,0xDB06,0xDE48,0xDF8A,0xDDCC,0xDC0E);
1367	&data_short(0xD750,0xD692,0xD4D4,0xD516,0xD058,0xD19A,0xD3DC,0xD21E);
1368	&data_short(0xC560,0xC4A2,0xC6E4,0xC726,0xC268,0xC3AA,0xC1EC,0xC02E);
1369	&data_short(0xCB70,0xCAB2,0xC8F4,0xC936,0xCC78,0xCDBA,0xCFFC,0xCE3E);
1370	&data_short(0x9180,0x9042,0x9204,0x93C6,0x9688,0x974A,0x950C,0x94CE);
1371	&data_short(0x9F90,0x9E52,0x9C14,0x9DD6,0x9898,0x995A,0x9B1C,0x9ADE);
1372	&data_short(0x8DA0,0x8C62,0x8E24,0x8FE6,0x8AA8,0x8B6A,0x892C,0x88EE);
1373	&data_short(0x83B0,0x8272,0x8034,0x81F6,0x84B8,0x857A,0x873C,0x86FE);
1374	&data_short(0xA9C0,0xA802,0xAA44,0xAB86,0xAEC8,0xAF0A,0xAD4C,0xAC8E);
1375	&data_short(0xA7D0,0xA612,0xA454,0xA596,0xA0D8,0xA11A,0xA35C,0xA29E);
1376	&data_short(0xB5E0,0xB422,0xB664,0xB7A6,0xB2E8,0xB32A,0xB16C,0xB0AE);
1377	&data_short(0xBBF0,0xBA32,0xB874,0xB9B6,0xBCF8,0xBD3A,0xBF7C,0xBEBE);
1378	}} # $sse2
1379
1380	&set_label("rem_4bit",64);
1381	&data_word(0,0x0000<<$S,0,0x1C20<<$S,0,0x3840<<$S,0,0x2460<<$S);
1382	&data_word(0,0x7080<<$S,0,0x6CA0<<$S,0,0x48C0<<$S,0,0x54E0<<$S);
1383	&data_word(0,0xE100<<$S,0,0xFD20<<$S,0,0xD940<<$S,0,0xC560<<$S);
1384	&data_word(0,0x9180<<$S,0,0x8DA0<<$S,0,0xA9C0<<$S,0,0xB5E0<<$S);
1385	}}} # !$x86only
1386
1387	&asciz("GHASH for x86, CRYPTOGAMS by <appro\@openssl.org>");
1388	&asm_finish();
1389
1390	close STDOUT or die "error closing STDOUT: $!";
1391
1392	# A question was risen about choice of vanilla MMX. Or rather why wasn't
1393	# SSE2 chosen instead? In addition to the fact that MMX runs on legacy
1394	# CPUs such as PIII, "4-bit" MMX version was observed to provide better
1395	# performance than corresponding SSE2 one even on contemporary CPUs.
1396	# SSE2 results were provided by Peter-Michael Hager. He maintains SSE2
1397	# implementation featuring full range of lookup-table sizes, but with
1398	# per-invocation lookup table setup. Latter means that table size is
1399	# chosen depending on how much data is to be hashed in every given call,
1400	# more data - larger table. Best reported result for Core2 is ~4 cycles
1401	# per processed byte out of 64KB block. This number accounts even for
1402	# 64KB table setup overhead. As discussed in gcm128.c we choose to be
1403	# more conservative in respect to lookup table sizes, but how do the
1404	# results compare? Minimalistic "256B" MMX version delivers ~11 cycles
1405	# on same platform. As also discussed in gcm128.c, next in line "8-bit
1406	# Shoup's" or "4KB" method should deliver twice the performance of
1407	# "256B" one, in other words not worse than ~6 cycles per byte. It
1408	# should be also be noted that in SSE2 case improvement can be "super-
1409	# linear," i.e. more than twice, mostly because >>8 maps to single
1410	# instruction on SSE2 register. This is unlike "4-bit" case when >>4
1411	# maps to same amount of instructions in both MMX and SSE2 cases.
1412	# Bottom line is that switch to SSE2 is considered to be justifiable
1413	# only in case we choose to implement "8-bit" method...

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source: vbox/trunk/src/libs/openssl-3.0.7/crypto/modes/asm/ghash-x86.pl@ 98024

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