VirtualBox

source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 17831

Last change on this file since 17831 was 17538, checked in by vboxsync, 16 years ago

REM,PGM: Added two mutualy exclusive flags to REMR3NotifyPhysRamRegister to indicate whether it's MMIO2 or RAM that's being registered. This is for the new code only, the old one sticks to the MM_RAM_FLAGS.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 157.0 KB
Line 
1/* $Id: VBoxRecompiler.c 17538 2009-03-08 05:32:49Z vboxsync $ */
2/** @file
3 * VBox Recompiler - QEMU.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_REM
27#include "vl.h"
28#include "exec-all.h"
29
30#include <VBox/rem.h>
31#include <VBox/vmapi.h>
32#include <VBox/tm.h>
33#include <VBox/ssm.h>
34#include <VBox/em.h>
35#include <VBox/trpm.h>
36#include <VBox/iom.h>
37#include <VBox/mm.h>
38#include <VBox/pgm.h>
39#include <VBox/pdm.h>
40#include <VBox/dbgf.h>
41#include <VBox/dbg.h>
42#include <VBox/hwaccm.h>
43#include <VBox/patm.h>
44#include <VBox/csam.h>
45#include "REMInternal.h"
46#include <VBox/vm.h>
47#include <VBox/param.h>
48#include <VBox/err.h>
49
50#include <VBox/log.h>
51#include <iprt/semaphore.h>
52#include <iprt/asm.h>
53#include <iprt/assert.h>
54#include <iprt/thread.h>
55#include <iprt/string.h>
56
57/* Don't wanna include everything. */
58extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
59extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
60extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
61extern void tlb_flush_page(CPUX86State *env, target_ulong addr);
62extern void tlb_flush(CPUState *env, int flush_global);
63extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
64extern void sync_ldtr(CPUX86State *env1, int selector);
65
66#ifdef VBOX_STRICT
67unsigned long get_phys_page_offset(target_ulong addr);
68#endif
69
70
71/*******************************************************************************
72* Defined Constants And Macros *
73*******************************************************************************/
74
75/** Copy 80-bit fpu register at pSrc to pDst.
76 * This is probably faster than *calling* memcpy.
77 */
78#define REM_COPY_FPU_REG(pDst, pSrc) \
79 do { *(PX86FPUMMX)(pDst) = *(const X86FPUMMX *)(pSrc); } while (0)
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
87static void remR3StateUpdate(PVM pVM);
88static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded);
89
90static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
91static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
92static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
93static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
94static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96
97static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
98static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
99static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
100static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
101static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103
104
105/*******************************************************************************
106* Global Variables *
107*******************************************************************************/
108
109/** @todo Move stats to REM::s some rainy day we have nothing do to. */
110#ifdef VBOX_WITH_STATISTICS
111static STAMPROFILEADV gStatExecuteSingleInstr;
112static STAMPROFILEADV gStatCompilationQEmu;
113static STAMPROFILEADV gStatRunCodeQEmu;
114static STAMPROFILEADV gStatTotalTimeQEmu;
115static STAMPROFILEADV gStatTimers;
116static STAMPROFILEADV gStatTBLookup;
117static STAMPROFILEADV gStatIRQ;
118static STAMPROFILEADV gStatRawCheck;
119static STAMPROFILEADV gStatMemRead;
120static STAMPROFILEADV gStatMemWrite;
121static STAMPROFILE gStatGCPhys2HCVirt;
122static STAMPROFILE gStatHCVirt2GCPhys;
123static STAMCOUNTER gStatCpuGetTSC;
124static STAMCOUNTER gStatRefuseTFInhibit;
125static STAMCOUNTER gStatRefuseVM86;
126static STAMCOUNTER gStatRefusePaging;
127static STAMCOUNTER gStatRefusePAE;
128static STAMCOUNTER gStatRefuseIOPLNot0;
129static STAMCOUNTER gStatRefuseIF0;
130static STAMCOUNTER gStatRefuseCode16;
131static STAMCOUNTER gStatRefuseWP0;
132static STAMCOUNTER gStatRefuseRing1or2;
133static STAMCOUNTER gStatRefuseCanExecute;
134static STAMCOUNTER gStatREMGDTChange;
135static STAMCOUNTER gStatREMIDTChange;
136static STAMCOUNTER gStatREMLDTRChange;
137static STAMCOUNTER gStatREMTRChange;
138static STAMCOUNTER gStatSelOutOfSync[6];
139static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
140static STAMCOUNTER gStatFlushTBs;
141/* in exec.c */
142extern uint32_t tlb_flush_count;
143extern uint32_t tb_flush_count;
144extern uint32_t tb_phys_invalidate_count;
145#endif
146
147/*
148 * Global stuff.
149 */
150
151/** MMIO read callbacks. */
152CPUReadMemoryFunc *g_apfnMMIORead[3] =
153{
154 remR3MMIOReadU8,
155 remR3MMIOReadU16,
156 remR3MMIOReadU32
157};
158
159/** MMIO write callbacks. */
160CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
161{
162 remR3MMIOWriteU8,
163 remR3MMIOWriteU16,
164 remR3MMIOWriteU32
165};
166
167/** Handler read callbacks. */
168CPUReadMemoryFunc *g_apfnHandlerRead[3] =
169{
170 remR3HandlerReadU8,
171 remR3HandlerReadU16,
172 remR3HandlerReadU32
173};
174
175/** Handler write callbacks. */
176CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
177{
178 remR3HandlerWriteU8,
179 remR3HandlerWriteU16,
180 remR3HandlerWriteU32
181};
182
183
184#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
185/*
186 * Debugger commands.
187 */
188static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
189
190/** '.remstep' arguments. */
191static const DBGCVARDESC g_aArgRemStep[] =
192{
193 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
194 { 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
195};
196
197/** Command descriptors. */
198static const DBGCCMD g_aCmds[] =
199{
200 {
201 .pszCmd ="remstep",
202 .cArgsMin = 0,
203 .cArgsMax = 1,
204 .paArgDescs = &g_aArgRemStep[0],
205 .cArgDescs = RT_ELEMENTS(g_aArgRemStep),
206 .pResultDesc = NULL,
207 .fFlags = 0,
208 .pfnHandler = remR3CmdDisasEnableStepping,
209 .pszSyntax = "[on/off]",
210 .pszDescription = "Enable or disable the single stepping with logged disassembly. "
211 "If no arguments show the current state."
212 }
213};
214#endif
215
216
217/* Instantiate the structure signatures. */
218#define REM_STRUCT_OP 0
219#include "Sun/structs.h"
220
221
222
223/*******************************************************************************
224* Internal Functions *
225*******************************************************************************/
226static void remAbort(int rc, const char *pszTip);
227extern int testmath(void);
228
229/* Put them here to avoid unused variable warning. */
230AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
231#if !defined(IPRT_NO_CRT) && (defined(RT_OS_LINUX) || defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS))
232//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
233/* Why did this have to be identical?? */
234AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
235#else
236AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
237#endif
238
239
240/**
241 * Initializes the REM.
242 *
243 * @returns VBox status code.
244 * @param pVM The VM to operate on.
245 */
246REMR3DECL(int) REMR3Init(PVM pVM)
247{
248 uint32_t u32Dummy;
249 unsigned i;
250
251 /*
252 * Assert sanity.
253 */
254 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
255 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
256 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
257#if defined(DEBUG) && !defined(RT_OS_SOLARIS) /// @todo fix the solaris math stuff.
258 Assert(!testmath());
259#endif
260 ASSERT_STRUCT_TABLE(Misc);
261 ASSERT_STRUCT_TABLE(TLB);
262 ASSERT_STRUCT_TABLE(SegmentCache);
263 ASSERT_STRUCT_TABLE(XMMReg);
264 ASSERT_STRUCT_TABLE(MMXReg);
265 ASSERT_STRUCT_TABLE(float_status);
266 ASSERT_STRUCT_TABLE(float32u);
267 ASSERT_STRUCT_TABLE(float64u);
268 ASSERT_STRUCT_TABLE(floatx80u);
269 ASSERT_STRUCT_TABLE(CPUState);
270
271 /*
272 * Init some internal data members.
273 */
274 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
275 pVM->rem.s.Env.pVM = pVM;
276#ifdef CPU_RAW_MODE_INIT
277 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
278#endif
279
280 /* ctx. */
281 pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
282 AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
283
284 /* ignore all notifications */
285 pVM->rem.s.fIgnoreAll = true;
286
287 /*
288 * Init the recompiler.
289 */
290 if (!cpu_x86_init(&pVM->rem.s.Env))
291 {
292 AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
293 return VERR_GENERAL_FAILURE;
294 }
295 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
296 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
297
298 /* allocate code buffer for single instruction emulation. */
299 pVM->rem.s.Env.cbCodeBuffer = 4096;
300 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
301 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
302
303 /* finally, set the cpu_single_env global. */
304 cpu_single_env = &pVM->rem.s.Env;
305
306 /* Nothing is pending by default */
307 pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
308
309 /*
310 * Register ram types.
311 */
312 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(-1, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
313 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
314 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(-1, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
315 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
316 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
317
318 /* stop ignoring. */
319 pVM->rem.s.fIgnoreAll = false;
320
321 /*
322 * Register the saved state data unit.
323 */
324 int rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
325 NULL, remR3Save, NULL,
326 NULL, remR3Load, NULL);
327 if (RT_FAILURE(rc))
328 return rc;
329
330#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
331 /*
332 * Debugger commands.
333 */
334 static bool fRegisteredCmds = false;
335 if (!fRegisteredCmds)
336 {
337 int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
338 if (RT_SUCCESS(rc))
339 fRegisteredCmds = true;
340 }
341#endif
342
343#ifdef VBOX_WITH_STATISTICS
344 /*
345 * Statistics.
346 */
347 STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
348 STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
349 STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
350 STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
351 STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
352 STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
353 STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
354 STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
355 STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
356 STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
357 STAM_REG(pVM, &gStatHCVirt2GCPhys, STAMTYPE_PROFILE, "/PROF/REM/HCVirt2GCPhys", STAMUNIT_TICKS_PER_CALL, "Profiling memory convertion.");
358 STAM_REG(pVM, &gStatGCPhys2HCVirt, STAMTYPE_PROFILE, "/PROF/REM/GCPhys2HCVirt", STAMUNIT_TICKS_PER_CALL, "Profiling memory convertion.");
359
360 STAM_REG(pVM, &gStatCpuGetTSC, STAMTYPE_COUNTER, "/REM/CpuGetTSC", STAMUNIT_OCCURENCES, "cpu_get_tsc calls");
361
362 STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
363 STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
364 STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
365 STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
366 STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
367 STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
368 STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
369 STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
370 STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
371 STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
372 STAM_REG(pVM, &gStatFlushTBs, STAMTYPE_COUNTER, "/REM/FlushTB", STAMUNIT_OCCURENCES, "Number of TB flushes");
373
374 STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
375 STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
376 STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
377 STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
378
379 STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
380 STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
381 STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
382 STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
383 STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
384 STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
385
386 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
387 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
388 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
389 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
390 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
391 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
392
393 STAM_REG(pVM, &tb_flush_count, STAMTYPE_U32_RESET, "/REM/TbFlushCount", STAMUNIT_OCCURENCES, "tb_flush() calls");
394 STAM_REG(pVM, &tb_phys_invalidate_count,STAMTYPE_U32_RESET, "/REM/TbPhysInvldCount", STAMUNIT_OCCURENCES, "tb_phys_invalidate() calls");
395 STAM_REG(pVM, &tlb_flush_count, STAMTYPE_U32_RESET, "/REM/TlbFlushCount", STAMUNIT_OCCURENCES, "tlb_flush() calls");
396
397
398#endif
399
400#ifdef DEBUG_ALL_LOGGING
401 loglevel = ~0;
402#endif
403
404 return rc;
405}
406
407
408/**
409 * Finalizes the REM initialization.
410 *
411 * This is called after all components, devices and drivers has
412 * been initialized. Its main purpose it to finish the RAM related
413 * initialization.
414 *
415 * @returns VBox status code.
416 *
417 * @param pVM The VM handle.
418 */
419REMR3DECL(int) REMR3InitFinalize(PVM pVM)
420{
421 int rc;
422
423 /*
424 * Ram size & dirty bit map.
425 */
426 Assert(!pVM->rem.s.fGCPhysLastRamFixed);
427 pVM->rem.s.fGCPhysLastRamFixed = true;
428#ifdef RT_STRICT
429 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, true /* fGuarded */);
430#else
431 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, false /* fGuarded */);
432#endif
433 return rc;
434}
435
436
437/**
438 * Initializes phys_ram_size, phys_ram_dirty and phys_ram_dirty_size.
439 *
440 * @returns VBox status code.
441 * @param pVM The VM handle.
442 * @param fGuarded Whether to guard the map.
443 */
444static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded)
445{
446 int rc = VINF_SUCCESS;
447 RTGCPHYS cb;
448
449 cb = pVM->rem.s.GCPhysLastRam + 1;
450 AssertLogRelMsgReturn(cb > pVM->rem.s.GCPhysLastRam,
451 ("GCPhysLastRam=%RGp - out of range\n", pVM->rem.s.GCPhysLastRam),
452 VERR_OUT_OF_RANGE);
453 phys_ram_size = cb;
454 phys_ram_dirty_size = cb >> PAGE_SHIFT;
455 AssertMsg(((RTGCPHYS)phys_ram_dirty_size << PAGE_SHIFT) == cb, ("%RGp\n", cb));
456
457 if (!fGuarded)
458 {
459 phys_ram_dirty = MMR3HeapAlloc(pVM, MM_TAG_REM, phys_ram_dirty_size);
460 AssertLogRelMsgReturn(phys_ram_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", phys_ram_dirty_size), VERR_NO_MEMORY);
461 }
462 else
463 {
464 /*
465 * Fill it up the nearest 4GB RAM and leave at least _64KB of guard after it.
466 */
467 uint32_t cbBitmapAligned = RT_ALIGN_32(phys_ram_dirty_size, PAGE_SIZE);
468 uint32_t cbBitmapFull = RT_ALIGN_32(phys_ram_dirty_size, (_4G >> PAGE_SHIFT));
469 if (cbBitmapFull == cbBitmapAligned)
470 cbBitmapFull += _4G >> PAGE_SHIFT;
471 else if (cbBitmapFull - cbBitmapAligned < _64K)
472 cbBitmapFull += _64K;
473
474 phys_ram_dirty = RTMemPageAlloc(cbBitmapFull);
475 AssertLogRelMsgReturn(phys_ram_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", cbBitmapFull), VERR_NO_MEMORY);
476
477 rc = RTMemProtect(phys_ram_dirty + cbBitmapAligned, cbBitmapFull - cbBitmapAligned, RTMEM_PROT_NONE);
478 if (RT_FAILURE(rc))
479 {
480 RTMemPageFree(phys_ram_dirty);
481 AssertLogRelRCReturn(rc, rc);
482 }
483
484 phys_ram_dirty += cbBitmapAligned - phys_ram_dirty_size;
485 }
486
487 /* initialize it. */
488 memset(phys_ram_dirty, 0xff, phys_ram_dirty_size);
489 return rc;
490}
491
492
493/**
494 * Terminates the REM.
495 *
496 * Termination means cleaning up and freeing all resources,
497 * the VM it self is at this point powered off or suspended.
498 *
499 * @returns VBox status code.
500 * @param pVM The VM to operate on.
501 */
502REMR3DECL(int) REMR3Term(PVM pVM)
503{
504 return VINF_SUCCESS;
505}
506
507
508/**
509 * The VM is being reset.
510 *
511 * For the REM component this means to call the cpu_reset() and
512 * reinitialize some state variables.
513 *
514 * @param pVM VM handle.
515 */
516REMR3DECL(void) REMR3Reset(PVM pVM)
517{
518 /*
519 * Reset the REM cpu.
520 */
521 pVM->rem.s.fIgnoreAll = true;
522 cpu_reset(&pVM->rem.s.Env);
523 pVM->rem.s.cInvalidatedPages = 0;
524 pVM->rem.s.fIgnoreAll = false;
525
526 /* Clear raw ring 0 init state */
527 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
528
529 /* Flush the TBs the next time we execute code here. */
530 pVM->rem.s.fFlushTBs = true;
531}
532
533
534/**
535 * Execute state save operation.
536 *
537 * @returns VBox status code.
538 * @param pVM VM Handle.
539 * @param pSSM SSM operation handle.
540 */
541static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
542{
543 LogFlow(("remR3Save:\n"));
544
545 /*
546 * Save the required CPU Env bits.
547 * (Not much because we're never in REM when doing the save.)
548 */
549 PREM pRem = &pVM->rem.s;
550 Assert(!pRem->fInREM);
551 SSMR3PutU32(pSSM, pRem->Env.hflags);
552 SSMR3PutU32(pSSM, ~0); /* separator */
553
554 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
555 SSMR3PutU32(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
556 SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
557
558 return SSMR3PutU32(pSSM, ~0); /* terminator */
559}
560
561
562/**
563 * Execute state load operation.
564 *
565 * @returns VBox status code.
566 * @param pVM VM Handle.
567 * @param pSSM SSM operation handle.
568 * @param u32Version Data layout version.
569 */
570static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
571{
572 uint32_t u32Dummy;
573 uint32_t fRawRing0 = false;
574 LogFlow(("remR3Load:\n"));
575
576 /*
577 * Validate version.
578 */
579 if ( u32Version != REM_SAVED_STATE_VERSION
580 && u32Version != REM_SAVED_STATE_VERSION_VER1_6)
581 {
582 AssertMsgFailed(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
583 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
584 }
585
586 /*
587 * Do a reset to be on the safe side...
588 */
589 REMR3Reset(pVM);
590
591 /*
592 * Ignore all ignorable notifications.
593 * (Not doing this will cause serious trouble.)
594 */
595 pVM->rem.s.fIgnoreAll = true;
596
597 /*
598 * Load the required CPU Env bits.
599 * (Not much because we're never in REM when doing the save.)
600 */
601 PREM pRem = &pVM->rem.s;
602 Assert(!pRem->fInREM);
603 SSMR3GetU32(pSSM, &pRem->Env.hflags);
604 if (u32Version == REM_SAVED_STATE_VERSION_VER1_6)
605 {
606 /* Redundant REM CPU state has to be loaded, but can be ignored. */
607 CPUX86State_Ver16 temp;
608 SSMR3GetMem(pSSM, &temp, RT_OFFSETOF(CPUX86State_Ver16, jmp_env));
609 }
610
611 uint32_t u32Sep;
612 int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
613 if (RT_FAILURE(rc))
614 return rc;
615 if (u32Sep != ~0U)
616 {
617 AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
618 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
619 }
620
621 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
622 SSMR3GetUInt(pSSM, &fRawRing0);
623 if (fRawRing0)
624 pRem->Env.state |= CPU_RAW_RING0;
625
626 if (u32Version == REM_SAVED_STATE_VERSION_VER1_6)
627 {
628 /*
629 * Load the REM stuff.
630 */
631 rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
632 if (RT_FAILURE(rc))
633 return rc;
634 if (pRem->cInvalidatedPages > RT_ELEMENTS(pRem->aGCPtrInvalidatedPages))
635 {
636 AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
637 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
638 }
639 unsigned i;
640 for (i = 0; i < pRem->cInvalidatedPages; i++)
641 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
642 }
643
644 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
645 if (RT_FAILURE(rc))
646 return rc;
647
648 /* check the terminator. */
649 rc = SSMR3GetU32(pSSM, &u32Sep);
650 if (RT_FAILURE(rc))
651 return rc;
652 if (u32Sep != ~0U)
653 {
654 AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
655 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
656 }
657
658 /*
659 * Get the CPUID features.
660 */
661 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
662 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
663
664 /*
665 * Sync the Load Flush the TLB
666 */
667 tlb_flush(&pRem->Env, 1);
668
669 /*
670 * Stop ignoring ignornable notifications.
671 */
672 pVM->rem.s.fIgnoreAll = false;
673
674 /*
675 * Sync the whole CPU state when executing code in the recompiler.
676 */
677 CPUMSetChangedFlags(pVM, CPUM_CHANGED_ALL);
678 return VINF_SUCCESS;
679}
680
681
682
683#undef LOG_GROUP
684#define LOG_GROUP LOG_GROUP_REM_RUN
685
686/**
687 * Single steps an instruction in recompiled mode.
688 *
689 * Before calling this function the REM state needs to be in sync with
690 * the VM. Call REMR3State() to perform the sync. It's only necessary
691 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
692 * and after calling REMR3StateBack().
693 *
694 * @returns VBox status code.
695 *
696 * @param pVM VM Handle.
697 */
698REMR3DECL(int) REMR3Step(PVM pVM)
699{
700 /*
701 * Lock the REM - we don't wanna have anyone interrupting us
702 * while stepping - and enabled single stepping. We also ignore
703 * pending interrupts and suchlike.
704 */
705 int interrupt_request = pVM->rem.s.Env.interrupt_request;
706 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER)));
707 pVM->rem.s.Env.interrupt_request = 0;
708 cpu_single_step(&pVM->rem.s.Env, 1);
709
710 /*
711 * If we're standing at a breakpoint, that have to be disabled before we start stepping.
712 */
713 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
714 bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
715
716 /*
717 * Execute and handle the return code.
718 * We execute without enabling the cpu tick, so on success we'll
719 * just flip it on and off to make sure it moves
720 */
721 int rc = cpu_exec(&pVM->rem.s.Env);
722 if (rc == EXCP_DEBUG)
723 {
724 TMCpuTickResume(pVM);
725 TMCpuTickPause(pVM);
726 TMVirtualResume(pVM);
727 TMVirtualPause(pVM);
728 rc = VINF_EM_DBG_STEPPED;
729 }
730 else
731 {
732 AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
733 switch (rc)
734 {
735 case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
736 case EXCP_HLT:
737 case EXCP_HALTED: rc = VINF_EM_HALT; break;
738 case EXCP_RC:
739 rc = pVM->rem.s.rc;
740 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
741 break;
742 default:
743 AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
744 rc = VERR_INTERNAL_ERROR;
745 break;
746 }
747 }
748
749 /*
750 * Restore the stuff we changed to prevent interruption.
751 * Unlock the REM.
752 */
753 if (fBp)
754 {
755 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
756 Assert(rc2 == 0); NOREF(rc2);
757 }
758 cpu_single_step(&pVM->rem.s.Env, 0);
759 pVM->rem.s.Env.interrupt_request = interrupt_request;
760
761 return rc;
762}
763
764
765/**
766 * Set a breakpoint using the REM facilities.
767 *
768 * @returns VBox status code.
769 * @param pVM The VM handle.
770 * @param Address The breakpoint address.
771 * @thread The emulation thread.
772 */
773REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
774{
775 VM_ASSERT_EMT(pVM);
776 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
777 {
778 LogFlow(("REMR3BreakpointSet: Address=%RGv\n", Address));
779 return VINF_SUCCESS;
780 }
781 LogFlow(("REMR3BreakpointSet: Address=%RGv - failed!\n", Address));
782 return VERR_REM_NO_MORE_BP_SLOTS;
783}
784
785
786/**
787 * Clears a breakpoint set by REMR3BreakpointSet().
788 *
789 * @returns VBox status code.
790 * @param pVM The VM handle.
791 * @param Address The breakpoint address.
792 * @thread The emulation thread.
793 */
794REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
795{
796 VM_ASSERT_EMT(pVM);
797 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
798 {
799 LogFlow(("REMR3BreakpointClear: Address=%RGv\n", Address));
800 return VINF_SUCCESS;
801 }
802 LogFlow(("REMR3BreakpointClear: Address=%RGv - not found!\n", Address));
803 return VERR_REM_BP_NOT_FOUND;
804}
805
806
807/**
808 * Emulate an instruction.
809 *
810 * This function executes one instruction without letting anyone
811 * interrupt it. This is intended for being called while being in
812 * raw mode and thus will take care of all the state syncing between
813 * REM and the rest.
814 *
815 * @returns VBox status code.
816 * @param pVM VM handle.
817 */
818REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
819{
820 bool fFlushTBs;
821
822 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
823
824 /* Make sure this flag is set; we might never execute remR3CanExecuteRaw in the AMD-V case.
825 * CPU_RAW_HWACC makes sure we never execute interrupt handlers in the recompiler.
826 */
827 if (HWACCMIsEnabled(pVM))
828 pVM->rem.s.Env.state |= CPU_RAW_HWACC;
829
830 /* Skip the TB flush as that's rather expensive and not necessary for single instruction emulation. */
831 fFlushTBs = pVM->rem.s.fFlushTBs;
832 pVM->rem.s.fFlushTBs = false;
833
834 /*
835 * Sync the state and enable single instruction / single stepping.
836 */
837 int rc = REMR3State(pVM);
838 pVM->rem.s.fFlushTBs = fFlushTBs;
839 if (RT_SUCCESS(rc))
840 {
841 int interrupt_request = pVM->rem.s.Env.interrupt_request;
842 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER)));
843 Assert(!pVM->rem.s.Env.singlestep_enabled);
844#if 1
845
846 /*
847 * Now we set the execute single instruction flag and enter the cpu_exec loop.
848 */
849 TMNotifyStartOfExecution(pVM);
850 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
851 rc = cpu_exec(&pVM->rem.s.Env);
852 TMNotifyEndOfExecution(pVM);
853 switch (rc)
854 {
855 /*
856 * Executed without anything out of the way happening.
857 */
858 case EXCP_SINGLE_INSTR:
859 rc = VINF_EM_RESCHEDULE;
860 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
861 break;
862
863 /*
864 * If we take a trap or start servicing a pending interrupt, we might end up here.
865 * (Timer thread or some other thread wishing EMT's attention.)
866 */
867 case EXCP_INTERRUPT:
868 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
869 rc = VINF_EM_RESCHEDULE;
870 break;
871
872 /*
873 * Single step, we assume!
874 * If there was a breakpoint there we're fucked now.
875 */
876 case EXCP_DEBUG:
877 {
878 /* breakpoint or single step? */
879 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
880 int iBP;
881 rc = VINF_EM_DBG_STEPPED;
882 for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
883 if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
884 {
885 rc = VINF_EM_DBG_BREAKPOINT;
886 break;
887 }
888 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc iBP=%d GCPtrPC=%RGv\n", rc, iBP, GCPtrPC));
889 break;
890 }
891
892 /*
893 * hlt instruction.
894 */
895 case EXCP_HLT:
896 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
897 rc = VINF_EM_HALT;
898 break;
899
900 /*
901 * The VM has halted.
902 */
903 case EXCP_HALTED:
904 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
905 rc = VINF_EM_HALT;
906 break;
907
908 /*
909 * Switch to RAW-mode.
910 */
911 case EXCP_EXECUTE_RAW:
912 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
913 rc = VINF_EM_RESCHEDULE_RAW;
914 break;
915
916 /*
917 * Switch to hardware accelerated RAW-mode.
918 */
919 case EXCP_EXECUTE_HWACC:
920 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
921 rc = VINF_EM_RESCHEDULE_HWACC;
922 break;
923
924 /*
925 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
926 */
927 case EXCP_RC:
928 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
929 rc = pVM->rem.s.rc;
930 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
931 break;
932
933 /*
934 * Figure out the rest when they arrive....
935 */
936 default:
937 AssertMsgFailed(("rc=%d\n", rc));
938 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
939 rc = VINF_EM_RESCHEDULE;
940 break;
941 }
942
943 /*
944 * Switch back the state.
945 */
946#else
947 pVM->rem.s.Env.interrupt_request = 0;
948 cpu_single_step(&pVM->rem.s.Env, 1);
949
950 /*
951 * Execute and handle the return code.
952 * We execute without enabling the cpu tick, so on success we'll
953 * just flip it on and off to make sure it moves.
954 *
955 * (We do not use emulate_single_instr() because that doesn't enter the
956 * right way in will cause serious trouble if a longjmp was attempted.)
957 */
958# ifdef DEBUG_bird
959 remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
960# endif
961 TMNotifyStartOfExecution(pVM);
962 int cTimesMax = 16384;
963 uint32_t eip = pVM->rem.s.Env.eip;
964 do
965 {
966 rc = cpu_exec(&pVM->rem.s.Env);
967
968 } while ( eip == pVM->rem.s.Env.eip
969 && (rc == EXCP_DEBUG || rc == EXCP_EXECUTE_RAW)
970 && --cTimesMax > 0);
971 TMNotifyEndOfExecution(pVM);
972 switch (rc)
973 {
974 /*
975 * Single step, we assume!
976 * If there was a breakpoint there we're fucked now.
977 */
978 case EXCP_DEBUG:
979 {
980 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
981 rc = VINF_EM_RESCHEDULE;
982 break;
983 }
984
985 /*
986 * We cannot be interrupted!
987 */
988 case EXCP_INTERRUPT:
989 AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
990 rc = VERR_INTERNAL_ERROR;
991 break;
992
993 /*
994 * hlt instruction.
995 */
996 case EXCP_HLT:
997 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
998 rc = VINF_EM_HALT;
999 break;
1000
1001 /*
1002 * The VM has halted.
1003 */
1004 case EXCP_HALTED:
1005 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
1006 rc = VINF_EM_HALT;
1007 break;
1008
1009 /*
1010 * Switch to RAW-mode.
1011 */
1012 case EXCP_EXECUTE_RAW:
1013 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1014 rc = VINF_EM_RESCHEDULE_RAW;
1015 break;
1016
1017 /*
1018 * Switch to hardware accelerated RAW-mode.
1019 */
1020 case EXCP_EXECUTE_HWACC:
1021 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1022 rc = VINF_EM_RESCHEDULE_HWACC;
1023 break;
1024
1025 /*
1026 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1027 */
1028 case EXCP_RC:
1029 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1030 rc = pVM->rem.s.rc;
1031 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1032 break;
1033
1034 /*
1035 * Figure out the rest when they arrive....
1036 */
1037 default:
1038 AssertMsgFailed(("rc=%d\n", rc));
1039 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
1040 rc = VINF_SUCCESS;
1041 break;
1042 }
1043
1044 /*
1045 * Switch back the state.
1046 */
1047 cpu_single_step(&pVM->rem.s.Env, 0);
1048#endif
1049 pVM->rem.s.Env.interrupt_request = interrupt_request;
1050 int rc2 = REMR3StateBack(pVM);
1051 AssertRC(rc2);
1052 }
1053
1054 Log2(("REMR3EmulateInstruction: returns %Rrc (cs:eip=%04x:%RGv)\n",
1055 rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1056 return rc;
1057}
1058
1059
1060/**
1061 * Runs code in recompiled mode.
1062 *
1063 * Before calling this function the REM state needs to be in sync with
1064 * the VM. Call REMR3State() to perform the sync. It's only necessary
1065 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
1066 * and after calling REMR3StateBack().
1067 *
1068 * @returns VBox status code.
1069 *
1070 * @param pVM VM Handle.
1071 */
1072REMR3DECL(int) REMR3Run(PVM pVM)
1073{
1074 Log2(("REMR3Run: (cs:eip=%04x:%RGv)\n", pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1075 Assert(pVM->rem.s.fInREM);
1076
1077 TMNotifyStartOfExecution(pVM);
1078 int rc = cpu_exec(&pVM->rem.s.Env);
1079 TMNotifyEndOfExecution(pVM);
1080 switch (rc)
1081 {
1082 /*
1083 * This happens when the execution was interrupted
1084 * by an external event, like pending timers.
1085 */
1086 case EXCP_INTERRUPT:
1087 Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
1088 rc = VINF_SUCCESS;
1089 break;
1090
1091 /*
1092 * hlt instruction.
1093 */
1094 case EXCP_HLT:
1095 Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
1096 rc = VINF_EM_HALT;
1097 break;
1098
1099 /*
1100 * The VM has halted.
1101 */
1102 case EXCP_HALTED:
1103 Log2(("REMR3Run: cpu_exec -> EXCP_HALTED\n"));
1104 rc = VINF_EM_HALT;
1105 break;
1106
1107 /*
1108 * Breakpoint/single step.
1109 */
1110 case EXCP_DEBUG:
1111 {
1112#if 0//def DEBUG_bird
1113 static int iBP = 0;
1114 printf("howdy, breakpoint! iBP=%d\n", iBP);
1115 switch (iBP)
1116 {
1117 case 0:
1118 cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
1119 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
1120 //pVM->rem.s.Env.interrupt_request = 0;
1121 //pVM->rem.s.Env.exception_index = -1;
1122 //g_fInterruptDisabled = 1;
1123 rc = VINF_SUCCESS;
1124 asm("int3");
1125 break;
1126 default:
1127 asm("int3");
1128 break;
1129 }
1130 iBP++;
1131#else
1132 /* breakpoint or single step? */
1133 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1134 int iBP;
1135 rc = VINF_EM_DBG_STEPPED;
1136 for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
1137 if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
1138 {
1139 rc = VINF_EM_DBG_BREAKPOINT;
1140 break;
1141 }
1142 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc iBP=%d GCPtrPC=%RGv\n", rc, iBP, GCPtrPC));
1143#endif
1144 break;
1145 }
1146
1147 /*
1148 * Switch to RAW-mode.
1149 */
1150 case EXCP_EXECUTE_RAW:
1151 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1152 rc = VINF_EM_RESCHEDULE_RAW;
1153 break;
1154
1155 /*
1156 * Switch to hardware accelerated RAW-mode.
1157 */
1158 case EXCP_EXECUTE_HWACC:
1159 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1160 rc = VINF_EM_RESCHEDULE_HWACC;
1161 break;
1162
1163#ifdef VBOX_WITH_VMI
1164 /*
1165 *
1166 */
1167 case EXCP_PARAV_CALL:
1168 Log2(("REMR3Run: cpu_exec -> EXCP_PARAV_CALL\n"));
1169 rc = VINF_EM_RESCHEDULE_PARAV;
1170 break;
1171#endif
1172
1173 /*
1174 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1175 */
1176 case EXCP_RC:
1177 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1178 rc = pVM->rem.s.rc;
1179 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1180 break;
1181
1182 /*
1183 * Figure out the rest when they arrive....
1184 */
1185 default:
1186 AssertMsgFailed(("rc=%d\n", rc));
1187 Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1188 rc = VINF_SUCCESS;
1189 break;
1190 }
1191
1192 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%RGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1193 return rc;
1194}
1195
1196
1197/**
1198 * Check if the cpu state is suitable for Raw execution.
1199 *
1200 * @returns boolean
1201 * @param env The CPU env struct.
1202 * @param eip The EIP to check this for (might differ from env->eip).
1203 * @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1204 * @param piException Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1205 *
1206 * @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1207 */
1208bool remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, int *piException)
1209{
1210 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1211 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1212 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1213
1214 /* Update counter. */
1215 env->pVM->rem.s.cCanExecuteRaw++;
1216
1217 if (HWACCMIsEnabled(env->pVM))
1218 {
1219 env->state |= CPU_RAW_HWACC;
1220
1221 /*
1222 * Create partial context for HWACCMR3CanExecuteGuest
1223 */
1224 CPUMCTX Ctx;
1225 Ctx.cr0 = env->cr[0];
1226 Ctx.cr3 = env->cr[3];
1227 Ctx.cr4 = env->cr[4];
1228
1229 Ctx.tr = env->tr.selector;
1230 Ctx.trHid.u64Base = env->tr.base;
1231 Ctx.trHid.u32Limit = env->tr.limit;
1232 Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1233
1234 Ctx.idtr.cbIdt = env->idt.limit;
1235 Ctx.idtr.pIdt = env->idt.base;
1236
1237 Ctx.eflags.u32 = env->eflags;
1238
1239 Ctx.cs = env->segs[R_CS].selector;
1240 Ctx.csHid.u64Base = env->segs[R_CS].base;
1241 Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1242 Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1243
1244 Ctx.ds = env->segs[R_DS].selector;
1245 Ctx.dsHid.u64Base = env->segs[R_DS].base;
1246 Ctx.dsHid.u32Limit = env->segs[R_DS].limit;
1247 Ctx.dsHid.Attr.u = (env->segs[R_DS].flags >> 8) & 0xF0FF;
1248
1249 Ctx.es = env->segs[R_ES].selector;
1250 Ctx.esHid.u64Base = env->segs[R_ES].base;
1251 Ctx.esHid.u32Limit = env->segs[R_ES].limit;
1252 Ctx.esHid.Attr.u = (env->segs[R_ES].flags >> 8) & 0xF0FF;
1253
1254 Ctx.fs = env->segs[R_FS].selector;
1255 Ctx.fsHid.u64Base = env->segs[R_FS].base;
1256 Ctx.fsHid.u32Limit = env->segs[R_FS].limit;
1257 Ctx.fsHid.Attr.u = (env->segs[R_FS].flags >> 8) & 0xF0FF;
1258
1259 Ctx.gs = env->segs[R_GS].selector;
1260 Ctx.gsHid.u64Base = env->segs[R_GS].base;
1261 Ctx.gsHid.u32Limit = env->segs[R_GS].limit;
1262 Ctx.gsHid.Attr.u = (env->segs[R_GS].flags >> 8) & 0xF0FF;
1263
1264 Ctx.ss = env->segs[R_SS].selector;
1265 Ctx.ssHid.u64Base = env->segs[R_SS].base;
1266 Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1267 Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1268
1269 Ctx.msrEFER = env->efer;
1270
1271 /* Hardware accelerated raw-mode:
1272 *
1273 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1274 */
1275 if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1276 {
1277 *piException = EXCP_EXECUTE_HWACC;
1278 return true;
1279 }
1280 return false;
1281 }
1282
1283 /*
1284 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1285 * or 32 bits protected mode ring 0 code
1286 *
1287 * The tests are ordered by the likelyhood of being true during normal execution.
1288 */
1289 if (fFlags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))
1290 {
1291 STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1292 Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1293 return false;
1294 }
1295
1296#ifndef VBOX_RAW_V86
1297 if (fFlags & VM_MASK) {
1298 STAM_COUNTER_INC(&gStatRefuseVM86);
1299 Log2(("raw mode refused: VM_MASK\n"));
1300 return false;
1301 }
1302#endif
1303
1304 if (env->state & CPU_EMULATE_SINGLE_INSTR)
1305 {
1306#ifndef DEBUG_bird
1307 Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1308#endif
1309 return false;
1310 }
1311
1312 if (env->singlestep_enabled)
1313 {
1314 //Log2(("raw mode refused: Single step\n"));
1315 return false;
1316 }
1317
1318 if (env->nb_breakpoints > 0)
1319 {
1320 //Log2(("raw mode refused: Breakpoints\n"));
1321 return false;
1322 }
1323
1324 uint32_t u32CR0 = env->cr[0];
1325 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1326 {
1327 STAM_COUNTER_INC(&gStatRefusePaging);
1328 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1329 return false;
1330 }
1331
1332 if (env->cr[4] & CR4_PAE_MASK)
1333 {
1334 if (!(env->cpuid_features & X86_CPUID_FEATURE_EDX_PAE))
1335 {
1336 STAM_COUNTER_INC(&gStatRefusePAE);
1337 return false;
1338 }
1339 }
1340
1341 if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1342 {
1343 if (!EMIsRawRing3Enabled(env->pVM))
1344 return false;
1345
1346 if (!(env->eflags & IF_MASK))
1347 {
1348 STAM_COUNTER_INC(&gStatRefuseIF0);
1349 Log2(("raw mode refused: IF (RawR3)\n"));
1350 return false;
1351 }
1352
1353 if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1354 {
1355 STAM_COUNTER_INC(&gStatRefuseWP0);
1356 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1357 return false;
1358 }
1359 }
1360 else
1361 {
1362 if (!EMIsRawRing0Enabled(env->pVM))
1363 return false;
1364
1365 // Let's start with pure 32 bits ring 0 code first
1366 if ((fFlags & (HF_SS32_MASK | HF_CS32_MASK)) != (HF_SS32_MASK | HF_CS32_MASK))
1367 {
1368 STAM_COUNTER_INC(&gStatRefuseCode16);
1369 Log2(("raw r0 mode refused: HF_[S|C]S32_MASK fFlags=%#x\n", fFlags));
1370 return false;
1371 }
1372
1373 // Only R0
1374 if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1375 {
1376 STAM_COUNTER_INC(&gStatRefuseRing1or2);
1377 Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1378 return false;
1379 }
1380
1381 if (!(u32CR0 & CR0_WP_MASK))
1382 {
1383 STAM_COUNTER_INC(&gStatRefuseWP0);
1384 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1385 return false;
1386 }
1387
1388 if (PATMIsPatchGCAddr(env->pVM, eip))
1389 {
1390 Log2(("raw r0 mode forced: patch code\n"));
1391 *piException = EXCP_EXECUTE_RAW;
1392 return true;
1393 }
1394
1395#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1396 if (!(env->eflags & IF_MASK))
1397 {
1398 STAM_COUNTER_INC(&gStatRefuseIF0);
1399 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1400 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1401 return false;
1402 }
1403#endif
1404
1405 env->state |= CPU_RAW_RING0;
1406 }
1407
1408 /*
1409 * Don't reschedule the first time we're called, because there might be
1410 * special reasons why we're here that is not covered by the above checks.
1411 */
1412 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1413 {
1414 Log2(("raw mode refused: first scheduling\n"));
1415 STAM_COUNTER_INC(&gStatRefuseCanExecute);
1416 return false;
1417 }
1418
1419 Assert(PGMPhysIsA20Enabled(env->pVM));
1420 *piException = EXCP_EXECUTE_RAW;
1421 return true;
1422}
1423
1424
1425/**
1426 * Fetches a code byte.
1427 *
1428 * @returns Success indicator (bool) for ease of use.
1429 * @param env The CPU environment structure.
1430 * @param GCPtrInstr Where to fetch code.
1431 * @param pu8Byte Where to store the byte on success
1432 */
1433bool remR3GetOpcode(CPUState *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte)
1434{
1435 int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1436 if (RT_SUCCESS(rc))
1437 return true;
1438 return false;
1439}
1440
1441
1442/**
1443 * Flush (or invalidate if you like) page table/dir entry.
1444 *
1445 * (invlpg instruction; tlb_flush_page)
1446 *
1447 * @param env Pointer to cpu environment.
1448 * @param GCPtr The virtual address which page table/dir entry should be invalidated.
1449 */
1450void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1451{
1452 PVM pVM = env->pVM;
1453
1454 /*
1455 * When we're replaying invlpg instructions or restoring a saved
1456 * state we disable this path.
1457 */
1458 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.fIgnoreAll)
1459 return;
1460 Log(("remR3FlushPage: GCPtr=%RGv\n", GCPtr));
1461 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1462
1463 //RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1464
1465 /*
1466 * Update the control registers before calling PGMFlushPage.
1467 */
1468 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1469 pCtx->cr0 = env->cr[0];
1470 pCtx->cr3 = env->cr[3];
1471 if ((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME)
1472 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1473 pCtx->cr4 = env->cr[4];
1474
1475 /*
1476 * Let PGM do the rest.
1477 */
1478 int rc = PGMInvalidatePage(pVM, GCPtr);
1479 if (RT_FAILURE(rc))
1480 {
1481 AssertMsgFailed(("remR3FlushPage %RGv failed with %d!!\n", GCPtr, rc));
1482 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1483 }
1484 //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1485}
1486
1487
1488/**
1489 * Called from tlb_protect_code in order to write monitor a code page.
1490 *
1491 * @param env Pointer to the CPU environment.
1492 * @param GCPtr Code page to monitor
1493 */
1494void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1495{
1496#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1497 Assert(env->pVM->rem.s.fInREM);
1498 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1499 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1500 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1501 && !(env->eflags & VM_MASK) /* no V86 mode */
1502 && !HWACCMIsEnabled(env->pVM))
1503 CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1504#endif
1505}
1506
1507
1508/**
1509 * Called from tlb_unprotect_code in order to clear write monitoring for a code page.
1510 *
1511 * @param env Pointer to the CPU environment.
1512 * @param GCPtr Code page to monitor
1513 */
1514void remR3UnprotectCode(CPUState *env, RTGCPTR GCPtr)
1515{
1516 Assert(env->pVM->rem.s.fInREM);
1517#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1518 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1519 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1520 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1521 && !(env->eflags & VM_MASK) /* no V86 mode */
1522 && !HWACCMIsEnabled(env->pVM))
1523 CSAMR3UnmonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1524#endif
1525}
1526
1527
1528/**
1529 * Called when the CPU is initialized, any of the CRx registers are changed or
1530 * when the A20 line is modified.
1531 *
1532 * @param env Pointer to the CPU environment.
1533 * @param fGlobal Set if the flush is global.
1534 */
1535void remR3FlushTLB(CPUState *env, bool fGlobal)
1536{
1537 PVM pVM = env->pVM;
1538
1539 /*
1540 * When we're replaying invlpg instructions or restoring a saved
1541 * state we disable this path.
1542 */
1543 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.fIgnoreAll)
1544 return;
1545 Assert(pVM->rem.s.fInREM);
1546
1547 /*
1548 * The caller doesn't check cr4, so we have to do that for ourselves.
1549 */
1550 if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1551 fGlobal = true;
1552 Log(("remR3FlushTLB: CR0=%RGr CR3=%RGr CR4=%RGr %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1553
1554 /*
1555 * Update the control registers before calling PGMR3FlushTLB.
1556 */
1557 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1558 pCtx->cr0 = env->cr[0];
1559 pCtx->cr3 = env->cr[3];
1560 if ((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME)
1561 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1562 pCtx->cr4 = env->cr[4];
1563
1564 /*
1565 * Let PGM do the rest.
1566 */
1567 PGMFlushTLB(pVM, env->cr[3], fGlobal);
1568}
1569
1570
1571/**
1572 * Called when any of the cr0, cr4 or efer registers is updated.
1573 *
1574 * @param env Pointer to the CPU environment.
1575 */
1576void remR3ChangeCpuMode(CPUState *env)
1577{
1578 int rc;
1579 PVM pVM = env->pVM;
1580
1581 /*
1582 * When we're replaying loads or restoring a saved
1583 * state this path is disabled.
1584 */
1585 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.fIgnoreAll)
1586 return;
1587 Assert(pVM->rem.s.fInREM);
1588
1589 /*
1590 * Update the control registers before calling PGMChangeMode()
1591 * as it may need to map whatever cr3 is pointing to.
1592 */
1593 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1594 pCtx->cr0 = env->cr[0];
1595 pCtx->cr3 = env->cr[3];
1596 if ((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME)
1597 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1598 pCtx->cr4 = env->cr[4];
1599
1600#ifdef TARGET_X86_64
1601 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1602 if (rc != VINF_SUCCESS)
1603 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], env->efer, rc);
1604#else
1605 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1606 if (rc != VINF_SUCCESS)
1607 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], 0LL, rc);
1608#endif
1609}
1610
1611
1612/**
1613 * Called from compiled code to run dma.
1614 *
1615 * @param env Pointer to the CPU environment.
1616 */
1617void remR3DmaRun(CPUState *env)
1618{
1619 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1620 PDMR3DmaRun(env->pVM);
1621 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1622}
1623
1624
1625/**
1626 * Called from compiled code to schedule pending timers in VMM
1627 *
1628 * @param env Pointer to the CPU environment.
1629 */
1630void remR3TimersRun(CPUState *env)
1631{
1632 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1633 remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1634 TMR3TimerQueuesDo(env->pVM);
1635 remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1636 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1637}
1638
1639
1640/**
1641 * Record trap occurance
1642 *
1643 * @returns VBox status code
1644 * @param env Pointer to the CPU environment.
1645 * @param uTrap Trap nr
1646 * @param uErrorCode Error code
1647 * @param pvNextEIP Next EIP
1648 */
1649int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1650{
1651 PVM pVM = env->pVM;
1652#ifdef VBOX_WITH_STATISTICS
1653 static STAMCOUNTER s_aStatTrap[255];
1654 static bool s_aRegisters[RT_ELEMENTS(s_aStatTrap)];
1655#endif
1656
1657#ifdef VBOX_WITH_STATISTICS
1658 if (uTrap < 255)
1659 {
1660 if (!s_aRegisters[uTrap])
1661 {
1662 s_aRegisters[uTrap] = true;
1663 char szStatName[64];
1664 RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1665 STAM_REG(env->pVM, &s_aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1666 }
1667 STAM_COUNTER_INC(&s_aStatTrap[uTrap]);
1668 }
1669#endif
1670 Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, (RTGCPTR)pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
1671 if( uTrap < 0x20
1672 && (env->cr[0] & X86_CR0_PE)
1673 && !(env->eflags & X86_EFL_VM))
1674 {
1675#ifdef DEBUG
1676 remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1677#endif
1678 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
1679 {
1680 LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, (RTGCPTR)pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
1681 remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1682 return VERR_REM_TOO_MANY_TRAPS;
1683 }
1684 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1685 pVM->rem.s.cPendingExceptions = 1;
1686 pVM->rem.s.uPendingException = uTrap;
1687 pVM->rem.s.uPendingExcptEIP = env->eip;
1688 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1689 }
1690 else
1691 {
1692 pVM->rem.s.cPendingExceptions = 0;
1693 pVM->rem.s.uPendingException = uTrap;
1694 pVM->rem.s.uPendingExcptEIP = env->eip;
1695 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1696 }
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/*
1702 * Clear current active trap
1703 *
1704 * @param pVM VM Handle.
1705 */
1706void remR3TrapClear(PVM pVM)
1707{
1708 pVM->rem.s.cPendingExceptions = 0;
1709 pVM->rem.s.uPendingException = 0;
1710 pVM->rem.s.uPendingExcptEIP = 0;
1711 pVM->rem.s.uPendingExcptCR2 = 0;
1712}
1713
1714
1715/*
1716 * Record previous call instruction addresses
1717 *
1718 * @param env Pointer to the CPU environment.
1719 */
1720void remR3RecordCall(CPUState *env)
1721{
1722 CSAMR3RecordCallAddress(env->pVM, env->eip);
1723}
1724
1725
1726/**
1727 * Syncs the internal REM state with the VM.
1728 *
1729 * This must be called before REMR3Run() is invoked whenever when the REM
1730 * state is not up to date. Calling it several times in a row is not
1731 * permitted.
1732 *
1733 * @returns VBox status code.
1734 *
1735 * @param pVM VM Handle.
1736 *
1737 * @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1738 * no do this since the majority of the callers don't want any unnecessary of events
1739 * pending that would immediatly interrupt execution.
1740 */
1741REMR3DECL(int) REMR3State(PVM pVM)
1742{
1743 Log2(("REMR3State:\n"));
1744 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1745 register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1746 register unsigned fFlags;
1747 bool fHiddenSelRegsValid = CPUMAreHiddenSelRegsValid(pVM);
1748 unsigned i;
1749
1750 Assert(!pVM->rem.s.fInREM);
1751 pVM->rem.s.fInStateSync = true;
1752
1753 /*
1754 * If we have to flush TBs, do that immediately.
1755 */
1756 if (pVM->rem.s.fFlushTBs)
1757 {
1758 STAM_COUNTER_INC(&gStatFlushTBs);
1759 tb_flush(&pVM->rem.s.Env);
1760 pVM->rem.s.fFlushTBs = false;
1761 }
1762
1763 /*
1764 * Copy the registers which require no special handling.
1765 */
1766#ifdef TARGET_X86_64
1767 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
1768 Assert(R_EAX == 0);
1769 pVM->rem.s.Env.regs[R_EAX] = pCtx->rax;
1770 Assert(R_ECX == 1);
1771 pVM->rem.s.Env.regs[R_ECX] = pCtx->rcx;
1772 Assert(R_EDX == 2);
1773 pVM->rem.s.Env.regs[R_EDX] = pCtx->rdx;
1774 Assert(R_EBX == 3);
1775 pVM->rem.s.Env.regs[R_EBX] = pCtx->rbx;
1776 Assert(R_ESP == 4);
1777 pVM->rem.s.Env.regs[R_ESP] = pCtx->rsp;
1778 Assert(R_EBP == 5);
1779 pVM->rem.s.Env.regs[R_EBP] = pCtx->rbp;
1780 Assert(R_ESI == 6);
1781 pVM->rem.s.Env.regs[R_ESI] = pCtx->rsi;
1782 Assert(R_EDI == 7);
1783 pVM->rem.s.Env.regs[R_EDI] = pCtx->rdi;
1784 pVM->rem.s.Env.regs[8] = pCtx->r8;
1785 pVM->rem.s.Env.regs[9] = pCtx->r9;
1786 pVM->rem.s.Env.regs[10] = pCtx->r10;
1787 pVM->rem.s.Env.regs[11] = pCtx->r11;
1788 pVM->rem.s.Env.regs[12] = pCtx->r12;
1789 pVM->rem.s.Env.regs[13] = pCtx->r13;
1790 pVM->rem.s.Env.regs[14] = pCtx->r14;
1791 pVM->rem.s.Env.regs[15] = pCtx->r15;
1792
1793 pVM->rem.s.Env.eip = pCtx->rip;
1794
1795 pVM->rem.s.Env.eflags = pCtx->rflags.u64;
1796#else
1797 Assert(R_EAX == 0);
1798 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1799 Assert(R_ECX == 1);
1800 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1801 Assert(R_EDX == 2);
1802 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1803 Assert(R_EBX == 3);
1804 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1805 Assert(R_ESP == 4);
1806 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1807 Assert(R_EBP == 5);
1808 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1809 Assert(R_ESI == 6);
1810 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1811 Assert(R_EDI == 7);
1812 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1813 pVM->rem.s.Env.eip = pCtx->eip;
1814
1815 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1816#endif
1817
1818 pVM->rem.s.Env.cr[2] = pCtx->cr2;
1819
1820 /** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1821 for (i=0;i<8;i++)
1822 pVM->rem.s.Env.dr[i] = pCtx->dr[i];
1823
1824 /*
1825 * Clear the halted hidden flag (the interrupt waking up the CPU can
1826 * have been dispatched in raw mode).
1827 */
1828 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
1829
1830 /*
1831 * Replay invlpg?
1832 */
1833 if (pVM->rem.s.cInvalidatedPages)
1834 {
1835 pVM->rem.s.fIgnoreInvlPg = true;
1836 RTUINT i;
1837 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1838 {
1839 Log2(("REMR3State: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1840 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1841 }
1842 pVM->rem.s.fIgnoreInvlPg = false;
1843 pVM->rem.s.cInvalidatedPages = 0;
1844 }
1845
1846 /* Replay notification changes? */
1847 if (pVM->rem.s.cHandlerNotifications)
1848 REMR3ReplayHandlerNotifications(pVM);
1849
1850 /* Update MSRs; before CRx registers! */
1851 pVM->rem.s.Env.efer = pCtx->msrEFER;
1852 pVM->rem.s.Env.star = pCtx->msrSTAR;
1853 pVM->rem.s.Env.pat = pCtx->msrPAT;
1854#ifdef TARGET_X86_64
1855 pVM->rem.s.Env.lstar = pCtx->msrLSTAR;
1856 pVM->rem.s.Env.cstar = pCtx->msrCSTAR;
1857 pVM->rem.s.Env.fmask = pCtx->msrSFMASK;
1858 pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
1859
1860 /* Update the internal long mode activate flag according to the new EFER value. */
1861 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1862 pVM->rem.s.Env.hflags |= HF_LMA_MASK;
1863 else
1864 pVM->rem.s.Env.hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
1865#endif
1866
1867 /*
1868 * Registers which are rarely changed and require special handling / order when changed.
1869 */
1870 fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1871 LogFlow(("CPUMGetAndClearChangedFlagsREM %x\n", fFlags));
1872 if (fFlags & ( CPUM_CHANGED_CR4 | CPUM_CHANGED_CR3 | CPUM_CHANGED_CR0
1873 | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_LDTR
1874 | CPUM_CHANGED_FPU_REM | CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_CPUID))
1875 {
1876 if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1877 {
1878 pVM->rem.s.fIgnoreCR3Load = true;
1879 tlb_flush(&pVM->rem.s.Env, true);
1880 pVM->rem.s.fIgnoreCR3Load = false;
1881 }
1882
1883 /* CR4 before CR0! */
1884 if (fFlags & CPUM_CHANGED_CR4)
1885 {
1886 pVM->rem.s.fIgnoreCR3Load = true;
1887 pVM->rem.s.fIgnoreCpuMode = true;
1888 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1889 pVM->rem.s.fIgnoreCpuMode = false;
1890 pVM->rem.s.fIgnoreCR3Load = false;
1891 }
1892
1893 if (fFlags & CPUM_CHANGED_CR0)
1894 {
1895 pVM->rem.s.fIgnoreCR3Load = true;
1896 pVM->rem.s.fIgnoreCpuMode = true;
1897 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1898 pVM->rem.s.fIgnoreCpuMode = false;
1899 pVM->rem.s.fIgnoreCR3Load = false;
1900 }
1901
1902 if (fFlags & CPUM_CHANGED_CR3)
1903 {
1904 pVM->rem.s.fIgnoreCR3Load = true;
1905 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1906 pVM->rem.s.fIgnoreCR3Load = false;
1907 }
1908
1909 if (fFlags & CPUM_CHANGED_GDTR)
1910 {
1911 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1912 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1913 }
1914
1915 if (fFlags & CPUM_CHANGED_IDTR)
1916 {
1917 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1918 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1919 }
1920
1921 if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1922 {
1923 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1924 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1925 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1926 }
1927
1928 if (fFlags & CPUM_CHANGED_LDTR)
1929 {
1930 if (fHiddenSelRegsValid)
1931 {
1932 pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1933 pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u64Base;
1934 pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1935 pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;
1936 }
1937 else
1938 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1939 }
1940
1941 if (fFlags & CPUM_CHANGED_CPUID)
1942 {
1943 uint32_t u32Dummy;
1944
1945 /*
1946 * Get the CPUID features.
1947 */
1948 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
1949 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
1950 }
1951
1952 /* Sync FPU state after CR4, CPUID and EFER (!). */
1953 if (fFlags & CPUM_CHANGED_FPU_REM)
1954 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu); /* 'save' is an excellent name. */
1955 }
1956
1957 /*
1958 * Sync TR unconditionally to make life simpler.
1959 */
1960 pVM->rem.s.Env.tr.selector = pCtx->tr;
1961 pVM->rem.s.Env.tr.base = pCtx->trHid.u64Base;
1962 pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1963 pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;
1964 /* Note! do_interrupt will fault if the busy flag is still set... */
1965 pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1966
1967 /*
1968 * Update selector registers.
1969 * This must be done *after* we've synced gdt, ldt and crX registers
1970 * since we're reading the GDT/LDT om sync_seg. This will happen with
1971 * saved state which takes a quick dip into rawmode for instance.
1972 */
1973 /*
1974 * Stack; Note first check this one as the CPL might have changed. The
1975 * wrong CPL can cause QEmu to raise an exception in sync_seg!!
1976 */
1977
1978 if (fHiddenSelRegsValid)
1979 {
1980 /* The hidden selector registers are valid in the CPU context. */
1981 /** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1982
1983 /* Set current CPL */
1984 cpu_x86_set_cpl(&pVM->rem.s.Env, CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)));
1985
1986 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1987 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1988 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1989 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1990 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1991 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1992 }
1993 else
1994 {
1995 /* In 'normal' raw mode we don't have access to the hidden selector registers. */
1996 if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1997 {
1998 Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1999
2000 cpu_x86_set_cpl(&pVM->rem.s.Env, CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)));
2001 sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
2002#ifdef VBOX_WITH_STATISTICS
2003 if (pVM->rem.s.Env.segs[R_SS].newselector)
2004 {
2005 STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
2006 }
2007#endif
2008 }
2009 else
2010 pVM->rem.s.Env.segs[R_SS].newselector = 0;
2011
2012 if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
2013 {
2014 Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
2015 sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
2016#ifdef VBOX_WITH_STATISTICS
2017 if (pVM->rem.s.Env.segs[R_ES].newselector)
2018 {
2019 STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
2020 }
2021#endif
2022 }
2023 else
2024 pVM->rem.s.Env.segs[R_ES].newselector = 0;
2025
2026 if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
2027 {
2028 Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
2029 sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
2030#ifdef VBOX_WITH_STATISTICS
2031 if (pVM->rem.s.Env.segs[R_CS].newselector)
2032 {
2033 STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
2034 }
2035#endif
2036 }
2037 else
2038 pVM->rem.s.Env.segs[R_CS].newselector = 0;
2039
2040 if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
2041 {
2042 Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
2043 sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
2044#ifdef VBOX_WITH_STATISTICS
2045 if (pVM->rem.s.Env.segs[R_DS].newselector)
2046 {
2047 STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
2048 }
2049#endif
2050 }
2051 else
2052 pVM->rem.s.Env.segs[R_DS].newselector = 0;
2053
2054 /** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
2055 * be the same but not the base/limit. */
2056 if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
2057 {
2058 Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
2059 sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
2060#ifdef VBOX_WITH_STATISTICS
2061 if (pVM->rem.s.Env.segs[R_FS].newselector)
2062 {
2063 STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
2064 }
2065#endif
2066 }
2067 else
2068 pVM->rem.s.Env.segs[R_FS].newselector = 0;
2069
2070 if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
2071 {
2072 Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
2073 sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
2074#ifdef VBOX_WITH_STATISTICS
2075 if (pVM->rem.s.Env.segs[R_GS].newselector)
2076 {
2077 STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
2078 }
2079#endif
2080 }
2081 else
2082 pVM->rem.s.Env.segs[R_GS].newselector = 0;
2083 }
2084
2085 /*
2086 * Check for traps.
2087 */
2088 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
2089 TRPMEVENT enmType;
2090 uint8_t u8TrapNo;
2091 int rc = TRPMQueryTrap(pVM, &u8TrapNo, &enmType);
2092 if (RT_SUCCESS(rc))
2093 {
2094#ifdef DEBUG
2095 if (u8TrapNo == 0x80)
2096 {
2097 remR3DumpLnxSyscall(pVM);
2098 remR3DumpOBsdSyscall(pVM);
2099 }
2100#endif
2101
2102 pVM->rem.s.Env.exception_index = u8TrapNo;
2103 if (enmType != TRPM_SOFTWARE_INT)
2104 {
2105 pVM->rem.s.Env.exception_is_int = 0;
2106 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
2107 }
2108 else
2109 {
2110 /*
2111 * The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
2112 * We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
2113 * for int03 and into.
2114 */
2115 pVM->rem.s.Env.exception_is_int = 1;
2116 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 2;
2117 /* int 3 may be generated by one-byte 0xcc */
2118 if (u8TrapNo == 3)
2119 {
2120 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xcc)
2121 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2122 }
2123 /* int 4 may be generated by one-byte 0xce */
2124 else if (u8TrapNo == 4)
2125 {
2126 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xce)
2127 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2128 }
2129 }
2130
2131 /* get error code and cr2 if needed. */
2132 switch (u8TrapNo)
2133 {
2134 case 0x0e:
2135 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
2136 /* fallthru */
2137 case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2138 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
2139 break;
2140
2141 case 0x11: case 0x08:
2142 default:
2143 pVM->rem.s.Env.error_code = 0;
2144 break;
2145 }
2146
2147 /*
2148 * We can now reset the active trap since the recompiler is gonna have a go at it.
2149 */
2150 rc = TRPMResetTrap(pVM);
2151 AssertRC(rc);
2152 Log2(("REMR3State: trap=%02x errcd=%RGv cr2=%RGv nexteip=%RGv%s\n", pVM->rem.s.Env.exception_index, (RTGCPTR)pVM->rem.s.Env.error_code,
2153 (RTGCPTR)pVM->rem.s.Env.cr[2], (RTGCPTR)pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
2154 }
2155
2156 /*
2157 * Clear old interrupt request flags; Check for pending hardware interrupts.
2158 * (See @remark for why we don't check for other FFs.)
2159 */
2160 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
2161 if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
2162 || VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
2163 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
2164
2165 /*
2166 * We're now in REM mode.
2167 */
2168 pVM->rem.s.fInREM = true;
2169 pVM->rem.s.fInStateSync = false;
2170 pVM->rem.s.cCanExecuteRaw = 0;
2171 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
2172 Log2(("REMR3State: returns VINF_SUCCESS\n"));
2173 return VINF_SUCCESS;
2174}
2175
2176
2177/**
2178 * Syncs back changes in the REM state to the the VM state.
2179 *
2180 * This must be called after invoking REMR3Run().
2181 * Calling it several times in a row is not permitted.
2182 *
2183 * @returns VBox status code.
2184 *
2185 * @param pVM VM Handle.
2186 */
2187REMR3DECL(int) REMR3StateBack(PVM pVM)
2188{
2189 Log2(("REMR3StateBack:\n"));
2190 Assert(pVM->rem.s.fInREM);
2191 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2192 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2193 unsigned i;
2194
2195 /*
2196 * Copy back the registers.
2197 * This is done in the order they are declared in the CPUMCTX structure.
2198 */
2199
2200 /** @todo FOP */
2201 /** @todo FPUIP */
2202 /** @todo CS */
2203 /** @todo FPUDP */
2204 /** @todo DS */
2205 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2206 pCtx->fpu.MXCSR = 0;
2207 pCtx->fpu.MXCSR_MASK = 0;
2208
2209 /** @todo check if FPU/XMM was actually used in the recompiler */
2210 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2211//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2212
2213#ifdef TARGET_X86_64
2214 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2215 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2216 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2217 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2218 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2219 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2220 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2221 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2222 pCtx->r8 = pVM->rem.s.Env.regs[8];
2223 pCtx->r9 = pVM->rem.s.Env.regs[9];
2224 pCtx->r10 = pVM->rem.s.Env.regs[10];
2225 pCtx->r11 = pVM->rem.s.Env.regs[11];
2226 pCtx->r12 = pVM->rem.s.Env.regs[12];
2227 pCtx->r13 = pVM->rem.s.Env.regs[13];
2228 pCtx->r14 = pVM->rem.s.Env.regs[14];
2229 pCtx->r15 = pVM->rem.s.Env.regs[15];
2230
2231 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2232
2233#else
2234 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2235 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2236 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2237 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2238 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2239 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2240 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2241
2242 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2243#endif
2244
2245 pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2246
2247#ifdef VBOX_WITH_STATISTICS
2248 if (pVM->rem.s.Env.segs[R_SS].newselector)
2249 {
2250 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
2251 }
2252 if (pVM->rem.s.Env.segs[R_GS].newselector)
2253 {
2254 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
2255 }
2256 if (pVM->rem.s.Env.segs[R_FS].newselector)
2257 {
2258 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
2259 }
2260 if (pVM->rem.s.Env.segs[R_ES].newselector)
2261 {
2262 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
2263 }
2264 if (pVM->rem.s.Env.segs[R_DS].newselector)
2265 {
2266 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2267 }
2268 if (pVM->rem.s.Env.segs[R_CS].newselector)
2269 {
2270 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2271 }
2272#endif
2273 pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2274 pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2275 pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2276 pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2277 pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2278
2279#ifdef TARGET_X86_64
2280 pCtx->rip = pVM->rem.s.Env.eip;
2281 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2282#else
2283 pCtx->eip = pVM->rem.s.Env.eip;
2284 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2285#endif
2286
2287 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2288 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2289 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2290 if ((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME)
2291 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2292 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2293
2294 for (i=0;i<8;i++)
2295 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2296
2297 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2298 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base)
2299 {
2300 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base;
2301 STAM_COUNTER_INC(&gStatREMGDTChange);
2302 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2303 }
2304
2305 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2306 if (pCtx->idtr.pIdt != pVM->rem.s.Env.idt.base)
2307 {
2308 pCtx->idtr.pIdt = pVM->rem.s.Env.idt.base;
2309 STAM_COUNTER_INC(&gStatREMIDTChange);
2310 VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2311 }
2312
2313 if ( pCtx->ldtr != pVM->rem.s.Env.ldt.selector
2314 || pCtx->ldtrHid.u64Base != pVM->rem.s.Env.ldt.base
2315 || pCtx->ldtrHid.u32Limit != pVM->rem.s.Env.ldt.limit
2316 || pCtx->ldtrHid.Attr.u != ((pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF))
2317 {
2318 pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2319 pCtx->ldtrHid.u64Base = pVM->rem.s.Env.ldt.base;
2320 pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2321 pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2322 STAM_COUNTER_INC(&gStatREMLDTRChange);
2323 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2324 }
2325
2326 if ( pCtx->tr != pVM->rem.s.Env.tr.selector
2327 || pCtx->trHid.u64Base != pVM->rem.s.Env.tr.base
2328 || pCtx->trHid.u32Limit != pVM->rem.s.Env.tr.limit
2329 /* Qemu and AMD/Intel have different ideas about the busy flag ... */
2330 || pCtx->trHid.Attr.u != ( (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF
2331 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> 8
2332 : 0) )
2333 {
2334 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2335 pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2336 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2337 (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> 8 : 0));
2338 pCtx->tr = pVM->rem.s.Env.tr.selector;
2339 pCtx->trHid.u64Base = pVM->rem.s.Env.tr.base;
2340 pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2341 pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2342 if (pCtx->trHid.Attr.u)
2343 pCtx->trHid.Attr.u |= DESC_TSS_BUSY_MASK >> 8;
2344 STAM_COUNTER_INC(&gStatREMTRChange);
2345 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2346 }
2347
2348 /** @todo These values could still be out of sync! */
2349 pCtx->csHid.u64Base = pVM->rem.s.Env.segs[R_CS].base;
2350 pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2351 /* Note! QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2352 pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2353
2354 pCtx->dsHid.u64Base = pVM->rem.s.Env.segs[R_DS].base;
2355 pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2356 pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2357
2358 pCtx->esHid.u64Base = pVM->rem.s.Env.segs[R_ES].base;
2359 pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2360 pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2361
2362 pCtx->fsHid.u64Base = pVM->rem.s.Env.segs[R_FS].base;
2363 pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2364 pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2365
2366 pCtx->gsHid.u64Base = pVM->rem.s.Env.segs[R_GS].base;
2367 pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2368 pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2369
2370 pCtx->ssHid.u64Base = pVM->rem.s.Env.segs[R_SS].base;
2371 pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2372 pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2373
2374 /* Sysenter MSR */
2375 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2376 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2377 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2378
2379 /* System MSRs. */
2380 pCtx->msrEFER = pVM->rem.s.Env.efer;
2381 pCtx->msrSTAR = pVM->rem.s.Env.star;
2382 pCtx->msrPAT = pVM->rem.s.Env.pat;
2383#ifdef TARGET_X86_64
2384 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2385 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2386 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2387 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2388#endif
2389
2390 remR3TrapClear(pVM);
2391
2392 /*
2393 * Check for traps.
2394 */
2395 if ( pVM->rem.s.Env.exception_index >= 0
2396 && pVM->rem.s.Env.exception_index < 256)
2397 {
2398 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2399 int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, (pVM->rem.s.Env.exception_is_int) ? TRPM_SOFTWARE_INT : TRPM_HARDWARE_INT);
2400 AssertRC(rc);
2401 switch (pVM->rem.s.Env.exception_index)
2402 {
2403 case 0x0e:
2404 TRPMSetFaultAddress(pVM, pCtx->cr2);
2405 /* fallthru */
2406 case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2407 case 0x11: case 0x08: /* 0 */
2408 TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2409 break;
2410 }
2411
2412 }
2413
2414 /*
2415 * We're not longer in REM mode.
2416 */
2417 pVM->rem.s.fInREM = false;
2418 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2419 Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2420 return VINF_SUCCESS;
2421}
2422
2423
2424/**
2425 * This is called by the disassembler when it wants to update the cpu state
2426 * before for instance doing a register dump.
2427 */
2428static void remR3StateUpdate(PVM pVM)
2429{
2430 Assert(pVM->rem.s.fInREM);
2431 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2432 unsigned i;
2433
2434 /*
2435 * Copy back the registers.
2436 * This is done in the order they are declared in the CPUMCTX structure.
2437 */
2438
2439 /** @todo FOP */
2440 /** @todo FPUIP */
2441 /** @todo CS */
2442 /** @todo FPUDP */
2443 /** @todo DS */
2444 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2445 pCtx->fpu.MXCSR = 0;
2446 pCtx->fpu.MXCSR_MASK = 0;
2447
2448 /** @todo check if FPU/XMM was actually used in the recompiler */
2449 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2450//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2451
2452#ifdef TARGET_X86_64
2453 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2454 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2455 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2456 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2457 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2458 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2459 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2460 pCtx->r8 = pVM->rem.s.Env.regs[8];
2461 pCtx->r9 = pVM->rem.s.Env.regs[9];
2462 pCtx->r10 = pVM->rem.s.Env.regs[10];
2463 pCtx->r11 = pVM->rem.s.Env.regs[11];
2464 pCtx->r12 = pVM->rem.s.Env.regs[12];
2465 pCtx->r13 = pVM->rem.s.Env.regs[13];
2466 pCtx->r14 = pVM->rem.s.Env.regs[14];
2467 pCtx->r15 = pVM->rem.s.Env.regs[15];
2468
2469 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2470#else
2471 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2472 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2473 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2474 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2475 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2476 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2477 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2478
2479 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2480#endif
2481
2482 pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2483
2484 pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2485 pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2486 pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2487 pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2488 pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2489
2490#ifdef TARGET_X86_64
2491 pCtx->rip = pVM->rem.s.Env.eip;
2492 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2493#else
2494 pCtx->eip = pVM->rem.s.Env.eip;
2495 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2496#endif
2497
2498 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2499 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2500 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2501 if ((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME)
2502 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2503 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2504
2505 for (i=0;i<8;i++)
2506 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2507
2508 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2509 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base)
2510 {
2511 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
2512 STAM_COUNTER_INC(&gStatREMGDTChange);
2513 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2514 }
2515
2516 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2517 if (pCtx->idtr.pIdt != (RTGCPTR)pVM->rem.s.Env.idt.base)
2518 {
2519 pCtx->idtr.pIdt = (RTGCPTR)pVM->rem.s.Env.idt.base;
2520 STAM_COUNTER_INC(&gStatREMIDTChange);
2521 VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2522 }
2523
2524 if ( pCtx->ldtr != pVM->rem.s.Env.ldt.selector
2525 || pCtx->ldtrHid.u64Base != pVM->rem.s.Env.ldt.base
2526 || pCtx->ldtrHid.u32Limit != pVM->rem.s.Env.ldt.limit
2527 || pCtx->ldtrHid.Attr.u != ((pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF))
2528 {
2529 pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2530 pCtx->ldtrHid.u64Base = pVM->rem.s.Env.ldt.base;
2531 pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2532 pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2533 STAM_COUNTER_INC(&gStatREMLDTRChange);
2534 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2535 }
2536
2537 if ( pCtx->tr != pVM->rem.s.Env.tr.selector
2538 || pCtx->trHid.u64Base != pVM->rem.s.Env.tr.base
2539 || pCtx->trHid.u32Limit != pVM->rem.s.Env.tr.limit
2540 /* Qemu and AMD/Intel have different ideas about the busy flag ... */
2541 || pCtx->trHid.Attr.u != ( (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF
2542 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> 8
2543 : 0) )
2544 {
2545 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2546 pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2547 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2548 (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> 8 : 0));
2549 pCtx->tr = pVM->rem.s.Env.tr.selector;
2550 pCtx->trHid.u64Base = pVM->rem.s.Env.tr.base;
2551 pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2552 pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2553 if (pCtx->trHid.Attr.u)
2554 pCtx->trHid.Attr.u |= DESC_TSS_BUSY_MASK >> 8;
2555 STAM_COUNTER_INC(&gStatREMTRChange);
2556 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2557 }
2558
2559 /** @todo These values could still be out of sync! */
2560 pCtx->csHid.u64Base = pVM->rem.s.Env.segs[R_CS].base;
2561 pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2562 /** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2563 pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2564
2565 pCtx->dsHid.u64Base = pVM->rem.s.Env.segs[R_DS].base;
2566 pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2567 pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2568
2569 pCtx->esHid.u64Base = pVM->rem.s.Env.segs[R_ES].base;
2570 pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2571 pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2572
2573 pCtx->fsHid.u64Base = pVM->rem.s.Env.segs[R_FS].base;
2574 pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2575 pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2576
2577 pCtx->gsHid.u64Base = pVM->rem.s.Env.segs[R_GS].base;
2578 pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2579 pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2580
2581 pCtx->ssHid.u64Base = pVM->rem.s.Env.segs[R_SS].base;
2582 pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2583 pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2584
2585 /* Sysenter MSR */
2586 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2587 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2588 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2589
2590 /* System MSRs. */
2591 pCtx->msrEFER = pVM->rem.s.Env.efer;
2592 pCtx->msrSTAR = pVM->rem.s.Env.star;
2593 pCtx->msrPAT = pVM->rem.s.Env.pat;
2594#ifdef TARGET_X86_64
2595 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2596 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2597 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2598 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2599#endif
2600
2601}
2602
2603
2604/**
2605 * Update the VMM state information if we're currently in REM.
2606 *
2607 * This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2608 * we're currently executing in REM and the VMM state is invalid. This method will of
2609 * course check that we're executing in REM before syncing any data over to the VMM.
2610 *
2611 * @param pVM The VM handle.
2612 */
2613REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2614{
2615 if (pVM->rem.s.fInREM)
2616 remR3StateUpdate(pVM);
2617}
2618
2619
2620#undef LOG_GROUP
2621#define LOG_GROUP LOG_GROUP_REM
2622
2623
2624/**
2625 * Notify the recompiler about Address Gate 20 state change.
2626 *
2627 * This notification is required since A20 gate changes are
2628 * initialized from a device driver and the VM might just as
2629 * well be in REM mode as in RAW mode.
2630 *
2631 * @param pVM VM handle.
2632 * @param fEnable True if the gate should be enabled.
2633 * False if the gate should be disabled.
2634 */
2635REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2636{
2637 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2638 VM_ASSERT_EMT(pVM);
2639
2640 bool fSaved = pVM->rem.s.fIgnoreAll; /* just in case. */
2641 pVM->rem.s.fIgnoreAll = fSaved || !pVM->rem.s.fInREM;
2642
2643 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2644
2645 pVM->rem.s.fIgnoreAll = fSaved;
2646}
2647
2648
2649/**
2650 * Replays the invalidated recorded pages.
2651 * Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2652 *
2653 * @param pVM VM handle.
2654 */
2655REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2656{
2657 VM_ASSERT_EMT(pVM);
2658
2659 /*
2660 * Sync the required registers.
2661 */
2662 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2663 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2664 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2665 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2666
2667 /*
2668 * Replay the flushes.
2669 */
2670 pVM->rem.s.fIgnoreInvlPg = true;
2671 RTUINT i;
2672 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2673 {
2674 Log2(("REMR3ReplayInvalidatedPages: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2675 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2676 }
2677 pVM->rem.s.fIgnoreInvlPg = false;
2678 pVM->rem.s.cInvalidatedPages = 0;
2679}
2680
2681
2682/**
2683 * Replays the handler notification changes
2684 * Called in response to VM_FF_REM_HANDLER_NOTIFY from the RAW execution loop.
2685 *
2686 * @param pVM VM handle.
2687 */
2688REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2689{
2690 LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2691 VM_ASSERT_EMT(pVM);
2692
2693 /*
2694 * Replay the flushes.
2695 */
2696 RTUINT i;
2697 const RTUINT c = pVM->rem.s.cHandlerNotifications;
2698 pVM->rem.s.cHandlerNotifications = 0;
2699 for (i = 0; i < c; i++)
2700 {
2701 PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2702 switch (pRec->enmKind)
2703 {
2704 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2705 REMR3NotifyHandlerPhysicalRegister(pVM,
2706 pRec->u.PhysicalRegister.enmType,
2707 pRec->u.PhysicalRegister.GCPhys,
2708 pRec->u.PhysicalRegister.cb,
2709 pRec->u.PhysicalRegister.fHasHCHandler);
2710 break;
2711
2712 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2713 REMR3NotifyHandlerPhysicalDeregister(pVM,
2714 pRec->u.PhysicalDeregister.enmType,
2715 pRec->u.PhysicalDeregister.GCPhys,
2716 pRec->u.PhysicalDeregister.cb,
2717 pRec->u.PhysicalDeregister.fHasHCHandler,
2718 pRec->u.PhysicalDeregister.fRestoreAsRAM);
2719 break;
2720
2721 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2722 REMR3NotifyHandlerPhysicalModify(pVM,
2723 pRec->u.PhysicalModify.enmType,
2724 pRec->u.PhysicalModify.GCPhysOld,
2725 pRec->u.PhysicalModify.GCPhysNew,
2726 pRec->u.PhysicalModify.cb,
2727 pRec->u.PhysicalModify.fHasHCHandler,
2728 pRec->u.PhysicalModify.fRestoreAsRAM);
2729 break;
2730
2731 default:
2732 AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2733 break;
2734 }
2735 }
2736 VM_FF_CLEAR(pVM, VM_FF_REM_HANDLER_NOTIFY);
2737}
2738
2739
2740/**
2741 * Notify REM about changed code page.
2742 *
2743 * @returns VBox status code.
2744 * @param pVM VM handle.
2745 * @param pvCodePage Code page address
2746 */
2747REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2748{
2749#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
2750 int rc;
2751 RTGCPHYS PhysGC;
2752 uint64_t flags;
2753
2754 VM_ASSERT_EMT(pVM);
2755
2756 /*
2757 * Get the physical page address.
2758 */
2759 rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2760 if (rc == VINF_SUCCESS)
2761 {
2762 /*
2763 * Sync the required registers and flush the whole page.
2764 * (Easier to do the whole page than notifying it about each physical
2765 * byte that was changed.
2766 */
2767 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2768 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2769 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2770 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2771
2772 tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2773 }
2774#endif
2775 return VINF_SUCCESS;
2776}
2777
2778
2779/**
2780 * Notification about a successful MMR3PhysRegister() call.
2781 *
2782 * @param pVM VM handle.
2783 * @param GCPhys The physical address the RAM.
2784 * @param cb Size of the memory.
2785 * @param fFlags Flags of the REM_NOTIFY_PHYS_RAM_FLAGS_* defines.
2786 */
2787REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, unsigned fFlags)
2788{
2789 Log(("REMR3NotifyPhysRamRegister: GCPhys=%RGp cb=%RGp fFlags=%#x\n", GCPhys, cb, fFlags));
2790 VM_ASSERT_EMT(pVM);
2791
2792 /*
2793 * Validate input - we trust the caller.
2794 */
2795 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2796 Assert(cb);
2797 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2798#ifdef VBOX_WITH_NEW_PHYS_CODE
2799 AssertMsg(fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_RAM || fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2, ("#x\n", fFlags));
2800#endif
2801
2802 /*
2803 * Base ram? Update GCPhysLastRam.
2804 */
2805#ifdef VBOX_WITH_NEW_PHYS_CODE
2806 if (fFlags & REM_NOTIFY_PHYS_RAM_FLAGS_RAM)
2807#else
2808 if (!GCPhys)
2809#endif
2810 {
2811 if (GCPhys + (cb - 1) > pVM->rem.s.GCPhysLastRam)
2812 {
2813 AssertReleaseMsg(!pVM->rem.s.fGCPhysLastRamFixed, ("GCPhys=%RGp cb=%RGp\n", GCPhys, cb));
2814 pVM->rem.s.GCPhysLastRam = GCPhys + (cb - 1);
2815 }
2816 }
2817
2818 /*
2819 * Register the ram.
2820 */
2821 Assert(!pVM->rem.s.fIgnoreAll);
2822 pVM->rem.s.fIgnoreAll = true;
2823
2824#ifdef VBOX_WITH_NEW_PHYS_CODE
2825 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2826#else
2827 if (!GCPhys)
2828 cpu_register_physical_memory(GCPhys, cb, GCPhys | IO_MEM_RAM_MISSING);
2829 else
2830 {
2831 if (fFlags & MM_RAM_FLAGS_RESERVED)
2832 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2833 else
2834 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2835 }
2836#endif
2837 Assert(pVM->rem.s.fIgnoreAll);
2838 pVM->rem.s.fIgnoreAll = false;
2839}
2840
2841#ifndef VBOX_WITH_NEW_PHYS_CODE
2842
2843/**
2844 * Notification about a successful PGMR3PhysRegisterChunk() call.
2845 *
2846 * @param pVM VM handle.
2847 * @param GCPhys The physical address the RAM.
2848 * @param cb Size of the memory.
2849 * @param pvRam The HC address of the RAM.
2850 * @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2851 */
2852REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2853{
2854 Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%RGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2855 VM_ASSERT_EMT(pVM);
2856
2857 /*
2858 * Validate input - we trust the caller.
2859 */
2860 Assert(pvRam);
2861 Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2862 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2863 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2864 Assert(fFlags == 0 /* normal RAM */);
2865 Assert(!pVM->rem.s.fIgnoreAll);
2866 pVM->rem.s.fIgnoreAll = true;
2867
2868 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2869
2870 Assert(pVM->rem.s.fIgnoreAll);
2871 pVM->rem.s.fIgnoreAll = false;
2872}
2873
2874
2875/**
2876 * Grows dynamically allocated guest RAM.
2877 * Will raise a fatal error if the operation fails.
2878 *
2879 * @param physaddr The physical address.
2880 */
2881void remR3GrowDynRange(unsigned long physaddr)
2882{
2883 int rc;
2884 PVM pVM = cpu_single_env->pVM;
2885
2886 LogFlow(("remR3GrowDynRange %RGp\n", (RTGCPHYS)physaddr));
2887 const RTGCPHYS GCPhys = physaddr;
2888 rc = PGM3PhysGrowRange(pVM, &GCPhys);
2889 if (RT_SUCCESS(rc))
2890 return;
2891
2892 LogRel(("\nUnable to allocate guest RAM chunk at %RGp\n", (RTGCPHYS)physaddr));
2893 cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %RGp\n", (RTGCPHYS)physaddr);
2894 AssertFatalFailed();
2895}
2896
2897#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2898
2899/**
2900 * Notification about a successful MMR3PhysRomRegister() call.
2901 *
2902 * @param pVM VM handle.
2903 * @param GCPhys The physical address of the ROM.
2904 * @param cb The size of the ROM.
2905 * @param pvCopy Pointer to the ROM copy.
2906 * @param fShadow Whether it's currently writable shadow ROM or normal readonly ROM.
2907 * This function will be called when ever the protection of the
2908 * shadow ROM changes (at reset and end of POST).
2909 */
2910REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)
2911{
2912 Log(("REMR3NotifyPhysRomRegister: GCPhys=%RGp cb=%d fShadow=%RTbool\n", GCPhys, cb, fShadow));
2913 VM_ASSERT_EMT(pVM);
2914
2915 /*
2916 * Validate input - we trust the caller.
2917 */
2918 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2919 Assert(cb);
2920 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2921
2922 /*
2923 * Register the rom.
2924 */
2925 Assert(!pVM->rem.s.fIgnoreAll);
2926 pVM->rem.s.fIgnoreAll = true;
2927
2928 cpu_register_physical_memory(GCPhys, cb, GCPhys | (fShadow ? 0 : IO_MEM_ROM));
2929
2930 Assert(pVM->rem.s.fIgnoreAll);
2931 pVM->rem.s.fIgnoreAll = false;
2932}
2933
2934
2935/**
2936 * Notification about a successful memory deregistration or reservation.
2937 *
2938 * @param pVM VM Handle.
2939 * @param GCPhys Start physical address.
2940 * @param cb The size of the range.
2941 */
2942REMR3DECL(void) REMR3NotifyPhysRamDeregister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2943{
2944 Log(("REMR3NotifyPhysRamDeregister: GCPhys=%RGp cb=%d\n", GCPhys, cb));
2945 VM_ASSERT_EMT(pVM);
2946
2947 /*
2948 * Validate input - we trust the caller.
2949 */
2950 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2951 Assert(cb);
2952 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2953
2954 /*
2955 * Unassigning the memory.
2956 */
2957 Assert(!pVM->rem.s.fIgnoreAll);
2958 pVM->rem.s.fIgnoreAll = true;
2959
2960 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2961
2962 Assert(pVM->rem.s.fIgnoreAll);
2963 pVM->rem.s.fIgnoreAll = false;
2964}
2965
2966
2967/**
2968 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
2969 *
2970 * @param pVM VM Handle.
2971 * @param enmType Handler type.
2972 * @param GCPhys Handler range address.
2973 * @param cb Size of the handler range.
2974 * @param fHasHCHandler Set if the handler has a HC callback function.
2975 *
2976 * @remark MMR3PhysRomRegister assumes that this function will not apply the
2977 * Handler memory type to memory which has no HC handler.
2978 */
2979REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2980{
2981 Log(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%d\n",
2982 enmType, GCPhys, cb, fHasHCHandler));
2983 VM_ASSERT_EMT(pVM);
2984 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2985 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2986
2987 if (pVM->rem.s.cHandlerNotifications)
2988 REMR3ReplayHandlerNotifications(pVM);
2989
2990 Assert(!pVM->rem.s.fIgnoreAll);
2991 pVM->rem.s.fIgnoreAll = true;
2992
2993 if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2994 cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2995 else if (fHasHCHandler)
2996 cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2997
2998 Assert(pVM->rem.s.fIgnoreAll);
2999 pVM->rem.s.fIgnoreAll = false;
3000}
3001
3002
3003/**
3004 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3005 *
3006 * @param pVM VM Handle.
3007 * @param enmType Handler type.
3008 * @param GCPhys Handler range address.
3009 * @param cb Size of the handler range.
3010 * @param fHasHCHandler Set if the handler has a HC callback function.
3011 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3012 */
3013REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3014{
3015 Log(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool RAM=%08x\n",
3016 enmType, GCPhys, cb, fHasHCHandler, fRestoreAsRAM, MMR3PhysGetRamSize(pVM)));
3017 VM_ASSERT_EMT(pVM);
3018
3019 if (pVM->rem.s.cHandlerNotifications)
3020 REMR3ReplayHandlerNotifications(pVM);
3021
3022 Assert(!pVM->rem.s.fIgnoreAll);
3023 pVM->rem.s.fIgnoreAll = true;
3024
3025/** @todo this isn't right, MMIO can (in theory) be restored as RAM. */
3026 if (enmType == PGMPHYSHANDLERTYPE_MMIO)
3027 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
3028 else if (fHasHCHandler)
3029 {
3030 if (!fRestoreAsRAM)
3031 {
3032 Assert(GCPhys > MMR3PhysGetRamSize(pVM));
3033 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
3034 }
3035 else
3036 {
3037 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3038 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3039 cpu_register_physical_memory(GCPhys, cb, GCPhys);
3040 }
3041 }
3042
3043 Assert(pVM->rem.s.fIgnoreAll);
3044 pVM->rem.s.fIgnoreAll = false;
3045}
3046
3047
3048/**
3049 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3050 *
3051 * @param pVM VM Handle.
3052 * @param enmType Handler type.
3053 * @param GCPhysOld Old handler range address.
3054 * @param GCPhysNew New handler range address.
3055 * @param cb Size of the handler range.
3056 * @param fHasHCHandler Set if the handler has a HC callback function.
3057 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3058 */
3059REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3060{
3061 Log(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%RGp GCPhysNew=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool\n",
3062 enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM));
3063 VM_ASSERT_EMT(pVM);
3064 AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
3065
3066 if (pVM->rem.s.cHandlerNotifications)
3067 REMR3ReplayHandlerNotifications(pVM);
3068
3069 if (fHasHCHandler)
3070 {
3071 Assert(!pVM->rem.s.fIgnoreAll);
3072 pVM->rem.s.fIgnoreAll = true;
3073
3074 /*
3075 * Reset the old page.
3076 */
3077 if (!fRestoreAsRAM)
3078 cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
3079 else
3080 {
3081 /* This is not perfect, but it'll do for PD monitoring... */
3082 Assert(cb == PAGE_SIZE);
3083 Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
3084 cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
3085 }
3086
3087 /*
3088 * Update the new page.
3089 */
3090 Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
3091 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3092 cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
3093
3094 Assert(pVM->rem.s.fIgnoreAll);
3095 pVM->rem.s.fIgnoreAll = false;
3096 }
3097}
3098
3099
3100/**
3101 * Checks if we're handling access to this page or not.
3102 *
3103 * @returns true if we're trapping access.
3104 * @returns false if we aren't.
3105 * @param pVM The VM handle.
3106 * @param GCPhys The physical address.
3107 *
3108 * @remark This function will only work correctly in VBOX_STRICT builds!
3109 */
3110REMR3DECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
3111{
3112#ifdef VBOX_STRICT
3113 if (pVM->rem.s.cHandlerNotifications)
3114 REMR3ReplayHandlerNotifications(pVM);
3115
3116 unsigned long off = get_phys_page_offset(GCPhys);
3117 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
3118 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
3119 || (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
3120#else
3121 return false;
3122#endif
3123}
3124
3125
3126/**
3127 * Deals with a rare case in get_phys_addr_code where the code
3128 * is being monitored.
3129 *
3130 * It could also be an MMIO page, in which case we will raise a fatal error.
3131 *
3132 * @returns The physical address corresponding to addr.
3133 * @param env The cpu environment.
3134 * @param addr The virtual address.
3135 * @param pTLBEntry The TLB entry.
3136 */
3137target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry)
3138{
3139 PVM pVM = env->pVM;
3140 if ((pTLBEntry->addr_code & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
3141 {
3142 target_ulong ret = pTLBEntry->addend + addr;
3143 AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%RGv addr_code=%RGv addend=%RGp ret=%RGp\n",
3144 (RTGCPTR)addr, (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPHYS)ret);
3145 return ret;
3146 }
3147 LogRel(("\nTrying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
3148 "*** handlers\n",
3149 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
3150 DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
3151 LogRel(("*** mmio\n"));
3152 DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
3153 LogRel(("*** phys\n"));
3154 DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
3155 cpu_abort(env, "Trying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
3156 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
3157 AssertFatalFailed();
3158}
3159
3160
3161/** Validate the physical address passed to the read functions.
3162 * Useful for finding non-guest-ram reads/writes. */
3163#if 0 //1 /* disable if it becomes bothersome... */
3164# define VBOX_CHECK_ADDR(GCPhys) AssertMsg(PGMPhysIsGCPhysValid(cpu_single_env->pVM, (GCPhys)), ("%RGp\n", (GCPhys)))
3165#else
3166# define VBOX_CHECK_ADDR(GCPhys) do { } while (0)
3167#endif
3168
3169/**
3170 * Read guest RAM and ROM.
3171 *
3172 * @param SrcGCPhys The source address (guest physical).
3173 * @param pvDst The destination address.
3174 * @param cb Number of bytes
3175 */
3176void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb)
3177{
3178 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3179 VBOX_CHECK_ADDR(SrcGCPhys);
3180 PGMPhysRead(cpu_single_env->pVM, SrcGCPhys, pvDst, cb);
3181 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3182}
3183
3184
3185/**
3186 * Read guest RAM and ROM, unsigned 8-bit.
3187 *
3188 * @param SrcGCPhys The source address (guest physical).
3189 */
3190uint8_t remR3PhysReadU8(RTGCPHYS SrcGCPhys)
3191{
3192 uint8_t val;
3193 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3194 VBOX_CHECK_ADDR(SrcGCPhys);
3195 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys);
3196 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3197 return val;
3198}
3199
3200
3201/**
3202 * Read guest RAM and ROM, signed 8-bit.
3203 *
3204 * @param SrcGCPhys The source address (guest physical).
3205 */
3206int8_t remR3PhysReadS8(RTGCPHYS SrcGCPhys)
3207{
3208 int8_t val;
3209 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3210 VBOX_CHECK_ADDR(SrcGCPhys);
3211 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys);
3212 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3213 return val;
3214}
3215
3216
3217/**
3218 * Read guest RAM and ROM, unsigned 16-bit.
3219 *
3220 * @param SrcGCPhys The source address (guest physical).
3221 */
3222uint16_t remR3PhysReadU16(RTGCPHYS SrcGCPhys)
3223{
3224 uint16_t val;
3225 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3226 VBOX_CHECK_ADDR(SrcGCPhys);
3227 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys);
3228 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3229 return val;
3230}
3231
3232
3233/**
3234 * Read guest RAM and ROM, signed 16-bit.
3235 *
3236 * @param SrcGCPhys The source address (guest physical).
3237 */
3238int16_t remR3PhysReadS16(RTGCPHYS SrcGCPhys)
3239{
3240 uint16_t val;
3241 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3242 VBOX_CHECK_ADDR(SrcGCPhys);
3243 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys);
3244 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3245 return val;
3246}
3247
3248
3249/**
3250 * Read guest RAM and ROM, unsigned 32-bit.
3251 *
3252 * @param SrcGCPhys The source address (guest physical).
3253 */
3254uint32_t remR3PhysReadU32(RTGCPHYS SrcGCPhys)
3255{
3256 uint32_t val;
3257 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3258 VBOX_CHECK_ADDR(SrcGCPhys);
3259 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys);
3260 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3261 return val;
3262}
3263
3264
3265/**
3266 * Read guest RAM and ROM, signed 32-bit.
3267 *
3268 * @param SrcGCPhys The source address (guest physical).
3269 */
3270int32_t remR3PhysReadS32(RTGCPHYS SrcGCPhys)
3271{
3272 int32_t val;
3273 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3274 VBOX_CHECK_ADDR(SrcGCPhys);
3275 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys);
3276 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3277 return val;
3278}
3279
3280
3281/**
3282 * Read guest RAM and ROM, unsigned 64-bit.
3283 *
3284 * @param SrcGCPhys The source address (guest physical).
3285 */
3286uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys)
3287{
3288 uint64_t val;
3289 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3290 VBOX_CHECK_ADDR(SrcGCPhys);
3291 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys);
3292 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3293 return val;
3294}
3295
3296
3297/**
3298 * Write guest RAM.
3299 *
3300 * @param DstGCPhys The destination address (guest physical).
3301 * @param pvSrc The source address.
3302 * @param cb Number of bytes to write
3303 */
3304void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb)
3305{
3306 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3307 VBOX_CHECK_ADDR(DstGCPhys);
3308 PGMPhysWrite(cpu_single_env->pVM, DstGCPhys, pvSrc, cb);
3309 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3310}
3311
3312
3313/**
3314 * Write guest RAM, unsigned 8-bit.
3315 *
3316 * @param DstGCPhys The destination address (guest physical).
3317 * @param val Value
3318 */
3319void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val)
3320{
3321 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3322 VBOX_CHECK_ADDR(DstGCPhys);
3323 PGMR3PhysWriteU8(cpu_single_env->pVM, DstGCPhys, val);
3324 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3325}
3326
3327
3328/**
3329 * Write guest RAM, unsigned 8-bit.
3330 *
3331 * @param DstGCPhys The destination address (guest physical).
3332 * @param val Value
3333 */
3334void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val)
3335{
3336 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3337 VBOX_CHECK_ADDR(DstGCPhys);
3338 PGMR3PhysWriteU16(cpu_single_env->pVM, DstGCPhys, val);
3339 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3340}
3341
3342
3343/**
3344 * Write guest RAM, unsigned 32-bit.
3345 *
3346 * @param DstGCPhys The destination address (guest physical).
3347 * @param val Value
3348 */
3349void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val)
3350{
3351 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3352 VBOX_CHECK_ADDR(DstGCPhys);
3353 PGMR3PhysWriteU32(cpu_single_env->pVM, DstGCPhys, val);
3354 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3355}
3356
3357
3358/**
3359 * Write guest RAM, unsigned 64-bit.
3360 *
3361 * @param DstGCPhys The destination address (guest physical).
3362 * @param val Value
3363 */
3364void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val)
3365{
3366 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3367 VBOX_CHECK_ADDR(DstGCPhys);
3368 PGMR3PhysWriteU64(cpu_single_env->pVM, DstGCPhys, val);
3369 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3370}
3371
3372#undef LOG_GROUP
3373#define LOG_GROUP LOG_GROUP_REM_MMIO
3374
3375/** Read MMIO memory. */
3376static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3377{
3378 uint32_t u32 = 0;
3379 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3380 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3381 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", GCPhys, u32));
3382 return u32;
3383}
3384
3385/** Read MMIO memory. */
3386static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3387{
3388 uint32_t u32 = 0;
3389 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3390 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3391 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", GCPhys, u32));
3392 return u32;
3393}
3394
3395/** Read MMIO memory. */
3396static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3397{
3398 uint32_t u32 = 0;
3399 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3400 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3401 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", GCPhys, u32));
3402 return u32;
3403}
3404
3405/** Write to MMIO memory. */
3406static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3407{
3408 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3409 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3410 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3411}
3412
3413/** Write to MMIO memory. */
3414static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3415{
3416 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3417 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3418 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3419}
3420
3421/** Write to MMIO memory. */
3422static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3423{
3424 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3425 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3426 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3427}
3428
3429
3430#undef LOG_GROUP
3431#define LOG_GROUP LOG_GROUP_REM_HANDLER
3432
3433/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3434
3435static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3436{
3437 Log2(("remR3HandlerReadU8: GCPhys=%RGp\n", GCPhys));
3438 uint8_t u8;
3439 PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3440 return u8;
3441}
3442
3443static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3444{
3445 Log2(("remR3HandlerReadU16: GCPhys=%RGp\n", GCPhys));
3446 uint16_t u16;
3447 PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3448 return u16;
3449}
3450
3451static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3452{
3453 Log2(("remR3HandlerReadU32: GCPhys=%RGp\n", GCPhys));
3454 uint32_t u32;
3455 PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3456 return u32;
3457}
3458
3459static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3460{
3461 Log2(("remR3HandlerWriteU8: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3462 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3463}
3464
3465static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3466{
3467 Log2(("remR3HandlerWriteU16: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3468 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3469}
3470
3471static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3472{
3473 Log2(("remR3HandlerWriteU32: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3474 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3475}
3476
3477/* -+- disassembly -+- */
3478
3479#undef LOG_GROUP
3480#define LOG_GROUP LOG_GROUP_REM_DISAS
3481
3482
3483/**
3484 * Enables or disables singled stepped disassembly.
3485 *
3486 * @returns VBox status code.
3487 * @param pVM VM handle.
3488 * @param fEnable To enable set this flag, to disable clear it.
3489 */
3490static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3491{
3492 LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3493 VM_ASSERT_EMT(pVM);
3494
3495 if (fEnable)
3496 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3497 else
3498 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3499 return VINF_SUCCESS;
3500}
3501
3502
3503/**
3504 * Enables or disables singled stepped disassembly.
3505 *
3506 * @returns VBox status code.
3507 * @param pVM VM handle.
3508 * @param fEnable To enable set this flag, to disable clear it.
3509 */
3510REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3511{
3512 PVMREQ pReq;
3513 int rc;
3514
3515 LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3516 if (VM_IS_EMT(pVM))
3517 return remR3DisasEnableStepping(pVM, fEnable);
3518
3519 rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3520 AssertRC(rc);
3521 if (RT_SUCCESS(rc))
3522 rc = pReq->iStatus;
3523 VMR3ReqFree(pReq);
3524 return rc;
3525}
3526
3527
3528#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
3529/**
3530 * External Debugger Command: .remstep [on|off|1|0]
3531 */
3532static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3533{
3534 bool fEnable;
3535 int rc;
3536
3537 /* print status */
3538 if (cArgs == 0)
3539 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3540 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3541
3542 /* convert the argument and change the mode. */
3543 rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3544 if (RT_FAILURE(rc))
3545 return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3546 rc = REMR3DisasEnableStepping(pVM, fEnable);
3547 if (RT_FAILURE(rc))
3548 return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3549 return rc;
3550}
3551#endif
3552
3553
3554/**
3555 * Disassembles one instruction and prints it to the log.
3556 *
3557 * @returns Success indicator.
3558 * @param env Pointer to the recompiler CPU structure.
3559 * @param f32BitCode Indicates that whether or not the code should
3560 * be disassembled as 16 or 32 bit. If -1 the CS
3561 * selector will be inspected.
3562 * @param pszPrefix
3563 */
3564bool remR3DisasInstr(CPUState *env, int f32BitCode, char *pszPrefix)
3565{
3566 PVM pVM = env->pVM;
3567 const bool fLog = LogIsEnabled();
3568 const bool fLog2 = LogIs2Enabled();
3569 int rc = VINF_SUCCESS;
3570
3571 /*
3572 * Don't bother if there ain't any log output to do.
3573 */
3574 if (!fLog && !fLog2)
3575 return true;
3576
3577 /*
3578 * Update the state so DBGF reads the correct register values.
3579 */
3580 remR3StateUpdate(pVM);
3581
3582 /*
3583 * Log registers if requested.
3584 */
3585 if (!fLog2)
3586 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3587
3588 /*
3589 * Disassemble to log.
3590 */
3591 if (fLog)
3592 rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3593
3594 return RT_SUCCESS(rc);
3595}
3596
3597
3598/**
3599 * Disassemble recompiled code.
3600 *
3601 * @param phFileIgnored Ignored, logfile usually.
3602 * @param pvCode Pointer to the code block.
3603 * @param cb Size of the code block.
3604 */
3605void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
3606{
3607 if (LogIs2Enabled())
3608 {
3609 unsigned off = 0;
3610 char szOutput[256];
3611 DISCPUSTATE Cpu;
3612
3613 memset(&Cpu, 0, sizeof(Cpu));
3614#ifdef RT_ARCH_X86
3615 Cpu.mode = CPUMODE_32BIT;
3616#else
3617 Cpu.mode = CPUMODE_64BIT;
3618#endif
3619
3620 RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3621 while (off < cb)
3622 {
3623 uint32_t cbInstr;
3624 if (RT_SUCCESS(DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput)))
3625 RTLogPrintf("%s", szOutput);
3626 else
3627 {
3628 RTLogPrintf("disas error\n");
3629 cbInstr = 1;
3630#ifdef RT_ARCH_AMD64 /** @todo remove when DISInstr starts supporing 64-bit code. */
3631 break;
3632#endif
3633 }
3634 off += cbInstr;
3635 }
3636 }
3637 NOREF(phFileIgnored);
3638}
3639
3640
3641/**
3642 * Disassemble guest code.
3643 *
3644 * @param phFileIgnored Ignored, logfile usually.
3645 * @param uCode The guest address of the code to disassemble. (flat?)
3646 * @param cb Number of bytes to disassemble.
3647 * @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3648 */
3649void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3650{
3651 if (LogIs2Enabled())
3652 {
3653 PVM pVM = cpu_single_env->pVM;
3654
3655 /*
3656 * Update the state so DBGF reads the correct register values (flags).
3657 */
3658 remR3StateUpdate(pVM);
3659
3660 /*
3661 * Do the disassembling.
3662 */
3663 RTLogPrintf("Guest Code: PC=%RGp %#RGp (%RGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3664 RTSEL cs = cpu_single_env->segs[R_CS].selector;
3665 RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3666 for (;;)
3667 {
3668 char szBuf[256];
3669 uint32_t cbInstr;
3670 int rc = DBGFR3DisasInstrEx(pVM,
3671 cs,
3672 eip,
3673 0,
3674 szBuf, sizeof(szBuf),
3675 &cbInstr);
3676 if (RT_SUCCESS(rc))
3677 RTLogPrintf("%RGp %s\n", uCode, szBuf);
3678 else
3679 {
3680 RTLogPrintf("%RGp %04x:%RGv: %s\n", uCode, cs, eip, szBuf);
3681 cbInstr = 1;
3682 }
3683
3684 /* next */
3685 if (cb <= cbInstr)
3686 break;
3687 cb -= cbInstr;
3688 uCode += cbInstr;
3689 eip += cbInstr;
3690 }
3691 }
3692 NOREF(phFileIgnored);
3693}
3694
3695
3696/**
3697 * Looks up a guest symbol.
3698 *
3699 * @returns Pointer to symbol name. This is a static buffer.
3700 * @param orig_addr The address in question.
3701 */
3702const char *lookup_symbol(target_ulong orig_addr)
3703{
3704 RTGCINTPTR off = 0;
3705 DBGFSYMBOL Sym;
3706 PVM pVM = cpu_single_env->pVM;
3707 int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3708 if (RT_SUCCESS(rc))
3709 {
3710 static char szSym[sizeof(Sym.szName) + 48];
3711 if (!off)
3712 RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3713 else if (off > 0)
3714 RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3715 else
3716 RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3717 return szSym;
3718 }
3719 return "<N/A>";
3720}
3721
3722
3723#undef LOG_GROUP
3724#define LOG_GROUP LOG_GROUP_REM
3725
3726
3727/* -+- FF notifications -+- */
3728
3729
3730/**
3731 * Notification about a pending interrupt.
3732 *
3733 * @param pVM VM Handle.
3734 * @param u8Interrupt Interrupt
3735 * @thread The emulation thread.
3736 */
3737REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3738{
3739 Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3740 pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3741}
3742
3743/**
3744 * Notification about a pending interrupt.
3745 *
3746 * @returns Pending interrupt or REM_NO_PENDING_IRQ
3747 * @param pVM VM Handle.
3748 * @thread The emulation thread.
3749 */
3750REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3751{
3752 return pVM->rem.s.u32PendingInterrupt;
3753}
3754
3755/**
3756 * Notification about the interrupt FF being set.
3757 *
3758 * @param pVM VM Handle.
3759 * @thread The emulation thread.
3760 */
3761REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3762{
3763 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3764 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3765 if (pVM->rem.s.fInREM)
3766 {
3767 if (VM_IS_EMT(pVM))
3768 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3769 else
3770 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3771 }
3772}
3773
3774
3775/**
3776 * Notification about the interrupt FF being set.
3777 *
3778 * @param pVM VM Handle.
3779 * @thread Any.
3780 */
3781REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3782{
3783 LogFlow(("REMR3NotifyInterruptClear:\n"));
3784 if (pVM->rem.s.fInREM)
3785 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3786}
3787
3788
3789/**
3790 * Notification about pending timer(s).
3791 *
3792 * @param pVM VM Handle.
3793 * @thread Any.
3794 */
3795REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3796{
3797#ifndef DEBUG_bird
3798 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3799#endif
3800 if (pVM->rem.s.fInREM)
3801 {
3802 if (VM_IS_EMT(pVM))
3803 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3804 else
3805 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3806 }
3807}
3808
3809
3810/**
3811 * Notification about pending DMA transfers.
3812 *
3813 * @param pVM VM Handle.
3814 * @thread Any.
3815 */
3816REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3817{
3818 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3819 if (pVM->rem.s.fInREM)
3820 {
3821 if (VM_IS_EMT(pVM))
3822 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3823 else
3824 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3825 }
3826}
3827
3828
3829/**
3830 * Notification about pending timer(s).
3831 *
3832 * @param pVM VM Handle.
3833 * @thread Any.
3834 */
3835REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3836{
3837 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3838 if (pVM->rem.s.fInREM)
3839 {
3840 if (VM_IS_EMT(pVM))
3841 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3842 else
3843 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3844 }
3845}
3846
3847
3848/**
3849 * Notification about pending FF set by an external thread.
3850 *
3851 * @param pVM VM handle.
3852 * @thread Any.
3853 */
3854REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3855{
3856 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3857 if (pVM->rem.s.fInREM)
3858 {
3859 if (VM_IS_EMT(pVM))
3860 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3861 else
3862 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3863 }
3864}
3865
3866
3867#ifdef VBOX_WITH_STATISTICS
3868void remR3ProfileStart(int statcode)
3869{
3870 STAMPROFILEADV *pStat;
3871 switch(statcode)
3872 {
3873 case STATS_EMULATE_SINGLE_INSTR:
3874 pStat = &gStatExecuteSingleInstr;
3875 break;
3876 case STATS_QEMU_COMPILATION:
3877 pStat = &gStatCompilationQEmu;
3878 break;
3879 case STATS_QEMU_RUN_EMULATED_CODE:
3880 pStat = &gStatRunCodeQEmu;
3881 break;
3882 case STATS_QEMU_TOTAL:
3883 pStat = &gStatTotalTimeQEmu;
3884 break;
3885 case STATS_QEMU_RUN_TIMERS:
3886 pStat = &gStatTimers;
3887 break;
3888 case STATS_TLB_LOOKUP:
3889 pStat= &gStatTBLookup;
3890 break;
3891 case STATS_IRQ_HANDLING:
3892 pStat= &gStatIRQ;
3893 break;
3894 case STATS_RAW_CHECK:
3895 pStat = &gStatRawCheck;
3896 break;
3897
3898 default:
3899 AssertMsgFailed(("unknown stat %d\n", statcode));
3900 return;
3901 }
3902 STAM_PROFILE_ADV_START(pStat, a);
3903}
3904
3905
3906void remR3ProfileStop(int statcode)
3907{
3908 STAMPROFILEADV *pStat;
3909 switch(statcode)
3910 {
3911 case STATS_EMULATE_SINGLE_INSTR:
3912 pStat = &gStatExecuteSingleInstr;
3913 break;
3914 case STATS_QEMU_COMPILATION:
3915 pStat = &gStatCompilationQEmu;
3916 break;
3917 case STATS_QEMU_RUN_EMULATED_CODE:
3918 pStat = &gStatRunCodeQEmu;
3919 break;
3920 case STATS_QEMU_TOTAL:
3921 pStat = &gStatTotalTimeQEmu;
3922 break;
3923 case STATS_QEMU_RUN_TIMERS:
3924 pStat = &gStatTimers;
3925 break;
3926 case STATS_TLB_LOOKUP:
3927 pStat= &gStatTBLookup;
3928 break;
3929 case STATS_IRQ_HANDLING:
3930 pStat= &gStatIRQ;
3931 break;
3932 case STATS_RAW_CHECK:
3933 pStat = &gStatRawCheck;
3934 break;
3935 default:
3936 AssertMsgFailed(("unknown stat %d\n", statcode));
3937 return;
3938 }
3939 STAM_PROFILE_ADV_STOP(pStat, a);
3940}
3941#endif
3942
3943/**
3944 * Raise an RC, force rem exit.
3945 *
3946 * @param pVM VM handle.
3947 * @param rc The rc.
3948 */
3949void remR3RaiseRC(PVM pVM, int rc)
3950{
3951 Log(("remR3RaiseRC: rc=%Rrc\n", rc));
3952 Assert(pVM->rem.s.fInREM);
3953 VM_ASSERT_EMT(pVM);
3954 pVM->rem.s.rc = rc;
3955 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
3956}
3957
3958
3959/* -+- timers -+- */
3960
3961uint64_t cpu_get_tsc(CPUX86State *env)
3962{
3963 STAM_COUNTER_INC(&gStatCpuGetTSC);
3964 return TMCpuTickGet(env->pVM);
3965}
3966
3967
3968/* -+- interrupts -+- */
3969
3970void cpu_set_ferr(CPUX86State *env)
3971{
3972 int rc = PDMIsaSetIrq(env->pVM, 13, 1);
3973 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
3974}
3975
3976int cpu_get_pic_interrupt(CPUState *env)
3977{
3978 uint8_t u8Interrupt;
3979 int rc;
3980
3981 /* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
3982 * In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
3983 * with the (a)pic.
3984 */
3985 /** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
3986 /** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
3987 * if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
3988 * remove this kludge. */
3989 if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
3990 {
3991 rc = VINF_SUCCESS;
3992 Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
3993 u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
3994 env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
3995 }
3996 else
3997 rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
3998
3999 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Rrc\n", u8Interrupt, rc));
4000 if (RT_SUCCESS(rc))
4001 {
4002 if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
4003 env->interrupt_request |= CPU_INTERRUPT_HARD;
4004 return u8Interrupt;
4005 }
4006 return -1;
4007}
4008
4009
4010/* -+- local apic -+- */
4011
4012void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4013{
4014 int rc = PDMApicSetBase(env->pVM, val);
4015 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Rrc\n", val, rc)); NOREF(rc);
4016}
4017
4018uint64_t cpu_get_apic_base(CPUX86State *env)
4019{
4020 uint64_t u64;
4021 int rc = PDMApicGetBase(env->pVM, &u64);
4022 if (RT_SUCCESS(rc))
4023 {
4024 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4025 return u64;
4026 }
4027 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", rc));
4028 return 0;
4029}
4030
4031void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4032{
4033 int rc = PDMApicSetTPR(env->pVM, val);
4034 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Rrc\n", val, rc)); NOREF(rc);
4035}
4036
4037uint8_t cpu_get_apic_tpr(CPUX86State *env)
4038{
4039 uint8_t u8;
4040 int rc = PDMApicGetTPR(env->pVM, &u8, NULL);
4041 if (RT_SUCCESS(rc))
4042 {
4043 LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4044 return u8;
4045 }
4046 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Rrc)\n", rc));
4047 return 0;
4048}
4049
4050
4051uint64_t cpu_apic_rdmsr(CPUX86State *env, uint32_t reg)
4052{
4053 uint64_t value;
4054 int rc = PDMApicReadMSR(env->pVM, 0/* cpu */, reg, &value);
4055 if (RT_SUCCESS(rc))
4056 {
4057 LogFlow(("cpu_apic_rdms returns %#x\n", value));
4058 return value;
4059 }
4060 /** @todo: exception ? */
4061 LogFlow(("cpu_apic_rdms returns 0 (rc=%Rrc)\n", rc));
4062 return value;
4063}
4064
4065void cpu_apic_wrmsr(CPUX86State *env, uint32_t reg, uint64_t value)
4066{
4067 int rc = PDMApicWriteMSR(env->pVM, 0 /* cpu */, reg, value);
4068 /** @todo: exception if error ? */
4069 LogFlow(("cpu_apic_wrmsr: rc=%Rrc\n", rc)); NOREF(rc);
4070}
4071
4072uint64_t cpu_rdmsr(CPUX86State *env, uint32_t msr)
4073{
4074 return CPUMGetGuestMsr(env->pVM, msr);
4075}
4076
4077void cpu_wrmsr(CPUX86State *env, uint32_t msr, uint64_t val)
4078{
4079 CPUMSetGuestMsr(env->pVM, msr, val);
4080}
4081
4082/* -+- I/O Ports -+- */
4083
4084#undef LOG_GROUP
4085#define LOG_GROUP LOG_GROUP_REM_IOPORT
4086
4087void cpu_outb(CPUState *env, int addr, int val)
4088{
4089 if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4090 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4091
4092 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4093 if (RT_LIKELY(rc == VINF_SUCCESS))
4094 return;
4095 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4096 {
4097 Log(("cpu_outb: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4098 remR3RaiseRC(env->pVM, rc);
4099 return;
4100 }
4101 remAbort(rc, __FUNCTION__);
4102}
4103
4104void cpu_outw(CPUState *env, int addr, int val)
4105{
4106 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4107 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4108 if (RT_LIKELY(rc == VINF_SUCCESS))
4109 return;
4110 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4111 {
4112 Log(("cpu_outw: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4113 remR3RaiseRC(env->pVM, rc);
4114 return;
4115 }
4116 remAbort(rc, __FUNCTION__);
4117}
4118
4119void cpu_outl(CPUState *env, int addr, int val)
4120{
4121 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4122 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4123 if (RT_LIKELY(rc == VINF_SUCCESS))
4124 return;
4125 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4126 {
4127 Log(("cpu_outl: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4128 remR3RaiseRC(env->pVM, rc);
4129 return;
4130 }
4131 remAbort(rc, __FUNCTION__);
4132}
4133
4134int cpu_inb(CPUState *env, int addr)
4135{
4136 uint32_t u32 = 0;
4137 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4138 if (RT_LIKELY(rc == VINF_SUCCESS))
4139 {
4140 if (/*addr != 0x61 && */addr != 0x71)
4141 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4142 return (int)u32;
4143 }
4144 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4145 {
4146 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4147 remR3RaiseRC(env->pVM, rc);
4148 return (int)u32;
4149 }
4150 remAbort(rc, __FUNCTION__);
4151 return 0xff;
4152}
4153
4154int cpu_inw(CPUState *env, int addr)
4155{
4156 uint32_t u32 = 0;
4157 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4158 if (RT_LIKELY(rc == VINF_SUCCESS))
4159 {
4160 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4161 return (int)u32;
4162 }
4163 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4164 {
4165 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4166 remR3RaiseRC(env->pVM, rc);
4167 return (int)u32;
4168 }
4169 remAbort(rc, __FUNCTION__);
4170 return 0xffff;
4171}
4172
4173int cpu_inl(CPUState *env, int addr)
4174{
4175 uint32_t u32 = 0;
4176 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4177 if (RT_LIKELY(rc == VINF_SUCCESS))
4178 {
4179//if (addr==0x01f0 && u32 == 0x6b6d)
4180// loglevel = ~0;
4181 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4182 return (int)u32;
4183 }
4184 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4185 {
4186 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4187 remR3RaiseRC(env->pVM, rc);
4188 return (int)u32;
4189 }
4190 remAbort(rc, __FUNCTION__);
4191 return 0xffffffff;
4192}
4193
4194#undef LOG_GROUP
4195#define LOG_GROUP LOG_GROUP_REM
4196
4197
4198/* -+- helpers and misc other interfaces -+- */
4199
4200/**
4201 * Perform the CPUID instruction.
4202 *
4203 * ASMCpuId cannot be invoked from some source files where this is used because of global
4204 * register allocations.
4205 *
4206 * @param env Pointer to the recompiler CPU structure.
4207 * @param uOperator CPUID operation (eax).
4208 * @param pvEAX Where to store eax.
4209 * @param pvEBX Where to store ebx.
4210 * @param pvECX Where to store ecx.
4211 * @param pvEDX Where to store edx.
4212 */
4213void remR3CpuId(CPUState *env, unsigned uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
4214{
4215 CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t *)pvEAX, (uint32_t *)pvEBX, (uint32_t *)pvECX, (uint32_t *)pvEDX);
4216}
4217
4218
4219#if 0 /* not used */
4220/**
4221 * Interface for qemu hardware to report back fatal errors.
4222 */
4223void hw_error(const char *pszFormat, ...)
4224{
4225 /*
4226 * Bitch about it.
4227 */
4228 /** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4229 * this in my Odin32 tree at home! */
4230 va_list args;
4231 va_start(args, pszFormat);
4232 RTLogPrintf("fatal error in virtual hardware:");
4233 RTLogPrintfV(pszFormat, args);
4234 va_end(args);
4235 AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4236
4237 /*
4238 * If we're in REM context we'll sync back the state before 'jumping' to
4239 * the EMs failure handling.
4240 */
4241 PVM pVM = cpu_single_env->pVM;
4242 if (pVM->rem.s.fInREM)
4243 REMR3StateBack(pVM);
4244 EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4245 AssertMsgFailed(("EMR3FatalError returned!\n"));
4246}
4247#endif
4248
4249/**
4250 * Interface for the qemu cpu to report unhandled situation
4251 * raising a fatal VM error.
4252 */
4253void cpu_abort(CPUState *env, const char *pszFormat, ...)
4254{
4255 /*
4256 * Bitch about it.
4257 */
4258 RTLogFlags(NULL, "nodisabled nobuffered");
4259 va_list args;
4260 va_start(args, pszFormat);
4261 RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4262 va_end(args);
4263 va_start(args, pszFormat);
4264 AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4265 va_end(args);
4266
4267 /*
4268 * If we're in REM context we'll sync back the state before 'jumping' to
4269 * the EMs failure handling.
4270 */
4271 PVM pVM = cpu_single_env->pVM;
4272 if (pVM->rem.s.fInREM)
4273 REMR3StateBack(pVM);
4274 EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4275 AssertMsgFailed(("EMR3FatalError returned!\n"));
4276}
4277
4278
4279/**
4280 * Aborts the VM.
4281 *
4282 * @param rc VBox error code.
4283 * @param pszTip Hint about why/when this happend.
4284 */
4285static void remAbort(int rc, const char *pszTip)
4286{
4287 /*
4288 * Bitch about it.
4289 */
4290 RTLogPrintf("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip);
4291 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip));
4292
4293 /*
4294 * Jump back to where we entered the recompiler.
4295 */
4296 PVM pVM = cpu_single_env->pVM;
4297 if (pVM->rem.s.fInREM)
4298 REMR3StateBack(pVM);
4299 EMR3FatalError(pVM, rc);
4300 AssertMsgFailed(("EMR3FatalError returned!\n"));
4301}
4302
4303
4304/**
4305 * Dumps a linux system call.
4306 * @param pVM VM handle.
4307 */
4308void remR3DumpLnxSyscall(PVM pVM)
4309{
4310 static const char *apsz[] =
4311 {
4312 "sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4313 "sys_exit",
4314 "sys_fork",
4315 "sys_read",
4316 "sys_write",
4317 "sys_open", /* 5 */
4318 "sys_close",
4319 "sys_waitpid",
4320 "sys_creat",
4321 "sys_link",
4322 "sys_unlink", /* 10 */
4323 "sys_execve",
4324 "sys_chdir",
4325 "sys_time",
4326 "sys_mknod",
4327 "sys_chmod", /* 15 */
4328 "sys_lchown16",
4329 "sys_ni_syscall", /* old break syscall holder */
4330 "sys_stat",
4331 "sys_lseek",
4332 "sys_getpid", /* 20 */
4333 "sys_mount",
4334 "sys_oldumount",
4335 "sys_setuid16",
4336 "sys_getuid16",
4337 "sys_stime", /* 25 */
4338 "sys_ptrace",
4339 "sys_alarm",
4340 "sys_fstat",
4341 "sys_pause",
4342 "sys_utime", /* 30 */
4343 "sys_ni_syscall", /* old stty syscall holder */
4344 "sys_ni_syscall", /* old gtty syscall holder */
4345 "sys_access",
4346 "sys_nice",
4347 "sys_ni_syscall", /* 35 - old ftime syscall holder */
4348 "sys_sync",
4349 "sys_kill",
4350 "sys_rename",
4351 "sys_mkdir",
4352 "sys_rmdir", /* 40 */
4353 "sys_dup",
4354 "sys_pipe",
4355 "sys_times",
4356 "sys_ni_syscall", /* old prof syscall holder */
4357 "sys_brk", /* 45 */
4358 "sys_setgid16",
4359 "sys_getgid16",
4360 "sys_signal",
4361 "sys_geteuid16",
4362 "sys_getegid16", /* 50 */
4363 "sys_acct",
4364 "sys_umount", /* recycled never used phys() */
4365 "sys_ni_syscall", /* old lock syscall holder */
4366 "sys_ioctl",
4367 "sys_fcntl", /* 55 */
4368 "sys_ni_syscall", /* old mpx syscall holder */
4369 "sys_setpgid",
4370 "sys_ni_syscall", /* old ulimit syscall holder */
4371 "sys_olduname",
4372 "sys_umask", /* 60 */
4373 "sys_chroot",
4374 "sys_ustat",
4375 "sys_dup2",
4376 "sys_getppid",
4377 "sys_getpgrp", /* 65 */
4378 "sys_setsid",
4379 "sys_sigaction",
4380 "sys_sgetmask",
4381 "sys_ssetmask",
4382 "sys_setreuid16", /* 70 */
4383 "sys_setregid16",
4384 "sys_sigsuspend",
4385 "sys_sigpending",
4386 "sys_sethostname",
4387 "sys_setrlimit", /* 75 */
4388 "sys_old_getrlimit",
4389 "sys_getrusage",
4390 "sys_gettimeofday",
4391 "sys_settimeofday",
4392 "sys_getgroups16", /* 80 */
4393 "sys_setgroups16",
4394 "old_select",
4395 "sys_symlink",
4396 "sys_lstat",
4397 "sys_readlink", /* 85 */
4398 "sys_uselib",
4399 "sys_swapon",
4400 "sys_reboot",
4401 "old_readdir",
4402 "old_mmap", /* 90 */
4403 "sys_munmap",
4404 "sys_truncate",
4405 "sys_ftruncate",
4406 "sys_fchmod",
4407 "sys_fchown16", /* 95 */
4408 "sys_getpriority",
4409 "sys_setpriority",
4410 "sys_ni_syscall", /* old profil syscall holder */
4411 "sys_statfs",
4412 "sys_fstatfs", /* 100 */
4413 "sys_ioperm",
4414 "sys_socketcall",
4415 "sys_syslog",
4416 "sys_setitimer",
4417 "sys_getitimer", /* 105 */
4418 "sys_newstat",
4419 "sys_newlstat",
4420 "sys_newfstat",
4421 "sys_uname",
4422 "sys_iopl", /* 110 */
4423 "sys_vhangup",
4424 "sys_ni_syscall", /* old "idle" system call */
4425 "sys_vm86old",
4426 "sys_wait4",
4427 "sys_swapoff", /* 115 */
4428 "sys_sysinfo",
4429 "sys_ipc",
4430 "sys_fsync",
4431 "sys_sigreturn",
4432 "sys_clone", /* 120 */
4433 "sys_setdomainname",
4434 "sys_newuname",
4435 "sys_modify_ldt",
4436 "sys_adjtimex",
4437 "sys_mprotect", /* 125 */
4438 "sys_sigprocmask",
4439 "sys_ni_syscall", /* old "create_module" */
4440 "sys_init_module",
4441 "sys_delete_module",
4442 "sys_ni_syscall", /* 130: old "get_kernel_syms" */
4443 "sys_quotactl",
4444 "sys_getpgid",
4445 "sys_fchdir",
4446 "sys_bdflush",
4447 "sys_sysfs", /* 135 */
4448 "sys_personality",
4449 "sys_ni_syscall", /* reserved for afs_syscall */
4450 "sys_setfsuid16",
4451 "sys_setfsgid16",
4452 "sys_llseek", /* 140 */
4453 "sys_getdents",
4454 "sys_select",
4455 "sys_flock",
4456 "sys_msync",
4457 "sys_readv", /* 145 */
4458 "sys_writev",
4459 "sys_getsid",
4460 "sys_fdatasync",
4461 "sys_sysctl",
4462 "sys_mlock", /* 150 */
4463 "sys_munlock",
4464 "sys_mlockall",
4465 "sys_munlockall",
4466 "sys_sched_setparam",
4467 "sys_sched_getparam", /* 155 */
4468 "sys_sched_setscheduler",
4469 "sys_sched_getscheduler",
4470 "sys_sched_yield",
4471 "sys_sched_get_priority_max",
4472 "sys_sched_get_priority_min", /* 160 */
4473 "sys_sched_rr_get_interval",
4474 "sys_nanosleep",
4475 "sys_mremap",
4476 "sys_setresuid16",
4477 "sys_getresuid16", /* 165 */
4478 "sys_vm86",
4479 "sys_ni_syscall", /* Old sys_query_module */
4480 "sys_poll",
4481 "sys_nfsservctl",
4482 "sys_setresgid16", /* 170 */
4483 "sys_getresgid16",
4484 "sys_prctl",
4485 "sys_rt_sigreturn",
4486 "sys_rt_sigaction",
4487 "sys_rt_sigprocmask", /* 175 */
4488 "sys_rt_sigpending",
4489 "sys_rt_sigtimedwait",
4490 "sys_rt_sigqueueinfo",
4491 "sys_rt_sigsuspend",
4492 "sys_pread64", /* 180 */
4493 "sys_pwrite64",
4494 "sys_chown16",
4495 "sys_getcwd",
4496 "sys_capget",
4497 "sys_capset", /* 185 */
4498 "sys_sigaltstack",
4499 "sys_sendfile",
4500 "sys_ni_syscall", /* reserved for streams1 */
4501 "sys_ni_syscall", /* reserved for streams2 */
4502 "sys_vfork", /* 190 */
4503 "sys_getrlimit",
4504 "sys_mmap2",
4505 "sys_truncate64",
4506 "sys_ftruncate64",
4507 "sys_stat64", /* 195 */
4508 "sys_lstat64",
4509 "sys_fstat64",
4510 "sys_lchown",
4511 "sys_getuid",
4512 "sys_getgid", /* 200 */
4513 "sys_geteuid",
4514 "sys_getegid",
4515 "sys_setreuid",
4516 "sys_setregid",
4517 "sys_getgroups", /* 205 */
4518 "sys_setgroups",
4519 "sys_fchown",
4520 "sys_setresuid",
4521 "sys_getresuid",
4522 "sys_setresgid", /* 210 */
4523 "sys_getresgid",
4524 "sys_chown",
4525 "sys_setuid",
4526 "sys_setgid",
4527 "sys_setfsuid", /* 215 */
4528 "sys_setfsgid",
4529 "sys_pivot_root",
4530 "sys_mincore",
4531 "sys_madvise",
4532 "sys_getdents64", /* 220 */
4533 "sys_fcntl64",
4534 "sys_ni_syscall", /* reserved for TUX */
4535 "sys_ni_syscall",
4536 "sys_gettid",
4537 "sys_readahead", /* 225 */
4538 "sys_setxattr",
4539 "sys_lsetxattr",
4540 "sys_fsetxattr",
4541 "sys_getxattr",
4542 "sys_lgetxattr", /* 230 */
4543 "sys_fgetxattr",
4544 "sys_listxattr",
4545 "sys_llistxattr",
4546 "sys_flistxattr",
4547 "sys_removexattr", /* 235 */
4548 "sys_lremovexattr",
4549 "sys_fremovexattr",
4550 "sys_tkill",
4551 "sys_sendfile64",
4552 "sys_futex", /* 240 */
4553 "sys_sched_setaffinity",
4554 "sys_sched_getaffinity",
4555 "sys_set_thread_area",
4556 "sys_get_thread_area",
4557 "sys_io_setup", /* 245 */
4558 "sys_io_destroy",
4559 "sys_io_getevents",
4560 "sys_io_submit",
4561 "sys_io_cancel",
4562 "sys_fadvise64", /* 250 */
4563 "sys_ni_syscall",
4564 "sys_exit_group",
4565 "sys_lookup_dcookie",
4566 "sys_epoll_create",
4567 "sys_epoll_ctl", /* 255 */
4568 "sys_epoll_wait",
4569 "sys_remap_file_pages",
4570 "sys_set_tid_address",
4571 "sys_timer_create",
4572 "sys_timer_settime", /* 260 */
4573 "sys_timer_gettime",
4574 "sys_timer_getoverrun",
4575 "sys_timer_delete",
4576 "sys_clock_settime",
4577 "sys_clock_gettime", /* 265 */
4578 "sys_clock_getres",
4579 "sys_clock_nanosleep",
4580 "sys_statfs64",
4581 "sys_fstatfs64",
4582 "sys_tgkill", /* 270 */
4583 "sys_utimes",
4584 "sys_fadvise64_64",
4585 "sys_ni_syscall" /* sys_vserver */
4586 };
4587
4588 uint32_t uEAX = CPUMGetGuestEAX(pVM);
4589 switch (uEAX)
4590 {
4591 default:
4592 if (uEAX < RT_ELEMENTS(apsz))
4593 Log(("REM: linux syscall %3d: %s (eip=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4594 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4595 CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4596 else
4597 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4598 break;
4599
4600 }
4601}
4602
4603
4604/**
4605 * Dumps an OpenBSD system call.
4606 * @param pVM VM handle.
4607 */
4608void remR3DumpOBsdSyscall(PVM pVM)
4609{
4610 static const char *apsz[] =
4611 {
4612 "SYS_syscall", //0
4613 "SYS_exit", //1
4614 "SYS_fork", //2
4615 "SYS_read", //3
4616 "SYS_write", //4
4617 "SYS_open", //5
4618 "SYS_close", //6
4619 "SYS_wait4", //7
4620 "SYS_8",
4621 "SYS_link", //9
4622 "SYS_unlink", //10
4623 "SYS_11",
4624 "SYS_chdir", //12
4625 "SYS_fchdir", //13
4626 "SYS_mknod", //14
4627 "SYS_chmod", //15
4628 "SYS_chown", //16
4629 "SYS_break", //17
4630 "SYS_18",
4631 "SYS_19",
4632 "SYS_getpid", //20
4633 "SYS_mount", //21
4634 "SYS_unmount", //22
4635 "SYS_setuid", //23
4636 "SYS_getuid", //24
4637 "SYS_geteuid", //25
4638 "SYS_ptrace", //26
4639 "SYS_recvmsg", //27
4640 "SYS_sendmsg", //28
4641 "SYS_recvfrom", //29
4642 "SYS_accept", //30
4643 "SYS_getpeername", //31
4644 "SYS_getsockname", //32
4645 "SYS_access", //33
4646 "SYS_chflags", //34
4647 "SYS_fchflags", //35
4648 "SYS_sync", //36
4649 "SYS_kill", //37
4650 "SYS_38",
4651 "SYS_getppid", //39
4652 "SYS_40",
4653 "SYS_dup", //41
4654 "SYS_opipe", //42
4655 "SYS_getegid", //43
4656 "SYS_profil", //44
4657 "SYS_ktrace", //45
4658 "SYS_sigaction", //46
4659 "SYS_getgid", //47
4660 "SYS_sigprocmask", //48
4661 "SYS_getlogin", //49
4662 "SYS_setlogin", //50
4663 "SYS_acct", //51
4664 "SYS_sigpending", //52
4665 "SYS_osigaltstack", //53
4666 "SYS_ioctl", //54
4667 "SYS_reboot", //55
4668 "SYS_revoke", //56
4669 "SYS_symlink", //57
4670 "SYS_readlink", //58
4671 "SYS_execve", //59
4672 "SYS_umask", //60
4673 "SYS_chroot", //61
4674 "SYS_62",
4675 "SYS_63",
4676 "SYS_64",
4677 "SYS_65",
4678 "SYS_vfork", //66
4679 "SYS_67",
4680 "SYS_68",
4681 "SYS_sbrk", //69
4682 "SYS_sstk", //70
4683 "SYS_61",
4684 "SYS_vadvise", //72
4685 "SYS_munmap", //73
4686 "SYS_mprotect", //74
4687 "SYS_madvise", //75
4688 "SYS_76",
4689 "SYS_77",
4690 "SYS_mincore", //78
4691 "SYS_getgroups", //79
4692 "SYS_setgroups", //80
4693 "SYS_getpgrp", //81
4694 "SYS_setpgid", //82
4695 "SYS_setitimer", //83
4696 "SYS_84",
4697 "SYS_85",
4698 "SYS_getitimer", //86
4699 "SYS_87",
4700 "SYS_88",
4701 "SYS_89",
4702 "SYS_dup2", //90
4703 "SYS_91",
4704 "SYS_fcntl", //92
4705 "SYS_select", //93
4706 "SYS_94",
4707 "SYS_fsync", //95
4708 "SYS_setpriority", //96
4709 "SYS_socket", //97
4710 "SYS_connect", //98
4711 "SYS_99",
4712 "SYS_getpriority", //100
4713 "SYS_101",
4714 "SYS_102",
4715 "SYS_sigreturn", //103
4716 "SYS_bind", //104
4717 "SYS_setsockopt", //105
4718 "SYS_listen", //106
4719 "SYS_107",
4720 "SYS_108",
4721 "SYS_109",
4722 "SYS_110",
4723 "SYS_sigsuspend", //111
4724 "SYS_112",
4725 "SYS_113",
4726 "SYS_114",
4727 "SYS_115",
4728 "SYS_gettimeofday", //116
4729 "SYS_getrusage", //117
4730 "SYS_getsockopt", //118
4731 "SYS_119",
4732 "SYS_readv", //120
4733 "SYS_writev", //121
4734 "SYS_settimeofday", //122
4735 "SYS_fchown", //123
4736 "SYS_fchmod", //124
4737 "SYS_125",
4738 "SYS_setreuid", //126
4739 "SYS_setregid", //127
4740 "SYS_rename", //128
4741 "SYS_129",
4742 "SYS_130",
4743 "SYS_flock", //131
4744 "SYS_mkfifo", //132
4745 "SYS_sendto", //133
4746 "SYS_shutdown", //134
4747 "SYS_socketpair", //135
4748 "SYS_mkdir", //136
4749 "SYS_rmdir", //137
4750 "SYS_utimes", //138
4751 "SYS_139",
4752 "SYS_adjtime", //140
4753 "SYS_141",
4754 "SYS_142",
4755 "SYS_143",
4756 "SYS_144",
4757 "SYS_145",
4758 "SYS_146",
4759 "SYS_setsid", //147
4760 "SYS_quotactl", //148
4761 "SYS_149",
4762 "SYS_150",
4763 "SYS_151",
4764 "SYS_152",
4765 "SYS_153",
4766 "SYS_154",
4767 "SYS_nfssvc", //155
4768 "SYS_156",
4769 "SYS_157",
4770 "SYS_158",
4771 "SYS_159",
4772 "SYS_160",
4773 "SYS_getfh", //161
4774 "SYS_162",
4775 "SYS_163",
4776 "SYS_164",
4777 "SYS_sysarch", //165
4778 "SYS_166",
4779 "SYS_167",
4780 "SYS_168",
4781 "SYS_169",
4782 "SYS_170",
4783 "SYS_171",
4784 "SYS_172",
4785 "SYS_pread", //173
4786 "SYS_pwrite", //174
4787 "SYS_175",
4788 "SYS_176",
4789 "SYS_177",
4790 "SYS_178",
4791 "SYS_179",
4792 "SYS_180",
4793 "SYS_setgid", //181
4794 "SYS_setegid", //182
4795 "SYS_seteuid", //183
4796 "SYS_lfs_bmapv", //184
4797 "SYS_lfs_markv", //185
4798 "SYS_lfs_segclean", //186
4799 "SYS_lfs_segwait", //187
4800 "SYS_188",
4801 "SYS_189",
4802 "SYS_190",
4803 "SYS_pathconf", //191
4804 "SYS_fpathconf", //192
4805 "SYS_swapctl", //193
4806 "SYS_getrlimit", //194
4807 "SYS_setrlimit", //195
4808 "SYS_getdirentries", //196
4809 "SYS_mmap", //197
4810 "SYS___syscall", //198
4811 "SYS_lseek", //199
4812 "SYS_truncate", //200
4813 "SYS_ftruncate", //201
4814 "SYS___sysctl", //202
4815 "SYS_mlock", //203
4816 "SYS_munlock", //204
4817 "SYS_205",
4818 "SYS_futimes", //206
4819 "SYS_getpgid", //207
4820 "SYS_xfspioctl", //208
4821 "SYS_209",
4822 "SYS_210",
4823 "SYS_211",
4824 "SYS_212",
4825 "SYS_213",
4826 "SYS_214",
4827 "SYS_215",
4828 "SYS_216",
4829 "SYS_217",
4830 "SYS_218",
4831 "SYS_219",
4832 "SYS_220",
4833 "SYS_semget", //221
4834 "SYS_222",
4835 "SYS_223",
4836 "SYS_224",
4837 "SYS_msgget", //225
4838 "SYS_msgsnd", //226
4839 "SYS_msgrcv", //227
4840 "SYS_shmat", //228
4841 "SYS_229",
4842 "SYS_shmdt", //230
4843 "SYS_231",
4844 "SYS_clock_gettime", //232
4845 "SYS_clock_settime", //233
4846 "SYS_clock_getres", //234
4847 "SYS_235",
4848 "SYS_236",
4849 "SYS_237",
4850 "SYS_238",
4851 "SYS_239",
4852 "SYS_nanosleep", //240
4853 "SYS_241",
4854 "SYS_242",
4855 "SYS_243",
4856 "SYS_244",
4857 "SYS_245",
4858 "SYS_246",
4859 "SYS_247",
4860 "SYS_248",
4861 "SYS_249",
4862 "SYS_minherit", //250
4863 "SYS_rfork", //251
4864 "SYS_poll", //252
4865 "SYS_issetugid", //253
4866 "SYS_lchown", //254
4867 "SYS_getsid", //255
4868 "SYS_msync", //256
4869 "SYS_257",
4870 "SYS_258",
4871 "SYS_259",
4872 "SYS_getfsstat", //260
4873 "SYS_statfs", //261
4874 "SYS_fstatfs", //262
4875 "SYS_pipe", //263
4876 "SYS_fhopen", //264
4877 "SYS_265",
4878 "SYS_fhstatfs", //266
4879 "SYS_preadv", //267
4880 "SYS_pwritev", //268
4881 "SYS_kqueue", //269
4882 "SYS_kevent", //270
4883 "SYS_mlockall", //271
4884 "SYS_munlockall", //272
4885 "SYS_getpeereid", //273
4886 "SYS_274",
4887 "SYS_275",
4888 "SYS_276",
4889 "SYS_277",
4890 "SYS_278",
4891 "SYS_279",
4892 "SYS_280",
4893 "SYS_getresuid", //281
4894 "SYS_setresuid", //282
4895 "SYS_getresgid", //283
4896 "SYS_setresgid", //284
4897 "SYS_285",
4898 "SYS_mquery", //286
4899 "SYS_closefrom", //287
4900 "SYS_sigaltstack", //288
4901 "SYS_shmget", //289
4902 "SYS_semop", //290
4903 "SYS_stat", //291
4904 "SYS_fstat", //292
4905 "SYS_lstat", //293
4906 "SYS_fhstat", //294
4907 "SYS___semctl", //295
4908 "SYS_shmctl", //296
4909 "SYS_msgctl", //297
4910 "SYS_MAXSYSCALL", //298
4911 //299
4912 //300
4913 };
4914 uint32_t uEAX;
4915 if (!LogIsEnabled())
4916 return;
4917 uEAX = CPUMGetGuestEAX(pVM);
4918 switch (uEAX)
4919 {
4920 default:
4921 if (uEAX < RT_ELEMENTS(apsz))
4922 {
4923 uint32_t au32Args[8] = {0};
4924 PGMPhysSimpleReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4925 RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4926 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4927 au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4928 }
4929 else
4930 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4931 break;
4932 }
4933}
4934
4935
4936#if defined(IPRT_NO_CRT) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
4937/**
4938 * The Dll main entry point (stub).
4939 */
4940bool __stdcall _DllMainCRTStartup(void *hModule, uint32_t dwReason, void *pvReserved)
4941{
4942 return true;
4943}
4944
4945void *memcpy(void *dst, const void *src, size_t size)
4946{
4947 uint8_t*pbDst = dst, *pbSrc = src;
4948 while (size-- > 0)
4949 *pbDst++ = *pbSrc++;
4950 return dst;
4951}
4952
4953#endif
4954
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette