VirtualBox

source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 67149

Last change on this file since 67149 was 66262, checked in by vboxsync, 8 years ago

REM: Do not mess with the TSS busy flag in CPU. Make sure that when loading TSS, the busy flag is set, not cleared. (bugref:8818)
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1/* $Id: VBoxRecompiler.c 66262 2017-03-27 10:25:29Z vboxsync $ */
2/** @file
3 * VBox Recompiler - QEMU.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_rem REM - Recompiled Execution Manager.
19 *
20 * The recompiled exeuction manager (REM) serves the final fallback for guest
21 * execution, after HM / raw-mode and IEM have given up.
22 *
23 * The REM is qemu with a whole bunch of VBox specific customization for
24 * interfacing with PATM, CSAM, PGM and other components.
25 *
26 * @sa @ref grp_rem
27 */
28
29
30/*********************************************************************************************************************************
31* Header Files *
32*********************************************************************************************************************************/
33#define LOG_GROUP LOG_GROUP_REM
34#include <stdio.h> /* FILE */
35#include "osdep.h"
36#include "config.h"
37#include "cpu.h"
38#include "exec-all.h"
39#include "ioport.h"
40
41#include <VBox/vmm/rem.h>
42#include <VBox/vmm/vmapi.h>
43#include <VBox/vmm/tm.h>
44#include <VBox/vmm/ssm.h>
45#include <VBox/vmm/em.h>
46#include <VBox/vmm/trpm.h>
47#include <VBox/vmm/iom.h>
48#include <VBox/vmm/mm.h>
49#include <VBox/vmm/pgm.h>
50#include <VBox/vmm/pdm.h>
51#include <VBox/vmm/dbgf.h>
52#include <VBox/dbg.h>
53#include <VBox/vmm/apic.h>
54#include <VBox/vmm/hm.h>
55#include <VBox/vmm/patm.h>
56#include <VBox/vmm/csam.h>
57#include "REMInternal.h"
58#include <VBox/vmm/vm.h>
59#include <VBox/vmm/uvm.h>
60#include <VBox/param.h>
61#include <VBox/err.h>
62
63#include <VBox/log.h>
64#include <iprt/alloca.h>
65#include <iprt/semaphore.h>
66#include <iprt/asm.h>
67#include <iprt/assert.h>
68#include <iprt/thread.h>
69#include <iprt/string.h>
70
71/* Don't wanna include everything. */
72extern void cpu_exec_init_all(uintptr_t tb_size);
73extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
74extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
75extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
76extern void tlb_flush_page(CPUX86State *env, target_ulong addr);
77extern void tlb_flush(CPUX86State *env, int flush_global);
78extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
79extern void sync_ldtr(CPUX86State *env1, int selector);
80
81#ifdef VBOX_STRICT
82ram_addr_t get_phys_page_offset(target_ulong addr);
83#endif
84
85
86/*********************************************************************************************************************************
87* Defined Constants And Macros *
88*********************************************************************************************************************************/
89
90/** Copy 80-bit fpu register at pSrc to pDst.
91 * This is probably faster than *calling* memcpy.
92 */
93#define REM_COPY_FPU_REG(pDst, pSrc) \
94 do { *(PX86FPUMMX)(pDst) = *(const X86FPUMMX *)(pSrc); } while (0)
95
96/** How remR3RunLoggingStep operates. */
97#define REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
98
99
100/** Selector flag shift between qemu and VBox.
101 * VBox shifts the qemu bits to the right. */
102#define SEL_FLAGS_SHIFT (8)
103/** Mask applied to the shifted qemu selector flags to get the attributes VBox
104 * (VT-x) needs. */
105#define SEL_FLAGS_SMASK UINT32_C(0x1F0FF)
106
107
108/*********************************************************************************************************************************
109* Internal Functions *
110*********************************************************************************************************************************/
111static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
112static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
113static DECLCALLBACK(int) remR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
114static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu);
115static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded);
116
117static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys);
118static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys);
119static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys);
120static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
121static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
122static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
123
124static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
125static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
126static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
127static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
128static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
129static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
130
131static void remR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
132static void remR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler);
133static void remR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
134
135
136/*********************************************************************************************************************************
137* Global Variables *
138*********************************************************************************************************************************/
139
140/** @todo Move stats to REM::s some rainy day we have nothing do to. */
141#ifdef VBOX_WITH_STATISTICS
142static STAMPROFILEADV gStatExecuteSingleInstr;
143static STAMPROFILEADV gStatCompilationQEmu;
144static STAMPROFILEADV gStatRunCodeQEmu;
145static STAMPROFILEADV gStatTotalTimeQEmu;
146static STAMPROFILEADV gStatTimers;
147static STAMPROFILEADV gStatTBLookup;
148static STAMPROFILEADV gStatIRQ;
149static STAMPROFILEADV gStatRawCheck;
150static STAMPROFILEADV gStatMemRead;
151static STAMPROFILEADV gStatMemWrite;
152static STAMPROFILE gStatGCPhys2HCVirt;
153static STAMCOUNTER gStatCpuGetTSC;
154static STAMCOUNTER gStatRefuseTFInhibit;
155static STAMCOUNTER gStatRefuseVM86;
156static STAMCOUNTER gStatRefusePaging;
157static STAMCOUNTER gStatRefusePAE;
158static STAMCOUNTER gStatRefuseIOPLNot0;
159static STAMCOUNTER gStatRefuseIF0;
160static STAMCOUNTER gStatRefuseCode16;
161static STAMCOUNTER gStatRefuseWP0;
162static STAMCOUNTER gStatRefuseRing1or2;
163static STAMCOUNTER gStatRefuseCanExecute;
164static STAMCOUNTER gaStatRefuseStale[6];
165static STAMCOUNTER gStatREMGDTChange;
166static STAMCOUNTER gStatREMIDTChange;
167static STAMCOUNTER gStatREMLDTRChange;
168static STAMCOUNTER gStatREMTRChange;
169static STAMCOUNTER gStatSelOutOfSync[6];
170static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
171static STAMCOUNTER gStatFlushTBs;
172#endif
173/* in exec.c */
174extern uint32_t tlb_flush_count;
175extern uint32_t tb_flush_count;
176extern uint32_t tb_phys_invalidate_count;
177
178/*
179 * Global stuff.
180 */
181
182/** MMIO read callbacks. */
183CPUReadMemoryFunc *g_apfnMMIORead[3] =
184{
185 remR3MMIOReadU8,
186 remR3MMIOReadU16,
187 remR3MMIOReadU32
188};
189
190/** MMIO write callbacks. */
191CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
192{
193 remR3MMIOWriteU8,
194 remR3MMIOWriteU16,
195 remR3MMIOWriteU32
196};
197
198/** Handler read callbacks. */
199CPUReadMemoryFunc *g_apfnHandlerRead[3] =
200{
201 remR3HandlerReadU8,
202 remR3HandlerReadU16,
203 remR3HandlerReadU32
204};
205
206/** Handler write callbacks. */
207CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
208{
209 remR3HandlerWriteU8,
210 remR3HandlerWriteU16,
211 remR3HandlerWriteU32
212};
213
214
215#ifdef VBOX_WITH_DEBUGGER
216/*
217 * Debugger commands.
218 */
219static FNDBGCCMD remR3CmdDisasEnableStepping;;
220
221/** '.remstep' arguments. */
222static const DBGCVARDESC g_aArgRemStep[] =
223{
224 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
225 { 0, ~0U, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
226};
227
228/** Command descriptors. */
229static const DBGCCMD g_aCmds[] =
230{
231 {
232 .pszCmd ="remstep",
233 .cArgsMin = 0,
234 .cArgsMax = 1,
235 .paArgDescs = &g_aArgRemStep[0],
236 .cArgDescs = RT_ELEMENTS(g_aArgRemStep),
237 .fFlags = 0,
238 .pfnHandler = remR3CmdDisasEnableStepping,
239 .pszSyntax = "[on/off]",
240 .pszDescription = "Enable or disable the single stepping with logged disassembly. "
241 "If no arguments show the current state."
242 }
243};
244#endif
245
246/** Prologue code, must be in lower 4G to simplify jumps to/from generated code.
247 * @todo huh??? That cannot be the case on the mac... So, this
248 * point is probably not valid any longer. */
249uint8_t *code_gen_prologue;
250
251
252/*********************************************************************************************************************************
253* Internal Functions *
254*********************************************************************************************************************************/
255void remAbort(int rc, const char *pszTip);
256extern int testmath(void);
257
258/* Put them here to avoid unused variable warning. */
259AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
260#if !defined(IPRT_NO_CRT) && (defined(RT_OS_LINUX) || defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS))
261//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
262/* Why did this have to be identical?? */
263AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
264#else
265AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
266#endif
267
268
269/**
270 * Initializes the REM.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM to operate on.
274 */
275REMR3DECL(int) REMR3Init(PVM pVM)
276{
277 PREMHANDLERNOTIFICATION pCur;
278 uint32_t u32Dummy;
279 int rc;
280 unsigned i;
281
282#ifdef VBOX_ENABLE_VBOXREM64
283 LogRel(("Using 64-bit aware REM\n"));
284#endif
285
286 /*
287 * Assert sanity.
288 */
289 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
290 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
291 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
292#if 0 /* just an annoyance at the moment. */
293#if defined(DEBUG) && !defined(RT_OS_SOLARIS) && !defined(RT_OS_FREEBSD) /// @todo fix the solaris and freebsd math stuff.
294 Assert(!testmath());
295#endif
296#endif
297
298 /*
299 * Init some internal data members.
300 */
301 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
302 pVM->rem.s.Env.pVM = pVM;
303#ifdef CPU_RAW_MODE_INIT
304 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
305#endif
306
307 /*
308 * Initialize the REM critical section.
309 *
310 * Note: This is not a 100% safe solution as updating the internal memory state while another VCPU
311 * is executing code could be dangerous. Taking the REM lock is not an option due to the danger of
312 * deadlocks. (mostly pgm vs rem locking)
313 */
314 rc = PDMR3CritSectInit(pVM, &pVM->rem.s.CritSectRegister, RT_SRC_POS, "REM-Register");
315 AssertRCReturn(rc, rc);
316
317 /* ctx. */
318 pVM->rem.s.pCtx = NULL; /* set when executing code. */
319 AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order has changed! REM depends on notification about ALL physical memory registrations\n"));
320
321 /* ignore all notifications */
322 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
323
324 code_gen_prologue = RTMemExecAlloc(_1K);
325 AssertLogRelReturn(code_gen_prologue, VERR_NO_MEMORY);
326
327 cpu_exec_init_all(0);
328
329 /*
330 * Init the recompiler.
331 */
332 if (!cpu_x86_init(&pVM->rem.s.Env, "vbox"))
333 {
334 AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
335 return VERR_GENERAL_FAILURE;
336 }
337 PVMCPU pVCpu = VMMGetCpu(pVM);
338 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
339 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
340
341 EMRemLock(pVM);
342 cpu_reset(&pVM->rem.s.Env);
343 EMRemUnlock(pVM);
344
345 /* allocate code buffer for single instruction emulation. */
346 pVM->rem.s.Env.cbCodeBuffer = 4096;
347 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
348 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
349
350 /* Finally, set the cpu_single_env global. */
351 cpu_single_env = &pVM->rem.s.Env;
352
353 /* Nothing is pending by default */
354 pVM->rem.s.uStateLoadPendingInterrupt = REM_NO_PENDING_IRQ;
355
356 /*
357 * Register ram types.
358 */
359 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(g_apfnMMIORead, g_apfnMMIOWrite, &pVM->rem.s.Env);
360 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
361 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
362 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
363 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
364
365 /* stop ignoring. */
366 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
367
368 /*
369 * Register the saved state data unit.
370 */
371 rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
372 NULL, NULL, NULL,
373 NULL, remR3Save, NULL,
374 NULL, remR3Load, remR3LoadDone);
375 if (RT_FAILURE(rc))
376 return rc;
377
378#ifdef VBOX_WITH_DEBUGGER
379 /*
380 * Debugger commands.
381 */
382 static bool fRegisteredCmds = false;
383 if (!fRegisteredCmds)
384 {
385 int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
386 if (RT_SUCCESS(rc))
387 fRegisteredCmds = true;
388 }
389#endif
390
391#ifdef VBOX_WITH_STATISTICS
392 /*
393 * Statistics.
394 */
395 STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
396 STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
397 STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
398 STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
399 STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer queue processing.");
400 STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling translation block lookup.");
401 STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling IRQ delivery.");
402 STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling remR3CanExecuteRaw calls.");
403 STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
404 STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
405 STAM_REG(pVM, &gStatGCPhys2HCVirt, STAMTYPE_PROFILE, "/PROF/REM/GCPhys2HCVirt", STAMUNIT_TICKS_PER_CALL, "Profiling memory conversion (PGMR3PhysTlbGCPhys2Ptr).");
406
407 STAM_REG(pVM, &gStatCpuGetTSC, STAMTYPE_COUNTER, "/REM/CpuGetTSC", STAMUNIT_OCCURENCES, "cpu_get_tsc calls");
408
409 STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
410 STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
411 STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
412 STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
413 STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
414 STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
415 STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
416 STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
417 STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
418 STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
419 STAM_REG(pVM, &gaStatRefuseStale[R_ES], STAMTYPE_COUNTER, "/REM/Refuse/StaleES", STAMUNIT_OCCURENCES, "Raw mode refused because of stale ES");
420 STAM_REG(pVM, &gaStatRefuseStale[R_CS], STAMTYPE_COUNTER, "/REM/Refuse/StaleCS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale CS");
421 STAM_REG(pVM, &gaStatRefuseStale[R_SS], STAMTYPE_COUNTER, "/REM/Refuse/StaleSS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale SS");
422 STAM_REG(pVM, &gaStatRefuseStale[R_DS], STAMTYPE_COUNTER, "/REM/Refuse/StaleDS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale DS");
423 STAM_REG(pVM, &gaStatRefuseStale[R_FS], STAMTYPE_COUNTER, "/REM/Refuse/StaleFS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale FS");
424 STAM_REG(pVM, &gaStatRefuseStale[R_GS], STAMTYPE_COUNTER, "/REM/Refuse/StaleGS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale GS");
425 STAM_REG(pVM, &gStatFlushTBs, STAMTYPE_COUNTER, "/REM/FlushTB", STAMUNIT_OCCURENCES, "Number of TB flushes");
426
427 STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
428 STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
429 STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
430 STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
431
432 STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
433 STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
434 STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
435 STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
436 STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
437 STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
438
439 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
440 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
441 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
442 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
443 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
444 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
445
446 STAM_REG(pVM, &pVM->rem.s.Env.StatTbFlush, STAMTYPE_PROFILE, "/REM/TbFlush", STAMUNIT_TICKS_PER_CALL, "profiling tb_flush().");
447#endif /* VBOX_WITH_STATISTICS */
448 AssertCompileMemberAlignment(CPUX86State, StatTbFlush, 4);
449 AssertCompileMemberAlignment(CPUX86State, StatTbFlush, 8);
450
451 STAM_REL_REG(pVM, &tb_flush_count, STAMTYPE_U32_RESET, "/REM/TbFlushCount", STAMUNIT_OCCURENCES, "tb_flush() calls");
452 STAM_REL_REG(pVM, &tb_phys_invalidate_count, STAMTYPE_U32_RESET, "/REM/TbPhysInvldCount", STAMUNIT_OCCURENCES, "tb_phys_invalidate() calls");
453 STAM_REL_REG(pVM, &tlb_flush_count, STAMTYPE_U32_RESET, "/REM/TlbFlushCount", STAMUNIT_OCCURENCES, "tlb_flush() calls");
454
455
456#ifdef DEBUG_ALL_LOGGING
457 loglevel = ~0;
458#endif
459
460 /*
461 * Init the handler notification lists.
462 */
463 pVM->rem.s.idxPendingList = UINT32_MAX;
464 pVM->rem.s.idxFreeList = 0;
465
466 for (i = 0 ; i < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications); i++)
467 {
468 pCur = &pVM->rem.s.aHandlerNotifications[i];
469 pCur->idxNext = i + 1;
470 pCur->idxSelf = i;
471 }
472 pCur->idxNext = UINT32_MAX; /* the last record. */
473
474 return rc;
475}
476
477
478/**
479 * Finalizes the REM initialization.
480 *
481 * This is called after all components, devices and drivers has
482 * been initialized. Its main purpose it to finish the RAM related
483 * initialization.
484 *
485 * @returns VBox status code.
486 *
487 * @param pVM The VM handle.
488 */
489REMR3DECL(int) REMR3InitFinalize(PVM pVM)
490{
491 int rc;
492
493 /*
494 * Ram size & dirty bit map.
495 */
496 Assert(!pVM->rem.s.fGCPhysLastRamFixed);
497 pVM->rem.s.fGCPhysLastRamFixed = true;
498#ifdef RT_STRICT
499 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, true /* fGuarded */);
500#else
501 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, false /* fGuarded */);
502#endif
503 return rc;
504}
505
506/**
507 * Initializes ram_list.phys_dirty and ram_list.phys_dirty_size.
508 *
509 * @returns VBox status code.
510 * @param pVM The VM handle.
511 * @param fGuarded Whether to guard the map.
512 */
513static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded)
514{
515 int rc = VINF_SUCCESS;
516 RTGCPHYS cb;
517
518 AssertLogRelReturn(QLIST_EMPTY(&ram_list.blocks), VERR_INTERNAL_ERROR_2);
519
520 cb = pVM->rem.s.GCPhysLastRam + 1;
521 AssertLogRelMsgReturn(cb > pVM->rem.s.GCPhysLastRam,
522 ("GCPhysLastRam=%RGp - out of range\n", pVM->rem.s.GCPhysLastRam),
523 VERR_OUT_OF_RANGE);
524
525 ram_list.phys_dirty_size = cb >> PAGE_SHIFT;
526 AssertMsg(((RTGCPHYS)ram_list.phys_dirty_size << PAGE_SHIFT) == cb, ("%RGp\n", cb));
527
528 if (!fGuarded)
529 {
530 ram_list.phys_dirty = MMR3HeapAlloc(pVM, MM_TAG_REM, ram_list.phys_dirty_size);
531 AssertLogRelMsgReturn(ram_list.phys_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", ram_list.phys_dirty_size), VERR_NO_MEMORY);
532 }
533 else
534 {
535 /*
536 * Fill it up the nearest 4GB RAM and leave at least _64KB of guard after it.
537 */
538 uint32_t cbBitmapAligned = RT_ALIGN_32(ram_list.phys_dirty_size, PAGE_SIZE);
539 uint32_t cbBitmapFull = RT_ALIGN_32(ram_list.phys_dirty_size, (_4G >> PAGE_SHIFT));
540 if (cbBitmapFull == cbBitmapAligned)
541 cbBitmapFull += _4G >> PAGE_SHIFT;
542 else if (cbBitmapFull - cbBitmapAligned < _64K)
543 cbBitmapFull += _64K;
544
545 ram_list.phys_dirty = RTMemPageAlloc(cbBitmapFull);
546 AssertLogRelMsgReturn(ram_list.phys_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", cbBitmapFull), VERR_NO_MEMORY);
547
548 rc = RTMemProtect(ram_list.phys_dirty + cbBitmapAligned, cbBitmapFull - cbBitmapAligned, RTMEM_PROT_NONE);
549 if (RT_FAILURE(rc))
550 {
551 RTMemPageFree(ram_list.phys_dirty, cbBitmapFull);
552 AssertLogRelRCReturn(rc, rc);
553 }
554
555 ram_list.phys_dirty += cbBitmapAligned - ram_list.phys_dirty_size;
556 }
557
558 /* initialize it. */
559 memset(ram_list.phys_dirty, 0xff, ram_list.phys_dirty_size);
560 return rc;
561}
562
563
564/**
565 * Terminates the REM.
566 *
567 * Termination means cleaning up and freeing all resources,
568 * the VM it self is at this point powered off or suspended.
569 *
570 * @returns VBox status code.
571 * @param pVM The VM to operate on.
572 */
573REMR3DECL(int) REMR3Term(PVM pVM)
574{
575 /*
576 * Statistics.
577 */
578 STAMR3Deregister(pVM->pUVM, "/PROF/REM/*");
579 STAMR3Deregister(pVM->pUVM, "/REM/*");
580
581 return VINF_SUCCESS;
582}
583
584
585/**
586 * The VM is being reset.
587 *
588 * For the REM component this means to call the cpu_reset() and
589 * reinitialize some state variables.
590 *
591 * @param pVM VM handle.
592 */
593REMR3DECL(void) REMR3Reset(PVM pVM)
594{
595 EMRemLock(pVM); /* Only pro forma, we're in a rendezvous. */
596
597 /*
598 * Reset the REM cpu.
599 */
600 Assert(pVM->rem.s.cIgnoreAll == 0);
601 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
602 cpu_reset(&pVM->rem.s.Env);
603 pVM->rem.s.cInvalidatedPages = 0;
604 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
605 Assert(pVM->rem.s.cIgnoreAll == 0);
606
607 /* Clear raw ring 0 init state */
608 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
609
610 /* Flush the TBs the next time we execute code here. */
611 pVM->rem.s.fFlushTBs = true;
612
613 EMRemUnlock(pVM);
614}
615
616
617/**
618 * Execute state save operation.
619 *
620 * @returns VBox status code.
621 * @param pVM VM Handle.
622 * @param pSSM SSM operation handle.
623 */
624static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
625{
626 PREM pRem = &pVM->rem.s;
627
628 /*
629 * Save the required CPU Env bits.
630 * (Not much because we're never in REM when doing the save.)
631 */
632 LogFlow(("remR3Save:\n"));
633 Assert(!pRem->fInREM);
634 SSMR3PutU32(pSSM, pRem->Env.hflags);
635 SSMR3PutU32(pSSM, ~0); /* separator */
636
637 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
638 SSMR3PutU32(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
639 SSMR3PutU32(pSSM, REM_NO_PENDING_IRQ);
640
641 return SSMR3PutU32(pSSM, ~0); /* terminator */
642}
643
644
645/**
646 * Execute state load operation.
647 *
648 * @returns VBox status code.
649 * @param pVM VM Handle.
650 * @param pSSM SSM operation handle.
651 * @param uVersion Data layout version.
652 * @param uPass The data pass.
653 */
654static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
655{
656 uint32_t u32Dummy;
657 uint32_t fRawRing0 = false;
658 uint32_t u32Sep;
659 uint32_t i;
660 int rc;
661 PREM pRem;
662
663 LogFlow(("remR3Load:\n"));
664 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
665
666 /*
667 * Validate version.
668 */
669 if ( uVersion != REM_SAVED_STATE_VERSION
670 && uVersion != REM_SAVED_STATE_VERSION_VER1_6)
671 {
672 AssertMsgFailed(("remR3Load: Invalid version uVersion=%d!\n", uVersion));
673 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
674 }
675
676 /*
677 * Do a reset to be on the safe side...
678 */
679 REMR3Reset(pVM);
680
681 /*
682 * Ignore all ignorable notifications.
683 * (Not doing this will cause serious trouble.)
684 */
685 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
686
687 /*
688 * Load the required CPU Env bits.
689 * (Not much because we're never in REM when doing the save.)
690 */
691 pRem = &pVM->rem.s;
692 Assert(!pRem->fInREM);
693 SSMR3GetU32(pSSM, &pRem->Env.hflags);
694 if (uVersion == REM_SAVED_STATE_VERSION_VER1_6)
695 {
696 /* Redundant REM CPU state has to be loaded, but can be ignored. */
697 CPUX86State_Ver16 temp;
698 SSMR3GetMem(pSSM, &temp, RT_OFFSETOF(CPUX86State_Ver16, jmp_env));
699 }
700
701 rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
702 if (RT_FAILURE(rc))
703 return rc;
704 if (u32Sep != ~0U)
705 {
706 AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
707 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
708 }
709
710 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
711 SSMR3GetUInt(pSSM, &fRawRing0);
712 if (fRawRing0)
713 pRem->Env.state |= CPU_RAW_RING0;
714
715 if (uVersion == REM_SAVED_STATE_VERSION_VER1_6)
716 {
717 /*
718 * Load the REM stuff.
719 */
720 /** @todo r=bird: We should just drop all these items, restoring doesn't make
721 * sense. */
722 rc = SSMR3GetU32(pSSM, (uint32_t *)&pRem->cInvalidatedPages);
723 if (RT_FAILURE(rc))
724 return rc;
725 if (pRem->cInvalidatedPages > RT_ELEMENTS(pRem->aGCPtrInvalidatedPages))
726 {
727 AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
728 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
729 }
730 for (i = 0; i < pRem->cInvalidatedPages; i++)
731 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
732 }
733
734 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.uStateLoadPendingInterrupt);
735 AssertRCReturn(rc, rc);
736 AssertLogRelMsgReturn( pVM->rem.s.uStateLoadPendingInterrupt == REM_NO_PENDING_IRQ
737 || pVM->rem.s.uStateLoadPendingInterrupt < 256,
738 ("uStateLoadPendingInterrupt=%#x\n", pVM->rem.s.uStateLoadPendingInterrupt),
739 VERR_SSM_UNEXPECTED_DATA);
740
741 /* check the terminator. */
742 rc = SSMR3GetU32(pSSM, &u32Sep);
743 if (RT_FAILURE(rc))
744 return rc;
745 if (u32Sep != ~0U)
746 {
747 AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
748 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
749 }
750
751 /*
752 * Get the CPUID features.
753 */
754 PVMCPU pVCpu = VMMGetCpu(pVM);
755 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
756 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
757
758 /*
759 * Stop ignoring ignorable notifications.
760 */
761 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
762
763 /*
764 * Sync the whole CPU state when executing code in the recompiler.
765 */
766 for (i = 0; i < pVM->cCpus; i++)
767 {
768 PVMCPU pVCpu = &pVM->aCpus[i];
769 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
770 }
771 return VINF_SUCCESS;
772}
773
774
775/**
776 * @callback_method_impl{FNSSMINTLOADDONE,
777 * For pushing misdesigned pending-interrupt mess to TRPM where it belongs. }
778 */
779static DECLCALLBACK(int) remR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
780{
781 if (pVM->rem.s.uStateLoadPendingInterrupt != REM_NO_PENDING_IRQ)
782 {
783 int rc = TRPMAssertTrap(&pVM->aCpus[0], pVM->rem.s.uStateLoadPendingInterrupt, TRPM_HARDWARE_INT);
784 AssertLogRelMsgReturn(rc, ("uStateLoadPendingInterrupt=%#x rc=%Rrc\n", pVM->rem.s.uStateLoadPendingInterrupt, rc), rc);
785 pVM->rem.s.uStateLoadPendingInterrupt = REM_NO_PENDING_IRQ;
786 }
787 return VINF_SUCCESS;
788}
789
790
791#undef LOG_GROUP
792#define LOG_GROUP LOG_GROUP_REM_RUN
793
794/**
795 * Single steps an instruction in recompiled mode.
796 *
797 * Before calling this function the REM state needs to be in sync with
798 * the VM. Call REMR3State() to perform the sync. It's only necessary
799 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
800 * and after calling REMR3StateBack().
801 *
802 * @returns VBox status code.
803 *
804 * @param pVM VM Handle.
805 * @param pVCpu VMCPU Handle.
806 */
807REMR3DECL(int) REMR3Step(PVM pVM, PVMCPU pVCpu)
808{
809 int rc, interrupt_request;
810 RTGCPTR GCPtrPC;
811 bool fBp;
812
813 /*
814 * Lock the REM - we don't wanna have anyone interrupting us
815 * while stepping - and enabled single stepping. We also ignore
816 * pending interrupts and suchlike.
817 */
818 interrupt_request = pVM->rem.s.Env.interrupt_request;
819 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB | CPU_INTERRUPT_EXTERNAL_TIMER)));
820 pVM->rem.s.Env.interrupt_request = 0;
821 cpu_single_step(&pVM->rem.s.Env, 1);
822
823 /*
824 * If we're standing at a breakpoint, that have to be disabled before we start stepping.
825 */
826 GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
827 fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC, BP_GDB);
828
829 /*
830 * Execute and handle the return code.
831 * We execute without enabling the cpu tick, so on success we'll
832 * just flip it on and off to make sure it moves
833 */
834 rc = cpu_exec(&pVM->rem.s.Env);
835 if (rc == EXCP_DEBUG)
836 {
837 TMR3NotifyResume(pVM, pVCpu);
838 TMR3NotifySuspend(pVM, pVCpu);
839 rc = VINF_EM_DBG_STEPPED;
840 }
841 else
842 {
843 switch (rc)
844 {
845 case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
846 case EXCP_HLT:
847 case EXCP_HALTED: rc = VINF_EM_HALT; break;
848 case EXCP_RC:
849 rc = pVM->rem.s.rc;
850 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
851 break;
852 case EXCP_EXECUTE_RAW:
853 case EXCP_EXECUTE_HM:
854 /** @todo is it correct? No! */
855 rc = VINF_SUCCESS;
856 break;
857 default:
858 AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
859 rc = VERR_INTERNAL_ERROR;
860 break;
861 }
862 }
863
864 /*
865 * Restore the stuff we changed to prevent interruption.
866 * Unlock the REM.
867 */
868 if (fBp)
869 {
870 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC, BP_GDB, NULL);
871 Assert(rc2 == 0); NOREF(rc2);
872 }
873 cpu_single_step(&pVM->rem.s.Env, 0);
874 pVM->rem.s.Env.interrupt_request = interrupt_request;
875
876 return rc;
877}
878
879
880/**
881 * Set a breakpoint using the REM facilities.
882 *
883 * @returns VBox status code.
884 * @param pVM The VM handle.
885 * @param Address The breakpoint address.
886 * @thread The emulation thread.
887 */
888REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
889{
890 VM_ASSERT_EMT(pVM);
891 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address, BP_GDB, NULL))
892 {
893 LogFlow(("REMR3BreakpointSet: Address=%RGv\n", Address));
894 return VINF_SUCCESS;
895 }
896 LogFlow(("REMR3BreakpointSet: Address=%RGv - failed!\n", Address));
897 return VERR_REM_NO_MORE_BP_SLOTS;
898}
899
900
901/**
902 * Clears a breakpoint set by REMR3BreakpointSet().
903 *
904 * @returns VBox status code.
905 * @param pVM The VM handle.
906 * @param Address The breakpoint address.
907 * @thread The emulation thread.
908 */
909REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
910{
911 VM_ASSERT_EMT(pVM);
912 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address, BP_GDB))
913 {
914 LogFlow(("REMR3BreakpointClear: Address=%RGv\n", Address));
915 return VINF_SUCCESS;
916 }
917 LogFlow(("REMR3BreakpointClear: Address=%RGv - not found!\n", Address));
918 return VERR_REM_BP_NOT_FOUND;
919}
920
921
922/**
923 * Emulate an instruction.
924 *
925 * This function executes one instruction without letting anyone
926 * interrupt it. This is intended for being called while being in
927 * raw mode and thus will take care of all the state syncing between
928 * REM and the rest.
929 *
930 * @returns VBox status code.
931 * @param pVM VM handle.
932 * @param pVCpu VMCPU Handle.
933 */
934REMR3DECL(int) REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu)
935{
936 bool fFlushTBs;
937
938 int rc, rc2;
939 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
940
941 /* Make sure this flag is set; we might never execute remR3CanExecuteRaw in the AMD-V case.
942 * CPU_RAW_HM makes sure we never execute interrupt handlers in the recompiler.
943 */
944 if (HMIsEnabled(pVM))
945 pVM->rem.s.Env.state |= CPU_RAW_HM;
946
947 /* Skip the TB flush as that's rather expensive and not necessary for single instruction emulation. */
948 fFlushTBs = pVM->rem.s.fFlushTBs;
949 pVM->rem.s.fFlushTBs = false;
950
951 /*
952 * Sync the state and enable single instruction / single stepping.
953 */
954 rc = REMR3State(pVM, pVCpu);
955 pVM->rem.s.fFlushTBs = fFlushTBs;
956 if (RT_SUCCESS(rc))
957 {
958 int interrupt_request = pVM->rem.s.Env.interrupt_request;
959 Assert(!( interrupt_request
960 & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD
961 | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB | CPU_INTERRUPT_EXTERNAL_TIMER
962 | CPU_INTERRUPT_EXTERNAL_DMA)));
963#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
964 cpu_single_step(&pVM->rem.s.Env, 0);
965#endif
966 Assert(!pVM->rem.s.Env.singlestep_enabled);
967
968 /*
969 * Now we set the execute single instruction flag and enter the cpu_exec loop.
970 */
971 TMNotifyStartOfExecution(pVCpu);
972 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
973 rc = cpu_exec(&pVM->rem.s.Env);
974 TMNotifyEndOfExecution(pVCpu);
975 switch (rc)
976 {
977 /*
978 * Executed without anything out of the way happening.
979 */
980 case EXCP_SINGLE_INSTR:
981 rc = VINF_EM_RESCHEDULE;
982 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
983 break;
984
985 /*
986 * If we take a trap or start servicing a pending interrupt, we might end up here.
987 * (Timer thread or some other thread wishing EMT's attention.)
988 */
989 case EXCP_INTERRUPT:
990 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
991 rc = VINF_EM_RESCHEDULE;
992 break;
993
994 /*
995 * Single step, we assume!
996 * If there was a breakpoint there we're fucked now.
997 */
998 case EXCP_DEBUG:
999 if (pVM->rem.s.Env.watchpoint_hit)
1000 {
1001 /** @todo deal with watchpoints */
1002 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1003 rc = VINF_EM_DBG_BREAKPOINT;
1004 }
1005 else
1006 {
1007 CPUBreakpoint *pBP;
1008 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1009 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1010 if (pBP->pc == GCPtrPC)
1011 break;
1012 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1013 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1014 }
1015 break;
1016
1017 /*
1018 * hlt instruction.
1019 */
1020 case EXCP_HLT:
1021 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
1022 rc = VINF_EM_HALT;
1023 break;
1024
1025 /*
1026 * The VM has halted.
1027 */
1028 case EXCP_HALTED:
1029 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
1030 rc = VINF_EM_HALT;
1031 break;
1032
1033 /*
1034 * Switch to RAW-mode.
1035 */
1036 case EXCP_EXECUTE_RAW:
1037 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1038 rc = VINF_EM_RESCHEDULE_RAW;
1039 break;
1040
1041 /*
1042 * Switch to hardware accelerated RAW-mode.
1043 */
1044 case EXCP_EXECUTE_HM:
1045 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HM\n"));
1046 rc = VINF_EM_RESCHEDULE_HM;
1047 break;
1048
1049 /*
1050 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1051 */
1052 case EXCP_RC:
1053 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
1054 rc = pVM->rem.s.rc;
1055 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1056 break;
1057
1058 /*
1059 * Figure out the rest when they arrive....
1060 */
1061 default:
1062 AssertMsgFailed(("rc=%d\n", rc));
1063 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
1064 rc = VINF_EM_RESCHEDULE;
1065 break;
1066 }
1067
1068 /*
1069 * Switch back the state.
1070 */
1071 pVM->rem.s.Env.interrupt_request = interrupt_request;
1072 rc2 = REMR3StateBack(pVM, pVCpu);
1073 AssertRC(rc2);
1074 }
1075
1076 Log2(("REMR3EmulateInstruction: returns %Rrc (cs:eip=%04x:%RGv)\n",
1077 rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1078 return rc;
1079}
1080
1081
1082/**
1083 * Used by REMR3Run to handle the case where CPU_EMULATE_SINGLE_STEP is set.
1084 *
1085 * @returns VBox status code.
1086 *
1087 * @param pVM The VM handle.
1088 * @param pVCpu The Virtual CPU handle.
1089 */
1090static int remR3RunLoggingStep(PVM pVM, PVMCPU pVCpu)
1091{
1092 int rc;
1093
1094 Assert(pVM->rem.s.fInREM);
1095#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1096 cpu_single_step(&pVM->rem.s.Env, 1);
1097#else
1098 Assert(!pVM->rem.s.Env.singlestep_enabled);
1099#endif
1100
1101 /*
1102 * Now we set the execute single instruction flag and enter the cpu_exec loop.
1103 */
1104 for (;;)
1105 {
1106 char szBuf[256];
1107
1108 /*
1109 * Log the current registers state and instruction.
1110 */
1111 remR3StateUpdate(pVM, pVCpu);
1112 DBGFR3Info(pVM->pUVM, "cpumguest", NULL, NULL);
1113 szBuf[0] = '\0';
1114 rc = DBGFR3DisasInstrEx(pVM->pUVM,
1115 pVCpu->idCpu,
1116 0, /* Sel */ 0, /* GCPtr */
1117 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
1118 szBuf,
1119 sizeof(szBuf),
1120 NULL);
1121 if (RT_FAILURE(rc))
1122 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrEx failed with rc=%Rrc\n", rc);
1123 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
1124
1125 /*
1126 * Execute the instruction.
1127 */
1128 TMNotifyStartOfExecution(pVCpu);
1129
1130 if ( pVM->rem.s.Env.exception_index < 0
1131 || pVM->rem.s.Env.exception_index > 256)
1132 pVM->rem.s.Env.exception_index = -1; /** @todo We need to do similar stuff elsewhere, I think. */
1133
1134#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1135 pVM->rem.s.Env.interrupt_request = 0;
1136#else
1137 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
1138#endif
1139 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1140 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
1141 RTLogPrintf("remR3RunLoggingStep: interrupt_request=%#x halted=%d exception_index=%#x\n",
1142 pVM->rem.s.Env.interrupt_request,
1143 pVM->rem.s.Env.halted,
1144 pVM->rem.s.Env.exception_index
1145 );
1146
1147 rc = cpu_exec(&pVM->rem.s.Env);
1148
1149 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> %#x interrupt_request=%#x halted=%d exception_index=%#x\n", rc,
1150 pVM->rem.s.Env.interrupt_request,
1151 pVM->rem.s.Env.halted,
1152 pVM->rem.s.Env.exception_index
1153 );
1154
1155 TMNotifyEndOfExecution(pVCpu);
1156
1157 switch (rc)
1158 {
1159#ifndef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1160 /*
1161 * The normal exit.
1162 */
1163 case EXCP_SINGLE_INSTR:
1164 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1165 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1166 continue;
1167 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n",
1168 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1169 rc = VINF_SUCCESS;
1170 break;
1171
1172#else
1173 /*
1174 * The normal exit, check for breakpoints at PC just to be sure.
1175 */
1176#endif
1177 case EXCP_DEBUG:
1178 if (pVM->rem.s.Env.watchpoint_hit)
1179 {
1180 /** @todo deal with watchpoints */
1181 Log2(("remR3RunLoggingStep: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1182 rc = VINF_EM_DBG_BREAKPOINT;
1183 }
1184 else
1185 {
1186 CPUBreakpoint *pBP;
1187 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1188 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1189 if (pBP->pc == GCPtrPC)
1190 break;
1191 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1192 Log2(("remR3RunLoggingStep: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1193 }
1194#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1195 if (rc == VINF_EM_DBG_STEPPED)
1196 {
1197 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1198 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1199 continue;
1200
1201 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n",
1202 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1203 rc = VINF_SUCCESS;
1204 }
1205#endif
1206 break;
1207
1208 /*
1209 * If we take a trap or start servicing a pending interrupt, we might end up here.
1210 * (Timer thread or some other thread wishing EMT's attention.)
1211 */
1212 case EXCP_INTERRUPT:
1213 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_INTERRUPT rc=VINF_SUCCESS\n");
1214 rc = VINF_SUCCESS;
1215 break;
1216
1217 /*
1218 * hlt instruction.
1219 */
1220 case EXCP_HLT:
1221 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_HLT rc=VINF_EM_HALT\n");
1222 rc = VINF_EM_HALT;
1223 break;
1224
1225 /*
1226 * The VM has halted.
1227 */
1228 case EXCP_HALTED:
1229 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_HALTED rc=VINF_EM_HALT\n");
1230 rc = VINF_EM_HALT;
1231 break;
1232
1233 /*
1234 * Switch to RAW-mode.
1235 */
1236 case EXCP_EXECUTE_RAW:
1237 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_EXECUTE_RAW rc=VINF_EM_RESCHEDULE_RAW\n");
1238 rc = VINF_EM_RESCHEDULE_RAW;
1239 break;
1240
1241 /*
1242 * Switch to hardware accelerated RAW-mode.
1243 */
1244 case EXCP_EXECUTE_HM:
1245 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_EXECUTE_HM rc=VINF_EM_RESCHEDULE_HM\n");
1246 rc = VINF_EM_RESCHEDULE_HM;
1247 break;
1248
1249 /*
1250 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1251 */
1252 case EXCP_RC:
1253 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc);
1254 rc = pVM->rem.s.rc;
1255 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1256 break;
1257
1258 /*
1259 * Figure out the rest when they arrive....
1260 */
1261 default:
1262 AssertMsgFailed(("rc=%d\n", rc));
1263 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> %d rc=VINF_EM_RESCHEDULE\n", rc);
1264 rc = VINF_EM_RESCHEDULE;
1265 break;
1266 }
1267 break;
1268 }
1269
1270#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1271// cpu_single_step(&pVM->rem.s.Env, 0);
1272#else
1273 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_SINGLE_INSTR | CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT);
1274#endif
1275 return rc;
1276}
1277
1278
1279/**
1280 * Runs code in recompiled mode.
1281 *
1282 * Before calling this function the REM state needs to be in sync with
1283 * the VM. Call REMR3State() to perform the sync. It's only necessary
1284 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
1285 * and after calling REMR3StateBack().
1286 *
1287 * @returns VBox status code.
1288 *
1289 * @param pVM VM Handle.
1290 * @param pVCpu VMCPU Handle.
1291 */
1292REMR3DECL(int) REMR3Run(PVM pVM, PVMCPU pVCpu)
1293{
1294 int rc;
1295
1296 if (RT_UNLIKELY(pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP))
1297 return remR3RunLoggingStep(pVM, pVCpu);
1298
1299 Assert(pVM->rem.s.fInREM);
1300 Log2(("REMR3Run: (cs:eip=%04x:%RGv)\n", pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1301
1302 TMNotifyStartOfExecution(pVCpu);
1303 rc = cpu_exec(&pVM->rem.s.Env);
1304 TMNotifyEndOfExecution(pVCpu);
1305 switch (rc)
1306 {
1307 /*
1308 * This happens when the execution was interrupted
1309 * by an external event, like pending timers.
1310 */
1311 case EXCP_INTERRUPT:
1312 Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
1313 rc = VINF_SUCCESS;
1314 break;
1315
1316 /*
1317 * hlt instruction.
1318 */
1319 case EXCP_HLT:
1320 Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
1321 rc = VINF_EM_HALT;
1322 break;
1323
1324 /*
1325 * The VM has halted.
1326 */
1327 case EXCP_HALTED:
1328 Log2(("REMR3Run: cpu_exec -> EXCP_HALTED\n"));
1329 rc = VINF_EM_HALT;
1330 break;
1331
1332 /*
1333 * Breakpoint/single step.
1334 */
1335 case EXCP_DEBUG:
1336 if (pVM->rem.s.Env.watchpoint_hit)
1337 {
1338 /** @todo deal with watchpoints */
1339 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1340 rc = VINF_EM_DBG_BREAKPOINT;
1341 }
1342 else
1343 {
1344 CPUBreakpoint *pBP;
1345 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1346 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1347 if (pBP->pc == GCPtrPC)
1348 break;
1349 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1350 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1351 }
1352 break;
1353
1354 /*
1355 * Switch to RAW-mode.
1356 */
1357 case EXCP_EXECUTE_RAW:
1358 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW pc=%RGv\n", pVM->rem.s.Env.eip));
1359 rc = VINF_EM_RESCHEDULE_RAW;
1360 break;
1361
1362 /*
1363 * Switch to hardware accelerated RAW-mode.
1364 */
1365 case EXCP_EXECUTE_HM:
1366 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_HM\n"));
1367 rc = VINF_EM_RESCHEDULE_HM;
1368 break;
1369
1370 /*
1371 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1372 */
1373 case EXCP_RC:
1374 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1375 rc = pVM->rem.s.rc;
1376 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1377 break;
1378
1379 /*
1380 * Figure out the rest when they arrive....
1381 */
1382 default:
1383 AssertMsgFailed(("rc=%d\n", rc));
1384 Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1385 rc = VINF_SUCCESS;
1386 break;
1387 }
1388
1389 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%RGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1390 return rc;
1391}
1392
1393
1394/**
1395 * Check if the cpu state is suitable for Raw execution.
1396 *
1397 * @returns true if RAW/HWACC mode is ok, false if we should stay in REM.
1398 *
1399 * @param env The CPU env struct.
1400 * @param eip The EIP to check this for (might differ from env->eip).
1401 * @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1402 * @param piException Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1403 *
1404 * @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1405 */
1406bool remR3CanExecuteRaw(CPUX86State *env, RTGCPTR eip, unsigned fFlags, int *piException)
1407{
1408 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1409 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1410 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1411 uint32_t u32CR0;
1412
1413#ifdef IEM_VERIFICATION_MODE
1414 return false;
1415#endif
1416
1417 /* Update counter. */
1418 env->pVM->rem.s.cCanExecuteRaw++;
1419
1420 /* Never when single stepping+logging guest code. */
1421 if (env->state & CPU_EMULATE_SINGLE_STEP)
1422 return false;
1423
1424 if (HMIsEnabled(env->pVM))
1425 {
1426#ifdef RT_OS_WINDOWS
1427 PCPUMCTX pCtx = alloca(sizeof(*pCtx));
1428#else
1429 CPUMCTX Ctx;
1430 PCPUMCTX pCtx = &Ctx;
1431#endif
1432
1433 env->state |= CPU_RAW_HM;
1434
1435 /*
1436 * The simple check first...
1437 */
1438 if (!EMIsHwVirtExecutionEnabled(env->pVM))
1439 return false;
1440
1441 /*
1442 * Create partial context for HMR3CanExecuteGuest
1443 */
1444 pCtx->cr0 = env->cr[0];
1445 pCtx->cr3 = env->cr[3];
1446 pCtx->cr4 = env->cr[4];
1447
1448 pCtx->tr.Sel = env->tr.selector;
1449 pCtx->tr.ValidSel = env->tr.selector;
1450 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1451 pCtx->tr.u64Base = env->tr.base;
1452 pCtx->tr.u32Limit = env->tr.limit;
1453 pCtx->tr.Attr.u = (env->tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1454
1455 pCtx->ldtr.Sel = env->ldt.selector;
1456 pCtx->ldtr.ValidSel = env->ldt.selector;
1457 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1458 pCtx->ldtr.u64Base = env->ldt.base;
1459 pCtx->ldtr.u32Limit = env->ldt.limit;
1460 pCtx->ldtr.Attr.u = (env->ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1461
1462 pCtx->idtr.cbIdt = env->idt.limit;
1463 pCtx->idtr.pIdt = env->idt.base;
1464
1465 pCtx->gdtr.cbGdt = env->gdt.limit;
1466 pCtx->gdtr.pGdt = env->gdt.base;
1467
1468 pCtx->rsp = env->regs[R_ESP];
1469 pCtx->rip = env->eip;
1470
1471 pCtx->eflags.u32 = env->eflags;
1472
1473 pCtx->cs.Sel = env->segs[R_CS].selector;
1474 pCtx->cs.ValidSel = env->segs[R_CS].selector;
1475 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1476 pCtx->cs.u64Base = env->segs[R_CS].base;
1477 pCtx->cs.u32Limit = env->segs[R_CS].limit;
1478 pCtx->cs.Attr.u = (env->segs[R_CS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1479
1480 pCtx->ds.Sel = env->segs[R_DS].selector;
1481 pCtx->ds.ValidSel = env->segs[R_DS].selector;
1482 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1483 pCtx->ds.u64Base = env->segs[R_DS].base;
1484 pCtx->ds.u32Limit = env->segs[R_DS].limit;
1485 pCtx->ds.Attr.u = (env->segs[R_DS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1486
1487 pCtx->es.Sel = env->segs[R_ES].selector;
1488 pCtx->es.ValidSel = env->segs[R_ES].selector;
1489 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1490 pCtx->es.u64Base = env->segs[R_ES].base;
1491 pCtx->es.u32Limit = env->segs[R_ES].limit;
1492 pCtx->es.Attr.u = (env->segs[R_ES].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1493
1494 pCtx->fs.Sel = env->segs[R_FS].selector;
1495 pCtx->fs.ValidSel = env->segs[R_FS].selector;
1496 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1497 pCtx->fs.u64Base = env->segs[R_FS].base;
1498 pCtx->fs.u32Limit = env->segs[R_FS].limit;
1499 pCtx->fs.Attr.u = (env->segs[R_FS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1500
1501 pCtx->gs.Sel = env->segs[R_GS].selector;
1502 pCtx->gs.ValidSel = env->segs[R_GS].selector;
1503 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1504 pCtx->gs.u64Base = env->segs[R_GS].base;
1505 pCtx->gs.u32Limit = env->segs[R_GS].limit;
1506 pCtx->gs.Attr.u = (env->segs[R_GS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1507
1508 pCtx->ss.Sel = env->segs[R_SS].selector;
1509 pCtx->ss.ValidSel = env->segs[R_SS].selector;
1510 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1511 pCtx->ss.u64Base = env->segs[R_SS].base;
1512 pCtx->ss.u32Limit = env->segs[R_SS].limit;
1513 pCtx->ss.Attr.u = (env->segs[R_SS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1514
1515 pCtx->msrEFER = env->efer;
1516
1517 /* Hardware accelerated raw-mode:
1518 *
1519 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1520 */
1521 if (HMR3CanExecuteGuest(env->pVM, pCtx) == true)
1522 {
1523 *piException = EXCP_EXECUTE_HM;
1524 return true;
1525 }
1526 return false;
1527 }
1528
1529 /*
1530 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1531 * or 32 bits protected mode ring 0 code
1532 *
1533 * The tests are ordered by the likelihood of being true during normal execution.
1534 */
1535 if (fFlags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))
1536 {
1537 STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1538 Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1539 return false;
1540 }
1541
1542#ifndef VBOX_RAW_V86
1543 if (fFlags & VM_MASK) {
1544 STAM_COUNTER_INC(&gStatRefuseVM86);
1545 Log2(("raw mode refused: VM_MASK\n"));
1546 return false;
1547 }
1548#endif
1549
1550 if (env->state & CPU_EMULATE_SINGLE_INSTR)
1551 {
1552#ifndef DEBUG_bird
1553 Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1554#endif
1555 return false;
1556 }
1557
1558 if (env->singlestep_enabled)
1559 {
1560 //Log2(("raw mode refused: Single step\n"));
1561 return false;
1562 }
1563
1564 if (!QTAILQ_EMPTY(&env->breakpoints))
1565 {
1566 //Log2(("raw mode refused: Breakpoints\n"));
1567 return false;
1568 }
1569
1570 if (!QTAILQ_EMPTY(&env->watchpoints))
1571 {
1572 //Log2(("raw mode refused: Watchpoints\n"));
1573 return false;
1574 }
1575
1576 u32CR0 = env->cr[0];
1577 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1578 {
1579 STAM_COUNTER_INC(&gStatRefusePaging);
1580 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1581 return false;
1582 }
1583
1584 if (env->cr[4] & CR4_PAE_MASK)
1585 {
1586 if (!(env->cpuid_features & X86_CPUID_FEATURE_EDX_PAE))
1587 {
1588 STAM_COUNTER_INC(&gStatRefusePAE);
1589 return false;
1590 }
1591 }
1592
1593 if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1594 {
1595 if (!EMIsRawRing3Enabled(env->pVM))
1596 return false;
1597
1598 if (!(env->eflags & IF_MASK))
1599 {
1600 STAM_COUNTER_INC(&gStatRefuseIF0);
1601 Log2(("raw mode refused: IF (RawR3)\n"));
1602 return false;
1603 }
1604
1605 if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1606 {
1607 STAM_COUNTER_INC(&gStatRefuseWP0);
1608 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1609 return false;
1610 }
1611 }
1612 else
1613 {
1614 if (!EMIsRawRing0Enabled(env->pVM))
1615 return false;
1616
1617 // Let's start with pure 32 bits ring 0 code first
1618 if ((fFlags & (HF_SS32_MASK | HF_CS32_MASK)) != (HF_SS32_MASK | HF_CS32_MASK))
1619 {
1620 STAM_COUNTER_INC(&gStatRefuseCode16);
1621 Log2(("raw r0 mode refused: HF_[S|C]S32_MASK fFlags=%#x\n", fFlags));
1622 return false;
1623 }
1624
1625 if (EMIsRawRing1Enabled(env->pVM))
1626 {
1627 /* Only ring 0 and 1 supervisor code. */
1628 if (((fFlags >> HF_CPL_SHIFT) & 3) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1629 {
1630 Log2(("raw r0 mode refused: CPL %d\n", (fFlags >> HF_CPL_SHIFT) & 3));
1631 return false;
1632 }
1633 }
1634 /* Only R0. */
1635 else if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1636 {
1637 STAM_COUNTER_INC(&gStatRefuseRing1or2);
1638 Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1639 return false;
1640 }
1641
1642 if (!(u32CR0 & CR0_WP_MASK))
1643 {
1644 STAM_COUNTER_INC(&gStatRefuseWP0);
1645 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1646 return false;
1647 }
1648
1649#ifdef VBOX_WITH_RAW_MODE
1650 if (PATMIsPatchGCAddr(env->pVM, eip))
1651 {
1652 Log2(("raw r0 mode forced: patch code\n"));
1653 *piException = EXCP_EXECUTE_RAW;
1654 return true;
1655 }
1656#endif
1657
1658#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1659 if (!(env->eflags & IF_MASK))
1660 {
1661 STAM_COUNTER_INC(&gStatRefuseIF0);
1662 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1663 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1664 return false;
1665 }
1666#endif
1667
1668#ifndef VBOX_WITH_RAW_RING1
1669 if (((env->eflags >> IOPL_SHIFT) & 3) != 0)
1670 {
1671 Log2(("raw r0 mode refused: IOPL %d\n", ((env->eflags >> IOPL_SHIFT) & 3)));
1672 return false;
1673 }
1674#endif
1675 env->state |= CPU_RAW_RING0;
1676 }
1677
1678 /*
1679 * Don't reschedule the first time we're called, because there might be
1680 * special reasons why we're here that is not covered by the above checks.
1681 */
1682 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1683 {
1684 Log2(("raw mode refused: first scheduling\n"));
1685 STAM_COUNTER_INC(&gStatRefuseCanExecute);
1686 return false;
1687 }
1688
1689 /*
1690 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1691 */
1692 if (env->segs[R_CS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1693 {
1694 Log2(("raw mode refused: stale CS (%#x)\n", env->segs[R_CS].selector));
1695 STAM_COUNTER_INC(&gaStatRefuseStale[R_CS]);
1696 return false;
1697 }
1698 if (env->segs[R_SS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1699 {
1700 Log2(("raw mode refused: stale SS (%#x)\n", env->segs[R_SS].selector));
1701 STAM_COUNTER_INC(&gaStatRefuseStale[R_SS]);
1702 return false;
1703 }
1704 if (env->segs[R_DS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1705 {
1706 Log2(("raw mode refused: stale DS (%#x)\n", env->segs[R_DS].selector));
1707 STAM_COUNTER_INC(&gaStatRefuseStale[R_DS]);
1708 return false;
1709 }
1710 if (env->segs[R_ES].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1711 {
1712 Log2(("raw mode refused: stale ES (%#x)\n", env->segs[R_ES].selector));
1713 STAM_COUNTER_INC(&gaStatRefuseStale[R_ES]);
1714 return false;
1715 }
1716 if (env->segs[R_FS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1717 {
1718 Log2(("raw mode refused: stale FS (%#x)\n", env->segs[R_FS].selector));
1719 STAM_COUNTER_INC(&gaStatRefuseStale[R_FS]);
1720 return false;
1721 }
1722 if (env->segs[R_GS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1723 {
1724 Log2(("raw mode refused: stale GS (%#x)\n", env->segs[R_GS].selector));
1725 STAM_COUNTER_INC(&gaStatRefuseStale[R_GS]);
1726 return false;
1727 }
1728
1729/* Assert(env->pVCpu && PGMPhysIsA20Enabled(env->pVCpu));*/
1730 *piException = EXCP_EXECUTE_RAW;
1731 return true;
1732}
1733
1734
1735#ifdef VBOX_WITH_RAW_MODE
1736/**
1737 * Fetches a code byte.
1738 *
1739 * @returns Success indicator (bool) for ease of use.
1740 * @param env The CPU environment structure.
1741 * @param GCPtrInstr Where to fetch code.
1742 * @param pu8Byte Where to store the byte on success
1743 */
1744bool remR3GetOpcode(CPUX86State *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte)
1745{
1746 int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1747 if (RT_SUCCESS(rc))
1748 return true;
1749 return false;
1750}
1751#endif /* VBOX_WITH_RAW_MODE */
1752
1753
1754/**
1755 * Flush (or invalidate if you like) page table/dir entry.
1756 *
1757 * (invlpg instruction; tlb_flush_page)
1758 *
1759 * @param env Pointer to cpu environment.
1760 * @param GCPtr The virtual address which page table/dir entry should be invalidated.
1761 */
1762void remR3FlushPage(CPUX86State *env, RTGCPTR GCPtr)
1763{
1764 PVM pVM = env->pVM;
1765 PCPUMCTX pCtx;
1766 int rc;
1767
1768 Assert(EMRemIsLockOwner(env->pVM));
1769
1770 /*
1771 * When we're replaying invlpg instructions or restoring a saved
1772 * state we disable this path.
1773 */
1774 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.cIgnoreAll)
1775 return;
1776 LogFlow(("remR3FlushPage: GCPtr=%RGv\n", GCPtr));
1777 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1778
1779 //RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1780
1781 /*
1782 * Update the control registers before calling PGMFlushPage.
1783 */
1784 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1785 Assert(pCtx);
1786 pCtx->cr0 = env->cr[0];
1787 pCtx->cr3 = env->cr[3];
1788#ifdef VBOX_WITH_RAW_MODE
1789 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1790 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1791#endif
1792 pCtx->cr4 = env->cr[4];
1793
1794 /*
1795 * Let PGM do the rest.
1796 */
1797 Assert(env->pVCpu);
1798 rc = PGMInvalidatePage(env->pVCpu, GCPtr);
1799 if (RT_FAILURE(rc))
1800 {
1801 AssertMsgFailed(("remR3FlushPage %RGv failed with %d!!\n", GCPtr, rc));
1802 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1803 }
1804 //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1805}
1806
1807
1808#ifndef REM_PHYS_ADDR_IN_TLB
1809/** Wrapper for PGMR3PhysTlbGCPhys2Ptr. */
1810void *remR3TlbGCPhys2Ptr(CPUX86State *env1, target_ulong physAddr, int fWritable)
1811{
1812 void *pv;
1813 int rc;
1814
1815
1816 /* Address must be aligned enough to fiddle with lower bits */
1817 Assert((physAddr & 0x3) == 0);
1818 /*AssertMsg((env1->a20_mask & physAddr) == physAddr, ("%llx\n", (uint64_t)physAddr));*/
1819
1820 STAM_PROFILE_START(&gStatGCPhys2HCVirt, a);
1821 rc = PGMR3PhysTlbGCPhys2Ptr(env1->pVM, physAddr, true /*fWritable*/, &pv);
1822 STAM_PROFILE_STOP(&gStatGCPhys2HCVirt, a);
1823 Assert( rc == VINF_SUCCESS
1824 || rc == VINF_PGM_PHYS_TLB_CATCH_WRITE
1825 || rc == VERR_PGM_PHYS_TLB_CATCH_ALL
1826 || rc == VERR_PGM_PHYS_TLB_UNASSIGNED);
1827 if (RT_FAILURE(rc))
1828 return (void *)1;
1829 if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
1830 return (void *)((uintptr_t)pv | 2);
1831 return pv;
1832}
1833#endif /* REM_PHYS_ADDR_IN_TLB */
1834
1835
1836/**
1837 * Called from tlb_protect_code in order to write monitor a code page.
1838 *
1839 * @param env Pointer to the CPU environment.
1840 * @param GCPtr Code page to monitor
1841 */
1842void remR3ProtectCode(CPUX86State *env, RTGCPTR GCPtr)
1843{
1844#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1845 Assert(env->pVM->rem.s.fInREM);
1846 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1847 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1848 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1849 && !(env->eflags & VM_MASK) /* no V86 mode */
1850 && !HMIsEnabled(env->pVM))
1851 CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1852#endif
1853}
1854
1855
1856/**
1857 * Called from tlb_unprotect_code in order to clear write monitoring for a code page.
1858 *
1859 * @param env Pointer to the CPU environment.
1860 * @param GCPtr Code page to monitor
1861 */
1862void remR3UnprotectCode(CPUX86State *env, RTGCPTR GCPtr)
1863{
1864 Assert(env->pVM->rem.s.fInREM);
1865#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1866 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1867 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1868 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1869 && !(env->eflags & VM_MASK) /* no V86 mode */
1870 && !HMIsEnabled(env->pVM))
1871 CSAMR3UnmonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1872#endif
1873}
1874
1875
1876/**
1877 * Called when the CPU is initialized, any of the CRx registers are changed or
1878 * when the A20 line is modified.
1879 *
1880 * @param env Pointer to the CPU environment.
1881 * @param fGlobal Set if the flush is global.
1882 */
1883void remR3FlushTLB(CPUX86State *env, bool fGlobal)
1884{
1885 PVM pVM = env->pVM;
1886 PCPUMCTX pCtx;
1887 Assert(EMRemIsLockOwner(pVM));
1888
1889 /*
1890 * When we're replaying invlpg instructions or restoring a saved
1891 * state we disable this path.
1892 */
1893 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.cIgnoreAll)
1894 return;
1895 Assert(pVM->rem.s.fInREM);
1896
1897 /*
1898 * The caller doesn't check cr4, so we have to do that for ourselves.
1899 */
1900 if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1901 fGlobal = true;
1902 Log(("remR3FlushTLB: CR0=%08RX64 CR3=%08RX64 CR4=%08RX64 %s\n", (uint64_t)env->cr[0], (uint64_t)env->cr[3], (uint64_t)env->cr[4], fGlobal ? " global" : ""));
1903
1904 /*
1905 * Update the control registers before calling PGMR3FlushTLB.
1906 */
1907 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1908 Assert(pCtx);
1909 pCtx->cr0 = env->cr[0];
1910 pCtx->cr3 = env->cr[3];
1911#ifdef VBOX_WITH_RAW_MODE
1912 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1913 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1914#endif
1915 pCtx->cr4 = env->cr[4];
1916
1917 /*
1918 * Let PGM do the rest.
1919 */
1920 Assert(env->pVCpu);
1921 PGMFlushTLB(env->pVCpu, env->cr[3], fGlobal);
1922}
1923
1924
1925/**
1926 * Called when any of the cr0, cr4 or efer registers is updated.
1927 *
1928 * @param env Pointer to the CPU environment.
1929 */
1930void remR3ChangeCpuMode(CPUX86State *env)
1931{
1932 PVM pVM = env->pVM;
1933 uint64_t efer;
1934 PCPUMCTX pCtx;
1935 int rc;
1936
1937 /*
1938 * When we're replaying loads or restoring a saved
1939 * state this path is disabled.
1940 */
1941 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.cIgnoreAll)
1942 return;
1943 Assert(pVM->rem.s.fInREM);
1944
1945 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1946 Assert(pCtx);
1947
1948 /*
1949 * Notify PGM about WP0 being enabled (like CPUSetGuestCR0 does).
1950 */
1951 if (((env->cr[0] ^ pCtx->cr0) & X86_CR0_WP) && (env->cr[0] & X86_CR0_WP))
1952 PGMCr0WpEnabled(env->pVCpu);
1953
1954 /*
1955 * Update the control registers before calling PGMChangeMode()
1956 * as it may need to map whatever cr3 is pointing to.
1957 */
1958 pCtx->cr0 = env->cr[0];
1959 pCtx->cr3 = env->cr[3];
1960#ifdef VBOX_WITH_RAW_MODE
1961 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1962 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1963#endif
1964 pCtx->cr4 = env->cr[4];
1965#ifdef TARGET_X86_64
1966 efer = env->efer;
1967 pCtx->msrEFER = efer;
1968#else
1969 efer = 0;
1970#endif
1971 Assert(env->pVCpu);
1972 rc = PGMChangeMode(env->pVCpu, env->cr[0], env->cr[4], efer);
1973 if (rc != VINF_SUCCESS)
1974 {
1975 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1976 {
1977 Log(("PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc -> remR3RaiseRC\n", env->cr[0], env->cr[4], efer, rc));
1978 remR3RaiseRC(env->pVM, rc);
1979 }
1980 else
1981 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], efer, rc);
1982 }
1983}
1984
1985
1986/**
1987 * Called from compiled code to run dma.
1988 *
1989 * @param env Pointer to the CPU environment.
1990 */
1991void remR3DmaRun(CPUX86State *env)
1992{
1993 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1994 PDMR3DmaRun(env->pVM);
1995 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1996}
1997
1998
1999/**
2000 * Called from compiled code to schedule pending timers in VMM
2001 *
2002 * @param env Pointer to the CPU environment.
2003 */
2004void remR3TimersRun(CPUX86State *env)
2005{
2006 LogFlow(("remR3TimersRun:\n"));
2007 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("remR3TimersRun\n"));
2008 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
2009 remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
2010 TMR3TimerQueuesDo(env->pVM);
2011 remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
2012 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
2013}
2014
2015
2016/**
2017 * Record trap occurrence
2018 *
2019 * @returns VBox status code
2020 * @param env Pointer to the CPU environment.
2021 * @param uTrap Trap nr
2022 * @param uErrorCode Error code
2023 * @param pvNextEIP Next EIP
2024 */
2025int remR3NotifyTrap(CPUX86State *env, uint32_t uTrap, uint32_t uErrorCode, RTGCPTR pvNextEIP)
2026{
2027 PVM pVM = env->pVM;
2028#ifdef VBOX_WITH_STATISTICS
2029 static STAMCOUNTER s_aStatTrap[255];
2030 static bool s_aRegisters[RT_ELEMENTS(s_aStatTrap)];
2031#endif
2032
2033#ifdef VBOX_WITH_STATISTICS
2034 if (uTrap < 255)
2035 {
2036 if (!s_aRegisters[uTrap])
2037 {
2038 char szStatName[64];
2039 s_aRegisters[uTrap] = true;
2040 RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
2041 STAM_REG(env->pVM, &s_aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
2042 }
2043 STAM_COUNTER_INC(&s_aStatTrap[uTrap]);
2044 }
2045#endif
2046 Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
2047 if( uTrap < 0x20
2048 && (env->cr[0] & X86_CR0_PE)
2049 && !(env->eflags & X86_EFL_VM))
2050 {
2051#ifdef DEBUG
2052 remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
2053#endif
2054 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
2055 {
2056 LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
2057 remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
2058 return VERR_REM_TOO_MANY_TRAPS;
2059 }
2060 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
2061 {
2062 Log(("remR3NotifyTrap: uTrap=%#x set as pending\n", uTrap));
2063 pVM->rem.s.cPendingExceptions = 1;
2064 }
2065 pVM->rem.s.uPendingException = uTrap;
2066 pVM->rem.s.uPendingExcptEIP = env->eip;
2067 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2068 }
2069 else
2070 {
2071 pVM->rem.s.cPendingExceptions = 0;
2072 pVM->rem.s.uPendingException = uTrap;
2073 pVM->rem.s.uPendingExcptEIP = env->eip;
2074 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2075 }
2076 return VINF_SUCCESS;
2077}
2078
2079
2080/*
2081 * Clear current active trap
2082 *
2083 * @param pVM VM Handle.
2084 */
2085void remR3TrapClear(PVM pVM)
2086{
2087 pVM->rem.s.cPendingExceptions = 0;
2088 pVM->rem.s.uPendingException = 0;
2089 pVM->rem.s.uPendingExcptEIP = 0;
2090 pVM->rem.s.uPendingExcptCR2 = 0;
2091}
2092
2093
2094/*
2095 * Record previous call instruction addresses
2096 *
2097 * @param env Pointer to the CPU environment.
2098 */
2099void remR3RecordCall(CPUX86State *env)
2100{
2101#ifdef VBOX_WITH_RAW_MODE
2102 CSAMR3RecordCallAddress(env->pVM, env->eip);
2103#endif
2104}
2105
2106
2107/**
2108 * Syncs the internal REM state with the VM.
2109 *
2110 * This must be called before REMR3Run() is invoked whenever when the REM
2111 * state is not up to date. Calling it several times in a row is not
2112 * permitted.
2113 *
2114 * @returns VBox status code.
2115 *
2116 * @param pVM VM Handle.
2117 * @param pVCpu VMCPU Handle.
2118 *
2119 * @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
2120 * no do this since the majority of the callers don't want any unnecessary of events
2121 * pending that would immediately interrupt execution.
2122 */
2123REMR3DECL(int) REMR3State(PVM pVM, PVMCPU pVCpu)
2124{
2125 register const CPUMCTX *pCtx;
2126 register unsigned fFlags;
2127 unsigned i;
2128 TRPMEVENT enmType;
2129 uint8_t u8TrapNo;
2130 uint32_t uCpl;
2131 int rc;
2132
2133 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
2134 Log2(("REMR3State:\n"));
2135
2136 pVM->rem.s.Env.pVCpu = pVCpu;
2137 pCtx = pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2138
2139 Assert(!pVM->rem.s.fInREM);
2140 pVM->rem.s.fInStateSync = true;
2141
2142 /*
2143 * If we have to flush TBs, do that immediately.
2144 */
2145 if (pVM->rem.s.fFlushTBs)
2146 {
2147 STAM_COUNTER_INC(&gStatFlushTBs);
2148 tb_flush(&pVM->rem.s.Env);
2149 pVM->rem.s.fFlushTBs = false;
2150 }
2151
2152 /*
2153 * Copy the registers which require no special handling.
2154 */
2155#ifdef TARGET_X86_64
2156 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2157 Assert(R_EAX == 0);
2158 pVM->rem.s.Env.regs[R_EAX] = pCtx->rax;
2159 Assert(R_ECX == 1);
2160 pVM->rem.s.Env.regs[R_ECX] = pCtx->rcx;
2161 Assert(R_EDX == 2);
2162 pVM->rem.s.Env.regs[R_EDX] = pCtx->rdx;
2163 Assert(R_EBX == 3);
2164 pVM->rem.s.Env.regs[R_EBX] = pCtx->rbx;
2165 Assert(R_ESP == 4);
2166 pVM->rem.s.Env.regs[R_ESP] = pCtx->rsp;
2167 Assert(R_EBP == 5);
2168 pVM->rem.s.Env.regs[R_EBP] = pCtx->rbp;
2169 Assert(R_ESI == 6);
2170 pVM->rem.s.Env.regs[R_ESI] = pCtx->rsi;
2171 Assert(R_EDI == 7);
2172 pVM->rem.s.Env.regs[R_EDI] = pCtx->rdi;
2173 pVM->rem.s.Env.regs[8] = pCtx->r8;
2174 pVM->rem.s.Env.regs[9] = pCtx->r9;
2175 pVM->rem.s.Env.regs[10] = pCtx->r10;
2176 pVM->rem.s.Env.regs[11] = pCtx->r11;
2177 pVM->rem.s.Env.regs[12] = pCtx->r12;
2178 pVM->rem.s.Env.regs[13] = pCtx->r13;
2179 pVM->rem.s.Env.regs[14] = pCtx->r14;
2180 pVM->rem.s.Env.regs[15] = pCtx->r15;
2181
2182 pVM->rem.s.Env.eip = pCtx->rip;
2183
2184 pVM->rem.s.Env.eflags = pCtx->rflags.u64;
2185#else
2186 Assert(R_EAX == 0);
2187 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
2188 Assert(R_ECX == 1);
2189 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
2190 Assert(R_EDX == 2);
2191 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
2192 Assert(R_EBX == 3);
2193 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
2194 Assert(R_ESP == 4);
2195 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
2196 Assert(R_EBP == 5);
2197 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
2198 Assert(R_ESI == 6);
2199 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
2200 Assert(R_EDI == 7);
2201 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
2202 pVM->rem.s.Env.eip = pCtx->eip;
2203
2204 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
2205#endif
2206
2207 pVM->rem.s.Env.cr[2] = pCtx->cr2;
2208
2209 /** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
2210 for (i=0;i<8;i++)
2211 pVM->rem.s.Env.dr[i] = pCtx->dr[i];
2212
2213#ifdef HF_HALTED_MASK /** @todo remove me when we're up to date again. */
2214 /*
2215 * Clear the halted hidden flag (the interrupt waking up the CPU can
2216 * have been dispatched in raw mode).
2217 */
2218 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
2219#endif
2220
2221 /*
2222 * Replay invlpg? Only if we're not flushing the TLB.
2223 */
2224 fFlags = CPUMR3RemEnter(pVCpu, &uCpl);
2225 LogFlow(("CPUMR3RemEnter %x %x\n", fFlags, uCpl));
2226 if (pVM->rem.s.cInvalidatedPages)
2227 {
2228 if (!(fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH))
2229 {
2230 RTUINT i;
2231
2232 pVM->rem.s.fIgnoreCR3Load = true;
2233 pVM->rem.s.fIgnoreInvlPg = true;
2234 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2235 {
2236 Log2(("REMR3State: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2237 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2238 }
2239 pVM->rem.s.fIgnoreInvlPg = false;
2240 pVM->rem.s.fIgnoreCR3Load = false;
2241 }
2242 pVM->rem.s.cInvalidatedPages = 0;
2243 }
2244
2245 /* Replay notification changes. */
2246 REMR3ReplayHandlerNotifications(pVM);
2247
2248 /* Update MSRs; before CRx registers! */
2249 pVM->rem.s.Env.efer = pCtx->msrEFER;
2250 pVM->rem.s.Env.star = pCtx->msrSTAR;
2251 pVM->rem.s.Env.pat = pCtx->msrPAT;
2252#ifdef TARGET_X86_64
2253 pVM->rem.s.Env.lstar = pCtx->msrLSTAR;
2254 pVM->rem.s.Env.cstar = pCtx->msrCSTAR;
2255 pVM->rem.s.Env.fmask = pCtx->msrSFMASK;
2256 pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
2257
2258 /* Update the internal long mode activate flag according to the new EFER value. */
2259 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
2260 pVM->rem.s.Env.hflags |= HF_LMA_MASK;
2261 else
2262 pVM->rem.s.Env.hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
2263#endif
2264
2265 /* Update the inhibit IRQ mask. */
2266 pVM->rem.s.Env.hflags &= ~HF_INHIBIT_IRQ_MASK;
2267 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2268 {
2269 RTGCPTR InhibitPC = EMGetInhibitInterruptsPC(pVCpu);
2270 if (InhibitPC == pCtx->rip)
2271 pVM->rem.s.Env.hflags |= HF_INHIBIT_IRQ_MASK;
2272 else
2273 {
2274 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#1)\n", (RTGCPTR)pCtx->rip, InhibitPC));
2275 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2276 }
2277 }
2278
2279 /* Update the inhibit NMI mask. */
2280 pVM->rem.s.Env.hflags2 &= ~HF2_NMI_MASK;
2281 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2282 pVM->rem.s.Env.hflags2 |= HF2_NMI_MASK;
2283
2284 /*
2285 * Sync the A20 gate.
2286 */
2287 bool fA20State = PGMPhysIsA20Enabled(pVCpu);
2288 if (fA20State != RT_BOOL(pVM->rem.s.Env.a20_mask & RT_BIT(20)))
2289 {
2290 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
2291 cpu_x86_set_a20(&pVM->rem.s.Env, fA20State);
2292 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
2293 }
2294
2295 /*
2296 * Registers which are rarely changed and require special handling / order when changed.
2297 */
2298 if (fFlags & ( CPUM_CHANGED_GLOBAL_TLB_FLUSH
2299 | CPUM_CHANGED_CR4
2300 | CPUM_CHANGED_CR0
2301 | CPUM_CHANGED_CR3
2302 | CPUM_CHANGED_GDTR
2303 | CPUM_CHANGED_IDTR
2304 | CPUM_CHANGED_SYSENTER_MSR
2305 | CPUM_CHANGED_LDTR
2306 | CPUM_CHANGED_CPUID
2307 | CPUM_CHANGED_FPU_REM
2308 )
2309 )
2310 {
2311 if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
2312 {
2313 pVM->rem.s.fIgnoreCR3Load = true;
2314 tlb_flush(&pVM->rem.s.Env, true);
2315 pVM->rem.s.fIgnoreCR3Load = false;
2316 }
2317
2318 /* CR4 before CR0! */
2319 if (fFlags & CPUM_CHANGED_CR4)
2320 {
2321 pVM->rem.s.fIgnoreCR3Load = true;
2322 pVM->rem.s.fIgnoreCpuMode = true;
2323 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
2324 pVM->rem.s.fIgnoreCpuMode = false;
2325 pVM->rem.s.fIgnoreCR3Load = false;
2326 }
2327
2328 if (fFlags & CPUM_CHANGED_CR0)
2329 {
2330 pVM->rem.s.fIgnoreCR3Load = true;
2331 pVM->rem.s.fIgnoreCpuMode = true;
2332 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
2333 pVM->rem.s.fIgnoreCpuMode = false;
2334 pVM->rem.s.fIgnoreCR3Load = false;
2335 }
2336
2337 if (fFlags & CPUM_CHANGED_CR3)
2338 {
2339 pVM->rem.s.fIgnoreCR3Load = true;
2340 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
2341 pVM->rem.s.fIgnoreCR3Load = false;
2342 }
2343
2344 if (fFlags & CPUM_CHANGED_GDTR)
2345 {
2346 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
2347 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
2348 }
2349
2350 if (fFlags & CPUM_CHANGED_IDTR)
2351 {
2352 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
2353 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
2354 }
2355
2356 if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
2357 {
2358 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
2359 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
2360 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
2361 }
2362
2363 if (fFlags & CPUM_CHANGED_LDTR)
2364 {
2365 if (pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2366 {
2367 pVM->rem.s.Env.ldt.selector = pCtx->ldtr.Sel;
2368 pVM->rem.s.Env.ldt.newselector = 0;
2369 pVM->rem.s.Env.ldt.fVBoxFlags = pCtx->ldtr.fFlags;
2370 pVM->rem.s.Env.ldt.base = pCtx->ldtr.u64Base;
2371 pVM->rem.s.Env.ldt.limit = pCtx->ldtr.u32Limit;
2372 pVM->rem.s.Env.ldt.flags = (pCtx->ldtr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2373 }
2374 else
2375 {
2376 AssertFailed(); /* Shouldn't happen, see cpumR3LoadExec. */
2377 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr.Sel);
2378 }
2379 }
2380
2381 if (fFlags & CPUM_CHANGED_CPUID)
2382 {
2383 uint32_t u32Dummy;
2384
2385 /*
2386 * Get the CPUID features.
2387 */
2388 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
2389 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
2390 }
2391
2392 /* Sync FPU state after CR4, CPUID and EFER (!). */
2393 if (fFlags & CPUM_CHANGED_FPU_REM)
2394 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87); /* 'save' is an excellent name. */
2395 }
2396
2397 /*
2398 * Sync TR unconditionally to make life simpler.
2399 */
2400 pVM->rem.s.Env.tr.selector = pCtx->tr.Sel;
2401 pVM->rem.s.Env.tr.newselector = 0;
2402 pVM->rem.s.Env.tr.fVBoxFlags = pCtx->tr.fFlags;
2403 pVM->rem.s.Env.tr.base = pCtx->tr.u64Base;
2404 pVM->rem.s.Env.tr.limit = pCtx->tr.u32Limit;
2405 pVM->rem.s.Env.tr.flags = (pCtx->tr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2406
2407 /*
2408 * Update selector registers.
2409 *
2410 * This must be done *after* we've synced gdt, ldt and crX registers
2411 * since we're reading the GDT/LDT om sync_seg. This will happen with
2412 * saved state which takes a quick dip into rawmode for instance.
2413 *
2414 * CPL/Stack; Note first check this one as the CPL might have changed.
2415 * The wrong CPL can cause QEmu to raise an exception in sync_seg!!
2416 */
2417 cpu_x86_set_cpl(&pVM->rem.s.Env, uCpl);
2418 /* Note! QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
2419#define SYNC_IN_SREG(a_pEnv, a_SReg, a_pRemSReg, a_pVBoxSReg) \
2420 do \
2421 { \
2422 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, a_pVBoxSReg)) \
2423 { \
2424 cpu_x86_load_seg_cache(a_pEnv, R_##a_SReg, \
2425 (a_pVBoxSReg)->Sel, \
2426 (a_pVBoxSReg)->u64Base, \
2427 (a_pVBoxSReg)->u32Limit, \
2428 ((a_pVBoxSReg)->Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT); \
2429 (a_pRemSReg)->fVBoxFlags = (a_pVBoxSReg)->fFlags; \
2430 } \
2431 /* This only-reload-if-changed stuff is the old approach, we should ditch it. */ \
2432 else if ((a_pRemSReg)->selector != (a_pVBoxSReg)->Sel) \
2433 { \
2434 Log2(("REMR3State: " #a_SReg " changed from %04x to %04x!\n", \
2435 (a_pRemSReg)->selector, (a_pVBoxSReg)->Sel)); \
2436 sync_seg(a_pEnv, R_##a_SReg, (a_pVBoxSReg)->Sel); \
2437 if ((a_pRemSReg)->newselector) \
2438 STAM_COUNTER_INC(&gStatSelOutOfSync[R_##a_SReg]); \
2439 } \
2440 else \
2441 (a_pRemSReg)->newselector = 0; \
2442 } while (0)
2443
2444 SYNC_IN_SREG(&pVM->rem.s.Env, CS, &pVM->rem.s.Env.segs[R_CS], &pCtx->cs);
2445 SYNC_IN_SREG(&pVM->rem.s.Env, SS, &pVM->rem.s.Env.segs[R_SS], &pCtx->ss);
2446 SYNC_IN_SREG(&pVM->rem.s.Env, DS, &pVM->rem.s.Env.segs[R_DS], &pCtx->ds);
2447 SYNC_IN_SREG(&pVM->rem.s.Env, ES, &pVM->rem.s.Env.segs[R_ES], &pCtx->es);
2448 SYNC_IN_SREG(&pVM->rem.s.Env, FS, &pVM->rem.s.Env.segs[R_FS], &pCtx->fs);
2449 SYNC_IN_SREG(&pVM->rem.s.Env, GS, &pVM->rem.s.Env.segs[R_GS], &pCtx->gs);
2450 /** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
2451 * be the same but not the base/limit. */
2452
2453 /*
2454 * Check for traps.
2455 */
2456 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
2457 rc = TRPMQueryTrap(pVCpu, &u8TrapNo, &enmType);
2458 if (RT_SUCCESS(rc))
2459 {
2460#ifdef DEBUG
2461 if (u8TrapNo == 0x80)
2462 {
2463 remR3DumpLnxSyscall(pVCpu);
2464 remR3DumpOBsdSyscall(pVCpu);
2465 }
2466#endif
2467
2468 pVM->rem.s.Env.exception_index = u8TrapNo;
2469 if (enmType != TRPM_SOFTWARE_INT)
2470 {
2471 pVM->rem.s.Env.exception_is_int = enmType == TRPM_HARDWARE_INT
2472 ? EXCEPTION_IS_INT_VALUE_HARDWARE_IRQ : 0; /* HACK ALERT! */
2473 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
2474 }
2475 else
2476 {
2477 /*
2478 * The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
2479 * We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
2480 * for int03 and into.
2481 */
2482 pVM->rem.s.Env.exception_is_int = 1;
2483 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 2;
2484 /* int 3 may be generated by one-byte 0xcc */
2485 if (u8TrapNo == 3)
2486 {
2487 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xcc)
2488 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2489 }
2490 /* int 4 may be generated by one-byte 0xce */
2491 else if (u8TrapNo == 4)
2492 {
2493 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xce)
2494 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2495 }
2496 }
2497
2498 /* get error code and cr2 if needed. */
2499 if (enmType == TRPM_TRAP)
2500 {
2501 switch (u8TrapNo)
2502 {
2503 case X86_XCPT_PF:
2504 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVCpu);
2505 /* fallthru */
2506 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP:
2507 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVCpu);
2508 break;
2509
2510 case X86_XCPT_AC: case X86_XCPT_DF:
2511 default:
2512 pVM->rem.s.Env.error_code = 0;
2513 break;
2514 }
2515 }
2516 else
2517 pVM->rem.s.Env.error_code = 0;
2518
2519 /*
2520 * We can now reset the active trap since the recompiler is gonna have a go at it.
2521 */
2522 rc = TRPMResetTrap(pVCpu);
2523 AssertRC(rc);
2524 Log2(("REMR3State: trap=%02x errcd=%RGv cr2=%RGv nexteip=%RGv%s\n", pVM->rem.s.Env.exception_index, (RTGCPTR)pVM->rem.s.Env.error_code,
2525 (RTGCPTR)pVM->rem.s.Env.cr[2], (RTGCPTR)pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
2526 }
2527
2528 /*
2529 * Clear old interrupt request flags; Check for pending hardware interrupts.
2530 * (See @remark for why we don't check for other FFs.)
2531 */
2532 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
2533 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2534 APICUpdatePendingInterrupts(pVCpu);
2535 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2536 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
2537
2538 /*
2539 * We're now in REM mode.
2540 */
2541 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_REM);
2542 pVM->rem.s.fInREM = true;
2543 pVM->rem.s.fInStateSync = false;
2544 pVM->rem.s.cCanExecuteRaw = 0;
2545 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
2546 Log2(("REMR3State: returns VINF_SUCCESS\n"));
2547 return VINF_SUCCESS;
2548}
2549
2550
2551/**
2552 * Syncs back changes in the REM state to the VM state.
2553 *
2554 * This must be called after invoking REMR3Run().
2555 * Calling it several times in a row is not permitted.
2556 *
2557 * @returns VBox status code.
2558 *
2559 * @param pVM VM Handle.
2560 * @param pVCpu VMCPU Handle.
2561 */
2562REMR3DECL(int) REMR3StateBack(PVM pVM, PVMCPU pVCpu)
2563{
2564 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2565 Assert(pCtx);
2566 unsigned i;
2567
2568 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2569 Log2(("REMR3StateBack:\n"));
2570 Assert(pVM->rem.s.fInREM);
2571
2572 /*
2573 * Copy back the registers.
2574 * This is done in the order they are declared in the CPUMCTX structure.
2575 */
2576
2577 /** @todo FOP */
2578 /** @todo FPUIP */
2579 /** @todo CS */
2580 /** @todo FPUDP */
2581 /** @todo DS */
2582
2583 /** @todo check if FPU/XMM was actually used in the recompiler */
2584 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87);
2585//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2586
2587#ifdef TARGET_X86_64
2588 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2589 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2590 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2591 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2592 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2593 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2594 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2595 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2596 pCtx->r8 = pVM->rem.s.Env.regs[8];
2597 pCtx->r9 = pVM->rem.s.Env.regs[9];
2598 pCtx->r10 = pVM->rem.s.Env.regs[10];
2599 pCtx->r11 = pVM->rem.s.Env.regs[11];
2600 pCtx->r12 = pVM->rem.s.Env.regs[12];
2601 pCtx->r13 = pVM->rem.s.Env.regs[13];
2602 pCtx->r14 = pVM->rem.s.Env.regs[14];
2603 pCtx->r15 = pVM->rem.s.Env.regs[15];
2604
2605 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2606
2607#else
2608 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2609 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2610 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2611 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2612 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2613 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2614 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2615
2616 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2617#endif
2618
2619#define SYNC_BACK_SREG(a_sreg, a_SREG) \
2620 do \
2621 { \
2622 pCtx->a_sreg.Sel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2623 if (!pVM->rem.s.Env.segs[R_SS].newselector) \
2624 { \
2625 pCtx->a_sreg.ValidSel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2626 pCtx->a_sreg.fFlags = CPUMSELREG_FLAGS_VALID; \
2627 pCtx->a_sreg.u64Base = pVM->rem.s.Env.segs[R_##a_SREG].base; \
2628 pCtx->a_sreg.u32Limit = pVM->rem.s.Env.segs[R_##a_SREG].limit; \
2629 /* Note! QEmu saves the 2nd dword of the descriptor; we (VT-x/AMD-V) keep only the attributes! */ \
2630 pCtx->a_sreg.Attr.u = (pVM->rem.s.Env.segs[R_##a_SREG].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK; \
2631 } \
2632 else \
2633 { \
2634 pCtx->a_sreg.fFlags = 0; \
2635 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_##a_SREG]); \
2636 } \
2637 } while (0)
2638
2639 SYNC_BACK_SREG(es, ES);
2640 SYNC_BACK_SREG(cs, CS);
2641 SYNC_BACK_SREG(ss, SS);
2642 SYNC_BACK_SREG(ds, DS);
2643 SYNC_BACK_SREG(fs, FS);
2644 SYNC_BACK_SREG(gs, GS);
2645
2646#ifdef TARGET_X86_64
2647 pCtx->rip = pVM->rem.s.Env.eip;
2648 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2649#else
2650 pCtx->eip = pVM->rem.s.Env.eip;
2651 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2652#endif
2653
2654 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2655 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2656 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2657#ifdef VBOX_WITH_RAW_MODE
2658 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2659 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2660#endif
2661 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2662
2663 for (i = 0; i < 8; i++)
2664 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2665
2666 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2667 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base)
2668 {
2669 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base;
2670 STAM_COUNTER_INC(&gStatREMGDTChange);
2671#ifdef VBOX_WITH_RAW_MODE
2672 if (!HMIsEnabled(pVM))
2673 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2674#endif
2675 }
2676
2677 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2678 if (pCtx->idtr.pIdt != pVM->rem.s.Env.idt.base)
2679 {
2680 pCtx->idtr.pIdt = pVM->rem.s.Env.idt.base;
2681 STAM_COUNTER_INC(&gStatREMIDTChange);
2682#ifdef VBOX_WITH_RAW_MODE
2683 if (!HMIsEnabled(pVM))
2684 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2685#endif
2686 }
2687
2688 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2689 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2690 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2691 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2692 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2693 || !(pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2694 )
2695 {
2696 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2697 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2698 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2699 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2700 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2701 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2702 STAM_COUNTER_INC(&gStatREMLDTRChange);
2703#ifdef VBOX_WITH_RAW_MODE
2704 if (!HMIsEnabled(pVM))
2705 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2706#endif
2707 }
2708
2709 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2710 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2711 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2712 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2713 || pCtx->tr.Attr.u != ((pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2714 || !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
2715 )
2716 {
2717 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2718 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2719 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2720 pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT));
2721 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2722 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2723 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2724 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2725 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2726 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2727 Assert(pCtx->tr.Attr.u & ~DESC_INTEL_UNUSABLE);
2728 STAM_COUNTER_INC(&gStatREMTRChange);
2729#ifdef VBOX_WITH_RAW_MODE
2730 if (!HMIsEnabled(pVM))
2731 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2732#endif
2733 }
2734
2735 /* Sysenter MSR */
2736 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2737 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2738 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2739
2740 /* System MSRs. */
2741 pCtx->msrEFER = pVM->rem.s.Env.efer;
2742 pCtx->msrSTAR = pVM->rem.s.Env.star;
2743 pCtx->msrPAT = pVM->rem.s.Env.pat;
2744#ifdef TARGET_X86_64
2745 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2746 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2747 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2748 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2749#endif
2750
2751 /* Inhibit interrupt flag. */
2752 if (pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK)
2753 {
2754 Log(("Settings VMCPU_FF_INHIBIT_INTERRUPTS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2755 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
2756 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2757 }
2758 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2759 {
2760 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#2)\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2761 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2762 }
2763
2764 /* Inhibit NMI flag. */
2765 if (pVM->rem.s.Env.hflags2 & HF2_NMI_MASK)
2766 {
2767 Log(("Settings VMCPU_FF_BLOCK_NMIS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2768 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2769 }
2770 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2771 {
2772 Log(("Clearing VMCPU_FF_BLOCK_NMIS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2773 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2774 }
2775
2776 remR3TrapClear(pVM);
2777
2778 /*
2779 * Check for traps.
2780 */
2781 if ( pVM->rem.s.Env.exception_index >= 0
2782 && pVM->rem.s.Env.exception_index < 256)
2783 {
2784 /* This cannot be a hardware-interrupt because exception_index < EXCP_INTERRUPT. */
2785 int rc;
2786
2787 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2788 TRPMEVENT enmType = pVM->rem.s.Env.exception_is_int == 0 ? TRPM_TRAP
2789 : pVM->rem.s.Env.exception_is_int == EXCEPTION_IS_INT_VALUE_HARDWARE_IRQ ? TRPM_HARDWARE_INT
2790 : TRPM_SOFTWARE_INT;
2791 rc = TRPMAssertTrap(pVCpu, pVM->rem.s.Env.exception_index, enmType);
2792 AssertRC(rc);
2793 if (enmType == TRPM_TRAP)
2794 {
2795 switch (pVM->rem.s.Env.exception_index)
2796 {
2797 case X86_XCPT_PF:
2798 TRPMSetFaultAddress(pVCpu, pCtx->cr2);
2799 /* fallthru */
2800 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP:
2801 case X86_XCPT_AC: case X86_XCPT_DF: /* 0 */
2802 TRPMSetErrorCode(pVCpu, pVM->rem.s.Env.error_code);
2803 break;
2804 }
2805 }
2806 }
2807
2808 /*
2809 * We're not longer in REM mode.
2810 */
2811 CPUMR3RemLeave(pVCpu,
2812 HMIsEnabled(pVM)
2813 || ( pVM->rem.s.Env.segs[R_SS].newselector
2814 | pVM->rem.s.Env.segs[R_GS].newselector
2815 | pVM->rem.s.Env.segs[R_FS].newselector
2816 | pVM->rem.s.Env.segs[R_ES].newselector
2817 | pVM->rem.s.Env.segs[R_DS].newselector
2818 | pVM->rem.s.Env.segs[R_CS].newselector) == 0
2819 );
2820 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_REM);
2821 pVM->rem.s.fInREM = false;
2822 pVM->rem.s.pCtx = NULL;
2823 pVM->rem.s.Env.pVCpu = NULL;
2824 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2825 Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2826 return VINF_SUCCESS;
2827}
2828
2829
2830/**
2831 * This is called by the disassembler when it wants to update the cpu state
2832 * before for instance doing a register dump.
2833 */
2834static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu)
2835{
2836 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2837 unsigned i;
2838
2839 Assert(pVM->rem.s.fInREM);
2840
2841 /*
2842 * Copy back the registers.
2843 * This is done in the order they are declared in the CPUMCTX structure.
2844 */
2845
2846 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87;
2847 /** @todo FOP */
2848 /** @todo FPUIP */
2849 /** @todo CS */
2850 /** @todo FPUDP */
2851 /** @todo DS */
2852 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2853 pFpuCtx->MXCSR = 0;
2854 pFpuCtx->MXCSR_MASK = 0;
2855
2856 /** @todo check if FPU/XMM was actually used in the recompiler */
2857 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)pFpuCtx);
2858//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2859
2860#ifdef TARGET_X86_64
2861 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2862 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2863 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2864 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2865 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2866 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2867 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2868 pCtx->r8 = pVM->rem.s.Env.regs[8];
2869 pCtx->r9 = pVM->rem.s.Env.regs[9];
2870 pCtx->r10 = pVM->rem.s.Env.regs[10];
2871 pCtx->r11 = pVM->rem.s.Env.regs[11];
2872 pCtx->r12 = pVM->rem.s.Env.regs[12];
2873 pCtx->r13 = pVM->rem.s.Env.regs[13];
2874 pCtx->r14 = pVM->rem.s.Env.regs[14];
2875 pCtx->r15 = pVM->rem.s.Env.regs[15];
2876
2877 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2878#else
2879 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2880 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2881 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2882 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2883 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2884 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2885 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2886
2887 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2888#endif
2889
2890 SYNC_BACK_SREG(es, ES);
2891 SYNC_BACK_SREG(cs, CS);
2892 SYNC_BACK_SREG(ss, SS);
2893 SYNC_BACK_SREG(ds, DS);
2894 SYNC_BACK_SREG(fs, FS);
2895 SYNC_BACK_SREG(gs, GS);
2896
2897#ifdef TARGET_X86_64
2898 pCtx->rip = pVM->rem.s.Env.eip;
2899 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2900#else
2901 pCtx->eip = pVM->rem.s.Env.eip;
2902 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2903#endif
2904
2905 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2906 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2907 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2908#ifdef VBOX_WITH_RAW_MODE
2909 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2910 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2911#endif
2912 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2913
2914 for (i = 0; i < 8; i++)
2915 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2916
2917 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2918 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base)
2919 {
2920 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
2921 STAM_COUNTER_INC(&gStatREMGDTChange);
2922#ifdef VBOX_WITH_RAW_MODE
2923 if (!HMIsEnabled(pVM))
2924 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2925#endif
2926 }
2927
2928 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2929 if (pCtx->idtr.pIdt != (RTGCPTR)pVM->rem.s.Env.idt.base)
2930 {
2931 pCtx->idtr.pIdt = (RTGCPTR)pVM->rem.s.Env.idt.base;
2932 STAM_COUNTER_INC(&gStatREMIDTChange);
2933#ifdef VBOX_WITH_RAW_MODE
2934 if (!HMIsEnabled(pVM))
2935 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2936#endif
2937 }
2938
2939 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2940 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2941 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2942 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2943 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2944 || !(pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2945 )
2946 {
2947 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2948 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2949 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2950 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2951 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2952 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2953 STAM_COUNTER_INC(&gStatREMLDTRChange);
2954#ifdef VBOX_WITH_RAW_MODE
2955 if (!HMIsEnabled(pVM))
2956 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2957#endif
2958 }
2959
2960 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2961 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2962 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2963 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2964 || pCtx->tr.Attr.u != ((pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2965 || !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
2966 )
2967 {
2968 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2969 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2970 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2971 pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT));
2972 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2973 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2974 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2975 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2976 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2977 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2978 Assert(pCtx->tr.Attr.u & ~DESC_INTEL_UNUSABLE);
2979 STAM_COUNTER_INC(&gStatREMTRChange);
2980#ifdef VBOX_WITH_RAW_MODE
2981 if (!HMIsEnabled(pVM))
2982 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2983#endif
2984 }
2985
2986 /* Sysenter MSR */
2987 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2988 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2989 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2990
2991 /* System MSRs. */
2992 pCtx->msrEFER = pVM->rem.s.Env.efer;
2993 pCtx->msrSTAR = pVM->rem.s.Env.star;
2994 pCtx->msrPAT = pVM->rem.s.Env.pat;
2995#ifdef TARGET_X86_64
2996 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2997 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2998 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2999 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
3000#endif
3001
3002}
3003
3004
3005/**
3006 * Update the VMM state information if we're currently in REM.
3007 *
3008 * This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
3009 * we're currently executing in REM and the VMM state is invalid. This method will of
3010 * course check that we're executing in REM before syncing any data over to the VMM.
3011 *
3012 * @param pVM The VM handle.
3013 * @param pVCpu The VMCPU handle.
3014 */
3015REMR3DECL(void) REMR3StateUpdate(PVM pVM, PVMCPU pVCpu)
3016{
3017 if (pVM->rem.s.fInREM)
3018 remR3StateUpdate(pVM, pVCpu);
3019}
3020
3021
3022#undef LOG_GROUP
3023#define LOG_GROUP LOG_GROUP_REM
3024
3025
3026/**
3027 * Notify the recompiler about Address Gate 20 state change.
3028 *
3029 * This notification is required since A20 gate changes are
3030 * initialized from a device driver and the VM might just as
3031 * well be in REM mode as in RAW mode.
3032 *
3033 * @param pVM VM handle.
3034 * @param pVCpu VMCPU handle.
3035 * @param fEnable True if the gate should be enabled.
3036 * False if the gate should be disabled.
3037 */
3038REMR3DECL(void) REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable)
3039{
3040 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
3041 VM_ASSERT_EMT(pVM);
3042
3043 /** @todo SMP and the A20 gate... */
3044 if (pVM->rem.s.Env.pVCpu == pVCpu)
3045 {
3046 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3047 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
3048 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3049 }
3050}
3051
3052
3053/**
3054 * Replays the handler notification changes
3055 * Called in response to VM_FF_REM_HANDLER_NOTIFY from the RAW execution loop.
3056 *
3057 * @param pVM VM handle.
3058 */
3059REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
3060{
3061 /*
3062 * Replay the flushes.
3063 */
3064 LogFlow(("REMR3ReplayHandlerNotifications:\n"));
3065 VM_ASSERT_EMT(pVM);
3066
3067 /** @todo this isn't ensuring correct replay order. */
3068 if (VM_FF_TEST_AND_CLEAR(pVM, VM_FF_REM_HANDLER_NOTIFY))
3069 {
3070 uint32_t idxNext;
3071 uint32_t idxRevHead;
3072 uint32_t idxHead;
3073#ifdef VBOX_STRICT
3074 int32_t c = 0;
3075#endif
3076
3077 /* Lockless purging of pending notifications. */
3078 idxHead = ASMAtomicXchgU32(&pVM->rem.s.idxPendingList, UINT32_MAX);
3079 if (idxHead == UINT32_MAX)
3080 return;
3081 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3082
3083 /*
3084 * Reverse the list to process it in FIFO order.
3085 */
3086 idxRevHead = UINT32_MAX;
3087 do
3088 {
3089 /* Save the index of the next rec. */
3090 idxNext = pVM->rem.s.aHandlerNotifications[idxHead].idxNext;
3091 Assert(idxNext < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || idxNext == UINT32_MAX);
3092 /* Push the record onto the reversed list. */
3093 pVM->rem.s.aHandlerNotifications[idxHead].idxNext = idxRevHead;
3094 idxRevHead = idxHead;
3095 Assert(++c <= RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3096 /* Advance. */
3097 idxHead = idxNext;
3098 } while (idxHead != UINT32_MAX);
3099
3100 /*
3101 * Loop thru the list, reinserting the record into the free list as they are
3102 * processed to avoid having other EMTs running out of entries while we're flushing.
3103 */
3104 idxHead = idxRevHead;
3105 do
3106 {
3107 PREMHANDLERNOTIFICATION pCur = &pVM->rem.s.aHandlerNotifications[idxHead];
3108 uint32_t idxCur;
3109 Assert(--c >= 0);
3110
3111 switch (pCur->enmKind)
3112 {
3113 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
3114 remR3NotifyHandlerPhysicalRegister(pVM,
3115 pCur->u.PhysicalRegister.enmKind,
3116 pCur->u.PhysicalRegister.GCPhys,
3117 pCur->u.PhysicalRegister.cb,
3118 pCur->u.PhysicalRegister.fHasHCHandler);
3119 break;
3120
3121 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
3122 remR3NotifyHandlerPhysicalDeregister(pVM,
3123 pCur->u.PhysicalDeregister.enmKind,
3124 pCur->u.PhysicalDeregister.GCPhys,
3125 pCur->u.PhysicalDeregister.cb,
3126 pCur->u.PhysicalDeregister.fHasHCHandler,
3127 pCur->u.PhysicalDeregister.fRestoreAsRAM);
3128 break;
3129
3130 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
3131 remR3NotifyHandlerPhysicalModify(pVM,
3132 pCur->u.PhysicalModify.enmKind,
3133 pCur->u.PhysicalModify.GCPhysOld,
3134 pCur->u.PhysicalModify.GCPhysNew,
3135 pCur->u.PhysicalModify.cb,
3136 pCur->u.PhysicalModify.fHasHCHandler,
3137 pCur->u.PhysicalModify.fRestoreAsRAM);
3138 break;
3139
3140 default:
3141 AssertReleaseMsgFailed(("enmKind=%d\n", pCur->enmKind));
3142 break;
3143 }
3144
3145 /*
3146 * Advance idxHead.
3147 */
3148 idxCur = idxHead;
3149 idxHead = pCur->idxNext;
3150 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || (idxHead == UINT32_MAX && c == 0));
3151
3152 /*
3153 * Put the record back into the free list.
3154 */
3155 do
3156 {
3157 idxNext = ASMAtomicUoReadU32(&pVM->rem.s.idxFreeList);
3158 ASMAtomicWriteU32(&pCur->idxNext, idxNext);
3159 ASMCompilerBarrier();
3160 } while (!ASMAtomicCmpXchgU32(&pVM->rem.s.idxFreeList, idxCur, idxNext));
3161 } while (idxHead != UINT32_MAX);
3162
3163#ifdef VBOX_STRICT
3164 if (pVM->cCpus == 1)
3165 {
3166 unsigned c;
3167 /* Check that all records are now on the free list. */
3168 for (c = 0, idxNext = pVM->rem.s.idxFreeList; idxNext != UINT32_MAX;
3169 idxNext = pVM->rem.s.aHandlerNotifications[idxNext].idxNext)
3170 c++;
3171 AssertReleaseMsg(c == RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), ("%#x != %#x, idxFreeList=%#x\n", c, RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), pVM->rem.s.idxFreeList));
3172 }
3173#endif
3174 }
3175}
3176
3177
3178/**
3179 * Notify REM about changed code page.
3180 *
3181 * @returns VBox status code.
3182 * @param pVM VM handle.
3183 * @param pVCpu VMCPU handle.
3184 * @param pvCodePage Code page address
3185 */
3186REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage)
3187{
3188#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
3189 int rc;
3190 RTGCPHYS PhysGC;
3191 uint64_t flags;
3192
3193 VM_ASSERT_EMT(pVM);
3194
3195 /*
3196 * Get the physical page address.
3197 */
3198 rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
3199 if (rc == VINF_SUCCESS)
3200 {
3201 /*
3202 * Sync the required registers and flush the whole page.
3203 * (Easier to do the whole page than notifying it about each physical
3204 * byte that was changed.
3205 */
3206 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
3207 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
3208 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
3209 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
3210
3211 tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
3212 }
3213#endif
3214 return VINF_SUCCESS;
3215}
3216
3217
3218/**
3219 * Notification about a successful MMR3PhysRegister() call.
3220 *
3221 * @param pVM VM handle.
3222 * @param GCPhys The physical address the RAM.
3223 * @param cb Size of the memory.
3224 * @param fFlags Flags of the REM_NOTIFY_PHYS_RAM_FLAGS_* defines.
3225 */
3226REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, unsigned fFlags)
3227{
3228 Log(("REMR3NotifyPhysRamRegister: GCPhys=%RGp cb=%RGp fFlags=%#x\n", GCPhys, cb, fFlags));
3229 VM_ASSERT_EMT(pVM);
3230
3231 /*
3232 * Validate input - we trust the caller.
3233 */
3234 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3235 Assert(cb);
3236 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3237 AssertMsg(fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_RAM || fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2, ("%#x\n", fFlags));
3238
3239 /*
3240 * Base ram? Update GCPhysLastRam.
3241 */
3242 if (fFlags & REM_NOTIFY_PHYS_RAM_FLAGS_RAM)
3243 {
3244 if (GCPhys + (cb - 1) > pVM->rem.s.GCPhysLastRam)
3245 {
3246 AssertReleaseMsg(!pVM->rem.s.fGCPhysLastRamFixed, ("GCPhys=%RGp cb=%RGp\n", GCPhys, cb));
3247 pVM->rem.s.GCPhysLastRam = GCPhys + (cb - 1);
3248 }
3249 }
3250
3251 /*
3252 * Register the ram.
3253 */
3254 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3255
3256 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3257 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys, GCPhys);
3258 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3259
3260 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3261}
3262
3263
3264/**
3265 * Notification about a successful MMR3PhysRomRegister() call.
3266 *
3267 * @param pVM VM handle.
3268 * @param GCPhys The physical address of the ROM.
3269 * @param cb The size of the ROM.
3270 * @param pvCopy Pointer to the ROM copy.
3271 * @param fShadow Whether it's currently writable shadow ROM or normal readonly ROM.
3272 * This function will be called when ever the protection of the
3273 * shadow ROM changes (at reset and end of POST).
3274 */
3275REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)
3276{
3277 Log(("REMR3NotifyPhysRomRegister: GCPhys=%RGp cb=%d fShadow=%RTbool\n", GCPhys, cb, fShadow));
3278 VM_ASSERT_EMT(pVM);
3279
3280 /*
3281 * Validate input - we trust the caller.
3282 */
3283 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3284 Assert(cb);
3285 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3286
3287 /*
3288 * Register the rom.
3289 */
3290 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3291
3292 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3293 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys | (fShadow ? 0 : IO_MEM_ROM), GCPhys);
3294 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3295
3296 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3297}
3298
3299
3300/**
3301 * Notification about a successful memory deregistration or reservation.
3302 *
3303 * @param pVM VM Handle.
3304 * @param GCPhys Start physical address.
3305 * @param cb The size of the range.
3306 */
3307REMR3DECL(void) REMR3NotifyPhysRamDeregister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
3308{
3309 Log(("REMR3NotifyPhysRamDeregister: GCPhys=%RGp cb=%d\n", GCPhys, cb));
3310 VM_ASSERT_EMT(pVM);
3311
3312 /*
3313 * Validate input - we trust the caller.
3314 */
3315 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3316 Assert(cb);
3317 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3318
3319 /*
3320 * Unassigning the memory.
3321 */
3322 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3323
3324 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3325 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3326 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3327
3328 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3329}
3330
3331
3332/**
3333 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
3334 *
3335 * @param pVM VM Handle.
3336 * @param enmKind Kind of access handler.
3337 * @param GCPhys Handler range address.
3338 * @param cb Size of the handler range.
3339 * @param fHasHCHandler Set if the handler has a HC callback function.
3340 *
3341 * @remark MMR3PhysRomRegister assumes that this function will not apply the
3342 * Handler memory type to memory which has no HC handler.
3343 */
3344static void remR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3345 bool fHasHCHandler)
3346{
3347 Log(("REMR3NotifyHandlerPhysicalRegister: enmKind=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%d\n",
3348 enmKind, GCPhys, cb, fHasHCHandler));
3349
3350 VM_ASSERT_EMT(pVM);
3351 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3352 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3353
3354
3355 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3356
3357 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3358 if (enmKind == PGMPHYSHANDLERKIND_MMIO)
3359 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iMMIOMemType, GCPhys);
3360 else if (fHasHCHandler)
3361 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iHandlerMemType, GCPhys);
3362 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3363
3364 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3365}
3366
3367/**
3368 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
3369 *
3370 * @param pVM VM Handle.
3371 * @param enmKind Kind of access handler.
3372 * @param GCPhys Handler range address.
3373 * @param cb Size of the handler range.
3374 * @param fHasHCHandler Set if the handler has a HC callback function.
3375 *
3376 * @remark MMR3PhysRomRegister assumes that this function will not apply the
3377 * Handler memory type to memory which has no HC handler.
3378 */
3379REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3380 bool fHasHCHandler)
3381{
3382 REMR3ReplayHandlerNotifications(pVM);
3383
3384 remR3NotifyHandlerPhysicalRegister(pVM, enmKind, GCPhys, cb, fHasHCHandler);
3385}
3386
3387/**
3388 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3389 *
3390 * @param pVM VM Handle.
3391 * @param enmKind Kind of access handler.
3392 * @param GCPhys Handler range address.
3393 * @param cb Size of the handler range.
3394 * @param fHasHCHandler Set if the handler has a HC callback function.
3395 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3396 */
3397static void remR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3398 bool fHasHCHandler, bool fRestoreAsRAM)
3399{
3400 Log(("REMR3NotifyHandlerPhysicalDeregister: enmKind=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool RAM=%08x\n",
3401 enmKind, GCPhys, cb, fHasHCHandler, fRestoreAsRAM, MMR3PhysGetRamSize(pVM)));
3402 VM_ASSERT_EMT(pVM);
3403
3404
3405 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3406
3407 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3408 /** @todo this isn't right, MMIO can (in theory) be restored as RAM. */
3409 if (enmKind == PGMPHYSHANDLERKIND_MMIO)
3410 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3411 else if (fHasHCHandler)
3412 {
3413 if (!fRestoreAsRAM)
3414 {
3415 Assert(GCPhys > MMR3PhysGetRamSize(pVM));
3416 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3417 }
3418 else
3419 {
3420 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3421 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3422 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys, GCPhys);
3423 }
3424 }
3425 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3426
3427 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3428}
3429
3430/**
3431 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3432 *
3433 * @param pVM VM Handle.
3434 * @param enmKind Kind of access handler.
3435 * @param GCPhys Handler range address.
3436 * @param cb Size of the handler range.
3437 * @param fHasHCHandler Set if the handler has a HC callback function.
3438 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3439 */
3440REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3441{
3442 REMR3ReplayHandlerNotifications(pVM);
3443 remR3NotifyHandlerPhysicalDeregister(pVM, enmKind, GCPhys, cb, fHasHCHandler, fRestoreAsRAM);
3444}
3445
3446
3447/**
3448 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3449 *
3450 * @param pVM VM Handle.
3451 * @param enmKind Kind of access handler.
3452 * @param GCPhysOld Old handler range address.
3453 * @param GCPhysNew New handler range address.
3454 * @param cb Size of the handler range.
3455 * @param fHasHCHandler Set if the handler has a HC callback function.
3456 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3457 */
3458static void remR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3459{
3460 Log(("REMR3NotifyHandlerPhysicalModify: enmKind=%d GCPhysOld=%RGp GCPhysNew=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool\n",
3461 enmKind, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM));
3462 VM_ASSERT_EMT(pVM);
3463 AssertReleaseMsg(enmKind != PGMPHYSHANDLERKIND_MMIO, ("enmKind=%d\n", enmKind));
3464
3465 if (fHasHCHandler)
3466 {
3467 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3468
3469 /*
3470 * Reset the old page.
3471 */
3472 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3473 if (!fRestoreAsRAM)
3474 cpu_register_physical_memory_offset(GCPhysOld, cb, IO_MEM_UNASSIGNED, GCPhysOld);
3475 else
3476 {
3477 /* This is not perfect, but it'll do for PD monitoring... */
3478 Assert(cb == PAGE_SIZE);
3479 Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
3480 cpu_register_physical_memory_offset(GCPhysOld, cb, GCPhysOld, GCPhysOld);
3481 }
3482
3483 /*
3484 * Update the new page.
3485 */
3486 Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
3487 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3488 cpu_register_physical_memory_offset(GCPhysNew, cb, pVM->rem.s.iHandlerMemType, GCPhysNew);
3489 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3490
3491 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3492 }
3493}
3494
3495/**
3496 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3497 *
3498 * @param pVM VM Handle.
3499 * @param enmKind Kind of access handler.
3500 * @param GCPhysOld Old handler range address.
3501 * @param GCPhysNew New handler range address.
3502 * @param cb Size of the handler range.
3503 * @param fHasHCHandler Set if the handler has a HC callback function.
3504 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3505 */
3506REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3507{
3508 REMR3ReplayHandlerNotifications(pVM);
3509
3510 remR3NotifyHandlerPhysicalModify(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM);
3511}
3512
3513/**
3514 * Checks if we're handling access to this page or not.
3515 *
3516 * @returns true if we're trapping access.
3517 * @returns false if we aren't.
3518 * @param pVM The VM handle.
3519 * @param GCPhys The physical address.
3520 *
3521 * @remark This function will only work correctly in VBOX_STRICT builds!
3522 */
3523REMR3DECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
3524{
3525#ifdef VBOX_STRICT
3526 ram_addr_t off;
3527 REMR3ReplayHandlerNotifications(pVM);
3528
3529 off = get_phys_page_offset(GCPhys);
3530 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
3531 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
3532 || (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
3533#else
3534 return false;
3535#endif
3536}
3537
3538
3539/**
3540 * Deals with a rare case in get_phys_addr_code where the code
3541 * is being monitored.
3542 *
3543 * It could also be an MMIO page, in which case we will raise a fatal error.
3544 *
3545 * @returns The physical address corresponding to addr.
3546 * @param env The cpu environment.
3547 * @param addr The virtual address.
3548 * @param pTLBEntry The TLB entry.
3549 * @param IoTlbEntry The I/O TLB entry address.
3550 */
3551target_ulong remR3PhysGetPhysicalAddressCode(CPUX86State *env,
3552 target_ulong addr,
3553 CPUTLBEntry *pTLBEntry,
3554 target_phys_addr_t IoTlbEntry)
3555{
3556 PVM pVM = env->pVM;
3557
3558 if ((IoTlbEntry & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
3559 {
3560 /* If code memory is being monitored, appropriate IOTLB entry will have
3561 handler IO type, and addend will provide real physical address, no
3562 matter if we store VA in TLB or not, as handlers are always passed PA */
3563 target_ulong ret = (IoTlbEntry & TARGET_PAGE_MASK) + addr;
3564 return ret;
3565 }
3566 LogRel(("\nTrying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv! (iHandlerMemType=%#x iMMIOMemType=%#x IOTLB=%RGp)\n"
3567 "*** handlers\n",
3568 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType, (RTGCPHYS)IoTlbEntry));
3569 DBGFR3Info(pVM->pUVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
3570 LogRel(("*** mmio\n"));
3571 DBGFR3Info(pVM->pUVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
3572 LogRel(("*** phys\n"));
3573 DBGFR3Info(pVM->pUVM, "phys", NULL, DBGFR3InfoLogRelHlp());
3574 cpu_abort(env, "Trying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
3575 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
3576 AssertFatalFailed();
3577}
3578
3579/**
3580 * Read guest RAM and ROM.
3581 *
3582 * @param SrcGCPhys The source address (guest physical).
3583 * @param pvDst The destination address.
3584 * @param cb Number of bytes
3585 */
3586void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb)
3587{
3588 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3589 VBOX_CHECK_ADDR(SrcGCPhys);
3590 VBOXSTRICTRC rcStrict = PGMPhysRead(cpu_single_env->pVM, SrcGCPhys, pvDst, cb, PGMACCESSORIGIN_REM);
3591 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3592#ifdef VBOX_DEBUG_PHYS
3593 LogRel(("read(%d): %08x\n", cb, (uint32_t)SrcGCPhys));
3594#endif
3595 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3596}
3597
3598
3599/**
3600 * Read guest RAM and ROM, unsigned 8-bit.
3601 *
3602 * @param SrcGCPhys The source address (guest physical).
3603 */
3604RTCCUINTREG remR3PhysReadU8(RTGCPHYS SrcGCPhys)
3605{
3606 uint8_t val;
3607 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3608 VBOX_CHECK_ADDR(SrcGCPhys);
3609 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3610 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3611#ifdef VBOX_DEBUG_PHYS
3612 LogRel(("readu8: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3613#endif
3614 return val;
3615}
3616
3617
3618/**
3619 * Read guest RAM and ROM, signed 8-bit.
3620 *
3621 * @param SrcGCPhys The source address (guest physical).
3622 */
3623RTCCINTREG remR3PhysReadS8(RTGCPHYS SrcGCPhys)
3624{
3625 int8_t val;
3626 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3627 VBOX_CHECK_ADDR(SrcGCPhys);
3628 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3629 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3630#ifdef VBOX_DEBUG_PHYS
3631 LogRel(("reads8: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3632#endif
3633 return val;
3634}
3635
3636
3637/**
3638 * Read guest RAM and ROM, unsigned 16-bit.
3639 *
3640 * @param SrcGCPhys The source address (guest physical).
3641 */
3642RTCCUINTREG remR3PhysReadU16(RTGCPHYS SrcGCPhys)
3643{
3644 uint16_t val;
3645 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3646 VBOX_CHECK_ADDR(SrcGCPhys);
3647 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3648 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3649#ifdef VBOX_DEBUG_PHYS
3650 LogRel(("readu16: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3651#endif
3652 return val;
3653}
3654
3655
3656/**
3657 * Read guest RAM and ROM, signed 16-bit.
3658 *
3659 * @param SrcGCPhys The source address (guest physical).
3660 */
3661RTCCINTREG remR3PhysReadS16(RTGCPHYS SrcGCPhys)
3662{
3663 int16_t val;
3664 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3665 VBOX_CHECK_ADDR(SrcGCPhys);
3666 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3667 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3668#ifdef VBOX_DEBUG_PHYS
3669 LogRel(("reads16: %x <- %08x\n", (uint16_t)val, (uint32_t)SrcGCPhys));
3670#endif
3671 return val;
3672}
3673
3674
3675/**
3676 * Read guest RAM and ROM, unsigned 32-bit.
3677 *
3678 * @param SrcGCPhys The source address (guest physical).
3679 */
3680RTCCUINTREG remR3PhysReadU32(RTGCPHYS SrcGCPhys)
3681{
3682 uint32_t val;
3683 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3684 VBOX_CHECK_ADDR(SrcGCPhys);
3685 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3686 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3687#ifdef VBOX_DEBUG_PHYS
3688 LogRel(("readu32: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3689#endif
3690 return val;
3691}
3692
3693
3694/**
3695 * Read guest RAM and ROM, signed 32-bit.
3696 *
3697 * @param SrcGCPhys The source address (guest physical).
3698 */
3699RTCCINTREG remR3PhysReadS32(RTGCPHYS SrcGCPhys)
3700{
3701 int32_t val;
3702 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3703 VBOX_CHECK_ADDR(SrcGCPhys);
3704 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3705 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3706#ifdef VBOX_DEBUG_PHYS
3707 LogRel(("reads32: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3708#endif
3709 return val;
3710}
3711
3712
3713/**
3714 * Read guest RAM and ROM, unsigned 64-bit.
3715 *
3716 * @param SrcGCPhys The source address (guest physical).
3717 */
3718uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys)
3719{
3720 uint64_t val;
3721 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3722 VBOX_CHECK_ADDR(SrcGCPhys);
3723 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3724 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3725#ifdef VBOX_DEBUG_PHYS
3726 LogRel(("readu64: %llx <- %08x\n", val, (uint32_t)SrcGCPhys));
3727#endif
3728 return val;
3729}
3730
3731
3732/**
3733 * Read guest RAM and ROM, signed 64-bit.
3734 *
3735 * @param SrcGCPhys The source address (guest physical).
3736 */
3737int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys)
3738{
3739 int64_t val;
3740 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3741 VBOX_CHECK_ADDR(SrcGCPhys);
3742 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3743 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3744#ifdef VBOX_DEBUG_PHYS
3745 LogRel(("reads64: %llx <- %08x\n", val, (uint32_t)SrcGCPhys));
3746#endif
3747 return val;
3748}
3749
3750
3751/**
3752 * Write guest RAM.
3753 *
3754 * @param DstGCPhys The destination address (guest physical).
3755 * @param pvSrc The source address.
3756 * @param cb Number of bytes to write
3757 */
3758void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb)
3759{
3760 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3761 VBOX_CHECK_ADDR(DstGCPhys);
3762 VBOXSTRICTRC rcStrict = PGMPhysWrite(cpu_single_env->pVM, DstGCPhys, pvSrc, cb, PGMACCESSORIGIN_REM);
3763 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3764 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3765#ifdef VBOX_DEBUG_PHYS
3766 LogRel(("write(%d): %08x\n", cb, (uint32_t)DstGCPhys));
3767#endif
3768}
3769
3770
3771/**
3772 * Write guest RAM, unsigned 8-bit.
3773 *
3774 * @param DstGCPhys The destination address (guest physical).
3775 * @param val Value
3776 */
3777void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val)
3778{
3779 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3780 VBOX_CHECK_ADDR(DstGCPhys);
3781 PGMR3PhysWriteU8(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3782 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3783#ifdef VBOX_DEBUG_PHYS
3784 LogRel(("writeu8: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3785#endif
3786}
3787
3788
3789/**
3790 * Write guest RAM, unsigned 8-bit.
3791 *
3792 * @param DstGCPhys The destination address (guest physical).
3793 * @param val Value
3794 */
3795void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val)
3796{
3797 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3798 VBOX_CHECK_ADDR(DstGCPhys);
3799 PGMR3PhysWriteU16(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3800 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3801#ifdef VBOX_DEBUG_PHYS
3802 LogRel(("writeu16: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3803#endif
3804}
3805
3806
3807/**
3808 * Write guest RAM, unsigned 32-bit.
3809 *
3810 * @param DstGCPhys The destination address (guest physical).
3811 * @param val Value
3812 */
3813void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val)
3814{
3815 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3816 VBOX_CHECK_ADDR(DstGCPhys);
3817 PGMR3PhysWriteU32(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3818 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3819#ifdef VBOX_DEBUG_PHYS
3820 LogRel(("writeu32: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3821#endif
3822}
3823
3824
3825/**
3826 * Write guest RAM, unsigned 64-bit.
3827 *
3828 * @param DstGCPhys The destination address (guest physical).
3829 * @param val Value
3830 */
3831void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val)
3832{
3833 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3834 VBOX_CHECK_ADDR(DstGCPhys);
3835 PGMR3PhysWriteU64(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3836 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3837#ifdef VBOX_DEBUG_PHYS
3838 LogRel(("writeu64: %llx -> %08x\n", val, (uint32_t)DstGCPhys));
3839#endif
3840}
3841
3842#undef LOG_GROUP
3843#define LOG_GROUP LOG_GROUP_REM_MMIO
3844
3845/** Read MMIO memory. */
3846static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys)
3847{
3848 CPUX86State *env = (CPUX86State *)pvEnv;
3849 uint32_t u32 = 0;
3850 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 1);
3851 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3852 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", (RTGCPHYS)GCPhys, u32));
3853 return u32;
3854}
3855
3856/** Read MMIO memory. */
3857static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys)
3858{
3859 CPUX86State *env = (CPUX86State *)pvEnv;
3860 uint32_t u32 = 0;
3861 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 2);
3862 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3863 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", (RTGCPHYS)GCPhys, u32));
3864 return u32;
3865}
3866
3867/** Read MMIO memory. */
3868static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys)
3869{
3870 CPUX86State *env = (CPUX86State *)pvEnv;
3871 uint32_t u32 = 0;
3872 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 4);
3873 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3874 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", (RTGCPHYS)GCPhys, u32));
3875 return u32;
3876}
3877
3878/** Write to MMIO memory. */
3879static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3880{
3881 CPUX86State *env = (CPUX86State *)pvEnv;
3882 int rc;
3883 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3884 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 1);
3885 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3886}
3887
3888/** Write to MMIO memory. */
3889static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3890{
3891 CPUX86State *env = (CPUX86State *)pvEnv;
3892 int rc;
3893 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3894 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 2);
3895 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3896}
3897
3898/** Write to MMIO memory. */
3899static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3900{
3901 CPUX86State *env = (CPUX86State *)pvEnv;
3902 int rc;
3903 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3904 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 4);
3905 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3906}
3907
3908
3909#undef LOG_GROUP
3910#define LOG_GROUP LOG_GROUP_REM_HANDLER
3911
3912/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3913
3914static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3915{
3916 uint8_t u8;
3917 Log2(("remR3HandlerReadU8: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3918 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8), PGMACCESSORIGIN_REM);
3919 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3920 return u8;
3921}
3922
3923static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3924{
3925 uint16_t u16;
3926 Log2(("remR3HandlerReadU16: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3927 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16), PGMACCESSORIGIN_REM);
3928 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3929 return u16;
3930}
3931
3932static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3933{
3934 uint32_t u32;
3935 Log2(("remR3HandlerReadU32: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3936 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32), PGMACCESSORIGIN_REM);
3937 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3938 return u32;
3939}
3940
3941static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3942{
3943 Log2(("remR3HandlerWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3944 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t), PGMACCESSORIGIN_REM);
3945 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3946}
3947
3948static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3949{
3950 Log2(("remR3HandlerWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3951 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t), PGMACCESSORIGIN_REM);
3952 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3953}
3954
3955static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3956{
3957 Log2(("remR3HandlerWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3958 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t), PGMACCESSORIGIN_REM);
3959 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3960}
3961
3962/* -+- disassembly -+- */
3963
3964#undef LOG_GROUP
3965#define LOG_GROUP LOG_GROUP_REM_DISAS
3966
3967
3968/**
3969 * Enables or disables singled stepped disassembly.
3970 *
3971 * @returns VBox status code.
3972 * @param pVM VM handle.
3973 * @param fEnable To enable set this flag, to disable clear it.
3974 */
3975static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3976{
3977 LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3978 VM_ASSERT_EMT(pVM);
3979
3980 if (fEnable)
3981 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3982 else
3983 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3984#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
3985 cpu_single_step(&pVM->rem.s.Env, fEnable);
3986#endif
3987 return VINF_SUCCESS;
3988}
3989
3990
3991/**
3992 * Enables or disables singled stepped disassembly.
3993 *
3994 * @returns VBox status code.
3995 * @param pVM VM handle.
3996 * @param fEnable To enable set this flag, to disable clear it.
3997 */
3998REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3999{
4000 int rc;
4001
4002 LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
4003 if (VM_IS_EMT(pVM))
4004 return remR3DisasEnableStepping(pVM, fEnable);
4005
4006 rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
4007 AssertRC(rc);
4008 return rc;
4009}
4010
4011
4012#ifdef VBOX_WITH_DEBUGGER
4013/**
4014 * External Debugger Command: .remstep [on|off|1|0]
4015 */
4016static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM,
4017 PCDBGCVAR paArgs, unsigned cArgs)
4018{
4019 int rc;
4020 PVM pVM = pUVM->pVM;
4021
4022 if (cArgs == 0)
4023 /*
4024 * Print the current status.
4025 */
4026 rc = DBGCCmdHlpPrintf(pCmdHlp, "DisasStepping is %s\n",
4027 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
4028 else
4029 {
4030 /*
4031 * Convert the argument and change the mode.
4032 */
4033 bool fEnable;
4034 rc = DBGCCmdHlpVarToBool(pCmdHlp, &paArgs[0], &fEnable);
4035 if (RT_SUCCESS(rc))
4036 {
4037 rc = REMR3DisasEnableStepping(pVM, fEnable);
4038 if (RT_SUCCESS(rc))
4039 rc = DBGCCmdHlpPrintf(pCmdHlp, "DisasStepping was %s\n", fEnable ? "enabled" : "disabled");
4040 else
4041 rc = DBGCCmdHlpFailRc(pCmdHlp, pCmd, rc, "REMR3DisasEnableStepping");
4042 }
4043 else
4044 rc = DBGCCmdHlpFailRc(pCmdHlp, pCmd, rc, "DBGCCmdHlpVarToBool");
4045 }
4046 return rc;
4047}
4048#endif /* VBOX_WITH_DEBUGGER */
4049
4050
4051/**
4052 * Disassembles one instruction and prints it to the log.
4053 *
4054 * @returns Success indicator.
4055 * @param env Pointer to the recompiler CPU structure.
4056 * @param f32BitCode Indicates that whether or not the code should
4057 * be disassembled as 16 or 32 bit. If -1 the CS
4058 * selector will be inspected.
4059 * @param pszPrefix
4060 */
4061bool remR3DisasInstr(CPUX86State *env, int f32BitCode, char *pszPrefix)
4062{
4063 PVM pVM = env->pVM;
4064 const bool fLog = LogIsEnabled();
4065 const bool fLog2 = LogIs2Enabled();
4066 int rc = VINF_SUCCESS;
4067
4068 /*
4069 * Don't bother if there ain't any log output to do.
4070 */
4071 if (!fLog && !fLog2)
4072 return true;
4073
4074 /*
4075 * Update the state so DBGF reads the correct register values.
4076 */
4077 remR3StateUpdate(pVM, env->pVCpu);
4078
4079 /*
4080 * Log registers if requested.
4081 */
4082 if (fLog2)
4083 DBGFR3_INFO_LOG(pVM, env->pVCpu, "cpumguest", pszPrefix);
4084
4085 /*
4086 * Disassemble to log.
4087 */
4088 if (fLog)
4089 {
4090 PVMCPU pVCpu = VMMGetCpu(pVM);
4091 char szBuf[256];
4092 szBuf[0] = '\0';
4093 int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM,
4094 pVCpu->idCpu,
4095 0, /* Sel */ 0, /* GCPtr */
4096 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
4097 szBuf,
4098 sizeof(szBuf),
4099 NULL);
4100 if (RT_FAILURE(rc))
4101 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrEx failed with rc=%Rrc\n", rc);
4102 if (pszPrefix && *pszPrefix)
4103 RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
4104 else
4105 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
4106 }
4107
4108 return RT_SUCCESS(rc);
4109}
4110
4111
4112/**
4113 * Disassemble recompiled code.
4114 *
4115 * @param phFileIgnored Ignored, logfile usually.
4116 * @param pvCode Pointer to the code block.
4117 * @param cb Size of the code block.
4118 */
4119void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
4120{
4121 if (LogIs2Enabled())
4122 {
4123 unsigned off = 0;
4124 char szOutput[256];
4125 DISCPUSTATE Cpu;
4126#ifdef RT_ARCH_X86
4127 DISCPUMODE enmCpuMode = DISCPUMODE_32BIT;
4128#else
4129 DISCPUMODE enmCpuMode = DISCPUMODE_64BIT;
4130#endif
4131
4132 RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
4133 while (off < cb)
4134 {
4135 uint32_t cbInstr;
4136 int rc = DISInstrToStr((uint8_t const *)pvCode + off, enmCpuMode,
4137 &Cpu, &cbInstr, szOutput, sizeof(szOutput));
4138 if (RT_SUCCESS(rc))
4139 RTLogPrintf("%s", szOutput);
4140 else
4141 {
4142 RTLogPrintf("disas error %Rrc\n", rc);
4143 cbInstr = 1;
4144 }
4145 off += cbInstr;
4146 }
4147 }
4148}
4149
4150
4151/**
4152 * Disassemble guest code.
4153 *
4154 * @param phFileIgnored Ignored, logfile usually.
4155 * @param uCode The guest address of the code to disassemble. (flat?)
4156 * @param cb Number of bytes to disassemble.
4157 * @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
4158 */
4159void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
4160{
4161 if (LogIs2Enabled())
4162 {
4163 PVM pVM = cpu_single_env->pVM;
4164 PVMCPU pVCpu = cpu_single_env->pVCpu;
4165 RTSEL cs;
4166 RTGCUINTPTR eip;
4167
4168 Assert(pVCpu);
4169
4170 /*
4171 * Update the state so DBGF reads the correct register values (flags).
4172 */
4173 remR3StateUpdate(pVM, pVCpu);
4174
4175 /*
4176 * Do the disassembling.
4177 */
4178 RTLogPrintf("Guest Code: PC=%llx %llx bytes fFlags=%d\n", (uint64_t)uCode, (uint64_t)cb, fFlags);
4179 cs = cpu_single_env->segs[R_CS].selector;
4180 eip = uCode - cpu_single_env->segs[R_CS].base;
4181 for (;;)
4182 {
4183 char szBuf[256];
4184 uint32_t cbInstr;
4185 int rc = DBGFR3DisasInstrEx(pVM->pUVM,
4186 pVCpu->idCpu,
4187 cs,
4188 eip,
4189 DBGF_DISAS_FLAGS_DEFAULT_MODE,
4190 szBuf, sizeof(szBuf),
4191 &cbInstr);
4192 if (RT_SUCCESS(rc))
4193 RTLogPrintf("%llx %s\n", (uint64_t)uCode, szBuf);
4194 else
4195 {
4196 RTLogPrintf("%llx %04x:%llx: %s\n", (uint64_t)uCode, cs, (uint64_t)eip, szBuf);
4197 cbInstr = 1;
4198 }
4199
4200 /* next */
4201 if (cb <= cbInstr)
4202 break;
4203 cb -= cbInstr;
4204 uCode += cbInstr;
4205 eip += cbInstr;
4206 }
4207 }
4208}
4209
4210
4211/**
4212 * Looks up a guest symbol.
4213 *
4214 * @returns Pointer to symbol name. This is a static buffer.
4215 * @param orig_addr The address in question.
4216 */
4217const char *lookup_symbol(target_ulong orig_addr)
4218{
4219 PVM pVM = cpu_single_env->pVM;
4220 RTGCINTPTR off = 0;
4221 RTDBGSYMBOL Sym;
4222 DBGFADDRESS Addr;
4223
4224 int rc = DBGFR3AsSymbolByAddr(pVM->pUVM, DBGF_AS_GLOBAL, DBGFR3AddrFromFlat(pVM->pUVM, &Addr, orig_addr),
4225 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL, &off, &Sym, NULL /*phMod*/);
4226 if (RT_SUCCESS(rc))
4227 {
4228 static char szSym[sizeof(Sym.szName) + 48];
4229 if (!off)
4230 RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
4231 else if (off > 0)
4232 RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
4233 else
4234 RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
4235 return szSym;
4236 }
4237 return "<N/A>";
4238}
4239
4240
4241#undef LOG_GROUP
4242#define LOG_GROUP LOG_GROUP_REM
4243
4244
4245/* -+- FF notifications -+- */
4246
4247/**
4248 * Notification about the interrupt FF being set.
4249 *
4250 * @param pVM VM Handle.
4251 * @param pVCpu VMCPU Handle.
4252 * @thread The emulation thread.
4253 */
4254REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu)
4255{
4256#ifndef IEM_VERIFICATION_MODE
4257 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
4258 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
4259 if (pVM->rem.s.fInREM)
4260 {
4261 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4262 CPU_INTERRUPT_EXTERNAL_HARD);
4263 }
4264#endif
4265}
4266
4267
4268/**
4269 * Notification about the interrupt FF being set.
4270 *
4271 * @param pVM VM Handle.
4272 * @param pVCpu VMCPU Handle.
4273 * @thread Any.
4274 */
4275REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu)
4276{
4277 LogFlow(("REMR3NotifyInterruptClear:\n"));
4278 if (pVM->rem.s.fInREM)
4279 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
4280}
4281
4282
4283/**
4284 * Notification about pending timer(s).
4285 *
4286 * @param pVM VM Handle.
4287 * @param pVCpuDst The target cpu for this notification.
4288 * TM will not broadcast pending timer events, but use
4289 * a dedicated EMT for them. So, only interrupt REM
4290 * execution if the given CPU is executing in REM.
4291 * @thread Any.
4292 */
4293REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM, PVMCPU pVCpuDst)
4294{
4295#ifndef IEM_VERIFICATION_MODE
4296#ifndef DEBUG_bird
4297 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
4298#endif
4299 if (pVM->rem.s.fInREM)
4300 {
4301 if (pVM->rem.s.Env.pVCpu == pVCpuDst)
4302 {
4303 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: setting\n"));
4304 ASMAtomicOrS32((int32_t volatile *)&pVM->rem.s.Env.interrupt_request,
4305 CPU_INTERRUPT_EXTERNAL_TIMER);
4306 }
4307 else
4308 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: pVCpu:%p != pVCpuDst:%p\n", pVM->rem.s.Env.pVCpu, pVCpuDst));
4309 }
4310 else
4311 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: !fInREM; cpu state=%d\n", VMCPU_GET_STATE(pVCpuDst)));
4312#endif
4313}
4314
4315
4316/**
4317 * Notification about pending DMA transfers.
4318 *
4319 * @param pVM VM Handle.
4320 * @thread Any.
4321 */
4322REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
4323{
4324#ifndef IEM_VERIFICATION_MODE
4325 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
4326 if (pVM->rem.s.fInREM)
4327 {
4328 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4329 CPU_INTERRUPT_EXTERNAL_DMA);
4330 }
4331#endif
4332}
4333
4334
4335/**
4336 * Notification about pending timer(s).
4337 *
4338 * @param pVM VM Handle.
4339 * @thread Any.
4340 */
4341REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
4342{
4343#ifndef IEM_VERIFICATION_MODE
4344 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
4345 if (pVM->rem.s.fInREM)
4346 {
4347 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4348 CPU_INTERRUPT_EXTERNAL_EXIT);
4349 }
4350#endif
4351}
4352
4353
4354/**
4355 * Notification about pending FF set by an external thread.
4356 *
4357 * @param pVM VM handle.
4358 * @thread Any.
4359 */
4360REMR3DECL(void) REMR3NotifyFF(PVM pVM)
4361{
4362#ifndef IEM_VERIFICATION_MODE
4363 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
4364 if (pVM->rem.s.fInREM)
4365 {
4366 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4367 CPU_INTERRUPT_EXTERNAL_EXIT);
4368 }
4369#endif
4370}
4371
4372
4373#ifdef VBOX_WITH_STATISTICS
4374void remR3ProfileStart(int statcode)
4375{
4376 STAMPROFILEADV *pStat;
4377 switch(statcode)
4378 {
4379 case STATS_EMULATE_SINGLE_INSTR:
4380 pStat = &gStatExecuteSingleInstr;
4381 break;
4382 case STATS_QEMU_COMPILATION:
4383 pStat = &gStatCompilationQEmu;
4384 break;
4385 case STATS_QEMU_RUN_EMULATED_CODE:
4386 pStat = &gStatRunCodeQEmu;
4387 break;
4388 case STATS_QEMU_TOTAL:
4389 pStat = &gStatTotalTimeQEmu;
4390 break;
4391 case STATS_QEMU_RUN_TIMERS:
4392 pStat = &gStatTimers;
4393 break;
4394 case STATS_TLB_LOOKUP:
4395 pStat= &gStatTBLookup;
4396 break;
4397 case STATS_IRQ_HANDLING:
4398 pStat= &gStatIRQ;
4399 break;
4400 case STATS_RAW_CHECK:
4401 pStat = &gStatRawCheck;
4402 break;
4403
4404 default:
4405 AssertMsgFailed(("unknown stat %d\n", statcode));
4406 return;
4407 }
4408 STAM_PROFILE_ADV_START(pStat, a);
4409}
4410
4411
4412void remR3ProfileStop(int statcode)
4413{
4414 STAMPROFILEADV *pStat;
4415 switch(statcode)
4416 {
4417 case STATS_EMULATE_SINGLE_INSTR:
4418 pStat = &gStatExecuteSingleInstr;
4419 break;
4420 case STATS_QEMU_COMPILATION:
4421 pStat = &gStatCompilationQEmu;
4422 break;
4423 case STATS_QEMU_RUN_EMULATED_CODE:
4424 pStat = &gStatRunCodeQEmu;
4425 break;
4426 case STATS_QEMU_TOTAL:
4427 pStat = &gStatTotalTimeQEmu;
4428 break;
4429 case STATS_QEMU_RUN_TIMERS:
4430 pStat = &gStatTimers;
4431 break;
4432 case STATS_TLB_LOOKUP:
4433 pStat= &gStatTBLookup;
4434 break;
4435 case STATS_IRQ_HANDLING:
4436 pStat= &gStatIRQ;
4437 break;
4438 case STATS_RAW_CHECK:
4439 pStat = &gStatRawCheck;
4440 break;
4441 default:
4442 AssertMsgFailed(("unknown stat %d\n", statcode));
4443 return;
4444 }
4445 STAM_PROFILE_ADV_STOP(pStat, a);
4446}
4447#endif
4448
4449/**
4450 * Raise an RC, force rem exit.
4451 *
4452 * @param pVM VM handle.
4453 * @param rc The rc.
4454 */
4455void remR3RaiseRC(PVM pVM, int rc)
4456{
4457 Log(("remR3RaiseRC: rc=%Rrc\n", rc));
4458 Assert(pVM->rem.s.fInREM);
4459 VM_ASSERT_EMT(pVM);
4460 pVM->rem.s.rc = rc;
4461 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
4462}
4463
4464
4465/* -+- timers -+- */
4466
4467uint64_t cpu_get_tsc(CPUX86State *env)
4468{
4469 STAM_COUNTER_INC(&gStatCpuGetTSC);
4470 return TMCpuTickGet(env->pVCpu);
4471}
4472
4473
4474/* -+- interrupts -+- */
4475
4476void cpu_set_ferr(CPUX86State *env)
4477{
4478 int rc = PDMIsaSetIrq(env->pVM, 13, 1, 0 /*uTagSrc*/);
4479 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
4480}
4481
4482int cpu_get_pic_interrupt(CPUX86State *env)
4483{
4484 uint8_t u8Interrupt;
4485 int rc;
4486
4487 if (VMCPU_FF_TEST_AND_CLEAR(env->pVCpu, VMCPU_FF_UPDATE_APIC))
4488 APICUpdatePendingInterrupts(env->pVCpu);
4489
4490 /* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
4491 * In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
4492 * with the (a)pic.
4493 */
4494 /* Note! We assume we will go directly to the recompiler to handle the pending interrupt! */
4495 rc = PDMGetInterrupt(env->pVCpu, &u8Interrupt);
4496 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Rrc pc=%04x:%08llx ~flags=%08llx\n",
4497 u8Interrupt, rc, env->segs[R_CS].selector, (uint64_t)env->eip, (uint64_t)env->eflags));
4498 if (RT_SUCCESS(rc))
4499 {
4500 if (VMCPU_FF_IS_PENDING(env->pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
4501 env->interrupt_request |= CPU_INTERRUPT_HARD;
4502 return u8Interrupt;
4503 }
4504 return -1;
4505}
4506
4507
4508/* -+- local apic -+- */
4509
4510#if 0 /* CPUMSetGuestMsr does this now. */
4511void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4512{
4513 int rc = PDMApicSetBase(env->pVM, val);
4514 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Rrc\n", val, rc)); NOREF(rc);
4515}
4516#endif
4517
4518uint64_t cpu_get_apic_base(CPUX86State *env)
4519{
4520 uint64_t u64;
4521 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64);
4522 if (RT_SUCCESS(rcStrict))
4523 {
4524 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4525 return u64;
4526 }
4527 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
4528 return 0;
4529}
4530
4531void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4532{
4533 int rc = APICSetTpr(env->pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4534 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Rrc\n", val, rc)); NOREF(rc);
4535}
4536
4537uint8_t cpu_get_apic_tpr(CPUX86State *env)
4538{
4539 uint8_t u8;
4540 int rc = APICGetTpr(env->pVCpu, &u8, NULL, NULL);
4541 if (RT_SUCCESS(rc))
4542 {
4543 LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4544 return u8 >> 4; /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4545 }
4546 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Rrc)\n", rc));
4547 return 0;
4548}
4549
4550/**
4551 * Read an MSR.
4552 *
4553 * @retval 0 success.
4554 * @retval -1 failure, raise \#GP(0).
4555 * @param env The cpu state.
4556 * @param idMsr The MSR to read.
4557 * @param puValue Where to return the value.
4558 */
4559int cpu_rdmsr(CPUX86State *env, uint32_t idMsr, uint64_t *puValue)
4560{
4561 Assert(env->pVCpu);
4562 return CPUMQueryGuestMsr(env->pVCpu, idMsr, puValue) == VINF_SUCCESS ? 0 : -1;
4563}
4564
4565/**
4566 * Write to an MSR.
4567 *
4568 * @retval 0 success.
4569 * @retval -1 failure, raise \#GP(0).
4570 * @param env The cpu state.
4571 * @param idMsr The MSR to write to.
4572 * @param uValue The value to write.
4573 */
4574int cpu_wrmsr(CPUX86State *env, uint32_t idMsr, uint64_t uValue)
4575{
4576 Assert(env->pVCpu);
4577 return CPUMSetGuestMsr(env->pVCpu, idMsr, uValue) == VINF_SUCCESS ? 0 : -1;
4578}
4579
4580/* -+- I/O Ports -+- */
4581
4582#undef LOG_GROUP
4583#define LOG_GROUP LOG_GROUP_REM_IOPORT
4584
4585void cpu_outb(CPUX86State *env, pio_addr_t addr, uint8_t val)
4586{
4587 int rc;
4588
4589 if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4590 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4591
4592 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 1);
4593 if (RT_LIKELY(rc == VINF_SUCCESS))
4594 return;
4595 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4596 {
4597 Log(("cpu_outb: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4598 remR3RaiseRC(env->pVM, rc);
4599 return;
4600 }
4601 remAbort(rc, __FUNCTION__);
4602}
4603
4604void cpu_outw(CPUX86State *env, pio_addr_t addr, uint16_t val)
4605{
4606 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4607 int rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 2);
4608 if (RT_LIKELY(rc == VINF_SUCCESS))
4609 return;
4610 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4611 {
4612 Log(("cpu_outw: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4613 remR3RaiseRC(env->pVM, rc);
4614 return;
4615 }
4616 remAbort(rc, __FUNCTION__);
4617}
4618
4619void cpu_outl(CPUX86State *env, pio_addr_t addr, uint32_t val)
4620{
4621 int rc;
4622 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4623 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 4);
4624 if (RT_LIKELY(rc == VINF_SUCCESS))
4625 return;
4626 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4627 {
4628 Log(("cpu_outl: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4629 remR3RaiseRC(env->pVM, rc);
4630 return;
4631 }
4632 remAbort(rc, __FUNCTION__);
4633}
4634
4635uint8_t cpu_inb(CPUX86State *env, pio_addr_t addr)
4636{
4637 uint32_t u32 = 0;
4638 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 1);
4639 if (RT_LIKELY(rc == VINF_SUCCESS))
4640 {
4641 if (/*addr != 0x61 && */addr != 0x71)
4642 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4643 return (uint8_t)u32;
4644 }
4645 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4646 {
4647 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4648 remR3RaiseRC(env->pVM, rc);
4649 return (uint8_t)u32;
4650 }
4651 remAbort(rc, __FUNCTION__);
4652 return UINT8_C(0xff);
4653}
4654
4655uint16_t cpu_inw(CPUX86State *env, pio_addr_t addr)
4656{
4657 uint32_t u32 = 0;
4658 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 2);
4659 if (RT_LIKELY(rc == VINF_SUCCESS))
4660 {
4661 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4662 return (uint16_t)u32;
4663 }
4664 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4665 {
4666 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4667 remR3RaiseRC(env->pVM, rc);
4668 return (uint16_t)u32;
4669 }
4670 remAbort(rc, __FUNCTION__);
4671 return UINT16_C(0xffff);
4672}
4673
4674uint32_t cpu_inl(CPUX86State *env, pio_addr_t addr)
4675{
4676 uint32_t u32 = 0;
4677 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 4);
4678 if (RT_LIKELY(rc == VINF_SUCCESS))
4679 {
4680 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4681 return u32;
4682 }
4683 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4684 {
4685 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4686 remR3RaiseRC(env->pVM, rc);
4687 return u32;
4688 }
4689 remAbort(rc, __FUNCTION__);
4690 return UINT32_C(0xffffffff);
4691}
4692
4693#undef LOG_GROUP
4694#define LOG_GROUP LOG_GROUP_REM
4695
4696
4697/* -+- helpers and misc other interfaces -+- */
4698
4699/**
4700 * Perform the CPUID instruction.
4701 *
4702 * @param env Pointer to the recompiler CPU structure.
4703 * @param idx The CPUID leaf (eax).
4704 * @param idxSub The CPUID sub-leaf (ecx) where applicable.
4705 * @param pEAX Where to store eax.
4706 * @param pEBX Where to store ebx.
4707 * @param pECX Where to store ecx.
4708 * @param pEDX Where to store edx.
4709 */
4710void cpu_x86_cpuid(CPUX86State *env, uint32_t idx, uint32_t idxSub,
4711 uint32_t *pEAX, uint32_t *pEBX, uint32_t *pECX, uint32_t *pEDX)
4712{
4713 NOREF(idxSub);
4714 CPUMGetGuestCpuId(env->pVCpu, idx, idxSub, pEAX, pEBX, pECX, pEDX);
4715}
4716
4717
4718#if 0 /* not used */
4719/**
4720 * Interface for qemu hardware to report back fatal errors.
4721 */
4722void hw_error(const char *pszFormat, ...)
4723{
4724 /*
4725 * Bitch about it.
4726 */
4727 /** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4728 * this in my Odin32 tree at home! */
4729 va_list args;
4730 va_start(args, pszFormat);
4731 RTLogPrintf("fatal error in virtual hardware:");
4732 RTLogPrintfV(pszFormat, args);
4733 va_end(args);
4734 AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4735
4736 /*
4737 * If we're in REM context we'll sync back the state before 'jumping' to
4738 * the EMs failure handling.
4739 */
4740 PVM pVM = cpu_single_env->pVM;
4741 if (pVM->rem.s.fInREM)
4742 REMR3StateBack(pVM);
4743 EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4744 AssertMsgFailed(("EMR3FatalError returned!\n"));
4745}
4746#endif
4747
4748/**
4749 * Interface for the qemu cpu to report unhandled situation
4750 * raising a fatal VM error.
4751 */
4752void cpu_abort(CPUX86State *env, const char *pszFormat, ...)
4753{
4754 va_list va;
4755 PVM pVM;
4756 PVMCPU pVCpu;
4757 char szMsg[256];
4758
4759 /*
4760 * Bitch about it.
4761 */
4762 RTLogFlags(NULL, "nodisabled nobuffered");
4763 RTLogFlush(NULL);
4764
4765 va_start(va, pszFormat);
4766#if defined(RT_OS_WINDOWS) && ARCH_BITS == 64
4767 /* It's a bit complicated when mixing MSC and GCC on AMD64. This is a bit ugly, but it works. */
4768 unsigned cArgs = 0;
4769 uintptr_t auArgs[6] = {0,0,0,0,0,0};
4770 const char *psz = strchr(pszFormat, '%');
4771 while (psz && cArgs < 6)
4772 {
4773 auArgs[cArgs++] = va_arg(va, uintptr_t);
4774 psz = strchr(psz + 1, '%');
4775 }
4776 switch (cArgs)
4777 {
4778 case 1: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0]); break;
4779 case 2: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1]); break;
4780 case 3: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2]); break;
4781 case 4: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3]); break;
4782 case 5: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3], auArgs[4]); break;
4783 case 6: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3], auArgs[4], auArgs[5]); break;
4784 default:
4785 case 0: RTStrPrintf(szMsg, sizeof(szMsg), "%s", pszFormat); break;
4786 }
4787#else
4788 RTStrPrintfV(szMsg, sizeof(szMsg), pszFormat, va);
4789#endif
4790 va_end(va);
4791
4792 RTLogPrintf("fatal error in recompiler cpu: %s\n", szMsg);
4793 RTLogRelPrintf("fatal error in recompiler cpu: %s\n", szMsg);
4794
4795 /*
4796 * If we're in REM context we'll sync back the state before 'jumping' to
4797 * the EMs failure handling.
4798 */
4799 pVM = cpu_single_env->pVM;
4800 pVCpu = cpu_single_env->pVCpu;
4801 Assert(pVCpu);
4802
4803 if (pVM->rem.s.fInREM)
4804 REMR3StateBack(pVM, pVCpu);
4805 EMR3FatalError(pVCpu, VERR_REM_VIRTUAL_CPU_ERROR);
4806 AssertMsgFailed(("EMR3FatalError returned!\n"));
4807}
4808
4809
4810/**
4811 * Aborts the VM.
4812 *
4813 * @param rc VBox error code.
4814 * @param pszTip Hint about why/when this happened.
4815 */
4816void remAbort(int rc, const char *pszTip)
4817{
4818 PVM pVM;
4819 PVMCPU pVCpu;
4820
4821 /*
4822 * Bitch about it.
4823 */
4824 RTLogPrintf("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip);
4825 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip));
4826
4827 /*
4828 * Jump back to where we entered the recompiler.
4829 */
4830 pVM = cpu_single_env->pVM;
4831 pVCpu = cpu_single_env->pVCpu;
4832 Assert(pVCpu);
4833
4834 if (pVM->rem.s.fInREM)
4835 REMR3StateBack(pVM, pVCpu);
4836
4837 EMR3FatalError(pVCpu, rc);
4838 AssertMsgFailed(("EMR3FatalError returned!\n"));
4839}
4840
4841
4842/**
4843 * Dumps a linux system call.
4844 * @param pVCpu VMCPU handle.
4845 */
4846void remR3DumpLnxSyscall(PVMCPU pVCpu)
4847{
4848 static const char *apsz[] =
4849 {
4850 "sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4851 "sys_exit",
4852 "sys_fork",
4853 "sys_read",
4854 "sys_write",
4855 "sys_open", /* 5 */
4856 "sys_close",
4857 "sys_waitpid",
4858 "sys_creat",
4859 "sys_link",
4860 "sys_unlink", /* 10 */
4861 "sys_execve",
4862 "sys_chdir",
4863 "sys_time",
4864 "sys_mknod",
4865 "sys_chmod", /* 15 */
4866 "sys_lchown16",
4867 "sys_ni_syscall", /* old break syscall holder */
4868 "sys_stat",
4869 "sys_lseek",
4870 "sys_getpid", /* 20 */
4871 "sys_mount",
4872 "sys_oldumount",
4873 "sys_setuid16",
4874 "sys_getuid16",
4875 "sys_stime", /* 25 */
4876 "sys_ptrace",
4877 "sys_alarm",
4878 "sys_fstat",
4879 "sys_pause",
4880 "sys_utime", /* 30 */
4881 "sys_ni_syscall", /* old stty syscall holder */
4882 "sys_ni_syscall", /* old gtty syscall holder */
4883 "sys_access",
4884 "sys_nice",
4885 "sys_ni_syscall", /* 35 - old ftime syscall holder */
4886 "sys_sync",
4887 "sys_kill",
4888 "sys_rename",
4889 "sys_mkdir",
4890 "sys_rmdir", /* 40 */
4891 "sys_dup",
4892 "sys_pipe",
4893 "sys_times",
4894 "sys_ni_syscall", /* old prof syscall holder */
4895 "sys_brk", /* 45 */
4896 "sys_setgid16",
4897 "sys_getgid16",
4898 "sys_signal",
4899 "sys_geteuid16",
4900 "sys_getegid16", /* 50 */
4901 "sys_acct",
4902 "sys_umount", /* recycled never used phys() */
4903 "sys_ni_syscall", /* old lock syscall holder */
4904 "sys_ioctl",
4905 "sys_fcntl", /* 55 */
4906 "sys_ni_syscall", /* old mpx syscall holder */
4907 "sys_setpgid",
4908 "sys_ni_syscall", /* old ulimit syscall holder */
4909 "sys_olduname",
4910 "sys_umask", /* 60 */
4911 "sys_chroot",
4912 "sys_ustat",
4913 "sys_dup2",
4914 "sys_getppid",
4915 "sys_getpgrp", /* 65 */
4916 "sys_setsid",
4917 "sys_sigaction",
4918 "sys_sgetmask",
4919 "sys_ssetmask",
4920 "sys_setreuid16", /* 70 */
4921 "sys_setregid16",
4922 "sys_sigsuspend",
4923 "sys_sigpending",
4924 "sys_sethostname",
4925 "sys_setrlimit", /* 75 */
4926 "sys_old_getrlimit",
4927 "sys_getrusage",
4928 "sys_gettimeofday",
4929 "sys_settimeofday",
4930 "sys_getgroups16", /* 80 */
4931 "sys_setgroups16",
4932 "old_select",
4933 "sys_symlink",
4934 "sys_lstat",
4935 "sys_readlink", /* 85 */
4936 "sys_uselib",
4937 "sys_swapon",
4938 "sys_reboot",
4939 "old_readdir",
4940 "old_mmap", /* 90 */
4941 "sys_munmap",
4942 "sys_truncate",
4943 "sys_ftruncate",
4944 "sys_fchmod",
4945 "sys_fchown16", /* 95 */
4946 "sys_getpriority",
4947 "sys_setpriority",
4948 "sys_ni_syscall", /* old profil syscall holder */
4949 "sys_statfs",
4950 "sys_fstatfs", /* 100 */
4951 "sys_ioperm",
4952 "sys_socketcall",
4953 "sys_syslog",
4954 "sys_setitimer",
4955 "sys_getitimer", /* 105 */
4956 "sys_newstat",
4957 "sys_newlstat",
4958 "sys_newfstat",
4959 "sys_uname",
4960 "sys_iopl", /* 110 */
4961 "sys_vhangup",
4962 "sys_ni_syscall", /* old "idle" system call */
4963 "sys_vm86old",
4964 "sys_wait4",
4965 "sys_swapoff", /* 115 */
4966 "sys_sysinfo",
4967 "sys_ipc",
4968 "sys_fsync",
4969 "sys_sigreturn",
4970 "sys_clone", /* 120 */
4971 "sys_setdomainname",
4972 "sys_newuname",
4973 "sys_modify_ldt",
4974 "sys_adjtimex",
4975 "sys_mprotect", /* 125 */
4976 "sys_sigprocmask",
4977 "sys_ni_syscall", /* old "create_module" */
4978 "sys_init_module",
4979 "sys_delete_module",
4980 "sys_ni_syscall", /* 130: old "get_kernel_syms" */
4981 "sys_quotactl",
4982 "sys_getpgid",
4983 "sys_fchdir",
4984 "sys_bdflush",
4985 "sys_sysfs", /* 135 */
4986 "sys_personality",
4987 "sys_ni_syscall", /* reserved for afs_syscall */
4988 "sys_setfsuid16",
4989 "sys_setfsgid16",
4990 "sys_llseek", /* 140 */
4991 "sys_getdents",
4992 "sys_select",
4993 "sys_flock",
4994 "sys_msync",
4995 "sys_readv", /* 145 */
4996 "sys_writev",
4997 "sys_getsid",
4998 "sys_fdatasync",
4999 "sys_sysctl",
5000 "sys_mlock", /* 150 */
5001 "sys_munlock",
5002 "sys_mlockall",
5003 "sys_munlockall",
5004 "sys_sched_setparam",
5005 "sys_sched_getparam", /* 155 */
5006 "sys_sched_setscheduler",
5007 "sys_sched_getscheduler",
5008 "sys_sched_yield",
5009 "sys_sched_get_priority_max",
5010 "sys_sched_get_priority_min", /* 160 */
5011 "sys_sched_rr_get_interval",
5012 "sys_nanosleep",
5013 "sys_mremap",
5014 "sys_setresuid16",
5015 "sys_getresuid16", /* 165 */
5016 "sys_vm86",
5017 "sys_ni_syscall", /* Old sys_query_module */
5018 "sys_poll",
5019 "sys_nfsservctl",
5020 "sys_setresgid16", /* 170 */
5021 "sys_getresgid16",
5022 "sys_prctl",
5023 "sys_rt_sigreturn",
5024 "sys_rt_sigaction",
5025 "sys_rt_sigprocmask", /* 175 */
5026 "sys_rt_sigpending",
5027 "sys_rt_sigtimedwait",
5028 "sys_rt_sigqueueinfo",
5029 "sys_rt_sigsuspend",
5030 "sys_pread64", /* 180 */
5031 "sys_pwrite64",
5032 "sys_chown16",
5033 "sys_getcwd",
5034 "sys_capget",
5035 "sys_capset", /* 185 */
5036 "sys_sigaltstack",
5037 "sys_sendfile",
5038 "sys_ni_syscall", /* reserved for streams1 */
5039 "sys_ni_syscall", /* reserved for streams2 */
5040 "sys_vfork", /* 190 */
5041 "sys_getrlimit",
5042 "sys_mmap2",
5043 "sys_truncate64",
5044 "sys_ftruncate64",
5045 "sys_stat64", /* 195 */
5046 "sys_lstat64",
5047 "sys_fstat64",
5048 "sys_lchown",
5049 "sys_getuid",
5050 "sys_getgid", /* 200 */
5051 "sys_geteuid",
5052 "sys_getegid",
5053 "sys_setreuid",
5054 "sys_setregid",
5055 "sys_getgroups", /* 205 */
5056 "sys_setgroups",
5057 "sys_fchown",
5058 "sys_setresuid",
5059 "sys_getresuid",
5060 "sys_setresgid", /* 210 */
5061 "sys_getresgid",
5062 "sys_chown",
5063 "sys_setuid",
5064 "sys_setgid",
5065 "sys_setfsuid", /* 215 */
5066 "sys_setfsgid",
5067 "sys_pivot_root",
5068 "sys_mincore",
5069 "sys_madvise",
5070 "sys_getdents64", /* 220 */
5071 "sys_fcntl64",
5072 "sys_ni_syscall", /* reserved for TUX */
5073 "sys_ni_syscall",
5074 "sys_gettid",
5075 "sys_readahead", /* 225 */
5076 "sys_setxattr",
5077 "sys_lsetxattr",
5078 "sys_fsetxattr",
5079 "sys_getxattr",
5080 "sys_lgetxattr", /* 230 */
5081 "sys_fgetxattr",
5082 "sys_listxattr",
5083 "sys_llistxattr",
5084 "sys_flistxattr",
5085 "sys_removexattr", /* 235 */
5086 "sys_lremovexattr",
5087 "sys_fremovexattr",
5088 "sys_tkill",
5089 "sys_sendfile64",
5090 "sys_futex", /* 240 */
5091 "sys_sched_setaffinity",
5092 "sys_sched_getaffinity",
5093 "sys_set_thread_area",
5094 "sys_get_thread_area",
5095 "sys_io_setup", /* 245 */
5096 "sys_io_destroy",
5097 "sys_io_getevents",
5098 "sys_io_submit",
5099 "sys_io_cancel",
5100 "sys_fadvise64", /* 250 */
5101 "sys_ni_syscall",
5102 "sys_exit_group",
5103 "sys_lookup_dcookie",
5104 "sys_epoll_create",
5105 "sys_epoll_ctl", /* 255 */
5106 "sys_epoll_wait",
5107 "sys_remap_file_pages",
5108 "sys_set_tid_address",
5109 "sys_timer_create",
5110 "sys_timer_settime", /* 260 */
5111 "sys_timer_gettime",
5112 "sys_timer_getoverrun",
5113 "sys_timer_delete",
5114 "sys_clock_settime",
5115 "sys_clock_gettime", /* 265 */
5116 "sys_clock_getres",
5117 "sys_clock_nanosleep",
5118 "sys_statfs64",
5119 "sys_fstatfs64",
5120 "sys_tgkill", /* 270 */
5121 "sys_utimes",
5122 "sys_fadvise64_64",
5123 "sys_ni_syscall" /* sys_vserver */
5124 };
5125
5126 uint32_t uEAX = CPUMGetGuestEAX(pVCpu);
5127 switch (uEAX)
5128 {
5129 default:
5130 if (uEAX < RT_ELEMENTS(apsz))
5131 Log(("REM: linux syscall %3d: %s (eip=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
5132 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), CPUMGetGuestEBX(pVCpu), CPUMGetGuestECX(pVCpu),
5133 CPUMGetGuestEDX(pVCpu), CPUMGetGuestESI(pVCpu), CPUMGetGuestEDI(pVCpu), CPUMGetGuestEBP(pVCpu)));
5134 else
5135 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX));
5136 break;
5137
5138 }
5139}
5140
5141
5142/**
5143 * Dumps an OpenBSD system call.
5144 * @param pVCpu VMCPU handle.
5145 */
5146void remR3DumpOBsdSyscall(PVMCPU pVCpu)
5147{
5148 static const char *apsz[] =
5149 {
5150 "SYS_syscall", //0
5151 "SYS_exit", //1
5152 "SYS_fork", //2
5153 "SYS_read", //3
5154 "SYS_write", //4
5155 "SYS_open", //5
5156 "SYS_close", //6
5157 "SYS_wait4", //7
5158 "SYS_8",
5159 "SYS_link", //9
5160 "SYS_unlink", //10
5161 "SYS_11",
5162 "SYS_chdir", //12
5163 "SYS_fchdir", //13
5164 "SYS_mknod", //14
5165 "SYS_chmod", //15
5166 "SYS_chown", //16
5167 "SYS_break", //17
5168 "SYS_18",
5169 "SYS_19",
5170 "SYS_getpid", //20
5171 "SYS_mount", //21
5172 "SYS_unmount", //22
5173 "SYS_setuid", //23
5174 "SYS_getuid", //24
5175 "SYS_geteuid", //25
5176 "SYS_ptrace", //26
5177 "SYS_recvmsg", //27
5178 "SYS_sendmsg", //28
5179 "SYS_recvfrom", //29
5180 "SYS_accept", //30
5181 "SYS_getpeername", //31
5182 "SYS_getsockname", //32
5183 "SYS_access", //33
5184 "SYS_chflags", //34
5185 "SYS_fchflags", //35
5186 "SYS_sync", //36
5187 "SYS_kill", //37
5188 "SYS_38",
5189 "SYS_getppid", //39
5190 "SYS_40",
5191 "SYS_dup", //41
5192 "SYS_opipe", //42
5193 "SYS_getegid", //43
5194 "SYS_profil", //44
5195 "SYS_ktrace", //45
5196 "SYS_sigaction", //46
5197 "SYS_getgid", //47
5198 "SYS_sigprocmask", //48
5199 "SYS_getlogin", //49
5200 "SYS_setlogin", //50
5201 "SYS_acct", //51
5202 "SYS_sigpending", //52
5203 "SYS_osigaltstack", //53
5204 "SYS_ioctl", //54
5205 "SYS_reboot", //55
5206 "SYS_revoke", //56
5207 "SYS_symlink", //57
5208 "SYS_readlink", //58
5209 "SYS_execve", //59
5210 "SYS_umask", //60
5211 "SYS_chroot", //61
5212 "SYS_62",
5213 "SYS_63",
5214 "SYS_64",
5215 "SYS_65",
5216 "SYS_vfork", //66
5217 "SYS_67",
5218 "SYS_68",
5219 "SYS_sbrk", //69
5220 "SYS_sstk", //70
5221 "SYS_61",
5222 "SYS_vadvise", //72
5223 "SYS_munmap", //73
5224 "SYS_mprotect", //74
5225 "SYS_madvise", //75
5226 "SYS_76",
5227 "SYS_77",
5228 "SYS_mincore", //78
5229 "SYS_getgroups", //79
5230 "SYS_setgroups", //80
5231 "SYS_getpgrp", //81
5232 "SYS_setpgid", //82
5233 "SYS_setitimer", //83
5234 "SYS_84",
5235 "SYS_85",
5236 "SYS_getitimer", //86
5237 "SYS_87",
5238 "SYS_88",
5239 "SYS_89",
5240 "SYS_dup2", //90
5241 "SYS_91",
5242 "SYS_fcntl", //92
5243 "SYS_select", //93
5244 "SYS_94",
5245 "SYS_fsync", //95
5246 "SYS_setpriority", //96
5247 "SYS_socket", //97
5248 "SYS_connect", //98
5249 "SYS_99",
5250 "SYS_getpriority", //100
5251 "SYS_101",
5252 "SYS_102",
5253 "SYS_sigreturn", //103
5254 "SYS_bind", //104
5255 "SYS_setsockopt", //105
5256 "SYS_listen", //106
5257 "SYS_107",
5258 "SYS_108",
5259 "SYS_109",
5260 "SYS_110",
5261 "SYS_sigsuspend", //111
5262 "SYS_112",
5263 "SYS_113",
5264 "SYS_114",
5265 "SYS_115",
5266 "SYS_gettimeofday", //116
5267 "SYS_getrusage", //117
5268 "SYS_getsockopt", //118
5269 "SYS_119",
5270 "SYS_readv", //120
5271 "SYS_writev", //121
5272 "SYS_settimeofday", //122
5273 "SYS_fchown", //123
5274 "SYS_fchmod", //124
5275 "SYS_125",
5276 "SYS_setreuid", //126
5277 "SYS_setregid", //127
5278 "SYS_rename", //128
5279 "SYS_129",
5280 "SYS_130",
5281 "SYS_flock", //131
5282 "SYS_mkfifo", //132
5283 "SYS_sendto", //133
5284 "SYS_shutdown", //134
5285 "SYS_socketpair", //135
5286 "SYS_mkdir", //136
5287 "SYS_rmdir", //137
5288 "SYS_utimes", //138
5289 "SYS_139",
5290 "SYS_adjtime", //140
5291 "SYS_141",
5292 "SYS_142",
5293 "SYS_143",
5294 "SYS_144",
5295 "SYS_145",
5296 "SYS_146",
5297 "SYS_setsid", //147
5298 "SYS_quotactl", //148
5299 "SYS_149",
5300 "SYS_150",
5301 "SYS_151",
5302 "SYS_152",
5303 "SYS_153",
5304 "SYS_154",
5305 "SYS_nfssvc", //155
5306 "SYS_156",
5307 "SYS_157",
5308 "SYS_158",
5309 "SYS_159",
5310 "SYS_160",
5311 "SYS_getfh", //161
5312 "SYS_162",
5313 "SYS_163",
5314 "SYS_164",
5315 "SYS_sysarch", //165
5316 "SYS_166",
5317 "SYS_167",
5318 "SYS_168",
5319 "SYS_169",
5320 "SYS_170",
5321 "SYS_171",
5322 "SYS_172",
5323 "SYS_pread", //173
5324 "SYS_pwrite", //174
5325 "SYS_175",
5326 "SYS_176",
5327 "SYS_177",
5328 "SYS_178",
5329 "SYS_179",
5330 "SYS_180",
5331 "SYS_setgid", //181
5332 "SYS_setegid", //182
5333 "SYS_seteuid", //183
5334 "SYS_lfs_bmapv", //184
5335 "SYS_lfs_markv", //185
5336 "SYS_lfs_segclean", //186
5337 "SYS_lfs_segwait", //187
5338 "SYS_188",
5339 "SYS_189",
5340 "SYS_190",
5341 "SYS_pathconf", //191
5342 "SYS_fpathconf", //192
5343 "SYS_swapctl", //193
5344 "SYS_getrlimit", //194
5345 "SYS_setrlimit", //195
5346 "SYS_getdirentries", //196
5347 "SYS_mmap", //197
5348 "SYS___syscall", //198
5349 "SYS_lseek", //199
5350 "SYS_truncate", //200
5351 "SYS_ftruncate", //201
5352 "SYS___sysctl", //202
5353 "SYS_mlock", //203
5354 "SYS_munlock", //204
5355 "SYS_205",
5356 "SYS_futimes", //206
5357 "SYS_getpgid", //207
5358 "SYS_xfspioctl", //208
5359 "SYS_209",
5360 "SYS_210",
5361 "SYS_211",
5362 "SYS_212",
5363 "SYS_213",
5364 "SYS_214",
5365 "SYS_215",
5366 "SYS_216",
5367 "SYS_217",
5368 "SYS_218",
5369 "SYS_219",
5370 "SYS_220",
5371 "SYS_semget", //221
5372 "SYS_222",
5373 "SYS_223",
5374 "SYS_224",
5375 "SYS_msgget", //225
5376 "SYS_msgsnd", //226
5377 "SYS_msgrcv", //227
5378 "SYS_shmat", //228
5379 "SYS_229",
5380 "SYS_shmdt", //230
5381 "SYS_231",
5382 "SYS_clock_gettime", //232
5383 "SYS_clock_settime", //233
5384 "SYS_clock_getres", //234
5385 "SYS_235",
5386 "SYS_236",
5387 "SYS_237",
5388 "SYS_238",
5389 "SYS_239",
5390 "SYS_nanosleep", //240
5391 "SYS_241",
5392 "SYS_242",
5393 "SYS_243",
5394 "SYS_244",
5395 "SYS_245",
5396 "SYS_246",
5397 "SYS_247",
5398 "SYS_248",
5399 "SYS_249",
5400 "SYS_minherit", //250
5401 "SYS_rfork", //251
5402 "SYS_poll", //252
5403 "SYS_issetugid", //253
5404 "SYS_lchown", //254
5405 "SYS_getsid", //255
5406 "SYS_msync", //256
5407 "SYS_257",
5408 "SYS_258",
5409 "SYS_259",
5410 "SYS_getfsstat", //260
5411 "SYS_statfs", //261
5412 "SYS_fstatfs", //262
5413 "SYS_pipe", //263
5414 "SYS_fhopen", //264
5415 "SYS_265",
5416 "SYS_fhstatfs", //266
5417 "SYS_preadv", //267
5418 "SYS_pwritev", //268
5419 "SYS_kqueue", //269
5420 "SYS_kevent", //270
5421 "SYS_mlockall", //271
5422 "SYS_munlockall", //272
5423 "SYS_getpeereid", //273
5424 "SYS_274",
5425 "SYS_275",
5426 "SYS_276",
5427 "SYS_277",
5428 "SYS_278",
5429 "SYS_279",
5430 "SYS_280",
5431 "SYS_getresuid", //281
5432 "SYS_setresuid", //282
5433 "SYS_getresgid", //283
5434 "SYS_setresgid", //284
5435 "SYS_285",
5436 "SYS_mquery", //286
5437 "SYS_closefrom", //287
5438 "SYS_sigaltstack", //288
5439 "SYS_shmget", //289
5440 "SYS_semop", //290
5441 "SYS_stat", //291
5442 "SYS_fstat", //292
5443 "SYS_lstat", //293
5444 "SYS_fhstat", //294
5445 "SYS___semctl", //295
5446 "SYS_shmctl", //296
5447 "SYS_msgctl", //297
5448 "SYS_MAXSYSCALL", //298
5449 //299
5450 //300
5451 };
5452 uint32_t uEAX;
5453 if (!LogIsEnabled())
5454 return;
5455 uEAX = CPUMGetGuestEAX(pVCpu);
5456 switch (uEAX)
5457 {
5458 default:
5459 if (uEAX < RT_ELEMENTS(apsz))
5460 {
5461 uint32_t au32Args[8] = {0};
5462 PGMPhysSimpleReadGCPtr(pVCpu, au32Args, CPUMGetGuestESP(pVCpu), sizeof(au32Args));
5463 RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
5464 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
5465 au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
5466 }
5467 else
5468 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX);
5469 break;
5470 }
5471}
5472
5473
5474#if defined(IPRT_NO_CRT) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
5475/**
5476 * The Dll main entry point (stub).
5477 */
5478bool __stdcall _DllMainCRTStartup(void *hModule, uint32_t dwReason, void *pvReserved)
5479{
5480 return true;
5481}
5482
5483void *memcpy(void *dst, const void *src, size_t size)
5484{
5485 uint8_t*pbDst = dst, *pbSrc = src;
5486 while (size-- > 0)
5487 *pbDst++ = *pbSrc++;
5488 return dst;
5489}
5490
5491#endif
5492
5493void cpu_smm_update(CPUX86State *env)
5494{
5495}
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