VBoxRecompiler.c@ 993

Last change on this file since 993 was 858, checked in by vboxsync, 18 years ago
Compile fix
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File size: 155.5 KB

Line
1	/** @file
2	*
3	* VBox Recompiler - QEMU.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include "vl.h"
27	#include "exec-all.h"
28
29	#include <VBox/rem.h>
30	#include <VBox/vmapi.h>
31	#include <VBox/tm.h>
32	#include <VBox/ssm.h>
33	#include <VBox/em.h>
34	#include <VBox/trpm.h>
35	#include <VBox/iom.h>
36	#include <VBox/mm.h>
37	#include <VBox/pgm.h>
38	#include <VBox/pdm.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/dbg.h>
41	#include <VBox/hwaccm.h>
42	#include <VBox/patm.h>
43	#include <VBox/csam.h>
44	#include "REMInternal.h"
45	#include <VBox/vm.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49	#define LOG_GROUP LOG_GROUP_REM
50	#include <VBox/log.h>
51	#include <iprt/semaphore.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/thread.h>
55	#include <iprt/string.h>
56
57	////#define VBOX_RAW_V86
58
59	/* Don't wanna include everything. */
60	extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
61	extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
62	extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
63	extern void tlb_flush_page(CPUX86State *env, uint32_t addr);
64	extern void tlb_flush(CPUState *env, int flush_global);
65	extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
66	extern void sync_ldtr(CPUX86State *env1, int selector);
67	extern int sync_tr(CPUX86State *env1, int selector);
68
69	#ifdef VBOX_STRICT
70	unsigned long get_phys_page_offset(target_ulong addr);
71	#endif
72
73
74	/*******************************************************************************
75	* Defined Constants And Macros *
76	*******************************************************************************/
77
78	/** Copy 80-bit fpu register at pSrc to pDst.
79	* This is probably faster than calling memcpy.
80	*/
81	#define REM_COPY_FPU_REG(pDst, pSrc) \
82	do { (PX86FPUMMX)(pDst) = (const X86FPUMMX *)(pSrc); } while (0)
83
84
85	/*******************************************************************************
86	* Internal Functions *
87	*******************************************************************************/
88	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
89	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
90	static void remR3StateUpdate(PVM pVM);
91	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
92	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
93	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
94	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
97
98	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
99	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
100	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
101	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
104
105
106	/*******************************************************************************
107	* Global Variables *
108	*******************************************************************************/
109
110	/** The log level of the recompiler. */
111	#if 1
112	extern int loglevel;
113	#else
114	int loglevel = ~0;
115	FILE *logfile = NULL;
116	#endif
117
118
119	/** @todo Move stats to REM::s some rainy day we have nothing do to. */
120	#ifdef VBOX_WITH_STATISTICS
121	static STAMPROFILEADV gStatExecuteSingleInstr;
122	static STAMPROFILEADV gStatCompilationQEmu;
123	static STAMPROFILEADV gStatRunCodeQEmu;
124	static STAMPROFILEADV gStatTotalTimeQEmu;
125	static STAMPROFILEADV gStatTimers;
126	static STAMPROFILEADV gStatTBLookup;
127	static STAMPROFILEADV gStatIRQ;
128	static STAMPROFILEADV gStatRawCheck;
129	static STAMPROFILEADV gStatMemRead;
130	static STAMPROFILEADV gStatMemWrite;
131	static STAMCOUNTER gStatRefuseTFInhibit;
132	static STAMCOUNTER gStatRefuseVM86;
133	static STAMCOUNTER gStatRefusePaging;
134	static STAMCOUNTER gStatRefusePAE;
135	static STAMCOUNTER gStatRefuseIOPLNot0;
136	static STAMCOUNTER gStatRefuseIF0;
137	static STAMCOUNTER gStatRefuseCode16;
138	static STAMCOUNTER gStatRefuseWP0;
139	static STAMCOUNTER gStatRefuseRing1or2;
140	static STAMCOUNTER gStatRefuseCanExecute;
141	static STAMCOUNTER gStatREMGDTChange;
142	static STAMCOUNTER gStatREMIDTChange;
143	static STAMCOUNTER gStatREMLDTRChange;
144	static STAMCOUNTER gStatREMTRChange;
145	static STAMCOUNTER gStatSelOutOfSync[6];
146	static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
147	#endif
148
149	/*
150	* Global stuff.
151	*/
152
153	/** MMIO read callbacks. */
154	CPUReadMemoryFunc *g_apfnMMIORead[3] =
155	{
156	remR3MMIOReadU8,
157	remR3MMIOReadU16,
158	remR3MMIOReadU32
159	};
160
161	/** MMIO write callbacks. */
162	CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
163	{
164	remR3MMIOWriteU8,
165	remR3MMIOWriteU16,
166	remR3MMIOWriteU32
167	};
168
169	/** Handler read callbacks. */
170	CPUReadMemoryFunc *g_apfnHandlerRead[3] =
171	{
172	remR3HandlerReadU8,
173	remR3HandlerReadU16,
174	remR3HandlerReadU32
175	};
176
177	/** Handler write callbacks. */
178	CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
179	{
180	remR3HandlerWriteU8,
181	remR3HandlerWriteU16,
182	remR3HandlerWriteU32
183	};
184
185	#ifndef PGM_DYNAMIC_RAM_ALLOC
186	/* Guest physical RAM base. Not to be used in external code. */
187	static uint8_t *phys_ram_base;
188	#endif
189
190	/*
191	* Instance stuff.
192	*/
193	/** Pointer to the cpu state. */
194	CPUState *cpu_single_env;
195
196
197	#ifdef VBOX_WITH_DEBUGGER
198	/*
199	* Debugger commands.
200	*/
201	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
202
203	/** '.remstep' arguments. */
204	static const DBGCVARDESC g_aArgRemStep[] =
205	{
206	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
207	{ 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
208	};
209
210	/** Command descriptors. */
211	static const DBGCCMD g_aCmds[] =
212	{
213	{
214	.pszCmd ="remstep",
215	.cArgsMin = 0,
216	.cArgsMax = 1,
217	.paArgDescs = &g_aArgRemStep[0],
218	.cArgDescs = ELEMENTS(g_aArgRemStep),
219	.pResultDesc = NULL,
220	.fFlags = 0,
221	.pfnHandler = remR3CmdDisasEnableStepping,
222	.pszSyntax = "[on/off]",
223	.pszDescription = "Enable or disable the single stepping with logged disassembly. "
224	"If no arguments show the current state."
225	}
226	};
227	#endif
228
229
230	/*******************************************************************************
231	* Internal Functions *
232	*******************************************************************************/
233	static void remAbort(int rc, const char *pszTip);
234
235
236	/* Put them here to avoid unused variable warning. */
237	AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
238	//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
239	//AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
240
241	/**
242	* Initializes the REM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	REMR3DECL(int) REMR3Init(PVM pVM)
248	{
249	uint32_t u32Dummy;
250	AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
251	//AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
252	AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
253	#if 0 /* not merged yet */
254	Assert(!testmath());
255	#endif
256
257	/*
258	* Init some internal data members.
259	*/
260	pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
261	pVM->rem.s.Env.pVM = pVM;
262	#ifdef CPU_RAW_MODE_INIT
263	pVM->rem.s.state \|= CPU_RAW_MODE_INIT;
264	#endif
265
266	/* ctx. */
267	int rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);
268	if (VBOX_FAILURE(rc))
269	{
270	AssertMsgFailed(("Failed to obtain guest ctx pointer. rc=%Vrc\n", rc));
271	return rc;
272	}
273	AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
274
275	/*
276	* Init the recompiler.
277	*/
278	if (!cpu_x86_init(&pVM->rem.s.Env))
279	{
280	AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
281	return VERR_GENERAL_FAILURE;
282	}
283	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
284
285	/* allocate code buffer for single instruction emulation. */
286	pVM->rem.s.Env.cbCodeBuffer = 4096;
287	pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
288	AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
289
290	/* finally, set the cpu_single_env global. */
291	cpu_single_env = &pVM->rem.s.Env;
292
293	/* Nothing is pending by default */
294	pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
295
296	#ifdef DEBUG_bird
297	//cpu_breakpoint_insert(&pVM->rem.s.Env, some-address);
298	#endif
299
300	/*
301	* Register ram types.
302	*/
303	pVM->rem.s.iMMIOMemType = cpu_register_io_memory(0, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
304	AssertReleaseMsg(pVM->rem.s.iMMIOMemType > 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
305	pVM->rem.s.iHandlerMemType = cpu_register_io_memory(0, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
306	AssertReleaseMsg(pVM->rem.s.iHandlerMemType > 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
307	Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
308
309	/*
310	* Register the saved state data unit.
311	*/
312	rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
313	NULL, remR3Save, NULL,
314	NULL, remR3Load, NULL);
315	if (VBOX_FAILURE(rc))
316	return rc;
317
318	#ifdef VBOX_WITH_DEBUGGER
319	/*
320	* Debugger commands.
321	*/
322	static bool fRegisteredCmds = false;
323	if (!fRegisteredCmds)
324	{
325	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
326	if (VBOX_SUCCESS(rc))
327	fRegisteredCmds = true;
328	}
329	#endif
330
331	#ifdef VBOX_WITH_STATISTICS
332	/*
333	* Statistics.
334	*/
335	STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
336	STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
337	STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
338	STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
339	STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
340	STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
341	STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
342	STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
343	STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
344	STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
345
346	STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
347	STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
348	STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
349	STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
350	STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
351	STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
352	STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
353	STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
354	STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
355	STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
356
357	STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
358	STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
359	STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
360	STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
361
362	STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
363	STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
364	STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
365	STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
366	STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
367	STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
368
369	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
370	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
371	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
372	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
373	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
374	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
375
376	#endif
377	return rc;
378	}
379
380
381	/**
382	* Terminates the REM.
383	*
384	* Termination means cleaning up and freeing all resources,
385	* the VM it self is at this point powered off or suspended.
386	*
387	* @returns VBox status code.
388	* @param pVM The VM to operate on.
389	*/
390	REMR3DECL(int) REMR3Term(PVM pVM)
391	{
392	return VINF_SUCCESS;
393	}
394
395
396	/**
397	* The VM is being reset.
398	*
399	* For the REM component this means to call the cpu_reset() and
400	* reinitialize some state variables.
401	*
402	* @param pVM VM handle.
403	*/
404	REMR3DECL(void) REMR3Reset(PVM pVM)
405	{
406	pVM->rem.s.fIgnoreCR3Load = true;
407	pVM->rem.s.fIgnoreInvlPg = true;
408	pVM->rem.s.fIgnoreCpuMode = true;
409
410	/*
411	* Reset the REM cpu.
412	*/
413	cpu_reset(&pVM->rem.s.Env);
414	pVM->rem.s.cInvalidatedPages = 0;
415
416	pVM->rem.s.fIgnoreCR3Load = false;
417	pVM->rem.s.fIgnoreInvlPg = false;
418	pVM->rem.s.fIgnoreCpuMode = false;
419	}
420
421
422	/**
423	* Execute state save operation.
424	*
425	* @returns VBox status code.
426	* @param pVM VM Handle.
427	* @param pSSM SSM operation handle.
428	*/
429	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
430	{
431	LogFlow(("remR3Save:\n"));
432
433	/*
434	* Save the required CPU Env bits.
435	* (Not much because we're never in REM when doing the save.)
436	*/
437	PREM pRem = &pVM->rem.s;
438	Assert(!pRem->fInREM);
439	SSMR3PutU32(pSSM, pRem->Env.hflags);
440	SSMR3PutMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
441	SSMR3PutU32(pSSM, ~0); /* separator */
442
443	/*
444	* Save the REM stuff.
445	*/
446	SSMR3PutUInt(pSSM, pRem->cInvalidatedPages);
447	unsigned i;
448	for (i = 0; i < pRem->cInvalidatedPages; i++)
449	SSMR3PutGCPtr(pSSM, pRem->aGCPtrInvalidatedPages[i]);
450
451	SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
452
453	return SSMR3PutU32(pSSM, ~0); /* terminator */
454	}
455
456
457	/**
458	* Execute state load operation.
459	*
460	* @returns VBox status code.
461	* @param pVM VM Handle.
462	* @param pSSM SSM operation handle.
463	* @param u32Version Data layout version.
464	*/
465	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
466	{
467	uint32_t u32Dummy;
468	LogFlow(("remR3Load:\n"));
469
470	/*
471	* Validate version.
472	*/
473	if (u32Version != REM_SAVED_STATE_VERSION)
474	{
475	Log(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
476	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
477	}
478
479	/*
480	* Do a reset to be on the safe side...
481	*/
482	REMR3Reset(pVM);
483
484	/*
485	* Ignore all ignorable notifications.
486	* Not doing this will cause big trouble.
487	*/
488	pVM->rem.s.fIgnoreCR3Load = true;
489	pVM->rem.s.fIgnoreInvlPg = true;
490	pVM->rem.s.fIgnoreCpuMode = true;
491
492	/*
493	* Load the required CPU Env bits.
494	* (Not much because we're never in REM when doing the save.)
495	*/
496	PREM pRem = &pVM->rem.s;
497	Assert(!pRem->fInREM);
498	SSMR3GetU32(pSSM, &pRem->Env.hflags);
499	SSMR3GetMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
500	uint32_t u32Sep;
501	int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
502	if (VBOX_FAILURE(rc))
503	return rc;
504	if (u32Sep != ~0)
505	{
506	AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
507	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
508	}
509
510	/*
511	* Load the REM stuff.
512	*/
513	rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
514	if (VBOX_FAILURE(rc))
515	return rc;
516	if (pRem->cInvalidatedPages > ELEMENTS(pRem->aGCPtrInvalidatedPages))
517	{
518	AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
519	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
520	}
521	unsigned i;
522	for (i = 0; i < pRem->cInvalidatedPages; i++)
523	SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
524
525	rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
526	if (VBOX_FAILURE(rc))
527	return rc;
528
529	/* check the terminator. */
530	rc = SSMR3GetU32(pSSM, &u32Sep);
531	if (VBOX_FAILURE(rc))
532	return rc;
533	if (u32Sep != ~0)
534	{
535	AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
536	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
537	}
538
539	/*
540	* Get the CPUID features.
541	*/
542	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
543
544	/*
545	* Sync the Load Flush the TLB
546	*/
547	tlb_flush(&pRem->Env, 1);
548
549	#if 0 /** @todo r=bird: this doesn't make sense. WHY? */
550	/*
551	* Clear all lazy flags (only FPU sync for now).
552	*/
553	CPUMGetAndClearFPUUsedREM(pVM);
554	#endif
555
556	/*
557	* Stop ignoring ignornable notifications.
558	*/
559	pVM->rem.s.fIgnoreCpuMode = false;
560	pVM->rem.s.fIgnoreInvlPg = false;
561	pVM->rem.s.fIgnoreCR3Load = false;
562
563	return VINF_SUCCESS;
564	}
565
566
567
568	#undef LOG_GROUP
569	#define LOG_GROUP LOG_GROUP_REM_RUN
570
571	/**
572	* Single steps an instruction in recompiled mode.
573	*
574	* Before calling this function the REM state needs to be in sync with
575	* the VM. Call REMR3State() to perform the sync. It's only necessary
576	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
577	* and after calling REMR3StateBack().
578	*
579	* @returns VBox status code.
580	*
581	* @param pVM VM Handle.
582	*/
583	REMR3DECL(int) REMR3Step(PVM pVM)
584	{
585	/*
586	* Lock the REM - we don't wanna have anyone interrupting us
587	* while stepping - and enabled single stepping. We also ignore
588	* pending interrupts and suchlike.
589	*/
590	int interrupt_request = pVM->rem.s.Env.interrupt_request;
591	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
592	pVM->rem.s.Env.interrupt_request = 0;
593	cpu_single_step(&pVM->rem.s.Env, 1);
594
595	/*
596	* If we're standing at a breakpoint, that have to be disabled before we start stepping.
597	*/
598	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
599	bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
600
601	/*
602	* Execute and handle the return code.
603	* We execute without enabling the cpu tick, so on success we'll
604	* just flip it on and off to make sure it moves
605	*/
606	int rc = cpu_exec(&pVM->rem.s.Env);
607	if (rc == EXCP_DEBUG)
608	{
609	TMCpuTickResume(pVM);
610	TMCpuTickPause(pVM);
611	TMVirtualResume(pVM);
612	TMVirtualPause(pVM);
613	rc = VINF_EM_DBG_STEPPED;
614	}
615	else
616	{
617	AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
618	switch (rc)
619	{
620	case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
621	case EXCP_HLT: rc = VINF_EM_HALT; break;
622	case EXCP_RC:
623	rc = pVM->rem.s.rc;
624	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
625	break;
626	default:
627	AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
628	rc = VERR_INTERNAL_ERROR;
629	break;
630	}
631	}
632
633	/*
634	* Restore the stuff we changed to prevent interruption.
635	* Unlock the REM.
636	*/
637	if (fBp)
638	{
639	int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
640	Assert(rc2 == 0); NOREF(rc2);
641	}
642	cpu_single_step(&pVM->rem.s.Env, 0);
643	pVM->rem.s.Env.interrupt_request = interrupt_request;
644
645	return rc;
646	}
647
648
649	/**
650	* Set a breakpoint using the REM facilities.
651	*
652	* @returns VBox status code.
653	* @param pVM The VM handle.
654	* @param Address The breakpoint address.
655	* @thread The emulation thread.
656	*/
657	REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
658	{
659	VM_ASSERT_EMT(pVM);
660	if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
661	{
662	LogFlow(("REMR3BreakpointSet: Address=%VGv\n", Address));
663	return VINF_SUCCESS;
664	}
665	LogFlow(("REMR3BreakpointSet: Address=%VGv - failed!\n", Address));
666	return VERR_REM_NO_MORE_BP_SLOTS;
667	}
668
669
670	/**
671	* Clears a breakpoint set by REMR3BreakpointSet().
672	*
673	* @returns VBox status code.
674	* @param pVM The VM handle.
675	* @param Address The breakpoint address.
676	* @thread The emulation thread.
677	*/
678	REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
679	{
680	VM_ASSERT_EMT(pVM);
681	if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
682	{
683	LogFlow(("REMR3BreakpointClear: Address=%VGv\n", Address));
684	return VINF_SUCCESS;
685	}
686	LogFlow(("REMR3BreakpointClear: Address=%VGv - not found!\n", Address));
687	return VERR_REM_BP_NOT_FOUND;
688	}
689
690
691	/**
692	* Emulate an instruction.
693	*
694	* This function executes one instruction without letting anyone
695	* interrupt it. This is intended for being called while being in
696	* raw mode and thus will take care of all the state syncing between
697	* REM and the rest.
698	*
699	* @returns VBox status code.
700	* @param pVM VM handle.
701	*/
702	REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
703	{
704	Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
705
706	/*
707	* Sync the state and enable single instruction / single stepping.
708	*/
709	int rc = REMR3State(pVM);
710	if (VBOX_SUCCESS(rc))
711	{
712	int interrupt_request = pVM->rem.s.Env.interrupt_request;
713	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
714	Assert(!pVM->rem.s.Env.singlestep_enabled);
715	#if 1
716
717	/*
718	* Now we set the execute single instruction flag and enter the cpu_exec loop.
719	*/
720	pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
721	TMCpuTickResume(pVM);
722	rc = cpu_exec(&pVM->rem.s.Env);
723	TMCpuTickPause(pVM);
724	switch (rc)
725	{
726	/*
727	* Executed without anything out of the way happening.
728	*/
729	case EXCP_SINGLE_INSTR:
730	rc = VINF_EM_RESCHEDULE;
731	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
732	break;
733
734	/*
735	* If we take a trap or start servicing a pending interrupt, we might end up here.
736	* (Timer thread or some other thread wishing EMT's attention.)
737	*/
738	case EXCP_INTERRUPT:
739	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
740	rc = VINF_EM_RESCHEDULE;
741	break;
742
743	/*
744	* Single step, we assume!
745	* If there was a breakpoint there we're fucked now.
746	*/
747	case EXCP_DEBUG:
748	{
749	/* breakpoint or single step? */
750	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
751	int iBP;
752	rc = VINF_EM_DBG_STEPPED;
753	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
754	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
755	{
756	rc = VINF_EM_DBG_BREAKPOINT;
757	break;
758	}
759	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
760	break;
761	}
762
763	/*
764	* hlt instruction.
765	*/
766	case EXCP_HLT:
767	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
768	rc = VINF_EM_HALT;
769	break;
770
771	/*
772	* Switch to RAW-mode.
773	*/
774	case EXCP_EXECUTE_RAW:
775	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
776	rc = VINF_EM_RESCHEDULE_RAW;
777	break;
778
779	/*
780	* Switch to hardware accelerated RAW-mode.
781	*/
782	case EXCP_EXECUTE_HWACC:
783	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
784	rc = VINF_EM_RESCHEDULE_HWACC;
785	break;
786
787	/*
788	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
789	*/
790	case EXCP_RC:
791	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
792	rc = pVM->rem.s.rc;
793	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
794	break;
795
796	/*
797	* Figure out the rest when they arrive....
798	*/
799	default:
800	AssertMsgFailed(("rc=%d\n", rc));
801	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
802	rc = VINF_EM_RESCHEDULE;
803	break;
804	}
805
806	/*
807	* Switch back the state.
808	*/
809	#else
810	pVM->rem.s.Env.interrupt_request = 0;
811	cpu_single_step(&pVM->rem.s.Env, 1);
812
813	/*
814	* Execute and handle the return code.
815	* We execute without enabling the cpu tick, so on success we'll
816	* just flip it on and off to make sure it moves.
817	*
818	* (We do not use emulate_single_instr() because that doesn't enter the
819	* right way in will cause serious trouble if a longjmp was attempted.)
820	*/
821	#ifdef DEBUG_bird
822	remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
823	#endif
824	int cTimesMax = 16384;
825	uint32_t eip = pVM->rem.s.Env.eip;
826	do
827	{
828	TMCpuTickResume(pVM);
829	rc = cpu_exec(&pVM->rem.s.Env);
830	TMCpuTickPause(pVM);
831
832	} while ( eip == pVM->rem.s.Env.eip
833	&& (rc == EXCP_DEBUG \|\| rc == EXCP_EXECUTE_RAW)
834	&& --cTimesMax > 0);
835	switch (rc)
836	{
837	/*
838	* Single step, we assume!
839	* If there was a breakpoint there we're fucked now.
840	*/
841	case EXCP_DEBUG:
842	{
843	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
844	rc = VINF_EM_RESCHEDULE;
845	break;
846	}
847
848	/*
849	* We cannot be interrupted!
850	*/
851	case EXCP_INTERRUPT:
852	AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
853	rc = VERR_INTERNAL_ERROR;
854	break;
855
856	/*
857	* hlt instruction.
858	*/
859	case EXCP_HLT:
860	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
861	rc = VINF_EM_HALT;
862	break;
863
864	/*
865	* Switch to RAW-mode.
866	*/
867	case EXCP_EXECUTE_RAW:
868	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
869	rc = VINF_EM_RESCHEDULE_RAW;
870	break;
871
872	/*
873	* Switch to hardware accelerated RAW-mode.
874	*/
875	case EXCP_EXECUTE_HWACC:
876	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
877	rc = VINF_EM_RESCHEDULE_HWACC;
878	break;
879
880	/*
881	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
882	*/
883	case EXCP_RC:
884	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
885	rc = pVM->rem.s.rc;
886	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
887	break;
888
889	/*
890	* Figure out the rest when they arrive....
891	*/
892	default:
893	AssertMsgFailed(("rc=%d\n", rc));
894	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
895	rc = VINF_SUCCESS;
896	break;
897	}
898
899	/*
900	* Switch back the state.
901	*/
902	cpu_single_step(&pVM->rem.s.Env, 0);
903	#endif
904	pVM->rem.s.Env.interrupt_request = interrupt_request;
905	int rc2 = REMR3StateBack(pVM);
906	AssertRC(rc2);
907	}
908
909	Log2(("REMR3EmulateInstruction: returns %Vrc (cs:eip=%04x:%08x)\n",
910	rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
911	return rc;
912	}
913
914
915	/**
916	* Runs code in recompiled mode.
917	*
918	* Before calling this function the REM state needs to be in sync with
919	* the VM. Call REMR3State() to perform the sync. It's only necessary
920	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
921	* and after calling REMR3StateBack().
922	*
923	* @returns VBox status code.
924	*
925	* @param pVM VM Handle.
926	*/
927	REMR3DECL(int) REMR3Run(PVM pVM)
928	{
929	Log2(("REMR3Run: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
930	Assert(pVM->rem.s.fInREM);
931	////Keyboard / tb stuff:
932	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0xf000
933	// && pVM->rem.s.Env.eip >= 0xe860
934	// && pVM->rem.s.Env.eip <= 0xe880)
935	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
936	////A20:
937	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x9020
938	// && pVM->rem.s.Env.eip >= 0x970
939	// && pVM->rem.s.Env.eip <= 0x9a0)
940	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
941	////Speaker (port 61h)
942	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x0010
943	// && ( (pVM->rem.s.Env.eip >= 0x90278c10 && pVM->rem.s.Env.eip <= 0x90278c30)
944	// \|\| (pVM->rem.s.Env.eip >= 0x9010e250 && pVM->rem.s.Env.eip <= 0x9010e260)
945	// )
946	// )
947	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
948	//DBGFR3InfoLog(pVM, "timers", NULL);
949
950
951	TMCpuTickResume(pVM);
952	int rc = cpu_exec(&pVM->rem.s.Env);
953	TMCpuTickPause(pVM);
954	switch (rc)
955	{
956	/*
957	* This happens when the execution was interrupted
958	* by an external event, like pending timers.
959	*/
960	case EXCP_INTERRUPT:
961	Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
962	rc = VINF_SUCCESS;
963	break;
964
965	/*
966	* hlt instruction.
967	*/
968	case EXCP_HLT:
969	Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
970	rc = VINF_EM_HALT;
971	break;
972
973	/*
974	* Breakpoint/single step.
975	*/
976	case EXCP_DEBUG:
977	{
978	#if 0//def DEBUG_bird
979	static int iBP = 0;
980	printf("howdy, breakpoint! iBP=%d\n", iBP);
981	switch (iBP)
982	{
983	case 0:
984	cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
985	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
986	//pVM->rem.s.Env.interrupt_request = 0;
987	//pVM->rem.s.Env.exception_index = -1;
988	//g_fInterruptDisabled = 1;
989	rc = VINF_SUCCESS;
990	asm("int3");
991	break;
992	default:
993	asm("int3");
994	break;
995	}
996	iBP++;
997	#else
998	/* breakpoint or single step? */
999	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1000	int iBP;
1001	rc = VINF_EM_DBG_STEPPED;
1002	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
1003	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
1004	{
1005	rc = VINF_EM_DBG_BREAKPOINT;
1006	break;
1007	}
1008	Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
1009	#endif
1010	break;
1011	}
1012
1013	/*
1014	* Switch to RAW-mode.
1015	*/
1016	case EXCP_EXECUTE_RAW:
1017	Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1018	rc = VINF_EM_RESCHEDULE_RAW;
1019	break;
1020
1021	/*
1022	* Switch to hardware accelerated RAW-mode.
1023	*/
1024	case EXCP_EXECUTE_HWACC:
1025	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1026	rc = VINF_EM_RESCHEDULE_HWACC;
1027	break;
1028
1029	/*
1030	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
1031	*/
1032	case EXCP_RC:
1033	Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
1034	rc = pVM->rem.s.rc;
1035	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1036	break;
1037
1038	/*
1039	* Figure out the rest when they arrive....
1040	*/
1041	default:
1042	AssertMsgFailed(("rc=%d\n", rc));
1043	Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1044	rc = VINF_SUCCESS;
1045	break;
1046	}
1047
1048	Log2(("REMR3Run: returns %Vrc (cs:eip=%04x:%08x)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
1049	return rc;
1050	}
1051
1052
1053	/**
1054	* Check if the cpu state is suitable for Raw execution.
1055	*
1056	* @returns boolean
1057	* @param env The CPU env struct.
1058	* @param eip The EIP to check this for (might differ from env->eip).
1059	* @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1060	* @param pExceptionIndex Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1061	*
1062	* @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1063	*/
1064	bool remR3CanExecuteRaw(CPUState env, RTGCPTR eip, unsigned fFlags, uint32_t pExceptionIndex)
1065	{
1066	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1067	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1068	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1069
1070	/* Update counter. */
1071	env->pVM->rem.s.cCanExecuteRaw++;
1072
1073	if (HWACCMIsEnabled(env->pVM))
1074	{
1075	env->state \|= CPU_RAW_HWACC;
1076
1077	/*
1078	* Create partial context for HWACCMR3CanExecuteGuest
1079	*/
1080	CPUMCTX Ctx;
1081	Ctx.cr0 = env->cr[0];
1082	Ctx.cr3 = env->cr[3];
1083	Ctx.cr4 = env->cr[4];
1084
1085	Ctx.tr = env->tr.selector;
1086	Ctx.trHid.u32Base = (uint32_t)env->tr.base;
1087	Ctx.trHid.u32Limit = env->tr.limit;
1088	Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1089
1090	Ctx.idtr.cbIdt = env->idt.limit;
1091	Ctx.idtr.pIdt = (uint32_t)env->idt.base;
1092
1093	Ctx.eflags.u32 = env->eflags;
1094
1095	Ctx.cs = env->segs[R_CS].selector;
1096	Ctx.csHid.u32Base = (uint32_t)env->segs[R_CS].base;
1097	Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1098	Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1099
1100	Ctx.ss = env->segs[R_SS].selector;
1101	Ctx.ssHid.u32Base = (uint32_t)env->segs[R_SS].base;
1102	Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1103	Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1104
1105	/* Hardware accelerated raw-mode:
1106	*
1107	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1108	*/
1109	if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1110	{
1111	*pExceptionIndex = EXCP_EXECUTE_HWACC;
1112	return true;
1113	}
1114	return false;
1115	}
1116
1117	/*
1118	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1119	* or 32 bits protected mode ring 0 code
1120	*
1121	* The tests are ordered by the likelyhood of being true during normal execution.
1122	*/
1123	if (fFlags & (HF_TF_MASK \| HF_INHIBIT_IRQ_MASK))
1124	{
1125	STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1126	Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1127	return false;
1128	}
1129
1130	#ifndef VBOX_RAW_V86
1131	if (fFlags & VM_MASK) {
1132	STAM_COUNTER_INC(&gStatRefuseVM86);
1133	Log2(("raw mode refused: VM_MASK\n"));
1134	return false;
1135	}
1136	#endif
1137
1138	if (env->state & CPU_EMULATE_SINGLE_INSTR)
1139	{
1140	#ifndef DEBUG_bird
1141	Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1142	#endif
1143	return false;
1144	}
1145
1146	if (env->singlestep_enabled)
1147	{
1148	//Log2(("raw mode refused: Single step\n"));
1149	return false;
1150	}
1151
1152	if (env->nb_breakpoints > 0)
1153	{
1154	//Log2(("raw mode refused: Breakpoints\n"));
1155	return false;
1156	}
1157
1158	uint32_t u32CR0 = env->cr[0];
1159	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
1160	{
1161	STAM_COUNTER_INC(&gStatRefusePaging);
1162	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1163	return false;
1164	}
1165
1166	if (env->cr[4] & CR4_PAE_MASK)
1167	{
1168	STAM_COUNTER_INC(&gStatRefusePAE);
1169	//Log2(("raw mode refused: PAE\n"));
1170	return false;
1171	}
1172
1173	if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1174	{
1175	if (!EMIsRawRing3Enabled(env->pVM))
1176	return false;
1177
1178	if (!(env->eflags & IF_MASK))
1179	{
1180	#ifdef VBOX_RAW_V86
1181	if(!(fFlags & VM_MASK))
1182	return false;
1183	#else
1184	STAM_COUNTER_INC(&gStatRefuseIF0);
1185	Log2(("raw mode refused: IF (RawR3)\n"));
1186	return false;
1187	#endif
1188	}
1189
1190	if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1191	{
1192	STAM_COUNTER_INC(&gStatRefuseWP0);
1193	Log2(("raw mode refused: CR0.WP + RawR0\n"));
1194	return false;
1195	}
1196	}
1197	else
1198	{
1199	if (!EMIsRawRing0Enabled(env->pVM))
1200	return false;
1201
1202	// Let's start with pure 32 bits ring 0 code first
1203	if ((fFlags & (HF_SS32_MASK \| HF_CS32_MASK)) != (HF_SS32_MASK \| HF_CS32_MASK))
1204	{
1205	STAM_COUNTER_INC(&gStatRefuseCode16);
1206	Log2(("raw r0 mode refused: HF_[S\|C]S32_MASK fFlags=%#x\n", fFlags));
1207	return false;
1208	}
1209
1210	// Only R0
1211	if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1212	{
1213	STAM_COUNTER_INC(&gStatRefuseRing1or2);
1214	Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1215	return false;
1216	}
1217
1218	if (!(u32CR0 & CR0_WP_MASK))
1219	{
1220	STAM_COUNTER_INC(&gStatRefuseWP0);
1221	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1222	return false;
1223	}
1224
1225	if (PATMIsPatchGCAddr(env->pVM, eip))
1226	{
1227	Log2(("raw r0 mode forced: patch code\n"));
1228	*pExceptionIndex = EXCP_EXECUTE_RAW;
1229	return true;
1230	}
1231
1232	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1233	if (!(env->eflags & IF_MASK))
1234	{
1235	STAM_COUNTER_INC(&gStatRefuseIF0);
1236	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1237	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1238	return false;
1239	}
1240	#endif
1241
1242	env->state \|= CPU_RAW_RING0;
1243	}
1244
1245	/*
1246	* Don't reschedule the first time we're called, because there might be
1247	* special reasons why we're here that is not covered by the above checks.
1248	*/
1249	if (env->pVM->rem.s.cCanExecuteRaw == 1)
1250	{
1251	Log2(("raw mode refused: first scheduling\n"));
1252	STAM_COUNTER_INC(&gStatRefuseCanExecute);
1253	return false;
1254	}
1255
1256	Assert(PGMPhysIsA20Enabled(env->pVM));
1257	*pExceptionIndex = EXCP_EXECUTE_RAW;
1258	return true;
1259	}
1260
1261
1262	/**
1263	* Fetches a code byte.
1264	*
1265	* @returns Success indicator (bool) for ease of use.
1266	* @param env The CPU environment structure.
1267	* @param GCPtrInstr Where to fetch code.
1268	* @param pu8Byte Where to store the byte on success
1269	*/
1270	bool remR3GetOpcode(CPUState env, RTGCPTR GCPtrInstr, uint8_t pu8Byte)
1271	{
1272	int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1273	if (VBOX_SUCCESS(rc))
1274	return true;
1275	return false;
1276	}
1277
1278
1279	/**
1280	* Flush (or invalidate if you like) page table/dir entry.
1281	*
1282	* (invlpg instruction; tlb_flush_page)
1283	*
1284	* @param env Pointer to cpu environment.
1285	* @param GCPtr The virtual address which page table/dir entry should be invalidated.
1286	*/
1287	void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1288	{
1289	PVM pVM = env->pVM;
1290
1291	/*
1292	* When we're replaying invlpg instructions or restoring a saved
1293	* state we disable this path.
1294	*/
1295	if (pVM->rem.s.fIgnoreInvlPg)
1296	return;
1297	Log(("remR3FlushPage: GCPtr=%VGv\n", GCPtr));
1298
1299	//RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1300
1301	/*
1302	* Update the control registers before calling PGMFlushPage.
1303	*/
1304	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1305	pCtx->cr0 = env->cr[0];
1306	pCtx->cr3 = env->cr[3];
1307	pCtx->cr4 = env->cr[4];
1308
1309	/*
1310	* Let PGM do the rest.
1311	*/
1312	int rc = PGMInvalidatePage(pVM, GCPtr);
1313	if (VBOX_FAILURE(rc))
1314	{
1315	AssertMsgFailed(("remR3FlushPage %x %x %x %d failed!!\n", GCPtr));
1316	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1317	}
1318	//RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1319	}
1320
1321	/**
1322	* Set page table/dir entry. (called from tlb_set_page)
1323	*
1324	* @param env Pointer to cpu environment.
1325	*/
1326	void remR3SetPage(CPUState env, CPUTLBEntry pRead, CPUTLBEntry *pWrite, int prot, int is_user)
1327	{
1328	uint32_t virt_addr, addend;
1329
1330	Log2(("tlb_set_page_raw read (%x-%x) write (%x-%x) prot %x is_user %d\n", pRead->address, pRead->addend, pWrite->address, pWrite->addend, prot, is_user));
1331
1332	if (prot & PAGE_WRITE)
1333	{
1334	addend = pWrite->addend;
1335	virt_addr = pWrite->address;
1336	}
1337	else
1338	if (prot & PAGE_READ)
1339	{
1340	addend = pRead->addend;
1341	virt_addr = pRead->address;
1342	}
1343	else
1344	{
1345	// Should never happen!
1346	AssertMsgFailed(("tlb_set_page_raw unexpected protection flags %x\n", prot));
1347	return;
1348	}
1349
1350	// Clear IO_* flags (TODO: are they actually useful for us??)
1351	virt_addr &= ~0xFFF;
1352
1353	/*
1354	* Update the control registers before calling PGMFlushPage.
1355	*/
1356	PCPUMCTX pCtx = (PCPUMCTX)env->pVM->rem.s.pCtx;
1357	pCtx->cr0 = env->cr[0];
1358	pCtx->cr3 = env->cr[3];
1359	pCtx->cr4 = env->cr[4];
1360
1361	/*
1362	* Let PGM do the rest.
1363	*/
1364	int rc = PGMInvalidatePage(env->pVM, (RTGCPTR)virt_addr);
1365	if (VBOX_FAILURE(rc))
1366	{
1367	AssertMsgFailed(("RAWEx_SetPageEntry %x %x %d failed!!\n", virt_addr, prot, is_user));
1368	VM_FF_SET(env->pVM, VM_FF_PGM_SYNC_CR3);
1369	}
1370	}
1371
1372	/**
1373	* Called from tlb_protect_code in order to write monitor a code page.
1374	*
1375	* @param env Pointer to the CPU environment.
1376	* @param GCPtr Code page to monitor
1377	*/
1378	void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1379	{
1380	if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1381	&& !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1382	&& (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1383	&& !(env->eflags & VM_MASK) /* no V86 mode */
1384	&& !HWACCMIsEnabled(env->pVM))
1385	CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1386	}
1387
1388	/**
1389	* Called when the CPU is initialized, any of the CRx registers are changed or
1390	* when the A20 line is modified.
1391	*
1392	* @param env Pointer to the CPU environment.
1393	* @param fGlobal Set if the flush is global.
1394	*/
1395	void remR3FlushTLB(CPUState *env, bool fGlobal)
1396	{
1397	PVM pVM = env->pVM;
1398
1399	/*
1400	* When we're replaying invlpg instructions or restoring a saved
1401	* state we disable this path.
1402	*/
1403	if (pVM->rem.s.fIgnoreCR3Load)
1404	return;
1405
1406	/*
1407	* The caller doesn't check cr4, so we have to do that for ourselves.
1408	*/
1409	if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1410	fGlobal = true;
1411	Log(("remR3FlushTLB: CR0=%VGp CR3=%VGp CR4=%VGp %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1412
1413	/*
1414	* Update the control registers before calling PGMR3FlushTLB.
1415	*/
1416	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1417	pCtx->cr0 = env->cr[0];
1418	pCtx->cr3 = env->cr[3];
1419	pCtx->cr4 = env->cr[4];
1420
1421	/*
1422	* Let PGM do the rest.
1423	*/
1424	PGMFlushTLB(pVM, env->cr[3], fGlobal);
1425	}
1426
1427
1428	/**
1429	* Called when any of the cr0, cr4 or efer registers is updated.
1430	*
1431	* @param env Pointer to the CPU environment.
1432	*/
1433	void remR3ChangeCpuMode(CPUState *env)
1434	{
1435	int rc;
1436	PVM pVM = env->pVM;
1437
1438	/*
1439	* When we're replaying loads or restoring a saved
1440	* state this path is disabled.
1441	*/
1442	if (pVM->rem.s.fIgnoreCpuMode)
1443	return;
1444
1445	/*
1446	* Update the control registers before calling PGMR3ChangeMode()
1447	* as it may need to map whatever cr3 is pointing to.
1448	*/
1449	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1450	pCtx->cr0 = env->cr[0];
1451	pCtx->cr3 = env->cr[3];
1452	pCtx->cr4 = env->cr[4];
1453
1454	#ifdef TARGET_X86_64
1455	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1456	if (rc != VINF_SUCCESS)
1457	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], env->efer, rc);
1458	#else
1459	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1460	if (rc != VINF_SUCCESS)
1461	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], 0LL, rc);
1462	#endif
1463	}
1464
1465
1466	/**
1467	* Called from compiled code to run dma.
1468	*
1469	* @param env Pointer to the CPU environment.
1470	*/
1471	void remR3DmaRun(CPUState *env)
1472	{
1473	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1474	PDMR3DmaRun(env->pVM);
1475	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1476	}
1477
1478	/**
1479	* Called from compiled code to schedule pending timers in VMM
1480	*
1481	* @param env Pointer to the CPU environment.
1482	*/
1483	void remR3TimersRun(CPUState *env)
1484	{
1485	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1486	remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1487	TMR3TimerQueuesDo(env->pVM);
1488	remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1489	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1490	}
1491
1492	/**
1493	* Record trap occurance
1494	*
1495	* @returns VBox status code
1496	* @param env Pointer to the CPU environment.
1497	* @param uTrap Trap nr
1498	* @param uErrorCode Error code
1499	* @param pvNextEIP Next EIP
1500	*/
1501	int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1502	{
1503	PVM pVM = (PVM)env->pVM;
1504	#ifdef VBOX_WITH_STATISTICS
1505	static STAMCOUNTER aStatTrap[255];
1506	static bool aRegisters[ELEMENTS(aStatTrap)];
1507	#endif
1508
1509	#ifdef VBOX_WITH_STATISTICS
1510	if (uTrap < 255)
1511	{
1512	if (!aRegisters[uTrap])
1513	{
1514	aRegisters[uTrap] = true;
1515	char szStatName[64];
1516	RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1517	STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1518	}
1519	STAM_COUNTER_INC(&aStatTrap[uTrap]);
1520	}
1521	#endif
1522	Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1523	if(uTrap < 0x20)
1524	{
1525	remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1526
1527	if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 128)
1528	{
1529	LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1530	remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1531	return VERR_REM_TOO_MANY_TRAPS;
1532	}
1533	if(pVM->rem.s.uPendingException != uTrap \|\| pVM->rem.s.uPendingExcptEIP != env->eip \|\| pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1534	pVM->rem.s.cPendingExceptions = 1;
1535	pVM->rem.s.uPendingException = uTrap;
1536	pVM->rem.s.uPendingExcptEIP = env->eip;
1537	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1538	}
1539	else
1540	{
1541	pVM->rem.s.cPendingExceptions = 0;
1542	pVM->rem.s.uPendingException = uTrap;
1543	pVM->rem.s.uPendingExcptEIP = env->eip;
1544	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1545	}
1546	return VINF_SUCCESS;
1547	}
1548
1549	/*
1550	* Clear current active trap
1551	*
1552	* @param pVM VM Handle.
1553	*/
1554	void remR3TrapClear(PVM pVM)
1555	{
1556	pVM->rem.s.cPendingExceptions = 0;
1557	pVM->rem.s.uPendingException = 0;
1558	pVM->rem.s.uPendingExcptEIP = 0;
1559	pVM->rem.s.uPendingExcptCR2 = 0;
1560	}
1561
1562
1563	/**
1564	* Syncs the internal REM state with the VM.
1565	*
1566	* This must be called before REMR3Run() is invoked whenever when the REM
1567	* state is not up to date. Calling it several times in a row is not
1568	* permitted.
1569	*
1570	* @returns VBox status code.
1571	*
1572	* @param pVM VM Handle.
1573	*
1574	* @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1575	* no do this since the majority of the callers don't want any unnecessary of events
1576	* pending that would immediatly interrupt execution.
1577	*/
1578	REMR3DECL(int) REMR3State(PVM pVM)
1579	{
1580	Assert(!pVM->rem.s.fInREM);
1581	Log2(("REMR3State:\n"));
1582	STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1583	register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1584	register unsigned fFlags;
1585
1586	/*
1587	* Copy the registers which requires no special handling.
1588	*/
1589	Assert(R_EAX == 0);
1590	pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1591	Assert(R_ECX == 1);
1592	pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1593	Assert(R_EDX == 2);
1594	pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1595	Assert(R_EBX == 3);
1596	pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1597	Assert(R_ESP == 4);
1598	pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1599	Assert(R_EBP == 5);
1600	pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1601	Assert(R_ESI == 6);
1602	pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1603	Assert(R_EDI == 7);
1604	pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1605	pVM->rem.s.Env.eip = pCtx->eip;
1606
1607	pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1608
1609	pVM->rem.s.Env.cr[2] = pCtx->cr2;
1610
1611	/** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1612	pVM->rem.s.Env.dr[0] = pCtx->dr0;
1613	pVM->rem.s.Env.dr[1] = pCtx->dr1;
1614	pVM->rem.s.Env.dr[2] = pCtx->dr2;
1615	pVM->rem.s.Env.dr[3] = pCtx->dr3;
1616	pVM->rem.s.Env.dr[4] = pCtx->dr4;
1617	pVM->rem.s.Env.dr[5] = pCtx->dr5;
1618	pVM->rem.s.Env.dr[6] = pCtx->dr6;
1619	pVM->rem.s.Env.dr[7] = pCtx->dr7;
1620
1621	/*
1622	* Replay invlpg?
1623	*/
1624	if (pVM->rem.s.cInvalidatedPages)
1625	{
1626	pVM->rem.s.fIgnoreInvlPg = true;
1627	RTUINT i;
1628	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1629	{
1630	Log2(("REMR3State: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1631	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1632	}
1633	pVM->rem.s.fIgnoreInvlPg = false;
1634	pVM->rem.s.cInvalidatedPages = 0;
1635	}
1636
1637	/*
1638	* Registers which are seldomly changed and require special handling / order when changed.
1639	*/
1640	fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1641	if (fFlags & ( CPUM_CHANGED_CR4 \| CPUM_CHANGED_CR3 \| CPUM_CHANGED_CR0
1642	\| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_TR
1643	\| CPUM_CHANGED_FPU_REM \| CPUM_CHANGED_SYSENTER_MSR))
1644	{
1645	if (fFlags & CPUM_CHANGED_FPU_REM)
1646	save_raw_fp_state(&pVM->rem.s.Env, (uint8_t )&pCtx->fpu); / 'save' is an excellent name. */
1647
1648	if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1649	{
1650	pVM->rem.s.fIgnoreCR3Load = true;
1651	tlb_flush(&pVM->rem.s.Env, true);
1652	pVM->rem.s.fIgnoreCR3Load = false;
1653	}
1654
1655	if (fFlags & CPUM_CHANGED_CR4)
1656	{
1657	pVM->rem.s.fIgnoreCR3Load = true;
1658	pVM->rem.s.fIgnoreCpuMode = true;
1659	cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1660	pVM->rem.s.fIgnoreCpuMode = false;
1661	pVM->rem.s.fIgnoreCR3Load = false;
1662	}
1663
1664	if (fFlags & CPUM_CHANGED_CR0)
1665	{
1666	pVM->rem.s.fIgnoreCR3Load = true;
1667	pVM->rem.s.fIgnoreCpuMode = true;
1668	cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1669	pVM->rem.s.fIgnoreCpuMode = false;
1670	pVM->rem.s.fIgnoreCR3Load = false;
1671	}
1672
1673	if (fFlags & CPUM_CHANGED_CR3)
1674	{
1675	pVM->rem.s.fIgnoreCR3Load = true;
1676	cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1677	pVM->rem.s.fIgnoreCR3Load = false;
1678	}
1679
1680	if (fFlags & CPUM_CHANGED_GDTR)
1681	{
1682	pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1683	pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1684	}
1685
1686	if (fFlags & CPUM_CHANGED_IDTR)
1687	{
1688	pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1689	pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1690	}
1691
1692	if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1693	{
1694	pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1695	pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1696	pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1697	}
1698
1699	if (fFlags & CPUM_CHANGED_LDTR)
1700	{
1701	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1702	{
1703	pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1704	pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u32Base;
1705	pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1706	pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1707	}
1708	else
1709	sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1710	}
1711
1712	if (fFlags & CPUM_CHANGED_TR)
1713	{
1714	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1715	{
1716	pVM->rem.s.Env.tr.selector = pCtx->tr;
1717	pVM->rem.s.Env.tr.base = pCtx->trHid.u32Base;
1718	pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1719	pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1720	}
1721	else
1722	sync_tr(&pVM->rem.s.Env, pCtx->tr);
1723
1724	/** @note do_interrupt will fault if the busy flag is still set.... */
1725	pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1726	}
1727	}
1728
1729	/*
1730	* Update selector registers.
1731	* This must be done after we've synced gdt, ldt and crX registers
1732	* since we're reading the GDT/LDT om sync_seg. This will happen with
1733	* saved state which takes a quick dip into rawmode for instance.
1734	*/
1735	/*
1736	* Stack; Note first check this one as the CPL might have changed. The
1737	* wrong CPL can cause QEmu to raise an exception in sync_seg!!
1738	*/
1739
1740	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1741	{
1742	/* The hidden selector registers are valid in the CPU context. */
1743	/** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1744
1745	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1746	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1747	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1748	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1749	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1750	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1751
1752	/* Set current CPL. */
1753	if (pCtx->eflags.Bits.u1VM == 1)
1754	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1755	else
1756	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1757	}
1758	else
1759	{
1760	/* In 'normal' raw mode we don't have access to the hidden selector registers. */
1761	if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1762	{
1763	Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1764	if (pCtx->eflags.Bits.u1VM == 1)
1765	{
1766	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1767	pVM->rem.s.Env.segs[R_SS].selector = (uint16_t)pCtx->ss;
1768	}
1769	else
1770	{
1771	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1772	sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1773	#ifdef VBOX_WITH_STATISTICS
1774	if (pVM->rem.s.Env.segs[R_SS].newselector)
1775	{
1776	STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1777	}
1778	#endif
1779	}
1780	}
1781	else
1782	pVM->rem.s.Env.segs[R_SS].newselector = 0;
1783
1784	if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1785	{
1786	Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1787	if (pCtx->eflags.Bits.u1VM == 1)
1788	{
1789	pVM->rem.s.Env.segs[R_ES].selector = (uint16_t)pCtx->es;
1790	}
1791	else
1792	{
1793	sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1794	#ifdef VBOX_WITH_STATISTICS
1795	if (pVM->rem.s.Env.segs[R_ES].newselector)
1796	{
1797	STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1798	}
1799	#endif
1800	}
1801	}
1802	else
1803	pVM->rem.s.Env.segs[R_ES].newselector = 0;
1804
1805	if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1806	{
1807	Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1808	if (pCtx->eflags.Bits.u1VM == 1)
1809	{
1810	pVM->rem.s.Env.segs[R_CS].selector = (uint16_t)pCtx->cs;
1811	}
1812	else
1813	{
1814	sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1815	#ifdef VBOX_WITH_STATISTICS
1816	if (pVM->rem.s.Env.segs[R_CS].newselector)
1817	{
1818	STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1819	}
1820	#endif
1821	}
1822	}
1823	else
1824	pVM->rem.s.Env.segs[R_CS].newselector = 0;
1825
1826	if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1827	{
1828	Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1829	if (pCtx->eflags.Bits.u1VM == 1)
1830	{
1831	pVM->rem.s.Env.segs[R_DS].selector = (uint16_t)pCtx->ds;
1832	}
1833	else
1834	{
1835	sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1836	#ifdef VBOX_WITH_STATISTICS
1837	if (pVM->rem.s.Env.segs[R_DS].newselector)
1838	{
1839	STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1840	}
1841	#endif
1842	}
1843	}
1844	else
1845	pVM->rem.s.Env.segs[R_DS].newselector = 0;
1846
1847	/** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1848	* be the same but not the base/limit. */
1849	if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1850	{
1851	Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1852	if (pCtx->eflags.Bits.u1VM == 1)
1853	{
1854	pVM->rem.s.Env.segs[R_FS].selector = (uint16_t)pCtx->fs;
1855	}
1856	else
1857	{
1858	sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1859	#ifdef VBOX_WITH_STATISTICS
1860	if (pVM->rem.s.Env.segs[R_FS].newselector)
1861	{
1862	STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1863	}
1864	#endif
1865	}
1866	}
1867	else
1868	pVM->rem.s.Env.segs[R_FS].newselector = 0;
1869
1870	if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1871	{
1872	Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1873	if (pCtx->eflags.Bits.u1VM == 1)
1874	{
1875	pVM->rem.s.Env.segs[R_GS].selector = (uint16_t)pCtx->gs;
1876	}
1877	else
1878	{
1879	sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1880	#ifdef VBOX_WITH_STATISTICS
1881	if (pVM->rem.s.Env.segs[R_GS].newselector)
1882	{
1883	STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1884	}
1885	#endif
1886	}
1887	}
1888	else
1889	pVM->rem.s.Env.segs[R_GS].newselector = 0;
1890	}
1891
1892	/*
1893	* Check for traps.
1894	*/
1895	pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
1896	bool fIsSoftwareInterrupt;
1897	uint8_t u8TrapNo;
1898	int rc = TRPMQueryTrap(pVM, &u8TrapNo, &fIsSoftwareInterrupt);
1899	if (VBOX_SUCCESS(rc))
1900	{
1901	#ifdef DEBUG
1902	if (u8TrapNo == 0x80)
1903	{
1904	remR3DumpLnxSyscall(pVM);
1905	remR3DumpOBsdSyscall(pVM);
1906	}
1907	#endif
1908
1909	pVM->rem.s.Env.exception_index = u8TrapNo;
1910	if (!fIsSoftwareInterrupt)
1911	{
1912	pVM->rem.s.Env.exception_is_int = 0;
1913	pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
1914	}
1915	else
1916	{
1917	/*
1918	* The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
1919	* We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
1920	* for int03 and into.
1921	*/
1922	pVM->rem.s.Env.exception_is_int = 1;
1923	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 2;
1924	/* int 3 may be generated by one-byte 0xcc */
1925	if (u8TrapNo == 3)
1926	{
1927	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xcc)
1928	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1929	}
1930	/* int 4 may be generated by one-byte 0xce */
1931	else if (u8TrapNo == 4)
1932	{
1933	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xce)
1934	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1935	}
1936	}
1937
1938	/* get error code and cr2 if needed. */
1939	switch (u8TrapNo)
1940	{
1941	case 0x0e:
1942	pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
1943	/* fallthru */
1944	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
1945	pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
1946	break;
1947
1948	case 0x11: case 0x08:
1949	default:
1950	pVM->rem.s.Env.error_code = 0;
1951	break;
1952	}
1953
1954	/*
1955	* We can now reset the active trap since the recompiler is gonna have a go at it.
1956	*/
1957	rc = TRPMResetTrap(pVM);
1958	AssertRC(rc);
1959	Log2(("REMR3State: trap=%02x errcd=%VGv cr2=%VGv nexteip=%VGv%s\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.error_code,
1960	pVM->rem.s.Env.cr[2], pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
1961	//if (pVM->rem.s.Env.eip == 0x40005a2f)
1962	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP \| CPU_RAW_MODE_DISABLED \| CPU_RAWR0_MODE_DISABLED;
1963	}
1964
1965	/*
1966	* Clear old interrupt request flags; Check for pending hardware interrupts.
1967	* (See @remark for why we don't check for other FFs.)
1968	*/
1969	pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER);
1970	if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
1971	\|\| VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
1972	pVM->rem.s.Env.interrupt_request \|= CPU_INTERRUPT_HARD;
1973
1974	/*
1975	* We're now in REM mode.
1976	*/
1977	pVM->rem.s.fInREM = true;
1978	pVM->rem.s.cCanExecuteRaw = 0;
1979	STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
1980	Log2(("REMR3State: returns VINF_SUCCESS\n"));
1981	return VINF_SUCCESS;
1982	}
1983
1984
1985	/**
1986	* Syncs back changes in the REM state to the the VM state.
1987	*
1988	* This must be called after invoking REMR3Run().
1989	* Calling it several times in a row is not permitted.
1990	*
1991	* @returns VBox status code.
1992	*
1993	* @param pVM VM Handle.
1994	*/
1995	REMR3DECL(int) REMR3StateBack(PVM pVM)
1996	{
1997	Log2(("REMR3StateBack:\n"));
1998	Assert(pVM->rem.s.fInREM);
1999	STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2000	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2001
2002	/*
2003	* Copy back the registers.
2004	* This is done in the order they are declared in the CPUMCTX structure.
2005	*/
2006
2007	/** @todo FOP */
2008	/** @todo FPUIP */
2009	/** @todo CS */
2010	/** @todo FPUDP */
2011	/** @todo DS */
2012	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2013	pCtx->fpu.MXCSR = 0;
2014	pCtx->fpu.MXCSR_MASK = 0;
2015
2016	/** @todo check if FPU/XMM was actually used in the recompiler */
2017	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2018	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2019
2020	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2021	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2022	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2023	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2024	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2025	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2026	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2027
2028	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2029	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2030
2031	#ifdef VBOX_WITH_STATISTICS
2032	if (pVM->rem.s.Env.segs[R_SS].newselector)
2033	{
2034	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
2035	}
2036	if (pVM->rem.s.Env.segs[R_GS].newselector)
2037	{
2038	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
2039	}
2040	if (pVM->rem.s.Env.segs[R_FS].newselector)
2041	{
2042	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
2043	}
2044	if (pVM->rem.s.Env.segs[R_ES].newselector)
2045	{
2046	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
2047	}
2048	if (pVM->rem.s.Env.segs[R_DS].newselector)
2049	{
2050	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2051	}
2052	if (pVM->rem.s.Env.segs[R_CS].newselector)
2053	{
2054	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2055	}
2056	#endif
2057	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2058	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2059	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2060	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2061	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2062
2063	pCtx->eip = pVM->rem.s.Env.eip;
2064	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2065
2066	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2067	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2068	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2069	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2070
2071	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2072	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2073	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2074	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2075	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2076	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2077	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2078	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2079
2080	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2081	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2082	{
2083	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2084	STAM_COUNTER_INC(&gStatREMGDTChange);
2085	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2086	}
2087
2088	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2089	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2090	{
2091	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2092	STAM_COUNTER_INC(&gStatREMIDTChange);
2093	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2094	}
2095
2096	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2097	{
2098	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2099	STAM_COUNTER_INC(&gStatREMLDTRChange);
2100	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2101	}
2102	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2103	{
2104	pCtx->tr = pVM->rem.s.Env.tr.selector;
2105	STAM_COUNTER_INC(&gStatREMTRChange);
2106	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2107	}
2108
2109	/** @todo These values could still be out of sync! */
2110	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2111	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2112	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2113	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2114
2115	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2116	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2117	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2118
2119	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2120	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2121	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2122
2123	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2124	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2125	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2126
2127	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2128	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2129	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2130
2131	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2132	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2133	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2134
2135	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2136	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2137	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2138
2139	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2140	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2141	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2142
2143	/* Sysenter MSR */
2144	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2145	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2146	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2147
2148	remR3TrapClear(pVM);
2149
2150	/*
2151	* Check for traps.
2152	*/
2153	if ( pVM->rem.s.Env.exception_index >= 0
2154	&& pVM->rem.s.Env.exception_index < 256)
2155	{
2156	Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2157	int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int);
2158	AssertRC(rc);
2159	switch (pVM->rem.s.Env.exception_index)
2160	{
2161	case 0x0e:
2162	TRPMSetFaultAddress(pVM, pCtx->cr2);
2163	/* fallthru */
2164	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2165	case 0x11: case 0x08: /* 0 */
2166	TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2167	break;
2168	}
2169
2170	}
2171
2172	/*
2173	* We're not longer in REM mode.
2174	*/
2175	pVM->rem.s.fInREM = false;
2176	STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2177	Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2178	return VINF_SUCCESS;
2179	}
2180
2181
2182	/**
2183	* This is called by the disassembler when it wants to update the cpu state
2184	* before for instance doing a register dump.
2185	*/
2186	static void remR3StateUpdate(PVM pVM)
2187	{
2188	Assert(pVM->rem.s.fInREM);
2189	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2190
2191	/*
2192	* Copy back the registers.
2193	* This is done in the order they are declared in the CPUMCTX structure.
2194	*/
2195
2196	/** @todo FOP */
2197	/** @todo FPUIP */
2198	/** @todo CS */
2199	/** @todo FPUDP */
2200	/** @todo DS */
2201	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2202	pCtx->fpu.MXCSR = 0;
2203	pCtx->fpu.MXCSR_MASK = 0;
2204
2205	/** @todo check if FPU/XMM was actually used in the recompiler */
2206	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2207	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2208
2209	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2210	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2211	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2212	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2213	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2214	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2215	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2216
2217	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2218	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2219
2220	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2221	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2222	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2223	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2224	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2225
2226	pCtx->eip = pVM->rem.s.Env.eip;
2227	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2228
2229	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2230	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2231	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2232	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2233
2234	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2235	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2236	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2237	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2238	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2239	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2240	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2241	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2242
2243	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2244	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2245	{
2246	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2247	STAM_COUNTER_INC(&gStatREMGDTChange);
2248	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2249	}
2250
2251	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2252	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2253	{
2254	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2255	STAM_COUNTER_INC(&gStatREMIDTChange);
2256	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2257	}
2258
2259	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2260	{
2261	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2262	STAM_COUNTER_INC(&gStatREMLDTRChange);
2263	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2264	}
2265	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2266	{
2267	pCtx->tr = pVM->rem.s.Env.tr.selector;
2268	STAM_COUNTER_INC(&gStatREMTRChange);
2269	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2270	}
2271
2272	/** @todo These values could still be out of sync! */
2273	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2274	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2275	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2276	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2277
2278	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2279	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2280	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2281
2282	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2283	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2284	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2285
2286	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2287	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2288	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2289
2290	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2291	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2292	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2293
2294	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2295	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2296	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2297
2298	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2299	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2300	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2301
2302	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2303	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2304	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2305
2306	/* Sysenter MSR */
2307	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2308	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2309	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2310	}
2311
2312
2313	/**
2314	* Update the VMM state information if we're currently in REM.
2315	*
2316	* This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2317	* we're currently executing in REM and the VMM state is invalid. This method will of
2318	* course check that we're executing in REM before syncing any data over to the VMM.
2319	*
2320	* @param pVM The VM handle.
2321	*/
2322	REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2323	{
2324	if (pVM->rem.s.fInREM)
2325	remR3StateUpdate(pVM);
2326	}
2327
2328
2329	#undef LOG_GROUP
2330	#define LOG_GROUP LOG_GROUP_REM
2331
2332
2333	/**
2334	* Notify the recompiler about Address Gate 20 state change.
2335	*
2336	* This notification is required since A20 gate changes are
2337	* initialized from a device driver and the VM might just as
2338	* well be in REM mode as in RAW mode.
2339	*
2340	* @param pVM VM handle.
2341	* @param fEnable True if the gate should be enabled.
2342	* False if the gate should be disabled.
2343	*/
2344	REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2345	{
2346	LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2347	VM_ASSERT_EMT(pVM);
2348	cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2349	}
2350
2351
2352	/**
2353	* Replays the invalidated recorded pages.
2354	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2355	*
2356	* @param pVM VM handle.
2357	*/
2358	REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2359	{
2360	VM_ASSERT_EMT(pVM);
2361
2362	/*
2363	* Sync the required registers.
2364	*/
2365	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2366	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2367	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2368	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2369
2370	/*
2371	* Replay the flushes.
2372	*/
2373	pVM->rem.s.fIgnoreInvlPg = true;
2374	RTUINT i;
2375	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2376	{
2377	Log2(("REMR3ReplayInvalidatedPages: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2378	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2379	}
2380	pVM->rem.s.fIgnoreInvlPg = false;
2381	pVM->rem.s.cInvalidatedPages = 0;
2382	}
2383
2384
2385	/**
2386	* Replays the invalidated recorded pages.
2387	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2388	*
2389	* @param pVM VM handle.
2390	*/
2391	REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2392	{
2393	LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2394	VM_ASSERT_EMT(pVM);
2395
2396	/*
2397	* Replay the flushes.
2398	*/
2399	RTUINT i;
2400	const RTUINT c = pVM->rem.s.cHandlerNotifications;
2401	pVM->rem.s.cHandlerNotifications = 0;
2402	for (i = 0; i < c; i++)
2403	{
2404	PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2405	switch (pRec->enmKind)
2406	{
2407	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2408	REMR3NotifyHandlerPhysicalRegister(pVM,
2409	pRec->u.PhysicalRegister.enmType,
2410	pRec->u.PhysicalRegister.GCPhys,
2411	pRec->u.PhysicalRegister.cb,
2412	pRec->u.PhysicalRegister.fHasHCHandler);
2413	break;
2414
2415	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2416	REMR3NotifyHandlerPhysicalDeregister(pVM,
2417	pRec->u.PhysicalDeregister.enmType,
2418	pRec->u.PhysicalDeregister.GCPhys,
2419	pRec->u.PhysicalDeregister.cb,
2420	pRec->u.PhysicalDeregister.fHasHCHandler,
2421	pRec->u.PhysicalDeregister.pvHCPtr);
2422	break;
2423
2424	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2425	REMR3NotifyHandlerPhysicalModify(pVM,
2426	pRec->u.PhysicalModify.enmType,
2427	pRec->u.PhysicalModify.GCPhysOld,
2428	pRec->u.PhysicalModify.GCPhysNew,
2429	pRec->u.PhysicalModify.cb,
2430	pRec->u.PhysicalModify.fHasHCHandler,
2431	pRec->u.PhysicalModify.pvHCPtr);
2432	break;
2433
2434	default:
2435	AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2436	break;
2437	}
2438	}
2439	}
2440
2441
2442	/**
2443	* Notify REM about changed code page.
2444	*
2445	* @returns VBox status code.
2446	* @param pVM VM handle.
2447	* @param pvCodePage Code page address
2448	*/
2449	REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2450	{
2451	int rc;
2452	RTGCPHYS PhysGC;
2453	uint64_t flags;
2454
2455	VM_ASSERT_EMT(pVM);
2456
2457	/*
2458	* Get the physical page address.
2459	*/
2460	rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2461	if (rc == VINF_SUCCESS)
2462	{
2463	/*
2464	* Sync the required registers and flush the whole page.
2465	* (Easier to do the whole page than notifying it about each physical
2466	* byte that was changed.
2467	*/
2468	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2469	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2470	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2471	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2472
2473	tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2474	}
2475	return VINF_SUCCESS;
2476	}
2477
2478	/**
2479	* Notification about a successful MMR3PhysRegister() call.
2480	*
2481	* @param pVM VM handle.
2482	* @param GCPhys The physical address the RAM.
2483	* @param cb Size of the memory.
2484	* @param pvRam The HC address of the RAM.
2485	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2486	*/
2487	REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
2488	{
2489	Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2490	VM_ASSERT_EMT(pVM);
2491
2492	/*
2493	* Validate input - we trust the caller.
2494	*/
2495	Assert(!GCPhys \|\| pvRam);
2496	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2497	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2498	Assert(cb);
2499	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2500
2501	/*
2502	* Base ram?
2503	*/
2504	if (!GCPhys)
2505	{
2506	#ifndef PGM_DYNAMIC_RAM_ALLOC
2507	AssertRelease(!phys_ram_base);
2508	phys_ram_base = pvRam;
2509	#endif
2510	phys_ram_size = cb;
2511	phys_ram_dirty = MMR3HeapAllocZ(pVM, MM_TAG_REM, cb >> PAGE_SHIFT);
2512	AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", cb >> PAGE_SHIFT));
2513	}
2514	#ifndef PGM_DYNAMIC_RAM_ALLOC
2515	AssertRelease(phys_ram_base);
2516	#endif
2517
2518	/*
2519	* Register the ram.
2520	*/
2521	#ifdef PGM_DYNAMIC_RAM_ALLOC
2522	if (!GCPhys)
2523	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_RAM_MISSING);
2524	else
2525	{
2526	uint32_t i;
2527
2528	cpu_register_physical_memory(GCPhys, cb, GCPhys \| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2529
2530	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2531	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2532	{
2533	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2534	{
2535	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2536	pVM->rem.s.aPhysReg[i].cb = cb;
2537	break;
2538	}
2539	}
2540	if (i == pVM->rem.s.cPhysRegistrations)
2541	{
2542	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2543	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2544	pVM->rem.s.aPhysReg[i].cb = cb;
2545	pVM->rem.s.cPhysRegistrations++;
2546	}
2547	}
2548	#else
2549	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvRam - (uintptr_t)phys_ram_base)
2550	\| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2551	#endif
2552	}
2553
2554
2555	/**
2556	* Notification about a successful PGMR3PhysRegisterChunk() call.
2557	*
2558	* @param pVM VM handle.
2559	* @param GCPhys The physical address the RAM.
2560	* @param cb Size of the memory.
2561	* @param pvRam The HC address of the RAM.
2562	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2563	*/
2564	REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2565	{
2566	uint32_t idx;
2567
2568	Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2569	VM_ASSERT_EMT(pVM);
2570
2571	/*
2572	* Validate input - we trust the caller.
2573	*/
2574	Assert(pvRam);
2575	Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2576	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2577	Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2578	Assert(fFlags == 0 /* normal RAM */);
2579
2580	if (!pVM->rem.s.paHCVirtToGCPhys)
2581	{
2582	uint32_t size = (_4G >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(REMCHUNKINFO);
2583
2584	Assert(phys_ram_size);
2585
2586	pVM->rem.s.paHCVirtToGCPhys = (PREMCHUNKINFO)MMR3HeapAllocZ(pVM, MM_TAG_REM, size);
2587	pVM->rem.s.paGCPhysToHCVirt = (RTHCPTR)MMR3HeapAllocZ(pVM, MM_TAG_REM, (phys_ram_size >> PGM_DYNAMIC_CHUNK_SHIFT)*sizeof(RTHCPTR));
2588	}
2589	pVM->rem.s.paGCPhysToHCVirt[GCPhys >> PGM_DYNAMIC_CHUNK_SHIFT] = pvRam;
2590
2591	idx = (pvRam >> PGM_DYNAMIC_CHUNK_SHIFT);
2592	if (!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1)
2593	{
2594	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1 = pvRam;
2595	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 = GCPhys;
2596	}
2597	else
2598	{
2599	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2);
2600	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2 = pvRam;
2601	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 = GCPhys;
2602	}
2603	/* Does the region spawn two chunks? */
2604	if (pvRam & PGM_DYNAMIC_CHUNK_OFFSET_MASK)
2605	{
2606	if (!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1)
2607	{
2608	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1 = pvRam;
2609	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys1 = GCPhys;
2610	}
2611	else
2612	{
2613	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2);
2614	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2 = pvRam;
2615	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys2 = GCPhys;
2616	}
2617	}
2618	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2619	}
2620
2621	/**
2622	* Convert GC physical address to HC virt
2623	*
2624	* @returns The HC virt address corresponding to addr.
2625	* @param env The cpu environment.
2626	* @param addr The physical address.
2627	*/
2628	void remR3GCPhys2HCVirt(void env, target_ulong addr)
2629	{
2630	#ifdef PGM_DYNAMIC_RAM_ALLOC
2631	PVM pVM = ((CPUState *)env)->pVM;
2632	uint32_t i;
2633
2634	/* lookup in pVM->rem.s.aPhysReg array first (for ROM range(s) inside the guest's RAM) */
2635	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2636	{
2637	uint32_t off = addr - pVM->rem.s.aPhysReg[i].GCPhys;
2638	if (off < pVM->rem.s.aPhysReg[i].cb)
2639	{
2640	Log(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].HCVirt + off));
2641	return (void *)(pVM->rem.s.aPhysReg[i].HCVirt + off);
2642	}
2643	}
2644	AssertMsg(addr < phys_ram_size, ("remR3GCPhys2HCVirt: unknown physical address %x\n", addr));
2645	Log(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK)));
2646	return (void *)(pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2647	#else
2648	return phys_ram_base + addr;
2649	#endif
2650	}
2651
2652	/**
2653	* Convert GC physical address to HC virt
2654	*
2655	* @returns The HC virt address corresponding to addr.
2656	* @param env The cpu environment.
2657	* @param addr The physical address.
2658	*/
2659	target_ulong remR3HCVirt2GCPhys(void env, void addr)
2660	{
2661	#ifdef PGM_DYNAMIC_RAM_ALLOC
2662	PVM pVM = ((CPUState *)env)->pVM;
2663	RTHCUINTPTR HCVirt = (RTHCUINTPTR)addr;
2664	uint32_t idx = (HCVirt >> PGM_DYNAMIC_CHUNK_SHIFT);
2665	RTHCUINTPTR off;
2666	RTUINT i;
2667
2668	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1;
2669
2670	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1
2671	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2672	{
2673	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off));
2674	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off;
2675	}
2676
2677	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2;
2678	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2
2679	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2680	{
2681	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off));
2682	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off;
2683	}
2684
2685	/* Must be externally registered RAM/ROM range */
2686	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2687	{
2688	uint32_t off = HCVirt - pVM->rem.s.aPhysReg[i].HCVirt;
2689	if (off < pVM->rem.s.aPhysReg[i].cb)
2690	{
2691	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].GCPhys + off));
2692	return pVM->rem.s.aPhysReg[i].GCPhys + off;
2693	}
2694	}
2695	AssertReleaseMsgFailed(("No translation for physical address %VHv???\n", addr));
2696	return 0;
2697	#else
2698	return (target_ulong)addr - (target_ulong)phys_ram_base;
2699	#endif
2700	}
2701
2702	/**
2703	* Grows dynamically allocated guest RAM.
2704	* Will raise a fatal error if the operation fails.
2705	*
2706	* @param physaddr The physical address.
2707	*/
2708	void remR3GrowDynRange(unsigned long physaddr)
2709	{
2710	int rc;
2711	PVM pVM = cpu_single_env->pVM;
2712
2713	Log(("remR3GrowDynRange %VGp\n", physaddr));
2714	rc = PGM3PhysGrowRange(pVM, (RTGCPHYS)physaddr);
2715	if (VBOX_SUCCESS(rc))
2716	return;
2717
2718	LogRel(("\nUnable to allocate guest RAM chunk at %VGp\n", physaddr));
2719	cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %VGp\n", physaddr);
2720	AssertFatalFailed();
2721	}
2722
2723	/**
2724	* Notification about a successful MMR3PhysRomRegister() call.
2725	*
2726	* @param pVM VM handle.
2727	* @param GCPhys The physical address of the ROM.
2728	* @param cb The size of the ROM.
2729	* @param pvCopy Pointer to the ROM copy.
2730	*/
2731	REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy)
2732	{
2733	#ifdef PGM_DYNAMIC_RAM_ALLOC
2734	uint32_t i;
2735	#endif
2736	Log(("REMR3NotifyPhysRomRegister: GCPhys=%VGp cb=%d pvCopy=%p\n", GCPhys, cb, pvCopy));
2737	VM_ASSERT_EMT(pVM);
2738
2739	/*
2740	* Validate input - we trust the caller.
2741	*/
2742	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2743	Assert(cb);
2744	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2745	Assert(pvCopy);
2746	Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2747
2748	/*
2749	* Register the rom.
2750	*/
2751	#ifdef PGM_DYNAMIC_RAM_ALLOC
2752	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_ROM);
2753	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2754	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2755	{
2756	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2757	{
2758	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2759	pVM->rem.s.aPhysReg[i].cb = cb;
2760	break;
2761	}
2762	}
2763	if (i == pVM->rem.s.cPhysRegistrations)
2764	{
2765	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2766	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2767	pVM->rem.s.aPhysReg[i].cb = cb;
2768	pVM->rem.s.cPhysRegistrations++;
2769	}
2770	#else
2771	AssertRelease(phys_ram_base);
2772	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvCopy - (uintptr_t)phys_ram_base) \| IO_MEM_ROM);
2773	#endif
2774	Log2(("%.64Vhxd\n", (char *)pvCopy + cb - 64));
2775	}
2776
2777
2778	/**
2779	* Notification about a successful MMR3PhysRegister() call.
2780	*
2781	* @param pVM VM Handle.
2782	* @param GCPhys Start physical address.
2783	* @param cb The size of the range.
2784	*/
2785	REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2786	{
2787	LogFlow(("REMR3NotifyPhysReserve: GCPhys=%VGp cb=%d\n", GCPhys, cb));
2788	VM_ASSERT_EMT(pVM);
2789
2790	/*
2791	* Validate input - we trust the caller.
2792	*/
2793	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2794	Assert(cb);
2795	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2796
2797	/*
2798	* Unassigning the memory.
2799	*/
2800	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2801	}
2802
2803
2804	/**
2805	* Notification about a successful PGMR3HandlerPhysicalRegister() call.
2806	*
2807	* @param pVM VM Handle.
2808	* @param enmType Handler type.
2809	* @param GCPhys Handler range address.
2810	* @param cb Size of the handler range.
2811	* @param fHasHCHandler Set if the handler has a HC callback function.
2812	*
2813	* @remark MMR3PhysRomRegister assumes that this function will not apply the
2814	* Handler memory type to memory which has no HC handler.
2815	*/
2816	REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2817	{
2818	LogFlow(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d\n",
2819	enmType, GCPhys, cb, fHasHCHandler));
2820	VM_ASSERT_EMT(pVM);
2821	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2822	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2823
2824	if (pVM->rem.s.cHandlerNotifications)
2825	REMR3ReplayHandlerNotifications(pVM);
2826
2827	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2828	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2829	else if (fHasHCHandler)
2830	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2831	}
2832
2833
2834	/**
2835	* Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2836	*
2837	* @param pVM VM Handle.
2838	* @param enmType Handler type.
2839	* @param GCPhys Handler range address.
2840	* @param cb Size of the handler range.
2841	* @param fHasHCHandler Set if the handler has a HC callback function.
2842	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2843	*/
2844	REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2845	{
2846	LogFlow(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p RAM=%08x\n",
2847	enmType, GCPhys, cb, fHasHCHandler, pvHCPtr, MMR3PhysGetRamSize(pVM)));
2848	VM_ASSERT_EMT(pVM);
2849
2850	if (pVM->rem.s.cHandlerNotifications)
2851	REMR3ReplayHandlerNotifications(pVM);
2852
2853	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2854	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2855	else if (fHasHCHandler)
2856	{
2857	if (!pvHCPtr)
2858	{
2859	Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2860	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2861	}
2862	else
2863	{
2864	/* This is not prefect, but it'll do for PD monitoring... */
2865	Assert(cb == PAGE_SIZE);
2866	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2867	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2868	#ifdef PGM_DYNAMIC_RAM_ALLOC
2869	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2870	#else
2871	cpu_register_physical_memory(GCPhys, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2872	#endif
2873	}
2874	}
2875	}
2876
2877
2878	/**
2879	* Notification about a successful PGMR3HandlerPhysicalModify() call.
2880	*
2881	* @param pVM VM Handle.
2882	* @param enmType Handler type.
2883	* @param GCPhysOld Old handler range address.
2884	* @param GCPhysNew New handler range address.
2885	* @param cb Size of the handler range.
2886	* @param fHasHCHandler Set if the handler has a HC callback function.
2887	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2888	*/
2889	REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2890	{
2891	LogFlow(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%VGp GCPhysNew=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p\n",
2892	enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, pvHCPtr));
2893	VM_ASSERT_EMT(pVM);
2894	AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2895
2896	if (pVM->rem.s.cHandlerNotifications)
2897	REMR3ReplayHandlerNotifications(pVM);
2898
2899	if (fHasHCHandler)
2900	{
2901	/*
2902	* Reset the old page.
2903	*/
2904	if (!pvHCPtr)
2905	cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2906	else
2907	{
2908	/* This is not prefect, but it'll do for PD monitoring... */
2909	Assert(cb == PAGE_SIZE);
2910	Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2911	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2912	#ifdef PGM_DYNAMIC_RAM_ALLOC
2913	cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2914	#else
2915	cpu_register_physical_memory(GCPhysOld, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2916	#endif
2917	}
2918
2919	/*
2920	* Update the new page.
2921	*/
2922	Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2923	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2924	cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2925	}
2926	}
2927
2928
2929	/**
2930	* Checks if we're handling access to this page or not.
2931	*
2932	* @returns true if we're trapping access.
2933	* @returns false if we aren't.
2934	* @param pVM The VM handle.
2935	* @param GCPhys The physical address.
2936	*
2937	* @remark This function will only work correctly in VBOX_STRICT builds!
2938	*/
2939	REMDECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
2940	{
2941	#ifdef VBOX_STRICT
2942	if (pVM->rem.s.cHandlerNotifications)
2943	REMR3ReplayHandlerNotifications(pVM);
2944
2945	unsigned long off = get_phys_page_offset(GCPhys);
2946	return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
2947	\|\| (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
2948	\|\| (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
2949	#else
2950	return false;
2951	#endif
2952	}
2953
2954
2955	/**
2956	* Deals with a rare case in get_phys_addr_code where the code
2957	* is being monitored.
2958	*
2959	* It could also be an MMIO page, in which case we will raise a fatal error.
2960	*
2961	* @returns The physical address corresponding to addr.
2962	* @param env The cpu environment.
2963	* @param addr The virtual address.
2964	* @param pTLBEntry The TLB entry.
2965	*/
2966	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry)
2967	{
2968	PVM pVM = env->pVM;
2969	if ((pTLBEntry->address & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
2970	{
2971	target_ulong ret = pTLBEntry->addend + addr;
2972	AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%VGv address=%VGv addend=%VGp ret=%VGp\n",
2973	(RTGCPTR)addr, (RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, ret);
2974	return ret;
2975	}
2976	LogRel(("\nTrying to execute code with memory type address=%VGv addend=%VGp at %VGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
2977	"*** handlers\n",
2978	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
2979	DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
2980	LogRel(("*** mmio\n"));
2981	DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
2982	LogRel(("*** phys\n"));
2983	DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
2984	cpu_abort(env, "Trying to execute code with memory type address=%VGv addend=%VGp at %VGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
2985	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
2986	AssertFatalFailed();
2987	}
2988
2989	/**
2990	* Read guest RAM and ROM.
2991	*
2992	* @param pbSrcPhys The source address. Relative to guest RAM.
2993	* @param pvDst The destination address.
2994	* @param cb Number of bytes
2995	*/
2996	void remR3PhysReadBytes(uint8_t pbSrcPhys, void pvDst, unsigned cb)
2997	{
2998	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2999
3000	/*
3001	* Calc the physical address ('off') and check that it's within the RAM.
3002	* ROM is accessed this way, even if it's not part of the RAM.
3003	*/
3004	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3005	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3006	if (off < (uintptr_t)phys_ram_size)
3007	PGMPhysRead(cpu_single_env->pVM, (RTGCPHYS)off, pvDst, cb);
3008	else
3009	{
3010	/* ROM range outside physical RAM, HC address passed directly */
3011	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3012	memcpy(pvDst, pbSrcPhys, cb);
3013	}
3014	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3015	}
3016
3017	/** @todo r=bird: s/Byte/U8/ s/Word/U16/ s/Dword/U32/, see MMIO and other functions.
3018	* It could be an idea to inline these wrapper functions... */
3019
3020	/**
3021	* Read guest RAM and ROM.
3022	*
3023	* @param pbSrcPhys The source address. Relative to guest RAM.
3024	*/
3025	uint8_t remR3PhysReadUByte(uint8_t *pbSrcPhys)
3026	{
3027	uint8_t val;
3028
3029	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3030
3031	/*
3032	* Calc the physical address ('off') and check that it's within the RAM.
3033	* ROM is accessed this way, even if it's not part of the RAM.
3034	*/
3035	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3036	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3037	if (off < (uintptr_t)phys_ram_size)
3038	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3039	else
3040	{
3041	/* ROM range outside physical RAM, HC address passed directly */
3042	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3043	val = *pbSrcPhys;
3044	}
3045	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3046	return val;
3047	}
3048
3049	/**
3050	* Read guest RAM and ROM.
3051	*
3052	* @param pbSrcPhys The source address. Relative to guest RAM.
3053	*/
3054	int8_t remR3PhysReadSByte(uint8_t *pbSrcPhys)
3055	{
3056	int8_t val;
3057
3058	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3059
3060	/*
3061	* Calc the physical address ('off') and check that it's within the RAM.
3062	* ROM is accessed this way, even if it's not part of the RAM.
3063	*/
3064	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3065	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3066	if (off < (uintptr_t)phys_ram_size)
3067	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3068	else
3069	{
3070	/* ROM range outside physical RAM, HC address passed directly */
3071	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3072	val = (int8_t )pbSrcPhys;
3073	}
3074	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3075	return val;
3076	}
3077
3078	/**
3079	* Read guest RAM and ROM.
3080	*
3081	* @param pbSrcPhys The source address. Relative to guest RAM.
3082	*/
3083	uint16_t remR3PhysReadUWord(uint8_t *pbSrcPhys)
3084	{
3085	uint16_t val;
3086
3087	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3088
3089	/*
3090	* Calc the physical address ('off') and check that it's within the RAM.
3091	* ROM is accessed this way, even if it's not part of the RAM.
3092	*/
3093	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3094	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3095	if (off < (uintptr_t)phys_ram_size)
3096	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3097	else
3098	{
3099	/* ROM range outside physical RAM, HC address passed directly */
3100	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3101	val = (uint16_t )pbSrcPhys;
3102	}
3103	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3104	return val;
3105	}
3106
3107	/**
3108	* Read guest RAM and ROM.
3109	*
3110	* @param pbSrcPhys The source address. Relative to guest RAM.
3111	*/
3112	int16_t remR3PhysReadSWord(uint8_t *pbSrcPhys)
3113	{
3114	int16_t val;
3115
3116	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3117
3118	/*
3119	* Calc the physical address ('off') and check that it's within the RAM.
3120	* ROM is accessed this way, even if it's not part of the RAM.
3121	*/
3122	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3123	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3124	if (off < (uintptr_t)phys_ram_size)
3125	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3126	else
3127	{
3128	/* ROM range outside physical RAM, HC address passed directly */
3129	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3130	val = (int16_t )pbSrcPhys;
3131	}
3132	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3133	return val;
3134	}
3135
3136	/**
3137	* Read guest RAM and ROM.
3138	*
3139	* @param pbSrcPhys The source address. Relative to guest RAM.
3140	*/
3141	uint32_t remR3PhysReadULong(uint8_t *pbSrcPhys)
3142	{
3143	uint32_t val;
3144
3145	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3146
3147	/*
3148	* Calc the physical address ('off') and check that it's within the RAM.
3149	* ROM is accessed this way, even if it's not part of the RAM.
3150	*/
3151	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3152	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3153	if (off < (uintptr_t)phys_ram_size)
3154	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3155	else
3156	{
3157	/* ROM range outside physical RAM, HC address passed directly */
3158	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3159	val = (uint32_t )pbSrcPhys;
3160	}
3161	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3162	return val;
3163	}
3164
3165	/**
3166	* Read guest RAM and ROM.
3167	*
3168	* @param pbSrcPhys The source address. Relative to guest RAM.
3169	*/
3170	int32_t remR3PhysReadSLong(uint8_t *pbSrcPhys)
3171	{
3172	int32_t val;
3173
3174	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3175
3176	/*
3177	* Calc the physical address ('off') and check that it's within the RAM.
3178	* ROM is accessed this way, even if it's not part of the RAM.
3179	*/
3180	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3181	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3182	if (off < (uintptr_t)phys_ram_size)
3183	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3184	else
3185	{
3186	/* ROM range outside physical RAM, HC address passed directly */
3187	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3188	val = (int32_t )pbSrcPhys;
3189	}
3190	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3191	return val;
3192	}
3193
3194	/**
3195	* Write guest RAM.
3196	*
3197	* @param pbDstPhys The destination address. Relative to guest RAM.
3198	* @param pvSrc The source address.
3199	* @param cb Number of bytes to write
3200	*/
3201	void remR3PhysWriteBytes(uint8_t pbDstPhys, const void pvSrc, unsigned cb)
3202	{
3203	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3204	/*
3205	* Calc the physical address ('off') and check that it's within the RAM.
3206	*/
3207	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3208	if (off < (uintptr_t)phys_ram_size)
3209	PGMPhysWrite(cpu_single_env->pVM, (RTGCPHYS)off, pvSrc, cb);
3210	else
3211	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, cb));
3212	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3213	}
3214
3215
3216	/**
3217	* Write guest RAM.
3218	*
3219	* @param pbDstPhys The destination address. Relative to guest RAM.
3220	* @param val Value
3221	*/
3222	void remR3PhysWriteByte(uint8_t *pbDstPhys, uint8_t val)
3223	{
3224	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3225	/*
3226	* Calc the physical address ('off') and check that it's within the RAM.
3227	*/
3228	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3229	if (off < (uintptr_t)phys_ram_size)
3230	PGMR3PhysWriteByte(cpu_single_env->pVM, (RTGCPHYS)off, val);
3231	else
3232	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 1));
3233	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3234	}
3235
3236	/**
3237	* Write guest RAM.
3238	*
3239	* @param pbDstPhys The destination address. Relative to guest RAM.
3240	* @param val Value
3241	*/
3242	void remR3PhysWriteWord(uint8_t *pbDstPhys, uint16_t val)
3243	{
3244	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3245	/*
3246	* Calc the physical address ('off') and check that it's within the RAM.
3247	*/
3248	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3249	if (off < (uintptr_t)phys_ram_size)
3250	PGMR3PhysWriteWord(cpu_single_env->pVM, (RTGCPHYS)off, val);
3251	else
3252	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 2));
3253	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3254	}
3255
3256	/**
3257	* Write guest RAM.
3258	*
3259	* @param pbDstPhys The destination address. Relative to guest RAM.
3260	* @param val Value
3261	*/
3262	void remR3PhysWriteDword(uint8_t *pbDstPhys, uint32_t val)
3263	{
3264	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3265	/*
3266	* Calc the physical address ('off') and check that it's within the RAM.
3267	*/
3268	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3269	if (off < (uintptr_t)phys_ram_size)
3270	PGMR3PhysWriteDword(cpu_single_env->pVM, (RTGCPHYS)off, val);
3271	else
3272	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 4));
3273	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3274	}
3275
3276
3277
3278	#undef LOG_GROUP
3279	#define LOG_GROUP LOG_GROUP_REM_MMIO
3280
3281	/** Read MMIO memory. */
3282	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3283	{
3284	uint32_t u32 = 0;
3285	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3286	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3287	Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32));
3288	return u32;
3289	}
3290
3291	/** Read MMIO memory. */
3292	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3293	{
3294	uint32_t u32 = 0;
3295	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3296	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3297	Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32));
3298	return u32;
3299	}
3300
3301	/** Read MMIO memory. */
3302	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3303	{
3304	uint32_t u32 = 0;
3305	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3306	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3307	Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32));
3308	return u32;
3309	}
3310
3311	/** Write to MMIO memory. */
3312	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3313	{
3314	Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3315	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3316	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3317	}
3318
3319	/** Write to MMIO memory. */
3320	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3321	{
3322	Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3323	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3324	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3325	}
3326
3327	/** Write to MMIO memory. */
3328	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3329	{
3330	Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3331	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3332	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3333	}
3334
3335
3336	#undef LOG_GROUP
3337	#define LOG_GROUP LOG_GROUP_REM_HANDLER
3338
3339	/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3340
3341	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3342	{
3343	Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys));
3344	uint8_t u8;
3345	PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3346	return u8;
3347	}
3348
3349	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3350	{
3351	Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys));
3352	uint16_t u16;
3353	PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3354	return u16;
3355	}
3356
3357	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3358	{
3359	Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys));
3360	uint32_t u32;
3361	PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3362	return u32;
3363	}
3364
3365	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3366	{
3367	Log2(("remR3HandlerWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3368	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3369	}
3370
3371	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3372	{
3373	Log2(("remR3HandlerWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3374	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3375	}
3376
3377	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3378	{
3379	Log2(("remR3HandlerWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3380	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3381	}
3382
3383	/* -+- disassembly -+- */
3384
3385	#undef LOG_GROUP
3386	#define LOG_GROUP LOG_GROUP_REM_DISAS
3387
3388
3389	/**
3390	* Enables or disables singled stepped disassembly.
3391	*
3392	* @returns VBox status code.
3393	* @param pVM VM handle.
3394	* @param fEnable To enable set this flag, to disable clear it.
3395	*/
3396	static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3397	{
3398	LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3399	VM_ASSERT_EMT(pVM);
3400
3401	if (fEnable)
3402	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
3403	else
3404	pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3405	return VINF_SUCCESS;
3406	}
3407
3408
3409	/**
3410	* Enables or disables singled stepped disassembly.
3411	*
3412	* @returns VBox status code.
3413	* @param pVM VM handle.
3414	* @param fEnable To enable set this flag, to disable clear it.
3415	*/
3416	REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3417	{
3418	PVMREQ pReq;
3419	int rc;
3420
3421	LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3422	if (VM_IS_EMT(pVM))
3423	return remR3DisasEnableStepping(pVM, fEnable);
3424
3425	rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3426	AssertRC(rc);
3427	if (VBOX_SUCCESS(rc))
3428	rc = pReq->iStatus;
3429	VMR3ReqFree(pReq);
3430	return rc;
3431	}
3432
3433
3434	#ifdef VBOX_WITH_DEBUGGER
3435	/**
3436	* External Debugger Command: .remstep [on\|off\|1\|0]
3437	*/
3438	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3439	{
3440	bool fEnable;
3441	int rc;
3442
3443	/* print status */
3444	if (cArgs == 0)
3445	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3446	pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3447
3448	/* convert the argument and change the mode. */
3449	rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3450	if (VBOX_FAILURE(rc))
3451	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3452	rc = REMR3DisasEnableStepping(pVM, fEnable);
3453	if (VBOX_FAILURE(rc))
3454	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3455	return rc;
3456	}
3457	#endif
3458
3459
3460	/**
3461	* Disassembles n instructions and prints them to the log.
3462	*
3463	* @returns Success indicator.
3464	* @param env Pointer to the recompiler CPU structure.
3465	* @param f32BitCode Indicates that whether or not the code should
3466	* be disassembled as 16 or 32 bit. If -1 the CS
3467	* selector will be inspected.
3468	* @param nrInstructions Nr of instructions to disassemble
3469	* @param pszPrefix
3470	* @remark not currently used for anything but ad-hoc debugging.
3471	*/
3472	bool remR3DisasBlock(CPUState env, int f32BitCode, int nrInstructions, char pszPrefix)
3473	{
3474	int i;
3475
3476	/*
3477	* Determin 16/32 bit mode.
3478	*/
3479	if (f32BitCode == -1)
3480	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3481
3482	/*
3483	* Convert cs:eip to host context address.
3484	* We don't care to much about cross page correctness presently.
3485	*/
3486	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3487	void *pvPC;
3488	if (f32BitCode && (env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3489	{
3490	/* convert eip to physical address. */
3491	int rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,
3492	GCPtrPC,
3493	env->cr[3],
3494	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE), /** @todo add longmode flag */
3495	&pvPC);
3496	if (VBOX_FAILURE(rc))
3497	{
3498	if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3499	return false;
3500	pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3501	+ (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3502	}
3503	}
3504	else
3505	{
3506	/* physical address */
3507	int rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions*16, &pvPC);
3508	if (VBOX_FAILURE(rc))
3509	return false;
3510	}
3511
3512	/*
3513	* Disassemble.
3514	*/
3515	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3516	DISCPUSTATE Cpu;
3517	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3518	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3519	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3520	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3521	//Cpu.dwUserData[2] = GCPtrPC;
3522
3523	for (i=0;i<nrInstructions;i++)
3524	{
3525	char szOutput[256];
3526	uint32_t cbOp;
3527	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3528	return false;
3529	if (pszPrefix)
3530	Log(("%s: %s", pszPrefix, szOutput));
3531	else
3532	Log(("%s", szOutput));
3533
3534	pvPC += cbOp;
3535	}
3536	return true;
3537	}
3538
3539
3540	/** @todo need to test the new code, using the old code in the mean while. */
3541	#define USE_OLD_DUMP_AND_DISASSEMBLY
3542
3543	/**
3544	* Disassembles one instruction and prints it to the log.
3545	*
3546	* @returns Success indicator.
3547	* @param env Pointer to the recompiler CPU structure.
3548	* @param f32BitCode Indicates that whether or not the code should
3549	* be disassembled as 16 or 32 bit. If -1 the CS
3550	* selector will be inspected.
3551	* @param pszPrefix
3552	*/
3553	bool remR3DisasInstr(CPUState env, int f32BitCode, char pszPrefix)
3554	{
3555	#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3556	PVM pVM = env->pVM;
3557
3558	/*
3559	* Determin 16/32 bit mode.
3560	*/
3561	if (f32BitCode == -1)
3562	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3563
3564	/*
3565	* Log registers
3566	*/
3567	if (LogIs2Enabled())
3568	{
3569	remR3StateUpdate(pVM);
3570	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3571	}
3572
3573	/*
3574	* Convert cs:eip to host context address.
3575	* We don't care to much about cross page correctness presently.
3576	*/
3577	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3578	void *pvPC;
3579	if ((env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3580	{
3581	/* convert eip to physical address. */
3582	int rc = PGMPhysGCPtr2HCPtrByGstCR3(pVM,
3583	GCPtrPC,
3584	env->cr[3],
3585	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE),
3586	&pvPC);
3587	if (VBOX_FAILURE(rc))
3588	{
3589	if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3590	return false;
3591	pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3592	+ (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3593	}
3594	}
3595	else
3596	{
3597
3598	/* physical address */
3599	int rc = PGMPhysGCPhys2HCPtr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3600	if (VBOX_FAILURE(rc))
3601	return false;
3602	}
3603
3604	/*
3605	* Disassemble.
3606	*/
3607	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3608	DISCPUSTATE Cpu;
3609	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3610	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3611	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3612	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3613	//Cpu.dwUserData[2] = GCPtrPC;
3614	char szOutput[256];
3615	uint32_t cbOp;
3616	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3617	return false;
3618
3619	if (!f32BitCode)
3620	{
3621	if (pszPrefix)
3622	Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3623	else
3624	Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3625	}
3626	else
3627	{
3628	if (pszPrefix)
3629	Log(("%s: %s", pszPrefix, szOutput));
3630	else
3631	Log(("%s", szOutput));
3632	}
3633	return true;
3634
3635	#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3636	PVM pVM = env->pVM;
3637	const bool fLog = LogIsEnabled();
3638	const bool fLog2 = LogIs2Enabled();
3639	int rc = VINF_SUCCESS;
3640
3641	/*
3642	* Don't bother if there ain't any log output to do.
3643	*/
3644	if (!fLog && !fLog2)
3645	return true;
3646
3647	/*
3648	* Update the state so DBGF reads the correct register values.
3649	*/
3650	remR3StateUpdate(pVM);
3651
3652	/*
3653	* Log registers if requested.
3654	*/
3655	if (!fLog2)
3656	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3657
3658	/*
3659	* Disassemble to log.
3660	*/
3661	if (fLog)
3662	rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3663
3664	return VBOX_SUCCESS(rc);
3665	#endif
3666	}
3667
3668
3669	/**
3670	* Disassemble recompiled code.
3671	*
3672	* @param phFileIgnored Ignored, logfile usually.
3673	* @param pvCode Pointer to the code block.
3674	* @param cb Size of the code block.
3675	*/
3676	void disas(FILE phFileIgnored, void pvCode, unsigned long cb)
3677	{
3678	if (LogIs2Enabled())
3679	{
3680	unsigned off = 0;
3681	char szOutput[256];
3682	DISCPUSTATE Cpu = {0};
3683	Cpu.mode = CPUMODE_32BIT;
3684
3685	RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3686	while (off < cb)
3687	{
3688	uint32_t cbInstr;
3689	if (DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput))
3690	RTLogPrintf("%s", szOutput);
3691	else
3692	{
3693	RTLogPrintf("disas error\n");
3694	cbInstr = 1;
3695	}
3696	off += cbInstr;
3697	}
3698	}
3699	NOREF(phFileIgnored);
3700	}
3701
3702
3703	/**
3704	* Disassemble guest code.
3705	*
3706	* @param phFileIgnored Ignored, logfile usually.
3707	* @param uCode The guest address of the code to disassemble. (flat?)
3708	* @param cb Number of bytes to disassemble.
3709	* @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3710	*/
3711	void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3712	{
3713	if (LogIs2Enabled())
3714	{
3715	PVM pVM = cpu_single_env->pVM;
3716
3717	/*
3718	* Update the state so DBGF reads the correct register values (flags).
3719	*/
3720	remR3StateUpdate(pVM);
3721
3722	/*
3723	* Do the disassembling.
3724	*/
3725	RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3726	RTSEL cs = cpu_single_env->segs[R_CS].selector;
3727	RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3728	for (;;)
3729	{
3730	char szBuf[256];
3731	size_t cbInstr;
3732	int rc = DBGFR3DisasInstrEx(pVM,
3733	cs,
3734	eip,
3735	0,
3736	szBuf, sizeof(szBuf),
3737	&cbInstr);
3738	if (VBOX_SUCCESS(rc))
3739	RTLogPrintf("%VGp %s\n", uCode, szBuf);
3740	else
3741	{
3742	RTLogPrintf("%VGp %04x:%VGp: %s\n", uCode, cs, eip, szBuf);
3743	cbInstr = 1;
3744	}
3745
3746	/* next */
3747	if (cb <= cbInstr)
3748	break;
3749	cb -= cbInstr;
3750	uCode += cbInstr;
3751	eip += cbInstr;
3752	}
3753	}
3754	NOREF(phFileIgnored);
3755	}
3756
3757
3758	/**
3759	* Looks up a guest symbol.
3760	*
3761	* @returns Pointer to symbol name. This is a static buffer.
3762	* @param orig_addr The address in question.
3763	*/
3764	const char *lookup_symbol(target_ulong orig_addr)
3765	{
3766	RTGCINTPTR off = 0;
3767	DBGFSYMBOL Sym;
3768	PVM pVM = cpu_single_env->pVM;
3769	int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3770	if (VBOX_SUCCESS(rc))
3771	{
3772	static char szSym[sizeof(Sym.szName) + 48];
3773	if (!off)
3774	RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3775	else if (off > 0)
3776	RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3777	else
3778	RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3779	return szSym;
3780	}
3781	return "<N/A>";
3782	}
3783
3784
3785	#undef LOG_GROUP
3786	#define LOG_GROUP LOG_GROUP_REM
3787
3788
3789	/* -+- FF notifications -+- */
3790
3791
3792	/**
3793	* Notification about a pending interrupt.
3794	*
3795	* @param pVM VM Handle.
3796	* @param u8Interrupt Interrupt
3797	* @thread The emulation thread.
3798	*/
3799	REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3800	{
3801	Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3802	pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3803	}
3804
3805	/**
3806	* Notification about a pending interrupt.
3807	*
3808	* @returns Pending interrupt or REM_NO_PENDING_IRQ
3809	* @param pVM VM Handle.
3810	* @thread The emulation thread.
3811	*/
3812	REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3813	{
3814	return pVM->rem.s.u32PendingInterrupt;
3815	}
3816
3817	/**
3818	* Notification about the interrupt FF being set.
3819	*
3820	* @param pVM VM Handle.
3821	* @thread The emulation thread.
3822	*/
3823	REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3824	{
3825	LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3826	(pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3827	if (pVM->rem.s.fInREM)
3828	{
3829	if (VM_IS_EMT(pVM))
3830	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3831	else
3832	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3833	}
3834	}
3835
3836
3837	/**
3838	* Notification about the interrupt FF being set.
3839	*
3840	* @param pVM VM Handle.
3841	* @thread The emulation thread.
3842	*/
3843	REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3844	{
3845	LogFlow(("REMR3NotifyInterruptClear:\n"));
3846	VM_ASSERT_EMT(pVM);
3847	if (pVM->rem.s.fInREM)
3848	cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3849	}
3850
3851
3852	/**
3853	* Notification about pending timer(s).
3854	*
3855	* @param pVM VM Handle.
3856	* @thread Any.
3857	*/
3858	REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3859	{
3860	#ifndef DEBUG_bird
3861	LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3862	#endif
3863	if (pVM->rem.s.fInREM)
3864	{
3865	if (VM_IS_EMT(pVM))
3866	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3867	else
3868	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3869	}
3870	}
3871
3872
3873	/**
3874	* Notification about pending DMA transfers.
3875	*
3876	* @param pVM VM Handle.
3877	* @thread Any.
3878	*/
3879	REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3880	{
3881	LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3882	if (pVM->rem.s.fInREM)
3883	{
3884	if (VM_IS_EMT(pVM))
3885	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3886	else
3887	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3888	}
3889	}
3890
3891
3892	/**
3893	* Notification about pending timer(s).
3894	*
3895	* @param pVM VM Handle.
3896	* @thread Any.
3897	*/
3898	REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3899	{
3900	LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3901	if (pVM->rem.s.fInREM)
3902	{
3903	if (VM_IS_EMT(pVM))
3904	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3905	else
3906	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3907	}
3908	}
3909
3910
3911	/**
3912	* Notification about pending FF set by an external thread.
3913	*
3914	* @param pVM VM handle.
3915	* @thread Any.
3916	*/
3917	REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3918	{
3919	LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3920	if (pVM->rem.s.fInREM)
3921	{
3922	if (VM_IS_EMT(pVM))
3923	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3924	else
3925	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3926	}
3927	}
3928
3929
3930	#ifdef VBOX_WITH_STATISTICS
3931	void remR3ProfileStart(int statcode)
3932	{
3933	STAMPROFILEADV *pStat;
3934	switch(statcode)
3935	{
3936	case STATS_EMULATE_SINGLE_INSTR:
3937	pStat = &gStatExecuteSingleInstr;
3938	break;
3939	case STATS_QEMU_COMPILATION:
3940	pStat = &gStatCompilationQEmu;
3941	break;
3942	case STATS_QEMU_RUN_EMULATED_CODE:
3943	pStat = &gStatRunCodeQEmu;
3944	break;
3945	case STATS_QEMU_TOTAL:
3946	pStat = &gStatTotalTimeQEmu;
3947	break;
3948	case STATS_QEMU_RUN_TIMERS:
3949	pStat = &gStatTimers;
3950	break;
3951	case STATS_TLB_LOOKUP:
3952	pStat= &gStatTBLookup;
3953	break;
3954	case STATS_IRQ_HANDLING:
3955	pStat= &gStatIRQ;
3956	break;
3957	case STATS_RAW_CHECK:
3958	pStat = &gStatRawCheck;
3959	break;
3960
3961	default:
3962	AssertMsgFailed(("unknown stat %d\n", statcode));
3963	return;
3964	}
3965	STAM_PROFILE_ADV_START(pStat, a);
3966	}
3967
3968
3969	void remR3ProfileStop(int statcode)
3970	{
3971	STAMPROFILEADV *pStat;
3972	switch(statcode)
3973	{
3974	case STATS_EMULATE_SINGLE_INSTR:
3975	pStat = &gStatExecuteSingleInstr;
3976	break;
3977	case STATS_QEMU_COMPILATION:
3978	pStat = &gStatCompilationQEmu;
3979	break;
3980	case STATS_QEMU_RUN_EMULATED_CODE:
3981	pStat = &gStatRunCodeQEmu;
3982	break;
3983	case STATS_QEMU_TOTAL:
3984	pStat = &gStatTotalTimeQEmu;
3985	break;
3986	case STATS_QEMU_RUN_TIMERS:
3987	pStat = &gStatTimers;
3988	break;
3989	case STATS_TLB_LOOKUP:
3990	pStat= &gStatTBLookup;
3991	break;
3992	case STATS_IRQ_HANDLING:
3993	pStat= &gStatIRQ;
3994	break;
3995	case STATS_RAW_CHECK:
3996	pStat = &gStatRawCheck;
3997	break;
3998	default:
3999	AssertMsgFailed(("unknown stat %d\n", statcode));
4000	return;
4001	}
4002	STAM_PROFILE_ADV_STOP(pStat, a);
4003	}
4004	#endif
4005
4006	/**
4007	* Raise an RC, force rem exit.
4008	*
4009	* @param pVM VM handle.
4010	* @param rc The rc.
4011	*/
4012	void remR3RaiseRC(PVM pVM, int rc)
4013	{
4014	Log(("remR3RaiseRC: rc=%Vrc\n", rc));
4015	Assert(pVM->rem.s.fInREM);
4016	VM_ASSERT_EMT(pVM);
4017	pVM->rem.s.rc = rc;
4018	cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
4019	}
4020
4021
4022	/* -+- timers -+- */
4023
4024	uint64_t cpu_get_tsc(CPUX86State *env)
4025	{
4026	return TMCpuTickGet(env->pVM);
4027	}
4028
4029
4030	/* -+- interrupts -+- */
4031
4032	void cpu_set_ferr(CPUX86State *env)
4033	{
4034	int rc = PDMIsaSetIrq(env->pVM, 13, 1);
4035	LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
4036	}
4037
4038	int cpu_get_pic_interrupt(CPUState *env)
4039	{
4040	uint8_t u8Interrupt;
4041	int rc;
4042
4043	/* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
4044	* In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
4045	* with the (a)pic.
4046	*/
4047	/** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
4048	/** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
4049	* if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4050	* remove this kludge. */
4051	if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4052	{
4053	rc = VINF_SUCCESS;
4054	Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
4055	u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4056	env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4057	}
4058	else
4059	rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
4060
4061	LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Vrc\n", u8Interrupt, rc));
4062	if (VBOX_SUCCESS(rc))
4063	{
4064	if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
4065	env->interrupt_request \|= CPU_INTERRUPT_HARD;
4066	return u8Interrupt;
4067	}
4068	return -1;
4069	}
4070
4071
4072	/* -+- local apic -+- */
4073
4074	void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4075	{
4076	int rc = PDMApicSetBase(env->pVM, val);
4077	LogFlow(("cpu_set_apic_base: val=%#llx rc=%Vrc\n", val, rc)); NOREF(rc);
4078	}
4079
4080	uint64_t cpu_get_apic_base(CPUX86State *env)
4081	{
4082	uint64_t u64;
4083	int rc = PDMApicGetBase(env->pVM, &u64);
4084	if (VBOX_SUCCESS(rc))
4085	{
4086	LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4087	return u64;
4088	}
4089	LogFlow(("cpu_get_apic_base: returns 0 (rc=%Vrc)\n", rc));
4090	return 0;
4091	}
4092
4093	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4094	{
4095	int rc = PDMApicSetTPR(env->pVM, val);
4096	LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Vrc\n", val, rc)); NOREF(rc);
4097	}
4098
4099	uint8_t cpu_get_apic_tpr(CPUX86State *env)
4100	{
4101	uint8_t u8;
4102	int rc = PDMApicGetTPR(env->pVM, &u8);
4103	if (VBOX_SUCCESS(rc))
4104	{
4105	LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4106	return u8;
4107	}
4108	LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Vrc)\n", rc));
4109	return 0;
4110	}
4111
4112
4113	/* -+- I/O Ports -+- */
4114
4115	#undef LOG_GROUP
4116	#define LOG_GROUP LOG_GROUP_REM_IOPORT
4117
4118	void cpu_outb(CPUState *env, int addr, int val)
4119	{
4120	if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4121	Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4122
4123	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4124	if (rc == VINF_SUCCESS)
4125	return;
4126	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4127	{
4128	Log(("cpu_outb: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4129	remR3RaiseRC(env->pVM, rc);
4130	return;
4131	}
4132	remAbort(rc, __FUNCTION__);
4133	}
4134
4135	void cpu_outw(CPUState *env, int addr, int val)
4136	{
4137	//Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4138	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4139	if (rc == VINF_SUCCESS)
4140	return;
4141	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4142	{
4143	Log(("cpu_outw: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4144	remR3RaiseRC(env->pVM, rc);
4145	return;
4146	}
4147	remAbort(rc, __FUNCTION__);
4148	}
4149
4150	void cpu_outl(CPUState *env, int addr, int val)
4151	{
4152	Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4153	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4154	if (rc == VINF_SUCCESS)
4155	return;
4156	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4157	{
4158	Log(("cpu_outl: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4159	remR3RaiseRC(env->pVM, rc);
4160	return;
4161	}
4162	remAbort(rc, __FUNCTION__);
4163	}
4164
4165	int cpu_inb(CPUState *env, int addr)
4166	{
4167	uint32_t u32 = 0;
4168	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4169	if (rc == VINF_SUCCESS)
4170	{
4171	if (/addr != 0x61 && /addr != 0x71)
4172	Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4173	return (int)u32;
4174	}
4175	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4176	{
4177	Log(("cpu_inb: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4178	remR3RaiseRC(env->pVM, rc);
4179	return (int)u32;
4180	}
4181	remAbort(rc, __FUNCTION__);
4182	return 0xff;
4183	}
4184
4185	int cpu_inw(CPUState *env, int addr)
4186	{
4187	uint32_t u32 = 0;
4188	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4189	if (rc == VINF_SUCCESS)
4190	{
4191	Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4192	return (int)u32;
4193	}
4194	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4195	{
4196	Log(("cpu_inw: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4197	remR3RaiseRC(env->pVM, rc);
4198	return (int)u32;
4199	}
4200	remAbort(rc, __FUNCTION__);
4201	return 0xffff;
4202	}
4203
4204	int cpu_inl(CPUState *env, int addr)
4205	{
4206	uint32_t u32 = 0;
4207	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4208	if (rc == VINF_SUCCESS)
4209	{
4210	//if (addr==0x01f0 && u32 == 0x6b6d)
4211	// loglevel = ~0;
4212	Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4213	return (int)u32;
4214	}
4215	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4216	{
4217	Log(("cpu_inl: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4218	remR3RaiseRC(env->pVM, rc);
4219	return (int)u32;
4220	}
4221	remAbort(rc, __FUNCTION__);
4222	return 0xffffffff;
4223	}
4224
4225	#undef LOG_GROUP
4226	#define LOG_GROUP LOG_GROUP_REM
4227
4228
4229	/* -+- helpers and misc other interfaces -+- */
4230
4231	/**
4232	* Perform the CPUID instruction.
4233	*
4234	* ASMCpuId cannot be invoked from some source files where this is used because of global
4235	* register allocations.
4236	*
4237	* @param env Pointer to the recompiler CPU structure.
4238	* @param uOperator CPUID operation (eax).
4239	* @param pvEAX Where to store eax.
4240	* @param pvEBX Where to store ebx.
4241	* @param pvECX Where to store ecx.
4242	* @param pvEDX Where to store edx.
4243	*/
4244	void remR3CpuId(CPUState env, unsigned uOperator, void pvEAX, void pvEBX, void pvECX, void *pvEDX)
4245	{
4246	CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t )pvEAX, (uint32_t )pvEBX, (uint32_t )pvECX, (uint32_t )pvEDX);
4247	}
4248
4249
4250	#if 0 /* not used */
4251	/**
4252	* Interface for qemu hardware to report back fatal errors.
4253	*/
4254	void hw_error(const char *pszFormat, ...)
4255	{
4256	/*
4257	* Bitch about it.
4258	*/
4259	/** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4260	* this in my Odin32 tree at home! */
4261	va_list args;
4262	va_start(args, pszFormat);
4263	RTLogPrintf("fatal error in virtual hardware:");
4264	RTLogPrintfV(pszFormat, args);
4265	va_end(args);
4266	AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4267
4268	/*
4269	* If we're in REM context we'll sync back the state before 'jumping' to
4270	* the EMs failure handling.
4271	*/
4272	PVM pVM = cpu_single_env->pVM;
4273	if (pVM->rem.s.fInREM)
4274	REMR3StateBack(pVM);
4275	EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4276	AssertMsgFailed(("EMR3FatalError returned!\n"));
4277	}
4278	#endif
4279
4280	/**
4281	* Interface for the qemu cpu to report unhandled situation
4282	* raising a fatal VM error.
4283	*/
4284	void cpu_abort(CPUState env, const char pszFormat, ...)
4285	{
4286	/*
4287	* Bitch about it.
4288	*/
4289	RTLogFlags(NULL, "nodisabled nobuffered");
4290	va_list args;
4291	va_start(args, pszFormat);
4292	RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4293	va_end(args);
4294	va_start(args, pszFormat);
4295	AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4296	va_end(args);
4297
4298	/*
4299	* If we're in REM context we'll sync back the state before 'jumping' to
4300	* the EMs failure handling.
4301	*/
4302	PVM pVM = cpu_single_env->pVM;
4303	if (pVM->rem.s.fInREM)
4304	REMR3StateBack(pVM);
4305	EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4306	AssertMsgFailed(("EMR3FatalError returned!\n"));
4307	}
4308
4309
4310	/**
4311	* Aborts the VM.
4312	*
4313	* @param rc VBox error code.
4314	* @param pszTip Hint about why/when this happend.
4315	*/
4316	static void remAbort(int rc, const char *pszTip)
4317	{
4318	/*
4319	* Bitch about it.
4320	*/
4321	RTLogPrintf("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip);
4322	AssertReleaseMsgFailed(("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip));
4323
4324	/*
4325	* Jump back to where we entered the recompiler.
4326	*/
4327	PVM pVM = cpu_single_env->pVM;
4328	if (pVM->rem.s.fInREM)
4329	REMR3StateBack(pVM);
4330	EMR3FatalError(pVM, rc);
4331	AssertMsgFailed(("EMR3FatalError returned!\n"));
4332	}
4333
4334
4335	/**
4336	* Dumps a linux system call.
4337	* @param pVM VM handle.
4338	*/
4339	void remR3DumpLnxSyscall(PVM pVM)
4340	{
4341	static const char *apsz[] =
4342	{
4343	"sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4344	"sys_exit",
4345	"sys_fork",
4346	"sys_read",
4347	"sys_write",
4348	"sys_open", /* 5 */
4349	"sys_close",
4350	"sys_waitpid",
4351	"sys_creat",
4352	"sys_link",
4353	"sys_unlink", /* 10 */
4354	"sys_execve",
4355	"sys_chdir",
4356	"sys_time",
4357	"sys_mknod",
4358	"sys_chmod", /* 15 */
4359	"sys_lchown16",
4360	"sys_ni_syscall", /* old break syscall holder */
4361	"sys_stat",
4362	"sys_lseek",
4363	"sys_getpid", /* 20 */
4364	"sys_mount",
4365	"sys_oldumount",
4366	"sys_setuid16",
4367	"sys_getuid16",
4368	"sys_stime", /* 25 */
4369	"sys_ptrace",
4370	"sys_alarm",
4371	"sys_fstat",
4372	"sys_pause",
4373	"sys_utime", /* 30 */
4374	"sys_ni_syscall", /* old stty syscall holder */
4375	"sys_ni_syscall", /* old gtty syscall holder */
4376	"sys_access",
4377	"sys_nice",
4378	"sys_ni_syscall", /* 35 - old ftime syscall holder */
4379	"sys_sync",
4380	"sys_kill",
4381	"sys_rename",
4382	"sys_mkdir",
4383	"sys_rmdir", /* 40 */
4384	"sys_dup",
4385	"sys_pipe",
4386	"sys_times",
4387	"sys_ni_syscall", /* old prof syscall holder */
4388	"sys_brk", /* 45 */
4389	"sys_setgid16",
4390	"sys_getgid16",
4391	"sys_signal",
4392	"sys_geteuid16",
4393	"sys_getegid16", /* 50 */
4394	"sys_acct",
4395	"sys_umount", /* recycled never used phys() */
4396	"sys_ni_syscall", /* old lock syscall holder */
4397	"sys_ioctl",
4398	"sys_fcntl", /* 55 */
4399	"sys_ni_syscall", /* old mpx syscall holder */
4400	"sys_setpgid",
4401	"sys_ni_syscall", /* old ulimit syscall holder */
4402	"sys_olduname",
4403	"sys_umask", /* 60 */
4404	"sys_chroot",
4405	"sys_ustat",
4406	"sys_dup2",
4407	"sys_getppid",
4408	"sys_getpgrp", /* 65 */
4409	"sys_setsid",
4410	"sys_sigaction",
4411	"sys_sgetmask",
4412	"sys_ssetmask",
4413	"sys_setreuid16", /* 70 */
4414	"sys_setregid16",
4415	"sys_sigsuspend",
4416	"sys_sigpending",
4417	"sys_sethostname",
4418	"sys_setrlimit", /* 75 */
4419	"sys_old_getrlimit",
4420	"sys_getrusage",
4421	"sys_gettimeofday",
4422	"sys_settimeofday",
4423	"sys_getgroups16", /* 80 */
4424	"sys_setgroups16",
4425	"old_select",
4426	"sys_symlink",
4427	"sys_lstat",
4428	"sys_readlink", /* 85 */
4429	"sys_uselib",
4430	"sys_swapon",
4431	"sys_reboot",
4432	"old_readdir",
4433	"old_mmap", /* 90 */
4434	"sys_munmap",
4435	"sys_truncate",
4436	"sys_ftruncate",
4437	"sys_fchmod",
4438	"sys_fchown16", /* 95 */
4439	"sys_getpriority",
4440	"sys_setpriority",
4441	"sys_ni_syscall", /* old profil syscall holder */
4442	"sys_statfs",
4443	"sys_fstatfs", /* 100 */
4444	"sys_ioperm",
4445	"sys_socketcall",
4446	"sys_syslog",
4447	"sys_setitimer",
4448	"sys_getitimer", /* 105 */
4449	"sys_newstat",
4450	"sys_newlstat",
4451	"sys_newfstat",
4452	"sys_uname",
4453	"sys_iopl", /* 110 */
4454	"sys_vhangup",
4455	"sys_ni_syscall", /* old "idle" system call */
4456	"sys_vm86old",
4457	"sys_wait4",
4458	"sys_swapoff", /* 115 */
4459	"sys_sysinfo",
4460	"sys_ipc",
4461	"sys_fsync",
4462	"sys_sigreturn",
4463	"sys_clone", /* 120 */
4464	"sys_setdomainname",
4465	"sys_newuname",
4466	"sys_modify_ldt",
4467	"sys_adjtimex",
4468	"sys_mprotect", /* 125 */
4469	"sys_sigprocmask",
4470	"sys_ni_syscall", /* old "create_module" */
4471	"sys_init_module",
4472	"sys_delete_module",
4473	"sys_ni_syscall", /* 130: old "get_kernel_syms" */
4474	"sys_quotactl",
4475	"sys_getpgid",
4476	"sys_fchdir",
4477	"sys_bdflush",
4478	"sys_sysfs", /* 135 */
4479	"sys_personality",
4480	"sys_ni_syscall", /* reserved for afs_syscall */
4481	"sys_setfsuid16",
4482	"sys_setfsgid16",
4483	"sys_llseek", /* 140 */
4484	"sys_getdents",
4485	"sys_select",
4486	"sys_flock",
4487	"sys_msync",
4488	"sys_readv", /* 145 */
4489	"sys_writev",
4490	"sys_getsid",
4491	"sys_fdatasync",
4492	"sys_sysctl",
4493	"sys_mlock", /* 150 */
4494	"sys_munlock",
4495	"sys_mlockall",
4496	"sys_munlockall",
4497	"sys_sched_setparam",
4498	"sys_sched_getparam", /* 155 */
4499	"sys_sched_setscheduler",
4500	"sys_sched_getscheduler",
4501	"sys_sched_yield",
4502	"sys_sched_get_priority_max",
4503	"sys_sched_get_priority_min", /* 160 */
4504	"sys_sched_rr_get_interval",
4505	"sys_nanosleep",
4506	"sys_mremap",
4507	"sys_setresuid16",
4508	"sys_getresuid16", /* 165 */
4509	"sys_vm86",
4510	"sys_ni_syscall", /* Old sys_query_module */
4511	"sys_poll",
4512	"sys_nfsservctl",
4513	"sys_setresgid16", /* 170 */
4514	"sys_getresgid16",
4515	"sys_prctl",
4516	"sys_rt_sigreturn",
4517	"sys_rt_sigaction",
4518	"sys_rt_sigprocmask", /* 175 */
4519	"sys_rt_sigpending",
4520	"sys_rt_sigtimedwait",
4521	"sys_rt_sigqueueinfo",
4522	"sys_rt_sigsuspend",
4523	"sys_pread64", /* 180 */
4524	"sys_pwrite64",
4525	"sys_chown16",
4526	"sys_getcwd",
4527	"sys_capget",
4528	"sys_capset", /* 185 */
4529	"sys_sigaltstack",
4530	"sys_sendfile",
4531	"sys_ni_syscall", /* reserved for streams1 */
4532	"sys_ni_syscall", /* reserved for streams2 */
4533	"sys_vfork", /* 190 */
4534	"sys_getrlimit",
4535	"sys_mmap2",
4536	"sys_truncate64",
4537	"sys_ftruncate64",
4538	"sys_stat64", /* 195 */
4539	"sys_lstat64",
4540	"sys_fstat64",
4541	"sys_lchown",
4542	"sys_getuid",
4543	"sys_getgid", /* 200 */
4544	"sys_geteuid",
4545	"sys_getegid",
4546	"sys_setreuid",
4547	"sys_setregid",
4548	"sys_getgroups", /* 205 */
4549	"sys_setgroups",
4550	"sys_fchown",
4551	"sys_setresuid",
4552	"sys_getresuid",
4553	"sys_setresgid", /* 210 */
4554	"sys_getresgid",
4555	"sys_chown",
4556	"sys_setuid",
4557	"sys_setgid",
4558	"sys_setfsuid", /* 215 */
4559	"sys_setfsgid",
4560	"sys_pivot_root",
4561	"sys_mincore",
4562	"sys_madvise",
4563	"sys_getdents64", /* 220 */
4564	"sys_fcntl64",
4565	"sys_ni_syscall", /* reserved for TUX */
4566	"sys_ni_syscall",
4567	"sys_gettid",
4568	"sys_readahead", /* 225 */
4569	"sys_setxattr",
4570	"sys_lsetxattr",
4571	"sys_fsetxattr",
4572	"sys_getxattr",
4573	"sys_lgetxattr", /* 230 */
4574	"sys_fgetxattr",
4575	"sys_listxattr",
4576	"sys_llistxattr",
4577	"sys_flistxattr",
4578	"sys_removexattr", /* 235 */
4579	"sys_lremovexattr",
4580	"sys_fremovexattr",
4581	"sys_tkill",
4582	"sys_sendfile64",
4583	"sys_futex", /* 240 */
4584	"sys_sched_setaffinity",
4585	"sys_sched_getaffinity",
4586	"sys_set_thread_area",
4587	"sys_get_thread_area",
4588	"sys_io_setup", /* 245 */
4589	"sys_io_destroy",
4590	"sys_io_getevents",
4591	"sys_io_submit",
4592	"sys_io_cancel",
4593	"sys_fadvise64", /* 250 */
4594	"sys_ni_syscall",
4595	"sys_exit_group",
4596	"sys_lookup_dcookie",
4597	"sys_epoll_create",
4598	"sys_epoll_ctl", /* 255 */
4599	"sys_epoll_wait",
4600	"sys_remap_file_pages",
4601	"sys_set_tid_address",
4602	"sys_timer_create",
4603	"sys_timer_settime", /* 260 */
4604	"sys_timer_gettime",
4605	"sys_timer_getoverrun",
4606	"sys_timer_delete",
4607	"sys_clock_settime",
4608	"sys_clock_gettime", /* 265 */
4609	"sys_clock_getres",
4610	"sys_clock_nanosleep",
4611	"sys_statfs64",
4612	"sys_fstatfs64",
4613	"sys_tgkill", /* 270 */
4614	"sys_utimes",
4615	"sys_fadvise64_64",
4616	"sys_ni_syscall" /* sys_vserver */
4617	};
4618
4619	uint32_t uEAX = CPUMGetGuestEAX(pVM);
4620	switch (uEAX)
4621	{
4622	default:
4623	if (uEAX < ELEMENTS(apsz))
4624	Log(("REM: linux syscall %3d: %s (eip=%VGv ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4625	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4626	CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4627	else
4628	Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4629	break;
4630
4631	}
4632	}
4633
4634
4635	/**
4636	* Dumps an OpenBSD system call.
4637	* @param pVM VM handle.
4638	*/
4639	void remR3DumpOBsdSyscall(PVM pVM)
4640	{
4641	static const char *apsz[] =
4642	{
4643	"SYS_syscall", //0
4644	"SYS_exit", //1
4645	"SYS_fork", //2
4646	"SYS_read", //3
4647	"SYS_write", //4
4648	"SYS_open", //5
4649	"SYS_close", //6
4650	"SYS_wait4", //7
4651	"SYS_8",
4652	"SYS_link", //9
4653	"SYS_unlink", //10
4654	"SYS_11",
4655	"SYS_chdir", //12
4656	"SYS_fchdir", //13
4657	"SYS_mknod", //14
4658	"SYS_chmod", //15
4659	"SYS_chown", //16
4660	"SYS_break", //17
4661	"SYS_18",
4662	"SYS_19",
4663	"SYS_getpid", //20
4664	"SYS_mount", //21
4665	"SYS_unmount", //22
4666	"SYS_setuid", //23
4667	"SYS_getuid", //24
4668	"SYS_geteuid", //25
4669	"SYS_ptrace", //26
4670	"SYS_recvmsg", //27
4671	"SYS_sendmsg", //28
4672	"SYS_recvfrom", //29
4673	"SYS_accept", //30
4674	"SYS_getpeername", //31
4675	"SYS_getsockname", //32
4676	"SYS_access", //33
4677	"SYS_chflags", //34
4678	"SYS_fchflags", //35
4679	"SYS_sync", //36
4680	"SYS_kill", //37
4681	"SYS_38",
4682	"SYS_getppid", //39
4683	"SYS_40",
4684	"SYS_dup", //41
4685	"SYS_opipe", //42
4686	"SYS_getegid", //43
4687	"SYS_profil", //44
4688	"SYS_ktrace", //45
4689	"SYS_sigaction", //46
4690	"SYS_getgid", //47
4691	"SYS_sigprocmask", //48
4692	"SYS_getlogin", //49
4693	"SYS_setlogin", //50
4694	"SYS_acct", //51
4695	"SYS_sigpending", //52
4696	"SYS_osigaltstack", //53
4697	"SYS_ioctl", //54
4698	"SYS_reboot", //55
4699	"SYS_revoke", //56
4700	"SYS_symlink", //57
4701	"SYS_readlink", //58
4702	"SYS_execve", //59
4703	"SYS_umask", //60
4704	"SYS_chroot", //61
4705	"SYS_62",
4706	"SYS_63",
4707	"SYS_64",
4708	"SYS_65",
4709	"SYS_vfork", //66
4710	"SYS_67",
4711	"SYS_68",
4712	"SYS_sbrk", //69
4713	"SYS_sstk", //70
4714	"SYS_61",
4715	"SYS_vadvise", //72
4716	"SYS_munmap", //73
4717	"SYS_mprotect", //74
4718	"SYS_madvise", //75
4719	"SYS_76",
4720	"SYS_77",
4721	"SYS_mincore", //78
4722	"SYS_getgroups", //79
4723	"SYS_setgroups", //80
4724	"SYS_getpgrp", //81
4725	"SYS_setpgid", //82
4726	"SYS_setitimer", //83
4727	"SYS_84",
4728	"SYS_85",
4729	"SYS_getitimer", //86
4730	"SYS_87",
4731	"SYS_88",
4732	"SYS_89",
4733	"SYS_dup2", //90
4734	"SYS_91",
4735	"SYS_fcntl", //92
4736	"SYS_select", //93
4737	"SYS_94",
4738	"SYS_fsync", //95
4739	"SYS_setpriority", //96
4740	"SYS_socket", //97
4741	"SYS_connect", //98
4742	"SYS_99",
4743	"SYS_getpriority", //100
4744	"SYS_101",
4745	"SYS_102",
4746	"SYS_sigreturn", //103
4747	"SYS_bind", //104
4748	"SYS_setsockopt", //105
4749	"SYS_listen", //106
4750	"SYS_107",
4751	"SYS_108",
4752	"SYS_109",
4753	"SYS_110",
4754	"SYS_sigsuspend", //111
4755	"SYS_112",
4756	"SYS_113",
4757	"SYS_114",
4758	"SYS_115",
4759	"SYS_gettimeofday", //116
4760	"SYS_getrusage", //117
4761	"SYS_getsockopt", //118
4762	"SYS_119",
4763	"SYS_readv", //120
4764	"SYS_writev", //121
4765	"SYS_settimeofday", //122
4766	"SYS_fchown", //123
4767	"SYS_fchmod", //124
4768	"SYS_125",
4769	"SYS_setreuid", //126
4770	"SYS_setregid", //127
4771	"SYS_rename", //128
4772	"SYS_129",
4773	"SYS_130",
4774	"SYS_flock", //131
4775	"SYS_mkfifo", //132
4776	"SYS_sendto", //133
4777	"SYS_shutdown", //134
4778	"SYS_socketpair", //135
4779	"SYS_mkdir", //136
4780	"SYS_rmdir", //137
4781	"SYS_utimes", //138
4782	"SYS_139",
4783	"SYS_adjtime", //140
4784	"SYS_141",
4785	"SYS_142",
4786	"SYS_143",
4787	"SYS_144",
4788	"SYS_145",
4789	"SYS_146",
4790	"SYS_setsid", //147
4791	"SYS_quotactl", //148
4792	"SYS_149",
4793	"SYS_150",
4794	"SYS_151",
4795	"SYS_152",
4796	"SYS_153",
4797	"SYS_154",
4798	"SYS_nfssvc", //155
4799	"SYS_156",
4800	"SYS_157",
4801	"SYS_158",
4802	"SYS_159",
4803	"SYS_160",
4804	"SYS_getfh", //161
4805	"SYS_162",
4806	"SYS_163",
4807	"SYS_164",
4808	"SYS_sysarch", //165
4809	"SYS_166",
4810	"SYS_167",
4811	"SYS_168",
4812	"SYS_169",
4813	"SYS_170",
4814	"SYS_171",
4815	"SYS_172",
4816	"SYS_pread", //173
4817	"SYS_pwrite", //174
4818	"SYS_175",
4819	"SYS_176",
4820	"SYS_177",
4821	"SYS_178",
4822	"SYS_179",
4823	"SYS_180",
4824	"SYS_setgid", //181
4825	"SYS_setegid", //182
4826	"SYS_seteuid", //183
4827	"SYS_lfs_bmapv", //184
4828	"SYS_lfs_markv", //185
4829	"SYS_lfs_segclean", //186
4830	"SYS_lfs_segwait", //187
4831	"SYS_188",
4832	"SYS_189",
4833	"SYS_190",
4834	"SYS_pathconf", //191
4835	"SYS_fpathconf", //192
4836	"SYS_swapctl", //193
4837	"SYS_getrlimit", //194
4838	"SYS_setrlimit", //195
4839	"SYS_getdirentries", //196
4840	"SYS_mmap", //197
4841	"SYS___syscall", //198
4842	"SYS_lseek", //199
4843	"SYS_truncate", //200
4844	"SYS_ftruncate", //201
4845	"SYS___sysctl", //202
4846	"SYS_mlock", //203
4847	"SYS_munlock", //204
4848	"SYS_205",
4849	"SYS_futimes", //206
4850	"SYS_getpgid", //207
4851	"SYS_xfspioctl", //208
4852	"SYS_209",
4853	"SYS_210",
4854	"SYS_211",
4855	"SYS_212",
4856	"SYS_213",
4857	"SYS_214",
4858	"SYS_215",
4859	"SYS_216",
4860	"SYS_217",
4861	"SYS_218",
4862	"SYS_219",
4863	"SYS_220",
4864	"SYS_semget", //221
4865	"SYS_222",
4866	"SYS_223",
4867	"SYS_224",
4868	"SYS_msgget", //225
4869	"SYS_msgsnd", //226
4870	"SYS_msgrcv", //227
4871	"SYS_shmat", //228
4872	"SYS_229",
4873	"SYS_shmdt", //230
4874	"SYS_231",
4875	"SYS_clock_gettime", //232
4876	"SYS_clock_settime", //233
4877	"SYS_clock_getres", //234
4878	"SYS_235",
4879	"SYS_236",
4880	"SYS_237",
4881	"SYS_238",
4882	"SYS_239",
4883	"SYS_nanosleep", //240
4884	"SYS_241",
4885	"SYS_242",
4886	"SYS_243",
4887	"SYS_244",
4888	"SYS_245",
4889	"SYS_246",
4890	"SYS_247",
4891	"SYS_248",
4892	"SYS_249",
4893	"SYS_minherit", //250
4894	"SYS_rfork", //251
4895	"SYS_poll", //252
4896	"SYS_issetugid", //253
4897	"SYS_lchown", //254
4898	"SYS_getsid", //255
4899	"SYS_msync", //256
4900	"SYS_257",
4901	"SYS_258",
4902	"SYS_259",
4903	"SYS_getfsstat", //260
4904	"SYS_statfs", //261
4905	"SYS_fstatfs", //262
4906	"SYS_pipe", //263
4907	"SYS_fhopen", //264
4908	"SYS_265",
4909	"SYS_fhstatfs", //266
4910	"SYS_preadv", //267
4911	"SYS_pwritev", //268
4912	"SYS_kqueue", //269
4913	"SYS_kevent", //270
4914	"SYS_mlockall", //271
4915	"SYS_munlockall", //272
4916	"SYS_getpeereid", //273
4917	"SYS_274",
4918	"SYS_275",
4919	"SYS_276",
4920	"SYS_277",
4921	"SYS_278",
4922	"SYS_279",
4923	"SYS_280",
4924	"SYS_getresuid", //281
4925	"SYS_setresuid", //282
4926	"SYS_getresgid", //283
4927	"SYS_setresgid", //284
4928	"SYS_285",
4929	"SYS_mquery", //286
4930	"SYS_closefrom", //287
4931	"SYS_sigaltstack", //288
4932	"SYS_shmget", //289
4933	"SYS_semop", //290
4934	"SYS_stat", //291
4935	"SYS_fstat", //292
4936	"SYS_lstat", //293
4937	"SYS_fhstat", //294
4938	"SYS___semctl", //295
4939	"SYS_shmctl", //296
4940	"SYS_msgctl", //297
4941	"SYS_MAXSYSCALL", //298
4942	//299
4943	//300
4944	};
4945	uint32_t uEAX;
4946	#ifndef DEBUG_bird
4947	if (!LogIsEnabled())
4948	return;
4949	#endif
4950	uEAX = CPUMGetGuestEAX(pVM);
4951	switch (uEAX)
4952	{
4953	default:
4954	if (uEAX < ELEMENTS(apsz))
4955	{
4956	uint32_t au32Args[8] = {0};
4957	PGMPhysReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4958	RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4959	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4960	au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4961	}
4962	else
4963	RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4964	break;
4965	}
4966	}

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source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 993

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