VBoxRecompiler.c@ 2126

Last change on this file since 2126 was 2126, checked in by vboxsync, 18 years ago
TRPM changes to assert and report trap/interrupt types accurately.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 154.2 KB

Line
1	/** @file
2	*
3	* VBox Recompiler - QEMU.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include "vl.h"
27	#include "exec-all.h"
28
29	#include <VBox/rem.h>
30	#include <VBox/vmapi.h>
31	#include <VBox/tm.h>
32	#include <VBox/ssm.h>
33	#include <VBox/em.h>
34	#include <VBox/trpm.h>
35	#include <VBox/iom.h>
36	#include <VBox/mm.h>
37	#include <VBox/pgm.h>
38	#include <VBox/pdm.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/dbg.h>
41	#include <VBox/hwaccm.h>
42	#include <VBox/patm.h>
43	#include <VBox/csam.h>
44	#include "REMInternal.h"
45	#include <VBox/vm.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49	#define LOG_GROUP LOG_GROUP_REM
50	#include <VBox/log.h>
51	#include <iprt/semaphore.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/thread.h>
55	#include <iprt/string.h>
56
57
58	/* Don't wanna include everything. */
59	extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
60	extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
61	extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
62	extern void tlb_flush_page(CPUX86State *env, uint32_t addr);
63	extern void tlb_flush(CPUState *env, int flush_global);
64	extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
65	extern void sync_ldtr(CPUX86State *env1, int selector);
66	extern int sync_tr(CPUX86State *env1, int selector);
67
68	#ifdef VBOX_STRICT
69	unsigned long get_phys_page_offset(target_ulong addr);
70	#endif
71
72
73	/*******************************************************************************
74	* Defined Constants And Macros *
75	*******************************************************************************/
76
77	/** Copy 80-bit fpu register at pSrc to pDst.
78	* This is probably faster than calling memcpy.
79	*/
80	#define REM_COPY_FPU_REG(pDst, pSrc) \
81	do { (PX86FPUMMX)(pDst) = (const X86FPUMMX *)(pSrc); } while (0)
82
83
84	/*******************************************************************************
85	* Internal Functions *
86	*******************************************************************************/
87	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
88	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
89	static void remR3StateUpdate(PVM pVM);
90	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
91	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
92	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
93	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
94	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96
97	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
98	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
99	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
100	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
101	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103
104
105	/*******************************************************************************
106	* Global Variables *
107	*******************************************************************************/
108
109	/** The log level of the recompiler. */
110	#if 1
111	extern int loglevel;
112	#else
113	int loglevel = ~0;
114	FILE *logfile = NULL;
115	#endif
116
117
118	/** @todo Move stats to REM::s some rainy day we have nothing do to. */
119	#ifdef VBOX_WITH_STATISTICS
120	static STAMPROFILEADV gStatExecuteSingleInstr;
121	static STAMPROFILEADV gStatCompilationQEmu;
122	static STAMPROFILEADV gStatRunCodeQEmu;
123	static STAMPROFILEADV gStatTotalTimeQEmu;
124	static STAMPROFILEADV gStatTimers;
125	static STAMPROFILEADV gStatTBLookup;
126	static STAMPROFILEADV gStatIRQ;
127	static STAMPROFILEADV gStatRawCheck;
128	static STAMPROFILEADV gStatMemRead;
129	static STAMPROFILEADV gStatMemWrite;
130	static STAMCOUNTER gStatRefuseTFInhibit;
131	static STAMCOUNTER gStatRefuseVM86;
132	static STAMCOUNTER gStatRefusePaging;
133	static STAMCOUNTER gStatRefusePAE;
134	static STAMCOUNTER gStatRefuseIOPLNot0;
135	static STAMCOUNTER gStatRefuseIF0;
136	static STAMCOUNTER gStatRefuseCode16;
137	static STAMCOUNTER gStatRefuseWP0;
138	static STAMCOUNTER gStatRefuseRing1or2;
139	static STAMCOUNTER gStatRefuseCanExecute;
140	static STAMCOUNTER gStatREMGDTChange;
141	static STAMCOUNTER gStatREMIDTChange;
142	static STAMCOUNTER gStatREMLDTRChange;
143	static STAMCOUNTER gStatREMTRChange;
144	static STAMCOUNTER gStatSelOutOfSync[6];
145	static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
146	#endif
147
148	/*
149	* Global stuff.
150	*/
151
152	/** MMIO read callbacks. */
153	CPUReadMemoryFunc *g_apfnMMIORead[3] =
154	{
155	remR3MMIOReadU8,
156	remR3MMIOReadU16,
157	remR3MMIOReadU32
158	};
159
160	/** MMIO write callbacks. */
161	CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
162	{
163	remR3MMIOWriteU8,
164	remR3MMIOWriteU16,
165	remR3MMIOWriteU32
166	};
167
168	/** Handler read callbacks. */
169	CPUReadMemoryFunc *g_apfnHandlerRead[3] =
170	{
171	remR3HandlerReadU8,
172	remR3HandlerReadU16,
173	remR3HandlerReadU32
174	};
175
176	/** Handler write callbacks. */
177	CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
178	{
179	remR3HandlerWriteU8,
180	remR3HandlerWriteU16,
181	remR3HandlerWriteU32
182	};
183
184	#ifndef PGM_DYNAMIC_RAM_ALLOC
185	/* Guest physical RAM base. Not to be used in external code. */
186	static uint8_t *phys_ram_base;
187	#endif
188
189	/*
190	* Instance stuff.
191	*/
192	/** Pointer to the cpu state. */
193	CPUState *cpu_single_env;
194
195
196	#ifdef VBOX_WITH_DEBUGGER
197	/*
198	* Debugger commands.
199	*/
200	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
201
202	/** '.remstep' arguments. */
203	static const DBGCVARDESC g_aArgRemStep[] =
204	{
205	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
206	{ 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
207	};
208
209	/** Command descriptors. */
210	static const DBGCCMD g_aCmds[] =
211	{
212	{
213	.pszCmd ="remstep",
214	.cArgsMin = 0,
215	.cArgsMax = 1,
216	.paArgDescs = &g_aArgRemStep[0],
217	.cArgDescs = ELEMENTS(g_aArgRemStep),
218	.pResultDesc = NULL,
219	.fFlags = 0,
220	.pfnHandler = remR3CmdDisasEnableStepping,
221	.pszSyntax = "[on/off]",
222	.pszDescription = "Enable or disable the single stepping with logged disassembly. "
223	"If no arguments show the current state."
224	}
225	};
226	#endif
227
228
229	/*******************************************************************************
230	* Internal Functions *
231	*******************************************************************************/
232	static void remAbort(int rc, const char *pszTip);
233
234
235	/* Put them here to avoid unused variable warning. */
236	AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
237	//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
238	//AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
239
240	/**
241	* Initializes the REM.
242	*
243	* @returns VBox status code.
244	* @param pVM The VM to operate on.
245	*/
246	REMR3DECL(int) REMR3Init(PVM pVM)
247	{
248	uint32_t u32Dummy;
249	AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
250	//AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
251	AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
252	#if 0 /* not merged yet */
253	Assert(!testmath());
254	#endif
255
256	/*
257	* Init some internal data members.
258	*/
259	pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
260	pVM->rem.s.Env.pVM = pVM;
261	#ifdef CPU_RAW_MODE_INIT
262	pVM->rem.s.state \|= CPU_RAW_MODE_INIT;
263	#endif
264
265	/* ctx. */
266	int rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);
267	if (VBOX_FAILURE(rc))
268	{
269	AssertMsgFailed(("Failed to obtain guest ctx pointer. rc=%Vrc\n", rc));
270	return rc;
271	}
272	AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
273
274	/*
275	* Init the recompiler.
276	*/
277	if (!cpu_x86_init(&pVM->rem.s.Env))
278	{
279	AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
280	return VERR_GENERAL_FAILURE;
281	}
282	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
283
284	/* allocate code buffer for single instruction emulation. */
285	pVM->rem.s.Env.cbCodeBuffer = 4096;
286	pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
287	AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
288
289	/* finally, set the cpu_single_env global. */
290	cpu_single_env = &pVM->rem.s.Env;
291
292	/* Nothing is pending by default */
293	pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
294
295	#ifdef DEBUG_bird
296	//cpu_breakpoint_insert(&pVM->rem.s.Env, some-address);
297	#endif
298
299	/*
300	* Register ram types.
301	*/
302	pVM->rem.s.iMMIOMemType = cpu_register_io_memory(0, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
303	AssertReleaseMsg(pVM->rem.s.iMMIOMemType > 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
304	pVM->rem.s.iHandlerMemType = cpu_register_io_memory(0, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
305	AssertReleaseMsg(pVM->rem.s.iHandlerMemType > 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
306	Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
307
308	/*
309	* Register the saved state data unit.
310	*/
311	rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
312	NULL, remR3Save, NULL,
313	NULL, remR3Load, NULL);
314	if (VBOX_FAILURE(rc))
315	return rc;
316
317	#ifdef VBOX_WITH_DEBUGGER
318	/*
319	* Debugger commands.
320	*/
321	static bool fRegisteredCmds = false;
322	if (!fRegisteredCmds)
323	{
324	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
325	if (VBOX_SUCCESS(rc))
326	fRegisteredCmds = true;
327	}
328	#endif
329
330	#ifdef VBOX_WITH_STATISTICS
331	/*
332	* Statistics.
333	*/
334	STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
335	STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
336	STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
337	STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
338	STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
339	STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
340	STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
341	STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
342	STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
343	STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
344
345	STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
346	STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
347	STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
348	STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
349	STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
350	STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
351	STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
352	STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
353	STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
354	STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
355
356	STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
357	STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
358	STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
359	STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
360
361	STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
362	STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
363	STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
364	STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
365	STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
366	STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
367
368	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
369	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
370	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
371	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
372	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
373	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
374
375	#endif
376	return rc;
377	}
378
379
380	/**
381	* Terminates the REM.
382	*
383	* Termination means cleaning up and freeing all resources,
384	* the VM it self is at this point powered off or suspended.
385	*
386	* @returns VBox status code.
387	* @param pVM The VM to operate on.
388	*/
389	REMR3DECL(int) REMR3Term(PVM pVM)
390	{
391	return VINF_SUCCESS;
392	}
393
394
395	/**
396	* The VM is being reset.
397	*
398	* For the REM component this means to call the cpu_reset() and
399	* reinitialize some state variables.
400	*
401	* @param pVM VM handle.
402	*/
403	REMR3DECL(void) REMR3Reset(PVM pVM)
404	{
405	pVM->rem.s.fIgnoreCR3Load = true;
406	pVM->rem.s.fIgnoreInvlPg = true;
407	pVM->rem.s.fIgnoreCpuMode = true;
408
409	/*
410	* Reset the REM cpu.
411	*/
412	cpu_reset(&pVM->rem.s.Env);
413	pVM->rem.s.cInvalidatedPages = 0;
414
415	pVM->rem.s.fIgnoreCR3Load = false;
416	pVM->rem.s.fIgnoreInvlPg = false;
417	pVM->rem.s.fIgnoreCpuMode = false;
418	}
419
420
421	/**
422	* Execute state save operation.
423	*
424	* @returns VBox status code.
425	* @param pVM VM Handle.
426	* @param pSSM SSM operation handle.
427	*/
428	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
429	{
430	LogFlow(("remR3Save:\n"));
431
432	/*
433	* Save the required CPU Env bits.
434	* (Not much because we're never in REM when doing the save.)
435	*/
436	PREM pRem = &pVM->rem.s;
437	Assert(!pRem->fInREM);
438	SSMR3PutU32(pSSM, pRem->Env.hflags);
439	SSMR3PutMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
440	SSMR3PutU32(pSSM, ~0); /* separator */
441
442	/* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
443	SSMR3PutUInt(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
444
445	/*
446	* Save the REM stuff.
447	*/
448	SSMR3PutUInt(pSSM, pRem->cInvalidatedPages);
449	unsigned i;
450	for (i = 0; i < pRem->cInvalidatedPages; i++)
451	SSMR3PutGCPtr(pSSM, pRem->aGCPtrInvalidatedPages[i]);
452
453	SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
454
455	return SSMR3PutU32(pSSM, ~0); /* terminator */
456	}
457
458
459	/**
460	* Execute state load operation.
461	*
462	* @returns VBox status code.
463	* @param pVM VM Handle.
464	* @param pSSM SSM operation handle.
465	* @param u32Version Data layout version.
466	*/
467	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
468	{
469	uint32_t u32Dummy;
470	uint32_t fRawRing0 = false;
471
472	LogFlow(("remR3Load:\n"));
473
474	/*
475	* Validate version.
476	*/
477	if (u32Version != REM_SAVED_STATE_VERSION)
478	{
479	Log(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
480	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
481	}
482
483	/*
484	* Do a reset to be on the safe side...
485	*/
486	REMR3Reset(pVM);
487
488	/*
489	* Ignore all ignorable notifications.
490	* Not doing this will cause big trouble.
491	*/
492	pVM->rem.s.fIgnoreCR3Load = true;
493	pVM->rem.s.fIgnoreInvlPg = true;
494	pVM->rem.s.fIgnoreCpuMode = true;
495
496	/*
497	* Load the required CPU Env bits.
498	* (Not much because we're never in REM when doing the save.)
499	*/
500	PREM pRem = &pVM->rem.s;
501	Assert(!pRem->fInREM);
502	SSMR3GetU32(pSSM, &pRem->Env.hflags);
503	SSMR3GetMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
504	uint32_t u32Sep;
505	int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
506	if (VBOX_FAILURE(rc))
507	return rc;
508	if (u32Sep != ~0)
509	{
510	AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
511	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
512	}
513
514	/* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
515	SSMR3GetUInt(pSSM, &fRawRing0);
516	if (fRawRing0)
517	pRem->Env.state \|= CPU_RAW_RING0;
518
519	/*
520	* Load the REM stuff.
521	*/
522	rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
523	if (VBOX_FAILURE(rc))
524	return rc;
525	if (pRem->cInvalidatedPages > ELEMENTS(pRem->aGCPtrInvalidatedPages))
526	{
527	AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
528	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
529	}
530	unsigned i;
531	for (i = 0; i < pRem->cInvalidatedPages; i++)
532	SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
533
534	rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
535	if (VBOX_FAILURE(rc))
536	return rc;
537
538	/* check the terminator. */
539	rc = SSMR3GetU32(pSSM, &u32Sep);
540	if (VBOX_FAILURE(rc))
541	return rc;
542	if (u32Sep != ~0)
543	{
544	AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
545	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
546	}
547
548	/*
549	* Get the CPUID features.
550	*/
551	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
552
553	/*
554	* Sync the Load Flush the TLB
555	*/
556	tlb_flush(&pRem->Env, 1);
557
558	#if 0 /** @todo r=bird: this doesn't make sense. WHY? */
559	/*
560	* Clear all lazy flags (only FPU sync for now).
561	*/
562	CPUMGetAndClearFPUUsedREM(pVM);
563	#endif
564
565	/*
566	* Stop ignoring ignornable notifications.
567	*/
568	pVM->rem.s.fIgnoreCpuMode = false;
569	pVM->rem.s.fIgnoreInvlPg = false;
570	pVM->rem.s.fIgnoreCR3Load = false;
571
572	return VINF_SUCCESS;
573	}
574
575
576
577	#undef LOG_GROUP
578	#define LOG_GROUP LOG_GROUP_REM_RUN
579
580	/**
581	* Single steps an instruction in recompiled mode.
582	*
583	* Before calling this function the REM state needs to be in sync with
584	* the VM. Call REMR3State() to perform the sync. It's only necessary
585	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
586	* and after calling REMR3StateBack().
587	*
588	* @returns VBox status code.
589	*
590	* @param pVM VM Handle.
591	*/
592	REMR3DECL(int) REMR3Step(PVM pVM)
593	{
594	/*
595	* Lock the REM - we don't wanna have anyone interrupting us
596	* while stepping - and enabled single stepping. We also ignore
597	* pending interrupts and suchlike.
598	*/
599	int interrupt_request = pVM->rem.s.Env.interrupt_request;
600	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
601	pVM->rem.s.Env.interrupt_request = 0;
602	cpu_single_step(&pVM->rem.s.Env, 1);
603
604	/*
605	* If we're standing at a breakpoint, that have to be disabled before we start stepping.
606	*/
607	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
608	bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
609
610	/*
611	* Execute and handle the return code.
612	* We execute without enabling the cpu tick, so on success we'll
613	* just flip it on and off to make sure it moves
614	*/
615	int rc = cpu_exec(&pVM->rem.s.Env);
616	if (rc == EXCP_DEBUG)
617	{
618	TMCpuTickResume(pVM);
619	TMCpuTickPause(pVM);
620	TMVirtualResume(pVM);
621	TMVirtualPause(pVM);
622	rc = VINF_EM_DBG_STEPPED;
623	}
624	else
625	{
626	AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
627	switch (rc)
628	{
629	case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
630	case EXCP_HLT: rc = VINF_EM_HALT; break;
631	case EXCP_RC:
632	rc = pVM->rem.s.rc;
633	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
634	break;
635	default:
636	AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
637	rc = VERR_INTERNAL_ERROR;
638	break;
639	}
640	}
641
642	/*
643	* Restore the stuff we changed to prevent interruption.
644	* Unlock the REM.
645	*/
646	if (fBp)
647	{
648	int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
649	Assert(rc2 == 0); NOREF(rc2);
650	}
651	cpu_single_step(&pVM->rem.s.Env, 0);
652	pVM->rem.s.Env.interrupt_request = interrupt_request;
653
654	return rc;
655	}
656
657
658	/**
659	* Set a breakpoint using the REM facilities.
660	*
661	* @returns VBox status code.
662	* @param pVM The VM handle.
663	* @param Address The breakpoint address.
664	* @thread The emulation thread.
665	*/
666	REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
667	{
668	VM_ASSERT_EMT(pVM);
669	if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
670	{
671	LogFlow(("REMR3BreakpointSet: Address=%VGv\n", Address));
672	return VINF_SUCCESS;
673	}
674	LogFlow(("REMR3BreakpointSet: Address=%VGv - failed!\n", Address));
675	return VERR_REM_NO_MORE_BP_SLOTS;
676	}
677
678
679	/**
680	* Clears a breakpoint set by REMR3BreakpointSet().
681	*
682	* @returns VBox status code.
683	* @param pVM The VM handle.
684	* @param Address The breakpoint address.
685	* @thread The emulation thread.
686	*/
687	REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
688	{
689	VM_ASSERT_EMT(pVM);
690	if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
691	{
692	LogFlow(("REMR3BreakpointClear: Address=%VGv\n", Address));
693	return VINF_SUCCESS;
694	}
695	LogFlow(("REMR3BreakpointClear: Address=%VGv - not found!\n", Address));
696	return VERR_REM_BP_NOT_FOUND;
697	}
698
699
700	/**
701	* Emulate an instruction.
702	*
703	* This function executes one instruction without letting anyone
704	* interrupt it. This is intended for being called while being in
705	* raw mode and thus will take care of all the state syncing between
706	* REM and the rest.
707	*
708	* @returns VBox status code.
709	* @param pVM VM handle.
710	*/
711	REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
712	{
713	Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
714
715	/*
716	* Sync the state and enable single instruction / single stepping.
717	*/
718	int rc = REMR3State(pVM);
719	if (VBOX_SUCCESS(rc))
720	{
721	int interrupt_request = pVM->rem.s.Env.interrupt_request;
722	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
723	Assert(!pVM->rem.s.Env.singlestep_enabled);
724	#if 1
725
726	/*
727	* Now we set the execute single instruction flag and enter the cpu_exec loop.
728	*/
729	pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
730	rc = cpu_exec(&pVM->rem.s.Env);
731	switch (rc)
732	{
733	/*
734	* Executed without anything out of the way happening.
735	*/
736	case EXCP_SINGLE_INSTR:
737	rc = VINF_EM_RESCHEDULE;
738	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
739	break;
740
741	/*
742	* If we take a trap or start servicing a pending interrupt, we might end up here.
743	* (Timer thread or some other thread wishing EMT's attention.)
744	*/
745	case EXCP_INTERRUPT:
746	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
747	rc = VINF_EM_RESCHEDULE;
748	break;
749
750	/*
751	* Single step, we assume!
752	* If there was a breakpoint there we're fucked now.
753	*/
754	case EXCP_DEBUG:
755	{
756	/* breakpoint or single step? */
757	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
758	int iBP;
759	rc = VINF_EM_DBG_STEPPED;
760	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
761	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
762	{
763	rc = VINF_EM_DBG_BREAKPOINT;
764	break;
765	}
766	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
767	break;
768	}
769
770	/*
771	* hlt instruction.
772	*/
773	case EXCP_HLT:
774	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
775	rc = VINF_EM_HALT;
776	break;
777
778	/*
779	* Switch to RAW-mode.
780	*/
781	case EXCP_EXECUTE_RAW:
782	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
783	rc = VINF_EM_RESCHEDULE_RAW;
784	break;
785
786	/*
787	* Switch to hardware accelerated RAW-mode.
788	*/
789	case EXCP_EXECUTE_HWACC:
790	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
791	rc = VINF_EM_RESCHEDULE_HWACC;
792	break;
793
794	/*
795	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
796	*/
797	case EXCP_RC:
798	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
799	rc = pVM->rem.s.rc;
800	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
801	break;
802
803	/*
804	* Figure out the rest when they arrive....
805	*/
806	default:
807	AssertMsgFailed(("rc=%d\n", rc));
808	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
809	rc = VINF_EM_RESCHEDULE;
810	break;
811	}
812
813	/*
814	* Switch back the state.
815	*/
816	#else
817	pVM->rem.s.Env.interrupt_request = 0;
818	cpu_single_step(&pVM->rem.s.Env, 1);
819
820	/*
821	* Execute and handle the return code.
822	* We execute without enabling the cpu tick, so on success we'll
823	* just flip it on and off to make sure it moves.
824	*
825	* (We do not use emulate_single_instr() because that doesn't enter the
826	* right way in will cause serious trouble if a longjmp was attempted.)
827	*/
828	#ifdef DEBUG_bird
829	remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
830	#endif
831	int cTimesMax = 16384;
832	uint32_t eip = pVM->rem.s.Env.eip;
833	do
834	{
835	rc = cpu_exec(&pVM->rem.s.Env);
836	} while ( eip == pVM->rem.s.Env.eip
837	&& (rc == EXCP_DEBUG \|\| rc == EXCP_EXECUTE_RAW)
838	&& --cTimesMax > 0);
839	switch (rc)
840	{
841	/*
842	* Single step, we assume!
843	* If there was a breakpoint there we're fucked now.
844	*/
845	case EXCP_DEBUG:
846	{
847	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
848	rc = VINF_EM_RESCHEDULE;
849	break;
850	}
851
852	/*
853	* We cannot be interrupted!
854	*/
855	case EXCP_INTERRUPT:
856	AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
857	rc = VERR_INTERNAL_ERROR;
858	break;
859
860	/*
861	* hlt instruction.
862	*/
863	case EXCP_HLT:
864	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
865	rc = VINF_EM_HALT;
866	break;
867
868	/*
869	* Switch to RAW-mode.
870	*/
871	case EXCP_EXECUTE_RAW:
872	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
873	rc = VINF_EM_RESCHEDULE_RAW;
874	break;
875
876	/*
877	* Switch to hardware accelerated RAW-mode.
878	*/
879	case EXCP_EXECUTE_HWACC:
880	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
881	rc = VINF_EM_RESCHEDULE_HWACC;
882	break;
883
884	/*
885	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
886	*/
887	case EXCP_RC:
888	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
889	rc = pVM->rem.s.rc;
890	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
891	break;
892
893	/*
894	* Figure out the rest when they arrive....
895	*/
896	default:
897	AssertMsgFailed(("rc=%d\n", rc));
898	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
899	rc = VINF_SUCCESS;
900	break;
901	}
902
903	/*
904	* Switch back the state.
905	*/
906	cpu_single_step(&pVM->rem.s.Env, 0);
907	#endif
908	pVM->rem.s.Env.interrupt_request = interrupt_request;
909	int rc2 = REMR3StateBack(pVM);
910	AssertRC(rc2);
911	}
912
913	Log2(("REMR3EmulateInstruction: returns %Vrc (cs:eip=%04x:%08x)\n",
914	rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
915	return rc;
916	}
917
918
919	/**
920	* Runs code in recompiled mode.
921	*
922	* Before calling this function the REM state needs to be in sync with
923	* the VM. Call REMR3State() to perform the sync. It's only necessary
924	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
925	* and after calling REMR3StateBack().
926	*
927	* @returns VBox status code.
928	*
929	* @param pVM VM Handle.
930	*/
931	REMR3DECL(int) REMR3Run(PVM pVM)
932	{
933	Log2(("REMR3Run: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
934	Assert(pVM->rem.s.fInREM);
935	////Keyboard / tb stuff:
936	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0xf000
937	// && pVM->rem.s.Env.eip >= 0xe860
938	// && pVM->rem.s.Env.eip <= 0xe880)
939	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
940	////A20:
941	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x9020
942	// && pVM->rem.s.Env.eip >= 0x970
943	// && pVM->rem.s.Env.eip <= 0x9a0)
944	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
945	////Speaker (port 61h)
946	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x0010
947	// && ( (pVM->rem.s.Env.eip >= 0x90278c10 && pVM->rem.s.Env.eip <= 0x90278c30)
948	// \|\| (pVM->rem.s.Env.eip >= 0x9010e250 && pVM->rem.s.Env.eip <= 0x9010e260)
949	// )
950	// )
951	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
952	//DBGFR3InfoLog(pVM, "timers", NULL);
953
954
955	int rc = cpu_exec(&pVM->rem.s.Env);
956	switch (rc)
957	{
958	/*
959	* This happens when the execution was interrupted
960	* by an external event, like pending timers.
961	*/
962	case EXCP_INTERRUPT:
963	Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
964	rc = VINF_SUCCESS;
965	break;
966
967	/*
968	* hlt instruction.
969	*/
970	case EXCP_HLT:
971	Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
972	rc = VINF_EM_HALT;
973	break;
974
975	/*
976	* Breakpoint/single step.
977	*/
978	case EXCP_DEBUG:
979	{
980	#if 0//def DEBUG_bird
981	static int iBP = 0;
982	printf("howdy, breakpoint! iBP=%d\n", iBP);
983	switch (iBP)
984	{
985	case 0:
986	cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
987	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
988	//pVM->rem.s.Env.interrupt_request = 0;
989	//pVM->rem.s.Env.exception_index = -1;
990	//g_fInterruptDisabled = 1;
991	rc = VINF_SUCCESS;
992	asm("int3");
993	break;
994	default:
995	asm("int3");
996	break;
997	}
998	iBP++;
999	#else
1000	/* breakpoint or single step? */
1001	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1002	int iBP;
1003	rc = VINF_EM_DBG_STEPPED;
1004	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
1005	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
1006	{
1007	rc = VINF_EM_DBG_BREAKPOINT;
1008	break;
1009	}
1010	Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
1011	#endif
1012	break;
1013	}
1014
1015	/*
1016	* Switch to RAW-mode.
1017	*/
1018	case EXCP_EXECUTE_RAW:
1019	Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1020	rc = VINF_EM_RESCHEDULE_RAW;
1021	break;
1022
1023	/*
1024	* Switch to hardware accelerated RAW-mode.
1025	*/
1026	case EXCP_EXECUTE_HWACC:
1027	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1028	rc = VINF_EM_RESCHEDULE_HWACC;
1029	break;
1030
1031	/*
1032	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
1033	*/
1034	case EXCP_RC:
1035	Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
1036	rc = pVM->rem.s.rc;
1037	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1038	break;
1039
1040	/*
1041	* Figure out the rest when they arrive....
1042	*/
1043	default:
1044	AssertMsgFailed(("rc=%d\n", rc));
1045	Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1046	rc = VINF_SUCCESS;
1047	break;
1048	}
1049
1050	Log2(("REMR3Run: returns %Vrc (cs:eip=%04x:%08x)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
1051	return rc;
1052	}
1053
1054
1055	/**
1056	* Check if the cpu state is suitable for Raw execution.
1057	*
1058	* @returns boolean
1059	* @param env The CPU env struct.
1060	* @param eip The EIP to check this for (might differ from env->eip).
1061	* @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1062	* @param pExceptionIndex Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1063	*
1064	* @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1065	*/
1066	bool remR3CanExecuteRaw(CPUState env, RTGCPTR eip, unsigned fFlags, uint32_t pExceptionIndex)
1067	{
1068	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1069	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1070	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1071
1072	/* Update counter. */
1073	env->pVM->rem.s.cCanExecuteRaw++;
1074
1075	if (HWACCMIsEnabled(env->pVM))
1076	{
1077	env->state \|= CPU_RAW_HWACC;
1078
1079	/*
1080	* Create partial context for HWACCMR3CanExecuteGuest
1081	*/
1082	CPUMCTX Ctx;
1083	Ctx.cr0 = env->cr[0];
1084	Ctx.cr3 = env->cr[3];
1085	Ctx.cr4 = env->cr[4];
1086
1087	Ctx.tr = env->tr.selector;
1088	Ctx.trHid.u32Base = (uint32_t)env->tr.base;
1089	Ctx.trHid.u32Limit = env->tr.limit;
1090	Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1091
1092	Ctx.idtr.cbIdt = env->idt.limit;
1093	Ctx.idtr.pIdt = (uint32_t)env->idt.base;
1094
1095	Ctx.eflags.u32 = env->eflags;
1096
1097	Ctx.cs = env->segs[R_CS].selector;
1098	Ctx.csHid.u32Base = (uint32_t)env->segs[R_CS].base;
1099	Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1100	Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1101
1102	Ctx.ss = env->segs[R_SS].selector;
1103	Ctx.ssHid.u32Base = (uint32_t)env->segs[R_SS].base;
1104	Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1105	Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1106
1107	/* Hardware accelerated raw-mode:
1108	*
1109	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1110	*/
1111	if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1112	{
1113	*pExceptionIndex = EXCP_EXECUTE_HWACC;
1114	return true;
1115	}
1116	return false;
1117	}
1118
1119	/*
1120	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1121	* or 32 bits protected mode ring 0 code
1122	*
1123	* The tests are ordered by the likelyhood of being true during normal execution.
1124	*/
1125	if (fFlags & (HF_TF_MASK \| HF_INHIBIT_IRQ_MASK))
1126	{
1127	STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1128	Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1129	return false;
1130	}
1131
1132	#ifndef VBOX_RAW_V86
1133	if (fFlags & VM_MASK) {
1134	STAM_COUNTER_INC(&gStatRefuseVM86);
1135	Log2(("raw mode refused: VM_MASK\n"));
1136	return false;
1137	}
1138	#endif
1139
1140	if (env->state & CPU_EMULATE_SINGLE_INSTR)
1141	{
1142	#ifndef DEBUG_bird
1143	Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1144	#endif
1145	return false;
1146	}
1147
1148	if (env->singlestep_enabled)
1149	{
1150	//Log2(("raw mode refused: Single step\n"));
1151	return false;
1152	}
1153
1154	if (env->nb_breakpoints > 0)
1155	{
1156	//Log2(("raw mode refused: Breakpoints\n"));
1157	return false;
1158	}
1159
1160	uint32_t u32CR0 = env->cr[0];
1161	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
1162	{
1163	STAM_COUNTER_INC(&gStatRefusePaging);
1164	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1165	return false;
1166	}
1167
1168	if (env->cr[4] & CR4_PAE_MASK)
1169	{
1170	STAM_COUNTER_INC(&gStatRefusePAE);
1171	//Log2(("raw mode refused: PAE\n"));
1172	return false;
1173	}
1174
1175	if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1176	{
1177	if (!EMIsRawRing3Enabled(env->pVM))
1178	return false;
1179
1180	if (!(env->eflags & IF_MASK))
1181	{
1182	STAM_COUNTER_INC(&gStatRefuseIF0);
1183	Log2(("raw mode refused: IF (RawR3)\n"));
1184	return false;
1185	}
1186
1187	if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1188	{
1189	STAM_COUNTER_INC(&gStatRefuseWP0);
1190	Log2(("raw mode refused: CR0.WP + RawR0\n"));
1191	return false;
1192	}
1193	}
1194	else
1195	{
1196	if (!EMIsRawRing0Enabled(env->pVM))
1197	return false;
1198
1199	// Let's start with pure 32 bits ring 0 code first
1200	if ((fFlags & (HF_SS32_MASK \| HF_CS32_MASK)) != (HF_SS32_MASK \| HF_CS32_MASK))
1201	{
1202	STAM_COUNTER_INC(&gStatRefuseCode16);
1203	Log2(("raw r0 mode refused: HF_[S\|C]S32_MASK fFlags=%#x\n", fFlags));
1204	return false;
1205	}
1206
1207	// Only R0
1208	if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1209	{
1210	STAM_COUNTER_INC(&gStatRefuseRing1or2);
1211	Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1212	return false;
1213	}
1214
1215	if (!(u32CR0 & CR0_WP_MASK))
1216	{
1217	STAM_COUNTER_INC(&gStatRefuseWP0);
1218	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1219	return false;
1220	}
1221
1222	if (PATMIsPatchGCAddr(env->pVM, eip))
1223	{
1224	Log2(("raw r0 mode forced: patch code\n"));
1225	*pExceptionIndex = EXCP_EXECUTE_RAW;
1226	return true;
1227	}
1228
1229	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1230	if (!(env->eflags & IF_MASK))
1231	{
1232	STAM_COUNTER_INC(&gStatRefuseIF0);
1233	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1234	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1235	return false;
1236	}
1237	#endif
1238
1239	env->state \|= CPU_RAW_RING0;
1240	}
1241
1242	/*
1243	* Don't reschedule the first time we're called, because there might be
1244	* special reasons why we're here that is not covered by the above checks.
1245	*/
1246	if (env->pVM->rem.s.cCanExecuteRaw == 1)
1247	{
1248	Log2(("raw mode refused: first scheduling\n"));
1249	STAM_COUNTER_INC(&gStatRefuseCanExecute);
1250	return false;
1251	}
1252
1253	Assert(PGMPhysIsA20Enabled(env->pVM));
1254	*pExceptionIndex = EXCP_EXECUTE_RAW;
1255	return true;
1256	}
1257
1258
1259	/**
1260	* Fetches a code byte.
1261	*
1262	* @returns Success indicator (bool) for ease of use.
1263	* @param env The CPU environment structure.
1264	* @param GCPtrInstr Where to fetch code.
1265	* @param pu8Byte Where to store the byte on success
1266	*/
1267	bool remR3GetOpcode(CPUState env, RTGCPTR GCPtrInstr, uint8_t pu8Byte)
1268	{
1269	int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1270	if (VBOX_SUCCESS(rc))
1271	return true;
1272	return false;
1273	}
1274
1275
1276	/**
1277	* Flush (or invalidate if you like) page table/dir entry.
1278	*
1279	* (invlpg instruction; tlb_flush_page)
1280	*
1281	* @param env Pointer to cpu environment.
1282	* @param GCPtr The virtual address which page table/dir entry should be invalidated.
1283	*/
1284	void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1285	{
1286	PVM pVM = env->pVM;
1287
1288	/*
1289	* When we're replaying invlpg instructions or restoring a saved
1290	* state we disable this path.
1291	*/
1292	if (pVM->rem.s.fIgnoreInvlPg)
1293	return;
1294	Log(("remR3FlushPage: GCPtr=%VGv\n", GCPtr));
1295
1296	//RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1297
1298	/*
1299	* Update the control registers before calling PGMFlushPage.
1300	*/
1301	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1302	pCtx->cr0 = env->cr[0];
1303	pCtx->cr3 = env->cr[3];
1304	pCtx->cr4 = env->cr[4];
1305
1306	/*
1307	* Let PGM do the rest.
1308	*/
1309	int rc = PGMInvalidatePage(pVM, GCPtr);
1310	if (VBOX_FAILURE(rc))
1311	{
1312	AssertMsgFailed(("remR3FlushPage %x %x %x %d failed!!\n", GCPtr));
1313	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1314	}
1315	//RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1316	}
1317
1318	/**
1319	* Set page table/dir entry. (called from tlb_set_page)
1320	*
1321	* @param env Pointer to cpu environment.
1322	*/
1323	void remR3SetPage(CPUState env, CPUTLBEntry pRead, CPUTLBEntry *pWrite, int prot, int is_user)
1324	{
1325	uint32_t virt_addr, addend;
1326
1327	Log2(("tlb_set_page_raw read (%x-%x) write (%x-%x) prot %x is_user %d\n", pRead->address, pRead->addend, pWrite->address, pWrite->addend, prot, is_user));
1328
1329	if (prot & PAGE_WRITE)
1330	{
1331	addend = pWrite->addend;
1332	virt_addr = pWrite->address;
1333	}
1334	else
1335	if (prot & PAGE_READ)
1336	{
1337	addend = pRead->addend;
1338	virt_addr = pRead->address;
1339	}
1340	else
1341	{
1342	// Should never happen!
1343	AssertMsgFailed(("tlb_set_page_raw unexpected protection flags %x\n", prot));
1344	return;
1345	}
1346
1347	// Clear IO_* flags (TODO: are they actually useful for us??)
1348	virt_addr &= ~0xFFF;
1349
1350	/*
1351	* Update the control registers before calling PGMFlushPage.
1352	*/
1353	PCPUMCTX pCtx = (PCPUMCTX)env->pVM->rem.s.pCtx;
1354	pCtx->cr0 = env->cr[0];
1355	pCtx->cr3 = env->cr[3];
1356	pCtx->cr4 = env->cr[4];
1357
1358	/*
1359	* Let PGM do the rest.
1360	*/
1361	int rc = PGMInvalidatePage(env->pVM, (RTGCPTR)virt_addr);
1362	if (VBOX_FAILURE(rc))
1363	{
1364	AssertMsgFailed(("RAWEx_SetPageEntry %x %x %d failed!!\n", virt_addr, prot, is_user));
1365	VM_FF_SET(env->pVM, VM_FF_PGM_SYNC_CR3);
1366	}
1367	}
1368
1369	/**
1370	* Called from tlb_protect_code in order to write monitor a code page.
1371	*
1372	* @param env Pointer to the CPU environment.
1373	* @param GCPtr Code page to monitor
1374	*/
1375	void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1376	{
1377	if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1378	&& !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1379	&& (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1380	&& !(env->eflags & VM_MASK) /* no V86 mode */
1381	&& !HWACCMIsEnabled(env->pVM))
1382	CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1383	}
1384
1385	/**
1386	* Called when the CPU is initialized, any of the CRx registers are changed or
1387	* when the A20 line is modified.
1388	*
1389	* @param env Pointer to the CPU environment.
1390	* @param fGlobal Set if the flush is global.
1391	*/
1392	void remR3FlushTLB(CPUState *env, bool fGlobal)
1393	{
1394	PVM pVM = env->pVM;
1395
1396	/*
1397	* When we're replaying invlpg instructions or restoring a saved
1398	* state we disable this path.
1399	*/
1400	if (pVM->rem.s.fIgnoreCR3Load)
1401	return;
1402
1403	/*
1404	* The caller doesn't check cr4, so we have to do that for ourselves.
1405	*/
1406	if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1407	fGlobal = true;
1408	Log(("remR3FlushTLB: CR0=%VGp CR3=%VGp CR4=%VGp %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1409
1410	/*
1411	* Update the control registers before calling PGMR3FlushTLB.
1412	*/
1413	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1414	pCtx->cr0 = env->cr[0];
1415	pCtx->cr3 = env->cr[3];
1416	pCtx->cr4 = env->cr[4];
1417
1418	/*
1419	* Let PGM do the rest.
1420	*/
1421	PGMFlushTLB(pVM, env->cr[3], fGlobal);
1422	}
1423
1424
1425	/**
1426	* Called when any of the cr0, cr4 or efer registers is updated.
1427	*
1428	* @param env Pointer to the CPU environment.
1429	*/
1430	void remR3ChangeCpuMode(CPUState *env)
1431	{
1432	int rc;
1433	PVM pVM = env->pVM;
1434
1435	/*
1436	* When we're replaying loads or restoring a saved
1437	* state this path is disabled.
1438	*/
1439	if (pVM->rem.s.fIgnoreCpuMode)
1440	return;
1441
1442	/*
1443	* Update the control registers before calling PGMR3ChangeMode()
1444	* as it may need to map whatever cr3 is pointing to.
1445	*/
1446	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1447	pCtx->cr0 = env->cr[0];
1448	pCtx->cr3 = env->cr[3];
1449	pCtx->cr4 = env->cr[4];
1450
1451	#ifdef TARGET_X86_64
1452	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1453	if (rc != VINF_SUCCESS)
1454	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], env->efer, rc);
1455	#else
1456	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1457	if (rc != VINF_SUCCESS)
1458	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], 0LL, rc);
1459	#endif
1460	}
1461
1462
1463	/**
1464	* Called from compiled code to run dma.
1465	*
1466	* @param env Pointer to the CPU environment.
1467	*/
1468	void remR3DmaRun(CPUState *env)
1469	{
1470	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1471	PDMR3DmaRun(env->pVM);
1472	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1473	}
1474
1475	/**
1476	* Called from compiled code to schedule pending timers in VMM
1477	*
1478	* @param env Pointer to the CPU environment.
1479	*/
1480	void remR3TimersRun(CPUState *env)
1481	{
1482	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1483	remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1484	TMR3TimerQueuesDo(env->pVM);
1485	remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1486	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1487	}
1488
1489	/**
1490	* Record trap occurance
1491	*
1492	* @returns VBox status code
1493	* @param env Pointer to the CPU environment.
1494	* @param uTrap Trap nr
1495	* @param uErrorCode Error code
1496	* @param pvNextEIP Next EIP
1497	*/
1498	int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1499	{
1500	PVM pVM = (PVM)env->pVM;
1501	#ifdef VBOX_WITH_STATISTICS
1502	static STAMCOUNTER aStatTrap[255];
1503	static bool aRegisters[ELEMENTS(aStatTrap)];
1504	#endif
1505
1506	#ifdef VBOX_WITH_STATISTICS
1507	if (uTrap < 255)
1508	{
1509	if (!aRegisters[uTrap])
1510	{
1511	aRegisters[uTrap] = true;
1512	char szStatName[64];
1513	RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1514	STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1515	}
1516	STAM_COUNTER_INC(&aStatTrap[uTrap]);
1517	}
1518	#endif
1519	Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1520	if(uTrap < 0x20)
1521	{
1522	remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1523
1524	if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 128)
1525	{
1526	LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1527	remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1528	return VERR_REM_TOO_MANY_TRAPS;
1529	}
1530	if(pVM->rem.s.uPendingException != uTrap \|\| pVM->rem.s.uPendingExcptEIP != env->eip \|\| pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1531	pVM->rem.s.cPendingExceptions = 1;
1532	pVM->rem.s.uPendingException = uTrap;
1533	pVM->rem.s.uPendingExcptEIP = env->eip;
1534	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1535	}
1536	else
1537	{
1538	pVM->rem.s.cPendingExceptions = 0;
1539	pVM->rem.s.uPendingException = uTrap;
1540	pVM->rem.s.uPendingExcptEIP = env->eip;
1541	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1542	}
1543	return VINF_SUCCESS;
1544	}
1545
1546	/*
1547	* Clear current active trap
1548	*
1549	* @param pVM VM Handle.
1550	*/
1551	void remR3TrapClear(PVM pVM)
1552	{
1553	pVM->rem.s.cPendingExceptions = 0;
1554	pVM->rem.s.uPendingException = 0;
1555	pVM->rem.s.uPendingExcptEIP = 0;
1556	pVM->rem.s.uPendingExcptCR2 = 0;
1557	}
1558
1559
1560	/**
1561	* Syncs the internal REM state with the VM.
1562	*
1563	* This must be called before REMR3Run() is invoked whenever when the REM
1564	* state is not up to date. Calling it several times in a row is not
1565	* permitted.
1566	*
1567	* @returns VBox status code.
1568	*
1569	* @param pVM VM Handle.
1570	*
1571	* @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1572	* no do this since the majority of the callers don't want any unnecessary of events
1573	* pending that would immediatly interrupt execution.
1574	*/
1575	REMR3DECL(int) REMR3State(PVM pVM)
1576	{
1577	Assert(!pVM->rem.s.fInREM);
1578	Log2(("REMR3State:\n"));
1579	STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1580	register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1581	register unsigned fFlags;
1582
1583	/*
1584	* Copy the registers which requires no special handling.
1585	*/
1586	Assert(R_EAX == 0);
1587	pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1588	Assert(R_ECX == 1);
1589	pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1590	Assert(R_EDX == 2);
1591	pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1592	Assert(R_EBX == 3);
1593	pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1594	Assert(R_ESP == 4);
1595	pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1596	Assert(R_EBP == 5);
1597	pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1598	Assert(R_ESI == 6);
1599	pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1600	Assert(R_EDI == 7);
1601	pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1602	pVM->rem.s.Env.eip = pCtx->eip;
1603
1604	pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1605
1606	pVM->rem.s.Env.cr[2] = pCtx->cr2;
1607
1608	/** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1609	pVM->rem.s.Env.dr[0] = pCtx->dr0;
1610	pVM->rem.s.Env.dr[1] = pCtx->dr1;
1611	pVM->rem.s.Env.dr[2] = pCtx->dr2;
1612	pVM->rem.s.Env.dr[3] = pCtx->dr3;
1613	pVM->rem.s.Env.dr[4] = pCtx->dr4;
1614	pVM->rem.s.Env.dr[5] = pCtx->dr5;
1615	pVM->rem.s.Env.dr[6] = pCtx->dr6;
1616	pVM->rem.s.Env.dr[7] = pCtx->dr7;
1617
1618	/*
1619	* Replay invlpg?
1620	*/
1621	if (pVM->rem.s.cInvalidatedPages)
1622	{
1623	pVM->rem.s.fIgnoreInvlPg = true;
1624	RTUINT i;
1625	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1626	{
1627	Log2(("REMR3State: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1628	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1629	}
1630	pVM->rem.s.fIgnoreInvlPg = false;
1631	pVM->rem.s.cInvalidatedPages = 0;
1632	}
1633
1634	/*
1635	* Registers which are seldomly changed and require special handling / order when changed.
1636	*/
1637	fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1638	if (fFlags & ( CPUM_CHANGED_CR4 \| CPUM_CHANGED_CR3 \| CPUM_CHANGED_CR0
1639	\| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_TR
1640	\| CPUM_CHANGED_FPU_REM \| CPUM_CHANGED_SYSENTER_MSR))
1641	{
1642	if (fFlags & CPUM_CHANGED_FPU_REM)
1643	save_raw_fp_state(&pVM->rem.s.Env, (uint8_t )&pCtx->fpu); / 'save' is an excellent name. */
1644
1645	if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1646	{
1647	pVM->rem.s.fIgnoreCR3Load = true;
1648	tlb_flush(&pVM->rem.s.Env, true);
1649	pVM->rem.s.fIgnoreCR3Load = false;
1650	}
1651
1652	if (fFlags & CPUM_CHANGED_CR4)
1653	{
1654	pVM->rem.s.fIgnoreCR3Load = true;
1655	pVM->rem.s.fIgnoreCpuMode = true;
1656	cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1657	pVM->rem.s.fIgnoreCpuMode = false;
1658	pVM->rem.s.fIgnoreCR3Load = false;
1659	}
1660
1661	if (fFlags & CPUM_CHANGED_CR0)
1662	{
1663	pVM->rem.s.fIgnoreCR3Load = true;
1664	pVM->rem.s.fIgnoreCpuMode = true;
1665	cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1666	pVM->rem.s.fIgnoreCpuMode = false;
1667	pVM->rem.s.fIgnoreCR3Load = false;
1668	}
1669
1670	if (fFlags & CPUM_CHANGED_CR3)
1671	{
1672	pVM->rem.s.fIgnoreCR3Load = true;
1673	cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1674	pVM->rem.s.fIgnoreCR3Load = false;
1675	}
1676
1677	if (fFlags & CPUM_CHANGED_GDTR)
1678	{
1679	pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1680	pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1681	}
1682
1683	if (fFlags & CPUM_CHANGED_IDTR)
1684	{
1685	pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1686	pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1687	}
1688
1689	if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1690	{
1691	pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1692	pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1693	pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1694	}
1695
1696	if (fFlags & CPUM_CHANGED_LDTR)
1697	{
1698	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1699	{
1700	pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1701	pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u32Base;
1702	pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1703	pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1704	}
1705	else
1706	sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1707	}
1708
1709	if (fFlags & CPUM_CHANGED_TR)
1710	{
1711	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1712	{
1713	pVM->rem.s.Env.tr.selector = pCtx->tr;
1714	pVM->rem.s.Env.tr.base = pCtx->trHid.u32Base;
1715	pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1716	pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1717	}
1718	else
1719	sync_tr(&pVM->rem.s.Env, pCtx->tr);
1720
1721	/** @note do_interrupt will fault if the busy flag is still set.... */
1722	pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1723	}
1724	}
1725
1726	/*
1727	* Update selector registers.
1728	* This must be done after we've synced gdt, ldt and crX registers
1729	* since we're reading the GDT/LDT om sync_seg. This will happen with
1730	* saved state which takes a quick dip into rawmode for instance.
1731	*/
1732	/*
1733	* Stack; Note first check this one as the CPL might have changed. The
1734	* wrong CPL can cause QEmu to raise an exception in sync_seg!!
1735	*/
1736
1737	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1738	{
1739	/* The hidden selector registers are valid in the CPU context. */
1740	/** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1741
1742	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1743	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1744	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1745	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1746	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1747	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1748
1749	/* Set current CPL. */
1750	if (pCtx->eflags.Bits.u1VM == 1)
1751	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1752	else
1753	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1754	}
1755	else
1756	{
1757	/* In 'normal' raw mode we don't have access to the hidden selector registers. */
1758	if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1759	{
1760	Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1761
1762	cpu_x86_set_cpl(&pVM->rem.s.Env, (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & 3));
1763	sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1764	#ifdef VBOX_WITH_STATISTICS
1765	if (pVM->rem.s.Env.segs[R_SS].newselector)
1766	{
1767	STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1768	}
1769	#endif
1770	}
1771	else
1772	pVM->rem.s.Env.segs[R_SS].newselector = 0;
1773
1774	if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1775	{
1776	Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1777	sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1778	#ifdef VBOX_WITH_STATISTICS
1779	if (pVM->rem.s.Env.segs[R_ES].newselector)
1780	{
1781	STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1782	}
1783	#endif
1784	}
1785	else
1786	pVM->rem.s.Env.segs[R_ES].newselector = 0;
1787
1788	if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1789	{
1790	Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1791	sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1792	#ifdef VBOX_WITH_STATISTICS
1793	if (pVM->rem.s.Env.segs[R_CS].newselector)
1794	{
1795	STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1796	}
1797	#endif
1798	}
1799	else
1800	pVM->rem.s.Env.segs[R_CS].newselector = 0;
1801
1802	if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1803	{
1804	Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1805	sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1806	#ifdef VBOX_WITH_STATISTICS
1807	if (pVM->rem.s.Env.segs[R_DS].newselector)
1808	{
1809	STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1810	}
1811	#endif
1812	}
1813	else
1814	pVM->rem.s.Env.segs[R_DS].newselector = 0;
1815
1816	/** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1817	* be the same but not the base/limit. */
1818	if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1819	{
1820	Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1821	sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1822	#ifdef VBOX_WITH_STATISTICS
1823	if (pVM->rem.s.Env.segs[R_FS].newselector)
1824	{
1825	STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1826	}
1827	#endif
1828	}
1829	else
1830	pVM->rem.s.Env.segs[R_FS].newselector = 0;
1831
1832	if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1833	{
1834	Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1835	sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1836	#ifdef VBOX_WITH_STATISTICS
1837	if (pVM->rem.s.Env.segs[R_GS].newselector)
1838	{
1839	STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1840	}
1841	#endif
1842	}
1843	else
1844	pVM->rem.s.Env.segs[R_GS].newselector = 0;
1845	}
1846
1847	/*
1848	* Check for traps.
1849	*/
1850	pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
1851	TRPMEVENT enmType;
1852	uint8_t u8TrapNo;
1853	int rc = TRPMQueryTrap(pVM, &u8TrapNo, &enmType);
1854	if (VBOX_SUCCESS(rc))
1855	{
1856	#ifdef DEBUG
1857	if (u8TrapNo == 0x80)
1858	{
1859	remR3DumpLnxSyscall(pVM);
1860	remR3DumpOBsdSyscall(pVM);
1861	}
1862	#endif
1863
1864	pVM->rem.s.Env.exception_index = u8TrapNo;
1865	if (enmType != TRPM_SOFTWARE_INT)
1866	{
1867	pVM->rem.s.Env.exception_is_int = 0;
1868	pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
1869	}
1870	else
1871	{
1872	/*
1873	* The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
1874	* We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
1875	* for int03 and into.
1876	*/
1877	pVM->rem.s.Env.exception_is_int = 1;
1878	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 2;
1879	/* int 3 may be generated by one-byte 0xcc */
1880	if (u8TrapNo == 3)
1881	{
1882	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xcc)
1883	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1884	}
1885	/* int 4 may be generated by one-byte 0xce */
1886	else if (u8TrapNo == 4)
1887	{
1888	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xce)
1889	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1890	}
1891	}
1892
1893	/* get error code and cr2 if needed. */
1894	switch (u8TrapNo)
1895	{
1896	case 0x0e:
1897	pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
1898	/* fallthru */
1899	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
1900	pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
1901	break;
1902
1903	case 0x11: case 0x08:
1904	default:
1905	pVM->rem.s.Env.error_code = 0;
1906	break;
1907	}
1908
1909	/*
1910	* We can now reset the active trap since the recompiler is gonna have a go at it.
1911	*/
1912	rc = TRPMResetTrap(pVM);
1913	AssertRC(rc);
1914	Log2(("REMR3State: trap=%02x errcd=%VGv cr2=%VGv nexteip=%VGv%s\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.error_code,
1915	pVM->rem.s.Env.cr[2], pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
1916	}
1917
1918	/*
1919	* Clear old interrupt request flags; Check for pending hardware interrupts.
1920	* (See @remark for why we don't check for other FFs.)
1921	*/
1922	pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER);
1923	if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
1924	\|\| VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
1925	pVM->rem.s.Env.interrupt_request \|= CPU_INTERRUPT_HARD;
1926
1927	/*
1928	* We're now in REM mode.
1929	*/
1930	pVM->rem.s.fInREM = true;
1931	pVM->rem.s.cCanExecuteRaw = 0;
1932	STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
1933	Log2(("REMR3State: returns VINF_SUCCESS\n"));
1934	return VINF_SUCCESS;
1935	}
1936
1937
1938	/**
1939	* Syncs back changes in the REM state to the the VM state.
1940	*
1941	* This must be called after invoking REMR3Run().
1942	* Calling it several times in a row is not permitted.
1943	*
1944	* @returns VBox status code.
1945	*
1946	* @param pVM VM Handle.
1947	*/
1948	REMR3DECL(int) REMR3StateBack(PVM pVM)
1949	{
1950	Log2(("REMR3StateBack:\n"));
1951	Assert(pVM->rem.s.fInREM);
1952	STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
1953	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
1954
1955	/*
1956	* Copy back the registers.
1957	* This is done in the order they are declared in the CPUMCTX structure.
1958	*/
1959
1960	/** @todo FOP */
1961	/** @todo FPUIP */
1962	/** @todo CS */
1963	/** @todo FPUDP */
1964	/** @todo DS */
1965	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
1966	pCtx->fpu.MXCSR = 0;
1967	pCtx->fpu.MXCSR_MASK = 0;
1968
1969	/** @todo check if FPU/XMM was actually used in the recompiler */
1970	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
1971	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
1972
1973	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
1974	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
1975	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
1976	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
1977	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
1978	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
1979	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
1980
1981	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
1982	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
1983
1984	#ifdef VBOX_WITH_STATISTICS
1985	if (pVM->rem.s.Env.segs[R_SS].newselector)
1986	{
1987	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
1988	}
1989	if (pVM->rem.s.Env.segs[R_GS].newselector)
1990	{
1991	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
1992	}
1993	if (pVM->rem.s.Env.segs[R_FS].newselector)
1994	{
1995	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
1996	}
1997	if (pVM->rem.s.Env.segs[R_ES].newselector)
1998	{
1999	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
2000	}
2001	if (pVM->rem.s.Env.segs[R_DS].newselector)
2002	{
2003	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2004	}
2005	if (pVM->rem.s.Env.segs[R_CS].newselector)
2006	{
2007	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2008	}
2009	#endif
2010	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2011	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2012	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2013	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2014	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2015
2016	pCtx->eip = pVM->rem.s.Env.eip;
2017	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2018
2019	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2020	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2021	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2022	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2023
2024	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2025	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2026	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2027	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2028	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2029	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2030	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2031	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2032
2033	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2034	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2035	{
2036	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2037	STAM_COUNTER_INC(&gStatREMGDTChange);
2038	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2039	}
2040
2041	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2042	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2043	{
2044	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2045	STAM_COUNTER_INC(&gStatREMIDTChange);
2046	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2047	}
2048
2049	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2050	{
2051	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2052	STAM_COUNTER_INC(&gStatREMLDTRChange);
2053	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2054	}
2055	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2056	{
2057	pCtx->tr = pVM->rem.s.Env.tr.selector;
2058	STAM_COUNTER_INC(&gStatREMTRChange);
2059	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2060	}
2061
2062	/** @todo These values could still be out of sync! */
2063	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2064	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2065	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2066	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2067
2068	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2069	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2070	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2071
2072	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2073	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2074	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2075
2076	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2077	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2078	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2079
2080	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2081	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2082	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2083
2084	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2085	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2086	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2087
2088	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2089	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2090	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2091
2092	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2093	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2094	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2095
2096	/* Sysenter MSR */
2097	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2098	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2099	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2100
2101	remR3TrapClear(pVM);
2102
2103	/*
2104	* Check for traps.
2105	*/
2106	if ( pVM->rem.s.Env.exception_index >= 0
2107	&& pVM->rem.s.Env.exception_index < 256)
2108	{
2109	Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2110	int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int);
2111	AssertRC(rc);
2112	switch (pVM->rem.s.Env.exception_index)
2113	{
2114	case 0x0e:
2115	TRPMSetFaultAddress(pVM, pCtx->cr2);
2116	/* fallthru */
2117	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2118	case 0x11: case 0x08: /* 0 */
2119	TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2120	break;
2121	}
2122
2123	}
2124
2125	/*
2126	* We're not longer in REM mode.
2127	*/
2128	pVM->rem.s.fInREM = false;
2129	STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2130	Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2131	return VINF_SUCCESS;
2132	}
2133
2134
2135	/**
2136	* This is called by the disassembler when it wants to update the cpu state
2137	* before for instance doing a register dump.
2138	*/
2139	static void remR3StateUpdate(PVM pVM)
2140	{
2141	Assert(pVM->rem.s.fInREM);
2142	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2143
2144	/*
2145	* Copy back the registers.
2146	* This is done in the order they are declared in the CPUMCTX structure.
2147	*/
2148
2149	/** @todo FOP */
2150	/** @todo FPUIP */
2151	/** @todo CS */
2152	/** @todo FPUDP */
2153	/** @todo DS */
2154	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2155	pCtx->fpu.MXCSR = 0;
2156	pCtx->fpu.MXCSR_MASK = 0;
2157
2158	/** @todo check if FPU/XMM was actually used in the recompiler */
2159	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2160	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2161
2162	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2163	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2164	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2165	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2166	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2167	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2168	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2169
2170	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2171	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2172
2173	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2174	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2175	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2176	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2177	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2178
2179	pCtx->eip = pVM->rem.s.Env.eip;
2180	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2181
2182	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2183	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2184	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2185	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2186
2187	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2188	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2189	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2190	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2191	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2192	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2193	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2194	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2195
2196	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2197	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2198	{
2199	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2200	STAM_COUNTER_INC(&gStatREMGDTChange);
2201	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2202	}
2203
2204	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2205	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2206	{
2207	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2208	STAM_COUNTER_INC(&gStatREMIDTChange);
2209	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2210	}
2211
2212	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2213	{
2214	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2215	STAM_COUNTER_INC(&gStatREMLDTRChange);
2216	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2217	}
2218	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2219	{
2220	pCtx->tr = pVM->rem.s.Env.tr.selector;
2221	STAM_COUNTER_INC(&gStatREMTRChange);
2222	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2223	}
2224
2225	/** @todo These values could still be out of sync! */
2226	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2227	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2228	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2229	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2230
2231	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2232	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2233	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2234
2235	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2236	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2237	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2238
2239	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2240	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2241	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2242
2243	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2244	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2245	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2246
2247	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2248	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2249	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2250
2251	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2252	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2253	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2254
2255	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2256	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2257	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2258
2259	/* Sysenter MSR */
2260	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2261	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2262	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2263	}
2264
2265
2266	/**
2267	* Update the VMM state information if we're currently in REM.
2268	*
2269	* This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2270	* we're currently executing in REM and the VMM state is invalid. This method will of
2271	* course check that we're executing in REM before syncing any data over to the VMM.
2272	*
2273	* @param pVM The VM handle.
2274	*/
2275	REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2276	{
2277	if (pVM->rem.s.fInREM)
2278	remR3StateUpdate(pVM);
2279	}
2280
2281
2282	#undef LOG_GROUP
2283	#define LOG_GROUP LOG_GROUP_REM
2284
2285
2286	/**
2287	* Notify the recompiler about Address Gate 20 state change.
2288	*
2289	* This notification is required since A20 gate changes are
2290	* initialized from a device driver and the VM might just as
2291	* well be in REM mode as in RAW mode.
2292	*
2293	* @param pVM VM handle.
2294	* @param fEnable True if the gate should be enabled.
2295	* False if the gate should be disabled.
2296	*/
2297	REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2298	{
2299	LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2300	VM_ASSERT_EMT(pVM);
2301	cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2302	}
2303
2304
2305	/**
2306	* Replays the invalidated recorded pages.
2307	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2308	*
2309	* @param pVM VM handle.
2310	*/
2311	REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2312	{
2313	VM_ASSERT_EMT(pVM);
2314
2315	/*
2316	* Sync the required registers.
2317	*/
2318	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2319	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2320	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2321	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2322
2323	/*
2324	* Replay the flushes.
2325	*/
2326	pVM->rem.s.fIgnoreInvlPg = true;
2327	RTUINT i;
2328	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2329	{
2330	Log2(("REMR3ReplayInvalidatedPages: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2331	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2332	}
2333	pVM->rem.s.fIgnoreInvlPg = false;
2334	pVM->rem.s.cInvalidatedPages = 0;
2335	}
2336
2337
2338	/**
2339	* Replays the invalidated recorded pages.
2340	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2341	*
2342	* @param pVM VM handle.
2343	*/
2344	REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2345	{
2346	LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2347	VM_ASSERT_EMT(pVM);
2348
2349	/*
2350	* Replay the flushes.
2351	*/
2352	RTUINT i;
2353	const RTUINT c = pVM->rem.s.cHandlerNotifications;
2354	pVM->rem.s.cHandlerNotifications = 0;
2355	for (i = 0; i < c; i++)
2356	{
2357	PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2358	switch (pRec->enmKind)
2359	{
2360	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2361	REMR3NotifyHandlerPhysicalRegister(pVM,
2362	pRec->u.PhysicalRegister.enmType,
2363	pRec->u.PhysicalRegister.GCPhys,
2364	pRec->u.PhysicalRegister.cb,
2365	pRec->u.PhysicalRegister.fHasHCHandler);
2366	break;
2367
2368	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2369	REMR3NotifyHandlerPhysicalDeregister(pVM,
2370	pRec->u.PhysicalDeregister.enmType,
2371	pRec->u.PhysicalDeregister.GCPhys,
2372	pRec->u.PhysicalDeregister.cb,
2373	pRec->u.PhysicalDeregister.fHasHCHandler,
2374	pRec->u.PhysicalDeregister.pvHCPtr);
2375	break;
2376
2377	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2378	REMR3NotifyHandlerPhysicalModify(pVM,
2379	pRec->u.PhysicalModify.enmType,
2380	pRec->u.PhysicalModify.GCPhysOld,
2381	pRec->u.PhysicalModify.GCPhysNew,
2382	pRec->u.PhysicalModify.cb,
2383	pRec->u.PhysicalModify.fHasHCHandler,
2384	pRec->u.PhysicalModify.pvHCPtr);
2385	break;
2386
2387	default:
2388	AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2389	break;
2390	}
2391	}
2392	}
2393
2394
2395	/**
2396	* Notify REM about changed code page.
2397	*
2398	* @returns VBox status code.
2399	* @param pVM VM handle.
2400	* @param pvCodePage Code page address
2401	*/
2402	REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2403	{
2404	int rc;
2405	RTGCPHYS PhysGC;
2406	uint64_t flags;
2407
2408	VM_ASSERT_EMT(pVM);
2409
2410	/*
2411	* Get the physical page address.
2412	*/
2413	rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2414	if (rc == VINF_SUCCESS)
2415	{
2416	/*
2417	* Sync the required registers and flush the whole page.
2418	* (Easier to do the whole page than notifying it about each physical
2419	* byte that was changed.
2420	*/
2421	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2422	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2423	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2424	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2425
2426	tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2427	}
2428	return VINF_SUCCESS;
2429	}
2430
2431	/**
2432	* Notification about a successful MMR3PhysRegister() call.
2433	*
2434	* @param pVM VM handle.
2435	* @param GCPhys The physical address the RAM.
2436	* @param cb Size of the memory.
2437	* @param pvRam The HC address of the RAM.
2438	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2439	*/
2440	REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
2441	{
2442	Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2443	VM_ASSERT_EMT(pVM);
2444
2445	/*
2446	* Validate input - we trust the caller.
2447	*/
2448	Assert(!GCPhys \|\| pvRam);
2449	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2450	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2451	Assert(cb);
2452	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2453
2454	/*
2455	* Base ram?
2456	*/
2457	if (!GCPhys)
2458	{
2459	#ifndef PGM_DYNAMIC_RAM_ALLOC
2460	AssertRelease(!phys_ram_base);
2461	phys_ram_base = pvRam;
2462	#endif
2463	phys_ram_size = cb;
2464	phys_ram_dirty = MMR3HeapAllocZ(pVM, MM_TAG_REM, cb >> PAGE_SHIFT);
2465	AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", cb >> PAGE_SHIFT));
2466	}
2467	#ifndef PGM_DYNAMIC_RAM_ALLOC
2468	AssertRelease(phys_ram_base);
2469	#endif
2470
2471	/*
2472	* Register the ram.
2473	*/
2474	#ifdef PGM_DYNAMIC_RAM_ALLOC
2475	if (!GCPhys)
2476	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_RAM_MISSING);
2477	else
2478	{
2479	uint32_t i;
2480
2481	cpu_register_physical_memory(GCPhys, cb, GCPhys \| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2482
2483	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2484	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2485	{
2486	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2487	{
2488	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2489	pVM->rem.s.aPhysReg[i].cb = cb;
2490	break;
2491	}
2492	}
2493	if (i == pVM->rem.s.cPhysRegistrations)
2494	{
2495	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2496	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2497	pVM->rem.s.aPhysReg[i].cb = cb;
2498	pVM->rem.s.cPhysRegistrations++;
2499	}
2500	}
2501	#else
2502	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvRam - (uintptr_t)phys_ram_base)
2503	\| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2504	#endif
2505	}
2506
2507
2508	/**
2509	* Notification about a successful PGMR3PhysRegisterChunk() call.
2510	*
2511	* @param pVM VM handle.
2512	* @param GCPhys The physical address the RAM.
2513	* @param cb Size of the memory.
2514	* @param pvRam The HC address of the RAM.
2515	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2516	*/
2517	REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2518	{
2519	uint32_t idx;
2520
2521	Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2522	VM_ASSERT_EMT(pVM);
2523
2524	/*
2525	* Validate input - we trust the caller.
2526	*/
2527	Assert(pvRam);
2528	Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2529	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2530	Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2531	Assert(fFlags == 0 /* normal RAM */);
2532
2533	if (!pVM->rem.s.paHCVirtToGCPhys)
2534	{
2535	uint32_t size = (_4G >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(REMCHUNKINFO);
2536
2537	Assert(phys_ram_size);
2538
2539	pVM->rem.s.paHCVirtToGCPhys = (PREMCHUNKINFO)MMR3HeapAllocZ(pVM, MM_TAG_REM, size);
2540	pVM->rem.s.paGCPhysToHCVirt = (RTHCPTR)MMR3HeapAllocZ(pVM, MM_TAG_REM, (phys_ram_size >> PGM_DYNAMIC_CHUNK_SHIFT)*sizeof(RTHCPTR));
2541	}
2542	pVM->rem.s.paGCPhysToHCVirt[GCPhys >> PGM_DYNAMIC_CHUNK_SHIFT] = pvRam;
2543
2544	idx = (pvRam >> PGM_DYNAMIC_CHUNK_SHIFT);
2545	if (!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1)
2546	{
2547	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1 = pvRam;
2548	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 = GCPhys;
2549	}
2550	else
2551	{
2552	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2);
2553	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2 = pvRam;
2554	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 = GCPhys;
2555	}
2556	/* Does the region spawn two chunks? */
2557	if (pvRam & PGM_DYNAMIC_CHUNK_OFFSET_MASK)
2558	{
2559	if (!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1)
2560	{
2561	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1 = pvRam;
2562	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys1 = GCPhys;
2563	}
2564	else
2565	{
2566	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2);
2567	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2 = pvRam;
2568	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys2 = GCPhys;
2569	}
2570	}
2571	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2572	}
2573
2574	/**
2575	* Convert GC physical address to HC virt
2576	*
2577	* @returns The HC virt address corresponding to addr.
2578	* @param env The cpu environment.
2579	* @param addr The physical address.
2580	*/
2581	void remR3GCPhys2HCVirt(void env, target_ulong addr)
2582	{
2583	#ifdef PGM_DYNAMIC_RAM_ALLOC
2584	PVM pVM = ((CPUState *)env)->pVM;
2585	uint32_t i;
2586
2587	/* lookup in pVM->rem.s.aPhysReg array first (for ROM range(s) inside the guest's RAM) */
2588	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2589	{
2590	uint32_t off = addr - pVM->rem.s.aPhysReg[i].GCPhys;
2591	if (off < pVM->rem.s.aPhysReg[i].cb)
2592	{
2593	Log2(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].HCVirt + off));
2594	return (void *)(pVM->rem.s.aPhysReg[i].HCVirt + off);
2595	}
2596	}
2597	AssertMsg(addr < phys_ram_size, ("remR3GCPhys2HCVirt: unknown physical address %x\n", addr));
2598	Log2(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK)));
2599	return (void *)(pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2600	#else
2601	return phys_ram_base + addr;
2602	#endif
2603	}
2604
2605	/**
2606	* Convert GC physical address to HC virt
2607	*
2608	* @returns The HC virt address corresponding to addr.
2609	* @param env The cpu environment.
2610	* @param addr The physical address.
2611	*/
2612	target_ulong remR3HCVirt2GCPhys(void env, void addr)
2613	{
2614	#ifdef PGM_DYNAMIC_RAM_ALLOC
2615	PVM pVM = ((CPUState *)env)->pVM;
2616	RTHCUINTPTR HCVirt = (RTHCUINTPTR)addr;
2617	uint32_t idx = (HCVirt >> PGM_DYNAMIC_CHUNK_SHIFT);
2618	RTHCUINTPTR off;
2619	RTUINT i;
2620
2621	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1;
2622
2623	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1
2624	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2625	{
2626	Log2(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off));
2627	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off;
2628	}
2629
2630	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2;
2631	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2
2632	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2633	{
2634	Log2(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off));
2635	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off;
2636	}
2637
2638	/* Must be externally registered RAM/ROM range */
2639	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2640	{
2641	uint32_t off = HCVirt - pVM->rem.s.aPhysReg[i].HCVirt;
2642	if (off < pVM->rem.s.aPhysReg[i].cb)
2643	{
2644	Log2(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].GCPhys + off));
2645	return pVM->rem.s.aPhysReg[i].GCPhys + off;
2646	}
2647	}
2648	AssertReleaseMsgFailed(("No translation for physical address %VHv???\n", addr));
2649	return 0;
2650	#else
2651	return (target_ulong)addr - (target_ulong)phys_ram_base;
2652	#endif
2653	}
2654
2655	/**
2656	* Grows dynamically allocated guest RAM.
2657	* Will raise a fatal error if the operation fails.
2658	*
2659	* @param physaddr The physical address.
2660	*/
2661	void remR3GrowDynRange(unsigned long physaddr)
2662	{
2663	int rc;
2664	PVM pVM = cpu_single_env->pVM;
2665
2666	Log(("remR3GrowDynRange %VGp\n", physaddr));
2667	rc = PGM3PhysGrowRange(pVM, (RTGCPHYS)physaddr);
2668	if (VBOX_SUCCESS(rc))
2669	return;
2670
2671	LogRel(("\nUnable to allocate guest RAM chunk at %VGp\n", physaddr));
2672	cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %VGp\n", physaddr);
2673	AssertFatalFailed();
2674	}
2675
2676	/**
2677	* Notification about a successful MMR3PhysRomRegister() call.
2678	*
2679	* @param pVM VM handle.
2680	* @param GCPhys The physical address of the ROM.
2681	* @param cb The size of the ROM.
2682	* @param pvCopy Pointer to the ROM copy.
2683	*/
2684	REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy)
2685	{
2686	#ifdef PGM_DYNAMIC_RAM_ALLOC
2687	uint32_t i;
2688	#endif
2689	Log(("REMR3NotifyPhysRomRegister: GCPhys=%VGp cb=%d pvCopy=%p\n", GCPhys, cb, pvCopy));
2690	VM_ASSERT_EMT(pVM);
2691
2692	/*
2693	* Validate input - we trust the caller.
2694	*/
2695	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2696	Assert(cb);
2697	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2698	Assert(pvCopy);
2699	Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2700
2701	/*
2702	* Register the rom.
2703	*/
2704	#ifdef PGM_DYNAMIC_RAM_ALLOC
2705	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_ROM);
2706	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2707	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2708	{
2709	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2710	{
2711	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2712	pVM->rem.s.aPhysReg[i].cb = cb;
2713	break;
2714	}
2715	}
2716	if (i == pVM->rem.s.cPhysRegistrations)
2717	{
2718	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2719	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2720	pVM->rem.s.aPhysReg[i].cb = cb;
2721	pVM->rem.s.cPhysRegistrations++;
2722	}
2723	#else
2724	AssertRelease(phys_ram_base);
2725	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvCopy - (uintptr_t)phys_ram_base) \| IO_MEM_ROM);
2726	#endif
2727	Log2(("%.64Vhxd\n", (char *)pvCopy + cb - 64));
2728	}
2729
2730
2731	/**
2732	* Notification about a successful MMR3PhysRegister() call.
2733	*
2734	* @param pVM VM Handle.
2735	* @param GCPhys Start physical address.
2736	* @param cb The size of the range.
2737	*/
2738	REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2739	{
2740	LogFlow(("REMR3NotifyPhysReserve: GCPhys=%VGp cb=%d\n", GCPhys, cb));
2741	VM_ASSERT_EMT(pVM);
2742
2743	/*
2744	* Validate input - we trust the caller.
2745	*/
2746	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2747	Assert(cb);
2748	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2749
2750	/*
2751	* Unassigning the memory.
2752	*/
2753	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2754	}
2755
2756
2757	/**
2758	* Notification about a successful PGMR3HandlerPhysicalRegister() call.
2759	*
2760	* @param pVM VM Handle.
2761	* @param enmType Handler type.
2762	* @param GCPhys Handler range address.
2763	* @param cb Size of the handler range.
2764	* @param fHasHCHandler Set if the handler has a HC callback function.
2765	*
2766	* @remark MMR3PhysRomRegister assumes that this function will not apply the
2767	* Handler memory type to memory which has no HC handler.
2768	*/
2769	REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2770	{
2771	LogFlow(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d\n",
2772	enmType, GCPhys, cb, fHasHCHandler));
2773	VM_ASSERT_EMT(pVM);
2774	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2775	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2776
2777	if (pVM->rem.s.cHandlerNotifications)
2778	REMR3ReplayHandlerNotifications(pVM);
2779
2780	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2781	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2782	else if (fHasHCHandler)
2783	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2784	}
2785
2786
2787	/**
2788	* Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2789	*
2790	* @param pVM VM Handle.
2791	* @param enmType Handler type.
2792	* @param GCPhys Handler range address.
2793	* @param cb Size of the handler range.
2794	* @param fHasHCHandler Set if the handler has a HC callback function.
2795	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2796	*/
2797	REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2798	{
2799	LogFlow(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p RAM=%08x\n",
2800	enmType, GCPhys, cb, fHasHCHandler, pvHCPtr, MMR3PhysGetRamSize(pVM)));
2801	VM_ASSERT_EMT(pVM);
2802
2803	if (pVM->rem.s.cHandlerNotifications)
2804	REMR3ReplayHandlerNotifications(pVM);
2805
2806	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2807	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2808	else if (fHasHCHandler)
2809	{
2810	if (!pvHCPtr)
2811	{
2812	Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2813	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2814	}
2815	else
2816	{
2817	/* This is not prefect, but it'll do for PD monitoring... */
2818	Assert(cb == PAGE_SIZE);
2819	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2820	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2821	#ifdef PGM_DYNAMIC_RAM_ALLOC
2822	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2823	#else
2824	cpu_register_physical_memory(GCPhys, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2825	#endif
2826	}
2827	}
2828	}
2829
2830
2831	/**
2832	* Notification about a successful PGMR3HandlerPhysicalModify() call.
2833	*
2834	* @param pVM VM Handle.
2835	* @param enmType Handler type.
2836	* @param GCPhysOld Old handler range address.
2837	* @param GCPhysNew New handler range address.
2838	* @param cb Size of the handler range.
2839	* @param fHasHCHandler Set if the handler has a HC callback function.
2840	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2841	*/
2842	REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2843	{
2844	LogFlow(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%VGp GCPhysNew=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p\n",
2845	enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, pvHCPtr));
2846	VM_ASSERT_EMT(pVM);
2847	AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2848
2849	if (pVM->rem.s.cHandlerNotifications)
2850	REMR3ReplayHandlerNotifications(pVM);
2851
2852	if (fHasHCHandler)
2853	{
2854	/*
2855	* Reset the old page.
2856	*/
2857	if (!pvHCPtr)
2858	cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2859	else
2860	{
2861	/* This is not prefect, but it'll do for PD monitoring... */
2862	Assert(cb == PAGE_SIZE);
2863	Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2864	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2865	#ifdef PGM_DYNAMIC_RAM_ALLOC
2866	cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2867	#else
2868	cpu_register_physical_memory(GCPhysOld, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2869	#endif
2870	}
2871
2872	/*
2873	* Update the new page.
2874	*/
2875	Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2876	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2877	cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2878	}
2879	}
2880
2881
2882	/**
2883	* Checks if we're handling access to this page or not.
2884	*
2885	* @returns true if we're trapping access.
2886	* @returns false if we aren't.
2887	* @param pVM The VM handle.
2888	* @param GCPhys The physical address.
2889	*
2890	* @remark This function will only work correctly in VBOX_STRICT builds!
2891	*/
2892	REMDECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
2893	{
2894	#ifdef VBOX_STRICT
2895	if (pVM->rem.s.cHandlerNotifications)
2896	REMR3ReplayHandlerNotifications(pVM);
2897
2898	unsigned long off = get_phys_page_offset(GCPhys);
2899	return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
2900	\|\| (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
2901	\|\| (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
2902	#else
2903	return false;
2904	#endif
2905	}
2906
2907
2908	/**
2909	* Deals with a rare case in get_phys_addr_code where the code
2910	* is being monitored.
2911	*
2912	* It could also be an MMIO page, in which case we will raise a fatal error.
2913	*
2914	* @returns The physical address corresponding to addr.
2915	* @param env The cpu environment.
2916	* @param addr The virtual address.
2917	* @param pTLBEntry The TLB entry.
2918	*/
2919	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry)
2920	{
2921	PVM pVM = env->pVM;
2922	if ((pTLBEntry->address & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
2923	{
2924	target_ulong ret = pTLBEntry->addend + addr;
2925	AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%VGv address=%VGv addend=%VGp ret=%VGp\n",
2926	(RTGCPTR)addr, (RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, ret);
2927	return ret;
2928	}
2929	LogRel(("\nTrying to execute code with memory type address=%VGv addend=%VGp at %VGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
2930	"*** handlers\n",
2931	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
2932	DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
2933	LogRel(("*** mmio\n"));
2934	DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
2935	LogRel(("*** phys\n"));
2936	DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
2937	cpu_abort(env, "Trying to execute code with memory type address=%VGv addend=%VGp at %VGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
2938	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
2939	AssertFatalFailed();
2940	}
2941
2942	/**
2943	* Read guest RAM and ROM.
2944	*
2945	* @param pbSrcPhys The source address. Relative to guest RAM.
2946	* @param pvDst The destination address.
2947	* @param cb Number of bytes
2948	*/
2949	void remR3PhysReadBytes(uint8_t pbSrcPhys, void pvDst, unsigned cb)
2950	{
2951	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2952
2953	/*
2954	* Calc the physical address ('off') and check that it's within the RAM.
2955	* ROM is accessed this way, even if it's not part of the RAM.
2956	*/
2957	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2958	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2959	if (off < (uintptr_t)phys_ram_size)
2960	PGMPhysRead(cpu_single_env->pVM, (RTGCPHYS)off, pvDst, cb);
2961	else
2962	{
2963	/* ROM range outside physical RAM, HC address passed directly */
2964	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2965	memcpy(pvDst, pbSrcPhys, cb);
2966	}
2967	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2968	}
2969
2970	/** @todo r=bird: s/Byte/U8/ s/Word/U16/ s/Dword/U32/, see MMIO and other functions.
2971	* It could be an idea to inline these wrapper functions... */
2972
2973	/**
2974	* Read guest RAM and ROM.
2975	*
2976	* @param pbSrcPhys The source address. Relative to guest RAM.
2977	*/
2978	uint8_t remR3PhysReadUByte(uint8_t *pbSrcPhys)
2979	{
2980	uint8_t val;
2981
2982	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2983
2984	/*
2985	* Calc the physical address ('off') and check that it's within the RAM.
2986	* ROM is accessed this way, even if it's not part of the RAM.
2987	*/
2988	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2989	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2990	if (off < (uintptr_t)phys_ram_size)
2991	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
2992	else
2993	{
2994	/* ROM range outside physical RAM, HC address passed directly */
2995	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2996	val = *pbSrcPhys;
2997	}
2998	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2999	return val;
3000	}
3001
3002	/**
3003	* Read guest RAM and ROM.
3004	*
3005	* @param pbSrcPhys The source address. Relative to guest RAM.
3006	*/
3007	int8_t remR3PhysReadSByte(uint8_t *pbSrcPhys)
3008	{
3009	int8_t val;
3010
3011	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3012
3013	/*
3014	* Calc the physical address ('off') and check that it's within the RAM.
3015	* ROM is accessed this way, even if it's not part of the RAM.
3016	*/
3017	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3018	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3019	if (off < (uintptr_t)phys_ram_size)
3020	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3021	else
3022	{
3023	/* ROM range outside physical RAM, HC address passed directly */
3024	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3025	val = (int8_t )pbSrcPhys;
3026	}
3027	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3028	return val;
3029	}
3030
3031	/**
3032	* Read guest RAM and ROM.
3033	*
3034	* @param pbSrcPhys The source address. Relative to guest RAM.
3035	*/
3036	uint16_t remR3PhysReadUWord(uint8_t *pbSrcPhys)
3037	{
3038	uint16_t val;
3039
3040	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3041
3042	/*
3043	* Calc the physical address ('off') and check that it's within the RAM.
3044	* ROM is accessed this way, even if it's not part of the RAM.
3045	*/
3046	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3047	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3048	if (off < (uintptr_t)phys_ram_size)
3049	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3050	else
3051	{
3052	/* ROM range outside physical RAM, HC address passed directly */
3053	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3054	val = (uint16_t )pbSrcPhys;
3055	}
3056	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3057	return val;
3058	}
3059
3060	/**
3061	* Read guest RAM and ROM.
3062	*
3063	* @param pbSrcPhys The source address. Relative to guest RAM.
3064	*/
3065	int16_t remR3PhysReadSWord(uint8_t *pbSrcPhys)
3066	{
3067	int16_t val;
3068
3069	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3070
3071	/*
3072	* Calc the physical address ('off') and check that it's within the RAM.
3073	* ROM is accessed this way, even if it's not part of the RAM.
3074	*/
3075	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3076	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3077	if (off < (uintptr_t)phys_ram_size)
3078	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3079	else
3080	{
3081	/* ROM range outside physical RAM, HC address passed directly */
3082	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3083	val = (int16_t )pbSrcPhys;
3084	}
3085	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3086	return val;
3087	}
3088
3089	/**
3090	* Read guest RAM and ROM.
3091	*
3092	* @param pbSrcPhys The source address. Relative to guest RAM.
3093	*/
3094	uint32_t remR3PhysReadULong(uint8_t *pbSrcPhys)
3095	{
3096	uint32_t val;
3097
3098	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3099
3100	/*
3101	* Calc the physical address ('off') and check that it's within the RAM.
3102	* ROM is accessed this way, even if it's not part of the RAM.
3103	*/
3104	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3105	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3106	if (off < (uintptr_t)phys_ram_size)
3107	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3108	else
3109	{
3110	/* ROM range outside physical RAM, HC address passed directly */
3111	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3112	val = (uint32_t )pbSrcPhys;
3113	}
3114	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3115	return val;
3116	}
3117
3118	/**
3119	* Read guest RAM and ROM.
3120	*
3121	* @param pbSrcPhys The source address. Relative to guest RAM.
3122	*/
3123	int32_t remR3PhysReadSLong(uint8_t *pbSrcPhys)
3124	{
3125	int32_t val;
3126
3127	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3128
3129	/*
3130	* Calc the physical address ('off') and check that it's within the RAM.
3131	* ROM is accessed this way, even if it's not part of the RAM.
3132	*/
3133	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3134	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3135	if (off < (uintptr_t)phys_ram_size)
3136	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3137	else
3138	{
3139	/* ROM range outside physical RAM, HC address passed directly */
3140	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3141	val = (int32_t )pbSrcPhys;
3142	}
3143	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3144	return val;
3145	}
3146
3147	/**
3148	* Write guest RAM.
3149	*
3150	* @param pbDstPhys The destination address. Relative to guest RAM.
3151	* @param pvSrc The source address.
3152	* @param cb Number of bytes to write
3153	*/
3154	void remR3PhysWriteBytes(uint8_t pbDstPhys, const void pvSrc, unsigned cb)
3155	{
3156	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3157	/*
3158	* Calc the physical address ('off') and check that it's within the RAM.
3159	*/
3160	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3161	if (off < (uintptr_t)phys_ram_size)
3162	PGMPhysWrite(cpu_single_env->pVM, (RTGCPHYS)off, pvSrc, cb);
3163	else
3164	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, cb));
3165	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3166	}
3167
3168
3169	/**
3170	* Write guest RAM.
3171	*
3172	* @param pbDstPhys The destination address. Relative to guest RAM.
3173	* @param val Value
3174	*/
3175	void remR3PhysWriteByte(uint8_t *pbDstPhys, uint8_t val)
3176	{
3177	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3178	/*
3179	* Calc the physical address ('off') and check that it's within the RAM.
3180	*/
3181	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3182	if (off < (uintptr_t)phys_ram_size)
3183	PGMR3PhysWriteByte(cpu_single_env->pVM, (RTGCPHYS)off, val);
3184	else
3185	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 1));
3186	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3187	}
3188
3189	/**
3190	* Write guest RAM.
3191	*
3192	* @param pbDstPhys The destination address. Relative to guest RAM.
3193	* @param val Value
3194	*/
3195	void remR3PhysWriteWord(uint8_t *pbDstPhys, uint16_t val)
3196	{
3197	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3198	/*
3199	* Calc the physical address ('off') and check that it's within the RAM.
3200	*/
3201	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3202	if (off < (uintptr_t)phys_ram_size)
3203	PGMR3PhysWriteWord(cpu_single_env->pVM, (RTGCPHYS)off, val);
3204	else
3205	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 2));
3206	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3207	}
3208
3209	/**
3210	* Write guest RAM.
3211	*
3212	* @param pbDstPhys The destination address. Relative to guest RAM.
3213	* @param val Value
3214	*/
3215	void remR3PhysWriteDword(uint8_t *pbDstPhys, uint32_t val)
3216	{
3217	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3218	/*
3219	* Calc the physical address ('off') and check that it's within the RAM.
3220	*/
3221	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3222	if (off < (uintptr_t)phys_ram_size)
3223	PGMR3PhysWriteDword(cpu_single_env->pVM, (RTGCPHYS)off, val);
3224	else
3225	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 4));
3226	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3227	}
3228
3229
3230
3231	#undef LOG_GROUP
3232	#define LOG_GROUP LOG_GROUP_REM_MMIO
3233
3234	/** Read MMIO memory. */
3235	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3236	{
3237	uint32_t u32 = 0;
3238	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3239	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3240	Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32));
3241	return u32;
3242	}
3243
3244	/** Read MMIO memory. */
3245	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3246	{
3247	uint32_t u32 = 0;
3248	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3249	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3250	Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32));
3251	return u32;
3252	}
3253
3254	/** Read MMIO memory. */
3255	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3256	{
3257	uint32_t u32 = 0;
3258	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3259	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3260	Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32));
3261	return u32;
3262	}
3263
3264	/** Write to MMIO memory. */
3265	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3266	{
3267	Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3268	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3269	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3270	}
3271
3272	/** Write to MMIO memory. */
3273	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3274	{
3275	Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3276	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3277	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3278	}
3279
3280	/** Write to MMIO memory. */
3281	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3282	{
3283	Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3284	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3285	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3286	}
3287
3288
3289	#undef LOG_GROUP
3290	#define LOG_GROUP LOG_GROUP_REM_HANDLER
3291
3292	/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3293
3294	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3295	{
3296	Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys));
3297	uint8_t u8;
3298	PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3299	return u8;
3300	}
3301
3302	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3303	{
3304	Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys));
3305	uint16_t u16;
3306	PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3307	return u16;
3308	}
3309
3310	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3311	{
3312	Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys));
3313	uint32_t u32;
3314	PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3315	return u32;
3316	}
3317
3318	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3319	{
3320	Log2(("remR3HandlerWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3321	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3322	}
3323
3324	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3325	{
3326	Log2(("remR3HandlerWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3327	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3328	}
3329
3330	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3331	{
3332	Log2(("remR3HandlerWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3333	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3334	}
3335
3336	/* -+- disassembly -+- */
3337
3338	#undef LOG_GROUP
3339	#define LOG_GROUP LOG_GROUP_REM_DISAS
3340
3341
3342	/**
3343	* Enables or disables singled stepped disassembly.
3344	*
3345	* @returns VBox status code.
3346	* @param pVM VM handle.
3347	* @param fEnable To enable set this flag, to disable clear it.
3348	*/
3349	static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3350	{
3351	LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3352	VM_ASSERT_EMT(pVM);
3353
3354	if (fEnable)
3355	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
3356	else
3357	pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3358	return VINF_SUCCESS;
3359	}
3360
3361
3362	/**
3363	* Enables or disables singled stepped disassembly.
3364	*
3365	* @returns VBox status code.
3366	* @param pVM VM handle.
3367	* @param fEnable To enable set this flag, to disable clear it.
3368	*/
3369	REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3370	{
3371	PVMREQ pReq;
3372	int rc;
3373
3374	LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3375	if (VM_IS_EMT(pVM))
3376	return remR3DisasEnableStepping(pVM, fEnable);
3377
3378	rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3379	AssertRC(rc);
3380	if (VBOX_SUCCESS(rc))
3381	rc = pReq->iStatus;
3382	VMR3ReqFree(pReq);
3383	return rc;
3384	}
3385
3386
3387	#ifdef VBOX_WITH_DEBUGGER
3388	/**
3389	* External Debugger Command: .remstep [on\|off\|1\|0]
3390	*/
3391	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3392	{
3393	bool fEnable;
3394	int rc;
3395
3396	/* print status */
3397	if (cArgs == 0)
3398	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3399	pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3400
3401	/* convert the argument and change the mode. */
3402	rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3403	if (VBOX_FAILURE(rc))
3404	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3405	rc = REMR3DisasEnableStepping(pVM, fEnable);
3406	if (VBOX_FAILURE(rc))
3407	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3408	return rc;
3409	}
3410	#endif
3411
3412
3413	/**
3414	* Disassembles n instructions and prints them to the log.
3415	*
3416	* @returns Success indicator.
3417	* @param env Pointer to the recompiler CPU structure.
3418	* @param f32BitCode Indicates that whether or not the code should
3419	* be disassembled as 16 or 32 bit. If -1 the CS
3420	* selector will be inspected.
3421	* @param nrInstructions Nr of instructions to disassemble
3422	* @param pszPrefix
3423	* @remark not currently used for anything but ad-hoc debugging.
3424	*/
3425	bool remR3DisasBlock(CPUState env, int f32BitCode, int nrInstructions, char pszPrefix)
3426	{
3427	int i;
3428
3429	/*
3430	* Determin 16/32 bit mode.
3431	*/
3432	if (f32BitCode == -1)
3433	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3434
3435	/*
3436	* Convert cs:eip to host context address.
3437	* We don't care to much about cross page correctness presently.
3438	*/
3439	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3440	void *pvPC;
3441	if (f32BitCode && (env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3442	{
3443	/* convert eip to physical address. */
3444	int rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,
3445	GCPtrPC,
3446	env->cr[3],
3447	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE), /** @todo add longmode flag */
3448	&pvPC);
3449	if (VBOX_FAILURE(rc))
3450	{
3451	if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3452	return false;
3453	pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3454	+ (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3455	}
3456	}
3457	else
3458	{
3459	/* physical address */
3460	int rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions*16, &pvPC);
3461	if (VBOX_FAILURE(rc))
3462	return false;
3463	}
3464
3465	/*
3466	* Disassemble.
3467	*/
3468	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3469	DISCPUSTATE Cpu;
3470	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3471	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3472	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3473	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3474	//Cpu.dwUserData[2] = GCPtrPC;
3475
3476	for (i=0;i<nrInstructions;i++)
3477	{
3478	char szOutput[256];
3479	uint32_t cbOp;
3480	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3481	return false;
3482	if (pszPrefix)
3483	Log(("%s: %s", pszPrefix, szOutput));
3484	else
3485	Log(("%s", szOutput));
3486
3487	pvPC += cbOp;
3488	}
3489	return true;
3490	}
3491
3492
3493	/** @todo need to test the new code, using the old code in the mean while. */
3494	#define USE_OLD_DUMP_AND_DISASSEMBLY
3495
3496	/**
3497	* Disassembles one instruction and prints it to the log.
3498	*
3499	* @returns Success indicator.
3500	* @param env Pointer to the recompiler CPU structure.
3501	* @param f32BitCode Indicates that whether or not the code should
3502	* be disassembled as 16 or 32 bit. If -1 the CS
3503	* selector will be inspected.
3504	* @param pszPrefix
3505	*/
3506	bool remR3DisasInstr(CPUState env, int f32BitCode, char pszPrefix)
3507	{
3508	#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3509	PVM pVM = env->pVM;
3510
3511	/*
3512	* Determin 16/32 bit mode.
3513	*/
3514	if (f32BitCode == -1)
3515	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3516
3517	/*
3518	* Log registers
3519	*/
3520	if (LogIs2Enabled())
3521	{
3522	remR3StateUpdate(pVM);
3523	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3524	}
3525
3526	/*
3527	* Convert cs:eip to host context address.
3528	* We don't care to much about cross page correctness presently.
3529	*/
3530	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3531	void *pvPC;
3532	if ((env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3533	{
3534	/* convert eip to physical address. */
3535	int rc = PGMPhysGCPtr2HCPtrByGstCR3(pVM,
3536	GCPtrPC,
3537	env->cr[3],
3538	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE),
3539	&pvPC);
3540	if (VBOX_FAILURE(rc))
3541	{
3542	if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3543	return false;
3544	pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3545	+ (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3546	}
3547	}
3548	else
3549	{
3550
3551	/* physical address */
3552	int rc = PGMPhysGCPhys2HCPtr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3553	if (VBOX_FAILURE(rc))
3554	return false;
3555	}
3556
3557	/*
3558	* Disassemble.
3559	*/
3560	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3561	DISCPUSTATE Cpu;
3562	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3563	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3564	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3565	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3566	//Cpu.dwUserData[2] = GCPtrPC;
3567	char szOutput[256];
3568	uint32_t cbOp;
3569	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3570	return false;
3571
3572	if (!f32BitCode)
3573	{
3574	if (pszPrefix)
3575	Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3576	else
3577	Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3578	}
3579	else
3580	{
3581	if (pszPrefix)
3582	Log(("%s: %s", pszPrefix, szOutput));
3583	else
3584	Log(("%s", szOutput));
3585	}
3586	return true;
3587
3588	#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3589	PVM pVM = env->pVM;
3590	const bool fLog = LogIsEnabled();
3591	const bool fLog2 = LogIs2Enabled();
3592	int rc = VINF_SUCCESS;
3593
3594	/*
3595	* Don't bother if there ain't any log output to do.
3596	*/
3597	if (!fLog && !fLog2)
3598	return true;
3599
3600	/*
3601	* Update the state so DBGF reads the correct register values.
3602	*/
3603	remR3StateUpdate(pVM);
3604
3605	/*
3606	* Log registers if requested.
3607	*/
3608	if (!fLog2)
3609	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3610
3611	/*
3612	* Disassemble to log.
3613	*/
3614	if (fLog)
3615	rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3616
3617	return VBOX_SUCCESS(rc);
3618	#endif
3619	}
3620
3621
3622	/**
3623	* Disassemble recompiled code.
3624	*
3625	* @param phFileIgnored Ignored, logfile usually.
3626	* @param pvCode Pointer to the code block.
3627	* @param cb Size of the code block.
3628	*/
3629	void disas(FILE phFileIgnored, void pvCode, unsigned long cb)
3630	{
3631	if (LogIs2Enabled())
3632	{
3633	unsigned off = 0;
3634	char szOutput[256];
3635	DISCPUSTATE Cpu = {0};
3636	Cpu.mode = CPUMODE_32BIT;
3637
3638	RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3639	while (off < cb)
3640	{
3641	uint32_t cbInstr;
3642	if (DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput))
3643	RTLogPrintf("%s", szOutput);
3644	else
3645	{
3646	RTLogPrintf("disas error\n");
3647	cbInstr = 1;
3648	}
3649	off += cbInstr;
3650	}
3651	}
3652	NOREF(phFileIgnored);
3653	}
3654
3655
3656	/**
3657	* Disassemble guest code.
3658	*
3659	* @param phFileIgnored Ignored, logfile usually.
3660	* @param uCode The guest address of the code to disassemble. (flat?)
3661	* @param cb Number of bytes to disassemble.
3662	* @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3663	*/
3664	void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3665	{
3666	if (LogIs2Enabled())
3667	{
3668	PVM pVM = cpu_single_env->pVM;
3669
3670	/*
3671	* Update the state so DBGF reads the correct register values (flags).
3672	*/
3673	remR3StateUpdate(pVM);
3674
3675	/*
3676	* Do the disassembling.
3677	*/
3678	RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3679	RTSEL cs = cpu_single_env->segs[R_CS].selector;
3680	RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3681	for (;;)
3682	{
3683	char szBuf[256];
3684	size_t cbInstr;
3685	int rc = DBGFR3DisasInstrEx(pVM,
3686	cs,
3687	eip,
3688	0,
3689	szBuf, sizeof(szBuf),
3690	&cbInstr);
3691	if (VBOX_SUCCESS(rc))
3692	RTLogPrintf("%VGp %s\n", uCode, szBuf);
3693	else
3694	{
3695	RTLogPrintf("%VGp %04x:%VGp: %s\n", uCode, cs, eip, szBuf);
3696	cbInstr = 1;
3697	}
3698
3699	/* next */
3700	if (cb <= cbInstr)
3701	break;
3702	cb -= cbInstr;
3703	uCode += cbInstr;
3704	eip += cbInstr;
3705	}
3706	}
3707	NOREF(phFileIgnored);
3708	}
3709
3710
3711	/**
3712	* Looks up a guest symbol.
3713	*
3714	* @returns Pointer to symbol name. This is a static buffer.
3715	* @param orig_addr The address in question.
3716	*/
3717	const char *lookup_symbol(target_ulong orig_addr)
3718	{
3719	RTGCINTPTR off = 0;
3720	DBGFSYMBOL Sym;
3721	PVM pVM = cpu_single_env->pVM;
3722	int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3723	if (VBOX_SUCCESS(rc))
3724	{
3725	static char szSym[sizeof(Sym.szName) + 48];
3726	if (!off)
3727	RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3728	else if (off > 0)
3729	RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3730	else
3731	RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3732	return szSym;
3733	}
3734	return "<N/A>";
3735	}
3736
3737
3738	#undef LOG_GROUP
3739	#define LOG_GROUP LOG_GROUP_REM
3740
3741
3742	/* -+- FF notifications -+- */
3743
3744
3745	/**
3746	* Notification about a pending interrupt.
3747	*
3748	* @param pVM VM Handle.
3749	* @param u8Interrupt Interrupt
3750	* @thread The emulation thread.
3751	*/
3752	REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3753	{
3754	Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3755	pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3756	}
3757
3758	/**
3759	* Notification about a pending interrupt.
3760	*
3761	* @returns Pending interrupt or REM_NO_PENDING_IRQ
3762	* @param pVM VM Handle.
3763	* @thread The emulation thread.
3764	*/
3765	REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3766	{
3767	return pVM->rem.s.u32PendingInterrupt;
3768	}
3769
3770	/**
3771	* Notification about the interrupt FF being set.
3772	*
3773	* @param pVM VM Handle.
3774	* @thread The emulation thread.
3775	*/
3776	REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3777	{
3778	LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3779	(pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3780	if (pVM->rem.s.fInREM)
3781	{
3782	if (VM_IS_EMT(pVM))
3783	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3784	else
3785	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3786	}
3787	}
3788
3789
3790	/**
3791	* Notification about the interrupt FF being set.
3792	*
3793	* @param pVM VM Handle.
3794	* @thread The emulation thread.
3795	*/
3796	REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3797	{
3798	LogFlow(("REMR3NotifyInterruptClear:\n"));
3799	VM_ASSERT_EMT(pVM);
3800	if (pVM->rem.s.fInREM)
3801	cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3802	}
3803
3804
3805	/**
3806	* Notification about pending timer(s).
3807	*
3808	* @param pVM VM Handle.
3809	* @thread Any.
3810	*/
3811	REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3812	{
3813	#ifndef DEBUG_bird
3814	LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3815	#endif
3816	if (pVM->rem.s.fInREM)
3817	{
3818	if (VM_IS_EMT(pVM))
3819	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3820	else
3821	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3822	}
3823	}
3824
3825
3826	/**
3827	* Notification about pending DMA transfers.
3828	*
3829	* @param pVM VM Handle.
3830	* @thread Any.
3831	*/
3832	REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3833	{
3834	LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3835	if (pVM->rem.s.fInREM)
3836	{
3837	if (VM_IS_EMT(pVM))
3838	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3839	else
3840	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3841	}
3842	}
3843
3844
3845	/**
3846	* Notification about pending timer(s).
3847	*
3848	* @param pVM VM Handle.
3849	* @thread Any.
3850	*/
3851	REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3852	{
3853	LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3854	if (pVM->rem.s.fInREM)
3855	{
3856	if (VM_IS_EMT(pVM))
3857	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3858	else
3859	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3860	}
3861	}
3862
3863
3864	/**
3865	* Notification about pending FF set by an external thread.
3866	*
3867	* @param pVM VM handle.
3868	* @thread Any.
3869	*/
3870	REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3871	{
3872	LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3873	if (pVM->rem.s.fInREM)
3874	{
3875	if (VM_IS_EMT(pVM))
3876	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3877	else
3878	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3879	}
3880	}
3881
3882
3883	#ifdef VBOX_WITH_STATISTICS
3884	void remR3ProfileStart(int statcode)
3885	{
3886	STAMPROFILEADV *pStat;
3887	switch(statcode)
3888	{
3889	case STATS_EMULATE_SINGLE_INSTR:
3890	pStat = &gStatExecuteSingleInstr;
3891	break;
3892	case STATS_QEMU_COMPILATION:
3893	pStat = &gStatCompilationQEmu;
3894	break;
3895	case STATS_QEMU_RUN_EMULATED_CODE:
3896	pStat = &gStatRunCodeQEmu;
3897	break;
3898	case STATS_QEMU_TOTAL:
3899	pStat = &gStatTotalTimeQEmu;
3900	break;
3901	case STATS_QEMU_RUN_TIMERS:
3902	pStat = &gStatTimers;
3903	break;
3904	case STATS_TLB_LOOKUP:
3905	pStat= &gStatTBLookup;
3906	break;
3907	case STATS_IRQ_HANDLING:
3908	pStat= &gStatIRQ;
3909	break;
3910	case STATS_RAW_CHECK:
3911	pStat = &gStatRawCheck;
3912	break;
3913
3914	default:
3915	AssertMsgFailed(("unknown stat %d\n", statcode));
3916	return;
3917	}
3918	STAM_PROFILE_ADV_START(pStat, a);
3919	}
3920
3921
3922	void remR3ProfileStop(int statcode)
3923	{
3924	STAMPROFILEADV *pStat;
3925	switch(statcode)
3926	{
3927	case STATS_EMULATE_SINGLE_INSTR:
3928	pStat = &gStatExecuteSingleInstr;
3929	break;
3930	case STATS_QEMU_COMPILATION:
3931	pStat = &gStatCompilationQEmu;
3932	break;
3933	case STATS_QEMU_RUN_EMULATED_CODE:
3934	pStat = &gStatRunCodeQEmu;
3935	break;
3936	case STATS_QEMU_TOTAL:
3937	pStat = &gStatTotalTimeQEmu;
3938	break;
3939	case STATS_QEMU_RUN_TIMERS:
3940	pStat = &gStatTimers;
3941	break;
3942	case STATS_TLB_LOOKUP:
3943	pStat= &gStatTBLookup;
3944	break;
3945	case STATS_IRQ_HANDLING:
3946	pStat= &gStatIRQ;
3947	break;
3948	case STATS_RAW_CHECK:
3949	pStat = &gStatRawCheck;
3950	break;
3951	default:
3952	AssertMsgFailed(("unknown stat %d\n", statcode));
3953	return;
3954	}
3955	STAM_PROFILE_ADV_STOP(pStat, a);
3956	}
3957	#endif
3958
3959	/**
3960	* Raise an RC, force rem exit.
3961	*
3962	* @param pVM VM handle.
3963	* @param rc The rc.
3964	*/
3965	void remR3RaiseRC(PVM pVM, int rc)
3966	{
3967	Log(("remR3RaiseRC: rc=%Vrc\n", rc));
3968	Assert(pVM->rem.s.fInREM);
3969	VM_ASSERT_EMT(pVM);
3970	pVM->rem.s.rc = rc;
3971	cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
3972	}
3973
3974
3975	/* -+- timers -+- */
3976
3977	uint64_t cpu_get_tsc(CPUX86State *env)
3978	{
3979	return TMCpuTickGet(env->pVM);
3980	}
3981
3982
3983	/* -+- interrupts -+- */
3984
3985	void cpu_set_ferr(CPUX86State *env)
3986	{
3987	int rc = PDMIsaSetIrq(env->pVM, 13, 1);
3988	LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
3989	}
3990
3991	int cpu_get_pic_interrupt(CPUState *env)
3992	{
3993	uint8_t u8Interrupt;
3994	int rc;
3995
3996	/* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
3997	* In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
3998	* with the (a)pic.
3999	*/
4000	/** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
4001	/** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
4002	* if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4003	* remove this kludge. */
4004	if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4005	{
4006	rc = VINF_SUCCESS;
4007	Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
4008	u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4009	env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4010	}
4011	else
4012	rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
4013
4014	LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Vrc\n", u8Interrupt, rc));
4015	if (VBOX_SUCCESS(rc))
4016	{
4017	if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
4018	env->interrupt_request \|= CPU_INTERRUPT_HARD;
4019	return u8Interrupt;
4020	}
4021	return -1;
4022	}
4023
4024
4025	/* -+- local apic -+- */
4026
4027	void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4028	{
4029	int rc = PDMApicSetBase(env->pVM, val);
4030	LogFlow(("cpu_set_apic_base: val=%#llx rc=%Vrc\n", val, rc)); NOREF(rc);
4031	}
4032
4033	uint64_t cpu_get_apic_base(CPUX86State *env)
4034	{
4035	uint64_t u64;
4036	int rc = PDMApicGetBase(env->pVM, &u64);
4037	if (VBOX_SUCCESS(rc))
4038	{
4039	LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4040	return u64;
4041	}
4042	LogFlow(("cpu_get_apic_base: returns 0 (rc=%Vrc)\n", rc));
4043	return 0;
4044	}
4045
4046	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4047	{
4048	int rc = PDMApicSetTPR(env->pVM, val);
4049	LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Vrc\n", val, rc)); NOREF(rc);
4050	}
4051
4052	uint8_t cpu_get_apic_tpr(CPUX86State *env)
4053	{
4054	uint8_t u8;
4055	int rc = PDMApicGetTPR(env->pVM, &u8);
4056	if (VBOX_SUCCESS(rc))
4057	{
4058	LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4059	return u8;
4060	}
4061	LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Vrc)\n", rc));
4062	return 0;
4063	}
4064
4065
4066	/* -+- I/O Ports -+- */
4067
4068	#undef LOG_GROUP
4069	#define LOG_GROUP LOG_GROUP_REM_IOPORT
4070
4071	void cpu_outb(CPUState *env, int addr, int val)
4072	{
4073	if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4074	Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4075
4076	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4077	if (rc == VINF_SUCCESS)
4078	return;
4079	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4080	{
4081	Log(("cpu_outb: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4082	remR3RaiseRC(env->pVM, rc);
4083	return;
4084	}
4085	remAbort(rc, __FUNCTION__);
4086	}
4087
4088	void cpu_outw(CPUState *env, int addr, int val)
4089	{
4090	//Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4091	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4092	if (rc == VINF_SUCCESS)
4093	return;
4094	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4095	{
4096	Log(("cpu_outw: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4097	remR3RaiseRC(env->pVM, rc);
4098	return;
4099	}
4100	remAbort(rc, __FUNCTION__);
4101	}
4102
4103	void cpu_outl(CPUState *env, int addr, int val)
4104	{
4105	Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4106	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4107	if (rc == VINF_SUCCESS)
4108	return;
4109	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4110	{
4111	Log(("cpu_outl: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4112	remR3RaiseRC(env->pVM, rc);
4113	return;
4114	}
4115	remAbort(rc, __FUNCTION__);
4116	}
4117
4118	int cpu_inb(CPUState *env, int addr)
4119	{
4120	uint32_t u32 = 0;
4121	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4122	if (rc == VINF_SUCCESS)
4123	{
4124	if (/addr != 0x61 && /addr != 0x71)
4125	Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4126	return (int)u32;
4127	}
4128	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4129	{
4130	Log(("cpu_inb: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4131	remR3RaiseRC(env->pVM, rc);
4132	return (int)u32;
4133	}
4134	remAbort(rc, __FUNCTION__);
4135	return 0xff;
4136	}
4137
4138	int cpu_inw(CPUState *env, int addr)
4139	{
4140	uint32_t u32 = 0;
4141	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4142	if (rc == VINF_SUCCESS)
4143	{
4144	Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4145	return (int)u32;
4146	}
4147	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4148	{
4149	Log(("cpu_inw: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4150	remR3RaiseRC(env->pVM, rc);
4151	return (int)u32;
4152	}
4153	remAbort(rc, __FUNCTION__);
4154	return 0xffff;
4155	}
4156
4157	int cpu_inl(CPUState *env, int addr)
4158	{
4159	uint32_t u32 = 0;
4160	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4161	if (rc == VINF_SUCCESS)
4162	{
4163	//if (addr==0x01f0 && u32 == 0x6b6d)
4164	// loglevel = ~0;
4165	Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4166	return (int)u32;
4167	}
4168	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4169	{
4170	Log(("cpu_inl: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4171	remR3RaiseRC(env->pVM, rc);
4172	return (int)u32;
4173	}
4174	remAbort(rc, __FUNCTION__);
4175	return 0xffffffff;
4176	}
4177
4178	#undef LOG_GROUP
4179	#define LOG_GROUP LOG_GROUP_REM
4180
4181
4182	/* -+- helpers and misc other interfaces -+- */
4183
4184	/**
4185	* Perform the CPUID instruction.
4186	*
4187	* ASMCpuId cannot be invoked from some source files where this is used because of global
4188	* register allocations.
4189	*
4190	* @param env Pointer to the recompiler CPU structure.
4191	* @param uOperator CPUID operation (eax).
4192	* @param pvEAX Where to store eax.
4193	* @param pvEBX Where to store ebx.
4194	* @param pvECX Where to store ecx.
4195	* @param pvEDX Where to store edx.
4196	*/
4197	void remR3CpuId(CPUState env, unsigned uOperator, void pvEAX, void pvEBX, void pvECX, void *pvEDX)
4198	{
4199	CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t )pvEAX, (uint32_t )pvEBX, (uint32_t )pvECX, (uint32_t )pvEDX);
4200	}
4201
4202
4203	#if 0 /* not used */
4204	/**
4205	* Interface for qemu hardware to report back fatal errors.
4206	*/
4207	void hw_error(const char *pszFormat, ...)
4208	{
4209	/*
4210	* Bitch about it.
4211	*/
4212	/** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4213	* this in my Odin32 tree at home! */
4214	va_list args;
4215	va_start(args, pszFormat);
4216	RTLogPrintf("fatal error in virtual hardware:");
4217	RTLogPrintfV(pszFormat, args);
4218	va_end(args);
4219	AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4220
4221	/*
4222	* If we're in REM context we'll sync back the state before 'jumping' to
4223	* the EMs failure handling.
4224	*/
4225	PVM pVM = cpu_single_env->pVM;
4226	if (pVM->rem.s.fInREM)
4227	REMR3StateBack(pVM);
4228	EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4229	AssertMsgFailed(("EMR3FatalError returned!\n"));
4230	}
4231	#endif
4232
4233	/**
4234	* Interface for the qemu cpu to report unhandled situation
4235	* raising a fatal VM error.
4236	*/
4237	void cpu_abort(CPUState env, const char pszFormat, ...)
4238	{
4239	/*
4240	* Bitch about it.
4241	*/
4242	RTLogFlags(NULL, "nodisabled nobuffered");
4243	va_list args;
4244	va_start(args, pszFormat);
4245	RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4246	va_end(args);
4247	va_start(args, pszFormat);
4248	AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4249	va_end(args);
4250
4251	/*
4252	* If we're in REM context we'll sync back the state before 'jumping' to
4253	* the EMs failure handling.
4254	*/
4255	PVM pVM = cpu_single_env->pVM;
4256	if (pVM->rem.s.fInREM)
4257	REMR3StateBack(pVM);
4258	EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4259	AssertMsgFailed(("EMR3FatalError returned!\n"));
4260	}
4261
4262
4263	/**
4264	* Aborts the VM.
4265	*
4266	* @param rc VBox error code.
4267	* @param pszTip Hint about why/when this happend.
4268	*/
4269	static void remAbort(int rc, const char *pszTip)
4270	{
4271	/*
4272	* Bitch about it.
4273	*/
4274	RTLogPrintf("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip);
4275	AssertReleaseMsgFailed(("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip));
4276
4277	/*
4278	* Jump back to where we entered the recompiler.
4279	*/
4280	PVM pVM = cpu_single_env->pVM;
4281	if (pVM->rem.s.fInREM)
4282	REMR3StateBack(pVM);
4283	EMR3FatalError(pVM, rc);
4284	AssertMsgFailed(("EMR3FatalError returned!\n"));
4285	}
4286
4287
4288	/**
4289	* Dumps a linux system call.
4290	* @param pVM VM handle.
4291	*/
4292	void remR3DumpLnxSyscall(PVM pVM)
4293	{
4294	static const char *apsz[] =
4295	{
4296	"sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4297	"sys_exit",
4298	"sys_fork",
4299	"sys_read",
4300	"sys_write",
4301	"sys_open", /* 5 */
4302	"sys_close",
4303	"sys_waitpid",
4304	"sys_creat",
4305	"sys_link",
4306	"sys_unlink", /* 10 */
4307	"sys_execve",
4308	"sys_chdir",
4309	"sys_time",
4310	"sys_mknod",
4311	"sys_chmod", /* 15 */
4312	"sys_lchown16",
4313	"sys_ni_syscall", /* old break syscall holder */
4314	"sys_stat",
4315	"sys_lseek",
4316	"sys_getpid", /* 20 */
4317	"sys_mount",
4318	"sys_oldumount",
4319	"sys_setuid16",
4320	"sys_getuid16",
4321	"sys_stime", /* 25 */
4322	"sys_ptrace",
4323	"sys_alarm",
4324	"sys_fstat",
4325	"sys_pause",
4326	"sys_utime", /* 30 */
4327	"sys_ni_syscall", /* old stty syscall holder */
4328	"sys_ni_syscall", /* old gtty syscall holder */
4329	"sys_access",
4330	"sys_nice",
4331	"sys_ni_syscall", /* 35 - old ftime syscall holder */
4332	"sys_sync",
4333	"sys_kill",
4334	"sys_rename",
4335	"sys_mkdir",
4336	"sys_rmdir", /* 40 */
4337	"sys_dup",
4338	"sys_pipe",
4339	"sys_times",
4340	"sys_ni_syscall", /* old prof syscall holder */
4341	"sys_brk", /* 45 */
4342	"sys_setgid16",
4343	"sys_getgid16",
4344	"sys_signal",
4345	"sys_geteuid16",
4346	"sys_getegid16", /* 50 */
4347	"sys_acct",
4348	"sys_umount", /* recycled never used phys() */
4349	"sys_ni_syscall", /* old lock syscall holder */
4350	"sys_ioctl",
4351	"sys_fcntl", /* 55 */
4352	"sys_ni_syscall", /* old mpx syscall holder */
4353	"sys_setpgid",
4354	"sys_ni_syscall", /* old ulimit syscall holder */
4355	"sys_olduname",
4356	"sys_umask", /* 60 */
4357	"sys_chroot",
4358	"sys_ustat",
4359	"sys_dup2",
4360	"sys_getppid",
4361	"sys_getpgrp", /* 65 */
4362	"sys_setsid",
4363	"sys_sigaction",
4364	"sys_sgetmask",
4365	"sys_ssetmask",
4366	"sys_setreuid16", /* 70 */
4367	"sys_setregid16",
4368	"sys_sigsuspend",
4369	"sys_sigpending",
4370	"sys_sethostname",
4371	"sys_setrlimit", /* 75 */
4372	"sys_old_getrlimit",
4373	"sys_getrusage",
4374	"sys_gettimeofday",
4375	"sys_settimeofday",
4376	"sys_getgroups16", /* 80 */
4377	"sys_setgroups16",
4378	"old_select",
4379	"sys_symlink",
4380	"sys_lstat",
4381	"sys_readlink", /* 85 */
4382	"sys_uselib",
4383	"sys_swapon",
4384	"sys_reboot",
4385	"old_readdir",
4386	"old_mmap", /* 90 */
4387	"sys_munmap",
4388	"sys_truncate",
4389	"sys_ftruncate",
4390	"sys_fchmod",
4391	"sys_fchown16", /* 95 */
4392	"sys_getpriority",
4393	"sys_setpriority",
4394	"sys_ni_syscall", /* old profil syscall holder */
4395	"sys_statfs",
4396	"sys_fstatfs", /* 100 */
4397	"sys_ioperm",
4398	"sys_socketcall",
4399	"sys_syslog",
4400	"sys_setitimer",
4401	"sys_getitimer", /* 105 */
4402	"sys_newstat",
4403	"sys_newlstat",
4404	"sys_newfstat",
4405	"sys_uname",
4406	"sys_iopl", /* 110 */
4407	"sys_vhangup",
4408	"sys_ni_syscall", /* old "idle" system call */
4409	"sys_vm86old",
4410	"sys_wait4",
4411	"sys_swapoff", /* 115 */
4412	"sys_sysinfo",
4413	"sys_ipc",
4414	"sys_fsync",
4415	"sys_sigreturn",
4416	"sys_clone", /* 120 */
4417	"sys_setdomainname",
4418	"sys_newuname",
4419	"sys_modify_ldt",
4420	"sys_adjtimex",
4421	"sys_mprotect", /* 125 */
4422	"sys_sigprocmask",
4423	"sys_ni_syscall", /* old "create_module" */
4424	"sys_init_module",
4425	"sys_delete_module",
4426	"sys_ni_syscall", /* 130: old "get_kernel_syms" */
4427	"sys_quotactl",
4428	"sys_getpgid",
4429	"sys_fchdir",
4430	"sys_bdflush",
4431	"sys_sysfs", /* 135 */
4432	"sys_personality",
4433	"sys_ni_syscall", /* reserved for afs_syscall */
4434	"sys_setfsuid16",
4435	"sys_setfsgid16",
4436	"sys_llseek", /* 140 */
4437	"sys_getdents",
4438	"sys_select",
4439	"sys_flock",
4440	"sys_msync",
4441	"sys_readv", /* 145 */
4442	"sys_writev",
4443	"sys_getsid",
4444	"sys_fdatasync",
4445	"sys_sysctl",
4446	"sys_mlock", /* 150 */
4447	"sys_munlock",
4448	"sys_mlockall",
4449	"sys_munlockall",
4450	"sys_sched_setparam",
4451	"sys_sched_getparam", /* 155 */
4452	"sys_sched_setscheduler",
4453	"sys_sched_getscheduler",
4454	"sys_sched_yield",
4455	"sys_sched_get_priority_max",
4456	"sys_sched_get_priority_min", /* 160 */
4457	"sys_sched_rr_get_interval",
4458	"sys_nanosleep",
4459	"sys_mremap",
4460	"sys_setresuid16",
4461	"sys_getresuid16", /* 165 */
4462	"sys_vm86",
4463	"sys_ni_syscall", /* Old sys_query_module */
4464	"sys_poll",
4465	"sys_nfsservctl",
4466	"sys_setresgid16", /* 170 */
4467	"sys_getresgid16",
4468	"sys_prctl",
4469	"sys_rt_sigreturn",
4470	"sys_rt_sigaction",
4471	"sys_rt_sigprocmask", /* 175 */
4472	"sys_rt_sigpending",
4473	"sys_rt_sigtimedwait",
4474	"sys_rt_sigqueueinfo",
4475	"sys_rt_sigsuspend",
4476	"sys_pread64", /* 180 */
4477	"sys_pwrite64",
4478	"sys_chown16",
4479	"sys_getcwd",
4480	"sys_capget",
4481	"sys_capset", /* 185 */
4482	"sys_sigaltstack",
4483	"sys_sendfile",
4484	"sys_ni_syscall", /* reserved for streams1 */
4485	"sys_ni_syscall", /* reserved for streams2 */
4486	"sys_vfork", /* 190 */
4487	"sys_getrlimit",
4488	"sys_mmap2",
4489	"sys_truncate64",
4490	"sys_ftruncate64",
4491	"sys_stat64", /* 195 */
4492	"sys_lstat64",
4493	"sys_fstat64",
4494	"sys_lchown",
4495	"sys_getuid",
4496	"sys_getgid", /* 200 */
4497	"sys_geteuid",
4498	"sys_getegid",
4499	"sys_setreuid",
4500	"sys_setregid",
4501	"sys_getgroups", /* 205 */
4502	"sys_setgroups",
4503	"sys_fchown",
4504	"sys_setresuid",
4505	"sys_getresuid",
4506	"sys_setresgid", /* 210 */
4507	"sys_getresgid",
4508	"sys_chown",
4509	"sys_setuid",
4510	"sys_setgid",
4511	"sys_setfsuid", /* 215 */
4512	"sys_setfsgid",
4513	"sys_pivot_root",
4514	"sys_mincore",
4515	"sys_madvise",
4516	"sys_getdents64", /* 220 */
4517	"sys_fcntl64",
4518	"sys_ni_syscall", /* reserved for TUX */
4519	"sys_ni_syscall",
4520	"sys_gettid",
4521	"sys_readahead", /* 225 */
4522	"sys_setxattr",
4523	"sys_lsetxattr",
4524	"sys_fsetxattr",
4525	"sys_getxattr",
4526	"sys_lgetxattr", /* 230 */
4527	"sys_fgetxattr",
4528	"sys_listxattr",
4529	"sys_llistxattr",
4530	"sys_flistxattr",
4531	"sys_removexattr", /* 235 */
4532	"sys_lremovexattr",
4533	"sys_fremovexattr",
4534	"sys_tkill",
4535	"sys_sendfile64",
4536	"sys_futex", /* 240 */
4537	"sys_sched_setaffinity",
4538	"sys_sched_getaffinity",
4539	"sys_set_thread_area",
4540	"sys_get_thread_area",
4541	"sys_io_setup", /* 245 */
4542	"sys_io_destroy",
4543	"sys_io_getevents",
4544	"sys_io_submit",
4545	"sys_io_cancel",
4546	"sys_fadvise64", /* 250 */
4547	"sys_ni_syscall",
4548	"sys_exit_group",
4549	"sys_lookup_dcookie",
4550	"sys_epoll_create",
4551	"sys_epoll_ctl", /* 255 */
4552	"sys_epoll_wait",
4553	"sys_remap_file_pages",
4554	"sys_set_tid_address",
4555	"sys_timer_create",
4556	"sys_timer_settime", /* 260 */
4557	"sys_timer_gettime",
4558	"sys_timer_getoverrun",
4559	"sys_timer_delete",
4560	"sys_clock_settime",
4561	"sys_clock_gettime", /* 265 */
4562	"sys_clock_getres",
4563	"sys_clock_nanosleep",
4564	"sys_statfs64",
4565	"sys_fstatfs64",
4566	"sys_tgkill", /* 270 */
4567	"sys_utimes",
4568	"sys_fadvise64_64",
4569	"sys_ni_syscall" /* sys_vserver */
4570	};
4571
4572	uint32_t uEAX = CPUMGetGuestEAX(pVM);
4573	switch (uEAX)
4574	{
4575	default:
4576	if (uEAX < ELEMENTS(apsz))
4577	Log(("REM: linux syscall %3d: %s (eip=%VGv ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4578	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4579	CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4580	else
4581	Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4582	break;
4583
4584	}
4585	}
4586
4587
4588	/**
4589	* Dumps an OpenBSD system call.
4590	* @param pVM VM handle.
4591	*/
4592	void remR3DumpOBsdSyscall(PVM pVM)
4593	{
4594	static const char *apsz[] =
4595	{
4596	"SYS_syscall", //0
4597	"SYS_exit", //1
4598	"SYS_fork", //2
4599	"SYS_read", //3
4600	"SYS_write", //4
4601	"SYS_open", //5
4602	"SYS_close", //6
4603	"SYS_wait4", //7
4604	"SYS_8",
4605	"SYS_link", //9
4606	"SYS_unlink", //10
4607	"SYS_11",
4608	"SYS_chdir", //12
4609	"SYS_fchdir", //13
4610	"SYS_mknod", //14
4611	"SYS_chmod", //15
4612	"SYS_chown", //16
4613	"SYS_break", //17
4614	"SYS_18",
4615	"SYS_19",
4616	"SYS_getpid", //20
4617	"SYS_mount", //21
4618	"SYS_unmount", //22
4619	"SYS_setuid", //23
4620	"SYS_getuid", //24
4621	"SYS_geteuid", //25
4622	"SYS_ptrace", //26
4623	"SYS_recvmsg", //27
4624	"SYS_sendmsg", //28
4625	"SYS_recvfrom", //29
4626	"SYS_accept", //30
4627	"SYS_getpeername", //31
4628	"SYS_getsockname", //32
4629	"SYS_access", //33
4630	"SYS_chflags", //34
4631	"SYS_fchflags", //35
4632	"SYS_sync", //36
4633	"SYS_kill", //37
4634	"SYS_38",
4635	"SYS_getppid", //39
4636	"SYS_40",
4637	"SYS_dup", //41
4638	"SYS_opipe", //42
4639	"SYS_getegid", //43
4640	"SYS_profil", //44
4641	"SYS_ktrace", //45
4642	"SYS_sigaction", //46
4643	"SYS_getgid", //47
4644	"SYS_sigprocmask", //48
4645	"SYS_getlogin", //49
4646	"SYS_setlogin", //50
4647	"SYS_acct", //51
4648	"SYS_sigpending", //52
4649	"SYS_osigaltstack", //53
4650	"SYS_ioctl", //54
4651	"SYS_reboot", //55
4652	"SYS_revoke", //56
4653	"SYS_symlink", //57
4654	"SYS_readlink", //58
4655	"SYS_execve", //59
4656	"SYS_umask", //60
4657	"SYS_chroot", //61
4658	"SYS_62",
4659	"SYS_63",
4660	"SYS_64",
4661	"SYS_65",
4662	"SYS_vfork", //66
4663	"SYS_67",
4664	"SYS_68",
4665	"SYS_sbrk", //69
4666	"SYS_sstk", //70
4667	"SYS_61",
4668	"SYS_vadvise", //72
4669	"SYS_munmap", //73
4670	"SYS_mprotect", //74
4671	"SYS_madvise", //75
4672	"SYS_76",
4673	"SYS_77",
4674	"SYS_mincore", //78
4675	"SYS_getgroups", //79
4676	"SYS_setgroups", //80
4677	"SYS_getpgrp", //81
4678	"SYS_setpgid", //82
4679	"SYS_setitimer", //83
4680	"SYS_84",
4681	"SYS_85",
4682	"SYS_getitimer", //86
4683	"SYS_87",
4684	"SYS_88",
4685	"SYS_89",
4686	"SYS_dup2", //90
4687	"SYS_91",
4688	"SYS_fcntl", //92
4689	"SYS_select", //93
4690	"SYS_94",
4691	"SYS_fsync", //95
4692	"SYS_setpriority", //96
4693	"SYS_socket", //97
4694	"SYS_connect", //98
4695	"SYS_99",
4696	"SYS_getpriority", //100
4697	"SYS_101",
4698	"SYS_102",
4699	"SYS_sigreturn", //103
4700	"SYS_bind", //104
4701	"SYS_setsockopt", //105
4702	"SYS_listen", //106
4703	"SYS_107",
4704	"SYS_108",
4705	"SYS_109",
4706	"SYS_110",
4707	"SYS_sigsuspend", //111
4708	"SYS_112",
4709	"SYS_113",
4710	"SYS_114",
4711	"SYS_115",
4712	"SYS_gettimeofday", //116
4713	"SYS_getrusage", //117
4714	"SYS_getsockopt", //118
4715	"SYS_119",
4716	"SYS_readv", //120
4717	"SYS_writev", //121
4718	"SYS_settimeofday", //122
4719	"SYS_fchown", //123
4720	"SYS_fchmod", //124
4721	"SYS_125",
4722	"SYS_setreuid", //126
4723	"SYS_setregid", //127
4724	"SYS_rename", //128
4725	"SYS_129",
4726	"SYS_130",
4727	"SYS_flock", //131
4728	"SYS_mkfifo", //132
4729	"SYS_sendto", //133
4730	"SYS_shutdown", //134
4731	"SYS_socketpair", //135
4732	"SYS_mkdir", //136
4733	"SYS_rmdir", //137
4734	"SYS_utimes", //138
4735	"SYS_139",
4736	"SYS_adjtime", //140
4737	"SYS_141",
4738	"SYS_142",
4739	"SYS_143",
4740	"SYS_144",
4741	"SYS_145",
4742	"SYS_146",
4743	"SYS_setsid", //147
4744	"SYS_quotactl", //148
4745	"SYS_149",
4746	"SYS_150",
4747	"SYS_151",
4748	"SYS_152",
4749	"SYS_153",
4750	"SYS_154",
4751	"SYS_nfssvc", //155
4752	"SYS_156",
4753	"SYS_157",
4754	"SYS_158",
4755	"SYS_159",
4756	"SYS_160",
4757	"SYS_getfh", //161
4758	"SYS_162",
4759	"SYS_163",
4760	"SYS_164",
4761	"SYS_sysarch", //165
4762	"SYS_166",
4763	"SYS_167",
4764	"SYS_168",
4765	"SYS_169",
4766	"SYS_170",
4767	"SYS_171",
4768	"SYS_172",
4769	"SYS_pread", //173
4770	"SYS_pwrite", //174
4771	"SYS_175",
4772	"SYS_176",
4773	"SYS_177",
4774	"SYS_178",
4775	"SYS_179",
4776	"SYS_180",
4777	"SYS_setgid", //181
4778	"SYS_setegid", //182
4779	"SYS_seteuid", //183
4780	"SYS_lfs_bmapv", //184
4781	"SYS_lfs_markv", //185
4782	"SYS_lfs_segclean", //186
4783	"SYS_lfs_segwait", //187
4784	"SYS_188",
4785	"SYS_189",
4786	"SYS_190",
4787	"SYS_pathconf", //191
4788	"SYS_fpathconf", //192
4789	"SYS_swapctl", //193
4790	"SYS_getrlimit", //194
4791	"SYS_setrlimit", //195
4792	"SYS_getdirentries", //196
4793	"SYS_mmap", //197
4794	"SYS___syscall", //198
4795	"SYS_lseek", //199
4796	"SYS_truncate", //200
4797	"SYS_ftruncate", //201
4798	"SYS___sysctl", //202
4799	"SYS_mlock", //203
4800	"SYS_munlock", //204
4801	"SYS_205",
4802	"SYS_futimes", //206
4803	"SYS_getpgid", //207
4804	"SYS_xfspioctl", //208
4805	"SYS_209",
4806	"SYS_210",
4807	"SYS_211",
4808	"SYS_212",
4809	"SYS_213",
4810	"SYS_214",
4811	"SYS_215",
4812	"SYS_216",
4813	"SYS_217",
4814	"SYS_218",
4815	"SYS_219",
4816	"SYS_220",
4817	"SYS_semget", //221
4818	"SYS_222",
4819	"SYS_223",
4820	"SYS_224",
4821	"SYS_msgget", //225
4822	"SYS_msgsnd", //226
4823	"SYS_msgrcv", //227
4824	"SYS_shmat", //228
4825	"SYS_229",
4826	"SYS_shmdt", //230
4827	"SYS_231",
4828	"SYS_clock_gettime", //232
4829	"SYS_clock_settime", //233
4830	"SYS_clock_getres", //234
4831	"SYS_235",
4832	"SYS_236",
4833	"SYS_237",
4834	"SYS_238",
4835	"SYS_239",
4836	"SYS_nanosleep", //240
4837	"SYS_241",
4838	"SYS_242",
4839	"SYS_243",
4840	"SYS_244",
4841	"SYS_245",
4842	"SYS_246",
4843	"SYS_247",
4844	"SYS_248",
4845	"SYS_249",
4846	"SYS_minherit", //250
4847	"SYS_rfork", //251
4848	"SYS_poll", //252
4849	"SYS_issetugid", //253
4850	"SYS_lchown", //254
4851	"SYS_getsid", //255
4852	"SYS_msync", //256
4853	"SYS_257",
4854	"SYS_258",
4855	"SYS_259",
4856	"SYS_getfsstat", //260
4857	"SYS_statfs", //261
4858	"SYS_fstatfs", //262
4859	"SYS_pipe", //263
4860	"SYS_fhopen", //264
4861	"SYS_265",
4862	"SYS_fhstatfs", //266
4863	"SYS_preadv", //267
4864	"SYS_pwritev", //268
4865	"SYS_kqueue", //269
4866	"SYS_kevent", //270
4867	"SYS_mlockall", //271
4868	"SYS_munlockall", //272
4869	"SYS_getpeereid", //273
4870	"SYS_274",
4871	"SYS_275",
4872	"SYS_276",
4873	"SYS_277",
4874	"SYS_278",
4875	"SYS_279",
4876	"SYS_280",
4877	"SYS_getresuid", //281
4878	"SYS_setresuid", //282
4879	"SYS_getresgid", //283
4880	"SYS_setresgid", //284
4881	"SYS_285",
4882	"SYS_mquery", //286
4883	"SYS_closefrom", //287
4884	"SYS_sigaltstack", //288
4885	"SYS_shmget", //289
4886	"SYS_semop", //290
4887	"SYS_stat", //291
4888	"SYS_fstat", //292
4889	"SYS_lstat", //293
4890	"SYS_fhstat", //294
4891	"SYS___semctl", //295
4892	"SYS_shmctl", //296
4893	"SYS_msgctl", //297
4894	"SYS_MAXSYSCALL", //298
4895	//299
4896	//300
4897	};
4898	uint32_t uEAX;
4899	#ifndef DEBUG_bird
4900	if (!LogIsEnabled())
4901	return;
4902	#endif
4903	uEAX = CPUMGetGuestEAX(pVM);
4904	switch (uEAX)
4905	{
4906	default:
4907	if (uEAX < ELEMENTS(apsz))
4908	{
4909	uint32_t au32Args[8] = {0};
4910	PGMPhysReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4911	RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4912	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4913	au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4914	}
4915	else
4916	RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4917	break;
4918	}
4919	}

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source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 2126

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