VirtualBox

source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 5436

Last change on this file since 5436 was 5369, checked in by vboxsync, 17 years ago

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1/* $Id: VBoxRecompiler.c 5369 2007-10-18 09:58:21Z vboxsync $ */
2/** @file
3 * VBox Recompiler - QEMU.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_REM
23#include "vl.h"
24#include "exec-all.h"
25
26#include <VBox/rem.h>
27#include <VBox/vmapi.h>
28#include <VBox/tm.h>
29#include <VBox/ssm.h>
30#include <VBox/em.h>
31#include <VBox/trpm.h>
32#include <VBox/iom.h>
33#include <VBox/mm.h>
34#include <VBox/pgm.h>
35#include <VBox/pdm.h>
36#include <VBox/dbgf.h>
37#include <VBox/dbg.h>
38#include <VBox/hwaccm.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include "REMInternal.h"
42#include <VBox/vm.h>
43#include <VBox/param.h>
44#include <VBox/err.h>
45
46#include <VBox/log.h>
47#include <iprt/semaphore.h>
48#include <iprt/asm.h>
49#include <iprt/assert.h>
50#include <iprt/thread.h>
51#include <iprt/string.h>
52
53/* Don't wanna include everything. */
54extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
55extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
56extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
57extern void tlb_flush_page(CPUX86State *env, uint32_t addr);
58extern void tlb_flush(CPUState *env, int flush_global);
59extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
60extern void sync_ldtr(CPUX86State *env1, int selector);
61extern int sync_tr(CPUX86State *env1, int selector);
62
63#ifdef VBOX_STRICT
64unsigned long get_phys_page_offset(target_ulong addr);
65#endif
66
67
68/*******************************************************************************
69* Defined Constants And Macros *
70*******************************************************************************/
71
72/** Copy 80-bit fpu register at pSrc to pDst.
73 * This is probably faster than *calling* memcpy.
74 */
75#define REM_COPY_FPU_REG(pDst, pSrc) \
76 do { *(PX86FPUMMX)(pDst) = *(const X86FPUMMX *)(pSrc); } while (0)
77
78
79/*******************************************************************************
80* Internal Functions *
81*******************************************************************************/
82static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
83static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
84static void remR3StateUpdate(PVM pVM);
85
86static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
87static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
88static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
89static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
90static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
91static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
92
93static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
94static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
95static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
96static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
97static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
98static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
99
100
101/*******************************************************************************
102* Global Variables *
103*******************************************************************************/
104
105/** @todo Move stats to REM::s some rainy day we have nothing do to. */
106#ifdef VBOX_WITH_STATISTICS
107static STAMPROFILEADV gStatExecuteSingleInstr;
108static STAMPROFILEADV gStatCompilationQEmu;
109static STAMPROFILEADV gStatRunCodeQEmu;
110static STAMPROFILEADV gStatTotalTimeQEmu;
111static STAMPROFILEADV gStatTimers;
112static STAMPROFILEADV gStatTBLookup;
113static STAMPROFILEADV gStatIRQ;
114static STAMPROFILEADV gStatRawCheck;
115static STAMPROFILEADV gStatMemRead;
116static STAMPROFILEADV gStatMemWrite;
117static STAMPROFILE gStatGCPhys2HCVirt;
118static STAMPROFILE gStatHCVirt2GCPhys;
119static STAMCOUNTER gStatCpuGetTSC;
120static STAMCOUNTER gStatRefuseTFInhibit;
121static STAMCOUNTER gStatRefuseVM86;
122static STAMCOUNTER gStatRefusePaging;
123static STAMCOUNTER gStatRefusePAE;
124static STAMCOUNTER gStatRefuseIOPLNot0;
125static STAMCOUNTER gStatRefuseIF0;
126static STAMCOUNTER gStatRefuseCode16;
127static STAMCOUNTER gStatRefuseWP0;
128static STAMCOUNTER gStatRefuseRing1or2;
129static STAMCOUNTER gStatRefuseCanExecute;
130static STAMCOUNTER gStatREMGDTChange;
131static STAMCOUNTER gStatREMIDTChange;
132static STAMCOUNTER gStatREMLDTRChange;
133static STAMCOUNTER gStatREMTRChange;
134static STAMCOUNTER gStatSelOutOfSync[6];
135static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
136#endif
137
138/*
139 * Global stuff.
140 */
141
142/** MMIO read callbacks. */
143CPUReadMemoryFunc *g_apfnMMIORead[3] =
144{
145 remR3MMIOReadU8,
146 remR3MMIOReadU16,
147 remR3MMIOReadU32
148};
149
150/** MMIO write callbacks. */
151CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
152{
153 remR3MMIOWriteU8,
154 remR3MMIOWriteU16,
155 remR3MMIOWriteU32
156};
157
158/** Handler read callbacks. */
159CPUReadMemoryFunc *g_apfnHandlerRead[3] =
160{
161 remR3HandlerReadU8,
162 remR3HandlerReadU16,
163 remR3HandlerReadU32
164};
165
166/** Handler write callbacks. */
167CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
168{
169 remR3HandlerWriteU8,
170 remR3HandlerWriteU16,
171 remR3HandlerWriteU32
172};
173
174
175#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDWS) && defined(RT_ARCH_AMD64))
176/*
177 * Debugger commands.
178 */
179static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
180
181/** '.remstep' arguments. */
182static const DBGCVARDESC g_aArgRemStep[] =
183{
184 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
185 { 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
186};
187
188/** Command descriptors. */
189static const DBGCCMD g_aCmds[] =
190{
191 {
192 .pszCmd ="remstep",
193 .cArgsMin = 0,
194 .cArgsMax = 1,
195 .paArgDescs = &g_aArgRemStep[0],
196 .cArgDescs = ELEMENTS(g_aArgRemStep),
197 .pResultDesc = NULL,
198 .fFlags = 0,
199 .pfnHandler = remR3CmdDisasEnableStepping,
200 .pszSyntax = "[on/off]",
201 .pszDescription = "Enable or disable the single stepping with logged disassembly. "
202 "If no arguments show the current state."
203 }
204};
205#endif
206
207
208/* Instantiate the structure signatures. */
209#define REM_STRUCT_OP 0
210#include "InnoTek/structs.h"
211
212
213
214/*******************************************************************************
215* Internal Functions *
216*******************************************************************************/
217static void remAbort(int rc, const char *pszTip);
218extern int testmath(void);
219
220/* Put them here to avoid unused variable warning. */
221AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
222#if !defined(IPRT_NO_CRT) && (defined(RT_OS_LINUX) || defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS))
223AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
224#else
225AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
226#endif
227
228
229/**
230 * Initializes the REM.
231 *
232 * @returns VBox status code.
233 * @param pVM The VM to operate on.
234 */
235REMR3DECL(int) REMR3Init(PVM pVM)
236{
237 uint32_t u32Dummy;
238 unsigned i;
239
240 /*
241 * Assert sanity.
242 */
243 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
244 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
245 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
246#if defined(DEBUG) && !defined(RT_OS_SOLARIS) /// @todo fix the solaris math stuff.
247 Assert(!testmath());
248#endif
249 ASSERT_STRUCT_TABLE(Misc);
250 ASSERT_STRUCT_TABLE(TLB);
251 ASSERT_STRUCT_TABLE(SegmentCache);
252 ASSERT_STRUCT_TABLE(XMMReg);
253 ASSERT_STRUCT_TABLE(MMXReg);
254 ASSERT_STRUCT_TABLE(float_status);
255 ASSERT_STRUCT_TABLE(float32u);
256 ASSERT_STRUCT_TABLE(float64u);
257 ASSERT_STRUCT_TABLE(floatx80u);
258 ASSERT_STRUCT_TABLE(CPUState);
259
260 /*
261 * Init some internal data members.
262 */
263 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
264 pVM->rem.s.Env.pVM = pVM;
265#ifdef CPU_RAW_MODE_INIT
266 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
267#endif
268
269 /* ctx. */
270 int rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);
271 if (VBOX_FAILURE(rc))
272 {
273 AssertMsgFailed(("Failed to obtain guest ctx pointer. rc=%Vrc\n", rc));
274 return rc;
275 }
276 AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
277
278 /* ignore all notifications */
279 pVM->rem.s.fIgnoreAll = true;
280
281 /*
282 * Init the recompiler.
283 */
284 if (!cpu_x86_init(&pVM->rem.s.Env))
285 {
286 AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
287 return VERR_GENERAL_FAILURE;
288 }
289 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
290 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
291
292 /* allocate code buffer for single instruction emulation. */
293 pVM->rem.s.Env.cbCodeBuffer = 4096;
294 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
295 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
296
297 /* finally, set the cpu_single_env global. */
298 cpu_single_env = &pVM->rem.s.Env;
299
300 /* Nothing is pending by default */
301 pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
302
303 /*
304 * Register ram types.
305 */
306 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(-1, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
307 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
308 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(-1, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
309 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
310 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
311
312 /* stop ignoring. */
313 pVM->rem.s.fIgnoreAll = false;
314
315 /*
316 * Register the saved state data unit.
317 */
318 rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
319 NULL, remR3Save, NULL,
320 NULL, remR3Load, NULL);
321 if (VBOX_FAILURE(rc))
322 return rc;
323
324#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
325 /*
326 * Debugger commands.
327 */
328 static bool fRegisteredCmds = false;
329 if (!fRegisteredCmds)
330 {
331 int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
332 if (VBOX_SUCCESS(rc))
333 fRegisteredCmds = true;
334 }
335#endif
336
337#ifdef VBOX_WITH_STATISTICS
338 /*
339 * Statistics.
340 */
341 STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
342 STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
343 STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
344 STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
345 STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
346 STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
347 STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
348 STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
349 STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
350 STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
351 STAM_REG(pVM, &gStatHCVirt2GCPhys, STAMTYPE_PROFILE, "/PROF/REM/HCVirt2GCPhys", STAMUNIT_TICKS_PER_CALL, "Profiling memory convertion.");
352 STAM_REG(pVM, &gStatGCPhys2HCVirt, STAMTYPE_PROFILE, "/PROF/REM/GCPhys2HCVirt", STAMUNIT_TICKS_PER_CALL, "Profiling memory convertion.");
353
354 STAM_REG(pVM, &gStatCpuGetTSC, STAMTYPE_COUNTER, "/REM/CpuGetTSC", STAMUNIT_OCCURENCES, "cpu_get_tsc calls");
355
356 STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
357 STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
358 STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
359 STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
360 STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
361 STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
362 STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
363 STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
364 STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
365 STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
366
367 STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
368 STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
369 STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
370 STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
371
372 STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
373 STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
374 STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
375 STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
376 STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
377 STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
378
379 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
380 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
381 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
382 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
383 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
384 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
385
386
387#endif
388
389#ifdef DEBUG_ALL_LOGGING
390 loglevel = ~0;
391#endif
392
393 return rc;
394}
395
396
397/**
398 * Terminates the REM.
399 *
400 * Termination means cleaning up and freeing all resources,
401 * the VM it self is at this point powered off or suspended.
402 *
403 * @returns VBox status code.
404 * @param pVM The VM to operate on.
405 */
406REMR3DECL(int) REMR3Term(PVM pVM)
407{
408 return VINF_SUCCESS;
409}
410
411
412/**
413 * The VM is being reset.
414 *
415 * For the REM component this means to call the cpu_reset() and
416 * reinitialize some state variables.
417 *
418 * @param pVM VM handle.
419 */
420REMR3DECL(void) REMR3Reset(PVM pVM)
421{
422 /*
423 * Reset the REM cpu.
424 */
425 pVM->rem.s.fIgnoreAll = true;
426 cpu_reset(&pVM->rem.s.Env);
427 pVM->rem.s.cInvalidatedPages = 0;
428 pVM->rem.s.fIgnoreAll = false;
429
430 /* Clear raw ring 0 init state */
431 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
432}
433
434
435/**
436 * Execute state save operation.
437 *
438 * @returns VBox status code.
439 * @param pVM VM Handle.
440 * @param pSSM SSM operation handle.
441 */
442static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
443{
444 LogFlow(("remR3Save:\n"));
445
446 /*
447 * Save the required CPU Env bits.
448 * (Not much because we're never in REM when doing the save.)
449 */
450 PREM pRem = &pVM->rem.s;
451 Assert(!pRem->fInREM);
452 SSMR3PutU32(pSSM, pRem->Env.hflags);
453 SSMR3PutMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
454 SSMR3PutU32(pSSM, ~0); /* separator */
455
456 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
457 SSMR3PutU32(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
458
459 /*
460 * Save the REM stuff.
461 */
462 SSMR3PutUInt(pSSM, pRem->cInvalidatedPages);
463 unsigned i;
464 for (i = 0; i < pRem->cInvalidatedPages; i++)
465 SSMR3PutGCPtr(pSSM, pRem->aGCPtrInvalidatedPages[i]);
466
467 SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
468
469 return SSMR3PutU32(pSSM, ~0); /* terminator */
470}
471
472
473/**
474 * Execute state load operation.
475 *
476 * @returns VBox status code.
477 * @param pVM VM Handle.
478 * @param pSSM SSM operation handle.
479 * @param u32Version Data layout version.
480 */
481static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
482{
483 uint32_t u32Dummy;
484 uint32_t fRawRing0 = false;
485 LogFlow(("remR3Load:\n"));
486
487 /*
488 * Validate version.
489 */
490 if (u32Version != REM_SAVED_STATE_VERSION)
491 {
492 Log(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
493 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
494 }
495
496 /*
497 * Do a reset to be on the safe side...
498 */
499 REMR3Reset(pVM);
500
501 /*
502 * Ignore all ignorable notifications.
503 * (Not doing this will cause serious trouble.)
504 */
505 pVM->rem.s.fIgnoreAll = true;
506
507 /*
508 * Load the required CPU Env bits.
509 * (Not much because we're never in REM when doing the save.)
510 */
511 PREM pRem = &pVM->rem.s;
512 Assert(!pRem->fInREM);
513 SSMR3GetU32(pSSM, &pRem->Env.hflags);
514 SSMR3GetMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
515 uint32_t u32Sep;
516 int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
517 if (VBOX_FAILURE(rc))
518 return rc;
519 if (u32Sep != ~0)
520 {
521 AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
522 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
523 }
524
525 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
526 SSMR3GetUInt(pSSM, &fRawRing0);
527 if (fRawRing0)
528 pRem->Env.state |= CPU_RAW_RING0;
529
530 /*
531 * Load the REM stuff.
532 */
533 rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
534 if (VBOX_FAILURE(rc))
535 return rc;
536 if (pRem->cInvalidatedPages > ELEMENTS(pRem->aGCPtrInvalidatedPages))
537 {
538 AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
539 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
540 }
541 unsigned i;
542 for (i = 0; i < pRem->cInvalidatedPages; i++)
543 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
544
545 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
546 if (VBOX_FAILURE(rc))
547 return rc;
548
549 /* check the terminator. */
550 rc = SSMR3GetU32(pSSM, &u32Sep);
551 if (VBOX_FAILURE(rc))
552 return rc;
553 if (u32Sep != ~0)
554 {
555 AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
556 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
557 }
558
559 /*
560 * Get the CPUID features.
561 */
562 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
563 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
564
565 /*
566 * Sync the Load Flush the TLB
567 */
568 tlb_flush(&pRem->Env, 1);
569
570#if 0 /** @todo r=bird: this doesn't make sense. WHY? */
571 /*
572 * Clear all lazy flags (only FPU sync for now).
573 */
574 CPUMGetAndClearFPUUsedREM(pVM);
575#endif
576
577 /*
578 * Stop ignoring ignornable notifications.
579 */
580 pVM->rem.s.fIgnoreAll = false;
581
582 return VINF_SUCCESS;
583}
584
585
586
587#undef LOG_GROUP
588#define LOG_GROUP LOG_GROUP_REM_RUN
589
590/**
591 * Single steps an instruction in recompiled mode.
592 *
593 * Before calling this function the REM state needs to be in sync with
594 * the VM. Call REMR3State() to perform the sync. It's only necessary
595 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
596 * and after calling REMR3StateBack().
597 *
598 * @returns VBox status code.
599 *
600 * @param pVM VM Handle.
601 */
602REMR3DECL(int) REMR3Step(PVM pVM)
603{
604 /*
605 * Lock the REM - we don't wanna have anyone interrupting us
606 * while stepping - and enabled single stepping. We also ignore
607 * pending interrupts and suchlike.
608 */
609 int interrupt_request = pVM->rem.s.Env.interrupt_request;
610 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER)));
611 pVM->rem.s.Env.interrupt_request = 0;
612 cpu_single_step(&pVM->rem.s.Env, 1);
613
614 /*
615 * If we're standing at a breakpoint, that have to be disabled before we start stepping.
616 */
617 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
618 bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
619
620 /*
621 * Execute and handle the return code.
622 * We execute without enabling the cpu tick, so on success we'll
623 * just flip it on and off to make sure it moves
624 */
625 int rc = cpu_exec(&pVM->rem.s.Env);
626 if (rc == EXCP_DEBUG)
627 {
628 TMCpuTickResume(pVM);
629 TMCpuTickPause(pVM);
630 TMVirtualResume(pVM);
631 TMVirtualPause(pVM);
632 rc = VINF_EM_DBG_STEPPED;
633 }
634 else
635 {
636 AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
637 switch (rc)
638 {
639 case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
640 case EXCP_HLT:
641 case EXCP_HALTED: rc = VINF_EM_HALT; break;
642 case EXCP_RC:
643 rc = pVM->rem.s.rc;
644 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
645 break;
646 default:
647 AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
648 rc = VERR_INTERNAL_ERROR;
649 break;
650 }
651 }
652
653 /*
654 * Restore the stuff we changed to prevent interruption.
655 * Unlock the REM.
656 */
657 if (fBp)
658 {
659 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
660 Assert(rc2 == 0); NOREF(rc2);
661 }
662 cpu_single_step(&pVM->rem.s.Env, 0);
663 pVM->rem.s.Env.interrupt_request = interrupt_request;
664
665 return rc;
666}
667
668
669/**
670 * Set a breakpoint using the REM facilities.
671 *
672 * @returns VBox status code.
673 * @param pVM The VM handle.
674 * @param Address The breakpoint address.
675 * @thread The emulation thread.
676 */
677REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
678{
679 VM_ASSERT_EMT(pVM);
680 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
681 {
682 LogFlow(("REMR3BreakpointSet: Address=%VGv\n", Address));
683 return VINF_SUCCESS;
684 }
685 LogFlow(("REMR3BreakpointSet: Address=%VGv - failed!\n", Address));
686 return VERR_REM_NO_MORE_BP_SLOTS;
687}
688
689
690/**
691 * Clears a breakpoint set by REMR3BreakpointSet().
692 *
693 * @returns VBox status code.
694 * @param pVM The VM handle.
695 * @param Address The breakpoint address.
696 * @thread The emulation thread.
697 */
698REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
699{
700 VM_ASSERT_EMT(pVM);
701 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
702 {
703 LogFlow(("REMR3BreakpointClear: Address=%VGv\n", Address));
704 return VINF_SUCCESS;
705 }
706 LogFlow(("REMR3BreakpointClear: Address=%VGv - not found!\n", Address));
707 return VERR_REM_BP_NOT_FOUND;
708}
709
710
711/**
712 * Emulate an instruction.
713 *
714 * This function executes one instruction without letting anyone
715 * interrupt it. This is intended for being called while being in
716 * raw mode and thus will take care of all the state syncing between
717 * REM and the rest.
718 *
719 * @returns VBox status code.
720 * @param pVM VM handle.
721 */
722REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
723{
724 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", pVM->rem.s.pCtx->cs, pVM->rem.s.pCtx->eip));
725
726 /*
727 * Sync the state and enable single instruction / single stepping.
728 */
729 int rc = REMR3State(pVM);
730 if (VBOX_SUCCESS(rc))
731 {
732 int interrupt_request = pVM->rem.s.Env.interrupt_request;
733 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER)));
734 Assert(!pVM->rem.s.Env.singlestep_enabled);
735#if 1
736
737 /*
738 * Now we set the execute single instruction flag and enter the cpu_exec loop.
739 */
740 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
741 rc = cpu_exec(&pVM->rem.s.Env);
742 switch (rc)
743 {
744 /*
745 * Executed without anything out of the way happening.
746 */
747 case EXCP_SINGLE_INSTR:
748 rc = VINF_EM_RESCHEDULE;
749 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
750 break;
751
752 /*
753 * If we take a trap or start servicing a pending interrupt, we might end up here.
754 * (Timer thread or some other thread wishing EMT's attention.)
755 */
756 case EXCP_INTERRUPT:
757 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
758 rc = VINF_EM_RESCHEDULE;
759 break;
760
761 /*
762 * Single step, we assume!
763 * If there was a breakpoint there we're fucked now.
764 */
765 case EXCP_DEBUG:
766 {
767 /* breakpoint or single step? */
768 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
769 int iBP;
770 rc = VINF_EM_DBG_STEPPED;
771 for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
772 if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
773 {
774 rc = VINF_EM_DBG_BREAKPOINT;
775 break;
776 }
777 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
778 break;
779 }
780
781 /*
782 * hlt instruction.
783 */
784 case EXCP_HLT:
785 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
786 rc = VINF_EM_HALT;
787 break;
788
789 /*
790 * The VM has halted.
791 */
792 case EXCP_HALTED:
793 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
794 rc = VINF_EM_HALT;
795 break;
796
797 /*
798 * Switch to RAW-mode.
799 */
800 case EXCP_EXECUTE_RAW:
801 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
802 rc = VINF_EM_RESCHEDULE_RAW;
803 break;
804
805 /*
806 * Switch to hardware accelerated RAW-mode.
807 */
808 case EXCP_EXECUTE_HWACC:
809 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
810 rc = VINF_EM_RESCHEDULE_HWACC;
811 break;
812
813 /*
814 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
815 */
816 case EXCP_RC:
817 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
818 rc = pVM->rem.s.rc;
819 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
820 break;
821
822 /*
823 * Figure out the rest when they arrive....
824 */
825 default:
826 AssertMsgFailed(("rc=%d\n", rc));
827 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
828 rc = VINF_EM_RESCHEDULE;
829 break;
830 }
831
832 /*
833 * Switch back the state.
834 */
835#else
836 pVM->rem.s.Env.interrupt_request = 0;
837 cpu_single_step(&pVM->rem.s.Env, 1);
838
839 /*
840 * Execute and handle the return code.
841 * We execute without enabling the cpu tick, so on success we'll
842 * just flip it on and off to make sure it moves.
843 *
844 * (We do not use emulate_single_instr() because that doesn't enter the
845 * right way in will cause serious trouble if a longjmp was attempted.)
846 */
847# ifdef DEBUG_bird
848 remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
849# endif
850 int cTimesMax = 16384;
851 uint32_t eip = pVM->rem.s.Env.eip;
852 do
853 {
854 rc = cpu_exec(&pVM->rem.s.Env);
855
856 } while ( eip == pVM->rem.s.Env.eip
857 && (rc == EXCP_DEBUG || rc == EXCP_EXECUTE_RAW)
858 && --cTimesMax > 0);
859 switch (rc)
860 {
861 /*
862 * Single step, we assume!
863 * If there was a breakpoint there we're fucked now.
864 */
865 case EXCP_DEBUG:
866 {
867 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
868 rc = VINF_EM_RESCHEDULE;
869 break;
870 }
871
872 /*
873 * We cannot be interrupted!
874 */
875 case EXCP_INTERRUPT:
876 AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
877 rc = VERR_INTERNAL_ERROR;
878 break;
879
880 /*
881 * hlt instruction.
882 */
883 case EXCP_HLT:
884 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
885 rc = VINF_EM_HALT;
886 break;
887
888 /*
889 * The VM has halted.
890 */
891 case EXCP_HALTED:
892 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
893 rc = VINF_EM_HALT;
894 break;
895
896 /*
897 * Switch to RAW-mode.
898 */
899 case EXCP_EXECUTE_RAW:
900 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
901 rc = VINF_EM_RESCHEDULE_RAW;
902 break;
903
904 /*
905 * Switch to hardware accelerated RAW-mode.
906 */
907 case EXCP_EXECUTE_HWACC:
908 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
909 rc = VINF_EM_RESCHEDULE_HWACC;
910 break;
911
912 /*
913 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
914 */
915 case EXCP_RC:
916 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
917 rc = pVM->rem.s.rc;
918 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
919 break;
920
921 /*
922 * Figure out the rest when they arrive....
923 */
924 default:
925 AssertMsgFailed(("rc=%d\n", rc));
926 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
927 rc = VINF_SUCCESS;
928 break;
929 }
930
931 /*
932 * Switch back the state.
933 */
934 cpu_single_step(&pVM->rem.s.Env, 0);
935#endif
936 pVM->rem.s.Env.interrupt_request = interrupt_request;
937 int rc2 = REMR3StateBack(pVM);
938 AssertRC(rc2);
939 }
940
941 Log2(("REMR3EmulateInstruction: returns %Vrc (cs:eip=%04x:%08x)\n",
942 rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
943 return rc;
944}
945
946
947/**
948 * Runs code in recompiled mode.
949 *
950 * Before calling this function the REM state needs to be in sync with
951 * the VM. Call REMR3State() to perform the sync. It's only necessary
952 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
953 * and after calling REMR3StateBack().
954 *
955 * @returns VBox status code.
956 *
957 * @param pVM VM Handle.
958 */
959REMR3DECL(int) REMR3Run(PVM pVM)
960{
961 Log2(("REMR3Run: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
962 Assert(pVM->rem.s.fInREM);
963////Keyboard / tb stuff:
964//if ( pVM->rem.s.Env.segs[R_CS].selector == 0xf000
965// && pVM->rem.s.Env.eip >= 0xe860
966// && pVM->rem.s.Env.eip <= 0xe880)
967// pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
968////A20:
969//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x9020
970// && pVM->rem.s.Env.eip >= 0x970
971// && pVM->rem.s.Env.eip <= 0x9a0)
972// pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
973////Speaker (port 61h)
974//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x0010
975// && ( (pVM->rem.s.Env.eip >= 0x90278c10 && pVM->rem.s.Env.eip <= 0x90278c30)
976// || (pVM->rem.s.Env.eip >= 0x9010e250 && pVM->rem.s.Env.eip <= 0x9010e260)
977// )
978// )
979// pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
980//DBGFR3InfoLog(pVM, "timers", NULL);
981
982
983 int rc = cpu_exec(&pVM->rem.s.Env);
984 switch (rc)
985 {
986 /*
987 * This happens when the execution was interrupted
988 * by an external event, like pending timers.
989 */
990 case EXCP_INTERRUPT:
991 Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
992 rc = VINF_SUCCESS;
993 break;
994
995 /*
996 * hlt instruction.
997 */
998 case EXCP_HLT:
999 Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
1000 rc = VINF_EM_HALT;
1001 break;
1002
1003 /*
1004 * The VM has halted.
1005 */
1006 case EXCP_HALTED:
1007 Log2(("REMR3Run: cpu_exec -> EXCP_HALTED\n"));
1008 rc = VINF_EM_HALT;
1009 break;
1010
1011 /*
1012 * Breakpoint/single step.
1013 */
1014 case EXCP_DEBUG:
1015 {
1016#if 0//def DEBUG_bird
1017 static int iBP = 0;
1018 printf("howdy, breakpoint! iBP=%d\n", iBP);
1019 switch (iBP)
1020 {
1021 case 0:
1022 cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
1023 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
1024 //pVM->rem.s.Env.interrupt_request = 0;
1025 //pVM->rem.s.Env.exception_index = -1;
1026 //g_fInterruptDisabled = 1;
1027 rc = VINF_SUCCESS;
1028 asm("int3");
1029 break;
1030 default:
1031 asm("int3");
1032 break;
1033 }
1034 iBP++;
1035#else
1036 /* breakpoint or single step? */
1037 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1038 int iBP;
1039 rc = VINF_EM_DBG_STEPPED;
1040 for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
1041 if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
1042 {
1043 rc = VINF_EM_DBG_BREAKPOINT;
1044 break;
1045 }
1046 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
1047#endif
1048 break;
1049 }
1050
1051 /*
1052 * Switch to RAW-mode.
1053 */
1054 case EXCP_EXECUTE_RAW:
1055 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1056 rc = VINF_EM_RESCHEDULE_RAW;
1057 break;
1058
1059 /*
1060 * Switch to hardware accelerated RAW-mode.
1061 */
1062 case EXCP_EXECUTE_HWACC:
1063 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1064 rc = VINF_EM_RESCHEDULE_HWACC;
1065 break;
1066
1067 /*
1068 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1069 */
1070 case EXCP_RC:
1071 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
1072 rc = pVM->rem.s.rc;
1073 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1074 break;
1075
1076 /*
1077 * Figure out the rest when they arrive....
1078 */
1079 default:
1080 AssertMsgFailed(("rc=%d\n", rc));
1081 Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1082 rc = VINF_SUCCESS;
1083 break;
1084 }
1085
1086 Log2(("REMR3Run: returns %Vrc (cs:eip=%04x:%08x)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
1087 return rc;
1088}
1089
1090
1091/**
1092 * Check if the cpu state is suitable for Raw execution.
1093 *
1094 * @returns boolean
1095 * @param env The CPU env struct.
1096 * @param eip The EIP to check this for (might differ from env->eip).
1097 * @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1098 * @param pExceptionIndex Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1099 *
1100 * @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1101 */
1102bool remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, uint32_t *pExceptionIndex)
1103{
1104 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1105 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1106 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1107
1108 /* Update counter. */
1109 env->pVM->rem.s.cCanExecuteRaw++;
1110
1111 if (HWACCMIsEnabled(env->pVM))
1112 {
1113 env->state |= CPU_RAW_HWACC;
1114
1115 /*
1116 * Create partial context for HWACCMR3CanExecuteGuest
1117 */
1118 CPUMCTX Ctx;
1119 Ctx.cr0 = env->cr[0];
1120 Ctx.cr3 = env->cr[3];
1121 Ctx.cr4 = env->cr[4];
1122
1123 Ctx.tr = env->tr.selector;
1124 Ctx.trHid.u32Base = (uint32_t)env->tr.base;
1125 Ctx.trHid.u32Limit = env->tr.limit;
1126 Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1127
1128 Ctx.idtr.cbIdt = env->idt.limit;
1129 Ctx.idtr.pIdt = (uint32_t)env->idt.base;
1130
1131 Ctx.eflags.u32 = env->eflags;
1132
1133 Ctx.cs = env->segs[R_CS].selector;
1134 Ctx.csHid.u32Base = (uint32_t)env->segs[R_CS].base;
1135 Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1136 Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1137
1138 Ctx.ss = env->segs[R_SS].selector;
1139 Ctx.ssHid.u32Base = (uint32_t)env->segs[R_SS].base;
1140 Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1141 Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1142
1143 /* Hardware accelerated raw-mode:
1144 *
1145 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1146 */
1147 if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1148 {
1149 *pExceptionIndex = EXCP_EXECUTE_HWACC;
1150 return true;
1151 }
1152 return false;
1153 }
1154
1155 /*
1156 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1157 * or 32 bits protected mode ring 0 code
1158 *
1159 * The tests are ordered by the likelyhood of being true during normal execution.
1160 */
1161 if (fFlags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))
1162 {
1163 STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1164 Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1165 return false;
1166 }
1167
1168#ifndef VBOX_RAW_V86
1169 if (fFlags & VM_MASK) {
1170 STAM_COUNTER_INC(&gStatRefuseVM86);
1171 Log2(("raw mode refused: VM_MASK\n"));
1172 return false;
1173 }
1174#endif
1175
1176 if (env->state & CPU_EMULATE_SINGLE_INSTR)
1177 {
1178#ifndef DEBUG_bird
1179 Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1180#endif
1181 return false;
1182 }
1183
1184 if (env->singlestep_enabled)
1185 {
1186 //Log2(("raw mode refused: Single step\n"));
1187 return false;
1188 }
1189
1190 if (env->nb_breakpoints > 0)
1191 {
1192 //Log2(("raw mode refused: Breakpoints\n"));
1193 return false;
1194 }
1195
1196 uint32_t u32CR0 = env->cr[0];
1197 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1198 {
1199 STAM_COUNTER_INC(&gStatRefusePaging);
1200 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1201 return false;
1202 }
1203
1204 if (env->cr[4] & CR4_PAE_MASK)
1205 {
1206 STAM_COUNTER_INC(&gStatRefusePAE);
1207 //Log2(("raw mode refused: PAE\n"));
1208 return false;
1209 }
1210
1211 if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1212 {
1213 if (!EMIsRawRing3Enabled(env->pVM))
1214 return false;
1215
1216 if (!(env->eflags & IF_MASK))
1217 {
1218 STAM_COUNTER_INC(&gStatRefuseIF0);
1219 Log2(("raw mode refused: IF (RawR3)\n"));
1220 return false;
1221 }
1222
1223 if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1224 {
1225 STAM_COUNTER_INC(&gStatRefuseWP0);
1226 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1227 return false;
1228 }
1229 }
1230 else
1231 {
1232 if (!EMIsRawRing0Enabled(env->pVM))
1233 return false;
1234
1235 // Let's start with pure 32 bits ring 0 code first
1236 if ((fFlags & (HF_SS32_MASK | HF_CS32_MASK)) != (HF_SS32_MASK | HF_CS32_MASK))
1237 {
1238 STAM_COUNTER_INC(&gStatRefuseCode16);
1239 Log2(("raw r0 mode refused: HF_[S|C]S32_MASK fFlags=%#x\n", fFlags));
1240 return false;
1241 }
1242
1243 // Only R0
1244 if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1245 {
1246 STAM_COUNTER_INC(&gStatRefuseRing1or2);
1247 Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1248 return false;
1249 }
1250
1251 if (!(u32CR0 & CR0_WP_MASK))
1252 {
1253 STAM_COUNTER_INC(&gStatRefuseWP0);
1254 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1255 return false;
1256 }
1257
1258 if (PATMIsPatchGCAddr(env->pVM, eip))
1259 {
1260 Log2(("raw r0 mode forced: patch code\n"));
1261 *pExceptionIndex = EXCP_EXECUTE_RAW;
1262 return true;
1263 }
1264
1265#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1266 if (!(env->eflags & IF_MASK))
1267 {
1268 STAM_COUNTER_INC(&gStatRefuseIF0);
1269 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1270 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1271 return false;
1272 }
1273#endif
1274
1275 env->state |= CPU_RAW_RING0;
1276 }
1277
1278 /*
1279 * Don't reschedule the first time we're called, because there might be
1280 * special reasons why we're here that is not covered by the above checks.
1281 */
1282 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1283 {
1284 Log2(("raw mode refused: first scheduling\n"));
1285 STAM_COUNTER_INC(&gStatRefuseCanExecute);
1286 return false;
1287 }
1288
1289 Assert(PGMPhysIsA20Enabled(env->pVM));
1290 *pExceptionIndex = EXCP_EXECUTE_RAW;
1291 return true;
1292}
1293
1294
1295/**
1296 * Fetches a code byte.
1297 *
1298 * @returns Success indicator (bool) for ease of use.
1299 * @param env The CPU environment structure.
1300 * @param GCPtrInstr Where to fetch code.
1301 * @param pu8Byte Where to store the byte on success
1302 */
1303bool remR3GetOpcode(CPUState *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte)
1304{
1305 int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1306 if (VBOX_SUCCESS(rc))
1307 return true;
1308 return false;
1309}
1310
1311
1312/**
1313 * Flush (or invalidate if you like) page table/dir entry.
1314 *
1315 * (invlpg instruction; tlb_flush_page)
1316 *
1317 * @param env Pointer to cpu environment.
1318 * @param GCPtr The virtual address which page table/dir entry should be invalidated.
1319 */
1320void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1321{
1322 PVM pVM = env->pVM;
1323
1324 /*
1325 * When we're replaying invlpg instructions or restoring a saved
1326 * state we disable this path.
1327 */
1328 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.fIgnoreAll)
1329 return;
1330 Log(("remR3FlushPage: GCPtr=%VGv\n", GCPtr));
1331 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1332
1333 //RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1334
1335 /*
1336 * Update the control registers before calling PGMFlushPage.
1337 */
1338 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1339 pCtx->cr0 = env->cr[0];
1340 pCtx->cr3 = env->cr[3];
1341 pCtx->cr4 = env->cr[4];
1342
1343 /*
1344 * Let PGM do the rest.
1345 */
1346 int rc = PGMInvalidatePage(pVM, GCPtr);
1347 if (VBOX_FAILURE(rc))
1348 {
1349 AssertMsgFailed(("remR3FlushPage %x %x %x %d failed!!\n", GCPtr));
1350 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1351 }
1352 //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1353}
1354
1355/**
1356 * Called from tlb_protect_code in order to write monitor a code page.
1357 *
1358 * @param env Pointer to the CPU environment.
1359 * @param GCPtr Code page to monitor
1360 */
1361void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1362{
1363 Assert(env->pVM->rem.s.fInREM);
1364 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1365 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1366 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1367 && !(env->eflags & VM_MASK) /* no V86 mode */
1368 && !HWACCMIsEnabled(env->pVM))
1369 CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1370}
1371
1372/**
1373 * Called when the CPU is initialized, any of the CRx registers are changed or
1374 * when the A20 line is modified.
1375 *
1376 * @param env Pointer to the CPU environment.
1377 * @param fGlobal Set if the flush is global.
1378 */
1379void remR3FlushTLB(CPUState *env, bool fGlobal)
1380{
1381 PVM pVM = env->pVM;
1382
1383 /*
1384 * When we're replaying invlpg instructions or restoring a saved
1385 * state we disable this path.
1386 */
1387 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.fIgnoreAll)
1388 return;
1389 Assert(pVM->rem.s.fInREM);
1390
1391 /*
1392 * The caller doesn't check cr4, so we have to do that for ourselves.
1393 */
1394 if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1395 fGlobal = true;
1396 Log(("remR3FlushTLB: CR0=%VGp CR3=%VGp CR4=%VGp %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1397
1398 /*
1399 * Update the control registers before calling PGMR3FlushTLB.
1400 */
1401 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1402 pCtx->cr0 = env->cr[0];
1403 pCtx->cr3 = env->cr[3];
1404 pCtx->cr4 = env->cr[4];
1405
1406 /*
1407 * Let PGM do the rest.
1408 */
1409 PGMFlushTLB(pVM, env->cr[3], fGlobal);
1410}
1411
1412
1413/**
1414 * Called when any of the cr0, cr4 or efer registers is updated.
1415 *
1416 * @param env Pointer to the CPU environment.
1417 */
1418void remR3ChangeCpuMode(CPUState *env)
1419{
1420 int rc;
1421 PVM pVM = env->pVM;
1422
1423 /*
1424 * When we're replaying loads or restoring a saved
1425 * state this path is disabled.
1426 */
1427 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.fIgnoreAll)
1428 return;
1429 Assert(pVM->rem.s.fInREM);
1430
1431 /*
1432 * Update the control registers before calling PGMR3ChangeMode()
1433 * as it may need to map whatever cr3 is pointing to.
1434 */
1435 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1436 pCtx->cr0 = env->cr[0];
1437 pCtx->cr3 = env->cr[3];
1438 pCtx->cr4 = env->cr[4];
1439
1440#ifdef TARGET_X86_64
1441 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1442 if (rc != VINF_SUCCESS)
1443 cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], env->efer, rc);
1444#else
1445 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1446 if (rc != VINF_SUCCESS)
1447 cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], 0LL, rc);
1448#endif
1449}
1450
1451
1452/**
1453 * Called from compiled code to run dma.
1454 *
1455 * @param env Pointer to the CPU environment.
1456 */
1457void remR3DmaRun(CPUState *env)
1458{
1459 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1460 PDMR3DmaRun(env->pVM);
1461 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1462}
1463
1464/**
1465 * Called from compiled code to schedule pending timers in VMM
1466 *
1467 * @param env Pointer to the CPU environment.
1468 */
1469void remR3TimersRun(CPUState *env)
1470{
1471 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1472 remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1473 TMR3TimerQueuesDo(env->pVM);
1474 remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1475 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1476}
1477
1478/**
1479 * Record trap occurance
1480 *
1481 * @returns VBox status code
1482 * @param env Pointer to the CPU environment.
1483 * @param uTrap Trap nr
1484 * @param uErrorCode Error code
1485 * @param pvNextEIP Next EIP
1486 */
1487int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1488{
1489 PVM pVM = env->pVM;
1490#ifdef VBOX_WITH_STATISTICS
1491 static STAMCOUNTER aStatTrap[255];
1492 static bool aRegisters[ELEMENTS(aStatTrap)];
1493#endif
1494
1495#ifdef VBOX_WITH_STATISTICS
1496 if (uTrap < 255)
1497 {
1498 if (!aRegisters[uTrap])
1499 {
1500 aRegisters[uTrap] = true;
1501 char szStatName[64];
1502 RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1503 STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1504 }
1505 STAM_COUNTER_INC(&aStatTrap[uTrap]);
1506 }
1507#endif
1508 Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1509 if( uTrap < 0x20
1510 && (env->cr[0] & X86_CR0_PE)
1511 && !(env->eflags & X86_EFL_VM))
1512 {
1513#ifdef DEBUG
1514 remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1515#endif
1516 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
1517 {
1518 LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1519 remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1520 return VERR_REM_TOO_MANY_TRAPS;
1521 }
1522 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1523 pVM->rem.s.cPendingExceptions = 1;
1524 pVM->rem.s.uPendingException = uTrap;
1525 pVM->rem.s.uPendingExcptEIP = env->eip;
1526 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1527 }
1528 else
1529 {
1530 pVM->rem.s.cPendingExceptions = 0;
1531 pVM->rem.s.uPendingException = uTrap;
1532 pVM->rem.s.uPendingExcptEIP = env->eip;
1533 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1534 }
1535 return VINF_SUCCESS;
1536}
1537
1538/*
1539 * Clear current active trap
1540 *
1541 * @param pVM VM Handle.
1542 */
1543void remR3TrapClear(PVM pVM)
1544{
1545 pVM->rem.s.cPendingExceptions = 0;
1546 pVM->rem.s.uPendingException = 0;
1547 pVM->rem.s.uPendingExcptEIP = 0;
1548 pVM->rem.s.uPendingExcptCR2 = 0;
1549}
1550
1551/*
1552 * Record previous call instruction addresses
1553 *
1554 * @param env Pointer to the CPU environment.
1555 */
1556void remR3RecordCall(CPUState *env)
1557{
1558 CSAMR3RecordCallAddress(env->pVM, env->eip);
1559}
1560
1561/**
1562 * Syncs the internal REM state with the VM.
1563 *
1564 * This must be called before REMR3Run() is invoked whenever when the REM
1565 * state is not up to date. Calling it several times in a row is not
1566 * permitted.
1567 *
1568 * @returns VBox status code.
1569 *
1570 * @param pVM VM Handle.
1571 *
1572 * @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1573 * no do this since the majority of the callers don't want any unnecessary of events
1574 * pending that would immediatly interrupt execution.
1575 */
1576REMR3DECL(int) REMR3State(PVM pVM)
1577{
1578 Log2(("REMR3State:\n"));
1579 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1580 register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1581 register unsigned fFlags;
1582 bool fHiddenSelRegsValid = CPUMAreHiddenSelRegsValid(pVM);
1583
1584 Assert(!pVM->rem.s.fInREM);
1585 pVM->rem.s.fInStateSync = true;
1586
1587 /*
1588 * Copy the registers which requires no special handling.
1589 */
1590 Assert(R_EAX == 0);
1591 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1592 Assert(R_ECX == 1);
1593 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1594 Assert(R_EDX == 2);
1595 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1596 Assert(R_EBX == 3);
1597 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1598 Assert(R_ESP == 4);
1599 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1600 Assert(R_EBP == 5);
1601 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1602 Assert(R_ESI == 6);
1603 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1604 Assert(R_EDI == 7);
1605 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1606 pVM->rem.s.Env.eip = pCtx->eip;
1607
1608 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1609
1610 pVM->rem.s.Env.cr[2] = pCtx->cr2;
1611
1612 /** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1613 pVM->rem.s.Env.dr[0] = pCtx->dr0;
1614 pVM->rem.s.Env.dr[1] = pCtx->dr1;
1615 pVM->rem.s.Env.dr[2] = pCtx->dr2;
1616 pVM->rem.s.Env.dr[3] = pCtx->dr3;
1617 pVM->rem.s.Env.dr[4] = pCtx->dr4;
1618 pVM->rem.s.Env.dr[5] = pCtx->dr5;
1619 pVM->rem.s.Env.dr[6] = pCtx->dr6;
1620 pVM->rem.s.Env.dr[7] = pCtx->dr7;
1621
1622 /*
1623 * Clear the halted hidden flag (the interrupt waking up the CPU can
1624 * have been dispatched in raw mode).
1625 */
1626 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
1627
1628 /*
1629 * Replay invlpg?
1630 */
1631 if (pVM->rem.s.cInvalidatedPages)
1632 {
1633 pVM->rem.s.fIgnoreInvlPg = true;
1634 RTUINT i;
1635 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1636 {
1637 Log2(("REMR3State: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1638 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1639 }
1640 pVM->rem.s.fIgnoreInvlPg = false;
1641 pVM->rem.s.cInvalidatedPages = 0;
1642 }
1643
1644 /*
1645 * Registers which are rarely changed and require special handling / order when changed.
1646 */
1647 fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1648 if (fFlags & ( CPUM_CHANGED_CR4 | CPUM_CHANGED_CR3 | CPUM_CHANGED_CR0
1649 | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_LDTR | CPUM_CHANGED_TR
1650 | CPUM_CHANGED_FPU_REM | CPUM_CHANGED_SYSENTER_MSR))
1651 {
1652 if (fFlags & CPUM_CHANGED_FPU_REM)
1653 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu); /* 'save' is an excellent name. */
1654
1655 if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1656 {
1657 pVM->rem.s.fIgnoreCR3Load = true;
1658 tlb_flush(&pVM->rem.s.Env, true);
1659 pVM->rem.s.fIgnoreCR3Load = false;
1660 }
1661
1662 if (fFlags & CPUM_CHANGED_CR4)
1663 {
1664 pVM->rem.s.fIgnoreCR3Load = true;
1665 pVM->rem.s.fIgnoreCpuMode = true;
1666 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1667 pVM->rem.s.fIgnoreCpuMode = false;
1668 pVM->rem.s.fIgnoreCR3Load = false;
1669 }
1670
1671 if (fFlags & CPUM_CHANGED_CR0)
1672 {
1673 pVM->rem.s.fIgnoreCR3Load = true;
1674 pVM->rem.s.fIgnoreCpuMode = true;
1675 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1676 pVM->rem.s.fIgnoreCpuMode = false;
1677 pVM->rem.s.fIgnoreCR3Load = false;
1678 }
1679
1680 if (fFlags & CPUM_CHANGED_CR3)
1681 {
1682 pVM->rem.s.fIgnoreCR3Load = true;
1683 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1684 pVM->rem.s.fIgnoreCR3Load = false;
1685 }
1686
1687 if (fFlags & CPUM_CHANGED_GDTR)
1688 {
1689 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1690 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1691 }
1692
1693 if (fFlags & CPUM_CHANGED_IDTR)
1694 {
1695 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1696 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1697 }
1698
1699 if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1700 {
1701 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1702 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1703 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1704 }
1705
1706 if (fFlags & CPUM_CHANGED_LDTR)
1707 {
1708 if (fHiddenSelRegsValid)
1709 {
1710 pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1711 pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u32Base;
1712 pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1713 pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1714 }
1715 else
1716 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1717 }
1718
1719 if (fFlags & CPUM_CHANGED_TR)
1720 {
1721 if (fHiddenSelRegsValid)
1722 {
1723 pVM->rem.s.Env.tr.selector = pCtx->tr;
1724 pVM->rem.s.Env.tr.base = pCtx->trHid.u32Base;
1725 pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1726 pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1727 }
1728 else
1729 sync_tr(&pVM->rem.s.Env, pCtx->tr);
1730
1731 /** @note do_interrupt will fault if the busy flag is still set.... */
1732 pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1733 }
1734 }
1735
1736 /*
1737 * Update selector registers.
1738 * This must be done *after* we've synced gdt, ldt and crX registers
1739 * since we're reading the GDT/LDT om sync_seg. This will happen with
1740 * saved state which takes a quick dip into rawmode for instance.
1741 */
1742 /*
1743 * Stack; Note first check this one as the CPL might have changed. The
1744 * wrong CPL can cause QEmu to raise an exception in sync_seg!!
1745 */
1746
1747 if (fHiddenSelRegsValid)
1748 {
1749 /* The hidden selector registers are valid in the CPU context. */
1750 /** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1751
1752 /* Set current CPL */
1753 cpu_x86_set_cpl(&pVM->rem.s.Env, CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)));
1754
1755 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1756 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1757 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1758 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1759 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1760 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1761 }
1762 else
1763 {
1764 /* In 'normal' raw mode we don't have access to the hidden selector registers. */
1765 if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1766 {
1767 Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1768
1769 cpu_x86_set_cpl(&pVM->rem.s.Env, (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & 3));
1770 sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1771#ifdef VBOX_WITH_STATISTICS
1772 if (pVM->rem.s.Env.segs[R_SS].newselector)
1773 {
1774 STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1775 }
1776#endif
1777 }
1778 else
1779 pVM->rem.s.Env.segs[R_SS].newselector = 0;
1780
1781 if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1782 {
1783 Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1784 sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1785#ifdef VBOX_WITH_STATISTICS
1786 if (pVM->rem.s.Env.segs[R_ES].newselector)
1787 {
1788 STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1789 }
1790#endif
1791 }
1792 else
1793 pVM->rem.s.Env.segs[R_ES].newselector = 0;
1794
1795 if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1796 {
1797 Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1798 sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1799#ifdef VBOX_WITH_STATISTICS
1800 if (pVM->rem.s.Env.segs[R_CS].newselector)
1801 {
1802 STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1803 }
1804#endif
1805 }
1806 else
1807 pVM->rem.s.Env.segs[R_CS].newselector = 0;
1808
1809 if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1810 {
1811 Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1812 sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1813#ifdef VBOX_WITH_STATISTICS
1814 if (pVM->rem.s.Env.segs[R_DS].newselector)
1815 {
1816 STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1817 }
1818#endif
1819 }
1820 else
1821 pVM->rem.s.Env.segs[R_DS].newselector = 0;
1822
1823 /** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1824 * be the same but not the base/limit. */
1825 if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1826 {
1827 Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1828 sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1829#ifdef VBOX_WITH_STATISTICS
1830 if (pVM->rem.s.Env.segs[R_FS].newselector)
1831 {
1832 STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1833 }
1834#endif
1835 }
1836 else
1837 pVM->rem.s.Env.segs[R_FS].newselector = 0;
1838
1839 if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1840 {
1841 Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1842 sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1843#ifdef VBOX_WITH_STATISTICS
1844 if (pVM->rem.s.Env.segs[R_GS].newselector)
1845 {
1846 STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1847 }
1848#endif
1849 }
1850 else
1851 pVM->rem.s.Env.segs[R_GS].newselector = 0;
1852 }
1853
1854 /*
1855 * Check for traps.
1856 */
1857 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
1858 TRPMEVENT enmType;
1859 uint8_t u8TrapNo;
1860 int rc = TRPMQueryTrap(pVM, &u8TrapNo, &enmType);
1861 if (VBOX_SUCCESS(rc))
1862 {
1863 #ifdef DEBUG
1864 if (u8TrapNo == 0x80)
1865 {
1866 remR3DumpLnxSyscall(pVM);
1867 remR3DumpOBsdSyscall(pVM);
1868 }
1869 #endif
1870
1871 pVM->rem.s.Env.exception_index = u8TrapNo;
1872 if (enmType != TRPM_SOFTWARE_INT)
1873 {
1874 pVM->rem.s.Env.exception_is_int = 0;
1875 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
1876 }
1877 else
1878 {
1879 /*
1880 * The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
1881 * We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
1882 * for int03 and into.
1883 */
1884 pVM->rem.s.Env.exception_is_int = 1;
1885 pVM->rem.s.Env.exception_next_eip = pCtx->eip + 2;
1886 /* int 3 may be generated by one-byte 0xcc */
1887 if (u8TrapNo == 3)
1888 {
1889 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xcc)
1890 pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1891 }
1892 /* int 4 may be generated by one-byte 0xce */
1893 else if (u8TrapNo == 4)
1894 {
1895 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xce)
1896 pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1897 }
1898 }
1899
1900 /* get error code and cr2 if needed. */
1901 switch (u8TrapNo)
1902 {
1903 case 0x0e:
1904 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
1905 /* fallthru */
1906 case 0x0a: case 0x0b: case 0x0c: case 0x0d:
1907 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
1908 break;
1909
1910 case 0x11: case 0x08:
1911 default:
1912 pVM->rem.s.Env.error_code = 0;
1913 break;
1914 }
1915
1916 /*
1917 * We can now reset the active trap since the recompiler is gonna have a go at it.
1918 */
1919 rc = TRPMResetTrap(pVM);
1920 AssertRC(rc);
1921 Log2(("REMR3State: trap=%02x errcd=%VGv cr2=%VGv nexteip=%VGv%s\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.error_code,
1922 pVM->rem.s.Env.cr[2], pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
1923 }
1924
1925 /*
1926 * Clear old interrupt request flags; Check for pending hardware interrupts.
1927 * (See @remark for why we don't check for other FFs.)
1928 */
1929 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
1930 if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
1931 || VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
1932 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
1933
1934 /*
1935 * We're now in REM mode.
1936 */
1937 pVM->rem.s.fInREM = true;
1938 pVM->rem.s.fInStateSync = false;
1939 pVM->rem.s.cCanExecuteRaw = 0;
1940 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
1941 Log2(("REMR3State: returns VINF_SUCCESS\n"));
1942 return VINF_SUCCESS;
1943}
1944
1945
1946/**
1947 * Syncs back changes in the REM state to the the VM state.
1948 *
1949 * This must be called after invoking REMR3Run().
1950 * Calling it several times in a row is not permitted.
1951 *
1952 * @returns VBox status code.
1953 *
1954 * @param pVM VM Handle.
1955 */
1956REMR3DECL(int) REMR3StateBack(PVM pVM)
1957{
1958 Log2(("REMR3StateBack:\n"));
1959 Assert(pVM->rem.s.fInREM);
1960 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
1961 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
1962
1963 /*
1964 * Copy back the registers.
1965 * This is done in the order they are declared in the CPUMCTX structure.
1966 */
1967
1968 /** @todo FOP */
1969 /** @todo FPUIP */
1970 /** @todo CS */
1971 /** @todo FPUDP */
1972 /** @todo DS */
1973 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
1974 pCtx->fpu.MXCSR = 0;
1975 pCtx->fpu.MXCSR_MASK = 0;
1976
1977 /** @todo check if FPU/XMM was actually used in the recompiler */
1978 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
1979//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
1980
1981 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
1982 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
1983 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
1984 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
1985 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
1986 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
1987 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
1988
1989 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
1990 pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
1991
1992#ifdef VBOX_WITH_STATISTICS
1993 if (pVM->rem.s.Env.segs[R_SS].newselector)
1994 {
1995 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
1996 }
1997 if (pVM->rem.s.Env.segs[R_GS].newselector)
1998 {
1999 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
2000 }
2001 if (pVM->rem.s.Env.segs[R_FS].newselector)
2002 {
2003 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
2004 }
2005 if (pVM->rem.s.Env.segs[R_ES].newselector)
2006 {
2007 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
2008 }
2009 if (pVM->rem.s.Env.segs[R_DS].newselector)
2010 {
2011 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2012 }
2013 if (pVM->rem.s.Env.segs[R_CS].newselector)
2014 {
2015 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2016 }
2017#endif
2018 pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2019 pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2020 pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2021 pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2022 pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2023
2024 pCtx->eip = pVM->rem.s.Env.eip;
2025 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2026
2027 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2028 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2029 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2030 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2031
2032 pCtx->dr0 = pVM->rem.s.Env.dr[0];
2033 pCtx->dr1 = pVM->rem.s.Env.dr[1];
2034 pCtx->dr2 = pVM->rem.s.Env.dr[2];
2035 pCtx->dr3 = pVM->rem.s.Env.dr[3];
2036 pCtx->dr4 = pVM->rem.s.Env.dr[4];
2037 pCtx->dr5 = pVM->rem.s.Env.dr[5];
2038 pCtx->dr6 = pVM->rem.s.Env.dr[6];
2039 pCtx->dr7 = pVM->rem.s.Env.dr[7];
2040
2041 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2042 if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2043 {
2044 pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2045 STAM_COUNTER_INC(&gStatREMGDTChange);
2046 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2047 }
2048
2049 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2050 if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2051 {
2052 pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2053 STAM_COUNTER_INC(&gStatREMIDTChange);
2054 VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2055 }
2056
2057 if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2058 {
2059 pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2060 STAM_COUNTER_INC(&gStatREMLDTRChange);
2061 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2062 }
2063 if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2064 {
2065 pCtx->tr = pVM->rem.s.Env.tr.selector;
2066 STAM_COUNTER_INC(&gStatREMTRChange);
2067 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2068 }
2069
2070 /** @todo These values could still be out of sync! */
2071 pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2072 pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2073 /** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2074 pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2075
2076 pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2077 pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2078 pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2079
2080 pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2081 pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2082 pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2083
2084 pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2085 pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2086 pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2087
2088 pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2089 pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2090 pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2091
2092 pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2093 pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2094 pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2095
2096 pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2097 pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2098 pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2099
2100 pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2101 pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2102 pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2103
2104 /* Sysenter MSR */
2105 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2106 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2107 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2108
2109 remR3TrapClear(pVM);
2110
2111 /*
2112 * Check for traps.
2113 */
2114 if ( pVM->rem.s.Env.exception_index >= 0
2115 && pVM->rem.s.Env.exception_index < 256)
2116 {
2117 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2118 int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, (pVM->rem.s.Env.exception_is_int) ? TRPM_SOFTWARE_INT : TRPM_HARDWARE_INT);
2119 AssertRC(rc);
2120 switch (pVM->rem.s.Env.exception_index)
2121 {
2122 case 0x0e:
2123 TRPMSetFaultAddress(pVM, pCtx->cr2);
2124 /* fallthru */
2125 case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2126 case 0x11: case 0x08: /* 0 */
2127 TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2128 break;
2129 }
2130
2131 }
2132
2133 /*
2134 * We're not longer in REM mode.
2135 */
2136 pVM->rem.s.fInREM = false;
2137 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2138 Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2139 return VINF_SUCCESS;
2140}
2141
2142
2143/**
2144 * This is called by the disassembler when it wants to update the cpu state
2145 * before for instance doing a register dump.
2146 */
2147static void remR3StateUpdate(PVM pVM)
2148{
2149 Assert(pVM->rem.s.fInREM);
2150 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2151
2152 /*
2153 * Copy back the registers.
2154 * This is done in the order they are declared in the CPUMCTX structure.
2155 */
2156
2157 /** @todo FOP */
2158 /** @todo FPUIP */
2159 /** @todo CS */
2160 /** @todo FPUDP */
2161 /** @todo DS */
2162 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2163 pCtx->fpu.MXCSR = 0;
2164 pCtx->fpu.MXCSR_MASK = 0;
2165
2166 /** @todo check if FPU/XMM was actually used in the recompiler */
2167 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2168//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2169
2170 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2171 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2172 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2173 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2174 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2175 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2176 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2177
2178 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2179 pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2180
2181 pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2182 pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2183 pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2184 pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2185 pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2186
2187 pCtx->eip = pVM->rem.s.Env.eip;
2188 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2189
2190 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2191 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2192 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2193 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2194
2195 pCtx->dr0 = pVM->rem.s.Env.dr[0];
2196 pCtx->dr1 = pVM->rem.s.Env.dr[1];
2197 pCtx->dr2 = pVM->rem.s.Env.dr[2];
2198 pCtx->dr3 = pVM->rem.s.Env.dr[3];
2199 pCtx->dr4 = pVM->rem.s.Env.dr[4];
2200 pCtx->dr5 = pVM->rem.s.Env.dr[5];
2201 pCtx->dr6 = pVM->rem.s.Env.dr[6];
2202 pCtx->dr7 = pVM->rem.s.Env.dr[7];
2203
2204 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2205 if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2206 {
2207 pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2208 STAM_COUNTER_INC(&gStatREMGDTChange);
2209 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2210 }
2211
2212 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2213 if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2214 {
2215 pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2216 STAM_COUNTER_INC(&gStatREMIDTChange);
2217 VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2218 }
2219
2220 if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2221 {
2222 pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2223 STAM_COUNTER_INC(&gStatREMLDTRChange);
2224 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2225 }
2226 if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2227 {
2228 pCtx->tr = pVM->rem.s.Env.tr.selector;
2229 STAM_COUNTER_INC(&gStatREMTRChange);
2230 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2231 }
2232
2233 /** @todo These values could still be out of sync! */
2234 pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2235 pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2236 /** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2237 pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2238
2239 pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2240 pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2241 pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2242
2243 pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2244 pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2245 pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2246
2247 pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2248 pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2249 pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2250
2251 pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2252 pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2253 pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2254
2255 pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2256 pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2257 pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2258
2259 pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2260 pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2261 pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2262
2263 pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2264 pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2265 pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2266
2267 /* Sysenter MSR */
2268 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2269 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2270 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2271}
2272
2273
2274/**
2275 * Update the VMM state information if we're currently in REM.
2276 *
2277 * This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2278 * we're currently executing in REM and the VMM state is invalid. This method will of
2279 * course check that we're executing in REM before syncing any data over to the VMM.
2280 *
2281 * @param pVM The VM handle.
2282 */
2283REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2284{
2285 if (pVM->rem.s.fInREM)
2286 remR3StateUpdate(pVM);
2287}
2288
2289
2290#undef LOG_GROUP
2291#define LOG_GROUP LOG_GROUP_REM
2292
2293
2294/**
2295 * Notify the recompiler about Address Gate 20 state change.
2296 *
2297 * This notification is required since A20 gate changes are
2298 * initialized from a device driver and the VM might just as
2299 * well be in REM mode as in RAW mode.
2300 *
2301 * @param pVM VM handle.
2302 * @param fEnable True if the gate should be enabled.
2303 * False if the gate should be disabled.
2304 */
2305REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2306{
2307 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2308 VM_ASSERT_EMT(pVM);
2309 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2310}
2311
2312
2313/**
2314 * Replays the invalidated recorded pages.
2315 * Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2316 *
2317 * @param pVM VM handle.
2318 */
2319REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2320{
2321 VM_ASSERT_EMT(pVM);
2322
2323 /*
2324 * Sync the required registers.
2325 */
2326 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2327 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2328 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2329 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2330
2331 /*
2332 * Replay the flushes.
2333 */
2334 pVM->rem.s.fIgnoreInvlPg = true;
2335 RTUINT i;
2336 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2337 {
2338 Log2(("REMR3ReplayInvalidatedPages: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2339 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2340 }
2341 pVM->rem.s.fIgnoreInvlPg = false;
2342 pVM->rem.s.cInvalidatedPages = 0;
2343}
2344
2345
2346/**
2347 * Replays the invalidated recorded pages.
2348 * Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2349 *
2350 * @param pVM VM handle.
2351 */
2352REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2353{
2354 LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2355 VM_ASSERT_EMT(pVM);
2356
2357 /*
2358 * Replay the flushes.
2359 */
2360 RTUINT i;
2361 const RTUINT c = pVM->rem.s.cHandlerNotifications;
2362 pVM->rem.s.cHandlerNotifications = 0;
2363 for (i = 0; i < c; i++)
2364 {
2365 PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2366 switch (pRec->enmKind)
2367 {
2368 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2369 REMR3NotifyHandlerPhysicalRegister(pVM,
2370 pRec->u.PhysicalRegister.enmType,
2371 pRec->u.PhysicalRegister.GCPhys,
2372 pRec->u.PhysicalRegister.cb,
2373 pRec->u.PhysicalRegister.fHasHCHandler);
2374 break;
2375
2376 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2377 REMR3NotifyHandlerPhysicalDeregister(pVM,
2378 pRec->u.PhysicalDeregister.enmType,
2379 pRec->u.PhysicalDeregister.GCPhys,
2380 pRec->u.PhysicalDeregister.cb,
2381 pRec->u.PhysicalDeregister.fHasHCHandler,
2382 pRec->u.PhysicalDeregister.fRestoreAsRAM);
2383 break;
2384
2385 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2386 REMR3NotifyHandlerPhysicalModify(pVM,
2387 pRec->u.PhysicalModify.enmType,
2388 pRec->u.PhysicalModify.GCPhysOld,
2389 pRec->u.PhysicalModify.GCPhysNew,
2390 pRec->u.PhysicalModify.cb,
2391 pRec->u.PhysicalModify.fHasHCHandler,
2392 pRec->u.PhysicalModify.fRestoreAsRAM);
2393 break;
2394
2395 default:
2396 AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2397 break;
2398 }
2399 }
2400}
2401
2402
2403/**
2404 * Notify REM about changed code page.
2405 *
2406 * @returns VBox status code.
2407 * @param pVM VM handle.
2408 * @param pvCodePage Code page address
2409 */
2410REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2411{
2412 int rc;
2413 RTGCPHYS PhysGC;
2414 uint64_t flags;
2415
2416 VM_ASSERT_EMT(pVM);
2417
2418 /*
2419 * Get the physical page address.
2420 */
2421 rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2422 if (rc == VINF_SUCCESS)
2423 {
2424 /*
2425 * Sync the required registers and flush the whole page.
2426 * (Easier to do the whole page than notifying it about each physical
2427 * byte that was changed.
2428 */
2429 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2430 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2431 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2432 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2433
2434 tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2435 }
2436 return VINF_SUCCESS;
2437}
2438
2439/**
2440 * Notification about a successful MMR3PhysRegister() call.
2441 *
2442 * @param pVM VM handle.
2443 * @param GCPhys The physical address the RAM.
2444 * @param cb Size of the memory.
2445 * @param pvRam The HC address of the RAM.
2446 * @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2447 */
2448REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
2449{
2450 Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2451 VM_ASSERT_EMT(pVM);
2452
2453 /*
2454 * Validate input - we trust the caller.
2455 */
2456 Assert(!GCPhys || pvRam);
2457 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2458 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2459 Assert(cb);
2460 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2461
2462 /*
2463 * Base ram?
2464 */
2465 if (!GCPhys)
2466 {
2467 phys_ram_size = cb;
2468 phys_ram_dirty_size = cb >> PAGE_SHIFT;
2469#ifndef VBOX_STRICT
2470 phys_ram_dirty = MMR3HeapAlloc(pVM, MM_TAG_REM, phys_ram_dirty_size);
2471 AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", phys_ram_dirty_size));
2472#else /* VBOX_STRICT: allocate a full map and make the out of bounds pages invalid. */
2473 phys_ram_dirty = RTMemPageAlloc(_4G >> PAGE_SHIFT);
2474 AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", _4G >> PAGE_SHIFT));
2475 uint32_t cbBitmap = RT_ALIGN_32(phys_ram_dirty_size, PAGE_SIZE);
2476 int rc = RTMemProtect(phys_ram_dirty + cbBitmap, (_4G >> PAGE_SHIFT) - cbBitmap, RTMEM_PROT_NONE);
2477 AssertRC(rc);
2478 phys_ram_dirty += cbBitmap - phys_ram_dirty_size;
2479#endif
2480 memset(phys_ram_dirty, 0xff, phys_ram_dirty_size);
2481 }
2482
2483 /*
2484 * Register the ram.
2485 */
2486 Assert(!pVM->rem.s.fIgnoreAll);
2487 pVM->rem.s.fIgnoreAll = true;
2488
2489 if (!GCPhys)
2490 cpu_register_physical_memory(GCPhys, cb, GCPhys | IO_MEM_RAM_MISSING);
2491 else
2492 {
2493 if (fFlags & MM_RAM_FLAGS_RESERVED)
2494 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2495 else
2496 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2497 }
2498 Assert(pVM->rem.s.fIgnoreAll);
2499 pVM->rem.s.fIgnoreAll = false;
2500}
2501
2502
2503/**
2504 * Notification about a successful PGMR3PhysRegisterChunk() call.
2505 *
2506 * @param pVM VM handle.
2507 * @param GCPhys The physical address the RAM.
2508 * @param cb Size of the memory.
2509 * @param pvRam The HC address of the RAM.
2510 * @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2511 */
2512REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2513{
2514 Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2515 VM_ASSERT_EMT(pVM);
2516
2517 /*
2518 * Validate input - we trust the caller.
2519 */
2520 Assert(pvRam);
2521 Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2522 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2523 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2524 Assert(fFlags == 0 /* normal RAM */);
2525 Assert(!pVM->rem.s.fIgnoreAll);
2526 pVM->rem.s.fIgnoreAll = true;
2527
2528 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2529
2530 Assert(pVM->rem.s.fIgnoreAll);
2531 pVM->rem.s.fIgnoreAll = false;
2532}
2533
2534
2535/**
2536 * Grows dynamically allocated guest RAM.
2537 * Will raise a fatal error if the operation fails.
2538 *
2539 * @param physaddr The physical address.
2540 */
2541void remR3GrowDynRange(unsigned long physaddr)
2542{
2543 int rc;
2544 PVM pVM = cpu_single_env->pVM;
2545
2546 Log(("remR3GrowDynRange %VGp\n", physaddr));
2547 rc = PGM3PhysGrowRange(pVM, (RTGCPHYS)physaddr);
2548 if (VBOX_SUCCESS(rc))
2549 return;
2550
2551 LogRel(("\nUnable to allocate guest RAM chunk at %VGp\n", physaddr));
2552 cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %VGp\n", physaddr);
2553 AssertFatalFailed();
2554}
2555
2556
2557/**
2558 * Notification about a successful MMR3PhysRomRegister() call.
2559 *
2560 * @param pVM VM handle.
2561 * @param GCPhys The physical address of the ROM.
2562 * @param cb The size of the ROM.
2563 * @param pvCopy Pointer to the ROM copy.
2564 * @param fShadow Whether it's currently writable shadow ROM or normal readonly ROM.
2565 * This function will be called when ever the protection of the
2566 * shadow ROM changes (at reset and end of POST).
2567 */
2568REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)
2569{
2570 Log(("REMR3NotifyPhysRomRegister: GCPhys=%VGp cb=%d pvCopy=%p fShadow=%RTbool\n", GCPhys, cb, pvCopy, fShadow));
2571 VM_ASSERT_EMT(pVM);
2572
2573 /*
2574 * Validate input - we trust the caller.
2575 */
2576 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2577 Assert(cb);
2578 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2579 Assert(pvCopy);
2580 Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2581
2582 /*
2583 * Register the rom.
2584 */
2585 Assert(!pVM->rem.s.fIgnoreAll);
2586 pVM->rem.s.fIgnoreAll = true;
2587
2588 cpu_register_physical_memory(GCPhys, cb, GCPhys | (fShadow ? 0 : IO_MEM_ROM));
2589
2590 Log2(("%.64Vhxd\n", (char *)pvCopy + cb - 64));
2591
2592 Assert(pVM->rem.s.fIgnoreAll);
2593 pVM->rem.s.fIgnoreAll = false;
2594}
2595
2596
2597/**
2598 * Notification about a successful MMR3PhysRegister() call.
2599 *
2600 * @param pVM VM Handle.
2601 * @param GCPhys Start physical address.
2602 * @param cb The size of the range.
2603 */
2604REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2605{
2606 Log(("REMR3NotifyPhysReserve: GCPhys=%VGp cb=%d\n", GCPhys, cb));
2607 VM_ASSERT_EMT(pVM);
2608
2609 /*
2610 * Validate input - we trust the caller.
2611 */
2612 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2613 Assert(cb);
2614 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2615
2616 /*
2617 * Unassigning the memory.
2618 */
2619 Assert(!pVM->rem.s.fIgnoreAll);
2620 pVM->rem.s.fIgnoreAll = true;
2621
2622 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2623
2624 Assert(pVM->rem.s.fIgnoreAll);
2625 pVM->rem.s.fIgnoreAll = false;
2626}
2627
2628
2629/**
2630 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
2631 *
2632 * @param pVM VM Handle.
2633 * @param enmType Handler type.
2634 * @param GCPhys Handler range address.
2635 * @param cb Size of the handler range.
2636 * @param fHasHCHandler Set if the handler has a HC callback function.
2637 *
2638 * @remark MMR3PhysRomRegister assumes that this function will not apply the
2639 * Handler memory type to memory which has no HC handler.
2640 */
2641REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2642{
2643 Log(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d\n",
2644 enmType, GCPhys, cb, fHasHCHandler));
2645 VM_ASSERT_EMT(pVM);
2646 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2647 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2648
2649 if (pVM->rem.s.cHandlerNotifications)
2650 REMR3ReplayHandlerNotifications(pVM);
2651
2652 Assert(!pVM->rem.s.fIgnoreAll);
2653 pVM->rem.s.fIgnoreAll = true;
2654
2655 if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2656 cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2657 else if (fHasHCHandler)
2658 cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2659
2660 Assert(pVM->rem.s.fIgnoreAll);
2661 pVM->rem.s.fIgnoreAll = false;
2662}
2663
2664
2665/**
2666 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2667 *
2668 * @param pVM VM Handle.
2669 * @param enmType Handler type.
2670 * @param GCPhys Handler range address.
2671 * @param cb Size of the handler range.
2672 * @param fHasHCHandler Set if the handler has a HC callback function.
2673 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
2674 */
2675REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
2676{
2677 Log(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%VGp cb=%VGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool RAM=%08x\n",
2678 enmType, GCPhys, cb, fHasHCHandler, fRestoreAsRAM, MMR3PhysGetRamSize(pVM)));
2679 VM_ASSERT_EMT(pVM);
2680
2681 if (pVM->rem.s.cHandlerNotifications)
2682 REMR3ReplayHandlerNotifications(pVM);
2683
2684 Assert(!pVM->rem.s.fIgnoreAll);
2685 pVM->rem.s.fIgnoreAll = true;
2686
2687 if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2688 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2689 else if (fHasHCHandler)
2690 {
2691 if (!fRestoreAsRAM)
2692 {
2693 Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2694 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2695 }
2696 else
2697 {
2698 /* This is not perfect, but it'll do for PD monitoring... */
2699 Assert(cb == PAGE_SIZE);
2700 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2701 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2702 }
2703 }
2704
2705 Assert(pVM->rem.s.fIgnoreAll);
2706 pVM->rem.s.fIgnoreAll = false;
2707}
2708
2709
2710/**
2711 * Notification about a successful PGMR3HandlerPhysicalModify() call.
2712 *
2713 * @param pVM VM Handle.
2714 * @param enmType Handler type.
2715 * @param GCPhysOld Old handler range address.
2716 * @param GCPhysNew New handler range address.
2717 * @param cb Size of the handler range.
2718 * @param fHasHCHandler Set if the handler has a HC callback function.
2719 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
2720 */
2721REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
2722{
2723 Log(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%VGp GCPhysNew=%VGp cb=%d fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool\n",
2724 enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM));
2725 VM_ASSERT_EMT(pVM);
2726 AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2727
2728 if (pVM->rem.s.cHandlerNotifications)
2729 REMR3ReplayHandlerNotifications(pVM);
2730
2731 if (fHasHCHandler)
2732 {
2733 Assert(!pVM->rem.s.fIgnoreAll);
2734 pVM->rem.s.fIgnoreAll = true;
2735
2736 /*
2737 * Reset the old page.
2738 */
2739 if (!fRestoreAsRAM)
2740 cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2741 else
2742 {
2743 /* This is not perfect, but it'll do for PD monitoring... */
2744 Assert(cb == PAGE_SIZE);
2745 Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2746 cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2747 }
2748
2749 /*
2750 * Update the new page.
2751 */
2752 Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2753 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2754 cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2755
2756 Assert(pVM->rem.s.fIgnoreAll);
2757 pVM->rem.s.fIgnoreAll = false;
2758 }
2759}
2760
2761
2762/**
2763 * Checks if we're handling access to this page or not.
2764 *
2765 * @returns true if we're trapping access.
2766 * @returns false if we aren't.
2767 * @param pVM The VM handle.
2768 * @param GCPhys The physical address.
2769 *
2770 * @remark This function will only work correctly in VBOX_STRICT builds!
2771 */
2772REMDECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
2773{
2774#ifdef VBOX_STRICT
2775 if (pVM->rem.s.cHandlerNotifications)
2776 REMR3ReplayHandlerNotifications(pVM);
2777
2778 unsigned long off = get_phys_page_offset(GCPhys);
2779 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
2780 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
2781 || (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
2782#else
2783 return false;
2784#endif
2785}
2786
2787
2788/**
2789 * Deals with a rare case in get_phys_addr_code where the code
2790 * is being monitored.
2791 *
2792 * It could also be an MMIO page, in which case we will raise a fatal error.
2793 *
2794 * @returns The physical address corresponding to addr.
2795 * @param env The cpu environment.
2796 * @param addr The virtual address.
2797 * @param pTLBEntry The TLB entry.
2798 */
2799target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry)
2800{
2801 PVM pVM = env->pVM;
2802 if ((pTLBEntry->addr_code & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
2803 {
2804 target_ulong ret = pTLBEntry->addend + addr;
2805 AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%VGv addr_code=%VGv addend=%VGp ret=%VGp\n",
2806 (RTGCPTR)addr, (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, ret);
2807 return ret;
2808 }
2809 LogRel(("\nTrying to execute code with memory type addr_code=%VGv addend=%VGp at %VGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
2810 "*** handlers\n",
2811 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
2812 DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
2813 LogRel(("*** mmio\n"));
2814 DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
2815 LogRel(("*** phys\n"));
2816 DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
2817 cpu_abort(env, "Trying to execute code with memory type addr_code=%VGv addend=%VGp at %VGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
2818 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
2819 AssertFatalFailed();
2820}
2821
2822
2823/** Validate the physical address passed to the read functions.
2824 * Useful for finding non-guest-ram reads/writes. */
2825#if 1 /* disable if it becomes bothersome... */
2826# define VBOX_CHECK_ADDR(GCPhys) AssertMsg(PGMPhysIsGCPhysValid(cpu_single_env->pVM, (GCPhys)), ("%VGp\n", (GCPhys)))
2827#else
2828# define VBOX_CHECK_ADDR(GCPhys) do { } while (0)
2829#endif
2830
2831/**
2832 * Read guest RAM and ROM.
2833 *
2834 * @param SrcGCPhys The source address (guest physical).
2835 * @param pvDst The destination address.
2836 * @param cb Number of bytes
2837 */
2838void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb)
2839{
2840 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2841 VBOX_CHECK_ADDR(SrcGCPhys);
2842 PGMPhysRead(cpu_single_env->pVM, SrcGCPhys, pvDst, cb);
2843 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2844}
2845
2846
2847/**
2848 * Read guest RAM and ROM, unsigned 8-bit.
2849 *
2850 * @param SrcGCPhys The source address (guest physical).
2851 */
2852uint8_t remR3PhysReadU8(RTGCPHYS SrcGCPhys)
2853{
2854 uint8_t val;
2855 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2856 VBOX_CHECK_ADDR(SrcGCPhys);
2857 val = PGMR3PhysReadByte(cpu_single_env->pVM, SrcGCPhys);
2858 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2859 return val;
2860}
2861
2862
2863/**
2864 * Read guest RAM and ROM, signed 8-bit.
2865 *
2866 * @param SrcGCPhys The source address (guest physical).
2867 */
2868int8_t remR3PhysReadS8(RTGCPHYS SrcGCPhys)
2869{
2870 int8_t val;
2871 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2872 VBOX_CHECK_ADDR(SrcGCPhys);
2873 val = PGMR3PhysReadByte(cpu_single_env->pVM, SrcGCPhys);
2874 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2875 return val;
2876}
2877
2878
2879/**
2880 * Read guest RAM and ROM, unsigned 16-bit.
2881 *
2882 * @param SrcGCPhys The source address (guest physical).
2883 */
2884uint16_t remR3PhysReadU16(RTGCPHYS SrcGCPhys)
2885{
2886 uint16_t val;
2887 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2888 VBOX_CHECK_ADDR(SrcGCPhys);
2889 val = PGMR3PhysReadWord(cpu_single_env->pVM, SrcGCPhys);
2890 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2891 return val;
2892}
2893
2894
2895/**
2896 * Read guest RAM and ROM, signed 16-bit.
2897 *
2898 * @param SrcGCPhys The source address (guest physical).
2899 */
2900int16_t remR3PhysReadS16(RTGCPHYS SrcGCPhys)
2901{
2902 uint16_t val;
2903 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2904 VBOX_CHECK_ADDR(SrcGCPhys);
2905 val = PGMR3PhysReadWord(cpu_single_env->pVM, SrcGCPhys);
2906 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2907 return val;
2908}
2909
2910
2911/**
2912 * Read guest RAM and ROM, unsigned 32-bit.
2913 *
2914 * @param SrcGCPhys The source address (guest physical).
2915 */
2916uint32_t remR3PhysReadU32(RTGCPHYS SrcGCPhys)
2917{
2918 uint32_t val;
2919 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2920 VBOX_CHECK_ADDR(SrcGCPhys);
2921 val = PGMR3PhysReadDword(cpu_single_env->pVM, SrcGCPhys);
2922 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2923 return val;
2924}
2925
2926
2927/**
2928 * Read guest RAM and ROM, signed 32-bit.
2929 *
2930 * @param SrcGCPhys The source address (guest physical).
2931 */
2932int32_t remR3PhysReadS32(RTGCPHYS SrcGCPhys)
2933{
2934 int32_t val;
2935 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2936 VBOX_CHECK_ADDR(SrcGCPhys);
2937 val = PGMR3PhysReadDword(cpu_single_env->pVM, SrcGCPhys);
2938 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2939 return val;
2940}
2941
2942
2943/**
2944 * Read guest RAM and ROM, unsigned 64-bit.
2945 *
2946 * @param SrcGCPhys The source address (guest physical).
2947 */
2948uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys)
2949{
2950 uint64_t val;
2951 STAM_PROFILE_ADV_START(&gStatMemRead, a);
2952 VBOX_CHECK_ADDR(SrcGCPhys);
2953 val = PGMR3PhysReadDword(cpu_single_env->pVM, SrcGCPhys)
2954 | ((uint64_t)PGMR3PhysReadDword(cpu_single_env->pVM, SrcGCPhys + 4) << 32); /** @todo fix me! */
2955 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2956 return val;
2957}
2958
2959
2960/**
2961 * Write guest RAM.
2962 *
2963 * @param DstGCPhys The destination address (guest physical).
2964 * @param pvSrc The source address.
2965 * @param cb Number of bytes to write
2966 */
2967void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb)
2968{
2969 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
2970 VBOX_CHECK_ADDR(DstGCPhys);
2971 PGMPhysWrite(cpu_single_env->pVM, DstGCPhys, pvSrc, cb);
2972 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
2973}
2974
2975
2976/**
2977 * Write guest RAM, unsigned 8-bit.
2978 *
2979 * @param DstGCPhys The destination address (guest physical).
2980 * @param val Value
2981 */
2982void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val)
2983{
2984 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
2985 VBOX_CHECK_ADDR(DstGCPhys);
2986 PGMR3PhysWriteByte(cpu_single_env->pVM, DstGCPhys, val);
2987 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
2988}
2989
2990
2991/**
2992 * Write guest RAM, unsigned 8-bit.
2993 *
2994 * @param DstGCPhys The destination address (guest physical).
2995 * @param val Value
2996 */
2997void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val)
2998{
2999 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3000 VBOX_CHECK_ADDR(DstGCPhys);
3001 PGMR3PhysWriteWord(cpu_single_env->pVM, DstGCPhys, val);
3002 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3003}
3004
3005
3006/**
3007 * Write guest RAM, unsigned 32-bit.
3008 *
3009 * @param DstGCPhys The destination address (guest physical).
3010 * @param val Value
3011 */
3012void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val)
3013{
3014 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3015 VBOX_CHECK_ADDR(DstGCPhys);
3016 PGMR3PhysWriteDword(cpu_single_env->pVM, DstGCPhys, val);
3017 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3018}
3019
3020
3021/**
3022 * Write guest RAM, unsigned 64-bit.
3023 *
3024 * @param DstGCPhys The destination address (guest physical).
3025 * @param val Value
3026 */
3027void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val)
3028{
3029 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3030 VBOX_CHECK_ADDR(DstGCPhys);
3031 PGMR3PhysWriteDword(cpu_single_env->pVM, DstGCPhys, (uint32_t)val); /** @todo add U64 interface. */
3032 PGMR3PhysWriteDword(cpu_single_env->pVM, DstGCPhys + 4, val >> 32);
3033 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3034}
3035
3036#undef LOG_GROUP
3037#define LOG_GROUP LOG_GROUP_REM_MMIO
3038
3039/** Read MMIO memory. */
3040static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3041{
3042 uint32_t u32 = 0;
3043 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3044 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3045 Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32));
3046 return u32;
3047}
3048
3049/** Read MMIO memory. */
3050static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3051{
3052 uint32_t u32 = 0;
3053 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3054 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3055 Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32));
3056 return u32;
3057}
3058
3059/** Read MMIO memory. */
3060static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3061{
3062 uint32_t u32 = 0;
3063 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3064 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3065 Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32));
3066 return u32;
3067}
3068
3069/** Write to MMIO memory. */
3070static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3071{
3072 Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3073 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3074 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3075}
3076
3077/** Write to MMIO memory. */
3078static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3079{
3080 Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3081 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3082 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3083}
3084
3085/** Write to MMIO memory. */
3086static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3087{
3088 Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3089 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3090 AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3091}
3092
3093
3094#undef LOG_GROUP
3095#define LOG_GROUP LOG_GROUP_REM_HANDLER
3096
3097/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3098
3099static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3100{
3101 Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys));
3102 uint8_t u8;
3103 PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3104 return u8;
3105}
3106
3107static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3108{
3109 Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys));
3110 uint16_t u16;
3111 PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3112 return u16;
3113}
3114
3115static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3116{
3117 Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys));
3118 uint32_t u32;
3119 PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3120 return u32;
3121}
3122
3123static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3124{
3125 Log2(("remR3HandlerWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3126 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3127}
3128
3129static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3130{
3131 Log2(("remR3HandlerWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3132 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3133}
3134
3135static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3136{
3137 Log2(("remR3HandlerWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3138 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3139}
3140
3141/* -+- disassembly -+- */
3142
3143#undef LOG_GROUP
3144#define LOG_GROUP LOG_GROUP_REM_DISAS
3145
3146
3147/**
3148 * Enables or disables singled stepped disassembly.
3149 *
3150 * @returns VBox status code.
3151 * @param pVM VM handle.
3152 * @param fEnable To enable set this flag, to disable clear it.
3153 */
3154static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3155{
3156 LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3157 VM_ASSERT_EMT(pVM);
3158
3159 if (fEnable)
3160 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3161 else
3162 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3163 return VINF_SUCCESS;
3164}
3165
3166
3167/**
3168 * Enables or disables singled stepped disassembly.
3169 *
3170 * @returns VBox status code.
3171 * @param pVM VM handle.
3172 * @param fEnable To enable set this flag, to disable clear it.
3173 */
3174REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3175{
3176 PVMREQ pReq;
3177 int rc;
3178
3179 LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3180 if (VM_IS_EMT(pVM))
3181 return remR3DisasEnableStepping(pVM, fEnable);
3182
3183 rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3184 AssertRC(rc);
3185 if (VBOX_SUCCESS(rc))
3186 rc = pReq->iStatus;
3187 VMR3ReqFree(pReq);
3188 return rc;
3189}
3190
3191
3192#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
3193/**
3194 * External Debugger Command: .remstep [on|off|1|0]
3195 */
3196static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3197{
3198 bool fEnable;
3199 int rc;
3200
3201 /* print status */
3202 if (cArgs == 0)
3203 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3204 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3205
3206 /* convert the argument and change the mode. */
3207 rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3208 if (VBOX_FAILURE(rc))
3209 return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3210 rc = REMR3DisasEnableStepping(pVM, fEnable);
3211 if (VBOX_FAILURE(rc))
3212 return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3213 return rc;
3214}
3215#endif
3216
3217
3218/**
3219 * Disassembles n instructions and prints them to the log.
3220 *
3221 * @returns Success indicator.
3222 * @param env Pointer to the recompiler CPU structure.
3223 * @param f32BitCode Indicates that whether or not the code should
3224 * be disassembled as 16 or 32 bit. If -1 the CS
3225 * selector will be inspected.
3226 * @param nrInstructions Nr of instructions to disassemble
3227 * @param pszPrefix
3228 * @remark not currently used for anything but ad-hoc debugging.
3229 */
3230bool remR3DisasBlock(CPUState *env, int f32BitCode, int nrInstructions, char *pszPrefix)
3231{
3232 int i;
3233
3234 /*
3235 * Determin 16/32 bit mode.
3236 */
3237 if (f32BitCode == -1)
3238 f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3239
3240 /*
3241 * Convert cs:eip to host context address.
3242 * We don't care to much about cross page correctness presently.
3243 */
3244 RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3245 void *pvPC;
3246 if (f32BitCode && (env->cr[0] & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG))
3247 {
3248 /* convert eip to physical address. */
3249 int rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,
3250 GCPtrPC,
3251 env->cr[3],
3252 env->cr[4] & (X86_CR4_PSE | X86_CR4_PAE), /** @todo add longmode flag */
3253 &pvPC);
3254 if (VBOX_FAILURE(rc))
3255 {
3256 if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3257 return false;
3258 pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3259 + (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3260 }
3261 }
3262 else
3263 {
3264 /* physical address */
3265 int rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions * 16, &pvPC);
3266 if (VBOX_FAILURE(rc))
3267 return false;
3268 }
3269
3270 /*
3271 * Disassemble.
3272 */
3273 RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3274 DISCPUSTATE Cpu;
3275 Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3276 Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3277 //Cpu.dwUserData[0] = (uintptr_t)pVM;
3278 //Cpu.dwUserData[1] = (uintptr_t)pvPC;
3279 //Cpu.dwUserData[2] = GCPtrPC;
3280
3281 for (i=0;i<nrInstructions;i++)
3282 {
3283 char szOutput[256];
3284 uint32_t cbOp;
3285 if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3286 return false;
3287 if (pszPrefix)
3288 Log(("%s: %s", pszPrefix, szOutput));
3289 else
3290 Log(("%s", szOutput));
3291
3292 pvPC += cbOp;
3293 }
3294 return true;
3295}
3296
3297
3298/** @todo need to test the new code, using the old code in the mean while. */
3299#define USE_OLD_DUMP_AND_DISASSEMBLY
3300
3301/**
3302 * Disassembles one instruction and prints it to the log.
3303 *
3304 * @returns Success indicator.
3305 * @param env Pointer to the recompiler CPU structure.
3306 * @param f32BitCode Indicates that whether or not the code should
3307 * be disassembled as 16 or 32 bit. If -1 the CS
3308 * selector will be inspected.
3309 * @param pszPrefix
3310 */
3311bool remR3DisasInstr(CPUState *env, int f32BitCode, char *pszPrefix)
3312{
3313#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3314 PVM pVM = env->pVM;
3315
3316 /*
3317 * Determin 16/32 bit mode.
3318 */
3319 if (f32BitCode == -1)
3320 f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3321
3322 /*
3323 * Log registers
3324 */
3325 if (LogIs2Enabled())
3326 {
3327 remR3StateUpdate(pVM);
3328 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3329 }
3330
3331 /*
3332 * Convert cs:eip to host context address.
3333 * We don't care to much about cross page correctness presently.
3334 */
3335 RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3336 void *pvPC;
3337 if ((env->cr[0] & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG))
3338 {
3339 /* convert eip to physical address. */
3340 int rc = PGMPhysGCPtr2HCPtrByGstCR3(pVM,
3341 GCPtrPC,
3342 env->cr[3],
3343 env->cr[4] & (X86_CR4_PSE | X86_CR4_PAE),
3344 &pvPC);
3345 if (VBOX_FAILURE(rc))
3346 {
3347 if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3348 return false;
3349 pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3350 + (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3351 }
3352 }
3353 else
3354 {
3355
3356 /* physical address */
3357 int rc = PGMPhysGCPhys2HCPtr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3358 if (VBOX_FAILURE(rc))
3359 return false;
3360 }
3361
3362 /*
3363 * Disassemble.
3364 */
3365 RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3366 DISCPUSTATE Cpu;
3367 Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3368 Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3369 //Cpu.dwUserData[0] = (uintptr_t)pVM;
3370 //Cpu.dwUserData[1] = (uintptr_t)pvPC;
3371 //Cpu.dwUserData[2] = GCPtrPC;
3372 char szOutput[256];
3373 uint32_t cbOp;
3374 if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3375 return false;
3376
3377 if (!f32BitCode)
3378 {
3379 if (pszPrefix)
3380 Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3381 else
3382 Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3383 }
3384 else
3385 {
3386 if (pszPrefix)
3387 Log(("%s: %s", pszPrefix, szOutput));
3388 else
3389 Log(("%s", szOutput));
3390 }
3391 return true;
3392
3393#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3394 PVM pVM = env->pVM;
3395 const bool fLog = LogIsEnabled();
3396 const bool fLog2 = LogIs2Enabled();
3397 int rc = VINF_SUCCESS;
3398
3399 /*
3400 * Don't bother if there ain't any log output to do.
3401 */
3402 if (!fLog && !fLog2)
3403 return true;
3404
3405 /*
3406 * Update the state so DBGF reads the correct register values.
3407 */
3408 remR3StateUpdate(pVM);
3409
3410 /*
3411 * Log registers if requested.
3412 */
3413 if (!fLog2)
3414 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3415
3416 /*
3417 * Disassemble to log.
3418 */
3419 if (fLog)
3420 rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3421
3422 return VBOX_SUCCESS(rc);
3423#endif
3424}
3425
3426
3427/**
3428 * Disassemble recompiled code.
3429 *
3430 * @param phFileIgnored Ignored, logfile usually.
3431 * @param pvCode Pointer to the code block.
3432 * @param cb Size of the code block.
3433 */
3434void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
3435{
3436 if (LogIs2Enabled())
3437 {
3438 unsigned off = 0;
3439 char szOutput[256];
3440 DISCPUSTATE Cpu;
3441
3442 memset(&Cpu, 0, sizeof(Cpu));
3443#ifdef RT_ARCH_X86
3444 Cpu.mode = CPUMODE_32BIT;
3445#else
3446 Cpu.mode = CPUMODE_64BIT;
3447#endif
3448
3449 RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3450 while (off < cb)
3451 {
3452 uint32_t cbInstr;
3453 if (DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput))
3454 RTLogPrintf("%s", szOutput);
3455 else
3456 {
3457 RTLogPrintf("disas error\n");
3458 cbInstr = 1;
3459#ifdef RT_ARCH_AMD64 /** @todo remove when DISInstr starts supporing 64-bit code. */
3460 break;
3461#endif
3462 }
3463 off += cbInstr;
3464 }
3465 }
3466 NOREF(phFileIgnored);
3467}
3468
3469
3470/**
3471 * Disassemble guest code.
3472 *
3473 * @param phFileIgnored Ignored, logfile usually.
3474 * @param uCode The guest address of the code to disassemble. (flat?)
3475 * @param cb Number of bytes to disassemble.
3476 * @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3477 */
3478void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3479{
3480 if (LogIs2Enabled())
3481 {
3482 PVM pVM = cpu_single_env->pVM;
3483
3484 /*
3485 * Update the state so DBGF reads the correct register values (flags).
3486 */
3487 remR3StateUpdate(pVM);
3488
3489 /*
3490 * Do the disassembling.
3491 */
3492 RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3493 RTSEL cs = cpu_single_env->segs[R_CS].selector;
3494 RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3495 for (;;)
3496 {
3497 char szBuf[256];
3498 uint32_t cbInstr;
3499 int rc = DBGFR3DisasInstrEx(pVM,
3500 cs,
3501 eip,
3502 0,
3503 szBuf, sizeof(szBuf),
3504 &cbInstr);
3505 if (VBOX_SUCCESS(rc))
3506 RTLogPrintf("%VGp %s\n", uCode, szBuf);
3507 else
3508 {
3509 RTLogPrintf("%VGp %04x:%VGp: %s\n", uCode, cs, eip, szBuf);
3510 cbInstr = 1;
3511 }
3512
3513 /* next */
3514 if (cb <= cbInstr)
3515 break;
3516 cb -= cbInstr;
3517 uCode += cbInstr;
3518 eip += cbInstr;
3519 }
3520 }
3521 NOREF(phFileIgnored);
3522}
3523
3524
3525/**
3526 * Looks up a guest symbol.
3527 *
3528 * @returns Pointer to symbol name. This is a static buffer.
3529 * @param orig_addr The address in question.
3530 */
3531const char *lookup_symbol(target_ulong orig_addr)
3532{
3533 RTGCINTPTR off = 0;
3534 DBGFSYMBOL Sym;
3535 PVM pVM = cpu_single_env->pVM;
3536 int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3537 if (VBOX_SUCCESS(rc))
3538 {
3539 static char szSym[sizeof(Sym.szName) + 48];
3540 if (!off)
3541 RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3542 else if (off > 0)
3543 RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3544 else
3545 RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3546 return szSym;
3547 }
3548 return "<N/A>";
3549}
3550
3551
3552#undef LOG_GROUP
3553#define LOG_GROUP LOG_GROUP_REM
3554
3555
3556/* -+- FF notifications -+- */
3557
3558
3559/**
3560 * Notification about a pending interrupt.
3561 *
3562 * @param pVM VM Handle.
3563 * @param u8Interrupt Interrupt
3564 * @thread The emulation thread.
3565 */
3566REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3567{
3568 Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3569 pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3570}
3571
3572/**
3573 * Notification about a pending interrupt.
3574 *
3575 * @returns Pending interrupt or REM_NO_PENDING_IRQ
3576 * @param pVM VM Handle.
3577 * @thread The emulation thread.
3578 */
3579REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3580{
3581 return pVM->rem.s.u32PendingInterrupt;
3582}
3583
3584/**
3585 * Notification about the interrupt FF being set.
3586 *
3587 * @param pVM VM Handle.
3588 * @thread The emulation thread.
3589 */
3590REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3591{
3592 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3593 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3594 if (pVM->rem.s.fInREM)
3595 {
3596 if (VM_IS_EMT(pVM))
3597 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3598 else
3599 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3600 }
3601}
3602
3603
3604/**
3605 * Notification about the interrupt FF being set.
3606 *
3607 * @param pVM VM Handle.
3608 * @thread The emulation thread.
3609 */
3610REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3611{
3612 LogFlow(("REMR3NotifyInterruptClear:\n"));
3613 VM_ASSERT_EMT(pVM);
3614 if (pVM->rem.s.fInREM)
3615 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3616}
3617
3618
3619/**
3620 * Notification about pending timer(s).
3621 *
3622 * @param pVM VM Handle.
3623 * @thread Any.
3624 */
3625REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3626{
3627#ifndef DEBUG_bird
3628 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3629#endif
3630 if (pVM->rem.s.fInREM)
3631 {
3632 if (VM_IS_EMT(pVM))
3633 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3634 else
3635 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3636 }
3637}
3638
3639
3640/**
3641 * Notification about pending DMA transfers.
3642 *
3643 * @param pVM VM Handle.
3644 * @thread Any.
3645 */
3646REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3647{
3648 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3649 if (pVM->rem.s.fInREM)
3650 {
3651 if (VM_IS_EMT(pVM))
3652 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3653 else
3654 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3655 }
3656}
3657
3658
3659/**
3660 * Notification about pending timer(s).
3661 *
3662 * @param pVM VM Handle.
3663 * @thread Any.
3664 */
3665REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3666{
3667 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3668 if (pVM->rem.s.fInREM)
3669 {
3670 if (VM_IS_EMT(pVM))
3671 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3672 else
3673 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3674 }
3675}
3676
3677
3678/**
3679 * Notification about pending FF set by an external thread.
3680 *
3681 * @param pVM VM handle.
3682 * @thread Any.
3683 */
3684REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3685{
3686 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3687 if (pVM->rem.s.fInREM)
3688 {
3689 if (VM_IS_EMT(pVM))
3690 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3691 else
3692 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3693 }
3694}
3695
3696
3697#ifdef VBOX_WITH_STATISTICS
3698void remR3ProfileStart(int statcode)
3699{
3700 STAMPROFILEADV *pStat;
3701 switch(statcode)
3702 {
3703 case STATS_EMULATE_SINGLE_INSTR:
3704 pStat = &gStatExecuteSingleInstr;
3705 break;
3706 case STATS_QEMU_COMPILATION:
3707 pStat = &gStatCompilationQEmu;
3708 break;
3709 case STATS_QEMU_RUN_EMULATED_CODE:
3710 pStat = &gStatRunCodeQEmu;
3711 break;
3712 case STATS_QEMU_TOTAL:
3713 pStat = &gStatTotalTimeQEmu;
3714 break;
3715 case STATS_QEMU_RUN_TIMERS:
3716 pStat = &gStatTimers;
3717 break;
3718 case STATS_TLB_LOOKUP:
3719 pStat= &gStatTBLookup;
3720 break;
3721 case STATS_IRQ_HANDLING:
3722 pStat= &gStatIRQ;
3723 break;
3724 case STATS_RAW_CHECK:
3725 pStat = &gStatRawCheck;
3726 break;
3727
3728 default:
3729 AssertMsgFailed(("unknown stat %d\n", statcode));
3730 return;
3731 }
3732 STAM_PROFILE_ADV_START(pStat, a);
3733}
3734
3735
3736void remR3ProfileStop(int statcode)
3737{
3738 STAMPROFILEADV *pStat;
3739 switch(statcode)
3740 {
3741 case STATS_EMULATE_SINGLE_INSTR:
3742 pStat = &gStatExecuteSingleInstr;
3743 break;
3744 case STATS_QEMU_COMPILATION:
3745 pStat = &gStatCompilationQEmu;
3746 break;
3747 case STATS_QEMU_RUN_EMULATED_CODE:
3748 pStat = &gStatRunCodeQEmu;
3749 break;
3750 case STATS_QEMU_TOTAL:
3751 pStat = &gStatTotalTimeQEmu;
3752 break;
3753 case STATS_QEMU_RUN_TIMERS:
3754 pStat = &gStatTimers;
3755 break;
3756 case STATS_TLB_LOOKUP:
3757 pStat= &gStatTBLookup;
3758 break;
3759 case STATS_IRQ_HANDLING:
3760 pStat= &gStatIRQ;
3761 break;
3762 case STATS_RAW_CHECK:
3763 pStat = &gStatRawCheck;
3764 break;
3765 default:
3766 AssertMsgFailed(("unknown stat %d\n", statcode));
3767 return;
3768 }
3769 STAM_PROFILE_ADV_STOP(pStat, a);
3770}
3771#endif
3772
3773/**
3774 * Raise an RC, force rem exit.
3775 *
3776 * @param pVM VM handle.
3777 * @param rc The rc.
3778 */
3779void remR3RaiseRC(PVM pVM, int rc)
3780{
3781 Log(("remR3RaiseRC: rc=%Vrc\n", rc));
3782 Assert(pVM->rem.s.fInREM);
3783 VM_ASSERT_EMT(pVM);
3784 pVM->rem.s.rc = rc;
3785 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
3786}
3787
3788
3789/* -+- timers -+- */
3790
3791uint64_t cpu_get_tsc(CPUX86State *env)
3792{
3793 STAM_COUNTER_INC(&gStatCpuGetTSC);
3794 return TMCpuTickGet(env->pVM);
3795}
3796
3797
3798/* -+- interrupts -+- */
3799
3800void cpu_set_ferr(CPUX86State *env)
3801{
3802 int rc = PDMIsaSetIrq(env->pVM, 13, 1);
3803 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
3804}
3805
3806int cpu_get_pic_interrupt(CPUState *env)
3807{
3808 uint8_t u8Interrupt;
3809 int rc;
3810
3811 /* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
3812 * In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
3813 * with the (a)pic.
3814 */
3815 /** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
3816 /** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
3817 * if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
3818 * remove this kludge. */
3819 if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
3820 {
3821 rc = VINF_SUCCESS;
3822 Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
3823 u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
3824 env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
3825 }
3826 else
3827 rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
3828
3829 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Vrc\n", u8Interrupt, rc));
3830 if (VBOX_SUCCESS(rc))
3831 {
3832 if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3833 env->interrupt_request |= CPU_INTERRUPT_HARD;
3834 return u8Interrupt;
3835 }
3836 return -1;
3837}
3838
3839
3840/* -+- local apic -+- */
3841
3842void cpu_set_apic_base(CPUX86State *env, uint64_t val)
3843{
3844 int rc = PDMApicSetBase(env->pVM, val);
3845 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Vrc\n", val, rc)); NOREF(rc);
3846}
3847
3848uint64_t cpu_get_apic_base(CPUX86State *env)
3849{
3850 uint64_t u64;
3851 int rc = PDMApicGetBase(env->pVM, &u64);
3852 if (VBOX_SUCCESS(rc))
3853 {
3854 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
3855 return u64;
3856 }
3857 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Vrc)\n", rc));
3858 return 0;
3859}
3860
3861void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
3862{
3863 int rc = PDMApicSetTPR(env->pVM, val);
3864 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Vrc\n", val, rc)); NOREF(rc);
3865}
3866
3867uint8_t cpu_get_apic_tpr(CPUX86State *env)
3868{
3869 uint8_t u8;
3870 int rc = PDMApicGetTPR(env->pVM, &u8);
3871 if (VBOX_SUCCESS(rc))
3872 {
3873 LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
3874 return u8;
3875 }
3876 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Vrc)\n", rc));
3877 return 0;
3878}
3879
3880
3881/* -+- I/O Ports -+- */
3882
3883#undef LOG_GROUP
3884#define LOG_GROUP LOG_GROUP_REM_IOPORT
3885
3886void cpu_outb(CPUState *env, int addr, int val)
3887{
3888 if (addr != 0x80 && addr != 0x70 && addr != 0x61)
3889 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
3890
3891 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
3892 if (RT_LIKELY(rc == VINF_SUCCESS))
3893 return;
3894 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3895 {
3896 Log(("cpu_outb: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
3897 remR3RaiseRC(env->pVM, rc);
3898 return;
3899 }
3900 remAbort(rc, __FUNCTION__);
3901}
3902
3903void cpu_outw(CPUState *env, int addr, int val)
3904{
3905 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
3906 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
3907 if (RT_LIKELY(rc == VINF_SUCCESS))
3908 return;
3909 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3910 {
3911 Log(("cpu_outw: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
3912 remR3RaiseRC(env->pVM, rc);
3913 return;
3914 }
3915 remAbort(rc, __FUNCTION__);
3916}
3917
3918void cpu_outl(CPUState *env, int addr, int val)
3919{
3920 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
3921 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
3922 if (RT_LIKELY(rc == VINF_SUCCESS))
3923 return;
3924 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3925 {
3926 Log(("cpu_outl: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
3927 remR3RaiseRC(env->pVM, rc);
3928 return;
3929 }
3930 remAbort(rc, __FUNCTION__);
3931}
3932
3933int cpu_inb(CPUState *env, int addr)
3934{
3935 uint32_t u32 = 0;
3936 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
3937 if (RT_LIKELY(rc == VINF_SUCCESS))
3938 {
3939 if (/*addr != 0x61 && */addr != 0x71)
3940 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
3941 return (int)u32;
3942 }
3943 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3944 {
3945 Log(("cpu_inb: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
3946 remR3RaiseRC(env->pVM, rc);
3947 return (int)u32;
3948 }
3949 remAbort(rc, __FUNCTION__);
3950 return 0xff;
3951}
3952
3953int cpu_inw(CPUState *env, int addr)
3954{
3955 uint32_t u32 = 0;
3956 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
3957 if (RT_LIKELY(rc == VINF_SUCCESS))
3958 {
3959 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
3960 return (int)u32;
3961 }
3962 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3963 {
3964 Log(("cpu_inw: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
3965 remR3RaiseRC(env->pVM, rc);
3966 return (int)u32;
3967 }
3968 remAbort(rc, __FUNCTION__);
3969 return 0xffff;
3970}
3971
3972int cpu_inl(CPUState *env, int addr)
3973{
3974 uint32_t u32 = 0;
3975 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
3976 if (RT_LIKELY(rc == VINF_SUCCESS))
3977 {
3978//if (addr==0x01f0 && u32 == 0x6b6d)
3979// loglevel = ~0;
3980 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
3981 return (int)u32;
3982 }
3983 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3984 {
3985 Log(("cpu_inl: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
3986 remR3RaiseRC(env->pVM, rc);
3987 return (int)u32;
3988 }
3989 remAbort(rc, __FUNCTION__);
3990 return 0xffffffff;
3991}
3992
3993#undef LOG_GROUP
3994#define LOG_GROUP LOG_GROUP_REM
3995
3996
3997/* -+- helpers and misc other interfaces -+- */
3998
3999/**
4000 * Perform the CPUID instruction.
4001 *
4002 * ASMCpuId cannot be invoked from some source files where this is used because of global
4003 * register allocations.
4004 *
4005 * @param env Pointer to the recompiler CPU structure.
4006 * @param uOperator CPUID operation (eax).
4007 * @param pvEAX Where to store eax.
4008 * @param pvEBX Where to store ebx.
4009 * @param pvECX Where to store ecx.
4010 * @param pvEDX Where to store edx.
4011 */
4012void remR3CpuId(CPUState *env, unsigned uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
4013{
4014 CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t *)pvEAX, (uint32_t *)pvEBX, (uint32_t *)pvECX, (uint32_t *)pvEDX);
4015}
4016
4017
4018#if 0 /* not used */
4019/**
4020 * Interface for qemu hardware to report back fatal errors.
4021 */
4022void hw_error(const char *pszFormat, ...)
4023{
4024 /*
4025 * Bitch about it.
4026 */
4027 /** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4028 * this in my Odin32 tree at home! */
4029 va_list args;
4030 va_start(args, pszFormat);
4031 RTLogPrintf("fatal error in virtual hardware:");
4032 RTLogPrintfV(pszFormat, args);
4033 va_end(args);
4034 AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4035
4036 /*
4037 * If we're in REM context we'll sync back the state before 'jumping' to
4038 * the EMs failure handling.
4039 */
4040 PVM pVM = cpu_single_env->pVM;
4041 if (pVM->rem.s.fInREM)
4042 REMR3StateBack(pVM);
4043 EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4044 AssertMsgFailed(("EMR3FatalError returned!\n"));
4045}
4046#endif
4047
4048/**
4049 * Interface for the qemu cpu to report unhandled situation
4050 * raising a fatal VM error.
4051 */
4052void cpu_abort(CPUState *env, const char *pszFormat, ...)
4053{
4054 /*
4055 * Bitch about it.
4056 */
4057 RTLogFlags(NULL, "nodisabled nobuffered");
4058 va_list args;
4059 va_start(args, pszFormat);
4060 RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4061 va_end(args);
4062 va_start(args, pszFormat);
4063 AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4064 va_end(args);
4065
4066 /*
4067 * If we're in REM context we'll sync back the state before 'jumping' to
4068 * the EMs failure handling.
4069 */
4070 PVM pVM = cpu_single_env->pVM;
4071 if (pVM->rem.s.fInREM)
4072 REMR3StateBack(pVM);
4073 EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4074 AssertMsgFailed(("EMR3FatalError returned!\n"));
4075}
4076
4077
4078/**
4079 * Aborts the VM.
4080 *
4081 * @param rc VBox error code.
4082 * @param pszTip Hint about why/when this happend.
4083 */
4084static void remAbort(int rc, const char *pszTip)
4085{
4086 /*
4087 * Bitch about it.
4088 */
4089 RTLogPrintf("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip);
4090 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip));
4091
4092 /*
4093 * Jump back to where we entered the recompiler.
4094 */
4095 PVM pVM = cpu_single_env->pVM;
4096 if (pVM->rem.s.fInREM)
4097 REMR3StateBack(pVM);
4098 EMR3FatalError(pVM, rc);
4099 AssertMsgFailed(("EMR3FatalError returned!\n"));
4100}
4101
4102
4103/**
4104 * Dumps a linux system call.
4105 * @param pVM VM handle.
4106 */
4107void remR3DumpLnxSyscall(PVM pVM)
4108{
4109 static const char *apsz[] =
4110 {
4111 "sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4112 "sys_exit",
4113 "sys_fork",
4114 "sys_read",
4115 "sys_write",
4116 "sys_open", /* 5 */
4117 "sys_close",
4118 "sys_waitpid",
4119 "sys_creat",
4120 "sys_link",
4121 "sys_unlink", /* 10 */
4122 "sys_execve",
4123 "sys_chdir",
4124 "sys_time",
4125 "sys_mknod",
4126 "sys_chmod", /* 15 */
4127 "sys_lchown16",
4128 "sys_ni_syscall", /* old break syscall holder */
4129 "sys_stat",
4130 "sys_lseek",
4131 "sys_getpid", /* 20 */
4132 "sys_mount",
4133 "sys_oldumount",
4134 "sys_setuid16",
4135 "sys_getuid16",
4136 "sys_stime", /* 25 */
4137 "sys_ptrace",
4138 "sys_alarm",
4139 "sys_fstat",
4140 "sys_pause",
4141 "sys_utime", /* 30 */
4142 "sys_ni_syscall", /* old stty syscall holder */
4143 "sys_ni_syscall", /* old gtty syscall holder */
4144 "sys_access",
4145 "sys_nice",
4146 "sys_ni_syscall", /* 35 - old ftime syscall holder */
4147 "sys_sync",
4148 "sys_kill",
4149 "sys_rename",
4150 "sys_mkdir",
4151 "sys_rmdir", /* 40 */
4152 "sys_dup",
4153 "sys_pipe",
4154 "sys_times",
4155 "sys_ni_syscall", /* old prof syscall holder */
4156 "sys_brk", /* 45 */
4157 "sys_setgid16",
4158 "sys_getgid16",
4159 "sys_signal",
4160 "sys_geteuid16",
4161 "sys_getegid16", /* 50 */
4162 "sys_acct",
4163 "sys_umount", /* recycled never used phys() */
4164 "sys_ni_syscall", /* old lock syscall holder */
4165 "sys_ioctl",
4166 "sys_fcntl", /* 55 */
4167 "sys_ni_syscall", /* old mpx syscall holder */
4168 "sys_setpgid",
4169 "sys_ni_syscall", /* old ulimit syscall holder */
4170 "sys_olduname",
4171 "sys_umask", /* 60 */
4172 "sys_chroot",
4173 "sys_ustat",
4174 "sys_dup2",
4175 "sys_getppid",
4176 "sys_getpgrp", /* 65 */
4177 "sys_setsid",
4178 "sys_sigaction",
4179 "sys_sgetmask",
4180 "sys_ssetmask",
4181 "sys_setreuid16", /* 70 */
4182 "sys_setregid16",
4183 "sys_sigsuspend",
4184 "sys_sigpending",
4185 "sys_sethostname",
4186 "sys_setrlimit", /* 75 */
4187 "sys_old_getrlimit",
4188 "sys_getrusage",
4189 "sys_gettimeofday",
4190 "sys_settimeofday",
4191 "sys_getgroups16", /* 80 */
4192 "sys_setgroups16",
4193 "old_select",
4194 "sys_symlink",
4195 "sys_lstat",
4196 "sys_readlink", /* 85 */
4197 "sys_uselib",
4198 "sys_swapon",
4199 "sys_reboot",
4200 "old_readdir",
4201 "old_mmap", /* 90 */
4202 "sys_munmap",
4203 "sys_truncate",
4204 "sys_ftruncate",
4205 "sys_fchmod",
4206 "sys_fchown16", /* 95 */
4207 "sys_getpriority",
4208 "sys_setpriority",
4209 "sys_ni_syscall", /* old profil syscall holder */
4210 "sys_statfs",
4211 "sys_fstatfs", /* 100 */
4212 "sys_ioperm",
4213 "sys_socketcall",
4214 "sys_syslog",
4215 "sys_setitimer",
4216 "sys_getitimer", /* 105 */
4217 "sys_newstat",
4218 "sys_newlstat",
4219 "sys_newfstat",
4220 "sys_uname",
4221 "sys_iopl", /* 110 */
4222 "sys_vhangup",
4223 "sys_ni_syscall", /* old "idle" system call */
4224 "sys_vm86old",
4225 "sys_wait4",
4226 "sys_swapoff", /* 115 */
4227 "sys_sysinfo",
4228 "sys_ipc",
4229 "sys_fsync",
4230 "sys_sigreturn",
4231 "sys_clone", /* 120 */
4232 "sys_setdomainname",
4233 "sys_newuname",
4234 "sys_modify_ldt",
4235 "sys_adjtimex",
4236 "sys_mprotect", /* 125 */
4237 "sys_sigprocmask",
4238 "sys_ni_syscall", /* old "create_module" */
4239 "sys_init_module",
4240 "sys_delete_module",
4241 "sys_ni_syscall", /* 130: old "get_kernel_syms" */
4242 "sys_quotactl",
4243 "sys_getpgid",
4244 "sys_fchdir",
4245 "sys_bdflush",
4246 "sys_sysfs", /* 135 */
4247 "sys_personality",
4248 "sys_ni_syscall", /* reserved for afs_syscall */
4249 "sys_setfsuid16",
4250 "sys_setfsgid16",
4251 "sys_llseek", /* 140 */
4252 "sys_getdents",
4253 "sys_select",
4254 "sys_flock",
4255 "sys_msync",
4256 "sys_readv", /* 145 */
4257 "sys_writev",
4258 "sys_getsid",
4259 "sys_fdatasync",
4260 "sys_sysctl",
4261 "sys_mlock", /* 150 */
4262 "sys_munlock",
4263 "sys_mlockall",
4264 "sys_munlockall",
4265 "sys_sched_setparam",
4266 "sys_sched_getparam", /* 155 */
4267 "sys_sched_setscheduler",
4268 "sys_sched_getscheduler",
4269 "sys_sched_yield",
4270 "sys_sched_get_priority_max",
4271 "sys_sched_get_priority_min", /* 160 */
4272 "sys_sched_rr_get_interval",
4273 "sys_nanosleep",
4274 "sys_mremap",
4275 "sys_setresuid16",
4276 "sys_getresuid16", /* 165 */
4277 "sys_vm86",
4278 "sys_ni_syscall", /* Old sys_query_module */
4279 "sys_poll",
4280 "sys_nfsservctl",
4281 "sys_setresgid16", /* 170 */
4282 "sys_getresgid16",
4283 "sys_prctl",
4284 "sys_rt_sigreturn",
4285 "sys_rt_sigaction",
4286 "sys_rt_sigprocmask", /* 175 */
4287 "sys_rt_sigpending",
4288 "sys_rt_sigtimedwait",
4289 "sys_rt_sigqueueinfo",
4290 "sys_rt_sigsuspend",
4291 "sys_pread64", /* 180 */
4292 "sys_pwrite64",
4293 "sys_chown16",
4294 "sys_getcwd",
4295 "sys_capget",
4296 "sys_capset", /* 185 */
4297 "sys_sigaltstack",
4298 "sys_sendfile",
4299 "sys_ni_syscall", /* reserved for streams1 */
4300 "sys_ni_syscall", /* reserved for streams2 */
4301 "sys_vfork", /* 190 */
4302 "sys_getrlimit",
4303 "sys_mmap2",
4304 "sys_truncate64",
4305 "sys_ftruncate64",
4306 "sys_stat64", /* 195 */
4307 "sys_lstat64",
4308 "sys_fstat64",
4309 "sys_lchown",
4310 "sys_getuid",
4311 "sys_getgid", /* 200 */
4312 "sys_geteuid",
4313 "sys_getegid",
4314 "sys_setreuid",
4315 "sys_setregid",
4316 "sys_getgroups", /* 205 */
4317 "sys_setgroups",
4318 "sys_fchown",
4319 "sys_setresuid",
4320 "sys_getresuid",
4321 "sys_setresgid", /* 210 */
4322 "sys_getresgid",
4323 "sys_chown",
4324 "sys_setuid",
4325 "sys_setgid",
4326 "sys_setfsuid", /* 215 */
4327 "sys_setfsgid",
4328 "sys_pivot_root",
4329 "sys_mincore",
4330 "sys_madvise",
4331 "sys_getdents64", /* 220 */
4332 "sys_fcntl64",
4333 "sys_ni_syscall", /* reserved for TUX */
4334 "sys_ni_syscall",
4335 "sys_gettid",
4336 "sys_readahead", /* 225 */
4337 "sys_setxattr",
4338 "sys_lsetxattr",
4339 "sys_fsetxattr",
4340 "sys_getxattr",
4341 "sys_lgetxattr", /* 230 */
4342 "sys_fgetxattr",
4343 "sys_listxattr",
4344 "sys_llistxattr",
4345 "sys_flistxattr",
4346 "sys_removexattr", /* 235 */
4347 "sys_lremovexattr",
4348 "sys_fremovexattr",
4349 "sys_tkill",
4350 "sys_sendfile64",
4351 "sys_futex", /* 240 */
4352 "sys_sched_setaffinity",
4353 "sys_sched_getaffinity",
4354 "sys_set_thread_area",
4355 "sys_get_thread_area",
4356 "sys_io_setup", /* 245 */
4357 "sys_io_destroy",
4358 "sys_io_getevents",
4359 "sys_io_submit",
4360 "sys_io_cancel",
4361 "sys_fadvise64", /* 250 */
4362 "sys_ni_syscall",
4363 "sys_exit_group",
4364 "sys_lookup_dcookie",
4365 "sys_epoll_create",
4366 "sys_epoll_ctl", /* 255 */
4367 "sys_epoll_wait",
4368 "sys_remap_file_pages",
4369 "sys_set_tid_address",
4370 "sys_timer_create",
4371 "sys_timer_settime", /* 260 */
4372 "sys_timer_gettime",
4373 "sys_timer_getoverrun",
4374 "sys_timer_delete",
4375 "sys_clock_settime",
4376 "sys_clock_gettime", /* 265 */
4377 "sys_clock_getres",
4378 "sys_clock_nanosleep",
4379 "sys_statfs64",
4380 "sys_fstatfs64",
4381 "sys_tgkill", /* 270 */
4382 "sys_utimes",
4383 "sys_fadvise64_64",
4384 "sys_ni_syscall" /* sys_vserver */
4385 };
4386
4387 uint32_t uEAX = CPUMGetGuestEAX(pVM);
4388 switch (uEAX)
4389 {
4390 default:
4391 if (uEAX < ELEMENTS(apsz))
4392 Log(("REM: linux syscall %3d: %s (eip=%VGv ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4393 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4394 CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4395 else
4396 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4397 break;
4398
4399 }
4400}
4401
4402
4403/**
4404 * Dumps an OpenBSD system call.
4405 * @param pVM VM handle.
4406 */
4407void remR3DumpOBsdSyscall(PVM pVM)
4408{
4409 static const char *apsz[] =
4410 {
4411 "SYS_syscall", //0
4412 "SYS_exit", //1
4413 "SYS_fork", //2
4414 "SYS_read", //3
4415 "SYS_write", //4
4416 "SYS_open", //5
4417 "SYS_close", //6
4418 "SYS_wait4", //7
4419 "SYS_8",
4420 "SYS_link", //9
4421 "SYS_unlink", //10
4422 "SYS_11",
4423 "SYS_chdir", //12
4424 "SYS_fchdir", //13
4425 "SYS_mknod", //14
4426 "SYS_chmod", //15
4427 "SYS_chown", //16
4428 "SYS_break", //17
4429 "SYS_18",
4430 "SYS_19",
4431 "SYS_getpid", //20
4432 "SYS_mount", //21
4433 "SYS_unmount", //22
4434 "SYS_setuid", //23
4435 "SYS_getuid", //24
4436 "SYS_geteuid", //25
4437 "SYS_ptrace", //26
4438 "SYS_recvmsg", //27
4439 "SYS_sendmsg", //28
4440 "SYS_recvfrom", //29
4441 "SYS_accept", //30
4442 "SYS_getpeername", //31
4443 "SYS_getsockname", //32
4444 "SYS_access", //33
4445 "SYS_chflags", //34
4446 "SYS_fchflags", //35
4447 "SYS_sync", //36
4448 "SYS_kill", //37
4449 "SYS_38",
4450 "SYS_getppid", //39
4451 "SYS_40",
4452 "SYS_dup", //41
4453 "SYS_opipe", //42
4454 "SYS_getegid", //43
4455 "SYS_profil", //44
4456 "SYS_ktrace", //45
4457 "SYS_sigaction", //46
4458 "SYS_getgid", //47
4459 "SYS_sigprocmask", //48
4460 "SYS_getlogin", //49
4461 "SYS_setlogin", //50
4462 "SYS_acct", //51
4463 "SYS_sigpending", //52
4464 "SYS_osigaltstack", //53
4465 "SYS_ioctl", //54
4466 "SYS_reboot", //55
4467 "SYS_revoke", //56
4468 "SYS_symlink", //57
4469 "SYS_readlink", //58
4470 "SYS_execve", //59
4471 "SYS_umask", //60
4472 "SYS_chroot", //61
4473 "SYS_62",
4474 "SYS_63",
4475 "SYS_64",
4476 "SYS_65",
4477 "SYS_vfork", //66
4478 "SYS_67",
4479 "SYS_68",
4480 "SYS_sbrk", //69
4481 "SYS_sstk", //70
4482 "SYS_61",
4483 "SYS_vadvise", //72
4484 "SYS_munmap", //73
4485 "SYS_mprotect", //74
4486 "SYS_madvise", //75
4487 "SYS_76",
4488 "SYS_77",
4489 "SYS_mincore", //78
4490 "SYS_getgroups", //79
4491 "SYS_setgroups", //80
4492 "SYS_getpgrp", //81
4493 "SYS_setpgid", //82
4494 "SYS_setitimer", //83
4495 "SYS_84",
4496 "SYS_85",
4497 "SYS_getitimer", //86
4498 "SYS_87",
4499 "SYS_88",
4500 "SYS_89",
4501 "SYS_dup2", //90
4502 "SYS_91",
4503 "SYS_fcntl", //92
4504 "SYS_select", //93
4505 "SYS_94",
4506 "SYS_fsync", //95
4507 "SYS_setpriority", //96
4508 "SYS_socket", //97
4509 "SYS_connect", //98
4510 "SYS_99",
4511 "SYS_getpriority", //100
4512 "SYS_101",
4513 "SYS_102",
4514 "SYS_sigreturn", //103
4515 "SYS_bind", //104
4516 "SYS_setsockopt", //105
4517 "SYS_listen", //106
4518 "SYS_107",
4519 "SYS_108",
4520 "SYS_109",
4521 "SYS_110",
4522 "SYS_sigsuspend", //111
4523 "SYS_112",
4524 "SYS_113",
4525 "SYS_114",
4526 "SYS_115",
4527 "SYS_gettimeofday", //116
4528 "SYS_getrusage", //117
4529 "SYS_getsockopt", //118
4530 "SYS_119",
4531 "SYS_readv", //120
4532 "SYS_writev", //121
4533 "SYS_settimeofday", //122
4534 "SYS_fchown", //123
4535 "SYS_fchmod", //124
4536 "SYS_125",
4537 "SYS_setreuid", //126
4538 "SYS_setregid", //127
4539 "SYS_rename", //128
4540 "SYS_129",
4541 "SYS_130",
4542 "SYS_flock", //131
4543 "SYS_mkfifo", //132
4544 "SYS_sendto", //133
4545 "SYS_shutdown", //134
4546 "SYS_socketpair", //135
4547 "SYS_mkdir", //136
4548 "SYS_rmdir", //137
4549 "SYS_utimes", //138
4550 "SYS_139",
4551 "SYS_adjtime", //140
4552 "SYS_141",
4553 "SYS_142",
4554 "SYS_143",
4555 "SYS_144",
4556 "SYS_145",
4557 "SYS_146",
4558 "SYS_setsid", //147
4559 "SYS_quotactl", //148
4560 "SYS_149",
4561 "SYS_150",
4562 "SYS_151",
4563 "SYS_152",
4564 "SYS_153",
4565 "SYS_154",
4566 "SYS_nfssvc", //155
4567 "SYS_156",
4568 "SYS_157",
4569 "SYS_158",
4570 "SYS_159",
4571 "SYS_160",
4572 "SYS_getfh", //161
4573 "SYS_162",
4574 "SYS_163",
4575 "SYS_164",
4576 "SYS_sysarch", //165
4577 "SYS_166",
4578 "SYS_167",
4579 "SYS_168",
4580 "SYS_169",
4581 "SYS_170",
4582 "SYS_171",
4583 "SYS_172",
4584 "SYS_pread", //173
4585 "SYS_pwrite", //174
4586 "SYS_175",
4587 "SYS_176",
4588 "SYS_177",
4589 "SYS_178",
4590 "SYS_179",
4591 "SYS_180",
4592 "SYS_setgid", //181
4593 "SYS_setegid", //182
4594 "SYS_seteuid", //183
4595 "SYS_lfs_bmapv", //184
4596 "SYS_lfs_markv", //185
4597 "SYS_lfs_segclean", //186
4598 "SYS_lfs_segwait", //187
4599 "SYS_188",
4600 "SYS_189",
4601 "SYS_190",
4602 "SYS_pathconf", //191
4603 "SYS_fpathconf", //192
4604 "SYS_swapctl", //193
4605 "SYS_getrlimit", //194
4606 "SYS_setrlimit", //195
4607 "SYS_getdirentries", //196
4608 "SYS_mmap", //197
4609 "SYS___syscall", //198
4610 "SYS_lseek", //199
4611 "SYS_truncate", //200
4612 "SYS_ftruncate", //201
4613 "SYS___sysctl", //202
4614 "SYS_mlock", //203
4615 "SYS_munlock", //204
4616 "SYS_205",
4617 "SYS_futimes", //206
4618 "SYS_getpgid", //207
4619 "SYS_xfspioctl", //208
4620 "SYS_209",
4621 "SYS_210",
4622 "SYS_211",
4623 "SYS_212",
4624 "SYS_213",
4625 "SYS_214",
4626 "SYS_215",
4627 "SYS_216",
4628 "SYS_217",
4629 "SYS_218",
4630 "SYS_219",
4631 "SYS_220",
4632 "SYS_semget", //221
4633 "SYS_222",
4634 "SYS_223",
4635 "SYS_224",
4636 "SYS_msgget", //225
4637 "SYS_msgsnd", //226
4638 "SYS_msgrcv", //227
4639 "SYS_shmat", //228
4640 "SYS_229",
4641 "SYS_shmdt", //230
4642 "SYS_231",
4643 "SYS_clock_gettime", //232
4644 "SYS_clock_settime", //233
4645 "SYS_clock_getres", //234
4646 "SYS_235",
4647 "SYS_236",
4648 "SYS_237",
4649 "SYS_238",
4650 "SYS_239",
4651 "SYS_nanosleep", //240
4652 "SYS_241",
4653 "SYS_242",
4654 "SYS_243",
4655 "SYS_244",
4656 "SYS_245",
4657 "SYS_246",
4658 "SYS_247",
4659 "SYS_248",
4660 "SYS_249",
4661 "SYS_minherit", //250
4662 "SYS_rfork", //251
4663 "SYS_poll", //252
4664 "SYS_issetugid", //253
4665 "SYS_lchown", //254
4666 "SYS_getsid", //255
4667 "SYS_msync", //256
4668 "SYS_257",
4669 "SYS_258",
4670 "SYS_259",
4671 "SYS_getfsstat", //260
4672 "SYS_statfs", //261
4673 "SYS_fstatfs", //262
4674 "SYS_pipe", //263
4675 "SYS_fhopen", //264
4676 "SYS_265",
4677 "SYS_fhstatfs", //266
4678 "SYS_preadv", //267
4679 "SYS_pwritev", //268
4680 "SYS_kqueue", //269
4681 "SYS_kevent", //270
4682 "SYS_mlockall", //271
4683 "SYS_munlockall", //272
4684 "SYS_getpeereid", //273
4685 "SYS_274",
4686 "SYS_275",
4687 "SYS_276",
4688 "SYS_277",
4689 "SYS_278",
4690 "SYS_279",
4691 "SYS_280",
4692 "SYS_getresuid", //281
4693 "SYS_setresuid", //282
4694 "SYS_getresgid", //283
4695 "SYS_setresgid", //284
4696 "SYS_285",
4697 "SYS_mquery", //286
4698 "SYS_closefrom", //287
4699 "SYS_sigaltstack", //288
4700 "SYS_shmget", //289
4701 "SYS_semop", //290
4702 "SYS_stat", //291
4703 "SYS_fstat", //292
4704 "SYS_lstat", //293
4705 "SYS_fhstat", //294
4706 "SYS___semctl", //295
4707 "SYS_shmctl", //296
4708 "SYS_msgctl", //297
4709 "SYS_MAXSYSCALL", //298
4710 //299
4711 //300
4712 };
4713 uint32_t uEAX;
4714 if (!LogIsEnabled())
4715 return;
4716 uEAX = CPUMGetGuestEAX(pVM);
4717 switch (uEAX)
4718 {
4719 default:
4720 if (uEAX < ELEMENTS(apsz))
4721 {
4722 uint32_t au32Args[8] = {0};
4723 PGMPhysReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4724 RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4725 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4726 au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4727 }
4728 else
4729 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4730 break;
4731 }
4732}
4733
4734
4735#if defined(IPRT_NO_CRT) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
4736/**
4737 * The Dll main entry point (stub).
4738 */
4739bool __stdcall _DllMainCRTStartup(void *hModule, uint32_t dwReason, void *pvReserved)
4740{
4741 return true;
4742}
4743
4744void *memcpy(void *dst, const void *src, size_t size)
4745{
4746 uint8_t*pbDst = dst, *pbSrc = src;
4747 while (size-- > 0)
4748 *pbDst++ = *pbSrc++;
4749 return dst;
4750}
4751
4752#endif
4753
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