VirtualBox

source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 61626

Last change on this file since 61626 was 60804, checked in by vboxsync, 9 years ago

VMM: Introduced the new APIC update force-flag and relevant fixes, Win8.1 SMP boots now.
VMM/HMVMXR0: Fixed the HLT exit to use instruction length and also keep the INHIBIT force-flag
more in sync with the VT-x's guest-interruptibility state.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 186.2 KB
Line 
1/* $Id: VBoxRecompiler.c 60804 2016-05-03 14:13:51Z vboxsync $ */
2/** @file
3 * VBox Recompiler - QEMU.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_rem REM - Recompiled Execution Manager.
19 *
20 * The recompiled exeuction manager (REM) serves the final fallback for guest
21 * execution, after HM / raw-mode and IEM have given up.
22 *
23 * The REM is qemu with a whole bunch of VBox specific customization for
24 * interfacing with PATM, CSAM, PGM and other components.
25 *
26 * @sa @ref grp_rem
27 */
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_REM
33#include <stdio.h> /* FILE */
34#include "osdep.h"
35#include "config.h"
36#include "cpu.h"
37#include "exec-all.h"
38#include "ioport.h"
39
40#include <VBox/vmm/rem.h>
41#include <VBox/vmm/vmapi.h>
42#include <VBox/vmm/tm.h>
43#include <VBox/vmm/ssm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/trpm.h>
46#include <VBox/vmm/iom.h>
47#include <VBox/vmm/mm.h>
48#include <VBox/vmm/pgm.h>
49#include <VBox/vmm/pdm.h>
50#include <VBox/vmm/dbgf.h>
51#include <VBox/dbg.h>
52#ifdef VBOX_WITH_NEW_APIC
53# include <VBox/vmm/apic.h>
54#endif
55#include <VBox/vmm/hm.h>
56#include <VBox/vmm/patm.h>
57#include <VBox/vmm/csam.h>
58#include "REMInternal.h"
59#include <VBox/vmm/vm.h>
60#include <VBox/vmm/uvm.h>
61#include <VBox/param.h>
62#include <VBox/err.h>
63
64#include <VBox/log.h>
65#include <iprt/alloca.h>
66#include <iprt/semaphore.h>
67#include <iprt/asm.h>
68#include <iprt/assert.h>
69#include <iprt/thread.h>
70#include <iprt/string.h>
71
72/* Don't wanna include everything. */
73extern void cpu_exec_init_all(uintptr_t tb_size);
74extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
75extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
76extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
77extern void tlb_flush_page(CPUX86State *env, target_ulong addr);
78extern void tlb_flush(CPUX86State *env, int flush_global);
79extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
80extern void sync_ldtr(CPUX86State *env1, int selector);
81
82#ifdef VBOX_STRICT
83ram_addr_t get_phys_page_offset(target_ulong addr);
84#endif
85
86
87/*********************************************************************************************************************************
88* Defined Constants And Macros *
89*********************************************************************************************************************************/
90
91/** Copy 80-bit fpu register at pSrc to pDst.
92 * This is probably faster than *calling* memcpy.
93 */
94#define REM_COPY_FPU_REG(pDst, pSrc) \
95 do { *(PX86FPUMMX)(pDst) = *(const X86FPUMMX *)(pSrc); } while (0)
96
97/** How remR3RunLoggingStep operates. */
98#define REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
99
100
101/** Selector flag shift between qemu and VBox.
102 * VBox shifts the qemu bits to the right. */
103#define SEL_FLAGS_SHIFT (8)
104/** Mask applied to the shifted qemu selector flags to get the attributes VBox
105 * (VT-x) needs. */
106#define SEL_FLAGS_SMASK UINT32_C(0x1F0FF)
107
108
109/*********************************************************************************************************************************
110* Internal Functions *
111*********************************************************************************************************************************/
112static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
113static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
114static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu);
115static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded);
116
117static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys);
118static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys);
119static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys);
120static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
121static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
122static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
123
124static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
125static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
126static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
127static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
128static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
129static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
130
131static void remR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
132static void remR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler);
133static void remR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
134
135
136/*********************************************************************************************************************************
137* Global Variables *
138*********************************************************************************************************************************/
139
140/** @todo Move stats to REM::s some rainy day we have nothing do to. */
141#ifdef VBOX_WITH_STATISTICS
142static STAMPROFILEADV gStatExecuteSingleInstr;
143static STAMPROFILEADV gStatCompilationQEmu;
144static STAMPROFILEADV gStatRunCodeQEmu;
145static STAMPROFILEADV gStatTotalTimeQEmu;
146static STAMPROFILEADV gStatTimers;
147static STAMPROFILEADV gStatTBLookup;
148static STAMPROFILEADV gStatIRQ;
149static STAMPROFILEADV gStatRawCheck;
150static STAMPROFILEADV gStatMemRead;
151static STAMPROFILEADV gStatMemWrite;
152static STAMPROFILE gStatGCPhys2HCVirt;
153static STAMCOUNTER gStatCpuGetTSC;
154static STAMCOUNTER gStatRefuseTFInhibit;
155static STAMCOUNTER gStatRefuseVM86;
156static STAMCOUNTER gStatRefusePaging;
157static STAMCOUNTER gStatRefusePAE;
158static STAMCOUNTER gStatRefuseIOPLNot0;
159static STAMCOUNTER gStatRefuseIF0;
160static STAMCOUNTER gStatRefuseCode16;
161static STAMCOUNTER gStatRefuseWP0;
162static STAMCOUNTER gStatRefuseRing1or2;
163static STAMCOUNTER gStatRefuseCanExecute;
164static STAMCOUNTER gaStatRefuseStale[6];
165static STAMCOUNTER gStatREMGDTChange;
166static STAMCOUNTER gStatREMIDTChange;
167static STAMCOUNTER gStatREMLDTRChange;
168static STAMCOUNTER gStatREMTRChange;
169static STAMCOUNTER gStatSelOutOfSync[6];
170static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
171static STAMCOUNTER gStatFlushTBs;
172#endif
173/* in exec.c */
174extern uint32_t tlb_flush_count;
175extern uint32_t tb_flush_count;
176extern uint32_t tb_phys_invalidate_count;
177
178/*
179 * Global stuff.
180 */
181
182/** MMIO read callbacks. */
183CPUReadMemoryFunc *g_apfnMMIORead[3] =
184{
185 remR3MMIOReadU8,
186 remR3MMIOReadU16,
187 remR3MMIOReadU32
188};
189
190/** MMIO write callbacks. */
191CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
192{
193 remR3MMIOWriteU8,
194 remR3MMIOWriteU16,
195 remR3MMIOWriteU32
196};
197
198/** Handler read callbacks. */
199CPUReadMemoryFunc *g_apfnHandlerRead[3] =
200{
201 remR3HandlerReadU8,
202 remR3HandlerReadU16,
203 remR3HandlerReadU32
204};
205
206/** Handler write callbacks. */
207CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
208{
209 remR3HandlerWriteU8,
210 remR3HandlerWriteU16,
211 remR3HandlerWriteU32
212};
213
214
215#ifdef VBOX_WITH_DEBUGGER
216/*
217 * Debugger commands.
218 */
219static FNDBGCCMD remR3CmdDisasEnableStepping;;
220
221/** '.remstep' arguments. */
222static const DBGCVARDESC g_aArgRemStep[] =
223{
224 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
225 { 0, ~0U, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
226};
227
228/** Command descriptors. */
229static const DBGCCMD g_aCmds[] =
230{
231 {
232 .pszCmd ="remstep",
233 .cArgsMin = 0,
234 .cArgsMax = 1,
235 .paArgDescs = &g_aArgRemStep[0],
236 .cArgDescs = RT_ELEMENTS(g_aArgRemStep),
237 .fFlags = 0,
238 .pfnHandler = remR3CmdDisasEnableStepping,
239 .pszSyntax = "[on/off]",
240 .pszDescription = "Enable or disable the single stepping with logged disassembly. "
241 "If no arguments show the current state."
242 }
243};
244#endif
245
246/** Prologue code, must be in lower 4G to simplify jumps to/from generated code.
247 * @todo huh??? That cannot be the case on the mac... So, this
248 * point is probably not valid any longer. */
249uint8_t *code_gen_prologue;
250
251
252/*********************************************************************************************************************************
253* Internal Functions *
254*********************************************************************************************************************************/
255void remAbort(int rc, const char *pszTip);
256extern int testmath(void);
257
258/* Put them here to avoid unused variable warning. */
259AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
260#if !defined(IPRT_NO_CRT) && (defined(RT_OS_LINUX) || defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS))
261//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
262/* Why did this have to be identical?? */
263AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
264#else
265AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
266#endif
267
268
269/**
270 * Initializes the REM.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM to operate on.
274 */
275REMR3DECL(int) REMR3Init(PVM pVM)
276{
277 PREMHANDLERNOTIFICATION pCur;
278 uint32_t u32Dummy;
279 int rc;
280 unsigned i;
281
282#ifdef VBOX_ENABLE_VBOXREM64
283 LogRel(("Using 64-bit aware REM\n"));
284#endif
285
286 /*
287 * Assert sanity.
288 */
289 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
290 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
291 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
292#if 0 /* just an annoyance at the moment. */
293#if defined(DEBUG) && !defined(RT_OS_SOLARIS) && !defined(RT_OS_FREEBSD) /// @todo fix the solaris and freebsd math stuff.
294 Assert(!testmath());
295#endif
296#endif
297
298 /*
299 * Init some internal data members.
300 */
301 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
302 pVM->rem.s.Env.pVM = pVM;
303#ifdef CPU_RAW_MODE_INIT
304 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
305#endif
306
307 /*
308 * Initialize the REM critical section.
309 *
310 * Note: This is not a 100% safe solution as updating the internal memory state while another VCPU
311 * is executing code could be dangerous. Taking the REM lock is not an option due to the danger of
312 * deadlocks. (mostly pgm vs rem locking)
313 */
314 rc = PDMR3CritSectInit(pVM, &pVM->rem.s.CritSectRegister, RT_SRC_POS, "REM-Register");
315 AssertRCReturn(rc, rc);
316
317 /* ctx. */
318 pVM->rem.s.pCtx = NULL; /* set when executing code. */
319 AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order has changed! REM depends on notification about ALL physical memory registrations\n"));
320
321 /* ignore all notifications */
322 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
323
324 code_gen_prologue = RTMemExecAlloc(_1K);
325 AssertLogRelReturn(code_gen_prologue, VERR_NO_MEMORY);
326
327 cpu_exec_init_all(0);
328
329 /*
330 * Init the recompiler.
331 */
332 if (!cpu_x86_init(&pVM->rem.s.Env, "vbox"))
333 {
334 AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
335 return VERR_GENERAL_FAILURE;
336 }
337 PVMCPU pVCpu = VMMGetCpu(pVM);
338 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
339 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
340
341 EMRemLock(pVM);
342 cpu_reset(&pVM->rem.s.Env);
343 EMRemUnlock(pVM);
344
345 /* allocate code buffer for single instruction emulation. */
346 pVM->rem.s.Env.cbCodeBuffer = 4096;
347 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
348 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
349
350 /* Finally, set the cpu_single_env global. */
351 cpu_single_env = &pVM->rem.s.Env;
352
353 /* Nothing is pending by default */
354 pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
355
356 /*
357 * Register ram types.
358 */
359 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(g_apfnMMIORead, g_apfnMMIOWrite, &pVM->rem.s.Env);
360 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
361 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
362 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
363 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
364
365 /* stop ignoring. */
366 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
367
368 /*
369 * Register the saved state data unit.
370 */
371 rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
372 NULL, NULL, NULL,
373 NULL, remR3Save, NULL,
374 NULL, remR3Load, NULL);
375 if (RT_FAILURE(rc))
376 return rc;
377
378#ifdef VBOX_WITH_DEBUGGER
379 /*
380 * Debugger commands.
381 */
382 static bool fRegisteredCmds = false;
383 if (!fRegisteredCmds)
384 {
385 int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
386 if (RT_SUCCESS(rc))
387 fRegisteredCmds = true;
388 }
389#endif
390
391#ifdef VBOX_WITH_STATISTICS
392 /*
393 * Statistics.
394 */
395 STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
396 STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
397 STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
398 STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
399 STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer queue processing.");
400 STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling translation block lookup.");
401 STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling IRQ delivery.");
402 STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling remR3CanExecuteRaw calls.");
403 STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
404 STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
405 STAM_REG(pVM, &gStatGCPhys2HCVirt, STAMTYPE_PROFILE, "/PROF/REM/GCPhys2HCVirt", STAMUNIT_TICKS_PER_CALL, "Profiling memory conversion (PGMR3PhysTlbGCPhys2Ptr).");
406
407 STAM_REG(pVM, &gStatCpuGetTSC, STAMTYPE_COUNTER, "/REM/CpuGetTSC", STAMUNIT_OCCURENCES, "cpu_get_tsc calls");
408
409 STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
410 STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
411 STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
412 STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
413 STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
414 STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
415 STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
416 STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
417 STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
418 STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
419 STAM_REG(pVM, &gaStatRefuseStale[R_ES], STAMTYPE_COUNTER, "/REM/Refuse/StaleES", STAMUNIT_OCCURENCES, "Raw mode refused because of stale ES");
420 STAM_REG(pVM, &gaStatRefuseStale[R_CS], STAMTYPE_COUNTER, "/REM/Refuse/StaleCS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale CS");
421 STAM_REG(pVM, &gaStatRefuseStale[R_SS], STAMTYPE_COUNTER, "/REM/Refuse/StaleSS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale SS");
422 STAM_REG(pVM, &gaStatRefuseStale[R_DS], STAMTYPE_COUNTER, "/REM/Refuse/StaleDS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale DS");
423 STAM_REG(pVM, &gaStatRefuseStale[R_FS], STAMTYPE_COUNTER, "/REM/Refuse/StaleFS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale FS");
424 STAM_REG(pVM, &gaStatRefuseStale[R_GS], STAMTYPE_COUNTER, "/REM/Refuse/StaleGS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale GS");
425 STAM_REG(pVM, &gStatFlushTBs, STAMTYPE_COUNTER, "/REM/FlushTB", STAMUNIT_OCCURENCES, "Number of TB flushes");
426
427 STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
428 STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
429 STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
430 STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
431
432 STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
433 STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
434 STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
435 STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
436 STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
437 STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
438
439 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
440 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
441 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
442 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
443 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
444 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
445
446 STAM_REG(pVM, &pVM->rem.s.Env.StatTbFlush, STAMTYPE_PROFILE, "/REM/TbFlush", STAMUNIT_TICKS_PER_CALL, "profiling tb_flush().");
447#endif /* VBOX_WITH_STATISTICS */
448 AssertCompileMemberAlignment(CPUX86State, StatTbFlush, 4);
449 AssertCompileMemberAlignment(CPUX86State, StatTbFlush, 8);
450
451 STAM_REL_REG(pVM, &tb_flush_count, STAMTYPE_U32_RESET, "/REM/TbFlushCount", STAMUNIT_OCCURENCES, "tb_flush() calls");
452 STAM_REL_REG(pVM, &tb_phys_invalidate_count, STAMTYPE_U32_RESET, "/REM/TbPhysInvldCount", STAMUNIT_OCCURENCES, "tb_phys_invalidate() calls");
453 STAM_REL_REG(pVM, &tlb_flush_count, STAMTYPE_U32_RESET, "/REM/TlbFlushCount", STAMUNIT_OCCURENCES, "tlb_flush() calls");
454
455
456#ifdef DEBUG_ALL_LOGGING
457 loglevel = ~0;
458#endif
459
460 /*
461 * Init the handler notification lists.
462 */
463 pVM->rem.s.idxPendingList = UINT32_MAX;
464 pVM->rem.s.idxFreeList = 0;
465
466 for (i = 0 ; i < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications); i++)
467 {
468 pCur = &pVM->rem.s.aHandlerNotifications[i];
469 pCur->idxNext = i + 1;
470 pCur->idxSelf = i;
471 }
472 pCur->idxNext = UINT32_MAX; /* the last record. */
473
474 return rc;
475}
476
477
478/**
479 * Finalizes the REM initialization.
480 *
481 * This is called after all components, devices and drivers has
482 * been initialized. Its main purpose it to finish the RAM related
483 * initialization.
484 *
485 * @returns VBox status code.
486 *
487 * @param pVM The VM handle.
488 */
489REMR3DECL(int) REMR3InitFinalize(PVM pVM)
490{
491 int rc;
492
493 /*
494 * Ram size & dirty bit map.
495 */
496 Assert(!pVM->rem.s.fGCPhysLastRamFixed);
497 pVM->rem.s.fGCPhysLastRamFixed = true;
498#ifdef RT_STRICT
499 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, true /* fGuarded */);
500#else
501 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, false /* fGuarded */);
502#endif
503 return rc;
504}
505
506/**
507 * Initializes ram_list.phys_dirty and ram_list.phys_dirty_size.
508 *
509 * @returns VBox status code.
510 * @param pVM The VM handle.
511 * @param fGuarded Whether to guard the map.
512 */
513static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded)
514{
515 int rc = VINF_SUCCESS;
516 RTGCPHYS cb;
517
518 AssertLogRelReturn(QLIST_EMPTY(&ram_list.blocks), VERR_INTERNAL_ERROR_2);
519
520 cb = pVM->rem.s.GCPhysLastRam + 1;
521 AssertLogRelMsgReturn(cb > pVM->rem.s.GCPhysLastRam,
522 ("GCPhysLastRam=%RGp - out of range\n", pVM->rem.s.GCPhysLastRam),
523 VERR_OUT_OF_RANGE);
524
525 ram_list.phys_dirty_size = cb >> PAGE_SHIFT;
526 AssertMsg(((RTGCPHYS)ram_list.phys_dirty_size << PAGE_SHIFT) == cb, ("%RGp\n", cb));
527
528 if (!fGuarded)
529 {
530 ram_list.phys_dirty = MMR3HeapAlloc(pVM, MM_TAG_REM, ram_list.phys_dirty_size);
531 AssertLogRelMsgReturn(ram_list.phys_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", ram_list.phys_dirty_size), VERR_NO_MEMORY);
532 }
533 else
534 {
535 /*
536 * Fill it up the nearest 4GB RAM and leave at least _64KB of guard after it.
537 */
538 uint32_t cbBitmapAligned = RT_ALIGN_32(ram_list.phys_dirty_size, PAGE_SIZE);
539 uint32_t cbBitmapFull = RT_ALIGN_32(ram_list.phys_dirty_size, (_4G >> PAGE_SHIFT));
540 if (cbBitmapFull == cbBitmapAligned)
541 cbBitmapFull += _4G >> PAGE_SHIFT;
542 else if (cbBitmapFull - cbBitmapAligned < _64K)
543 cbBitmapFull += _64K;
544
545 ram_list.phys_dirty = RTMemPageAlloc(cbBitmapFull);
546 AssertLogRelMsgReturn(ram_list.phys_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", cbBitmapFull), VERR_NO_MEMORY);
547
548 rc = RTMemProtect(ram_list.phys_dirty + cbBitmapAligned, cbBitmapFull - cbBitmapAligned, RTMEM_PROT_NONE);
549 if (RT_FAILURE(rc))
550 {
551 RTMemPageFree(ram_list.phys_dirty, cbBitmapFull);
552 AssertLogRelRCReturn(rc, rc);
553 }
554
555 ram_list.phys_dirty += cbBitmapAligned - ram_list.phys_dirty_size;
556 }
557
558 /* initialize it. */
559 memset(ram_list.phys_dirty, 0xff, ram_list.phys_dirty_size);
560 return rc;
561}
562
563
564/**
565 * Terminates the REM.
566 *
567 * Termination means cleaning up and freeing all resources,
568 * the VM it self is at this point powered off or suspended.
569 *
570 * @returns VBox status code.
571 * @param pVM The VM to operate on.
572 */
573REMR3DECL(int) REMR3Term(PVM pVM)
574{
575 /*
576 * Statistics.
577 */
578 STAMR3Deregister(pVM->pUVM, "/PROF/REM/*");
579 STAMR3Deregister(pVM->pUVM, "/REM/*");
580
581 return VINF_SUCCESS;
582}
583
584
585/**
586 * The VM is being reset.
587 *
588 * For the REM component this means to call the cpu_reset() and
589 * reinitialize some state variables.
590 *
591 * @param pVM VM handle.
592 */
593REMR3DECL(void) REMR3Reset(PVM pVM)
594{
595 EMRemLock(pVM); /* Only pro forma, we're in a rendezvous. */
596
597 /*
598 * Reset the REM cpu.
599 */
600 Assert(pVM->rem.s.cIgnoreAll == 0);
601 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
602 cpu_reset(&pVM->rem.s.Env);
603 pVM->rem.s.cInvalidatedPages = 0;
604 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
605 Assert(pVM->rem.s.cIgnoreAll == 0);
606
607 /* Clear raw ring 0 init state */
608 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
609
610 /* Flush the TBs the next time we execute code here. */
611 pVM->rem.s.fFlushTBs = true;
612
613 EMRemUnlock(pVM);
614}
615
616
617/**
618 * Execute state save operation.
619 *
620 * @returns VBox status code.
621 * @param pVM VM Handle.
622 * @param pSSM SSM operation handle.
623 */
624static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
625{
626 PREM pRem = &pVM->rem.s;
627
628 /*
629 * Save the required CPU Env bits.
630 * (Not much because we're never in REM when doing the save.)
631 */
632 LogFlow(("remR3Save:\n"));
633 Assert(!pRem->fInREM);
634 SSMR3PutU32(pSSM, pRem->Env.hflags);
635 SSMR3PutU32(pSSM, ~0); /* separator */
636
637 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
638 SSMR3PutU32(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
639 SSMR3PutU32(pSSM, pVM->rem.s.u32PendingInterrupt);
640
641 return SSMR3PutU32(pSSM, ~0); /* terminator */
642}
643
644
645/**
646 * Execute state load operation.
647 *
648 * @returns VBox status code.
649 * @param pVM VM Handle.
650 * @param pSSM SSM operation handle.
651 * @param uVersion Data layout version.
652 * @param uPass The data pass.
653 */
654static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
655{
656 uint32_t u32Dummy;
657 uint32_t fRawRing0 = false;
658 uint32_t u32Sep;
659 uint32_t i;
660 int rc;
661 PREM pRem;
662
663 LogFlow(("remR3Load:\n"));
664 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
665
666 /*
667 * Validate version.
668 */
669 if ( uVersion != REM_SAVED_STATE_VERSION
670 && uVersion != REM_SAVED_STATE_VERSION_VER1_6)
671 {
672 AssertMsgFailed(("remR3Load: Invalid version uVersion=%d!\n", uVersion));
673 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
674 }
675
676 /*
677 * Do a reset to be on the safe side...
678 */
679 REMR3Reset(pVM);
680
681 /*
682 * Ignore all ignorable notifications.
683 * (Not doing this will cause serious trouble.)
684 */
685 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
686
687 /*
688 * Load the required CPU Env bits.
689 * (Not much because we're never in REM when doing the save.)
690 */
691 pRem = &pVM->rem.s;
692 Assert(!pRem->fInREM);
693 SSMR3GetU32(pSSM, &pRem->Env.hflags);
694 if (uVersion == REM_SAVED_STATE_VERSION_VER1_6)
695 {
696 /* Redundant REM CPU state has to be loaded, but can be ignored. */
697 CPUX86State_Ver16 temp;
698 SSMR3GetMem(pSSM, &temp, RT_OFFSETOF(CPUX86State_Ver16, jmp_env));
699 }
700
701 rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
702 if (RT_FAILURE(rc))
703 return rc;
704 if (u32Sep != ~0U)
705 {
706 AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
707 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
708 }
709
710 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
711 SSMR3GetUInt(pSSM, &fRawRing0);
712 if (fRawRing0)
713 pRem->Env.state |= CPU_RAW_RING0;
714
715 if (uVersion == REM_SAVED_STATE_VERSION_VER1_6)
716 {
717 /*
718 * Load the REM stuff.
719 */
720 /** @todo r=bird: We should just drop all these items, restoring doesn't make
721 * sense. */
722 rc = SSMR3GetU32(pSSM, (uint32_t *)&pRem->cInvalidatedPages);
723 if (RT_FAILURE(rc))
724 return rc;
725 if (pRem->cInvalidatedPages > RT_ELEMENTS(pRem->aGCPtrInvalidatedPages))
726 {
727 AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
728 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
729 }
730 for (i = 0; i < pRem->cInvalidatedPages; i++)
731 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
732 }
733
734 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
735 if (RT_FAILURE(rc))
736 return rc;
737
738 /* check the terminator. */
739 rc = SSMR3GetU32(pSSM, &u32Sep);
740 if (RT_FAILURE(rc))
741 return rc;
742 if (u32Sep != ~0U)
743 {
744 AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
745 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
746 }
747
748 /*
749 * Get the CPUID features.
750 */
751 PVMCPU pVCpu = VMMGetCpu(pVM);
752 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
753 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
754
755 /*
756 * Stop ignoring ignorable notifications.
757 */
758 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
759
760 /*
761 * Sync the whole CPU state when executing code in the recompiler.
762 */
763 for (i = 0; i < pVM->cCpus; i++)
764 {
765 PVMCPU pVCpu = &pVM->aCpus[i];
766 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
767 }
768 return VINF_SUCCESS;
769}
770
771
772
773#undef LOG_GROUP
774#define LOG_GROUP LOG_GROUP_REM_RUN
775
776/**
777 * Single steps an instruction in recompiled mode.
778 *
779 * Before calling this function the REM state needs to be in sync with
780 * the VM. Call REMR3State() to perform the sync. It's only necessary
781 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
782 * and after calling REMR3StateBack().
783 *
784 * @returns VBox status code.
785 *
786 * @param pVM VM Handle.
787 * @param pVCpu VMCPU Handle.
788 */
789REMR3DECL(int) REMR3Step(PVM pVM, PVMCPU pVCpu)
790{
791 int rc, interrupt_request;
792 RTGCPTR GCPtrPC;
793 bool fBp;
794
795 /*
796 * Lock the REM - we don't wanna have anyone interrupting us
797 * while stepping - and enabled single stepping. We also ignore
798 * pending interrupts and suchlike.
799 */
800 interrupt_request = pVM->rem.s.Env.interrupt_request;
801 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB | CPU_INTERRUPT_EXTERNAL_TIMER)));
802 pVM->rem.s.Env.interrupt_request = 0;
803 cpu_single_step(&pVM->rem.s.Env, 1);
804
805 /*
806 * If we're standing at a breakpoint, that have to be disabled before we start stepping.
807 */
808 GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
809 fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC, BP_GDB);
810
811 /*
812 * Execute and handle the return code.
813 * We execute without enabling the cpu tick, so on success we'll
814 * just flip it on and off to make sure it moves
815 */
816 rc = cpu_exec(&pVM->rem.s.Env);
817 if (rc == EXCP_DEBUG)
818 {
819 TMR3NotifyResume(pVM, pVCpu);
820 TMR3NotifySuspend(pVM, pVCpu);
821 rc = VINF_EM_DBG_STEPPED;
822 }
823 else
824 {
825 switch (rc)
826 {
827 case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
828 case EXCP_HLT:
829 case EXCP_HALTED: rc = VINF_EM_HALT; break;
830 case EXCP_RC:
831 rc = pVM->rem.s.rc;
832 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
833 break;
834 case EXCP_EXECUTE_RAW:
835 case EXCP_EXECUTE_HM:
836 /** @todo: is it correct? No! */
837 rc = VINF_SUCCESS;
838 break;
839 default:
840 AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
841 rc = VERR_INTERNAL_ERROR;
842 break;
843 }
844 }
845
846 /*
847 * Restore the stuff we changed to prevent interruption.
848 * Unlock the REM.
849 */
850 if (fBp)
851 {
852 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC, BP_GDB, NULL);
853 Assert(rc2 == 0); NOREF(rc2);
854 }
855 cpu_single_step(&pVM->rem.s.Env, 0);
856 pVM->rem.s.Env.interrupt_request = interrupt_request;
857
858 return rc;
859}
860
861
862/**
863 * Set a breakpoint using the REM facilities.
864 *
865 * @returns VBox status code.
866 * @param pVM The VM handle.
867 * @param Address The breakpoint address.
868 * @thread The emulation thread.
869 */
870REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
871{
872 VM_ASSERT_EMT(pVM);
873 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address, BP_GDB, NULL))
874 {
875 LogFlow(("REMR3BreakpointSet: Address=%RGv\n", Address));
876 return VINF_SUCCESS;
877 }
878 LogFlow(("REMR3BreakpointSet: Address=%RGv - failed!\n", Address));
879 return VERR_REM_NO_MORE_BP_SLOTS;
880}
881
882
883/**
884 * Clears a breakpoint set by REMR3BreakpointSet().
885 *
886 * @returns VBox status code.
887 * @param pVM The VM handle.
888 * @param Address The breakpoint address.
889 * @thread The emulation thread.
890 */
891REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
892{
893 VM_ASSERT_EMT(pVM);
894 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address, BP_GDB))
895 {
896 LogFlow(("REMR3BreakpointClear: Address=%RGv\n", Address));
897 return VINF_SUCCESS;
898 }
899 LogFlow(("REMR3BreakpointClear: Address=%RGv - not found!\n", Address));
900 return VERR_REM_BP_NOT_FOUND;
901}
902
903
904/**
905 * Emulate an instruction.
906 *
907 * This function executes one instruction without letting anyone
908 * interrupt it. This is intended for being called while being in
909 * raw mode and thus will take care of all the state syncing between
910 * REM and the rest.
911 *
912 * @returns VBox status code.
913 * @param pVM VM handle.
914 * @param pVCpu VMCPU Handle.
915 */
916REMR3DECL(int) REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu)
917{
918 bool fFlushTBs;
919
920 int rc, rc2;
921 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
922
923 /* Make sure this flag is set; we might never execute remR3CanExecuteRaw in the AMD-V case.
924 * CPU_RAW_HM makes sure we never execute interrupt handlers in the recompiler.
925 */
926 if (HMIsEnabled(pVM))
927 pVM->rem.s.Env.state |= CPU_RAW_HM;
928
929 /* Skip the TB flush as that's rather expensive and not necessary for single instruction emulation. */
930 fFlushTBs = pVM->rem.s.fFlushTBs;
931 pVM->rem.s.fFlushTBs = false;
932
933 /*
934 * Sync the state and enable single instruction / single stepping.
935 */
936 rc = REMR3State(pVM, pVCpu);
937 pVM->rem.s.fFlushTBs = fFlushTBs;
938 if (RT_SUCCESS(rc))
939 {
940 int interrupt_request = pVM->rem.s.Env.interrupt_request;
941 Assert(!( interrupt_request
942 & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD
943 | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB | CPU_INTERRUPT_EXTERNAL_TIMER
944 | CPU_INTERRUPT_EXTERNAL_DMA)));
945#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
946 cpu_single_step(&pVM->rem.s.Env, 0);
947#endif
948 Assert(!pVM->rem.s.Env.singlestep_enabled);
949
950 /*
951 * Now we set the execute single instruction flag and enter the cpu_exec loop.
952 */
953 TMNotifyStartOfExecution(pVCpu);
954 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
955 rc = cpu_exec(&pVM->rem.s.Env);
956 TMNotifyEndOfExecution(pVCpu);
957 switch (rc)
958 {
959 /*
960 * Executed without anything out of the way happening.
961 */
962 case EXCP_SINGLE_INSTR:
963 rc = VINF_EM_RESCHEDULE;
964 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
965 break;
966
967 /*
968 * If we take a trap or start servicing a pending interrupt, we might end up here.
969 * (Timer thread or some other thread wishing EMT's attention.)
970 */
971 case EXCP_INTERRUPT:
972 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
973 rc = VINF_EM_RESCHEDULE;
974 break;
975
976 /*
977 * Single step, we assume!
978 * If there was a breakpoint there we're fucked now.
979 */
980 case EXCP_DEBUG:
981 if (pVM->rem.s.Env.watchpoint_hit)
982 {
983 /** @todo deal with watchpoints */
984 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
985 rc = VINF_EM_DBG_BREAKPOINT;
986 }
987 else
988 {
989 CPUBreakpoint *pBP;
990 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
991 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
992 if (pBP->pc == GCPtrPC)
993 break;
994 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
995 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
996 }
997 break;
998
999 /*
1000 * hlt instruction.
1001 */
1002 case EXCP_HLT:
1003 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
1004 rc = VINF_EM_HALT;
1005 break;
1006
1007 /*
1008 * The VM has halted.
1009 */
1010 case EXCP_HALTED:
1011 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
1012 rc = VINF_EM_HALT;
1013 break;
1014
1015 /*
1016 * Switch to RAW-mode.
1017 */
1018 case EXCP_EXECUTE_RAW:
1019 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1020 rc = VINF_EM_RESCHEDULE_RAW;
1021 break;
1022
1023 /*
1024 * Switch to hardware accelerated RAW-mode.
1025 */
1026 case EXCP_EXECUTE_HM:
1027 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HM\n"));
1028 rc = VINF_EM_RESCHEDULE_HM;
1029 break;
1030
1031 /*
1032 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1033 */
1034 case EXCP_RC:
1035 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
1036 rc = pVM->rem.s.rc;
1037 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1038 break;
1039
1040 /*
1041 * Figure out the rest when they arrive....
1042 */
1043 default:
1044 AssertMsgFailed(("rc=%d\n", rc));
1045 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
1046 rc = VINF_EM_RESCHEDULE;
1047 break;
1048 }
1049
1050 /*
1051 * Switch back the state.
1052 */
1053 pVM->rem.s.Env.interrupt_request = interrupt_request;
1054 rc2 = REMR3StateBack(pVM, pVCpu);
1055 AssertRC(rc2);
1056 }
1057
1058 Log2(("REMR3EmulateInstruction: returns %Rrc (cs:eip=%04x:%RGv)\n",
1059 rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1060 return rc;
1061}
1062
1063
1064/**
1065 * Used by REMR3Run to handle the case where CPU_EMULATE_SINGLE_STEP is set.
1066 *
1067 * @returns VBox status code.
1068 *
1069 * @param pVM The VM handle.
1070 * @param pVCpu The Virtual CPU handle.
1071 */
1072static int remR3RunLoggingStep(PVM pVM, PVMCPU pVCpu)
1073{
1074 int rc;
1075
1076 Assert(pVM->rem.s.fInREM);
1077#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1078 cpu_single_step(&pVM->rem.s.Env, 1);
1079#else
1080 Assert(!pVM->rem.s.Env.singlestep_enabled);
1081#endif
1082
1083 /*
1084 * Now we set the execute single instruction flag and enter the cpu_exec loop.
1085 */
1086 for (;;)
1087 {
1088 char szBuf[256];
1089
1090 /*
1091 * Log the current registers state and instruction.
1092 */
1093 remR3StateUpdate(pVM, pVCpu);
1094 DBGFR3Info(pVM->pUVM, "cpumguest", NULL, NULL);
1095 szBuf[0] = '\0';
1096 rc = DBGFR3DisasInstrEx(pVM->pUVM,
1097 pVCpu->idCpu,
1098 0, /* Sel */ 0, /* GCPtr */
1099 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
1100 szBuf,
1101 sizeof(szBuf),
1102 NULL);
1103 if (RT_FAILURE(rc))
1104 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrEx failed with rc=%Rrc\n", rc);
1105 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
1106
1107 /*
1108 * Execute the instruction.
1109 */
1110 TMNotifyStartOfExecution(pVCpu);
1111
1112 if ( pVM->rem.s.Env.exception_index < 0
1113 || pVM->rem.s.Env.exception_index > 256)
1114 pVM->rem.s.Env.exception_index = -1; /** @todo We need to do similar stuff elsewhere, I think. */
1115
1116#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1117 pVM->rem.s.Env.interrupt_request = 0;
1118#else
1119 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
1120#endif
1121 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
1122 || pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
1123 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
1124 RTLogPrintf("remR3RunLoggingStep: interrupt_request=%#x halted=%d exception_index=%#x\n",
1125 pVM->rem.s.Env.interrupt_request,
1126 pVM->rem.s.Env.halted,
1127 pVM->rem.s.Env.exception_index
1128 );
1129
1130 rc = cpu_exec(&pVM->rem.s.Env);
1131
1132 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> %#x interrupt_request=%#x halted=%d exception_index=%#x\n", rc,
1133 pVM->rem.s.Env.interrupt_request,
1134 pVM->rem.s.Env.halted,
1135 pVM->rem.s.Env.exception_index
1136 );
1137
1138 TMNotifyEndOfExecution(pVCpu);
1139
1140 switch (rc)
1141 {
1142#ifndef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1143 /*
1144 * The normal exit.
1145 */
1146 case EXCP_SINGLE_INSTR:
1147 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1148 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1149 continue;
1150 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n",
1151 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1152 rc = VINF_SUCCESS;
1153 break;
1154
1155#else
1156 /*
1157 * The normal exit, check for breakpoints at PC just to be sure.
1158 */
1159#endif
1160 case EXCP_DEBUG:
1161 if (pVM->rem.s.Env.watchpoint_hit)
1162 {
1163 /** @todo deal with watchpoints */
1164 Log2(("remR3RunLoggingStep: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1165 rc = VINF_EM_DBG_BREAKPOINT;
1166 }
1167 else
1168 {
1169 CPUBreakpoint *pBP;
1170 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1171 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1172 if (pBP->pc == GCPtrPC)
1173 break;
1174 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1175 Log2(("remR3RunLoggingStep: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1176 }
1177#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1178 if (rc == VINF_EM_DBG_STEPPED)
1179 {
1180 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1181 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1182 continue;
1183
1184 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n",
1185 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1186 rc = VINF_SUCCESS;
1187 }
1188#endif
1189 break;
1190
1191 /*
1192 * If we take a trap or start servicing a pending interrupt, we might end up here.
1193 * (Timer thread or some other thread wishing EMT's attention.)
1194 */
1195 case EXCP_INTERRUPT:
1196 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_INTERRUPT rc=VINF_SUCCESS\n");
1197 rc = VINF_SUCCESS;
1198 break;
1199
1200 /*
1201 * hlt instruction.
1202 */
1203 case EXCP_HLT:
1204 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_HLT rc=VINF_EM_HALT\n");
1205 rc = VINF_EM_HALT;
1206 break;
1207
1208 /*
1209 * The VM has halted.
1210 */
1211 case EXCP_HALTED:
1212 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_HALTED rc=VINF_EM_HALT\n");
1213 rc = VINF_EM_HALT;
1214 break;
1215
1216 /*
1217 * Switch to RAW-mode.
1218 */
1219 case EXCP_EXECUTE_RAW:
1220 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_EXECUTE_RAW rc=VINF_EM_RESCHEDULE_RAW\n");
1221 rc = VINF_EM_RESCHEDULE_RAW;
1222 break;
1223
1224 /*
1225 * Switch to hardware accelerated RAW-mode.
1226 */
1227 case EXCP_EXECUTE_HM:
1228 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_EXECUTE_HM rc=VINF_EM_RESCHEDULE_HM\n");
1229 rc = VINF_EM_RESCHEDULE_HM;
1230 break;
1231
1232 /*
1233 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1234 */
1235 case EXCP_RC:
1236 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc);
1237 rc = pVM->rem.s.rc;
1238 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1239 break;
1240
1241 /*
1242 * Figure out the rest when they arrive....
1243 */
1244 default:
1245 AssertMsgFailed(("rc=%d\n", rc));
1246 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> %d rc=VINF_EM_RESCHEDULE\n", rc);
1247 rc = VINF_EM_RESCHEDULE;
1248 break;
1249 }
1250 break;
1251 }
1252
1253#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1254// cpu_single_step(&pVM->rem.s.Env, 0);
1255#else
1256 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_SINGLE_INSTR | CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT);
1257#endif
1258 return rc;
1259}
1260
1261
1262/**
1263 * Runs code in recompiled mode.
1264 *
1265 * Before calling this function the REM state needs to be in sync with
1266 * the VM. Call REMR3State() to perform the sync. It's only necessary
1267 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
1268 * and after calling REMR3StateBack().
1269 *
1270 * @returns VBox status code.
1271 *
1272 * @param pVM VM Handle.
1273 * @param pVCpu VMCPU Handle.
1274 */
1275REMR3DECL(int) REMR3Run(PVM pVM, PVMCPU pVCpu)
1276{
1277 int rc;
1278
1279 if (RT_UNLIKELY(pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP))
1280 return remR3RunLoggingStep(pVM, pVCpu);
1281
1282 Assert(pVM->rem.s.fInREM);
1283 Log2(("REMR3Run: (cs:eip=%04x:%RGv)\n", pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1284
1285 TMNotifyStartOfExecution(pVCpu);
1286 rc = cpu_exec(&pVM->rem.s.Env);
1287 TMNotifyEndOfExecution(pVCpu);
1288 switch (rc)
1289 {
1290 /*
1291 * This happens when the execution was interrupted
1292 * by an external event, like pending timers.
1293 */
1294 case EXCP_INTERRUPT:
1295 Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
1296 rc = VINF_SUCCESS;
1297 break;
1298
1299 /*
1300 * hlt instruction.
1301 */
1302 case EXCP_HLT:
1303 Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
1304 rc = VINF_EM_HALT;
1305 break;
1306
1307 /*
1308 * The VM has halted.
1309 */
1310 case EXCP_HALTED:
1311 Log2(("REMR3Run: cpu_exec -> EXCP_HALTED\n"));
1312 rc = VINF_EM_HALT;
1313 break;
1314
1315 /*
1316 * Breakpoint/single step.
1317 */
1318 case EXCP_DEBUG:
1319 if (pVM->rem.s.Env.watchpoint_hit)
1320 {
1321 /** @todo deal with watchpoints */
1322 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1323 rc = VINF_EM_DBG_BREAKPOINT;
1324 }
1325 else
1326 {
1327 CPUBreakpoint *pBP;
1328 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1329 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1330 if (pBP->pc == GCPtrPC)
1331 break;
1332 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1333 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1334 }
1335 break;
1336
1337 /*
1338 * Switch to RAW-mode.
1339 */
1340 case EXCP_EXECUTE_RAW:
1341 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW pc=%RGv\n", pVM->rem.s.Env.eip));
1342 rc = VINF_EM_RESCHEDULE_RAW;
1343 break;
1344
1345 /*
1346 * Switch to hardware accelerated RAW-mode.
1347 */
1348 case EXCP_EXECUTE_HM:
1349 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_HM\n"));
1350 rc = VINF_EM_RESCHEDULE_HM;
1351 break;
1352
1353 /*
1354 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1355 */
1356 case EXCP_RC:
1357 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1358 rc = pVM->rem.s.rc;
1359 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1360 break;
1361
1362 /*
1363 * Figure out the rest when they arrive....
1364 */
1365 default:
1366 AssertMsgFailed(("rc=%d\n", rc));
1367 Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1368 rc = VINF_SUCCESS;
1369 break;
1370 }
1371
1372 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%RGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1373 return rc;
1374}
1375
1376
1377/**
1378 * Check if the cpu state is suitable for Raw execution.
1379 *
1380 * @returns true if RAW/HWACC mode is ok, false if we should stay in REM.
1381 *
1382 * @param env The CPU env struct.
1383 * @param eip The EIP to check this for (might differ from env->eip).
1384 * @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1385 * @param piException Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1386 *
1387 * @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1388 */
1389bool remR3CanExecuteRaw(CPUX86State *env, RTGCPTR eip, unsigned fFlags, int *piException)
1390{
1391 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1392 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1393 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1394 uint32_t u32CR0;
1395
1396#ifdef IEM_VERIFICATION_MODE
1397 return false;
1398#endif
1399
1400 /* Update counter. */
1401 env->pVM->rem.s.cCanExecuteRaw++;
1402
1403 /* Never when single stepping+logging guest code. */
1404 if (env->state & CPU_EMULATE_SINGLE_STEP)
1405 return false;
1406
1407 if (HMIsEnabled(env->pVM))
1408 {
1409#ifdef RT_OS_WINDOWS
1410 PCPUMCTX pCtx = alloca(sizeof(*pCtx));
1411#else
1412 CPUMCTX Ctx;
1413 PCPUMCTX pCtx = &Ctx;
1414#endif
1415
1416 env->state |= CPU_RAW_HM;
1417
1418 /*
1419 * The simple check first...
1420 */
1421 if (!EMIsHwVirtExecutionEnabled(env->pVM))
1422 return false;
1423
1424 /*
1425 * Create partial context for HMR3CanExecuteGuest
1426 */
1427 pCtx->cr0 = env->cr[0];
1428 pCtx->cr3 = env->cr[3];
1429 pCtx->cr4 = env->cr[4];
1430
1431 pCtx->tr.Sel = env->tr.selector;
1432 pCtx->tr.ValidSel = env->tr.selector;
1433 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1434 pCtx->tr.u64Base = env->tr.base;
1435 pCtx->tr.u32Limit = env->tr.limit;
1436 pCtx->tr.Attr.u = (env->tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1437
1438 pCtx->ldtr.Sel = env->ldt.selector;
1439 pCtx->ldtr.ValidSel = env->ldt.selector;
1440 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1441 pCtx->ldtr.u64Base = env->ldt.base;
1442 pCtx->ldtr.u32Limit = env->ldt.limit;
1443 pCtx->ldtr.Attr.u = (env->ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1444
1445 pCtx->idtr.cbIdt = env->idt.limit;
1446 pCtx->idtr.pIdt = env->idt.base;
1447
1448 pCtx->gdtr.cbGdt = env->gdt.limit;
1449 pCtx->gdtr.pGdt = env->gdt.base;
1450
1451 pCtx->rsp = env->regs[R_ESP];
1452 pCtx->rip = env->eip;
1453
1454 pCtx->eflags.u32 = env->eflags;
1455
1456 pCtx->cs.Sel = env->segs[R_CS].selector;
1457 pCtx->cs.ValidSel = env->segs[R_CS].selector;
1458 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1459 pCtx->cs.u64Base = env->segs[R_CS].base;
1460 pCtx->cs.u32Limit = env->segs[R_CS].limit;
1461 pCtx->cs.Attr.u = (env->segs[R_CS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1462
1463 pCtx->ds.Sel = env->segs[R_DS].selector;
1464 pCtx->ds.ValidSel = env->segs[R_DS].selector;
1465 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1466 pCtx->ds.u64Base = env->segs[R_DS].base;
1467 pCtx->ds.u32Limit = env->segs[R_DS].limit;
1468 pCtx->ds.Attr.u = (env->segs[R_DS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1469
1470 pCtx->es.Sel = env->segs[R_ES].selector;
1471 pCtx->es.ValidSel = env->segs[R_ES].selector;
1472 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1473 pCtx->es.u64Base = env->segs[R_ES].base;
1474 pCtx->es.u32Limit = env->segs[R_ES].limit;
1475 pCtx->es.Attr.u = (env->segs[R_ES].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1476
1477 pCtx->fs.Sel = env->segs[R_FS].selector;
1478 pCtx->fs.ValidSel = env->segs[R_FS].selector;
1479 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1480 pCtx->fs.u64Base = env->segs[R_FS].base;
1481 pCtx->fs.u32Limit = env->segs[R_FS].limit;
1482 pCtx->fs.Attr.u = (env->segs[R_FS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1483
1484 pCtx->gs.Sel = env->segs[R_GS].selector;
1485 pCtx->gs.ValidSel = env->segs[R_GS].selector;
1486 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1487 pCtx->gs.u64Base = env->segs[R_GS].base;
1488 pCtx->gs.u32Limit = env->segs[R_GS].limit;
1489 pCtx->gs.Attr.u = (env->segs[R_GS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1490
1491 pCtx->ss.Sel = env->segs[R_SS].selector;
1492 pCtx->ss.ValidSel = env->segs[R_SS].selector;
1493 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1494 pCtx->ss.u64Base = env->segs[R_SS].base;
1495 pCtx->ss.u32Limit = env->segs[R_SS].limit;
1496 pCtx->ss.Attr.u = (env->segs[R_SS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1497
1498 pCtx->msrEFER = env->efer;
1499
1500 /* Hardware accelerated raw-mode:
1501 *
1502 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1503 */
1504 if (HMR3CanExecuteGuest(env->pVM, pCtx) == true)
1505 {
1506 *piException = EXCP_EXECUTE_HM;
1507 return true;
1508 }
1509 return false;
1510 }
1511
1512 /*
1513 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1514 * or 32 bits protected mode ring 0 code
1515 *
1516 * The tests are ordered by the likelihood of being true during normal execution.
1517 */
1518 if (fFlags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))
1519 {
1520 STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1521 Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1522 return false;
1523 }
1524
1525#ifndef VBOX_RAW_V86
1526 if (fFlags & VM_MASK) {
1527 STAM_COUNTER_INC(&gStatRefuseVM86);
1528 Log2(("raw mode refused: VM_MASK\n"));
1529 return false;
1530 }
1531#endif
1532
1533 if (env->state & CPU_EMULATE_SINGLE_INSTR)
1534 {
1535#ifndef DEBUG_bird
1536 Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1537#endif
1538 return false;
1539 }
1540
1541 if (env->singlestep_enabled)
1542 {
1543 //Log2(("raw mode refused: Single step\n"));
1544 return false;
1545 }
1546
1547 if (!QTAILQ_EMPTY(&env->breakpoints))
1548 {
1549 //Log2(("raw mode refused: Breakpoints\n"));
1550 return false;
1551 }
1552
1553 if (!QTAILQ_EMPTY(&env->watchpoints))
1554 {
1555 //Log2(("raw mode refused: Watchpoints\n"));
1556 return false;
1557 }
1558
1559 u32CR0 = env->cr[0];
1560 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1561 {
1562 STAM_COUNTER_INC(&gStatRefusePaging);
1563 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1564 return false;
1565 }
1566
1567 if (env->cr[4] & CR4_PAE_MASK)
1568 {
1569 if (!(env->cpuid_features & X86_CPUID_FEATURE_EDX_PAE))
1570 {
1571 STAM_COUNTER_INC(&gStatRefusePAE);
1572 return false;
1573 }
1574 }
1575
1576 if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1577 {
1578 if (!EMIsRawRing3Enabled(env->pVM))
1579 return false;
1580
1581 if (!(env->eflags & IF_MASK))
1582 {
1583 STAM_COUNTER_INC(&gStatRefuseIF0);
1584 Log2(("raw mode refused: IF (RawR3)\n"));
1585 return false;
1586 }
1587
1588 if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1589 {
1590 STAM_COUNTER_INC(&gStatRefuseWP0);
1591 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1592 return false;
1593 }
1594 }
1595 else
1596 {
1597 if (!EMIsRawRing0Enabled(env->pVM))
1598 return false;
1599
1600 // Let's start with pure 32 bits ring 0 code first
1601 if ((fFlags & (HF_SS32_MASK | HF_CS32_MASK)) != (HF_SS32_MASK | HF_CS32_MASK))
1602 {
1603 STAM_COUNTER_INC(&gStatRefuseCode16);
1604 Log2(("raw r0 mode refused: HF_[S|C]S32_MASK fFlags=%#x\n", fFlags));
1605 return false;
1606 }
1607
1608 if (EMIsRawRing1Enabled(env->pVM))
1609 {
1610 /* Only ring 0 and 1 supervisor code. */
1611 if (((fFlags >> HF_CPL_SHIFT) & 3) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1612 {
1613 Log2(("raw r0 mode refused: CPL %d\n", (fFlags >> HF_CPL_SHIFT) & 3));
1614 return false;
1615 }
1616 }
1617 /* Only R0. */
1618 else if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1619 {
1620 STAM_COUNTER_INC(&gStatRefuseRing1or2);
1621 Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1622 return false;
1623 }
1624
1625 if (!(u32CR0 & CR0_WP_MASK))
1626 {
1627 STAM_COUNTER_INC(&gStatRefuseWP0);
1628 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1629 return false;
1630 }
1631
1632#ifdef VBOX_WITH_RAW_MODE
1633 if (PATMIsPatchGCAddr(env->pVM, eip))
1634 {
1635 Log2(("raw r0 mode forced: patch code\n"));
1636 *piException = EXCP_EXECUTE_RAW;
1637 return true;
1638 }
1639#endif
1640
1641#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1642 if (!(env->eflags & IF_MASK))
1643 {
1644 STAM_COUNTER_INC(&gStatRefuseIF0);
1645 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1646 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1647 return false;
1648 }
1649#endif
1650
1651#ifndef VBOX_WITH_RAW_RING1
1652 if (((env->eflags >> IOPL_SHIFT) & 3) != 0)
1653 {
1654 Log2(("raw r0 mode refused: IOPL %d\n", ((env->eflags >> IOPL_SHIFT) & 3)));
1655 return false;
1656 }
1657#endif
1658 env->state |= CPU_RAW_RING0;
1659 }
1660
1661 /*
1662 * Don't reschedule the first time we're called, because there might be
1663 * special reasons why we're here that is not covered by the above checks.
1664 */
1665 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1666 {
1667 Log2(("raw mode refused: first scheduling\n"));
1668 STAM_COUNTER_INC(&gStatRefuseCanExecute);
1669 return false;
1670 }
1671
1672 /*
1673 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1674 */
1675 if (env->segs[R_CS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1676 {
1677 Log2(("raw mode refused: stale CS (%#x)\n", env->segs[R_CS].selector));
1678 STAM_COUNTER_INC(&gaStatRefuseStale[R_CS]);
1679 return false;
1680 }
1681 if (env->segs[R_SS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1682 {
1683 Log2(("raw mode refused: stale SS (%#x)\n", env->segs[R_SS].selector));
1684 STAM_COUNTER_INC(&gaStatRefuseStale[R_SS]);
1685 return false;
1686 }
1687 if (env->segs[R_DS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1688 {
1689 Log2(("raw mode refused: stale DS (%#x)\n", env->segs[R_DS].selector));
1690 STAM_COUNTER_INC(&gaStatRefuseStale[R_DS]);
1691 return false;
1692 }
1693 if (env->segs[R_ES].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1694 {
1695 Log2(("raw mode refused: stale ES (%#x)\n", env->segs[R_ES].selector));
1696 STAM_COUNTER_INC(&gaStatRefuseStale[R_ES]);
1697 return false;
1698 }
1699 if (env->segs[R_FS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1700 {
1701 Log2(("raw mode refused: stale FS (%#x)\n", env->segs[R_FS].selector));
1702 STAM_COUNTER_INC(&gaStatRefuseStale[R_FS]);
1703 return false;
1704 }
1705 if (env->segs[R_GS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1706 {
1707 Log2(("raw mode refused: stale GS (%#x)\n", env->segs[R_GS].selector));
1708 STAM_COUNTER_INC(&gaStatRefuseStale[R_GS]);
1709 return false;
1710 }
1711
1712/* Assert(env->pVCpu && PGMPhysIsA20Enabled(env->pVCpu));*/
1713 *piException = EXCP_EXECUTE_RAW;
1714 return true;
1715}
1716
1717
1718#ifdef VBOX_WITH_RAW_MODE
1719/**
1720 * Fetches a code byte.
1721 *
1722 * @returns Success indicator (bool) for ease of use.
1723 * @param env The CPU environment structure.
1724 * @param GCPtrInstr Where to fetch code.
1725 * @param pu8Byte Where to store the byte on success
1726 */
1727bool remR3GetOpcode(CPUX86State *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte)
1728{
1729 int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1730 if (RT_SUCCESS(rc))
1731 return true;
1732 return false;
1733}
1734#endif /* VBOX_WITH_RAW_MODE */
1735
1736
1737/**
1738 * Flush (or invalidate if you like) page table/dir entry.
1739 *
1740 * (invlpg instruction; tlb_flush_page)
1741 *
1742 * @param env Pointer to cpu environment.
1743 * @param GCPtr The virtual address which page table/dir entry should be invalidated.
1744 */
1745void remR3FlushPage(CPUX86State *env, RTGCPTR GCPtr)
1746{
1747 PVM pVM = env->pVM;
1748 PCPUMCTX pCtx;
1749 int rc;
1750
1751 Assert(EMRemIsLockOwner(env->pVM));
1752
1753 /*
1754 * When we're replaying invlpg instructions or restoring a saved
1755 * state we disable this path.
1756 */
1757 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.cIgnoreAll)
1758 return;
1759 LogFlow(("remR3FlushPage: GCPtr=%RGv\n", GCPtr));
1760 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1761
1762 //RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1763
1764 /*
1765 * Update the control registers before calling PGMFlushPage.
1766 */
1767 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1768 Assert(pCtx);
1769 pCtx->cr0 = env->cr[0];
1770 pCtx->cr3 = env->cr[3];
1771#ifdef VBOX_WITH_RAW_MODE
1772 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1773 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1774#endif
1775 pCtx->cr4 = env->cr[4];
1776
1777 /*
1778 * Let PGM do the rest.
1779 */
1780 Assert(env->pVCpu);
1781 rc = PGMInvalidatePage(env->pVCpu, GCPtr);
1782 if (RT_FAILURE(rc))
1783 {
1784 AssertMsgFailed(("remR3FlushPage %RGv failed with %d!!\n", GCPtr, rc));
1785 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1786 }
1787 //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1788}
1789
1790
1791#ifndef REM_PHYS_ADDR_IN_TLB
1792/** Wrapper for PGMR3PhysTlbGCPhys2Ptr. */
1793void *remR3TlbGCPhys2Ptr(CPUX86State *env1, target_ulong physAddr, int fWritable)
1794{
1795 void *pv;
1796 int rc;
1797
1798
1799 /* Address must be aligned enough to fiddle with lower bits */
1800 Assert((physAddr & 0x3) == 0);
1801 /*AssertMsg((env1->a20_mask & physAddr) == physAddr, ("%llx\n", (uint64_t)physAddr));*/
1802
1803 STAM_PROFILE_START(&gStatGCPhys2HCVirt, a);
1804 rc = PGMR3PhysTlbGCPhys2Ptr(env1->pVM, physAddr, true /*fWritable*/, &pv);
1805 STAM_PROFILE_STOP(&gStatGCPhys2HCVirt, a);
1806 Assert( rc == VINF_SUCCESS
1807 || rc == VINF_PGM_PHYS_TLB_CATCH_WRITE
1808 || rc == VERR_PGM_PHYS_TLB_CATCH_ALL
1809 || rc == VERR_PGM_PHYS_TLB_UNASSIGNED);
1810 if (RT_FAILURE(rc))
1811 return (void *)1;
1812 if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
1813 return (void *)((uintptr_t)pv | 2);
1814 return pv;
1815}
1816#endif /* REM_PHYS_ADDR_IN_TLB */
1817
1818
1819/**
1820 * Called from tlb_protect_code in order to write monitor a code page.
1821 *
1822 * @param env Pointer to the CPU environment.
1823 * @param GCPtr Code page to monitor
1824 */
1825void remR3ProtectCode(CPUX86State *env, RTGCPTR GCPtr)
1826{
1827#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1828 Assert(env->pVM->rem.s.fInREM);
1829 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1830 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1831 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1832 && !(env->eflags & VM_MASK) /* no V86 mode */
1833 && !HMIsEnabled(env->pVM))
1834 CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1835#endif
1836}
1837
1838
1839/**
1840 * Called from tlb_unprotect_code in order to clear write monitoring for a code page.
1841 *
1842 * @param env Pointer to the CPU environment.
1843 * @param GCPtr Code page to monitor
1844 */
1845void remR3UnprotectCode(CPUX86State *env, RTGCPTR GCPtr)
1846{
1847 Assert(env->pVM->rem.s.fInREM);
1848#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1849 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1850 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1851 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1852 && !(env->eflags & VM_MASK) /* no V86 mode */
1853 && !HMIsEnabled(env->pVM))
1854 CSAMR3UnmonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1855#endif
1856}
1857
1858
1859/**
1860 * Called when the CPU is initialized, any of the CRx registers are changed or
1861 * when the A20 line is modified.
1862 *
1863 * @param env Pointer to the CPU environment.
1864 * @param fGlobal Set if the flush is global.
1865 */
1866void remR3FlushTLB(CPUX86State *env, bool fGlobal)
1867{
1868 PVM pVM = env->pVM;
1869 PCPUMCTX pCtx;
1870 Assert(EMRemIsLockOwner(pVM));
1871
1872 /*
1873 * When we're replaying invlpg instructions or restoring a saved
1874 * state we disable this path.
1875 */
1876 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.cIgnoreAll)
1877 return;
1878 Assert(pVM->rem.s.fInREM);
1879
1880 /*
1881 * The caller doesn't check cr4, so we have to do that for ourselves.
1882 */
1883 if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1884 fGlobal = true;
1885 Log(("remR3FlushTLB: CR0=%08RX64 CR3=%08RX64 CR4=%08RX64 %s\n", (uint64_t)env->cr[0], (uint64_t)env->cr[3], (uint64_t)env->cr[4], fGlobal ? " global" : ""));
1886
1887 /*
1888 * Update the control registers before calling PGMR3FlushTLB.
1889 */
1890 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1891 Assert(pCtx);
1892 pCtx->cr0 = env->cr[0];
1893 pCtx->cr3 = env->cr[3];
1894#ifdef VBOX_WITH_RAW_MODE
1895 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1896 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1897#endif
1898 pCtx->cr4 = env->cr[4];
1899
1900 /*
1901 * Let PGM do the rest.
1902 */
1903 Assert(env->pVCpu);
1904 PGMFlushTLB(env->pVCpu, env->cr[3], fGlobal);
1905}
1906
1907
1908/**
1909 * Called when any of the cr0, cr4 or efer registers is updated.
1910 *
1911 * @param env Pointer to the CPU environment.
1912 */
1913void remR3ChangeCpuMode(CPUX86State *env)
1914{
1915 PVM pVM = env->pVM;
1916 uint64_t efer;
1917 PCPUMCTX pCtx;
1918 int rc;
1919
1920 /*
1921 * When we're replaying loads or restoring a saved
1922 * state this path is disabled.
1923 */
1924 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.cIgnoreAll)
1925 return;
1926 Assert(pVM->rem.s.fInREM);
1927
1928 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1929 Assert(pCtx);
1930
1931 /*
1932 * Notify PGM about WP0 being enabled (like CPUSetGuestCR0 does).
1933 */
1934 if (((env->cr[0] ^ pCtx->cr0) & X86_CR0_WP) && (env->cr[0] & X86_CR0_WP))
1935 PGMCr0WpEnabled(env->pVCpu);
1936
1937 /*
1938 * Update the control registers before calling PGMChangeMode()
1939 * as it may need to map whatever cr3 is pointing to.
1940 */
1941 pCtx->cr0 = env->cr[0];
1942 pCtx->cr3 = env->cr[3];
1943#ifdef VBOX_WITH_RAW_MODE
1944 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1945 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1946#endif
1947 pCtx->cr4 = env->cr[4];
1948#ifdef TARGET_X86_64
1949 efer = env->efer;
1950 pCtx->msrEFER = efer;
1951#else
1952 efer = 0;
1953#endif
1954 Assert(env->pVCpu);
1955 rc = PGMChangeMode(env->pVCpu, env->cr[0], env->cr[4], efer);
1956 if (rc != VINF_SUCCESS)
1957 {
1958 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1959 {
1960 Log(("PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc -> remR3RaiseRC\n", env->cr[0], env->cr[4], efer, rc));
1961 remR3RaiseRC(env->pVM, rc);
1962 }
1963 else
1964 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], efer, rc);
1965 }
1966}
1967
1968
1969/**
1970 * Called from compiled code to run dma.
1971 *
1972 * @param env Pointer to the CPU environment.
1973 */
1974void remR3DmaRun(CPUX86State *env)
1975{
1976 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1977 PDMR3DmaRun(env->pVM);
1978 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1979}
1980
1981
1982/**
1983 * Called from compiled code to schedule pending timers in VMM
1984 *
1985 * @param env Pointer to the CPU environment.
1986 */
1987void remR3TimersRun(CPUX86State *env)
1988{
1989 LogFlow(("remR3TimersRun:\n"));
1990 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("remR3TimersRun\n"));
1991 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1992 remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1993 TMR3TimerQueuesDo(env->pVM);
1994 remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1995 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1996}
1997
1998
1999/**
2000 * Record trap occurrence
2001 *
2002 * @returns VBox status code
2003 * @param env Pointer to the CPU environment.
2004 * @param uTrap Trap nr
2005 * @param uErrorCode Error code
2006 * @param pvNextEIP Next EIP
2007 */
2008int remR3NotifyTrap(CPUX86State *env, uint32_t uTrap, uint32_t uErrorCode, RTGCPTR pvNextEIP)
2009{
2010 PVM pVM = env->pVM;
2011#ifdef VBOX_WITH_STATISTICS
2012 static STAMCOUNTER s_aStatTrap[255];
2013 static bool s_aRegisters[RT_ELEMENTS(s_aStatTrap)];
2014#endif
2015
2016#ifdef VBOX_WITH_STATISTICS
2017 if (uTrap < 255)
2018 {
2019 if (!s_aRegisters[uTrap])
2020 {
2021 char szStatName[64];
2022 s_aRegisters[uTrap] = true;
2023 RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
2024 STAM_REG(env->pVM, &s_aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
2025 }
2026 STAM_COUNTER_INC(&s_aStatTrap[uTrap]);
2027 }
2028#endif
2029 Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
2030 if( uTrap < 0x20
2031 && (env->cr[0] & X86_CR0_PE)
2032 && !(env->eflags & X86_EFL_VM))
2033 {
2034#ifdef DEBUG
2035 remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
2036#endif
2037 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
2038 {
2039 LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
2040 remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
2041 return VERR_REM_TOO_MANY_TRAPS;
2042 }
2043 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
2044 {
2045 Log(("remR3NotifyTrap: uTrap=%#x set as pending\n", uTrap));
2046 pVM->rem.s.cPendingExceptions = 1;
2047 }
2048 pVM->rem.s.uPendingException = uTrap;
2049 pVM->rem.s.uPendingExcptEIP = env->eip;
2050 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2051 }
2052 else
2053 {
2054 pVM->rem.s.cPendingExceptions = 0;
2055 pVM->rem.s.uPendingException = uTrap;
2056 pVM->rem.s.uPendingExcptEIP = env->eip;
2057 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2058 }
2059 return VINF_SUCCESS;
2060}
2061
2062
2063/*
2064 * Clear current active trap
2065 *
2066 * @param pVM VM Handle.
2067 */
2068void remR3TrapClear(PVM pVM)
2069{
2070 pVM->rem.s.cPendingExceptions = 0;
2071 pVM->rem.s.uPendingException = 0;
2072 pVM->rem.s.uPendingExcptEIP = 0;
2073 pVM->rem.s.uPendingExcptCR2 = 0;
2074}
2075
2076
2077/*
2078 * Record previous call instruction addresses
2079 *
2080 * @param env Pointer to the CPU environment.
2081 */
2082void remR3RecordCall(CPUX86State *env)
2083{
2084#ifdef VBOX_WITH_RAW_MODE
2085 CSAMR3RecordCallAddress(env->pVM, env->eip);
2086#endif
2087}
2088
2089
2090/**
2091 * Syncs the internal REM state with the VM.
2092 *
2093 * This must be called before REMR3Run() is invoked whenever when the REM
2094 * state is not up to date. Calling it several times in a row is not
2095 * permitted.
2096 *
2097 * @returns VBox status code.
2098 *
2099 * @param pVM VM Handle.
2100 * @param pVCpu VMCPU Handle.
2101 *
2102 * @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
2103 * no do this since the majority of the callers don't want any unnecessary of events
2104 * pending that would immediately interrupt execution.
2105 */
2106REMR3DECL(int) REMR3State(PVM pVM, PVMCPU pVCpu)
2107{
2108 register const CPUMCTX *pCtx;
2109 register unsigned fFlags;
2110 unsigned i;
2111 TRPMEVENT enmType;
2112 uint8_t u8TrapNo;
2113 uint32_t uCpl;
2114 int rc;
2115
2116 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
2117 Log2(("REMR3State:\n"));
2118
2119 pVM->rem.s.Env.pVCpu = pVCpu;
2120 pCtx = pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2121
2122 Assert(!pVM->rem.s.fInREM);
2123 pVM->rem.s.fInStateSync = true;
2124
2125 /*
2126 * If we have to flush TBs, do that immediately.
2127 */
2128 if (pVM->rem.s.fFlushTBs)
2129 {
2130 STAM_COUNTER_INC(&gStatFlushTBs);
2131 tb_flush(&pVM->rem.s.Env);
2132 pVM->rem.s.fFlushTBs = false;
2133 }
2134
2135 /*
2136 * Copy the registers which require no special handling.
2137 */
2138#ifdef TARGET_X86_64
2139 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2140 Assert(R_EAX == 0);
2141 pVM->rem.s.Env.regs[R_EAX] = pCtx->rax;
2142 Assert(R_ECX == 1);
2143 pVM->rem.s.Env.regs[R_ECX] = pCtx->rcx;
2144 Assert(R_EDX == 2);
2145 pVM->rem.s.Env.regs[R_EDX] = pCtx->rdx;
2146 Assert(R_EBX == 3);
2147 pVM->rem.s.Env.regs[R_EBX] = pCtx->rbx;
2148 Assert(R_ESP == 4);
2149 pVM->rem.s.Env.regs[R_ESP] = pCtx->rsp;
2150 Assert(R_EBP == 5);
2151 pVM->rem.s.Env.regs[R_EBP] = pCtx->rbp;
2152 Assert(R_ESI == 6);
2153 pVM->rem.s.Env.regs[R_ESI] = pCtx->rsi;
2154 Assert(R_EDI == 7);
2155 pVM->rem.s.Env.regs[R_EDI] = pCtx->rdi;
2156 pVM->rem.s.Env.regs[8] = pCtx->r8;
2157 pVM->rem.s.Env.regs[9] = pCtx->r9;
2158 pVM->rem.s.Env.regs[10] = pCtx->r10;
2159 pVM->rem.s.Env.regs[11] = pCtx->r11;
2160 pVM->rem.s.Env.regs[12] = pCtx->r12;
2161 pVM->rem.s.Env.regs[13] = pCtx->r13;
2162 pVM->rem.s.Env.regs[14] = pCtx->r14;
2163 pVM->rem.s.Env.regs[15] = pCtx->r15;
2164
2165 pVM->rem.s.Env.eip = pCtx->rip;
2166
2167 pVM->rem.s.Env.eflags = pCtx->rflags.u64;
2168#else
2169 Assert(R_EAX == 0);
2170 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
2171 Assert(R_ECX == 1);
2172 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
2173 Assert(R_EDX == 2);
2174 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
2175 Assert(R_EBX == 3);
2176 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
2177 Assert(R_ESP == 4);
2178 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
2179 Assert(R_EBP == 5);
2180 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
2181 Assert(R_ESI == 6);
2182 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
2183 Assert(R_EDI == 7);
2184 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
2185 pVM->rem.s.Env.eip = pCtx->eip;
2186
2187 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
2188#endif
2189
2190 pVM->rem.s.Env.cr[2] = pCtx->cr2;
2191
2192 /** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
2193 for (i=0;i<8;i++)
2194 pVM->rem.s.Env.dr[i] = pCtx->dr[i];
2195
2196#ifdef HF_HALTED_MASK /** @todo remove me when we're up to date again. */
2197 /*
2198 * Clear the halted hidden flag (the interrupt waking up the CPU can
2199 * have been dispatched in raw mode).
2200 */
2201 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
2202#endif
2203
2204 /*
2205 * Replay invlpg? Only if we're not flushing the TLB.
2206 */
2207 fFlags = CPUMR3RemEnter(pVCpu, &uCpl);
2208 LogFlow(("CPUMR3RemEnter %x %x\n", fFlags, uCpl));
2209 if (pVM->rem.s.cInvalidatedPages)
2210 {
2211 if (!(fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH))
2212 {
2213 RTUINT i;
2214
2215 pVM->rem.s.fIgnoreCR3Load = true;
2216 pVM->rem.s.fIgnoreInvlPg = true;
2217 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2218 {
2219 Log2(("REMR3State: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2220 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2221 }
2222 pVM->rem.s.fIgnoreInvlPg = false;
2223 pVM->rem.s.fIgnoreCR3Load = false;
2224 }
2225 pVM->rem.s.cInvalidatedPages = 0;
2226 }
2227
2228 /* Replay notification changes. */
2229 REMR3ReplayHandlerNotifications(pVM);
2230
2231 /* Update MSRs; before CRx registers! */
2232 pVM->rem.s.Env.efer = pCtx->msrEFER;
2233 pVM->rem.s.Env.star = pCtx->msrSTAR;
2234 pVM->rem.s.Env.pat = pCtx->msrPAT;
2235#ifdef TARGET_X86_64
2236 pVM->rem.s.Env.lstar = pCtx->msrLSTAR;
2237 pVM->rem.s.Env.cstar = pCtx->msrCSTAR;
2238 pVM->rem.s.Env.fmask = pCtx->msrSFMASK;
2239 pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
2240
2241 /* Update the internal long mode activate flag according to the new EFER value. */
2242 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
2243 pVM->rem.s.Env.hflags |= HF_LMA_MASK;
2244 else
2245 pVM->rem.s.Env.hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
2246#endif
2247
2248 /* Update the inhibit IRQ mask. */
2249 pVM->rem.s.Env.hflags &= ~HF_INHIBIT_IRQ_MASK;
2250 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2251 {
2252 RTGCPTR InhibitPC = EMGetInhibitInterruptsPC(pVCpu);
2253 if (InhibitPC == pCtx->rip)
2254 pVM->rem.s.Env.hflags |= HF_INHIBIT_IRQ_MASK;
2255 else
2256 {
2257 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#1)\n", (RTGCPTR)pCtx->rip, InhibitPC));
2258 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2259 }
2260 }
2261
2262 /* Update the inhibit NMI mask. */
2263 pVM->rem.s.Env.hflags2 &= ~HF2_NMI_MASK;
2264 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2265 pVM->rem.s.Env.hflags2 |= HF2_NMI_MASK;
2266
2267 /*
2268 * Sync the A20 gate.
2269 */
2270 bool fA20State = PGMPhysIsA20Enabled(pVCpu);
2271 if (fA20State != RT_BOOL(pVM->rem.s.Env.a20_mask & RT_BIT(20)))
2272 {
2273 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
2274 cpu_x86_set_a20(&pVM->rem.s.Env, fA20State);
2275 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
2276 }
2277
2278 /*
2279 * Registers which are rarely changed and require special handling / order when changed.
2280 */
2281 if (fFlags & ( CPUM_CHANGED_GLOBAL_TLB_FLUSH
2282 | CPUM_CHANGED_CR4
2283 | CPUM_CHANGED_CR0
2284 | CPUM_CHANGED_CR3
2285 | CPUM_CHANGED_GDTR
2286 | CPUM_CHANGED_IDTR
2287 | CPUM_CHANGED_SYSENTER_MSR
2288 | CPUM_CHANGED_LDTR
2289 | CPUM_CHANGED_CPUID
2290 | CPUM_CHANGED_FPU_REM
2291 )
2292 )
2293 {
2294 if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
2295 {
2296 pVM->rem.s.fIgnoreCR3Load = true;
2297 tlb_flush(&pVM->rem.s.Env, true);
2298 pVM->rem.s.fIgnoreCR3Load = false;
2299 }
2300
2301 /* CR4 before CR0! */
2302 if (fFlags & CPUM_CHANGED_CR4)
2303 {
2304 pVM->rem.s.fIgnoreCR3Load = true;
2305 pVM->rem.s.fIgnoreCpuMode = true;
2306 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
2307 pVM->rem.s.fIgnoreCpuMode = false;
2308 pVM->rem.s.fIgnoreCR3Load = false;
2309 }
2310
2311 if (fFlags & CPUM_CHANGED_CR0)
2312 {
2313 pVM->rem.s.fIgnoreCR3Load = true;
2314 pVM->rem.s.fIgnoreCpuMode = true;
2315 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
2316 pVM->rem.s.fIgnoreCpuMode = false;
2317 pVM->rem.s.fIgnoreCR3Load = false;
2318 }
2319
2320 if (fFlags & CPUM_CHANGED_CR3)
2321 {
2322 pVM->rem.s.fIgnoreCR3Load = true;
2323 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
2324 pVM->rem.s.fIgnoreCR3Load = false;
2325 }
2326
2327 if (fFlags & CPUM_CHANGED_GDTR)
2328 {
2329 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
2330 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
2331 }
2332
2333 if (fFlags & CPUM_CHANGED_IDTR)
2334 {
2335 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
2336 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
2337 }
2338
2339 if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
2340 {
2341 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
2342 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
2343 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
2344 }
2345
2346 if (fFlags & CPUM_CHANGED_LDTR)
2347 {
2348 if (pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2349 {
2350 pVM->rem.s.Env.ldt.selector = pCtx->ldtr.Sel;
2351 pVM->rem.s.Env.ldt.newselector = 0;
2352 pVM->rem.s.Env.ldt.fVBoxFlags = pCtx->ldtr.fFlags;
2353 pVM->rem.s.Env.ldt.base = pCtx->ldtr.u64Base;
2354 pVM->rem.s.Env.ldt.limit = pCtx->ldtr.u32Limit;
2355 pVM->rem.s.Env.ldt.flags = (pCtx->ldtr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2356 }
2357 else
2358 {
2359 AssertFailed(); /* Shouldn't happen, see cpumR3LoadExec. */
2360 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr.Sel);
2361 }
2362 }
2363
2364 if (fFlags & CPUM_CHANGED_CPUID)
2365 {
2366 uint32_t u32Dummy;
2367
2368 /*
2369 * Get the CPUID features.
2370 */
2371 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
2372 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
2373 }
2374
2375 /* Sync FPU state after CR4, CPUID and EFER (!). */
2376 if (fFlags & CPUM_CHANGED_FPU_REM)
2377 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87); /* 'save' is an excellent name. */
2378 }
2379
2380 /*
2381 * Sync TR unconditionally to make life simpler.
2382 */
2383 pVM->rem.s.Env.tr.selector = pCtx->tr.Sel;
2384 pVM->rem.s.Env.tr.newselector = 0;
2385 pVM->rem.s.Env.tr.fVBoxFlags = pCtx->tr.fFlags;
2386 pVM->rem.s.Env.tr.base = pCtx->tr.u64Base;
2387 pVM->rem.s.Env.tr.limit = pCtx->tr.u32Limit;
2388 pVM->rem.s.Env.tr.flags = (pCtx->tr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2389 /* Note! do_interrupt will fault if the busy flag is still set... */ /** @todo so fix do_interrupt then! */
2390 pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
2391
2392 /*
2393 * Update selector registers.
2394 *
2395 * This must be done *after* we've synced gdt, ldt and crX registers
2396 * since we're reading the GDT/LDT om sync_seg. This will happen with
2397 * saved state which takes a quick dip into rawmode for instance.
2398 *
2399 * CPL/Stack; Note first check this one as the CPL might have changed.
2400 * The wrong CPL can cause QEmu to raise an exception in sync_seg!!
2401 */
2402 cpu_x86_set_cpl(&pVM->rem.s.Env, uCpl);
2403 /* Note! QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
2404#define SYNC_IN_SREG(a_pEnv, a_SReg, a_pRemSReg, a_pVBoxSReg) \
2405 do \
2406 { \
2407 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, a_pVBoxSReg)) \
2408 { \
2409 cpu_x86_load_seg_cache(a_pEnv, R_##a_SReg, \
2410 (a_pVBoxSReg)->Sel, \
2411 (a_pVBoxSReg)->u64Base, \
2412 (a_pVBoxSReg)->u32Limit, \
2413 ((a_pVBoxSReg)->Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT); \
2414 (a_pRemSReg)->fVBoxFlags = (a_pVBoxSReg)->fFlags; \
2415 } \
2416 /* This only-reload-if-changed stuff is the old approach, we should ditch it. */ \
2417 else if ((a_pRemSReg)->selector != (a_pVBoxSReg)->Sel) \
2418 { \
2419 Log2(("REMR3State: " #a_SReg " changed from %04x to %04x!\n", \
2420 (a_pRemSReg)->selector, (a_pVBoxSReg)->Sel)); \
2421 sync_seg(a_pEnv, R_##a_SReg, (a_pVBoxSReg)->Sel); \
2422 if ((a_pRemSReg)->newselector) \
2423 STAM_COUNTER_INC(&gStatSelOutOfSync[R_##a_SReg]); \
2424 } \
2425 else \
2426 (a_pRemSReg)->newselector = 0; \
2427 } while (0)
2428
2429 SYNC_IN_SREG(&pVM->rem.s.Env, CS, &pVM->rem.s.Env.segs[R_CS], &pCtx->cs);
2430 SYNC_IN_SREG(&pVM->rem.s.Env, SS, &pVM->rem.s.Env.segs[R_SS], &pCtx->ss);
2431 SYNC_IN_SREG(&pVM->rem.s.Env, DS, &pVM->rem.s.Env.segs[R_DS], &pCtx->ds);
2432 SYNC_IN_SREG(&pVM->rem.s.Env, ES, &pVM->rem.s.Env.segs[R_ES], &pCtx->es);
2433 SYNC_IN_SREG(&pVM->rem.s.Env, FS, &pVM->rem.s.Env.segs[R_FS], &pCtx->fs);
2434 SYNC_IN_SREG(&pVM->rem.s.Env, GS, &pVM->rem.s.Env.segs[R_GS], &pCtx->gs);
2435 /** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
2436 * be the same but not the base/limit. */
2437
2438 /*
2439 * Check for traps.
2440 */
2441 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
2442 rc = TRPMQueryTrap(pVCpu, &u8TrapNo, &enmType);
2443 if (RT_SUCCESS(rc))
2444 {
2445#ifdef DEBUG
2446 if (u8TrapNo == 0x80)
2447 {
2448 remR3DumpLnxSyscall(pVCpu);
2449 remR3DumpOBsdSyscall(pVCpu);
2450 }
2451#endif
2452
2453 pVM->rem.s.Env.exception_index = u8TrapNo;
2454 if (enmType != TRPM_SOFTWARE_INT)
2455 {
2456 pVM->rem.s.Env.exception_is_int = 0;
2457#ifdef IEM_VERIFICATION_MODE /* Ugly hack, needs proper fixing. */
2458 pVM->rem.s.Env.exception_is_int = enmType == TRPM_HARDWARE_INT ? 0x42 : 0;
2459#endif
2460 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
2461 }
2462 else
2463 {
2464 /*
2465 * The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
2466 * We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
2467 * for int03 and into.
2468 */
2469 pVM->rem.s.Env.exception_is_int = 1;
2470 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 2;
2471 /* int 3 may be generated by one-byte 0xcc */
2472 if (u8TrapNo == 3)
2473 {
2474 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xcc)
2475 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2476 }
2477 /* int 4 may be generated by one-byte 0xce */
2478 else if (u8TrapNo == 4)
2479 {
2480 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xce)
2481 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2482 }
2483 }
2484
2485 /* get error code and cr2 if needed. */
2486 if (enmType == TRPM_TRAP)
2487 {
2488 switch (u8TrapNo)
2489 {
2490 case X86_XCPT_PF:
2491 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVCpu);
2492 /* fallthru */
2493 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP:
2494 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVCpu);
2495 break;
2496
2497 case X86_XCPT_AC: case X86_XCPT_DF:
2498 default:
2499 pVM->rem.s.Env.error_code = 0;
2500 break;
2501 }
2502 }
2503 else
2504 pVM->rem.s.Env.error_code = 0;
2505
2506 /*
2507 * We can now reset the active trap since the recompiler is gonna have a go at it.
2508 */
2509 rc = TRPMResetTrap(pVCpu);
2510 AssertRC(rc);
2511 Log2(("REMR3State: trap=%02x errcd=%RGv cr2=%RGv nexteip=%RGv%s\n", pVM->rem.s.Env.exception_index, (RTGCPTR)pVM->rem.s.Env.error_code,
2512 (RTGCPTR)pVM->rem.s.Env.cr[2], (RTGCPTR)pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
2513 }
2514
2515 /*
2516 * Clear old interrupt request flags; Check for pending hardware interrupts.
2517 * (See @remark for why we don't check for other FFs.)
2518 */
2519 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
2520#ifdef VBOX_WITH_NEW_APIC
2521 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2522 APICUpdatePendingInterrupts(pVCpu);
2523#endif
2524 if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
2525 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2526 {
2527 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
2528 }
2529
2530 /*
2531 * We're now in REM mode.
2532 */
2533 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_REM);
2534 pVM->rem.s.fInREM = true;
2535 pVM->rem.s.fInStateSync = false;
2536 pVM->rem.s.cCanExecuteRaw = 0;
2537 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
2538 Log2(("REMR3State: returns VINF_SUCCESS\n"));
2539 return VINF_SUCCESS;
2540}
2541
2542
2543/**
2544 * Syncs back changes in the REM state to the the VM state.
2545 *
2546 * This must be called after invoking REMR3Run().
2547 * Calling it several times in a row is not permitted.
2548 *
2549 * @returns VBox status code.
2550 *
2551 * @param pVM VM Handle.
2552 * @param pVCpu VMCPU Handle.
2553 */
2554REMR3DECL(int) REMR3StateBack(PVM pVM, PVMCPU pVCpu)
2555{
2556 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2557 Assert(pCtx);
2558 unsigned i;
2559
2560 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2561 Log2(("REMR3StateBack:\n"));
2562 Assert(pVM->rem.s.fInREM);
2563
2564 /*
2565 * Copy back the registers.
2566 * This is done in the order they are declared in the CPUMCTX structure.
2567 */
2568
2569 /** @todo FOP */
2570 /** @todo FPUIP */
2571 /** @todo CS */
2572 /** @todo FPUDP */
2573 /** @todo DS */
2574
2575 /** @todo check if FPU/XMM was actually used in the recompiler */
2576 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87);
2577//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2578
2579#ifdef TARGET_X86_64
2580 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2581 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2582 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2583 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2584 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2585 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2586 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2587 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2588 pCtx->r8 = pVM->rem.s.Env.regs[8];
2589 pCtx->r9 = pVM->rem.s.Env.regs[9];
2590 pCtx->r10 = pVM->rem.s.Env.regs[10];
2591 pCtx->r11 = pVM->rem.s.Env.regs[11];
2592 pCtx->r12 = pVM->rem.s.Env.regs[12];
2593 pCtx->r13 = pVM->rem.s.Env.regs[13];
2594 pCtx->r14 = pVM->rem.s.Env.regs[14];
2595 pCtx->r15 = pVM->rem.s.Env.regs[15];
2596
2597 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2598
2599#else
2600 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2601 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2602 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2603 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2604 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2605 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2606 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2607
2608 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2609#endif
2610
2611#define SYNC_BACK_SREG(a_sreg, a_SREG) \
2612 do \
2613 { \
2614 pCtx->a_sreg.Sel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2615 if (!pVM->rem.s.Env.segs[R_SS].newselector) \
2616 { \
2617 pCtx->a_sreg.ValidSel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2618 pCtx->a_sreg.fFlags = CPUMSELREG_FLAGS_VALID; \
2619 pCtx->a_sreg.u64Base = pVM->rem.s.Env.segs[R_##a_SREG].base; \
2620 pCtx->a_sreg.u32Limit = pVM->rem.s.Env.segs[R_##a_SREG].limit; \
2621 /* Note! QEmu saves the 2nd dword of the descriptor; we (VT-x/AMD-V) keep only the attributes! */ \
2622 pCtx->a_sreg.Attr.u = (pVM->rem.s.Env.segs[R_##a_SREG].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK; \
2623 } \
2624 else \
2625 { \
2626 pCtx->a_sreg.fFlags = 0; \
2627 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_##a_SREG]); \
2628 } \
2629 } while (0)
2630
2631 SYNC_BACK_SREG(es, ES);
2632 SYNC_BACK_SREG(cs, CS);
2633 SYNC_BACK_SREG(ss, SS);
2634 SYNC_BACK_SREG(ds, DS);
2635 SYNC_BACK_SREG(fs, FS);
2636 SYNC_BACK_SREG(gs, GS);
2637
2638#ifdef TARGET_X86_64
2639 pCtx->rip = pVM->rem.s.Env.eip;
2640 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2641#else
2642 pCtx->eip = pVM->rem.s.Env.eip;
2643 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2644#endif
2645
2646 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2647 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2648 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2649#ifdef VBOX_WITH_RAW_MODE
2650 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2651 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2652#endif
2653 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2654
2655 for (i = 0; i < 8; i++)
2656 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2657
2658 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2659 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base)
2660 {
2661 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base;
2662 STAM_COUNTER_INC(&gStatREMGDTChange);
2663#ifdef VBOX_WITH_RAW_MODE
2664 if (!HMIsEnabled(pVM))
2665 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2666#endif
2667 }
2668
2669 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2670 if (pCtx->idtr.pIdt != pVM->rem.s.Env.idt.base)
2671 {
2672 pCtx->idtr.pIdt = pVM->rem.s.Env.idt.base;
2673 STAM_COUNTER_INC(&gStatREMIDTChange);
2674#ifdef VBOX_WITH_RAW_MODE
2675 if (!HMIsEnabled(pVM))
2676 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2677#endif
2678 }
2679
2680 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2681 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2682 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2683 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2684 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2685 || !(pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2686 )
2687 {
2688 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2689 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2690 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2691 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2692 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2693 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2694 STAM_COUNTER_INC(&gStatREMLDTRChange);
2695#ifdef VBOX_WITH_RAW_MODE
2696 if (!HMIsEnabled(pVM))
2697 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2698#endif
2699 }
2700
2701 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2702 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2703 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2704 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2705 /* Qemu and AMD/Intel have different ideas about the busy flag ... */ /** @todo just fix qemu! */
2706 || pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2707 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
2708 : 0)
2709 || !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
2710 )
2711 {
2712 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2713 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2714 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2715 (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2716 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT : 0));
2717 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2718 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2719 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2720 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2721 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2722 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2723 if (pCtx->tr.Attr.u & ~DESC_INTEL_UNUSABLE)
2724 pCtx->tr.Attr.u |= DESC_TSS_BUSY_MASK >> SEL_FLAGS_SHIFT;
2725 STAM_COUNTER_INC(&gStatREMTRChange);
2726#ifdef VBOX_WITH_RAW_MODE
2727 if (!HMIsEnabled(pVM))
2728 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2729#endif
2730 }
2731
2732 /* Sysenter MSR */
2733 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2734 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2735 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2736
2737 /* System MSRs. */
2738 pCtx->msrEFER = pVM->rem.s.Env.efer;
2739 pCtx->msrSTAR = pVM->rem.s.Env.star;
2740 pCtx->msrPAT = pVM->rem.s.Env.pat;
2741#ifdef TARGET_X86_64
2742 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2743 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2744 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2745 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2746#endif
2747
2748 /* Inhibit interrupt flag. */
2749 if (pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK)
2750 {
2751 Log(("Settings VMCPU_FF_INHIBIT_INTERRUPTS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2752 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
2753 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2754 }
2755 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2756 {
2757 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#2)\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2758 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2759 }
2760
2761 /* Inhibit NMI flag. */
2762 if (pVM->rem.s.Env.hflags2 & HF2_NMI_MASK)
2763 {
2764 Log(("Settings VMCPU_FF_BLOCK_NMIS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2765 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2766 }
2767 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2768 {
2769 Log(("Clearing VMCPU_FF_BLOCK_NMIS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2770 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2771 }
2772
2773 remR3TrapClear(pVM);
2774
2775 /*
2776 * Check for traps.
2777 */
2778 if ( pVM->rem.s.Env.exception_index >= 0
2779 && pVM->rem.s.Env.exception_index < 256)
2780 {
2781 /* This cannot be a hardware-interrupt because exception_index < EXCP_INTERRUPT. */
2782 int rc;
2783
2784 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2785 TRPMEVENT enmType = pVM->rem.s.Env.exception_is_int ? TRPM_SOFTWARE_INT : TRPM_TRAP;
2786 rc = TRPMAssertTrap(pVCpu, pVM->rem.s.Env.exception_index, enmType);
2787 AssertRC(rc);
2788 if (enmType == TRPM_TRAP)
2789 {
2790 switch (pVM->rem.s.Env.exception_index)
2791 {
2792 case X86_XCPT_PF:
2793 TRPMSetFaultAddress(pVCpu, pCtx->cr2);
2794 /* fallthru */
2795 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP:
2796 case X86_XCPT_AC: case X86_XCPT_DF: /* 0 */
2797 TRPMSetErrorCode(pVCpu, pVM->rem.s.Env.error_code);
2798 break;
2799 }
2800 }
2801 }
2802
2803 /*
2804 * We're not longer in REM mode.
2805 */
2806 CPUMR3RemLeave(pVCpu,
2807 HMIsEnabled(pVM)
2808 || ( pVM->rem.s.Env.segs[R_SS].newselector
2809 | pVM->rem.s.Env.segs[R_GS].newselector
2810 | pVM->rem.s.Env.segs[R_FS].newselector
2811 | pVM->rem.s.Env.segs[R_ES].newselector
2812 | pVM->rem.s.Env.segs[R_DS].newselector
2813 | pVM->rem.s.Env.segs[R_CS].newselector) == 0
2814 );
2815 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_REM);
2816 pVM->rem.s.fInREM = false;
2817 pVM->rem.s.pCtx = NULL;
2818 pVM->rem.s.Env.pVCpu = NULL;
2819 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2820 Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2821 return VINF_SUCCESS;
2822}
2823
2824
2825/**
2826 * This is called by the disassembler when it wants to update the cpu state
2827 * before for instance doing a register dump.
2828 */
2829static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu)
2830{
2831 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2832 unsigned i;
2833
2834 Assert(pVM->rem.s.fInREM);
2835
2836 /*
2837 * Copy back the registers.
2838 * This is done in the order they are declared in the CPUMCTX structure.
2839 */
2840
2841 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87;
2842 /** @todo FOP */
2843 /** @todo FPUIP */
2844 /** @todo CS */
2845 /** @todo FPUDP */
2846 /** @todo DS */
2847 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2848 pFpuCtx->MXCSR = 0;
2849 pFpuCtx->MXCSR_MASK = 0;
2850
2851 /** @todo check if FPU/XMM was actually used in the recompiler */
2852 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)pFpuCtx);
2853//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2854
2855#ifdef TARGET_X86_64
2856 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2857 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2858 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2859 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2860 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2861 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2862 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2863 pCtx->r8 = pVM->rem.s.Env.regs[8];
2864 pCtx->r9 = pVM->rem.s.Env.regs[9];
2865 pCtx->r10 = pVM->rem.s.Env.regs[10];
2866 pCtx->r11 = pVM->rem.s.Env.regs[11];
2867 pCtx->r12 = pVM->rem.s.Env.regs[12];
2868 pCtx->r13 = pVM->rem.s.Env.regs[13];
2869 pCtx->r14 = pVM->rem.s.Env.regs[14];
2870 pCtx->r15 = pVM->rem.s.Env.regs[15];
2871
2872 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2873#else
2874 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2875 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2876 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2877 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2878 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2879 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2880 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2881
2882 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2883#endif
2884
2885 SYNC_BACK_SREG(es, ES);
2886 SYNC_BACK_SREG(cs, CS);
2887 SYNC_BACK_SREG(ss, SS);
2888 SYNC_BACK_SREG(ds, DS);
2889 SYNC_BACK_SREG(fs, FS);
2890 SYNC_BACK_SREG(gs, GS);
2891
2892#ifdef TARGET_X86_64
2893 pCtx->rip = pVM->rem.s.Env.eip;
2894 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2895#else
2896 pCtx->eip = pVM->rem.s.Env.eip;
2897 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2898#endif
2899
2900 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2901 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2902 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2903#ifdef VBOX_WITH_RAW_MODE
2904 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2905 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2906#endif
2907 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2908
2909 for (i = 0; i < 8; i++)
2910 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2911
2912 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2913 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base)
2914 {
2915 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
2916 STAM_COUNTER_INC(&gStatREMGDTChange);
2917#ifdef VBOX_WITH_RAW_MODE
2918 if (!HMIsEnabled(pVM))
2919 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2920#endif
2921 }
2922
2923 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2924 if (pCtx->idtr.pIdt != (RTGCPTR)pVM->rem.s.Env.idt.base)
2925 {
2926 pCtx->idtr.pIdt = (RTGCPTR)pVM->rem.s.Env.idt.base;
2927 STAM_COUNTER_INC(&gStatREMIDTChange);
2928#ifdef VBOX_WITH_RAW_MODE
2929 if (!HMIsEnabled(pVM))
2930 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2931#endif
2932 }
2933
2934 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2935 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2936 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2937 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2938 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2939 || !(pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2940 )
2941 {
2942 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2943 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2944 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2945 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2946 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2947 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2948 STAM_COUNTER_INC(&gStatREMLDTRChange);
2949#ifdef VBOX_WITH_RAW_MODE
2950 if (!HMIsEnabled(pVM))
2951 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2952#endif
2953 }
2954
2955 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2956 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2957 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2958 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2959 /* Qemu and AMD/Intel have different ideas about the busy flag ... */
2960 || pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2961 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
2962 : 0)
2963 || !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
2964 )
2965 {
2966 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2967 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2968 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2969 (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2970 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT : 0));
2971 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2972 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2973 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2974 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2975 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2976 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2977 if (pCtx->tr.Attr.u & ~DESC_INTEL_UNUSABLE)
2978 pCtx->tr.Attr.u |= DESC_TSS_BUSY_MASK >> SEL_FLAGS_SHIFT;
2979 STAM_COUNTER_INC(&gStatREMTRChange);
2980#ifdef VBOX_WITH_RAW_MODE
2981 if (!HMIsEnabled(pVM))
2982 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2983#endif
2984 }
2985
2986 /* Sysenter MSR */
2987 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2988 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2989 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2990
2991 /* System MSRs. */
2992 pCtx->msrEFER = pVM->rem.s.Env.efer;
2993 pCtx->msrSTAR = pVM->rem.s.Env.star;
2994 pCtx->msrPAT = pVM->rem.s.Env.pat;
2995#ifdef TARGET_X86_64
2996 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2997 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2998 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2999 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
3000#endif
3001
3002}
3003
3004
3005/**
3006 * Update the VMM state information if we're currently in REM.
3007 *
3008 * This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
3009 * we're currently executing in REM and the VMM state is invalid. This method will of
3010 * course check that we're executing in REM before syncing any data over to the VMM.
3011 *
3012 * @param pVM The VM handle.
3013 * @param pVCpu The VMCPU handle.
3014 */
3015REMR3DECL(void) REMR3StateUpdate(PVM pVM, PVMCPU pVCpu)
3016{
3017 if (pVM->rem.s.fInREM)
3018 remR3StateUpdate(pVM, pVCpu);
3019}
3020
3021
3022#undef LOG_GROUP
3023#define LOG_GROUP LOG_GROUP_REM
3024
3025
3026/**
3027 * Notify the recompiler about Address Gate 20 state change.
3028 *
3029 * This notification is required since A20 gate changes are
3030 * initialized from a device driver and the VM might just as
3031 * well be in REM mode as in RAW mode.
3032 *
3033 * @param pVM VM handle.
3034 * @param pVCpu VMCPU handle.
3035 * @param fEnable True if the gate should be enabled.
3036 * False if the gate should be disabled.
3037 */
3038REMR3DECL(void) REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable)
3039{
3040 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
3041 VM_ASSERT_EMT(pVM);
3042
3043 /** @todo SMP and the A20 gate... */
3044 if (pVM->rem.s.Env.pVCpu == pVCpu)
3045 {
3046 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3047 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
3048 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3049 }
3050}
3051
3052
3053/**
3054 * Replays the handler notification changes
3055 * Called in response to VM_FF_REM_HANDLER_NOTIFY from the RAW execution loop.
3056 *
3057 * @param pVM VM handle.
3058 */
3059REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
3060{
3061 /*
3062 * Replay the flushes.
3063 */
3064 LogFlow(("REMR3ReplayHandlerNotifications:\n"));
3065 VM_ASSERT_EMT(pVM);
3066
3067 /** @todo this isn't ensuring correct replay order. */
3068 if (VM_FF_TEST_AND_CLEAR(pVM, VM_FF_REM_HANDLER_NOTIFY))
3069 {
3070 uint32_t idxNext;
3071 uint32_t idxRevHead;
3072 uint32_t idxHead;
3073#ifdef VBOX_STRICT
3074 int32_t c = 0;
3075#endif
3076
3077 /* Lockless purging of pending notifications. */
3078 idxHead = ASMAtomicXchgU32(&pVM->rem.s.idxPendingList, UINT32_MAX);
3079 if (idxHead == UINT32_MAX)
3080 return;
3081 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3082
3083 /*
3084 * Reverse the list to process it in FIFO order.
3085 */
3086 idxRevHead = UINT32_MAX;
3087 do
3088 {
3089 /* Save the index of the next rec. */
3090 idxNext = pVM->rem.s.aHandlerNotifications[idxHead].idxNext;
3091 Assert(idxNext < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || idxNext == UINT32_MAX);
3092 /* Push the record onto the reversed list. */
3093 pVM->rem.s.aHandlerNotifications[idxHead].idxNext = idxRevHead;
3094 idxRevHead = idxHead;
3095 Assert(++c <= RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3096 /* Advance. */
3097 idxHead = idxNext;
3098 } while (idxHead != UINT32_MAX);
3099
3100 /*
3101 * Loop thru the list, reinserting the record into the free list as they are
3102 * processed to avoid having other EMTs running out of entries while we're flushing.
3103 */
3104 idxHead = idxRevHead;
3105 do
3106 {
3107 PREMHANDLERNOTIFICATION pCur = &pVM->rem.s.aHandlerNotifications[idxHead];
3108 uint32_t idxCur;
3109 Assert(--c >= 0);
3110
3111 switch (pCur->enmKind)
3112 {
3113 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
3114 remR3NotifyHandlerPhysicalRegister(pVM,
3115 pCur->u.PhysicalRegister.enmKind,
3116 pCur->u.PhysicalRegister.GCPhys,
3117 pCur->u.PhysicalRegister.cb,
3118 pCur->u.PhysicalRegister.fHasHCHandler);
3119 break;
3120
3121 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
3122 remR3NotifyHandlerPhysicalDeregister(pVM,
3123 pCur->u.PhysicalDeregister.enmKind,
3124 pCur->u.PhysicalDeregister.GCPhys,
3125 pCur->u.PhysicalDeregister.cb,
3126 pCur->u.PhysicalDeregister.fHasHCHandler,
3127 pCur->u.PhysicalDeregister.fRestoreAsRAM);
3128 break;
3129
3130 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
3131 remR3NotifyHandlerPhysicalModify(pVM,
3132 pCur->u.PhysicalModify.enmKind,
3133 pCur->u.PhysicalModify.GCPhysOld,
3134 pCur->u.PhysicalModify.GCPhysNew,
3135 pCur->u.PhysicalModify.cb,
3136 pCur->u.PhysicalModify.fHasHCHandler,
3137 pCur->u.PhysicalModify.fRestoreAsRAM);
3138 break;
3139
3140 default:
3141 AssertReleaseMsgFailed(("enmKind=%d\n", pCur->enmKind));
3142 break;
3143 }
3144
3145 /*
3146 * Advance idxHead.
3147 */
3148 idxCur = idxHead;
3149 idxHead = pCur->idxNext;
3150 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || (idxHead == UINT32_MAX && c == 0));
3151
3152 /*
3153 * Put the record back into the free list.
3154 */
3155 do
3156 {
3157 idxNext = ASMAtomicUoReadU32(&pVM->rem.s.idxFreeList);
3158 ASMAtomicWriteU32(&pCur->idxNext, idxNext);
3159 ASMCompilerBarrier();
3160 } while (!ASMAtomicCmpXchgU32(&pVM->rem.s.idxFreeList, idxCur, idxNext));
3161 } while (idxHead != UINT32_MAX);
3162
3163#ifdef VBOX_STRICT
3164 if (pVM->cCpus == 1)
3165 {
3166 unsigned c;
3167 /* Check that all records are now on the free list. */
3168 for (c = 0, idxNext = pVM->rem.s.idxFreeList; idxNext != UINT32_MAX;
3169 idxNext = pVM->rem.s.aHandlerNotifications[idxNext].idxNext)
3170 c++;
3171 AssertReleaseMsg(c == RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), ("%#x != %#x, idxFreeList=%#x\n", c, RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), pVM->rem.s.idxFreeList));
3172 }
3173#endif
3174 }
3175}
3176
3177
3178/**
3179 * Notify REM about changed code page.
3180 *
3181 * @returns VBox status code.
3182 * @param pVM VM handle.
3183 * @param pVCpu VMCPU handle.
3184 * @param pvCodePage Code page address
3185 */
3186REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage)
3187{
3188#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
3189 int rc;
3190 RTGCPHYS PhysGC;
3191 uint64_t flags;
3192
3193 VM_ASSERT_EMT(pVM);
3194
3195 /*
3196 * Get the physical page address.
3197 */
3198 rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
3199 if (rc == VINF_SUCCESS)
3200 {
3201 /*
3202 * Sync the required registers and flush the whole page.
3203 * (Easier to do the whole page than notifying it about each physical
3204 * byte that was changed.
3205 */
3206 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
3207 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
3208 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
3209 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
3210
3211 tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
3212 }
3213#endif
3214 return VINF_SUCCESS;
3215}
3216
3217
3218/**
3219 * Notification about a successful MMR3PhysRegister() call.
3220 *
3221 * @param pVM VM handle.
3222 * @param GCPhys The physical address the RAM.
3223 * @param cb Size of the memory.
3224 * @param fFlags Flags of the REM_NOTIFY_PHYS_RAM_FLAGS_* defines.
3225 */
3226REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, unsigned fFlags)
3227{
3228 Log(("REMR3NotifyPhysRamRegister: GCPhys=%RGp cb=%RGp fFlags=%#x\n", GCPhys, cb, fFlags));
3229 VM_ASSERT_EMT(pVM);
3230
3231 /*
3232 * Validate input - we trust the caller.
3233 */
3234 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3235 Assert(cb);
3236 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3237 AssertMsg(fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_RAM || fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2, ("%#x\n", fFlags));
3238
3239 /*
3240 * Base ram? Update GCPhysLastRam.
3241 */
3242 if (fFlags & REM_NOTIFY_PHYS_RAM_FLAGS_RAM)
3243 {
3244 if (GCPhys + (cb - 1) > pVM->rem.s.GCPhysLastRam)
3245 {
3246 AssertReleaseMsg(!pVM->rem.s.fGCPhysLastRamFixed, ("GCPhys=%RGp cb=%RGp\n", GCPhys, cb));
3247 pVM->rem.s.GCPhysLastRam = GCPhys + (cb - 1);
3248 }
3249 }
3250
3251 /*
3252 * Register the ram.
3253 */
3254 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3255
3256 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3257 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys, GCPhys);
3258 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3259
3260 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3261}
3262
3263
3264/**
3265 * Notification about a successful MMR3PhysRomRegister() call.
3266 *
3267 * @param pVM VM handle.
3268 * @param GCPhys The physical address of the ROM.
3269 * @param cb The size of the ROM.
3270 * @param pvCopy Pointer to the ROM copy.
3271 * @param fShadow Whether it's currently writable shadow ROM or normal readonly ROM.
3272 * This function will be called when ever the protection of the
3273 * shadow ROM changes (at reset and end of POST).
3274 */
3275REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)
3276{
3277 Log(("REMR3NotifyPhysRomRegister: GCPhys=%RGp cb=%d fShadow=%RTbool\n", GCPhys, cb, fShadow));
3278 VM_ASSERT_EMT(pVM);
3279
3280 /*
3281 * Validate input - we trust the caller.
3282 */
3283 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3284 Assert(cb);
3285 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3286
3287 /*
3288 * Register the rom.
3289 */
3290 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3291
3292 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3293 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys | (fShadow ? 0 : IO_MEM_ROM), GCPhys);
3294 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3295
3296 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3297}
3298
3299
3300/**
3301 * Notification about a successful memory deregistration or reservation.
3302 *
3303 * @param pVM VM Handle.
3304 * @param GCPhys Start physical address.
3305 * @param cb The size of the range.
3306 */
3307REMR3DECL(void) REMR3NotifyPhysRamDeregister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
3308{
3309 Log(("REMR3NotifyPhysRamDeregister: GCPhys=%RGp cb=%d\n", GCPhys, cb));
3310 VM_ASSERT_EMT(pVM);
3311
3312 /*
3313 * Validate input - we trust the caller.
3314 */
3315 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3316 Assert(cb);
3317 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3318
3319 /*
3320 * Unassigning the memory.
3321 */
3322 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3323
3324 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3325 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3326 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3327
3328 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3329}
3330
3331
3332/**
3333 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
3334 *
3335 * @param pVM VM Handle.
3336 * @param enmKind Kind of access handler.
3337 * @param GCPhys Handler range address.
3338 * @param cb Size of the handler range.
3339 * @param fHasHCHandler Set if the handler has a HC callback function.
3340 *
3341 * @remark MMR3PhysRomRegister assumes that this function will not apply the
3342 * Handler memory type to memory which has no HC handler.
3343 */
3344static void remR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3345 bool fHasHCHandler)
3346{
3347 Log(("REMR3NotifyHandlerPhysicalRegister: enmKind=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%d\n",
3348 enmKind, GCPhys, cb, fHasHCHandler));
3349
3350 VM_ASSERT_EMT(pVM);
3351 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3352 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3353
3354
3355 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3356
3357 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3358 if (enmKind == PGMPHYSHANDLERKIND_MMIO)
3359 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iMMIOMemType, GCPhys);
3360 else if (fHasHCHandler)
3361 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iHandlerMemType, GCPhys);
3362 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3363
3364 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3365}
3366
3367/**
3368 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
3369 *
3370 * @param pVM VM Handle.
3371 * @param enmKind Kind of access handler.
3372 * @param GCPhys Handler range address.
3373 * @param cb Size of the handler range.
3374 * @param fHasHCHandler Set if the handler has a HC callback function.
3375 *
3376 * @remark MMR3PhysRomRegister assumes that this function will not apply the
3377 * Handler memory type to memory which has no HC handler.
3378 */
3379REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3380 bool fHasHCHandler)
3381{
3382 REMR3ReplayHandlerNotifications(pVM);
3383
3384 remR3NotifyHandlerPhysicalRegister(pVM, enmKind, GCPhys, cb, fHasHCHandler);
3385}
3386
3387/**
3388 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3389 *
3390 * @param pVM VM Handle.
3391 * @param enmKind Kind of access handler.
3392 * @param GCPhys Handler range address.
3393 * @param cb Size of the handler range.
3394 * @param fHasHCHandler Set if the handler has a HC callback function.
3395 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3396 */
3397static void remR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3398 bool fHasHCHandler, bool fRestoreAsRAM)
3399{
3400 Log(("REMR3NotifyHandlerPhysicalDeregister: enmKind=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool RAM=%08x\n",
3401 enmKind, GCPhys, cb, fHasHCHandler, fRestoreAsRAM, MMR3PhysGetRamSize(pVM)));
3402 VM_ASSERT_EMT(pVM);
3403
3404
3405 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3406
3407 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3408 /** @todo this isn't right, MMIO can (in theory) be restored as RAM. */
3409 if (enmKind == PGMPHYSHANDLERKIND_MMIO)
3410 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3411 else if (fHasHCHandler)
3412 {
3413 if (!fRestoreAsRAM)
3414 {
3415 Assert(GCPhys > MMR3PhysGetRamSize(pVM));
3416 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3417 }
3418 else
3419 {
3420 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3421 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3422 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys, GCPhys);
3423 }
3424 }
3425 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3426
3427 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3428}
3429
3430/**
3431 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3432 *
3433 * @param pVM VM Handle.
3434 * @param enmKind Kind of access handler.
3435 * @param GCPhys Handler range address.
3436 * @param cb Size of the handler range.
3437 * @param fHasHCHandler Set if the handler has a HC callback function.
3438 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3439 */
3440REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3441{
3442 REMR3ReplayHandlerNotifications(pVM);
3443 remR3NotifyHandlerPhysicalDeregister(pVM, enmKind, GCPhys, cb, fHasHCHandler, fRestoreAsRAM);
3444}
3445
3446
3447/**
3448 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3449 *
3450 * @param pVM VM Handle.
3451 * @param enmKind Kind of access handler.
3452 * @param GCPhysOld Old handler range address.
3453 * @param GCPhysNew New handler range address.
3454 * @param cb Size of the handler range.
3455 * @param fHasHCHandler Set if the handler has a HC callback function.
3456 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3457 */
3458static void remR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3459{
3460 Log(("REMR3NotifyHandlerPhysicalModify: enmKind=%d GCPhysOld=%RGp GCPhysNew=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool\n",
3461 enmKind, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM));
3462 VM_ASSERT_EMT(pVM);
3463 AssertReleaseMsg(enmKind != PGMPHYSHANDLERKIND_MMIO, ("enmKind=%d\n", enmKind));
3464
3465 if (fHasHCHandler)
3466 {
3467 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3468
3469 /*
3470 * Reset the old page.
3471 */
3472 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3473 if (!fRestoreAsRAM)
3474 cpu_register_physical_memory_offset(GCPhysOld, cb, IO_MEM_UNASSIGNED, GCPhysOld);
3475 else
3476 {
3477 /* This is not perfect, but it'll do for PD monitoring... */
3478 Assert(cb == PAGE_SIZE);
3479 Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
3480 cpu_register_physical_memory_offset(GCPhysOld, cb, GCPhysOld, GCPhysOld);
3481 }
3482
3483 /*
3484 * Update the new page.
3485 */
3486 Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
3487 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3488 cpu_register_physical_memory_offset(GCPhysNew, cb, pVM->rem.s.iHandlerMemType, GCPhysNew);
3489 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3490
3491 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3492 }
3493}
3494
3495/**
3496 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3497 *
3498 * @param pVM VM Handle.
3499 * @param enmKind Kind of access handler.
3500 * @param GCPhysOld Old handler range address.
3501 * @param GCPhysNew New handler range address.
3502 * @param cb Size of the handler range.
3503 * @param fHasHCHandler Set if the handler has a HC callback function.
3504 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3505 */
3506REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3507{
3508 REMR3ReplayHandlerNotifications(pVM);
3509
3510 remR3NotifyHandlerPhysicalModify(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM);
3511}
3512
3513/**
3514 * Checks if we're handling access to this page or not.
3515 *
3516 * @returns true if we're trapping access.
3517 * @returns false if we aren't.
3518 * @param pVM The VM handle.
3519 * @param GCPhys The physical address.
3520 *
3521 * @remark This function will only work correctly in VBOX_STRICT builds!
3522 */
3523REMR3DECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
3524{
3525#ifdef VBOX_STRICT
3526 ram_addr_t off;
3527 REMR3ReplayHandlerNotifications(pVM);
3528
3529 off = get_phys_page_offset(GCPhys);
3530 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
3531 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
3532 || (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
3533#else
3534 return false;
3535#endif
3536}
3537
3538
3539/**
3540 * Deals with a rare case in get_phys_addr_code where the code
3541 * is being monitored.
3542 *
3543 * It could also be an MMIO page, in which case we will raise a fatal error.
3544 *
3545 * @returns The physical address corresponding to addr.
3546 * @param env The cpu environment.
3547 * @param addr The virtual address.
3548 * @param pTLBEntry The TLB entry.
3549 * @param IoTlbEntry The I/O TLB entry address.
3550 */
3551target_ulong remR3PhysGetPhysicalAddressCode(CPUX86State *env,
3552 target_ulong addr,
3553 CPUTLBEntry *pTLBEntry,
3554 target_phys_addr_t IoTlbEntry)
3555{
3556 PVM pVM = env->pVM;
3557
3558 if ((IoTlbEntry & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
3559 {
3560 /* If code memory is being monitored, appropriate IOTLB entry will have
3561 handler IO type, and addend will provide real physical address, no
3562 matter if we store VA in TLB or not, as handlers are always passed PA */
3563 target_ulong ret = (IoTlbEntry & TARGET_PAGE_MASK) + addr;
3564 return ret;
3565 }
3566 LogRel(("\nTrying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv! (iHandlerMemType=%#x iMMIOMemType=%#x IOTLB=%RGp)\n"
3567 "*** handlers\n",
3568 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType, (RTGCPHYS)IoTlbEntry));
3569 DBGFR3Info(pVM->pUVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
3570 LogRel(("*** mmio\n"));
3571 DBGFR3Info(pVM->pUVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
3572 LogRel(("*** phys\n"));
3573 DBGFR3Info(pVM->pUVM, "phys", NULL, DBGFR3InfoLogRelHlp());
3574 cpu_abort(env, "Trying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
3575 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
3576 AssertFatalFailed();
3577}
3578
3579/**
3580 * Read guest RAM and ROM.
3581 *
3582 * @param SrcGCPhys The source address (guest physical).
3583 * @param pvDst The destination address.
3584 * @param cb Number of bytes
3585 */
3586void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb)
3587{
3588 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3589 VBOX_CHECK_ADDR(SrcGCPhys);
3590 VBOXSTRICTRC rcStrict = PGMPhysRead(cpu_single_env->pVM, SrcGCPhys, pvDst, cb, PGMACCESSORIGIN_REM);
3591 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3592#ifdef VBOX_DEBUG_PHYS
3593 LogRel(("read(%d): %08x\n", cb, (uint32_t)SrcGCPhys));
3594#endif
3595 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3596}
3597
3598
3599/**
3600 * Read guest RAM and ROM, unsigned 8-bit.
3601 *
3602 * @param SrcGCPhys The source address (guest physical).
3603 */
3604RTCCUINTREG remR3PhysReadU8(RTGCPHYS SrcGCPhys)
3605{
3606 uint8_t val;
3607 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3608 VBOX_CHECK_ADDR(SrcGCPhys);
3609 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3610 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3611#ifdef VBOX_DEBUG_PHYS
3612 LogRel(("readu8: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3613#endif
3614 return val;
3615}
3616
3617
3618/**
3619 * Read guest RAM and ROM, signed 8-bit.
3620 *
3621 * @param SrcGCPhys The source address (guest physical).
3622 */
3623RTCCINTREG remR3PhysReadS8(RTGCPHYS SrcGCPhys)
3624{
3625 int8_t val;
3626 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3627 VBOX_CHECK_ADDR(SrcGCPhys);
3628 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3629 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3630#ifdef VBOX_DEBUG_PHYS
3631 LogRel(("reads8: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3632#endif
3633 return val;
3634}
3635
3636
3637/**
3638 * Read guest RAM and ROM, unsigned 16-bit.
3639 *
3640 * @param SrcGCPhys The source address (guest physical).
3641 */
3642RTCCUINTREG remR3PhysReadU16(RTGCPHYS SrcGCPhys)
3643{
3644 uint16_t val;
3645 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3646 VBOX_CHECK_ADDR(SrcGCPhys);
3647 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3648 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3649#ifdef VBOX_DEBUG_PHYS
3650 LogRel(("readu16: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3651#endif
3652 return val;
3653}
3654
3655
3656/**
3657 * Read guest RAM and ROM, signed 16-bit.
3658 *
3659 * @param SrcGCPhys The source address (guest physical).
3660 */
3661RTCCINTREG remR3PhysReadS16(RTGCPHYS SrcGCPhys)
3662{
3663 int16_t val;
3664 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3665 VBOX_CHECK_ADDR(SrcGCPhys);
3666 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3667 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3668#ifdef VBOX_DEBUG_PHYS
3669 LogRel(("reads16: %x <- %08x\n", (uint16_t)val, (uint32_t)SrcGCPhys));
3670#endif
3671 return val;
3672}
3673
3674
3675/**
3676 * Read guest RAM and ROM, unsigned 32-bit.
3677 *
3678 * @param SrcGCPhys The source address (guest physical).
3679 */
3680RTCCUINTREG remR3PhysReadU32(RTGCPHYS SrcGCPhys)
3681{
3682 uint32_t val;
3683 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3684 VBOX_CHECK_ADDR(SrcGCPhys);
3685 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3686 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3687#ifdef VBOX_DEBUG_PHYS
3688 LogRel(("readu32: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3689#endif
3690 return val;
3691}
3692
3693
3694/**
3695 * Read guest RAM and ROM, signed 32-bit.
3696 *
3697 * @param SrcGCPhys The source address (guest physical).
3698 */
3699RTCCINTREG remR3PhysReadS32(RTGCPHYS SrcGCPhys)
3700{
3701 int32_t val;
3702 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3703 VBOX_CHECK_ADDR(SrcGCPhys);
3704 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3705 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3706#ifdef VBOX_DEBUG_PHYS
3707 LogRel(("reads32: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3708#endif
3709 return val;
3710}
3711
3712
3713/**
3714 * Read guest RAM and ROM, unsigned 64-bit.
3715 *
3716 * @param SrcGCPhys The source address (guest physical).
3717 */
3718uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys)
3719{
3720 uint64_t val;
3721 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3722 VBOX_CHECK_ADDR(SrcGCPhys);
3723 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3724 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3725#ifdef VBOX_DEBUG_PHYS
3726 LogRel(("readu64: %llx <- %08x\n", val, (uint32_t)SrcGCPhys));
3727#endif
3728 return val;
3729}
3730
3731
3732/**
3733 * Read guest RAM and ROM, signed 64-bit.
3734 *
3735 * @param SrcGCPhys The source address (guest physical).
3736 */
3737int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys)
3738{
3739 int64_t val;
3740 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3741 VBOX_CHECK_ADDR(SrcGCPhys);
3742 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3743 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3744#ifdef VBOX_DEBUG_PHYS
3745 LogRel(("reads64: %llx <- %08x\n", val, (uint32_t)SrcGCPhys));
3746#endif
3747 return val;
3748}
3749
3750
3751/**
3752 * Write guest RAM.
3753 *
3754 * @param DstGCPhys The destination address (guest physical).
3755 * @param pvSrc The source address.
3756 * @param cb Number of bytes to write
3757 */
3758void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb)
3759{
3760 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3761 VBOX_CHECK_ADDR(DstGCPhys);
3762 VBOXSTRICTRC rcStrict = PGMPhysWrite(cpu_single_env->pVM, DstGCPhys, pvSrc, cb, PGMACCESSORIGIN_REM);
3763 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3764 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3765#ifdef VBOX_DEBUG_PHYS
3766 LogRel(("write(%d): %08x\n", cb, (uint32_t)DstGCPhys));
3767#endif
3768}
3769
3770
3771/**
3772 * Write guest RAM, unsigned 8-bit.
3773 *
3774 * @param DstGCPhys The destination address (guest physical).
3775 * @param val Value
3776 */
3777void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val)
3778{
3779 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3780 VBOX_CHECK_ADDR(DstGCPhys);
3781 PGMR3PhysWriteU8(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3782 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3783#ifdef VBOX_DEBUG_PHYS
3784 LogRel(("writeu8: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3785#endif
3786}
3787
3788
3789/**
3790 * Write guest RAM, unsigned 8-bit.
3791 *
3792 * @param DstGCPhys The destination address (guest physical).
3793 * @param val Value
3794 */
3795void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val)
3796{
3797 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3798 VBOX_CHECK_ADDR(DstGCPhys);
3799 PGMR3PhysWriteU16(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3800 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3801#ifdef VBOX_DEBUG_PHYS
3802 LogRel(("writeu16: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3803#endif
3804}
3805
3806
3807/**
3808 * Write guest RAM, unsigned 32-bit.
3809 *
3810 * @param DstGCPhys The destination address (guest physical).
3811 * @param val Value
3812 */
3813void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val)
3814{
3815 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3816 VBOX_CHECK_ADDR(DstGCPhys);
3817 PGMR3PhysWriteU32(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3818 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3819#ifdef VBOX_DEBUG_PHYS
3820 LogRel(("writeu32: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3821#endif
3822}
3823
3824
3825/**
3826 * Write guest RAM, unsigned 64-bit.
3827 *
3828 * @param DstGCPhys The destination address (guest physical).
3829 * @param val Value
3830 */
3831void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val)
3832{
3833 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3834 VBOX_CHECK_ADDR(DstGCPhys);
3835 PGMR3PhysWriteU64(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3836 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3837#ifdef VBOX_DEBUG_PHYS
3838 LogRel(("writeu64: %llx -> %08x\n", val, (uint32_t)DstGCPhys));
3839#endif
3840}
3841
3842#undef LOG_GROUP
3843#define LOG_GROUP LOG_GROUP_REM_MMIO
3844
3845/** Read MMIO memory. */
3846static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys)
3847{
3848 CPUX86State *env = (CPUX86State *)pvEnv;
3849 uint32_t u32 = 0;
3850 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 1);
3851 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3852 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", (RTGCPHYS)GCPhys, u32));
3853 return u32;
3854}
3855
3856/** Read MMIO memory. */
3857static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys)
3858{
3859 CPUX86State *env = (CPUX86State *)pvEnv;
3860 uint32_t u32 = 0;
3861 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 2);
3862 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3863 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", (RTGCPHYS)GCPhys, u32));
3864 return u32;
3865}
3866
3867/** Read MMIO memory. */
3868static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys)
3869{
3870 CPUX86State *env = (CPUX86State *)pvEnv;
3871 uint32_t u32 = 0;
3872 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 4);
3873 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3874 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", (RTGCPHYS)GCPhys, u32));
3875 return u32;
3876}
3877
3878/** Write to MMIO memory. */
3879static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3880{
3881 CPUX86State *env = (CPUX86State *)pvEnv;
3882 int rc;
3883 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3884 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 1);
3885 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3886}
3887
3888/** Write to MMIO memory. */
3889static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3890{
3891 CPUX86State *env = (CPUX86State *)pvEnv;
3892 int rc;
3893 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3894 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 2);
3895 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3896}
3897
3898/** Write to MMIO memory. */
3899static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3900{
3901 CPUX86State *env = (CPUX86State *)pvEnv;
3902 int rc;
3903 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3904 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 4);
3905 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3906}
3907
3908
3909#undef LOG_GROUP
3910#define LOG_GROUP LOG_GROUP_REM_HANDLER
3911
3912/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3913
3914static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3915{
3916 uint8_t u8;
3917 Log2(("remR3HandlerReadU8: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3918 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8), PGMACCESSORIGIN_REM);
3919 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3920 return u8;
3921}
3922
3923static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3924{
3925 uint16_t u16;
3926 Log2(("remR3HandlerReadU16: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3927 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16), PGMACCESSORIGIN_REM);
3928 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3929 return u16;
3930}
3931
3932static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3933{
3934 uint32_t u32;
3935 Log2(("remR3HandlerReadU32: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3936 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32), PGMACCESSORIGIN_REM);
3937 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3938 return u32;
3939}
3940
3941static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3942{
3943 Log2(("remR3HandlerWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3944 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t), PGMACCESSORIGIN_REM);
3945 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3946}
3947
3948static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3949{
3950 Log2(("remR3HandlerWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3951 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t), PGMACCESSORIGIN_REM);
3952 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3953}
3954
3955static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3956{
3957 Log2(("remR3HandlerWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3958 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t), PGMACCESSORIGIN_REM);
3959 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3960}
3961
3962/* -+- disassembly -+- */
3963
3964#undef LOG_GROUP
3965#define LOG_GROUP LOG_GROUP_REM_DISAS
3966
3967
3968/**
3969 * Enables or disables singled stepped disassembly.
3970 *
3971 * @returns VBox status code.
3972 * @param pVM VM handle.
3973 * @param fEnable To enable set this flag, to disable clear it.
3974 */
3975static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3976{
3977 LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3978 VM_ASSERT_EMT(pVM);
3979
3980 if (fEnable)
3981 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3982 else
3983 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3984#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
3985 cpu_single_step(&pVM->rem.s.Env, fEnable);
3986#endif
3987 return VINF_SUCCESS;
3988}
3989
3990
3991/**
3992 * Enables or disables singled stepped disassembly.
3993 *
3994 * @returns VBox status code.
3995 * @param pVM VM handle.
3996 * @param fEnable To enable set this flag, to disable clear it.
3997 */
3998REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3999{
4000 int rc;
4001
4002 LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
4003 if (VM_IS_EMT(pVM))
4004 return remR3DisasEnableStepping(pVM, fEnable);
4005
4006 rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
4007 AssertRC(rc);
4008 return rc;
4009}
4010
4011
4012#ifdef VBOX_WITH_DEBUGGER
4013/**
4014 * External Debugger Command: .remstep [on|off|1|0]
4015 */
4016static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM,
4017 PCDBGCVAR paArgs, unsigned cArgs)
4018{
4019 int rc;
4020 PVM pVM = pUVM->pVM;
4021
4022 if (cArgs == 0)
4023 /*
4024 * Print the current status.
4025 */
4026 rc = DBGCCmdHlpPrintf(pCmdHlp, "DisasStepping is %s\n",
4027 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
4028 else
4029 {
4030 /*
4031 * Convert the argument and change the mode.
4032 */
4033 bool fEnable;
4034 rc = DBGCCmdHlpVarToBool(pCmdHlp, &paArgs[0], &fEnable);
4035 if (RT_SUCCESS(rc))
4036 {
4037 rc = REMR3DisasEnableStepping(pVM, fEnable);
4038 if (RT_SUCCESS(rc))
4039 rc = DBGCCmdHlpPrintf(pCmdHlp, "DisasStepping was %s\n", fEnable ? "enabled" : "disabled");
4040 else
4041 rc = DBGCCmdHlpFailRc(pCmdHlp, pCmd, rc, "REMR3DisasEnableStepping");
4042 }
4043 else
4044 rc = DBGCCmdHlpFailRc(pCmdHlp, pCmd, rc, "DBGCCmdHlpVarToBool");
4045 }
4046 return rc;
4047}
4048#endif /* VBOX_WITH_DEBUGGER */
4049
4050
4051/**
4052 * Disassembles one instruction and prints it to the log.
4053 *
4054 * @returns Success indicator.
4055 * @param env Pointer to the recompiler CPU structure.
4056 * @param f32BitCode Indicates that whether or not the code should
4057 * be disassembled as 16 or 32 bit. If -1 the CS
4058 * selector will be inspected.
4059 * @param pszPrefix
4060 */
4061bool remR3DisasInstr(CPUX86State *env, int f32BitCode, char *pszPrefix)
4062{
4063 PVM pVM = env->pVM;
4064 const bool fLog = LogIsEnabled();
4065 const bool fLog2 = LogIs2Enabled();
4066 int rc = VINF_SUCCESS;
4067
4068 /*
4069 * Don't bother if there ain't any log output to do.
4070 */
4071 if (!fLog && !fLog2)
4072 return true;
4073
4074 /*
4075 * Update the state so DBGF reads the correct register values.
4076 */
4077 remR3StateUpdate(pVM, env->pVCpu);
4078
4079 /*
4080 * Log registers if requested.
4081 */
4082 if (fLog2)
4083 DBGFR3_INFO_LOG(pVM, "cpumguest", pszPrefix);
4084
4085 /*
4086 * Disassemble to log.
4087 */
4088 if (fLog)
4089 {
4090 PVMCPU pVCpu = VMMGetCpu(pVM);
4091 char szBuf[256];
4092 szBuf[0] = '\0';
4093 int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM,
4094 pVCpu->idCpu,
4095 0, /* Sel */ 0, /* GCPtr */
4096 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
4097 szBuf,
4098 sizeof(szBuf),
4099 NULL);
4100 if (RT_FAILURE(rc))
4101 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrEx failed with rc=%Rrc\n", rc);
4102 if (pszPrefix && *pszPrefix)
4103 RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
4104 else
4105 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
4106 }
4107
4108 return RT_SUCCESS(rc);
4109}
4110
4111
4112/**
4113 * Disassemble recompiled code.
4114 *
4115 * @param phFileIgnored Ignored, logfile usually.
4116 * @param pvCode Pointer to the code block.
4117 * @param cb Size of the code block.
4118 */
4119void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
4120{
4121 if (LogIs2Enabled())
4122 {
4123 unsigned off = 0;
4124 char szOutput[256];
4125 DISCPUSTATE Cpu;
4126#ifdef RT_ARCH_X86
4127 DISCPUMODE enmCpuMode = DISCPUMODE_32BIT;
4128#else
4129 DISCPUMODE enmCpuMode = DISCPUMODE_64BIT;
4130#endif
4131
4132 RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
4133 while (off < cb)
4134 {
4135 uint32_t cbInstr;
4136 int rc = DISInstrToStr((uint8_t const *)pvCode + off, enmCpuMode,
4137 &Cpu, &cbInstr, szOutput, sizeof(szOutput));
4138 if (RT_SUCCESS(rc))
4139 RTLogPrintf("%s", szOutput);
4140 else
4141 {
4142 RTLogPrintf("disas error %Rrc\n", rc);
4143 cbInstr = 1;
4144 }
4145 off += cbInstr;
4146 }
4147 }
4148}
4149
4150
4151/**
4152 * Disassemble guest code.
4153 *
4154 * @param phFileIgnored Ignored, logfile usually.
4155 * @param uCode The guest address of the code to disassemble. (flat?)
4156 * @param cb Number of bytes to disassemble.
4157 * @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
4158 */
4159void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
4160{
4161 if (LogIs2Enabled())
4162 {
4163 PVM pVM = cpu_single_env->pVM;
4164 PVMCPU pVCpu = cpu_single_env->pVCpu;
4165 RTSEL cs;
4166 RTGCUINTPTR eip;
4167
4168 Assert(pVCpu);
4169
4170 /*
4171 * Update the state so DBGF reads the correct register values (flags).
4172 */
4173 remR3StateUpdate(pVM, pVCpu);
4174
4175 /*
4176 * Do the disassembling.
4177 */
4178 RTLogPrintf("Guest Code: PC=%llx %llx bytes fFlags=%d\n", (uint64_t)uCode, (uint64_t)cb, fFlags);
4179 cs = cpu_single_env->segs[R_CS].selector;
4180 eip = uCode - cpu_single_env->segs[R_CS].base;
4181 for (;;)
4182 {
4183 char szBuf[256];
4184 uint32_t cbInstr;
4185 int rc = DBGFR3DisasInstrEx(pVM->pUVM,
4186 pVCpu->idCpu,
4187 cs,
4188 eip,
4189 DBGF_DISAS_FLAGS_DEFAULT_MODE,
4190 szBuf, sizeof(szBuf),
4191 &cbInstr);
4192 if (RT_SUCCESS(rc))
4193 RTLogPrintf("%llx %s\n", (uint64_t)uCode, szBuf);
4194 else
4195 {
4196 RTLogPrintf("%llx %04x:%llx: %s\n", (uint64_t)uCode, cs, (uint64_t)eip, szBuf);
4197 cbInstr = 1;
4198 }
4199
4200 /* next */
4201 if (cb <= cbInstr)
4202 break;
4203 cb -= cbInstr;
4204 uCode += cbInstr;
4205 eip += cbInstr;
4206 }
4207 }
4208}
4209
4210
4211/**
4212 * Looks up a guest symbol.
4213 *
4214 * @returns Pointer to symbol name. This is a static buffer.
4215 * @param orig_addr The address in question.
4216 */
4217const char *lookup_symbol(target_ulong orig_addr)
4218{
4219 PVM pVM = cpu_single_env->pVM;
4220 RTGCINTPTR off = 0;
4221 RTDBGSYMBOL Sym;
4222 DBGFADDRESS Addr;
4223
4224 int rc = DBGFR3AsSymbolByAddr(pVM->pUVM, DBGF_AS_GLOBAL, DBGFR3AddrFromFlat(pVM->pUVM, &Addr, orig_addr),
4225 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL, &off, &Sym, NULL /*phMod*/);
4226 if (RT_SUCCESS(rc))
4227 {
4228 static char szSym[sizeof(Sym.szName) + 48];
4229 if (!off)
4230 RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
4231 else if (off > 0)
4232 RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
4233 else
4234 RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
4235 return szSym;
4236 }
4237 return "<N/A>";
4238}
4239
4240
4241#undef LOG_GROUP
4242#define LOG_GROUP LOG_GROUP_REM
4243
4244
4245/* -+- FF notifications -+- */
4246
4247
4248/**
4249 * Notification about a pending interrupt.
4250 *
4251 * @param pVM VM Handle.
4252 * @param pVCpu VMCPU Handle.
4253 * @param u8Interrupt Interrupt
4254 * @thread The emulation thread.
4255 */
4256REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCpu, uint8_t u8Interrupt)
4257{
4258 Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
4259 pVM->rem.s.u32PendingInterrupt = u8Interrupt;
4260}
4261
4262/**
4263 * Notification about a pending interrupt.
4264 *
4265 * @returns Pending interrupt or REM_NO_PENDING_IRQ
4266 * @param pVM VM Handle.
4267 * @param pVCpu VMCPU Handle.
4268 * @thread The emulation thread.
4269 */
4270REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM, PVMCPU pVCpu)
4271{
4272 return pVM->rem.s.u32PendingInterrupt;
4273}
4274
4275/**
4276 * Notification about the interrupt FF being set.
4277 *
4278 * @param pVM VM Handle.
4279 * @param pVCpu VMCPU Handle.
4280 * @thread The emulation thread.
4281 */
4282REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu)
4283{
4284#ifndef IEM_VERIFICATION_MODE
4285 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
4286 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
4287 if (pVM->rem.s.fInREM)
4288 {
4289 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4290 CPU_INTERRUPT_EXTERNAL_HARD);
4291 }
4292#endif
4293}
4294
4295
4296/**
4297 * Notification about the interrupt FF being set.
4298 *
4299 * @param pVM VM Handle.
4300 * @param pVCpu VMCPU Handle.
4301 * @thread Any.
4302 */
4303REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu)
4304{
4305 LogFlow(("REMR3NotifyInterruptClear:\n"));
4306 if (pVM->rem.s.fInREM)
4307 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
4308}
4309
4310
4311/**
4312 * Notification about pending timer(s).
4313 *
4314 * @param pVM VM Handle.
4315 * @param pVCpuDst The target cpu for this notification.
4316 * TM will not broadcast pending timer events, but use
4317 * a dedicated EMT for them. So, only interrupt REM
4318 * execution if the given CPU is executing in REM.
4319 * @thread Any.
4320 */
4321REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM, PVMCPU pVCpuDst)
4322{
4323#ifndef IEM_VERIFICATION_MODE
4324#ifndef DEBUG_bird
4325 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
4326#endif
4327 if (pVM->rem.s.fInREM)
4328 {
4329 if (pVM->rem.s.Env.pVCpu == pVCpuDst)
4330 {
4331 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: setting\n"));
4332 ASMAtomicOrS32((int32_t volatile *)&pVM->rem.s.Env.interrupt_request,
4333 CPU_INTERRUPT_EXTERNAL_TIMER);
4334 }
4335 else
4336 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: pVCpu:%p != pVCpuDst:%p\n", pVM->rem.s.Env.pVCpu, pVCpuDst));
4337 }
4338 else
4339 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: !fInREM; cpu state=%d\n", VMCPU_GET_STATE(pVCpuDst)));
4340#endif
4341}
4342
4343
4344/**
4345 * Notification about pending DMA transfers.
4346 *
4347 * @param pVM VM Handle.
4348 * @thread Any.
4349 */
4350REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
4351{
4352#ifndef IEM_VERIFICATION_MODE
4353 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
4354 if (pVM->rem.s.fInREM)
4355 {
4356 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4357 CPU_INTERRUPT_EXTERNAL_DMA);
4358 }
4359#endif
4360}
4361
4362
4363/**
4364 * Notification about pending timer(s).
4365 *
4366 * @param pVM VM Handle.
4367 * @thread Any.
4368 */
4369REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
4370{
4371#ifndef IEM_VERIFICATION_MODE
4372 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
4373 if (pVM->rem.s.fInREM)
4374 {
4375 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4376 CPU_INTERRUPT_EXTERNAL_EXIT);
4377 }
4378#endif
4379}
4380
4381
4382/**
4383 * Notification about pending FF set by an external thread.
4384 *
4385 * @param pVM VM handle.
4386 * @thread Any.
4387 */
4388REMR3DECL(void) REMR3NotifyFF(PVM pVM)
4389{
4390#ifndef IEM_VERIFICATION_MODE
4391 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
4392 if (pVM->rem.s.fInREM)
4393 {
4394 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4395 CPU_INTERRUPT_EXTERNAL_EXIT);
4396 }
4397#endif
4398}
4399
4400
4401#ifdef VBOX_WITH_STATISTICS
4402void remR3ProfileStart(int statcode)
4403{
4404 STAMPROFILEADV *pStat;
4405 switch(statcode)
4406 {
4407 case STATS_EMULATE_SINGLE_INSTR:
4408 pStat = &gStatExecuteSingleInstr;
4409 break;
4410 case STATS_QEMU_COMPILATION:
4411 pStat = &gStatCompilationQEmu;
4412 break;
4413 case STATS_QEMU_RUN_EMULATED_CODE:
4414 pStat = &gStatRunCodeQEmu;
4415 break;
4416 case STATS_QEMU_TOTAL:
4417 pStat = &gStatTotalTimeQEmu;
4418 break;
4419 case STATS_QEMU_RUN_TIMERS:
4420 pStat = &gStatTimers;
4421 break;
4422 case STATS_TLB_LOOKUP:
4423 pStat= &gStatTBLookup;
4424 break;
4425 case STATS_IRQ_HANDLING:
4426 pStat= &gStatIRQ;
4427 break;
4428 case STATS_RAW_CHECK:
4429 pStat = &gStatRawCheck;
4430 break;
4431
4432 default:
4433 AssertMsgFailed(("unknown stat %d\n", statcode));
4434 return;
4435 }
4436 STAM_PROFILE_ADV_START(pStat, a);
4437}
4438
4439
4440void remR3ProfileStop(int statcode)
4441{
4442 STAMPROFILEADV *pStat;
4443 switch(statcode)
4444 {
4445 case STATS_EMULATE_SINGLE_INSTR:
4446 pStat = &gStatExecuteSingleInstr;
4447 break;
4448 case STATS_QEMU_COMPILATION:
4449 pStat = &gStatCompilationQEmu;
4450 break;
4451 case STATS_QEMU_RUN_EMULATED_CODE:
4452 pStat = &gStatRunCodeQEmu;
4453 break;
4454 case STATS_QEMU_TOTAL:
4455 pStat = &gStatTotalTimeQEmu;
4456 break;
4457 case STATS_QEMU_RUN_TIMERS:
4458 pStat = &gStatTimers;
4459 break;
4460 case STATS_TLB_LOOKUP:
4461 pStat= &gStatTBLookup;
4462 break;
4463 case STATS_IRQ_HANDLING:
4464 pStat= &gStatIRQ;
4465 break;
4466 case STATS_RAW_CHECK:
4467 pStat = &gStatRawCheck;
4468 break;
4469 default:
4470 AssertMsgFailed(("unknown stat %d\n", statcode));
4471 return;
4472 }
4473 STAM_PROFILE_ADV_STOP(pStat, a);
4474}
4475#endif
4476
4477/**
4478 * Raise an RC, force rem exit.
4479 *
4480 * @param pVM VM handle.
4481 * @param rc The rc.
4482 */
4483void remR3RaiseRC(PVM pVM, int rc)
4484{
4485 Log(("remR3RaiseRC: rc=%Rrc\n", rc));
4486 Assert(pVM->rem.s.fInREM);
4487 VM_ASSERT_EMT(pVM);
4488 pVM->rem.s.rc = rc;
4489 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
4490}
4491
4492
4493/* -+- timers -+- */
4494
4495uint64_t cpu_get_tsc(CPUX86State *env)
4496{
4497 STAM_COUNTER_INC(&gStatCpuGetTSC);
4498 return TMCpuTickGet(env->pVCpu);
4499}
4500
4501
4502/* -+- interrupts -+- */
4503
4504void cpu_set_ferr(CPUX86State *env)
4505{
4506 int rc = PDMIsaSetIrq(env->pVM, 13, 1, 0 /*uTagSrc*/);
4507 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
4508}
4509
4510int cpu_get_pic_interrupt(CPUX86State *env)
4511{
4512 uint8_t u8Interrupt;
4513 int rc;
4514
4515#ifdef VBOX_WITH_NEW_APIC
4516 if (VMCPU_FF_TEST_AND_CLEAR(env->pVCpu, VMCPU_FF_UPDATE_APIC))
4517 APICUpdatePendingInterrupts(env->pVCpu);
4518#endif
4519
4520 /* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
4521 * In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
4522 * with the (a)pic.
4523 */
4524 /* Note! We assume we will go directly to the recompiler to handle the pending interrupt! */
4525 /** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
4526 * if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4527 * remove this kludge. */
4528 if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4529 {
4530 rc = VINF_SUCCESS;
4531 Assert(env->pVM->rem.s.u32PendingInterrupt <= 255);
4532 u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4533 env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4534 }
4535 else
4536 rc = PDMGetInterrupt(env->pVCpu, &u8Interrupt);
4537
4538 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Rrc pc=%04x:%08llx ~flags=%08llx\n",
4539 u8Interrupt, rc, env->segs[R_CS].selector, (uint64_t)env->eip, (uint64_t)env->eflags));
4540 if (RT_SUCCESS(rc))
4541 {
4542 if (VMCPU_FF_IS_PENDING(env->pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
4543 env->interrupt_request |= CPU_INTERRUPT_HARD;
4544 return u8Interrupt;
4545 }
4546 return -1;
4547}
4548
4549
4550/* -+- local apic -+- */
4551
4552#if 0 /* CPUMSetGuestMsr does this now. */
4553void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4554{
4555 int rc = PDMApicSetBase(env->pVM, val);
4556 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Rrc\n", val, rc)); NOREF(rc);
4557}
4558#endif
4559
4560uint64_t cpu_get_apic_base(CPUX86State *env)
4561{
4562 uint64_t u64;
4563 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64);
4564 if (RT_SUCCESS(rcStrict))
4565 {
4566 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4567 return u64;
4568 }
4569 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
4570 return 0;
4571}
4572
4573void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4574{
4575 int rc = PDMApicSetTPR(env->pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4576 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Rrc\n", val, rc)); NOREF(rc);
4577}
4578
4579uint8_t cpu_get_apic_tpr(CPUX86State *env)
4580{
4581 uint8_t u8;
4582 int rc = PDMApicGetTPR(env->pVCpu, &u8, NULL, NULL);
4583 if (RT_SUCCESS(rc))
4584 {
4585 LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4586 return u8 >> 4; /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4587 }
4588 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Rrc)\n", rc));
4589 return 0;
4590}
4591
4592/**
4593 * Read an MSR.
4594 *
4595 * @retval 0 success.
4596 * @retval -1 failure, raise \#GP(0).
4597 * @param env The cpu state.
4598 * @param idMsr The MSR to read.
4599 * @param puValue Where to return the value.
4600 */
4601int cpu_rdmsr(CPUX86State *env, uint32_t idMsr, uint64_t *puValue)
4602{
4603 Assert(env->pVCpu);
4604 return CPUMQueryGuestMsr(env->pVCpu, idMsr, puValue) == VINF_SUCCESS ? 0 : -1;
4605}
4606
4607/**
4608 * Write to an MSR.
4609 *
4610 * @retval 0 success.
4611 * @retval -1 failure, raise \#GP(0).
4612 * @param env The cpu state.
4613 * @param idMsr The MSR to write to.
4614 * @param uValue The value to write.
4615 */
4616int cpu_wrmsr(CPUX86State *env, uint32_t idMsr, uint64_t uValue)
4617{
4618 Assert(env->pVCpu);
4619 return CPUMSetGuestMsr(env->pVCpu, idMsr, uValue) == VINF_SUCCESS ? 0 : -1;
4620}
4621
4622/* -+- I/O Ports -+- */
4623
4624#undef LOG_GROUP
4625#define LOG_GROUP LOG_GROUP_REM_IOPORT
4626
4627void cpu_outb(CPUX86State *env, pio_addr_t addr, uint8_t val)
4628{
4629 int rc;
4630
4631 if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4632 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4633
4634 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 1);
4635 if (RT_LIKELY(rc == VINF_SUCCESS))
4636 return;
4637 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4638 {
4639 Log(("cpu_outb: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4640 remR3RaiseRC(env->pVM, rc);
4641 return;
4642 }
4643 remAbort(rc, __FUNCTION__);
4644}
4645
4646void cpu_outw(CPUX86State *env, pio_addr_t addr, uint16_t val)
4647{
4648 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4649 int rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 2);
4650 if (RT_LIKELY(rc == VINF_SUCCESS))
4651 return;
4652 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4653 {
4654 Log(("cpu_outw: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4655 remR3RaiseRC(env->pVM, rc);
4656 return;
4657 }
4658 remAbort(rc, __FUNCTION__);
4659}
4660
4661void cpu_outl(CPUX86State *env, pio_addr_t addr, uint32_t val)
4662{
4663 int rc;
4664 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4665 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 4);
4666 if (RT_LIKELY(rc == VINF_SUCCESS))
4667 return;
4668 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4669 {
4670 Log(("cpu_outl: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4671 remR3RaiseRC(env->pVM, rc);
4672 return;
4673 }
4674 remAbort(rc, __FUNCTION__);
4675}
4676
4677uint8_t cpu_inb(CPUX86State *env, pio_addr_t addr)
4678{
4679 uint32_t u32 = 0;
4680 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 1);
4681 if (RT_LIKELY(rc == VINF_SUCCESS))
4682 {
4683 if (/*addr != 0x61 && */addr != 0x71)
4684 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4685 return (uint8_t)u32;
4686 }
4687 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4688 {
4689 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4690 remR3RaiseRC(env->pVM, rc);
4691 return (uint8_t)u32;
4692 }
4693 remAbort(rc, __FUNCTION__);
4694 return UINT8_C(0xff);
4695}
4696
4697uint16_t cpu_inw(CPUX86State *env, pio_addr_t addr)
4698{
4699 uint32_t u32 = 0;
4700 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 2);
4701 if (RT_LIKELY(rc == VINF_SUCCESS))
4702 {
4703 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4704 return (uint16_t)u32;
4705 }
4706 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4707 {
4708 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4709 remR3RaiseRC(env->pVM, rc);
4710 return (uint16_t)u32;
4711 }
4712 remAbort(rc, __FUNCTION__);
4713 return UINT16_C(0xffff);
4714}
4715
4716uint32_t cpu_inl(CPUX86State *env, pio_addr_t addr)
4717{
4718 uint32_t u32 = 0;
4719 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 4);
4720 if (RT_LIKELY(rc == VINF_SUCCESS))
4721 {
4722 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4723 return u32;
4724 }
4725 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4726 {
4727 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4728 remR3RaiseRC(env->pVM, rc);
4729 return u32;
4730 }
4731 remAbort(rc, __FUNCTION__);
4732 return UINT32_C(0xffffffff);
4733}
4734
4735#undef LOG_GROUP
4736#define LOG_GROUP LOG_GROUP_REM
4737
4738
4739/* -+- helpers and misc other interfaces -+- */
4740
4741/**
4742 * Perform the CPUID instruction.
4743 *
4744 * @param env Pointer to the recompiler CPU structure.
4745 * @param idx The CPUID leaf (eax).
4746 * @param idxSub The CPUID sub-leaf (ecx) where applicable.
4747 * @param pEAX Where to store eax.
4748 * @param pEBX Where to store ebx.
4749 * @param pECX Where to store ecx.
4750 * @param pEDX Where to store edx.
4751 */
4752void cpu_x86_cpuid(CPUX86State *env, uint32_t idx, uint32_t idxSub,
4753 uint32_t *pEAX, uint32_t *pEBX, uint32_t *pECX, uint32_t *pEDX)
4754{
4755 NOREF(idxSub);
4756 CPUMGetGuestCpuId(env->pVCpu, idx, idxSub, pEAX, pEBX, pECX, pEDX);
4757}
4758
4759
4760#if 0 /* not used */
4761/**
4762 * Interface for qemu hardware to report back fatal errors.
4763 */
4764void hw_error(const char *pszFormat, ...)
4765{
4766 /*
4767 * Bitch about it.
4768 */
4769 /** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4770 * this in my Odin32 tree at home! */
4771 va_list args;
4772 va_start(args, pszFormat);
4773 RTLogPrintf("fatal error in virtual hardware:");
4774 RTLogPrintfV(pszFormat, args);
4775 va_end(args);
4776 AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4777
4778 /*
4779 * If we're in REM context we'll sync back the state before 'jumping' to
4780 * the EMs failure handling.
4781 */
4782 PVM pVM = cpu_single_env->pVM;
4783 if (pVM->rem.s.fInREM)
4784 REMR3StateBack(pVM);
4785 EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4786 AssertMsgFailed(("EMR3FatalError returned!\n"));
4787}
4788#endif
4789
4790/**
4791 * Interface for the qemu cpu to report unhandled situation
4792 * raising a fatal VM error.
4793 */
4794void cpu_abort(CPUX86State *env, const char *pszFormat, ...)
4795{
4796 va_list va;
4797 PVM pVM;
4798 PVMCPU pVCpu;
4799 char szMsg[256];
4800
4801 /*
4802 * Bitch about it.
4803 */
4804 RTLogFlags(NULL, "nodisabled nobuffered");
4805 RTLogFlush(NULL);
4806
4807 va_start(va, pszFormat);
4808#if defined(RT_OS_WINDOWS) && ARCH_BITS == 64
4809 /* It's a bit complicated when mixing MSC and GCC on AMD64. This is a bit ugly, but it works. */
4810 unsigned cArgs = 0;
4811 uintptr_t auArgs[6] = {0,0,0,0,0,0};
4812 const char *psz = strchr(pszFormat, '%');
4813 while (psz && cArgs < 6)
4814 {
4815 auArgs[cArgs++] = va_arg(va, uintptr_t);
4816 psz = strchr(psz + 1, '%');
4817 }
4818 switch (cArgs)
4819 {
4820 case 1: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0]); break;
4821 case 2: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1]); break;
4822 case 3: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2]); break;
4823 case 4: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3]); break;
4824 case 5: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3], auArgs[4]); break;
4825 case 6: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3], auArgs[4], auArgs[5]); break;
4826 default:
4827 case 0: RTStrPrintf(szMsg, sizeof(szMsg), "%s", pszFormat); break;
4828 }
4829#else
4830 RTStrPrintfV(szMsg, sizeof(szMsg), pszFormat, va);
4831#endif
4832 va_end(va);
4833
4834 RTLogPrintf("fatal error in recompiler cpu: %s\n", szMsg);
4835 RTLogRelPrintf("fatal error in recompiler cpu: %s\n", szMsg);
4836
4837 /*
4838 * If we're in REM context we'll sync back the state before 'jumping' to
4839 * the EMs failure handling.
4840 */
4841 pVM = cpu_single_env->pVM;
4842 pVCpu = cpu_single_env->pVCpu;
4843 Assert(pVCpu);
4844
4845 if (pVM->rem.s.fInREM)
4846 REMR3StateBack(pVM, pVCpu);
4847 EMR3FatalError(pVCpu, VERR_REM_VIRTUAL_CPU_ERROR);
4848 AssertMsgFailed(("EMR3FatalError returned!\n"));
4849}
4850
4851
4852/**
4853 * Aborts the VM.
4854 *
4855 * @param rc VBox error code.
4856 * @param pszTip Hint about why/when this happened.
4857 */
4858void remAbort(int rc, const char *pszTip)
4859{
4860 PVM pVM;
4861 PVMCPU pVCpu;
4862
4863 /*
4864 * Bitch about it.
4865 */
4866 RTLogPrintf("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip);
4867 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip));
4868
4869 /*
4870 * Jump back to where we entered the recompiler.
4871 */
4872 pVM = cpu_single_env->pVM;
4873 pVCpu = cpu_single_env->pVCpu;
4874 Assert(pVCpu);
4875
4876 if (pVM->rem.s.fInREM)
4877 REMR3StateBack(pVM, pVCpu);
4878
4879 EMR3FatalError(pVCpu, rc);
4880 AssertMsgFailed(("EMR3FatalError returned!\n"));
4881}
4882
4883
4884/**
4885 * Dumps a linux system call.
4886 * @param pVCpu VMCPU handle.
4887 */
4888void remR3DumpLnxSyscall(PVMCPU pVCpu)
4889{
4890 static const char *apsz[] =
4891 {
4892 "sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4893 "sys_exit",
4894 "sys_fork",
4895 "sys_read",
4896 "sys_write",
4897 "sys_open", /* 5 */
4898 "sys_close",
4899 "sys_waitpid",
4900 "sys_creat",
4901 "sys_link",
4902 "sys_unlink", /* 10 */
4903 "sys_execve",
4904 "sys_chdir",
4905 "sys_time",
4906 "sys_mknod",
4907 "sys_chmod", /* 15 */
4908 "sys_lchown16",
4909 "sys_ni_syscall", /* old break syscall holder */
4910 "sys_stat",
4911 "sys_lseek",
4912 "sys_getpid", /* 20 */
4913 "sys_mount",
4914 "sys_oldumount",
4915 "sys_setuid16",
4916 "sys_getuid16",
4917 "sys_stime", /* 25 */
4918 "sys_ptrace",
4919 "sys_alarm",
4920 "sys_fstat",
4921 "sys_pause",
4922 "sys_utime", /* 30 */
4923 "sys_ni_syscall", /* old stty syscall holder */
4924 "sys_ni_syscall", /* old gtty syscall holder */
4925 "sys_access",
4926 "sys_nice",
4927 "sys_ni_syscall", /* 35 - old ftime syscall holder */
4928 "sys_sync",
4929 "sys_kill",
4930 "sys_rename",
4931 "sys_mkdir",
4932 "sys_rmdir", /* 40 */
4933 "sys_dup",
4934 "sys_pipe",
4935 "sys_times",
4936 "sys_ni_syscall", /* old prof syscall holder */
4937 "sys_brk", /* 45 */
4938 "sys_setgid16",
4939 "sys_getgid16",
4940 "sys_signal",
4941 "sys_geteuid16",
4942 "sys_getegid16", /* 50 */
4943 "sys_acct",
4944 "sys_umount", /* recycled never used phys() */
4945 "sys_ni_syscall", /* old lock syscall holder */
4946 "sys_ioctl",
4947 "sys_fcntl", /* 55 */
4948 "sys_ni_syscall", /* old mpx syscall holder */
4949 "sys_setpgid",
4950 "sys_ni_syscall", /* old ulimit syscall holder */
4951 "sys_olduname",
4952 "sys_umask", /* 60 */
4953 "sys_chroot",
4954 "sys_ustat",
4955 "sys_dup2",
4956 "sys_getppid",
4957 "sys_getpgrp", /* 65 */
4958 "sys_setsid",
4959 "sys_sigaction",
4960 "sys_sgetmask",
4961 "sys_ssetmask",
4962 "sys_setreuid16", /* 70 */
4963 "sys_setregid16",
4964 "sys_sigsuspend",
4965 "sys_sigpending",
4966 "sys_sethostname",
4967 "sys_setrlimit", /* 75 */
4968 "sys_old_getrlimit",
4969 "sys_getrusage",
4970 "sys_gettimeofday",
4971 "sys_settimeofday",
4972 "sys_getgroups16", /* 80 */
4973 "sys_setgroups16",
4974 "old_select",
4975 "sys_symlink",
4976 "sys_lstat",
4977 "sys_readlink", /* 85 */
4978 "sys_uselib",
4979 "sys_swapon",
4980 "sys_reboot",
4981 "old_readdir",
4982 "old_mmap", /* 90 */
4983 "sys_munmap",
4984 "sys_truncate",
4985 "sys_ftruncate",
4986 "sys_fchmod",
4987 "sys_fchown16", /* 95 */
4988 "sys_getpriority",
4989 "sys_setpriority",
4990 "sys_ni_syscall", /* old profil syscall holder */
4991 "sys_statfs",
4992 "sys_fstatfs", /* 100 */
4993 "sys_ioperm",
4994 "sys_socketcall",
4995 "sys_syslog",
4996 "sys_setitimer",
4997 "sys_getitimer", /* 105 */
4998 "sys_newstat",
4999 "sys_newlstat",
5000 "sys_newfstat",
5001 "sys_uname",
5002 "sys_iopl", /* 110 */
5003 "sys_vhangup",
5004 "sys_ni_syscall", /* old "idle" system call */
5005 "sys_vm86old",
5006 "sys_wait4",
5007 "sys_swapoff", /* 115 */
5008 "sys_sysinfo",
5009 "sys_ipc",
5010 "sys_fsync",
5011 "sys_sigreturn",
5012 "sys_clone", /* 120 */
5013 "sys_setdomainname",
5014 "sys_newuname",
5015 "sys_modify_ldt",
5016 "sys_adjtimex",
5017 "sys_mprotect", /* 125 */
5018 "sys_sigprocmask",
5019 "sys_ni_syscall", /* old "create_module" */
5020 "sys_init_module",
5021 "sys_delete_module",
5022 "sys_ni_syscall", /* 130: old "get_kernel_syms" */
5023 "sys_quotactl",
5024 "sys_getpgid",
5025 "sys_fchdir",
5026 "sys_bdflush",
5027 "sys_sysfs", /* 135 */
5028 "sys_personality",
5029 "sys_ni_syscall", /* reserved for afs_syscall */
5030 "sys_setfsuid16",
5031 "sys_setfsgid16",
5032 "sys_llseek", /* 140 */
5033 "sys_getdents",
5034 "sys_select",
5035 "sys_flock",
5036 "sys_msync",
5037 "sys_readv", /* 145 */
5038 "sys_writev",
5039 "sys_getsid",
5040 "sys_fdatasync",
5041 "sys_sysctl",
5042 "sys_mlock", /* 150 */
5043 "sys_munlock",
5044 "sys_mlockall",
5045 "sys_munlockall",
5046 "sys_sched_setparam",
5047 "sys_sched_getparam", /* 155 */
5048 "sys_sched_setscheduler",
5049 "sys_sched_getscheduler",
5050 "sys_sched_yield",
5051 "sys_sched_get_priority_max",
5052 "sys_sched_get_priority_min", /* 160 */
5053 "sys_sched_rr_get_interval",
5054 "sys_nanosleep",
5055 "sys_mremap",
5056 "sys_setresuid16",
5057 "sys_getresuid16", /* 165 */
5058 "sys_vm86",
5059 "sys_ni_syscall", /* Old sys_query_module */
5060 "sys_poll",
5061 "sys_nfsservctl",
5062 "sys_setresgid16", /* 170 */
5063 "sys_getresgid16",
5064 "sys_prctl",
5065 "sys_rt_sigreturn",
5066 "sys_rt_sigaction",
5067 "sys_rt_sigprocmask", /* 175 */
5068 "sys_rt_sigpending",
5069 "sys_rt_sigtimedwait",
5070 "sys_rt_sigqueueinfo",
5071 "sys_rt_sigsuspend",
5072 "sys_pread64", /* 180 */
5073 "sys_pwrite64",
5074 "sys_chown16",
5075 "sys_getcwd",
5076 "sys_capget",
5077 "sys_capset", /* 185 */
5078 "sys_sigaltstack",
5079 "sys_sendfile",
5080 "sys_ni_syscall", /* reserved for streams1 */
5081 "sys_ni_syscall", /* reserved for streams2 */
5082 "sys_vfork", /* 190 */
5083 "sys_getrlimit",
5084 "sys_mmap2",
5085 "sys_truncate64",
5086 "sys_ftruncate64",
5087 "sys_stat64", /* 195 */
5088 "sys_lstat64",
5089 "sys_fstat64",
5090 "sys_lchown",
5091 "sys_getuid",
5092 "sys_getgid", /* 200 */
5093 "sys_geteuid",
5094 "sys_getegid",
5095 "sys_setreuid",
5096 "sys_setregid",
5097 "sys_getgroups", /* 205 */
5098 "sys_setgroups",
5099 "sys_fchown",
5100 "sys_setresuid",
5101 "sys_getresuid",
5102 "sys_setresgid", /* 210 */
5103 "sys_getresgid",
5104 "sys_chown",
5105 "sys_setuid",
5106 "sys_setgid",
5107 "sys_setfsuid", /* 215 */
5108 "sys_setfsgid",
5109 "sys_pivot_root",
5110 "sys_mincore",
5111 "sys_madvise",
5112 "sys_getdents64", /* 220 */
5113 "sys_fcntl64",
5114 "sys_ni_syscall", /* reserved for TUX */
5115 "sys_ni_syscall",
5116 "sys_gettid",
5117 "sys_readahead", /* 225 */
5118 "sys_setxattr",
5119 "sys_lsetxattr",
5120 "sys_fsetxattr",
5121 "sys_getxattr",
5122 "sys_lgetxattr", /* 230 */
5123 "sys_fgetxattr",
5124 "sys_listxattr",
5125 "sys_llistxattr",
5126 "sys_flistxattr",
5127 "sys_removexattr", /* 235 */
5128 "sys_lremovexattr",
5129 "sys_fremovexattr",
5130 "sys_tkill",
5131 "sys_sendfile64",
5132 "sys_futex", /* 240 */
5133 "sys_sched_setaffinity",
5134 "sys_sched_getaffinity",
5135 "sys_set_thread_area",
5136 "sys_get_thread_area",
5137 "sys_io_setup", /* 245 */
5138 "sys_io_destroy",
5139 "sys_io_getevents",
5140 "sys_io_submit",
5141 "sys_io_cancel",
5142 "sys_fadvise64", /* 250 */
5143 "sys_ni_syscall",
5144 "sys_exit_group",
5145 "sys_lookup_dcookie",
5146 "sys_epoll_create",
5147 "sys_epoll_ctl", /* 255 */
5148 "sys_epoll_wait",
5149 "sys_remap_file_pages",
5150 "sys_set_tid_address",
5151 "sys_timer_create",
5152 "sys_timer_settime", /* 260 */
5153 "sys_timer_gettime",
5154 "sys_timer_getoverrun",
5155 "sys_timer_delete",
5156 "sys_clock_settime",
5157 "sys_clock_gettime", /* 265 */
5158 "sys_clock_getres",
5159 "sys_clock_nanosleep",
5160 "sys_statfs64",
5161 "sys_fstatfs64",
5162 "sys_tgkill", /* 270 */
5163 "sys_utimes",
5164 "sys_fadvise64_64",
5165 "sys_ni_syscall" /* sys_vserver */
5166 };
5167
5168 uint32_t uEAX = CPUMGetGuestEAX(pVCpu);
5169 switch (uEAX)
5170 {
5171 default:
5172 if (uEAX < RT_ELEMENTS(apsz))
5173 Log(("REM: linux syscall %3d: %s (eip=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
5174 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), CPUMGetGuestEBX(pVCpu), CPUMGetGuestECX(pVCpu),
5175 CPUMGetGuestEDX(pVCpu), CPUMGetGuestESI(pVCpu), CPUMGetGuestEDI(pVCpu), CPUMGetGuestEBP(pVCpu)));
5176 else
5177 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX));
5178 break;
5179
5180 }
5181}
5182
5183
5184/**
5185 * Dumps an OpenBSD system call.
5186 * @param pVCpu VMCPU handle.
5187 */
5188void remR3DumpOBsdSyscall(PVMCPU pVCpu)
5189{
5190 static const char *apsz[] =
5191 {
5192 "SYS_syscall", //0
5193 "SYS_exit", //1
5194 "SYS_fork", //2
5195 "SYS_read", //3
5196 "SYS_write", //4
5197 "SYS_open", //5
5198 "SYS_close", //6
5199 "SYS_wait4", //7
5200 "SYS_8",
5201 "SYS_link", //9
5202 "SYS_unlink", //10
5203 "SYS_11",
5204 "SYS_chdir", //12
5205 "SYS_fchdir", //13
5206 "SYS_mknod", //14
5207 "SYS_chmod", //15
5208 "SYS_chown", //16
5209 "SYS_break", //17
5210 "SYS_18",
5211 "SYS_19",
5212 "SYS_getpid", //20
5213 "SYS_mount", //21
5214 "SYS_unmount", //22
5215 "SYS_setuid", //23
5216 "SYS_getuid", //24
5217 "SYS_geteuid", //25
5218 "SYS_ptrace", //26
5219 "SYS_recvmsg", //27
5220 "SYS_sendmsg", //28
5221 "SYS_recvfrom", //29
5222 "SYS_accept", //30
5223 "SYS_getpeername", //31
5224 "SYS_getsockname", //32
5225 "SYS_access", //33
5226 "SYS_chflags", //34
5227 "SYS_fchflags", //35
5228 "SYS_sync", //36
5229 "SYS_kill", //37
5230 "SYS_38",
5231 "SYS_getppid", //39
5232 "SYS_40",
5233 "SYS_dup", //41
5234 "SYS_opipe", //42
5235 "SYS_getegid", //43
5236 "SYS_profil", //44
5237 "SYS_ktrace", //45
5238 "SYS_sigaction", //46
5239 "SYS_getgid", //47
5240 "SYS_sigprocmask", //48
5241 "SYS_getlogin", //49
5242 "SYS_setlogin", //50
5243 "SYS_acct", //51
5244 "SYS_sigpending", //52
5245 "SYS_osigaltstack", //53
5246 "SYS_ioctl", //54
5247 "SYS_reboot", //55
5248 "SYS_revoke", //56
5249 "SYS_symlink", //57
5250 "SYS_readlink", //58
5251 "SYS_execve", //59
5252 "SYS_umask", //60
5253 "SYS_chroot", //61
5254 "SYS_62",
5255 "SYS_63",
5256 "SYS_64",
5257 "SYS_65",
5258 "SYS_vfork", //66
5259 "SYS_67",
5260 "SYS_68",
5261 "SYS_sbrk", //69
5262 "SYS_sstk", //70
5263 "SYS_61",
5264 "SYS_vadvise", //72
5265 "SYS_munmap", //73
5266 "SYS_mprotect", //74
5267 "SYS_madvise", //75
5268 "SYS_76",
5269 "SYS_77",
5270 "SYS_mincore", //78
5271 "SYS_getgroups", //79
5272 "SYS_setgroups", //80
5273 "SYS_getpgrp", //81
5274 "SYS_setpgid", //82
5275 "SYS_setitimer", //83
5276 "SYS_84",
5277 "SYS_85",
5278 "SYS_getitimer", //86
5279 "SYS_87",
5280 "SYS_88",
5281 "SYS_89",
5282 "SYS_dup2", //90
5283 "SYS_91",
5284 "SYS_fcntl", //92
5285 "SYS_select", //93
5286 "SYS_94",
5287 "SYS_fsync", //95
5288 "SYS_setpriority", //96
5289 "SYS_socket", //97
5290 "SYS_connect", //98
5291 "SYS_99",
5292 "SYS_getpriority", //100
5293 "SYS_101",
5294 "SYS_102",
5295 "SYS_sigreturn", //103
5296 "SYS_bind", //104
5297 "SYS_setsockopt", //105
5298 "SYS_listen", //106
5299 "SYS_107",
5300 "SYS_108",
5301 "SYS_109",
5302 "SYS_110",
5303 "SYS_sigsuspend", //111
5304 "SYS_112",
5305 "SYS_113",
5306 "SYS_114",
5307 "SYS_115",
5308 "SYS_gettimeofday", //116
5309 "SYS_getrusage", //117
5310 "SYS_getsockopt", //118
5311 "SYS_119",
5312 "SYS_readv", //120
5313 "SYS_writev", //121
5314 "SYS_settimeofday", //122
5315 "SYS_fchown", //123
5316 "SYS_fchmod", //124
5317 "SYS_125",
5318 "SYS_setreuid", //126
5319 "SYS_setregid", //127
5320 "SYS_rename", //128
5321 "SYS_129",
5322 "SYS_130",
5323 "SYS_flock", //131
5324 "SYS_mkfifo", //132
5325 "SYS_sendto", //133
5326 "SYS_shutdown", //134
5327 "SYS_socketpair", //135
5328 "SYS_mkdir", //136
5329 "SYS_rmdir", //137
5330 "SYS_utimes", //138
5331 "SYS_139",
5332 "SYS_adjtime", //140
5333 "SYS_141",
5334 "SYS_142",
5335 "SYS_143",
5336 "SYS_144",
5337 "SYS_145",
5338 "SYS_146",
5339 "SYS_setsid", //147
5340 "SYS_quotactl", //148
5341 "SYS_149",
5342 "SYS_150",
5343 "SYS_151",
5344 "SYS_152",
5345 "SYS_153",
5346 "SYS_154",
5347 "SYS_nfssvc", //155
5348 "SYS_156",
5349 "SYS_157",
5350 "SYS_158",
5351 "SYS_159",
5352 "SYS_160",
5353 "SYS_getfh", //161
5354 "SYS_162",
5355 "SYS_163",
5356 "SYS_164",
5357 "SYS_sysarch", //165
5358 "SYS_166",
5359 "SYS_167",
5360 "SYS_168",
5361 "SYS_169",
5362 "SYS_170",
5363 "SYS_171",
5364 "SYS_172",
5365 "SYS_pread", //173
5366 "SYS_pwrite", //174
5367 "SYS_175",
5368 "SYS_176",
5369 "SYS_177",
5370 "SYS_178",
5371 "SYS_179",
5372 "SYS_180",
5373 "SYS_setgid", //181
5374 "SYS_setegid", //182
5375 "SYS_seteuid", //183
5376 "SYS_lfs_bmapv", //184
5377 "SYS_lfs_markv", //185
5378 "SYS_lfs_segclean", //186
5379 "SYS_lfs_segwait", //187
5380 "SYS_188",
5381 "SYS_189",
5382 "SYS_190",
5383 "SYS_pathconf", //191
5384 "SYS_fpathconf", //192
5385 "SYS_swapctl", //193
5386 "SYS_getrlimit", //194
5387 "SYS_setrlimit", //195
5388 "SYS_getdirentries", //196
5389 "SYS_mmap", //197
5390 "SYS___syscall", //198
5391 "SYS_lseek", //199
5392 "SYS_truncate", //200
5393 "SYS_ftruncate", //201
5394 "SYS___sysctl", //202
5395 "SYS_mlock", //203
5396 "SYS_munlock", //204
5397 "SYS_205",
5398 "SYS_futimes", //206
5399 "SYS_getpgid", //207
5400 "SYS_xfspioctl", //208
5401 "SYS_209",
5402 "SYS_210",
5403 "SYS_211",
5404 "SYS_212",
5405 "SYS_213",
5406 "SYS_214",
5407 "SYS_215",
5408 "SYS_216",
5409 "SYS_217",
5410 "SYS_218",
5411 "SYS_219",
5412 "SYS_220",
5413 "SYS_semget", //221
5414 "SYS_222",
5415 "SYS_223",
5416 "SYS_224",
5417 "SYS_msgget", //225
5418 "SYS_msgsnd", //226
5419 "SYS_msgrcv", //227
5420 "SYS_shmat", //228
5421 "SYS_229",
5422 "SYS_shmdt", //230
5423 "SYS_231",
5424 "SYS_clock_gettime", //232
5425 "SYS_clock_settime", //233
5426 "SYS_clock_getres", //234
5427 "SYS_235",
5428 "SYS_236",
5429 "SYS_237",
5430 "SYS_238",
5431 "SYS_239",
5432 "SYS_nanosleep", //240
5433 "SYS_241",
5434 "SYS_242",
5435 "SYS_243",
5436 "SYS_244",
5437 "SYS_245",
5438 "SYS_246",
5439 "SYS_247",
5440 "SYS_248",
5441 "SYS_249",
5442 "SYS_minherit", //250
5443 "SYS_rfork", //251
5444 "SYS_poll", //252
5445 "SYS_issetugid", //253
5446 "SYS_lchown", //254
5447 "SYS_getsid", //255
5448 "SYS_msync", //256
5449 "SYS_257",
5450 "SYS_258",
5451 "SYS_259",
5452 "SYS_getfsstat", //260
5453 "SYS_statfs", //261
5454 "SYS_fstatfs", //262
5455 "SYS_pipe", //263
5456 "SYS_fhopen", //264
5457 "SYS_265",
5458 "SYS_fhstatfs", //266
5459 "SYS_preadv", //267
5460 "SYS_pwritev", //268
5461 "SYS_kqueue", //269
5462 "SYS_kevent", //270
5463 "SYS_mlockall", //271
5464 "SYS_munlockall", //272
5465 "SYS_getpeereid", //273
5466 "SYS_274",
5467 "SYS_275",
5468 "SYS_276",
5469 "SYS_277",
5470 "SYS_278",
5471 "SYS_279",
5472 "SYS_280",
5473 "SYS_getresuid", //281
5474 "SYS_setresuid", //282
5475 "SYS_getresgid", //283
5476 "SYS_setresgid", //284
5477 "SYS_285",
5478 "SYS_mquery", //286
5479 "SYS_closefrom", //287
5480 "SYS_sigaltstack", //288
5481 "SYS_shmget", //289
5482 "SYS_semop", //290
5483 "SYS_stat", //291
5484 "SYS_fstat", //292
5485 "SYS_lstat", //293
5486 "SYS_fhstat", //294
5487 "SYS___semctl", //295
5488 "SYS_shmctl", //296
5489 "SYS_msgctl", //297
5490 "SYS_MAXSYSCALL", //298
5491 //299
5492 //300
5493 };
5494 uint32_t uEAX;
5495 if (!LogIsEnabled())
5496 return;
5497 uEAX = CPUMGetGuestEAX(pVCpu);
5498 switch (uEAX)
5499 {
5500 default:
5501 if (uEAX < RT_ELEMENTS(apsz))
5502 {
5503 uint32_t au32Args[8] = {0};
5504 PGMPhysSimpleReadGCPtr(pVCpu, au32Args, CPUMGetGuestESP(pVCpu), sizeof(au32Args));
5505 RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
5506 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
5507 au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
5508 }
5509 else
5510 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX);
5511 break;
5512 }
5513}
5514
5515
5516#if defined(IPRT_NO_CRT) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
5517/**
5518 * The Dll main entry point (stub).
5519 */
5520bool __stdcall _DllMainCRTStartup(void *hModule, uint32_t dwReason, void *pvReserved)
5521{
5522 return true;
5523}
5524
5525void *memcpy(void *dst, const void *src, size_t size)
5526{
5527 uint8_t*pbDst = dst, *pbSrc = src;
5528 while (size-- > 0)
5529 *pbDst++ = *pbSrc++;
5530 return dst;
5531}
5532
5533#endif
5534
5535void cpu_smm_update(CPUX86State *env)
5536{
5537}
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