VirtualBox

source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 62286

Last change on this file since 62286 was 62286, checked in by vboxsync, 9 years ago

REM: Fixed TRPM -> recompiler IRQ translation problem, well hacked it.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 186.2 KB
Line 
1/* $Id: VBoxRecompiler.c 62286 2016-07-15 18:02:42Z vboxsync $ */
2/** @file
3 * VBox Recompiler - QEMU.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_rem REM - Recompiled Execution Manager.
19 *
20 * The recompiled exeuction manager (REM) serves the final fallback for guest
21 * execution, after HM / raw-mode and IEM have given up.
22 *
23 * The REM is qemu with a whole bunch of VBox specific customization for
24 * interfacing with PATM, CSAM, PGM and other components.
25 *
26 * @sa @ref grp_rem
27 */
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_REM
33#include <stdio.h> /* FILE */
34#include "osdep.h"
35#include "config.h"
36#include "cpu.h"
37#include "exec-all.h"
38#include "ioport.h"
39
40#include <VBox/vmm/rem.h>
41#include <VBox/vmm/vmapi.h>
42#include <VBox/vmm/tm.h>
43#include <VBox/vmm/ssm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/trpm.h>
46#include <VBox/vmm/iom.h>
47#include <VBox/vmm/mm.h>
48#include <VBox/vmm/pgm.h>
49#include <VBox/vmm/pdm.h>
50#include <VBox/vmm/dbgf.h>
51#include <VBox/dbg.h>
52#ifdef VBOX_WITH_NEW_APIC
53# include <VBox/vmm/apic.h>
54#endif
55#include <VBox/vmm/hm.h>
56#include <VBox/vmm/patm.h>
57#include <VBox/vmm/csam.h>
58#include "REMInternal.h"
59#include <VBox/vmm/vm.h>
60#include <VBox/vmm/uvm.h>
61#include <VBox/param.h>
62#include <VBox/err.h>
63
64#include <VBox/log.h>
65#include <iprt/alloca.h>
66#include <iprt/semaphore.h>
67#include <iprt/asm.h>
68#include <iprt/assert.h>
69#include <iprt/thread.h>
70#include <iprt/string.h>
71
72/* Don't wanna include everything. */
73extern void cpu_exec_init_all(uintptr_t tb_size);
74extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
75extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
76extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
77extern void tlb_flush_page(CPUX86State *env, target_ulong addr);
78extern void tlb_flush(CPUX86State *env, int flush_global);
79extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
80extern void sync_ldtr(CPUX86State *env1, int selector);
81
82#ifdef VBOX_STRICT
83ram_addr_t get_phys_page_offset(target_ulong addr);
84#endif
85
86
87/*********************************************************************************************************************************
88* Defined Constants And Macros *
89*********************************************************************************************************************************/
90
91/** Copy 80-bit fpu register at pSrc to pDst.
92 * This is probably faster than *calling* memcpy.
93 */
94#define REM_COPY_FPU_REG(pDst, pSrc) \
95 do { *(PX86FPUMMX)(pDst) = *(const X86FPUMMX *)(pSrc); } while (0)
96
97/** How remR3RunLoggingStep operates. */
98#define REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
99
100
101/** Selector flag shift between qemu and VBox.
102 * VBox shifts the qemu bits to the right. */
103#define SEL_FLAGS_SHIFT (8)
104/** Mask applied to the shifted qemu selector flags to get the attributes VBox
105 * (VT-x) needs. */
106#define SEL_FLAGS_SMASK UINT32_C(0x1F0FF)
107
108
109/*********************************************************************************************************************************
110* Internal Functions *
111*********************************************************************************************************************************/
112static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
113static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
114static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu);
115static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded);
116
117static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys);
118static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys);
119static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys);
120static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
121static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
122static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32);
123
124static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
125static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
126static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
127static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
128static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
129static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
130
131static void remR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
132static void remR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler);
133static void remR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
134
135
136/*********************************************************************************************************************************
137* Global Variables *
138*********************************************************************************************************************************/
139
140/** @todo Move stats to REM::s some rainy day we have nothing do to. */
141#ifdef VBOX_WITH_STATISTICS
142static STAMPROFILEADV gStatExecuteSingleInstr;
143static STAMPROFILEADV gStatCompilationQEmu;
144static STAMPROFILEADV gStatRunCodeQEmu;
145static STAMPROFILEADV gStatTotalTimeQEmu;
146static STAMPROFILEADV gStatTimers;
147static STAMPROFILEADV gStatTBLookup;
148static STAMPROFILEADV gStatIRQ;
149static STAMPROFILEADV gStatRawCheck;
150static STAMPROFILEADV gStatMemRead;
151static STAMPROFILEADV gStatMemWrite;
152static STAMPROFILE gStatGCPhys2HCVirt;
153static STAMCOUNTER gStatCpuGetTSC;
154static STAMCOUNTER gStatRefuseTFInhibit;
155static STAMCOUNTER gStatRefuseVM86;
156static STAMCOUNTER gStatRefusePaging;
157static STAMCOUNTER gStatRefusePAE;
158static STAMCOUNTER gStatRefuseIOPLNot0;
159static STAMCOUNTER gStatRefuseIF0;
160static STAMCOUNTER gStatRefuseCode16;
161static STAMCOUNTER gStatRefuseWP0;
162static STAMCOUNTER gStatRefuseRing1or2;
163static STAMCOUNTER gStatRefuseCanExecute;
164static STAMCOUNTER gaStatRefuseStale[6];
165static STAMCOUNTER gStatREMGDTChange;
166static STAMCOUNTER gStatREMIDTChange;
167static STAMCOUNTER gStatREMLDTRChange;
168static STAMCOUNTER gStatREMTRChange;
169static STAMCOUNTER gStatSelOutOfSync[6];
170static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
171static STAMCOUNTER gStatFlushTBs;
172#endif
173/* in exec.c */
174extern uint32_t tlb_flush_count;
175extern uint32_t tb_flush_count;
176extern uint32_t tb_phys_invalidate_count;
177
178/*
179 * Global stuff.
180 */
181
182/** MMIO read callbacks. */
183CPUReadMemoryFunc *g_apfnMMIORead[3] =
184{
185 remR3MMIOReadU8,
186 remR3MMIOReadU16,
187 remR3MMIOReadU32
188};
189
190/** MMIO write callbacks. */
191CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
192{
193 remR3MMIOWriteU8,
194 remR3MMIOWriteU16,
195 remR3MMIOWriteU32
196};
197
198/** Handler read callbacks. */
199CPUReadMemoryFunc *g_apfnHandlerRead[3] =
200{
201 remR3HandlerReadU8,
202 remR3HandlerReadU16,
203 remR3HandlerReadU32
204};
205
206/** Handler write callbacks. */
207CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
208{
209 remR3HandlerWriteU8,
210 remR3HandlerWriteU16,
211 remR3HandlerWriteU32
212};
213
214
215#ifdef VBOX_WITH_DEBUGGER
216/*
217 * Debugger commands.
218 */
219static FNDBGCCMD remR3CmdDisasEnableStepping;;
220
221/** '.remstep' arguments. */
222static const DBGCVARDESC g_aArgRemStep[] =
223{
224 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
225 { 0, ~0U, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
226};
227
228/** Command descriptors. */
229static const DBGCCMD g_aCmds[] =
230{
231 {
232 .pszCmd ="remstep",
233 .cArgsMin = 0,
234 .cArgsMax = 1,
235 .paArgDescs = &g_aArgRemStep[0],
236 .cArgDescs = RT_ELEMENTS(g_aArgRemStep),
237 .fFlags = 0,
238 .pfnHandler = remR3CmdDisasEnableStepping,
239 .pszSyntax = "[on/off]",
240 .pszDescription = "Enable or disable the single stepping with logged disassembly. "
241 "If no arguments show the current state."
242 }
243};
244#endif
245
246/** Prologue code, must be in lower 4G to simplify jumps to/from generated code.
247 * @todo huh??? That cannot be the case on the mac... So, this
248 * point is probably not valid any longer. */
249uint8_t *code_gen_prologue;
250
251
252/*********************************************************************************************************************************
253* Internal Functions *
254*********************************************************************************************************************************/
255void remAbort(int rc, const char *pszTip);
256extern int testmath(void);
257
258/* Put them here to avoid unused variable warning. */
259AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
260#if !defined(IPRT_NO_CRT) && (defined(RT_OS_LINUX) || defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS))
261//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
262/* Why did this have to be identical?? */
263AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
264#else
265AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
266#endif
267
268
269/**
270 * Initializes the REM.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM to operate on.
274 */
275REMR3DECL(int) REMR3Init(PVM pVM)
276{
277 PREMHANDLERNOTIFICATION pCur;
278 uint32_t u32Dummy;
279 int rc;
280 unsigned i;
281
282#ifdef VBOX_ENABLE_VBOXREM64
283 LogRel(("Using 64-bit aware REM\n"));
284#endif
285
286 /*
287 * Assert sanity.
288 */
289 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
290 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
291 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
292#if 0 /* just an annoyance at the moment. */
293#if defined(DEBUG) && !defined(RT_OS_SOLARIS) && !defined(RT_OS_FREEBSD) /// @todo fix the solaris and freebsd math stuff.
294 Assert(!testmath());
295#endif
296#endif
297
298 /*
299 * Init some internal data members.
300 */
301 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
302 pVM->rem.s.Env.pVM = pVM;
303#ifdef CPU_RAW_MODE_INIT
304 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
305#endif
306
307 /*
308 * Initialize the REM critical section.
309 *
310 * Note: This is not a 100% safe solution as updating the internal memory state while another VCPU
311 * is executing code could be dangerous. Taking the REM lock is not an option due to the danger of
312 * deadlocks. (mostly pgm vs rem locking)
313 */
314 rc = PDMR3CritSectInit(pVM, &pVM->rem.s.CritSectRegister, RT_SRC_POS, "REM-Register");
315 AssertRCReturn(rc, rc);
316
317 /* ctx. */
318 pVM->rem.s.pCtx = NULL; /* set when executing code. */
319 AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order has changed! REM depends on notification about ALL physical memory registrations\n"));
320
321 /* ignore all notifications */
322 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
323
324 code_gen_prologue = RTMemExecAlloc(_1K);
325 AssertLogRelReturn(code_gen_prologue, VERR_NO_MEMORY);
326
327 cpu_exec_init_all(0);
328
329 /*
330 * Init the recompiler.
331 */
332 if (!cpu_x86_init(&pVM->rem.s.Env, "vbox"))
333 {
334 AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
335 return VERR_GENERAL_FAILURE;
336 }
337 PVMCPU pVCpu = VMMGetCpu(pVM);
338 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
339 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
340
341 EMRemLock(pVM);
342 cpu_reset(&pVM->rem.s.Env);
343 EMRemUnlock(pVM);
344
345 /* allocate code buffer for single instruction emulation. */
346 pVM->rem.s.Env.cbCodeBuffer = 4096;
347 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
348 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
349
350 /* Finally, set the cpu_single_env global. */
351 cpu_single_env = &pVM->rem.s.Env;
352
353 /* Nothing is pending by default */
354 pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
355
356 /*
357 * Register ram types.
358 */
359 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(g_apfnMMIORead, g_apfnMMIOWrite, &pVM->rem.s.Env);
360 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
361 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
362 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
363 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
364
365 /* stop ignoring. */
366 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
367
368 /*
369 * Register the saved state data unit.
370 */
371 rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
372 NULL, NULL, NULL,
373 NULL, remR3Save, NULL,
374 NULL, remR3Load, NULL);
375 if (RT_FAILURE(rc))
376 return rc;
377
378#ifdef VBOX_WITH_DEBUGGER
379 /*
380 * Debugger commands.
381 */
382 static bool fRegisteredCmds = false;
383 if (!fRegisteredCmds)
384 {
385 int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
386 if (RT_SUCCESS(rc))
387 fRegisteredCmds = true;
388 }
389#endif
390
391#ifdef VBOX_WITH_STATISTICS
392 /*
393 * Statistics.
394 */
395 STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
396 STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
397 STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
398 STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
399 STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer queue processing.");
400 STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling translation block lookup.");
401 STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling IRQ delivery.");
402 STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling remR3CanExecuteRaw calls.");
403 STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
404 STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
405 STAM_REG(pVM, &gStatGCPhys2HCVirt, STAMTYPE_PROFILE, "/PROF/REM/GCPhys2HCVirt", STAMUNIT_TICKS_PER_CALL, "Profiling memory conversion (PGMR3PhysTlbGCPhys2Ptr).");
406
407 STAM_REG(pVM, &gStatCpuGetTSC, STAMTYPE_COUNTER, "/REM/CpuGetTSC", STAMUNIT_OCCURENCES, "cpu_get_tsc calls");
408
409 STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
410 STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
411 STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
412 STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
413 STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
414 STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
415 STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
416 STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
417 STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
418 STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
419 STAM_REG(pVM, &gaStatRefuseStale[R_ES], STAMTYPE_COUNTER, "/REM/Refuse/StaleES", STAMUNIT_OCCURENCES, "Raw mode refused because of stale ES");
420 STAM_REG(pVM, &gaStatRefuseStale[R_CS], STAMTYPE_COUNTER, "/REM/Refuse/StaleCS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale CS");
421 STAM_REG(pVM, &gaStatRefuseStale[R_SS], STAMTYPE_COUNTER, "/REM/Refuse/StaleSS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale SS");
422 STAM_REG(pVM, &gaStatRefuseStale[R_DS], STAMTYPE_COUNTER, "/REM/Refuse/StaleDS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale DS");
423 STAM_REG(pVM, &gaStatRefuseStale[R_FS], STAMTYPE_COUNTER, "/REM/Refuse/StaleFS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale FS");
424 STAM_REG(pVM, &gaStatRefuseStale[R_GS], STAMTYPE_COUNTER, "/REM/Refuse/StaleGS", STAMUNIT_OCCURENCES, "Raw mode refused because of stale GS");
425 STAM_REG(pVM, &gStatFlushTBs, STAMTYPE_COUNTER, "/REM/FlushTB", STAMUNIT_OCCURENCES, "Number of TB flushes");
426
427 STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
428 STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
429 STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
430 STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
431
432 STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
433 STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
434 STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
435 STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
436 STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
437 STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
438
439 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
440 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
441 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
442 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
443 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
444 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
445
446 STAM_REG(pVM, &pVM->rem.s.Env.StatTbFlush, STAMTYPE_PROFILE, "/REM/TbFlush", STAMUNIT_TICKS_PER_CALL, "profiling tb_flush().");
447#endif /* VBOX_WITH_STATISTICS */
448 AssertCompileMemberAlignment(CPUX86State, StatTbFlush, 4);
449 AssertCompileMemberAlignment(CPUX86State, StatTbFlush, 8);
450
451 STAM_REL_REG(pVM, &tb_flush_count, STAMTYPE_U32_RESET, "/REM/TbFlushCount", STAMUNIT_OCCURENCES, "tb_flush() calls");
452 STAM_REL_REG(pVM, &tb_phys_invalidate_count, STAMTYPE_U32_RESET, "/REM/TbPhysInvldCount", STAMUNIT_OCCURENCES, "tb_phys_invalidate() calls");
453 STAM_REL_REG(pVM, &tlb_flush_count, STAMTYPE_U32_RESET, "/REM/TlbFlushCount", STAMUNIT_OCCURENCES, "tlb_flush() calls");
454
455
456#ifdef DEBUG_ALL_LOGGING
457 loglevel = ~0;
458#endif
459
460 /*
461 * Init the handler notification lists.
462 */
463 pVM->rem.s.idxPendingList = UINT32_MAX;
464 pVM->rem.s.idxFreeList = 0;
465
466 for (i = 0 ; i < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications); i++)
467 {
468 pCur = &pVM->rem.s.aHandlerNotifications[i];
469 pCur->idxNext = i + 1;
470 pCur->idxSelf = i;
471 }
472 pCur->idxNext = UINT32_MAX; /* the last record. */
473
474 return rc;
475}
476
477
478/**
479 * Finalizes the REM initialization.
480 *
481 * This is called after all components, devices and drivers has
482 * been initialized. Its main purpose it to finish the RAM related
483 * initialization.
484 *
485 * @returns VBox status code.
486 *
487 * @param pVM The VM handle.
488 */
489REMR3DECL(int) REMR3InitFinalize(PVM pVM)
490{
491 int rc;
492
493 /*
494 * Ram size & dirty bit map.
495 */
496 Assert(!pVM->rem.s.fGCPhysLastRamFixed);
497 pVM->rem.s.fGCPhysLastRamFixed = true;
498#ifdef RT_STRICT
499 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, true /* fGuarded */);
500#else
501 rc = remR3InitPhysRamSizeAndDirtyMap(pVM, false /* fGuarded */);
502#endif
503 return rc;
504}
505
506/**
507 * Initializes ram_list.phys_dirty and ram_list.phys_dirty_size.
508 *
509 * @returns VBox status code.
510 * @param pVM The VM handle.
511 * @param fGuarded Whether to guard the map.
512 */
513static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded)
514{
515 int rc = VINF_SUCCESS;
516 RTGCPHYS cb;
517
518 AssertLogRelReturn(QLIST_EMPTY(&ram_list.blocks), VERR_INTERNAL_ERROR_2);
519
520 cb = pVM->rem.s.GCPhysLastRam + 1;
521 AssertLogRelMsgReturn(cb > pVM->rem.s.GCPhysLastRam,
522 ("GCPhysLastRam=%RGp - out of range\n", pVM->rem.s.GCPhysLastRam),
523 VERR_OUT_OF_RANGE);
524
525 ram_list.phys_dirty_size = cb >> PAGE_SHIFT;
526 AssertMsg(((RTGCPHYS)ram_list.phys_dirty_size << PAGE_SHIFT) == cb, ("%RGp\n", cb));
527
528 if (!fGuarded)
529 {
530 ram_list.phys_dirty = MMR3HeapAlloc(pVM, MM_TAG_REM, ram_list.phys_dirty_size);
531 AssertLogRelMsgReturn(ram_list.phys_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", ram_list.phys_dirty_size), VERR_NO_MEMORY);
532 }
533 else
534 {
535 /*
536 * Fill it up the nearest 4GB RAM and leave at least _64KB of guard after it.
537 */
538 uint32_t cbBitmapAligned = RT_ALIGN_32(ram_list.phys_dirty_size, PAGE_SIZE);
539 uint32_t cbBitmapFull = RT_ALIGN_32(ram_list.phys_dirty_size, (_4G >> PAGE_SHIFT));
540 if (cbBitmapFull == cbBitmapAligned)
541 cbBitmapFull += _4G >> PAGE_SHIFT;
542 else if (cbBitmapFull - cbBitmapAligned < _64K)
543 cbBitmapFull += _64K;
544
545 ram_list.phys_dirty = RTMemPageAlloc(cbBitmapFull);
546 AssertLogRelMsgReturn(ram_list.phys_dirty, ("Failed to allocate %u bytes of dirty page map bytes\n", cbBitmapFull), VERR_NO_MEMORY);
547
548 rc = RTMemProtect(ram_list.phys_dirty + cbBitmapAligned, cbBitmapFull - cbBitmapAligned, RTMEM_PROT_NONE);
549 if (RT_FAILURE(rc))
550 {
551 RTMemPageFree(ram_list.phys_dirty, cbBitmapFull);
552 AssertLogRelRCReturn(rc, rc);
553 }
554
555 ram_list.phys_dirty += cbBitmapAligned - ram_list.phys_dirty_size;
556 }
557
558 /* initialize it. */
559 memset(ram_list.phys_dirty, 0xff, ram_list.phys_dirty_size);
560 return rc;
561}
562
563
564/**
565 * Terminates the REM.
566 *
567 * Termination means cleaning up and freeing all resources,
568 * the VM it self is at this point powered off or suspended.
569 *
570 * @returns VBox status code.
571 * @param pVM The VM to operate on.
572 */
573REMR3DECL(int) REMR3Term(PVM pVM)
574{
575 /*
576 * Statistics.
577 */
578 STAMR3Deregister(pVM->pUVM, "/PROF/REM/*");
579 STAMR3Deregister(pVM->pUVM, "/REM/*");
580
581 return VINF_SUCCESS;
582}
583
584
585/**
586 * The VM is being reset.
587 *
588 * For the REM component this means to call the cpu_reset() and
589 * reinitialize some state variables.
590 *
591 * @param pVM VM handle.
592 */
593REMR3DECL(void) REMR3Reset(PVM pVM)
594{
595 EMRemLock(pVM); /* Only pro forma, we're in a rendezvous. */
596
597 /*
598 * Reset the REM cpu.
599 */
600 Assert(pVM->rem.s.cIgnoreAll == 0);
601 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
602 cpu_reset(&pVM->rem.s.Env);
603 pVM->rem.s.cInvalidatedPages = 0;
604 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
605 Assert(pVM->rem.s.cIgnoreAll == 0);
606
607 /* Clear raw ring 0 init state */
608 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
609
610 /* Flush the TBs the next time we execute code here. */
611 pVM->rem.s.fFlushTBs = true;
612
613 EMRemUnlock(pVM);
614}
615
616
617/**
618 * Execute state save operation.
619 *
620 * @returns VBox status code.
621 * @param pVM VM Handle.
622 * @param pSSM SSM operation handle.
623 */
624static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
625{
626 PREM pRem = &pVM->rem.s;
627
628 /*
629 * Save the required CPU Env bits.
630 * (Not much because we're never in REM when doing the save.)
631 */
632 LogFlow(("remR3Save:\n"));
633 Assert(!pRem->fInREM);
634 SSMR3PutU32(pSSM, pRem->Env.hflags);
635 SSMR3PutU32(pSSM, ~0); /* separator */
636
637 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
638 SSMR3PutU32(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
639 SSMR3PutU32(pSSM, pVM->rem.s.u32PendingInterrupt);
640
641 return SSMR3PutU32(pSSM, ~0); /* terminator */
642}
643
644
645/**
646 * Execute state load operation.
647 *
648 * @returns VBox status code.
649 * @param pVM VM Handle.
650 * @param pSSM SSM operation handle.
651 * @param uVersion Data layout version.
652 * @param uPass The data pass.
653 */
654static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
655{
656 uint32_t u32Dummy;
657 uint32_t fRawRing0 = false;
658 uint32_t u32Sep;
659 uint32_t i;
660 int rc;
661 PREM pRem;
662
663 LogFlow(("remR3Load:\n"));
664 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
665
666 /*
667 * Validate version.
668 */
669 if ( uVersion != REM_SAVED_STATE_VERSION
670 && uVersion != REM_SAVED_STATE_VERSION_VER1_6)
671 {
672 AssertMsgFailed(("remR3Load: Invalid version uVersion=%d!\n", uVersion));
673 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
674 }
675
676 /*
677 * Do a reset to be on the safe side...
678 */
679 REMR3Reset(pVM);
680
681 /*
682 * Ignore all ignorable notifications.
683 * (Not doing this will cause serious trouble.)
684 */
685 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
686
687 /*
688 * Load the required CPU Env bits.
689 * (Not much because we're never in REM when doing the save.)
690 */
691 pRem = &pVM->rem.s;
692 Assert(!pRem->fInREM);
693 SSMR3GetU32(pSSM, &pRem->Env.hflags);
694 if (uVersion == REM_SAVED_STATE_VERSION_VER1_6)
695 {
696 /* Redundant REM CPU state has to be loaded, but can be ignored. */
697 CPUX86State_Ver16 temp;
698 SSMR3GetMem(pSSM, &temp, RT_OFFSETOF(CPUX86State_Ver16, jmp_env));
699 }
700
701 rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
702 if (RT_FAILURE(rc))
703 return rc;
704 if (u32Sep != ~0U)
705 {
706 AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
707 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
708 }
709
710 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
711 SSMR3GetUInt(pSSM, &fRawRing0);
712 if (fRawRing0)
713 pRem->Env.state |= CPU_RAW_RING0;
714
715 if (uVersion == REM_SAVED_STATE_VERSION_VER1_6)
716 {
717 /*
718 * Load the REM stuff.
719 */
720 /** @todo r=bird: We should just drop all these items, restoring doesn't make
721 * sense. */
722 rc = SSMR3GetU32(pSSM, (uint32_t *)&pRem->cInvalidatedPages);
723 if (RT_FAILURE(rc))
724 return rc;
725 if (pRem->cInvalidatedPages > RT_ELEMENTS(pRem->aGCPtrInvalidatedPages))
726 {
727 AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
728 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
729 }
730 for (i = 0; i < pRem->cInvalidatedPages; i++)
731 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
732 }
733
734 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
735 if (RT_FAILURE(rc))
736 return rc;
737
738 /* check the terminator. */
739 rc = SSMR3GetU32(pSSM, &u32Sep);
740 if (RT_FAILURE(rc))
741 return rc;
742 if (u32Sep != ~0U)
743 {
744 AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
745 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
746 }
747
748 /*
749 * Get the CPUID features.
750 */
751 PVMCPU pVCpu = VMMGetCpu(pVM);
752 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
753 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
754
755 /*
756 * Stop ignoring ignorable notifications.
757 */
758 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
759
760 /*
761 * Sync the whole CPU state when executing code in the recompiler.
762 */
763 for (i = 0; i < pVM->cCpus; i++)
764 {
765 PVMCPU pVCpu = &pVM->aCpus[i];
766 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
767 }
768 return VINF_SUCCESS;
769}
770
771
772
773#undef LOG_GROUP
774#define LOG_GROUP LOG_GROUP_REM_RUN
775
776/**
777 * Single steps an instruction in recompiled mode.
778 *
779 * Before calling this function the REM state needs to be in sync with
780 * the VM. Call REMR3State() to perform the sync. It's only necessary
781 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
782 * and after calling REMR3StateBack().
783 *
784 * @returns VBox status code.
785 *
786 * @param pVM VM Handle.
787 * @param pVCpu VMCPU Handle.
788 */
789REMR3DECL(int) REMR3Step(PVM pVM, PVMCPU pVCpu)
790{
791 int rc, interrupt_request;
792 RTGCPTR GCPtrPC;
793 bool fBp;
794
795 /*
796 * Lock the REM - we don't wanna have anyone interrupting us
797 * while stepping - and enabled single stepping. We also ignore
798 * pending interrupts and suchlike.
799 */
800 interrupt_request = pVM->rem.s.Env.interrupt_request;
801 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB | CPU_INTERRUPT_EXTERNAL_TIMER)));
802 pVM->rem.s.Env.interrupt_request = 0;
803 cpu_single_step(&pVM->rem.s.Env, 1);
804
805 /*
806 * If we're standing at a breakpoint, that have to be disabled before we start stepping.
807 */
808 GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
809 fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC, BP_GDB);
810
811 /*
812 * Execute and handle the return code.
813 * We execute without enabling the cpu tick, so on success we'll
814 * just flip it on and off to make sure it moves
815 */
816 rc = cpu_exec(&pVM->rem.s.Env);
817 if (rc == EXCP_DEBUG)
818 {
819 TMR3NotifyResume(pVM, pVCpu);
820 TMR3NotifySuspend(pVM, pVCpu);
821 rc = VINF_EM_DBG_STEPPED;
822 }
823 else
824 {
825 switch (rc)
826 {
827 case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
828 case EXCP_HLT:
829 case EXCP_HALTED: rc = VINF_EM_HALT; break;
830 case EXCP_RC:
831 rc = pVM->rem.s.rc;
832 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
833 break;
834 case EXCP_EXECUTE_RAW:
835 case EXCP_EXECUTE_HM:
836 /** @todo: is it correct? No! */
837 rc = VINF_SUCCESS;
838 break;
839 default:
840 AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
841 rc = VERR_INTERNAL_ERROR;
842 break;
843 }
844 }
845
846 /*
847 * Restore the stuff we changed to prevent interruption.
848 * Unlock the REM.
849 */
850 if (fBp)
851 {
852 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC, BP_GDB, NULL);
853 Assert(rc2 == 0); NOREF(rc2);
854 }
855 cpu_single_step(&pVM->rem.s.Env, 0);
856 pVM->rem.s.Env.interrupt_request = interrupt_request;
857
858 return rc;
859}
860
861
862/**
863 * Set a breakpoint using the REM facilities.
864 *
865 * @returns VBox status code.
866 * @param pVM The VM handle.
867 * @param Address The breakpoint address.
868 * @thread The emulation thread.
869 */
870REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
871{
872 VM_ASSERT_EMT(pVM);
873 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address, BP_GDB, NULL))
874 {
875 LogFlow(("REMR3BreakpointSet: Address=%RGv\n", Address));
876 return VINF_SUCCESS;
877 }
878 LogFlow(("REMR3BreakpointSet: Address=%RGv - failed!\n", Address));
879 return VERR_REM_NO_MORE_BP_SLOTS;
880}
881
882
883/**
884 * Clears a breakpoint set by REMR3BreakpointSet().
885 *
886 * @returns VBox status code.
887 * @param pVM The VM handle.
888 * @param Address The breakpoint address.
889 * @thread The emulation thread.
890 */
891REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
892{
893 VM_ASSERT_EMT(pVM);
894 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address, BP_GDB))
895 {
896 LogFlow(("REMR3BreakpointClear: Address=%RGv\n", Address));
897 return VINF_SUCCESS;
898 }
899 LogFlow(("REMR3BreakpointClear: Address=%RGv - not found!\n", Address));
900 return VERR_REM_BP_NOT_FOUND;
901}
902
903
904/**
905 * Emulate an instruction.
906 *
907 * This function executes one instruction without letting anyone
908 * interrupt it. This is intended for being called while being in
909 * raw mode and thus will take care of all the state syncing between
910 * REM and the rest.
911 *
912 * @returns VBox status code.
913 * @param pVM VM handle.
914 * @param pVCpu VMCPU Handle.
915 */
916REMR3DECL(int) REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu)
917{
918 bool fFlushTBs;
919
920 int rc, rc2;
921 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
922
923 /* Make sure this flag is set; we might never execute remR3CanExecuteRaw in the AMD-V case.
924 * CPU_RAW_HM makes sure we never execute interrupt handlers in the recompiler.
925 */
926 if (HMIsEnabled(pVM))
927 pVM->rem.s.Env.state |= CPU_RAW_HM;
928
929 /* Skip the TB flush as that's rather expensive and not necessary for single instruction emulation. */
930 fFlushTBs = pVM->rem.s.fFlushTBs;
931 pVM->rem.s.fFlushTBs = false;
932
933 /*
934 * Sync the state and enable single instruction / single stepping.
935 */
936 rc = REMR3State(pVM, pVCpu);
937 pVM->rem.s.fFlushTBs = fFlushTBs;
938 if (RT_SUCCESS(rc))
939 {
940 int interrupt_request = pVM->rem.s.Env.interrupt_request;
941 Assert(!( interrupt_request
942 & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD
943 | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_FLUSH_TLB | CPU_INTERRUPT_EXTERNAL_TIMER
944 | CPU_INTERRUPT_EXTERNAL_DMA)));
945#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
946 cpu_single_step(&pVM->rem.s.Env, 0);
947#endif
948 Assert(!pVM->rem.s.Env.singlestep_enabled);
949
950 /*
951 * Now we set the execute single instruction flag and enter the cpu_exec loop.
952 */
953 TMNotifyStartOfExecution(pVCpu);
954 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
955 rc = cpu_exec(&pVM->rem.s.Env);
956 TMNotifyEndOfExecution(pVCpu);
957 switch (rc)
958 {
959 /*
960 * Executed without anything out of the way happening.
961 */
962 case EXCP_SINGLE_INSTR:
963 rc = VINF_EM_RESCHEDULE;
964 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
965 break;
966
967 /*
968 * If we take a trap or start servicing a pending interrupt, we might end up here.
969 * (Timer thread or some other thread wishing EMT's attention.)
970 */
971 case EXCP_INTERRUPT:
972 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
973 rc = VINF_EM_RESCHEDULE;
974 break;
975
976 /*
977 * Single step, we assume!
978 * If there was a breakpoint there we're fucked now.
979 */
980 case EXCP_DEBUG:
981 if (pVM->rem.s.Env.watchpoint_hit)
982 {
983 /** @todo deal with watchpoints */
984 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
985 rc = VINF_EM_DBG_BREAKPOINT;
986 }
987 else
988 {
989 CPUBreakpoint *pBP;
990 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
991 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
992 if (pBP->pc == GCPtrPC)
993 break;
994 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
995 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
996 }
997 break;
998
999 /*
1000 * hlt instruction.
1001 */
1002 case EXCP_HLT:
1003 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
1004 rc = VINF_EM_HALT;
1005 break;
1006
1007 /*
1008 * The VM has halted.
1009 */
1010 case EXCP_HALTED:
1011 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
1012 rc = VINF_EM_HALT;
1013 break;
1014
1015 /*
1016 * Switch to RAW-mode.
1017 */
1018 case EXCP_EXECUTE_RAW:
1019 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1020 rc = VINF_EM_RESCHEDULE_RAW;
1021 break;
1022
1023 /*
1024 * Switch to hardware accelerated RAW-mode.
1025 */
1026 case EXCP_EXECUTE_HM:
1027 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HM\n"));
1028 rc = VINF_EM_RESCHEDULE_HM;
1029 break;
1030
1031 /*
1032 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1033 */
1034 case EXCP_RC:
1035 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
1036 rc = pVM->rem.s.rc;
1037 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1038 break;
1039
1040 /*
1041 * Figure out the rest when they arrive....
1042 */
1043 default:
1044 AssertMsgFailed(("rc=%d\n", rc));
1045 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
1046 rc = VINF_EM_RESCHEDULE;
1047 break;
1048 }
1049
1050 /*
1051 * Switch back the state.
1052 */
1053 pVM->rem.s.Env.interrupt_request = interrupt_request;
1054 rc2 = REMR3StateBack(pVM, pVCpu);
1055 AssertRC(rc2);
1056 }
1057
1058 Log2(("REMR3EmulateInstruction: returns %Rrc (cs:eip=%04x:%RGv)\n",
1059 rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1060 return rc;
1061}
1062
1063
1064/**
1065 * Used by REMR3Run to handle the case where CPU_EMULATE_SINGLE_STEP is set.
1066 *
1067 * @returns VBox status code.
1068 *
1069 * @param pVM The VM handle.
1070 * @param pVCpu The Virtual CPU handle.
1071 */
1072static int remR3RunLoggingStep(PVM pVM, PVMCPU pVCpu)
1073{
1074 int rc;
1075
1076 Assert(pVM->rem.s.fInREM);
1077#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1078 cpu_single_step(&pVM->rem.s.Env, 1);
1079#else
1080 Assert(!pVM->rem.s.Env.singlestep_enabled);
1081#endif
1082
1083 /*
1084 * Now we set the execute single instruction flag and enter the cpu_exec loop.
1085 */
1086 for (;;)
1087 {
1088 char szBuf[256];
1089
1090 /*
1091 * Log the current registers state and instruction.
1092 */
1093 remR3StateUpdate(pVM, pVCpu);
1094 DBGFR3Info(pVM->pUVM, "cpumguest", NULL, NULL);
1095 szBuf[0] = '\0';
1096 rc = DBGFR3DisasInstrEx(pVM->pUVM,
1097 pVCpu->idCpu,
1098 0, /* Sel */ 0, /* GCPtr */
1099 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
1100 szBuf,
1101 sizeof(szBuf),
1102 NULL);
1103 if (RT_FAILURE(rc))
1104 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrEx failed with rc=%Rrc\n", rc);
1105 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
1106
1107 /*
1108 * Execute the instruction.
1109 */
1110 TMNotifyStartOfExecution(pVCpu);
1111
1112 if ( pVM->rem.s.Env.exception_index < 0
1113 || pVM->rem.s.Env.exception_index > 256)
1114 pVM->rem.s.Env.exception_index = -1; /** @todo We need to do similar stuff elsewhere, I think. */
1115
1116#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1117 pVM->rem.s.Env.interrupt_request = 0;
1118#else
1119 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
1120#endif
1121 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
1122 || pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
1123 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
1124 RTLogPrintf("remR3RunLoggingStep: interrupt_request=%#x halted=%d exception_index=%#x\n",
1125 pVM->rem.s.Env.interrupt_request,
1126 pVM->rem.s.Env.halted,
1127 pVM->rem.s.Env.exception_index
1128 );
1129
1130 rc = cpu_exec(&pVM->rem.s.Env);
1131
1132 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> %#x interrupt_request=%#x halted=%d exception_index=%#x\n", rc,
1133 pVM->rem.s.Env.interrupt_request,
1134 pVM->rem.s.Env.halted,
1135 pVM->rem.s.Env.exception_index
1136 );
1137
1138 TMNotifyEndOfExecution(pVCpu);
1139
1140 switch (rc)
1141 {
1142#ifndef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1143 /*
1144 * The normal exit.
1145 */
1146 case EXCP_SINGLE_INSTR:
1147 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1148 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1149 continue;
1150 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n",
1151 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1152 rc = VINF_SUCCESS;
1153 break;
1154
1155#else
1156 /*
1157 * The normal exit, check for breakpoints at PC just to be sure.
1158 */
1159#endif
1160 case EXCP_DEBUG:
1161 if (pVM->rem.s.Env.watchpoint_hit)
1162 {
1163 /** @todo deal with watchpoints */
1164 Log2(("remR3RunLoggingStep: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1165 rc = VINF_EM_DBG_BREAKPOINT;
1166 }
1167 else
1168 {
1169 CPUBreakpoint *pBP;
1170 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1171 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1172 if (pBP->pc == GCPtrPC)
1173 break;
1174 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1175 Log2(("remR3RunLoggingStep: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1176 }
1177#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1178 if (rc == VINF_EM_DBG_STEPPED)
1179 {
1180 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK)
1181 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))
1182 continue;
1183
1184 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n",
1185 pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1186 rc = VINF_SUCCESS;
1187 }
1188#endif
1189 break;
1190
1191 /*
1192 * If we take a trap or start servicing a pending interrupt, we might end up here.
1193 * (Timer thread or some other thread wishing EMT's attention.)
1194 */
1195 case EXCP_INTERRUPT:
1196 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_INTERRUPT rc=VINF_SUCCESS\n");
1197 rc = VINF_SUCCESS;
1198 break;
1199
1200 /*
1201 * hlt instruction.
1202 */
1203 case EXCP_HLT:
1204 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_HLT rc=VINF_EM_HALT\n");
1205 rc = VINF_EM_HALT;
1206 break;
1207
1208 /*
1209 * The VM has halted.
1210 */
1211 case EXCP_HALTED:
1212 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_HALTED rc=VINF_EM_HALT\n");
1213 rc = VINF_EM_HALT;
1214 break;
1215
1216 /*
1217 * Switch to RAW-mode.
1218 */
1219 case EXCP_EXECUTE_RAW:
1220 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_EXECUTE_RAW rc=VINF_EM_RESCHEDULE_RAW\n");
1221 rc = VINF_EM_RESCHEDULE_RAW;
1222 break;
1223
1224 /*
1225 * Switch to hardware accelerated RAW-mode.
1226 */
1227 case EXCP_EXECUTE_HM:
1228 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_EXECUTE_HM rc=VINF_EM_RESCHEDULE_HM\n");
1229 rc = VINF_EM_RESCHEDULE_HM;
1230 break;
1231
1232 /*
1233 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1234 */
1235 case EXCP_RC:
1236 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc);
1237 rc = pVM->rem.s.rc;
1238 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1239 break;
1240
1241 /*
1242 * Figure out the rest when they arrive....
1243 */
1244 default:
1245 AssertMsgFailed(("rc=%d\n", rc));
1246 RTLogPrintf("remR3RunLoggingStep: cpu_exec -> %d rc=VINF_EM_RESCHEDULE\n", rc);
1247 rc = VINF_EM_RESCHEDULE;
1248 break;
1249 }
1250 break;
1251 }
1252
1253#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
1254// cpu_single_step(&pVM->rem.s.Env, 0);
1255#else
1256 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_SINGLE_INSTR | CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT);
1257#endif
1258 return rc;
1259}
1260
1261
1262/**
1263 * Runs code in recompiled mode.
1264 *
1265 * Before calling this function the REM state needs to be in sync with
1266 * the VM. Call REMR3State() to perform the sync. It's only necessary
1267 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
1268 * and after calling REMR3StateBack().
1269 *
1270 * @returns VBox status code.
1271 *
1272 * @param pVM VM Handle.
1273 * @param pVCpu VMCPU Handle.
1274 */
1275REMR3DECL(int) REMR3Run(PVM pVM, PVMCPU pVCpu)
1276{
1277 int rc;
1278
1279 if (RT_UNLIKELY(pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP))
1280 return remR3RunLoggingStep(pVM, pVCpu);
1281
1282 Assert(pVM->rem.s.fInREM);
1283 Log2(("REMR3Run: (cs:eip=%04x:%RGv)\n", pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1284
1285 TMNotifyStartOfExecution(pVCpu);
1286 rc = cpu_exec(&pVM->rem.s.Env);
1287 TMNotifyEndOfExecution(pVCpu);
1288 switch (rc)
1289 {
1290 /*
1291 * This happens when the execution was interrupted
1292 * by an external event, like pending timers.
1293 */
1294 case EXCP_INTERRUPT:
1295 Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
1296 rc = VINF_SUCCESS;
1297 break;
1298
1299 /*
1300 * hlt instruction.
1301 */
1302 case EXCP_HLT:
1303 Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
1304 rc = VINF_EM_HALT;
1305 break;
1306
1307 /*
1308 * The VM has halted.
1309 */
1310 case EXCP_HALTED:
1311 Log2(("REMR3Run: cpu_exec -> EXCP_HALTED\n"));
1312 rc = VINF_EM_HALT;
1313 break;
1314
1315 /*
1316 * Breakpoint/single step.
1317 */
1318 case EXCP_DEBUG:
1319 if (pVM->rem.s.Env.watchpoint_hit)
1320 {
1321 /** @todo deal with watchpoints */
1322 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc !watchpoint_hit!\n", rc));
1323 rc = VINF_EM_DBG_BREAKPOINT;
1324 }
1325 else
1326 {
1327 CPUBreakpoint *pBP;
1328 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1329 QTAILQ_FOREACH(pBP, &pVM->rem.s.Env.breakpoints, entry)
1330 if (pBP->pc == GCPtrPC)
1331 break;
1332 rc = pBP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_STEPPED;
1333 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc pBP=%p GCPtrPC=%RGv\n", rc, pBP, GCPtrPC));
1334 }
1335 break;
1336
1337 /*
1338 * Switch to RAW-mode.
1339 */
1340 case EXCP_EXECUTE_RAW:
1341 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW pc=%RGv\n", pVM->rem.s.Env.eip));
1342 rc = VINF_EM_RESCHEDULE_RAW;
1343 break;
1344
1345 /*
1346 * Switch to hardware accelerated RAW-mode.
1347 */
1348 case EXCP_EXECUTE_HM:
1349 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_HM\n"));
1350 rc = VINF_EM_RESCHEDULE_HM;
1351 break;
1352
1353 /*
1354 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1355 */
1356 case EXCP_RC:
1357 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1358 rc = pVM->rem.s.rc;
1359 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1360 break;
1361
1362 /*
1363 * Figure out the rest when they arrive....
1364 */
1365 default:
1366 AssertMsgFailed(("rc=%d\n", rc));
1367 Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1368 rc = VINF_SUCCESS;
1369 break;
1370 }
1371
1372 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%RGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1373 return rc;
1374}
1375
1376
1377/**
1378 * Check if the cpu state is suitable for Raw execution.
1379 *
1380 * @returns true if RAW/HWACC mode is ok, false if we should stay in REM.
1381 *
1382 * @param env The CPU env struct.
1383 * @param eip The EIP to check this for (might differ from env->eip).
1384 * @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1385 * @param piException Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1386 *
1387 * @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1388 */
1389bool remR3CanExecuteRaw(CPUX86State *env, RTGCPTR eip, unsigned fFlags, int *piException)
1390{
1391 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1392 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1393 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1394 uint32_t u32CR0;
1395
1396#ifdef IEM_VERIFICATION_MODE
1397 return false;
1398#endif
1399
1400 /* Update counter. */
1401 env->pVM->rem.s.cCanExecuteRaw++;
1402
1403 /* Never when single stepping+logging guest code. */
1404 if (env->state & CPU_EMULATE_SINGLE_STEP)
1405 return false;
1406
1407 if (HMIsEnabled(env->pVM))
1408 {
1409#ifdef RT_OS_WINDOWS
1410 PCPUMCTX pCtx = alloca(sizeof(*pCtx));
1411#else
1412 CPUMCTX Ctx;
1413 PCPUMCTX pCtx = &Ctx;
1414#endif
1415
1416 env->state |= CPU_RAW_HM;
1417
1418 /*
1419 * The simple check first...
1420 */
1421 if (!EMIsHwVirtExecutionEnabled(env->pVM))
1422 return false;
1423
1424 /*
1425 * Create partial context for HMR3CanExecuteGuest
1426 */
1427 pCtx->cr0 = env->cr[0];
1428 pCtx->cr3 = env->cr[3];
1429 pCtx->cr4 = env->cr[4];
1430
1431 pCtx->tr.Sel = env->tr.selector;
1432 pCtx->tr.ValidSel = env->tr.selector;
1433 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1434 pCtx->tr.u64Base = env->tr.base;
1435 pCtx->tr.u32Limit = env->tr.limit;
1436 pCtx->tr.Attr.u = (env->tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1437
1438 pCtx->ldtr.Sel = env->ldt.selector;
1439 pCtx->ldtr.ValidSel = env->ldt.selector;
1440 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1441 pCtx->ldtr.u64Base = env->ldt.base;
1442 pCtx->ldtr.u32Limit = env->ldt.limit;
1443 pCtx->ldtr.Attr.u = (env->ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1444
1445 pCtx->idtr.cbIdt = env->idt.limit;
1446 pCtx->idtr.pIdt = env->idt.base;
1447
1448 pCtx->gdtr.cbGdt = env->gdt.limit;
1449 pCtx->gdtr.pGdt = env->gdt.base;
1450
1451 pCtx->rsp = env->regs[R_ESP];
1452 pCtx->rip = env->eip;
1453
1454 pCtx->eflags.u32 = env->eflags;
1455
1456 pCtx->cs.Sel = env->segs[R_CS].selector;
1457 pCtx->cs.ValidSel = env->segs[R_CS].selector;
1458 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1459 pCtx->cs.u64Base = env->segs[R_CS].base;
1460 pCtx->cs.u32Limit = env->segs[R_CS].limit;
1461 pCtx->cs.Attr.u = (env->segs[R_CS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1462
1463 pCtx->ds.Sel = env->segs[R_DS].selector;
1464 pCtx->ds.ValidSel = env->segs[R_DS].selector;
1465 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1466 pCtx->ds.u64Base = env->segs[R_DS].base;
1467 pCtx->ds.u32Limit = env->segs[R_DS].limit;
1468 pCtx->ds.Attr.u = (env->segs[R_DS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1469
1470 pCtx->es.Sel = env->segs[R_ES].selector;
1471 pCtx->es.ValidSel = env->segs[R_ES].selector;
1472 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1473 pCtx->es.u64Base = env->segs[R_ES].base;
1474 pCtx->es.u32Limit = env->segs[R_ES].limit;
1475 pCtx->es.Attr.u = (env->segs[R_ES].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1476
1477 pCtx->fs.Sel = env->segs[R_FS].selector;
1478 pCtx->fs.ValidSel = env->segs[R_FS].selector;
1479 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1480 pCtx->fs.u64Base = env->segs[R_FS].base;
1481 pCtx->fs.u32Limit = env->segs[R_FS].limit;
1482 pCtx->fs.Attr.u = (env->segs[R_FS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1483
1484 pCtx->gs.Sel = env->segs[R_GS].selector;
1485 pCtx->gs.ValidSel = env->segs[R_GS].selector;
1486 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1487 pCtx->gs.u64Base = env->segs[R_GS].base;
1488 pCtx->gs.u32Limit = env->segs[R_GS].limit;
1489 pCtx->gs.Attr.u = (env->segs[R_GS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1490
1491 pCtx->ss.Sel = env->segs[R_SS].selector;
1492 pCtx->ss.ValidSel = env->segs[R_SS].selector;
1493 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1494 pCtx->ss.u64Base = env->segs[R_SS].base;
1495 pCtx->ss.u32Limit = env->segs[R_SS].limit;
1496 pCtx->ss.Attr.u = (env->segs[R_SS].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
1497
1498 pCtx->msrEFER = env->efer;
1499
1500 /* Hardware accelerated raw-mode:
1501 *
1502 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1503 */
1504 if (HMR3CanExecuteGuest(env->pVM, pCtx) == true)
1505 {
1506 *piException = EXCP_EXECUTE_HM;
1507 return true;
1508 }
1509 return false;
1510 }
1511
1512 /*
1513 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1514 * or 32 bits protected mode ring 0 code
1515 *
1516 * The tests are ordered by the likelihood of being true during normal execution.
1517 */
1518 if (fFlags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))
1519 {
1520 STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1521 Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1522 return false;
1523 }
1524
1525#ifndef VBOX_RAW_V86
1526 if (fFlags & VM_MASK) {
1527 STAM_COUNTER_INC(&gStatRefuseVM86);
1528 Log2(("raw mode refused: VM_MASK\n"));
1529 return false;
1530 }
1531#endif
1532
1533 if (env->state & CPU_EMULATE_SINGLE_INSTR)
1534 {
1535#ifndef DEBUG_bird
1536 Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1537#endif
1538 return false;
1539 }
1540
1541 if (env->singlestep_enabled)
1542 {
1543 //Log2(("raw mode refused: Single step\n"));
1544 return false;
1545 }
1546
1547 if (!QTAILQ_EMPTY(&env->breakpoints))
1548 {
1549 //Log2(("raw mode refused: Breakpoints\n"));
1550 return false;
1551 }
1552
1553 if (!QTAILQ_EMPTY(&env->watchpoints))
1554 {
1555 //Log2(("raw mode refused: Watchpoints\n"));
1556 return false;
1557 }
1558
1559 u32CR0 = env->cr[0];
1560 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1561 {
1562 STAM_COUNTER_INC(&gStatRefusePaging);
1563 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1564 return false;
1565 }
1566
1567 if (env->cr[4] & CR4_PAE_MASK)
1568 {
1569 if (!(env->cpuid_features & X86_CPUID_FEATURE_EDX_PAE))
1570 {
1571 STAM_COUNTER_INC(&gStatRefusePAE);
1572 return false;
1573 }
1574 }
1575
1576 if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1577 {
1578 if (!EMIsRawRing3Enabled(env->pVM))
1579 return false;
1580
1581 if (!(env->eflags & IF_MASK))
1582 {
1583 STAM_COUNTER_INC(&gStatRefuseIF0);
1584 Log2(("raw mode refused: IF (RawR3)\n"));
1585 return false;
1586 }
1587
1588 if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1589 {
1590 STAM_COUNTER_INC(&gStatRefuseWP0);
1591 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1592 return false;
1593 }
1594 }
1595 else
1596 {
1597 if (!EMIsRawRing0Enabled(env->pVM))
1598 return false;
1599
1600 // Let's start with pure 32 bits ring 0 code first
1601 if ((fFlags & (HF_SS32_MASK | HF_CS32_MASK)) != (HF_SS32_MASK | HF_CS32_MASK))
1602 {
1603 STAM_COUNTER_INC(&gStatRefuseCode16);
1604 Log2(("raw r0 mode refused: HF_[S|C]S32_MASK fFlags=%#x\n", fFlags));
1605 return false;
1606 }
1607
1608 if (EMIsRawRing1Enabled(env->pVM))
1609 {
1610 /* Only ring 0 and 1 supervisor code. */
1611 if (((fFlags >> HF_CPL_SHIFT) & 3) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1612 {
1613 Log2(("raw r0 mode refused: CPL %d\n", (fFlags >> HF_CPL_SHIFT) & 3));
1614 return false;
1615 }
1616 }
1617 /* Only R0. */
1618 else if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1619 {
1620 STAM_COUNTER_INC(&gStatRefuseRing1or2);
1621 Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1622 return false;
1623 }
1624
1625 if (!(u32CR0 & CR0_WP_MASK))
1626 {
1627 STAM_COUNTER_INC(&gStatRefuseWP0);
1628 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1629 return false;
1630 }
1631
1632#ifdef VBOX_WITH_RAW_MODE
1633 if (PATMIsPatchGCAddr(env->pVM, eip))
1634 {
1635 Log2(("raw r0 mode forced: patch code\n"));
1636 *piException = EXCP_EXECUTE_RAW;
1637 return true;
1638 }
1639#endif
1640
1641#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1642 if (!(env->eflags & IF_MASK))
1643 {
1644 STAM_COUNTER_INC(&gStatRefuseIF0);
1645 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1646 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1647 return false;
1648 }
1649#endif
1650
1651#ifndef VBOX_WITH_RAW_RING1
1652 if (((env->eflags >> IOPL_SHIFT) & 3) != 0)
1653 {
1654 Log2(("raw r0 mode refused: IOPL %d\n", ((env->eflags >> IOPL_SHIFT) & 3)));
1655 return false;
1656 }
1657#endif
1658 env->state |= CPU_RAW_RING0;
1659 }
1660
1661 /*
1662 * Don't reschedule the first time we're called, because there might be
1663 * special reasons why we're here that is not covered by the above checks.
1664 */
1665 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1666 {
1667 Log2(("raw mode refused: first scheduling\n"));
1668 STAM_COUNTER_INC(&gStatRefuseCanExecute);
1669 return false;
1670 }
1671
1672 /*
1673 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1674 */
1675 if (env->segs[R_CS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1676 {
1677 Log2(("raw mode refused: stale CS (%#x)\n", env->segs[R_CS].selector));
1678 STAM_COUNTER_INC(&gaStatRefuseStale[R_CS]);
1679 return false;
1680 }
1681 if (env->segs[R_SS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1682 {
1683 Log2(("raw mode refused: stale SS (%#x)\n", env->segs[R_SS].selector));
1684 STAM_COUNTER_INC(&gaStatRefuseStale[R_SS]);
1685 return false;
1686 }
1687 if (env->segs[R_DS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1688 {
1689 Log2(("raw mode refused: stale DS (%#x)\n", env->segs[R_DS].selector));
1690 STAM_COUNTER_INC(&gaStatRefuseStale[R_DS]);
1691 return false;
1692 }
1693 if (env->segs[R_ES].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1694 {
1695 Log2(("raw mode refused: stale ES (%#x)\n", env->segs[R_ES].selector));
1696 STAM_COUNTER_INC(&gaStatRefuseStale[R_ES]);
1697 return false;
1698 }
1699 if (env->segs[R_FS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1700 {
1701 Log2(("raw mode refused: stale FS (%#x)\n", env->segs[R_FS].selector));
1702 STAM_COUNTER_INC(&gaStatRefuseStale[R_FS]);
1703 return false;
1704 }
1705 if (env->segs[R_GS].fVBoxFlags & CPUMSELREG_FLAGS_STALE)
1706 {
1707 Log2(("raw mode refused: stale GS (%#x)\n", env->segs[R_GS].selector));
1708 STAM_COUNTER_INC(&gaStatRefuseStale[R_GS]);
1709 return false;
1710 }
1711
1712/* Assert(env->pVCpu && PGMPhysIsA20Enabled(env->pVCpu));*/
1713 *piException = EXCP_EXECUTE_RAW;
1714 return true;
1715}
1716
1717
1718#ifdef VBOX_WITH_RAW_MODE
1719/**
1720 * Fetches a code byte.
1721 *
1722 * @returns Success indicator (bool) for ease of use.
1723 * @param env The CPU environment structure.
1724 * @param GCPtrInstr Where to fetch code.
1725 * @param pu8Byte Where to store the byte on success
1726 */
1727bool remR3GetOpcode(CPUX86State *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte)
1728{
1729 int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1730 if (RT_SUCCESS(rc))
1731 return true;
1732 return false;
1733}
1734#endif /* VBOX_WITH_RAW_MODE */
1735
1736
1737/**
1738 * Flush (or invalidate if you like) page table/dir entry.
1739 *
1740 * (invlpg instruction; tlb_flush_page)
1741 *
1742 * @param env Pointer to cpu environment.
1743 * @param GCPtr The virtual address which page table/dir entry should be invalidated.
1744 */
1745void remR3FlushPage(CPUX86State *env, RTGCPTR GCPtr)
1746{
1747 PVM pVM = env->pVM;
1748 PCPUMCTX pCtx;
1749 int rc;
1750
1751 Assert(EMRemIsLockOwner(env->pVM));
1752
1753 /*
1754 * When we're replaying invlpg instructions or restoring a saved
1755 * state we disable this path.
1756 */
1757 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.cIgnoreAll)
1758 return;
1759 LogFlow(("remR3FlushPage: GCPtr=%RGv\n", GCPtr));
1760 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1761
1762 //RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1763
1764 /*
1765 * Update the control registers before calling PGMFlushPage.
1766 */
1767 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1768 Assert(pCtx);
1769 pCtx->cr0 = env->cr[0];
1770 pCtx->cr3 = env->cr[3];
1771#ifdef VBOX_WITH_RAW_MODE
1772 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1773 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1774#endif
1775 pCtx->cr4 = env->cr[4];
1776
1777 /*
1778 * Let PGM do the rest.
1779 */
1780 Assert(env->pVCpu);
1781 rc = PGMInvalidatePage(env->pVCpu, GCPtr);
1782 if (RT_FAILURE(rc))
1783 {
1784 AssertMsgFailed(("remR3FlushPage %RGv failed with %d!!\n", GCPtr, rc));
1785 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1786 }
1787 //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1788}
1789
1790
1791#ifndef REM_PHYS_ADDR_IN_TLB
1792/** Wrapper for PGMR3PhysTlbGCPhys2Ptr. */
1793void *remR3TlbGCPhys2Ptr(CPUX86State *env1, target_ulong physAddr, int fWritable)
1794{
1795 void *pv;
1796 int rc;
1797
1798
1799 /* Address must be aligned enough to fiddle with lower bits */
1800 Assert((physAddr & 0x3) == 0);
1801 /*AssertMsg((env1->a20_mask & physAddr) == physAddr, ("%llx\n", (uint64_t)physAddr));*/
1802
1803 STAM_PROFILE_START(&gStatGCPhys2HCVirt, a);
1804 rc = PGMR3PhysTlbGCPhys2Ptr(env1->pVM, physAddr, true /*fWritable*/, &pv);
1805 STAM_PROFILE_STOP(&gStatGCPhys2HCVirt, a);
1806 Assert( rc == VINF_SUCCESS
1807 || rc == VINF_PGM_PHYS_TLB_CATCH_WRITE
1808 || rc == VERR_PGM_PHYS_TLB_CATCH_ALL
1809 || rc == VERR_PGM_PHYS_TLB_UNASSIGNED);
1810 if (RT_FAILURE(rc))
1811 return (void *)1;
1812 if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
1813 return (void *)((uintptr_t)pv | 2);
1814 return pv;
1815}
1816#endif /* REM_PHYS_ADDR_IN_TLB */
1817
1818
1819/**
1820 * Called from tlb_protect_code in order to write monitor a code page.
1821 *
1822 * @param env Pointer to the CPU environment.
1823 * @param GCPtr Code page to monitor
1824 */
1825void remR3ProtectCode(CPUX86State *env, RTGCPTR GCPtr)
1826{
1827#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1828 Assert(env->pVM->rem.s.fInREM);
1829 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1830 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1831 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1832 && !(env->eflags & VM_MASK) /* no V86 mode */
1833 && !HMIsEnabled(env->pVM))
1834 CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1835#endif
1836}
1837
1838
1839/**
1840 * Called from tlb_unprotect_code in order to clear write monitoring for a code page.
1841 *
1842 * @param env Pointer to the CPU environment.
1843 * @param GCPtr Code page to monitor
1844 */
1845void remR3UnprotectCode(CPUX86State *env, RTGCPTR GCPtr)
1846{
1847 Assert(env->pVM->rem.s.fInREM);
1848#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1849 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1850 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1851 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1852 && !(env->eflags & VM_MASK) /* no V86 mode */
1853 && !HMIsEnabled(env->pVM))
1854 CSAMR3UnmonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1855#endif
1856}
1857
1858
1859/**
1860 * Called when the CPU is initialized, any of the CRx registers are changed or
1861 * when the A20 line is modified.
1862 *
1863 * @param env Pointer to the CPU environment.
1864 * @param fGlobal Set if the flush is global.
1865 */
1866void remR3FlushTLB(CPUX86State *env, bool fGlobal)
1867{
1868 PVM pVM = env->pVM;
1869 PCPUMCTX pCtx;
1870 Assert(EMRemIsLockOwner(pVM));
1871
1872 /*
1873 * When we're replaying invlpg instructions or restoring a saved
1874 * state we disable this path.
1875 */
1876 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.cIgnoreAll)
1877 return;
1878 Assert(pVM->rem.s.fInREM);
1879
1880 /*
1881 * The caller doesn't check cr4, so we have to do that for ourselves.
1882 */
1883 if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1884 fGlobal = true;
1885 Log(("remR3FlushTLB: CR0=%08RX64 CR3=%08RX64 CR4=%08RX64 %s\n", (uint64_t)env->cr[0], (uint64_t)env->cr[3], (uint64_t)env->cr[4], fGlobal ? " global" : ""));
1886
1887 /*
1888 * Update the control registers before calling PGMR3FlushTLB.
1889 */
1890 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1891 Assert(pCtx);
1892 pCtx->cr0 = env->cr[0];
1893 pCtx->cr3 = env->cr[3];
1894#ifdef VBOX_WITH_RAW_MODE
1895 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1896 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1897#endif
1898 pCtx->cr4 = env->cr[4];
1899
1900 /*
1901 * Let PGM do the rest.
1902 */
1903 Assert(env->pVCpu);
1904 PGMFlushTLB(env->pVCpu, env->cr[3], fGlobal);
1905}
1906
1907
1908/**
1909 * Called when any of the cr0, cr4 or efer registers is updated.
1910 *
1911 * @param env Pointer to the CPU environment.
1912 */
1913void remR3ChangeCpuMode(CPUX86State *env)
1914{
1915 PVM pVM = env->pVM;
1916 uint64_t efer;
1917 PCPUMCTX pCtx;
1918 int rc;
1919
1920 /*
1921 * When we're replaying loads or restoring a saved
1922 * state this path is disabled.
1923 */
1924 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.cIgnoreAll)
1925 return;
1926 Assert(pVM->rem.s.fInREM);
1927
1928 pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1929 Assert(pCtx);
1930
1931 /*
1932 * Notify PGM about WP0 being enabled (like CPUSetGuestCR0 does).
1933 */
1934 if (((env->cr[0] ^ pCtx->cr0) & X86_CR0_WP) && (env->cr[0] & X86_CR0_WP))
1935 PGMCr0WpEnabled(env->pVCpu);
1936
1937 /*
1938 * Update the control registers before calling PGMChangeMode()
1939 * as it may need to map whatever cr3 is pointing to.
1940 */
1941 pCtx->cr0 = env->cr[0];
1942 pCtx->cr3 = env->cr[3];
1943#ifdef VBOX_WITH_RAW_MODE
1944 if (((env->cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
1945 VMCPU_FF_SET(env->pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1946#endif
1947 pCtx->cr4 = env->cr[4];
1948#ifdef TARGET_X86_64
1949 efer = env->efer;
1950 pCtx->msrEFER = efer;
1951#else
1952 efer = 0;
1953#endif
1954 Assert(env->pVCpu);
1955 rc = PGMChangeMode(env->pVCpu, env->cr[0], env->cr[4], efer);
1956 if (rc != VINF_SUCCESS)
1957 {
1958 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1959 {
1960 Log(("PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc -> remR3RaiseRC\n", env->cr[0], env->cr[4], efer, rc));
1961 remR3RaiseRC(env->pVM, rc);
1962 }
1963 else
1964 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], efer, rc);
1965 }
1966}
1967
1968
1969/**
1970 * Called from compiled code to run dma.
1971 *
1972 * @param env Pointer to the CPU environment.
1973 */
1974void remR3DmaRun(CPUX86State *env)
1975{
1976 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1977 PDMR3DmaRun(env->pVM);
1978 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1979}
1980
1981
1982/**
1983 * Called from compiled code to schedule pending timers in VMM
1984 *
1985 * @param env Pointer to the CPU environment.
1986 */
1987void remR3TimersRun(CPUX86State *env)
1988{
1989 LogFlow(("remR3TimersRun:\n"));
1990 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("remR3TimersRun\n"));
1991 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1992 remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1993 TMR3TimerQueuesDo(env->pVM);
1994 remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1995 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1996}
1997
1998
1999/**
2000 * Record trap occurrence
2001 *
2002 * @returns VBox status code
2003 * @param env Pointer to the CPU environment.
2004 * @param uTrap Trap nr
2005 * @param uErrorCode Error code
2006 * @param pvNextEIP Next EIP
2007 */
2008int remR3NotifyTrap(CPUX86State *env, uint32_t uTrap, uint32_t uErrorCode, RTGCPTR pvNextEIP)
2009{
2010 PVM pVM = env->pVM;
2011#ifdef VBOX_WITH_STATISTICS
2012 static STAMCOUNTER s_aStatTrap[255];
2013 static bool s_aRegisters[RT_ELEMENTS(s_aStatTrap)];
2014#endif
2015
2016#ifdef VBOX_WITH_STATISTICS
2017 if (uTrap < 255)
2018 {
2019 if (!s_aRegisters[uTrap])
2020 {
2021 char szStatName[64];
2022 s_aRegisters[uTrap] = true;
2023 RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
2024 STAM_REG(env->pVM, &s_aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
2025 }
2026 STAM_COUNTER_INC(&s_aStatTrap[uTrap]);
2027 }
2028#endif
2029 Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
2030 if( uTrap < 0x20
2031 && (env->cr[0] & X86_CR0_PE)
2032 && !(env->eflags & X86_EFL_VM))
2033 {
2034#ifdef DEBUG
2035 remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
2036#endif
2037 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
2038 {
2039 LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
2040 remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
2041 return VERR_REM_TOO_MANY_TRAPS;
2042 }
2043 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
2044 {
2045 Log(("remR3NotifyTrap: uTrap=%#x set as pending\n", uTrap));
2046 pVM->rem.s.cPendingExceptions = 1;
2047 }
2048 pVM->rem.s.uPendingException = uTrap;
2049 pVM->rem.s.uPendingExcptEIP = env->eip;
2050 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2051 }
2052 else
2053 {
2054 pVM->rem.s.cPendingExceptions = 0;
2055 pVM->rem.s.uPendingException = uTrap;
2056 pVM->rem.s.uPendingExcptEIP = env->eip;
2057 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
2058 }
2059 return VINF_SUCCESS;
2060}
2061
2062
2063/*
2064 * Clear current active trap
2065 *
2066 * @param pVM VM Handle.
2067 */
2068void remR3TrapClear(PVM pVM)
2069{
2070 pVM->rem.s.cPendingExceptions = 0;
2071 pVM->rem.s.uPendingException = 0;
2072 pVM->rem.s.uPendingExcptEIP = 0;
2073 pVM->rem.s.uPendingExcptCR2 = 0;
2074}
2075
2076
2077/*
2078 * Record previous call instruction addresses
2079 *
2080 * @param env Pointer to the CPU environment.
2081 */
2082void remR3RecordCall(CPUX86State *env)
2083{
2084#ifdef VBOX_WITH_RAW_MODE
2085 CSAMR3RecordCallAddress(env->pVM, env->eip);
2086#endif
2087}
2088
2089
2090/**
2091 * Syncs the internal REM state with the VM.
2092 *
2093 * This must be called before REMR3Run() is invoked whenever when the REM
2094 * state is not up to date. Calling it several times in a row is not
2095 * permitted.
2096 *
2097 * @returns VBox status code.
2098 *
2099 * @param pVM VM Handle.
2100 * @param pVCpu VMCPU Handle.
2101 *
2102 * @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
2103 * no do this since the majority of the callers don't want any unnecessary of events
2104 * pending that would immediately interrupt execution.
2105 */
2106REMR3DECL(int) REMR3State(PVM pVM, PVMCPU pVCpu)
2107{
2108 register const CPUMCTX *pCtx;
2109 register unsigned fFlags;
2110 unsigned i;
2111 TRPMEVENT enmType;
2112 uint8_t u8TrapNo;
2113 uint32_t uCpl;
2114 int rc;
2115
2116 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
2117 Log2(("REMR3State:\n"));
2118
2119 pVM->rem.s.Env.pVCpu = pVCpu;
2120 pCtx = pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2121
2122 Assert(!pVM->rem.s.fInREM);
2123 pVM->rem.s.fInStateSync = true;
2124
2125 /*
2126 * If we have to flush TBs, do that immediately.
2127 */
2128 if (pVM->rem.s.fFlushTBs)
2129 {
2130 STAM_COUNTER_INC(&gStatFlushTBs);
2131 tb_flush(&pVM->rem.s.Env);
2132 pVM->rem.s.fFlushTBs = false;
2133 }
2134
2135 /*
2136 * Copy the registers which require no special handling.
2137 */
2138#ifdef TARGET_X86_64
2139 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2140 Assert(R_EAX == 0);
2141 pVM->rem.s.Env.regs[R_EAX] = pCtx->rax;
2142 Assert(R_ECX == 1);
2143 pVM->rem.s.Env.regs[R_ECX] = pCtx->rcx;
2144 Assert(R_EDX == 2);
2145 pVM->rem.s.Env.regs[R_EDX] = pCtx->rdx;
2146 Assert(R_EBX == 3);
2147 pVM->rem.s.Env.regs[R_EBX] = pCtx->rbx;
2148 Assert(R_ESP == 4);
2149 pVM->rem.s.Env.regs[R_ESP] = pCtx->rsp;
2150 Assert(R_EBP == 5);
2151 pVM->rem.s.Env.regs[R_EBP] = pCtx->rbp;
2152 Assert(R_ESI == 6);
2153 pVM->rem.s.Env.regs[R_ESI] = pCtx->rsi;
2154 Assert(R_EDI == 7);
2155 pVM->rem.s.Env.regs[R_EDI] = pCtx->rdi;
2156 pVM->rem.s.Env.regs[8] = pCtx->r8;
2157 pVM->rem.s.Env.regs[9] = pCtx->r9;
2158 pVM->rem.s.Env.regs[10] = pCtx->r10;
2159 pVM->rem.s.Env.regs[11] = pCtx->r11;
2160 pVM->rem.s.Env.regs[12] = pCtx->r12;
2161 pVM->rem.s.Env.regs[13] = pCtx->r13;
2162 pVM->rem.s.Env.regs[14] = pCtx->r14;
2163 pVM->rem.s.Env.regs[15] = pCtx->r15;
2164
2165 pVM->rem.s.Env.eip = pCtx->rip;
2166
2167 pVM->rem.s.Env.eflags = pCtx->rflags.u64;
2168#else
2169 Assert(R_EAX == 0);
2170 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
2171 Assert(R_ECX == 1);
2172 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
2173 Assert(R_EDX == 2);
2174 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
2175 Assert(R_EBX == 3);
2176 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
2177 Assert(R_ESP == 4);
2178 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
2179 Assert(R_EBP == 5);
2180 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
2181 Assert(R_ESI == 6);
2182 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
2183 Assert(R_EDI == 7);
2184 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
2185 pVM->rem.s.Env.eip = pCtx->eip;
2186
2187 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
2188#endif
2189
2190 pVM->rem.s.Env.cr[2] = pCtx->cr2;
2191
2192 /** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
2193 for (i=0;i<8;i++)
2194 pVM->rem.s.Env.dr[i] = pCtx->dr[i];
2195
2196#ifdef HF_HALTED_MASK /** @todo remove me when we're up to date again. */
2197 /*
2198 * Clear the halted hidden flag (the interrupt waking up the CPU can
2199 * have been dispatched in raw mode).
2200 */
2201 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
2202#endif
2203
2204 /*
2205 * Replay invlpg? Only if we're not flushing the TLB.
2206 */
2207 fFlags = CPUMR3RemEnter(pVCpu, &uCpl);
2208 LogFlow(("CPUMR3RemEnter %x %x\n", fFlags, uCpl));
2209 if (pVM->rem.s.cInvalidatedPages)
2210 {
2211 if (!(fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH))
2212 {
2213 RTUINT i;
2214
2215 pVM->rem.s.fIgnoreCR3Load = true;
2216 pVM->rem.s.fIgnoreInvlPg = true;
2217 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2218 {
2219 Log2(("REMR3State: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2220 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2221 }
2222 pVM->rem.s.fIgnoreInvlPg = false;
2223 pVM->rem.s.fIgnoreCR3Load = false;
2224 }
2225 pVM->rem.s.cInvalidatedPages = 0;
2226 }
2227
2228 /* Replay notification changes. */
2229 REMR3ReplayHandlerNotifications(pVM);
2230
2231 /* Update MSRs; before CRx registers! */
2232 pVM->rem.s.Env.efer = pCtx->msrEFER;
2233 pVM->rem.s.Env.star = pCtx->msrSTAR;
2234 pVM->rem.s.Env.pat = pCtx->msrPAT;
2235#ifdef TARGET_X86_64
2236 pVM->rem.s.Env.lstar = pCtx->msrLSTAR;
2237 pVM->rem.s.Env.cstar = pCtx->msrCSTAR;
2238 pVM->rem.s.Env.fmask = pCtx->msrSFMASK;
2239 pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
2240
2241 /* Update the internal long mode activate flag according to the new EFER value. */
2242 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
2243 pVM->rem.s.Env.hflags |= HF_LMA_MASK;
2244 else
2245 pVM->rem.s.Env.hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
2246#endif
2247
2248 /* Update the inhibit IRQ mask. */
2249 pVM->rem.s.Env.hflags &= ~HF_INHIBIT_IRQ_MASK;
2250 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2251 {
2252 RTGCPTR InhibitPC = EMGetInhibitInterruptsPC(pVCpu);
2253 if (InhibitPC == pCtx->rip)
2254 pVM->rem.s.Env.hflags |= HF_INHIBIT_IRQ_MASK;
2255 else
2256 {
2257 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#1)\n", (RTGCPTR)pCtx->rip, InhibitPC));
2258 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2259 }
2260 }
2261
2262 /* Update the inhibit NMI mask. */
2263 pVM->rem.s.Env.hflags2 &= ~HF2_NMI_MASK;
2264 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2265 pVM->rem.s.Env.hflags2 |= HF2_NMI_MASK;
2266
2267 /*
2268 * Sync the A20 gate.
2269 */
2270 bool fA20State = PGMPhysIsA20Enabled(pVCpu);
2271 if (fA20State != RT_BOOL(pVM->rem.s.Env.a20_mask & RT_BIT(20)))
2272 {
2273 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
2274 cpu_x86_set_a20(&pVM->rem.s.Env, fA20State);
2275 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
2276 }
2277
2278 /*
2279 * Registers which are rarely changed and require special handling / order when changed.
2280 */
2281 if (fFlags & ( CPUM_CHANGED_GLOBAL_TLB_FLUSH
2282 | CPUM_CHANGED_CR4
2283 | CPUM_CHANGED_CR0
2284 | CPUM_CHANGED_CR3
2285 | CPUM_CHANGED_GDTR
2286 | CPUM_CHANGED_IDTR
2287 | CPUM_CHANGED_SYSENTER_MSR
2288 | CPUM_CHANGED_LDTR
2289 | CPUM_CHANGED_CPUID
2290 | CPUM_CHANGED_FPU_REM
2291 )
2292 )
2293 {
2294 if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
2295 {
2296 pVM->rem.s.fIgnoreCR3Load = true;
2297 tlb_flush(&pVM->rem.s.Env, true);
2298 pVM->rem.s.fIgnoreCR3Load = false;
2299 }
2300
2301 /* CR4 before CR0! */
2302 if (fFlags & CPUM_CHANGED_CR4)
2303 {
2304 pVM->rem.s.fIgnoreCR3Load = true;
2305 pVM->rem.s.fIgnoreCpuMode = true;
2306 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
2307 pVM->rem.s.fIgnoreCpuMode = false;
2308 pVM->rem.s.fIgnoreCR3Load = false;
2309 }
2310
2311 if (fFlags & CPUM_CHANGED_CR0)
2312 {
2313 pVM->rem.s.fIgnoreCR3Load = true;
2314 pVM->rem.s.fIgnoreCpuMode = true;
2315 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
2316 pVM->rem.s.fIgnoreCpuMode = false;
2317 pVM->rem.s.fIgnoreCR3Load = false;
2318 }
2319
2320 if (fFlags & CPUM_CHANGED_CR3)
2321 {
2322 pVM->rem.s.fIgnoreCR3Load = true;
2323 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
2324 pVM->rem.s.fIgnoreCR3Load = false;
2325 }
2326
2327 if (fFlags & CPUM_CHANGED_GDTR)
2328 {
2329 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
2330 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
2331 }
2332
2333 if (fFlags & CPUM_CHANGED_IDTR)
2334 {
2335 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
2336 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
2337 }
2338
2339 if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
2340 {
2341 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
2342 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
2343 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
2344 }
2345
2346 if (fFlags & CPUM_CHANGED_LDTR)
2347 {
2348 if (pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2349 {
2350 pVM->rem.s.Env.ldt.selector = pCtx->ldtr.Sel;
2351 pVM->rem.s.Env.ldt.newselector = 0;
2352 pVM->rem.s.Env.ldt.fVBoxFlags = pCtx->ldtr.fFlags;
2353 pVM->rem.s.Env.ldt.base = pCtx->ldtr.u64Base;
2354 pVM->rem.s.Env.ldt.limit = pCtx->ldtr.u32Limit;
2355 pVM->rem.s.Env.ldt.flags = (pCtx->ldtr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2356 }
2357 else
2358 {
2359 AssertFailed(); /* Shouldn't happen, see cpumR3LoadExec. */
2360 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr.Sel);
2361 }
2362 }
2363
2364 if (fFlags & CPUM_CHANGED_CPUID)
2365 {
2366 uint32_t u32Dummy;
2367
2368 /*
2369 * Get the CPUID features.
2370 */
2371 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
2372 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
2373 }
2374
2375 /* Sync FPU state after CR4, CPUID and EFER (!). */
2376 if (fFlags & CPUM_CHANGED_FPU_REM)
2377 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87); /* 'save' is an excellent name. */
2378 }
2379
2380 /*
2381 * Sync TR unconditionally to make life simpler.
2382 */
2383 pVM->rem.s.Env.tr.selector = pCtx->tr.Sel;
2384 pVM->rem.s.Env.tr.newselector = 0;
2385 pVM->rem.s.Env.tr.fVBoxFlags = pCtx->tr.fFlags;
2386 pVM->rem.s.Env.tr.base = pCtx->tr.u64Base;
2387 pVM->rem.s.Env.tr.limit = pCtx->tr.u32Limit;
2388 pVM->rem.s.Env.tr.flags = (pCtx->tr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT;
2389 /* Note! do_interrupt will fault if the busy flag is still set... */ /** @todo so fix do_interrupt then! */
2390 pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
2391
2392 /*
2393 * Update selector registers.
2394 *
2395 * This must be done *after* we've synced gdt, ldt and crX registers
2396 * since we're reading the GDT/LDT om sync_seg. This will happen with
2397 * saved state which takes a quick dip into rawmode for instance.
2398 *
2399 * CPL/Stack; Note first check this one as the CPL might have changed.
2400 * The wrong CPL can cause QEmu to raise an exception in sync_seg!!
2401 */
2402 cpu_x86_set_cpl(&pVM->rem.s.Env, uCpl);
2403 /* Note! QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
2404#define SYNC_IN_SREG(a_pEnv, a_SReg, a_pRemSReg, a_pVBoxSReg) \
2405 do \
2406 { \
2407 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, a_pVBoxSReg)) \
2408 { \
2409 cpu_x86_load_seg_cache(a_pEnv, R_##a_SReg, \
2410 (a_pVBoxSReg)->Sel, \
2411 (a_pVBoxSReg)->u64Base, \
2412 (a_pVBoxSReg)->u32Limit, \
2413 ((a_pVBoxSReg)->Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT); \
2414 (a_pRemSReg)->fVBoxFlags = (a_pVBoxSReg)->fFlags; \
2415 } \
2416 /* This only-reload-if-changed stuff is the old approach, we should ditch it. */ \
2417 else if ((a_pRemSReg)->selector != (a_pVBoxSReg)->Sel) \
2418 { \
2419 Log2(("REMR3State: " #a_SReg " changed from %04x to %04x!\n", \
2420 (a_pRemSReg)->selector, (a_pVBoxSReg)->Sel)); \
2421 sync_seg(a_pEnv, R_##a_SReg, (a_pVBoxSReg)->Sel); \
2422 if ((a_pRemSReg)->newselector) \
2423 STAM_COUNTER_INC(&gStatSelOutOfSync[R_##a_SReg]); \
2424 } \
2425 else \
2426 (a_pRemSReg)->newselector = 0; \
2427 } while (0)
2428
2429 SYNC_IN_SREG(&pVM->rem.s.Env, CS, &pVM->rem.s.Env.segs[R_CS], &pCtx->cs);
2430 SYNC_IN_SREG(&pVM->rem.s.Env, SS, &pVM->rem.s.Env.segs[R_SS], &pCtx->ss);
2431 SYNC_IN_SREG(&pVM->rem.s.Env, DS, &pVM->rem.s.Env.segs[R_DS], &pCtx->ds);
2432 SYNC_IN_SREG(&pVM->rem.s.Env, ES, &pVM->rem.s.Env.segs[R_ES], &pCtx->es);
2433 SYNC_IN_SREG(&pVM->rem.s.Env, FS, &pVM->rem.s.Env.segs[R_FS], &pCtx->fs);
2434 SYNC_IN_SREG(&pVM->rem.s.Env, GS, &pVM->rem.s.Env.segs[R_GS], &pCtx->gs);
2435 /** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
2436 * be the same but not the base/limit. */
2437
2438 /*
2439 * Check for traps.
2440 */
2441 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
2442 rc = TRPMQueryTrap(pVCpu, &u8TrapNo, &enmType);
2443 if (RT_SUCCESS(rc))
2444 {
2445#ifdef DEBUG
2446 if (u8TrapNo == 0x80)
2447 {
2448 remR3DumpLnxSyscall(pVCpu);
2449 remR3DumpOBsdSyscall(pVCpu);
2450 }
2451#endif
2452
2453 pVM->rem.s.Env.exception_index = u8TrapNo;
2454 if (enmType != TRPM_SOFTWARE_INT)
2455 {
2456 pVM->rem.s.Env.exception_is_int = enmType == TRPM_HARDWARE_INT
2457 ? EXCEPTION_IS_INT_VALUE_HARDWARE_IRQ : 0; /* HACK ALERT! */
2458 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
2459 }
2460 else
2461 {
2462 /*
2463 * The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
2464 * We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
2465 * for int03 and into.
2466 */
2467 pVM->rem.s.Env.exception_is_int = 1;
2468 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 2;
2469 /* int 3 may be generated by one-byte 0xcc */
2470 if (u8TrapNo == 3)
2471 {
2472 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xcc)
2473 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2474 }
2475 /* int 4 may be generated by one-byte 0xce */
2476 else if (u8TrapNo == 4)
2477 {
2478 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xce)
2479 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2480 }
2481 }
2482
2483 /* get error code and cr2 if needed. */
2484 if (enmType == TRPM_TRAP)
2485 {
2486 switch (u8TrapNo)
2487 {
2488 case X86_XCPT_PF:
2489 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVCpu);
2490 /* fallthru */
2491 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP:
2492 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVCpu);
2493 break;
2494
2495 case X86_XCPT_AC: case X86_XCPT_DF:
2496 default:
2497 pVM->rem.s.Env.error_code = 0;
2498 break;
2499 }
2500 }
2501 else
2502 pVM->rem.s.Env.error_code = 0;
2503
2504 /*
2505 * We can now reset the active trap since the recompiler is gonna have a go at it.
2506 */
2507 rc = TRPMResetTrap(pVCpu);
2508 AssertRC(rc);
2509 Log2(("REMR3State: trap=%02x errcd=%RGv cr2=%RGv nexteip=%RGv%s\n", pVM->rem.s.Env.exception_index, (RTGCPTR)pVM->rem.s.Env.error_code,
2510 (RTGCPTR)pVM->rem.s.Env.cr[2], (RTGCPTR)pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
2511 }
2512
2513 /*
2514 * Clear old interrupt request flags; Check for pending hardware interrupts.
2515 * (See @remark for why we don't check for other FFs.)
2516 */
2517 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
2518#ifdef VBOX_WITH_NEW_APIC
2519 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2520 APICUpdatePendingInterrupts(pVCpu);
2521#endif
2522 if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
2523 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2524 {
2525 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
2526 }
2527
2528 /*
2529 * We're now in REM mode.
2530 */
2531 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_REM);
2532 pVM->rem.s.fInREM = true;
2533 pVM->rem.s.fInStateSync = false;
2534 pVM->rem.s.cCanExecuteRaw = 0;
2535 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
2536 Log2(("REMR3State: returns VINF_SUCCESS\n"));
2537 return VINF_SUCCESS;
2538}
2539
2540
2541/**
2542 * Syncs back changes in the REM state to the the VM state.
2543 *
2544 * This must be called after invoking REMR3Run().
2545 * Calling it several times in a row is not permitted.
2546 *
2547 * @returns VBox status code.
2548 *
2549 * @param pVM VM Handle.
2550 * @param pVCpu VMCPU Handle.
2551 */
2552REMR3DECL(int) REMR3StateBack(PVM pVM, PVMCPU pVCpu)
2553{
2554 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2555 Assert(pCtx);
2556 unsigned i;
2557
2558 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2559 Log2(("REMR3StateBack:\n"));
2560 Assert(pVM->rem.s.fInREM);
2561
2562 /*
2563 * Copy back the registers.
2564 * This is done in the order they are declared in the CPUMCTX structure.
2565 */
2566
2567 /** @todo FOP */
2568 /** @todo FPUIP */
2569 /** @todo CS */
2570 /** @todo FPUDP */
2571 /** @todo DS */
2572
2573 /** @todo check if FPU/XMM was actually used in the recompiler */
2574 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->pXStateR3->x87);
2575//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2576
2577#ifdef TARGET_X86_64
2578 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2579 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2580 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2581 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2582 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2583 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2584 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2585 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2586 pCtx->r8 = pVM->rem.s.Env.regs[8];
2587 pCtx->r9 = pVM->rem.s.Env.regs[9];
2588 pCtx->r10 = pVM->rem.s.Env.regs[10];
2589 pCtx->r11 = pVM->rem.s.Env.regs[11];
2590 pCtx->r12 = pVM->rem.s.Env.regs[12];
2591 pCtx->r13 = pVM->rem.s.Env.regs[13];
2592 pCtx->r14 = pVM->rem.s.Env.regs[14];
2593 pCtx->r15 = pVM->rem.s.Env.regs[15];
2594
2595 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2596
2597#else
2598 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2599 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2600 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2601 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2602 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2603 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2604 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2605
2606 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2607#endif
2608
2609#define SYNC_BACK_SREG(a_sreg, a_SREG) \
2610 do \
2611 { \
2612 pCtx->a_sreg.Sel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2613 if (!pVM->rem.s.Env.segs[R_SS].newselector) \
2614 { \
2615 pCtx->a_sreg.ValidSel = pVM->rem.s.Env.segs[R_##a_SREG].selector; \
2616 pCtx->a_sreg.fFlags = CPUMSELREG_FLAGS_VALID; \
2617 pCtx->a_sreg.u64Base = pVM->rem.s.Env.segs[R_##a_SREG].base; \
2618 pCtx->a_sreg.u32Limit = pVM->rem.s.Env.segs[R_##a_SREG].limit; \
2619 /* Note! QEmu saves the 2nd dword of the descriptor; we (VT-x/AMD-V) keep only the attributes! */ \
2620 pCtx->a_sreg.Attr.u = (pVM->rem.s.Env.segs[R_##a_SREG].flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK; \
2621 } \
2622 else \
2623 { \
2624 pCtx->a_sreg.fFlags = 0; \
2625 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_##a_SREG]); \
2626 } \
2627 } while (0)
2628
2629 SYNC_BACK_SREG(es, ES);
2630 SYNC_BACK_SREG(cs, CS);
2631 SYNC_BACK_SREG(ss, SS);
2632 SYNC_BACK_SREG(ds, DS);
2633 SYNC_BACK_SREG(fs, FS);
2634 SYNC_BACK_SREG(gs, GS);
2635
2636#ifdef TARGET_X86_64
2637 pCtx->rip = pVM->rem.s.Env.eip;
2638 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2639#else
2640 pCtx->eip = pVM->rem.s.Env.eip;
2641 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2642#endif
2643
2644 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2645 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2646 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2647#ifdef VBOX_WITH_RAW_MODE
2648 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2649 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2650#endif
2651 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2652
2653 for (i = 0; i < 8; i++)
2654 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2655
2656 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2657 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base)
2658 {
2659 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base;
2660 STAM_COUNTER_INC(&gStatREMGDTChange);
2661#ifdef VBOX_WITH_RAW_MODE
2662 if (!HMIsEnabled(pVM))
2663 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2664#endif
2665 }
2666
2667 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2668 if (pCtx->idtr.pIdt != pVM->rem.s.Env.idt.base)
2669 {
2670 pCtx->idtr.pIdt = pVM->rem.s.Env.idt.base;
2671 STAM_COUNTER_INC(&gStatREMIDTChange);
2672#ifdef VBOX_WITH_RAW_MODE
2673 if (!HMIsEnabled(pVM))
2674 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2675#endif
2676 }
2677
2678 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2679 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2680 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2681 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2682 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2683 || !(pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2684 )
2685 {
2686 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2687 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2688 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2689 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2690 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2691 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2692 STAM_COUNTER_INC(&gStatREMLDTRChange);
2693#ifdef VBOX_WITH_RAW_MODE
2694 if (!HMIsEnabled(pVM))
2695 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2696#endif
2697 }
2698
2699 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2700 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2701 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2702 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2703 /* Qemu and AMD/Intel have different ideas about the busy flag ... */ /** @todo just fix qemu! */
2704 || pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2705 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
2706 : 0)
2707 || !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
2708 )
2709 {
2710 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2711 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2712 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2713 (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2714 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT : 0));
2715 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2716 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2717 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2718 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2719 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2720 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2721 if (pCtx->tr.Attr.u & ~DESC_INTEL_UNUSABLE)
2722 pCtx->tr.Attr.u |= DESC_TSS_BUSY_MASK >> SEL_FLAGS_SHIFT;
2723 STAM_COUNTER_INC(&gStatREMTRChange);
2724#ifdef VBOX_WITH_RAW_MODE
2725 if (!HMIsEnabled(pVM))
2726 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2727#endif
2728 }
2729
2730 /* Sysenter MSR */
2731 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2732 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2733 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2734
2735 /* System MSRs. */
2736 pCtx->msrEFER = pVM->rem.s.Env.efer;
2737 pCtx->msrSTAR = pVM->rem.s.Env.star;
2738 pCtx->msrPAT = pVM->rem.s.Env.pat;
2739#ifdef TARGET_X86_64
2740 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2741 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2742 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2743 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2744#endif
2745
2746 /* Inhibit interrupt flag. */
2747 if (pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK)
2748 {
2749 Log(("Settings VMCPU_FF_INHIBIT_INTERRUPTS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2750 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
2751 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2752 }
2753 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2754 {
2755 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv (REM#2)\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2756 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2757 }
2758
2759 /* Inhibit NMI flag. */
2760 if (pVM->rem.s.Env.hflags2 & HF2_NMI_MASK)
2761 {
2762 Log(("Settings VMCPU_FF_BLOCK_NMIS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2763 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2764 }
2765 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2766 {
2767 Log(("Clearing VMCPU_FF_BLOCK_NMIS at %RGv (REM)\n", (RTGCPTR)pCtx->rip));
2768 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2769 }
2770
2771 remR3TrapClear(pVM);
2772
2773 /*
2774 * Check for traps.
2775 */
2776 if ( pVM->rem.s.Env.exception_index >= 0
2777 && pVM->rem.s.Env.exception_index < 256)
2778 {
2779 /* This cannot be a hardware-interrupt because exception_index < EXCP_INTERRUPT. */
2780 int rc;
2781
2782 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2783 TRPMEVENT enmType = pVM->rem.s.Env.exception_is_int ? TRPM_SOFTWARE_INT : TRPM_TRAP;
2784 rc = TRPMAssertTrap(pVCpu, pVM->rem.s.Env.exception_index, enmType);
2785 AssertRC(rc);
2786 if (enmType == TRPM_TRAP)
2787 {
2788 switch (pVM->rem.s.Env.exception_index)
2789 {
2790 case X86_XCPT_PF:
2791 TRPMSetFaultAddress(pVCpu, pCtx->cr2);
2792 /* fallthru */
2793 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP:
2794 case X86_XCPT_AC: case X86_XCPT_DF: /* 0 */
2795 TRPMSetErrorCode(pVCpu, pVM->rem.s.Env.error_code);
2796 break;
2797 }
2798 }
2799 }
2800
2801 /*
2802 * We're not longer in REM mode.
2803 */
2804 CPUMR3RemLeave(pVCpu,
2805 HMIsEnabled(pVM)
2806 || ( pVM->rem.s.Env.segs[R_SS].newselector
2807 | pVM->rem.s.Env.segs[R_GS].newselector
2808 | pVM->rem.s.Env.segs[R_FS].newselector
2809 | pVM->rem.s.Env.segs[R_ES].newselector
2810 | pVM->rem.s.Env.segs[R_DS].newselector
2811 | pVM->rem.s.Env.segs[R_CS].newselector) == 0
2812 );
2813 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_REM);
2814 pVM->rem.s.fInREM = false;
2815 pVM->rem.s.pCtx = NULL;
2816 pVM->rem.s.Env.pVCpu = NULL;
2817 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2818 Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2819 return VINF_SUCCESS;
2820}
2821
2822
2823/**
2824 * This is called by the disassembler when it wants to update the cpu state
2825 * before for instance doing a register dump.
2826 */
2827static void remR3StateUpdate(PVM pVM, PVMCPU pVCpu)
2828{
2829 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2830 unsigned i;
2831
2832 Assert(pVM->rem.s.fInREM);
2833
2834 /*
2835 * Copy back the registers.
2836 * This is done in the order they are declared in the CPUMCTX structure.
2837 */
2838
2839 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87;
2840 /** @todo FOP */
2841 /** @todo FPUIP */
2842 /** @todo CS */
2843 /** @todo FPUDP */
2844 /** @todo DS */
2845 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2846 pFpuCtx->MXCSR = 0;
2847 pFpuCtx->MXCSR_MASK = 0;
2848
2849 /** @todo check if FPU/XMM was actually used in the recompiler */
2850 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)pFpuCtx);
2851//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2852
2853#ifdef TARGET_X86_64
2854 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2855 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2856 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2857 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2858 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2859 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2860 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2861 pCtx->r8 = pVM->rem.s.Env.regs[8];
2862 pCtx->r9 = pVM->rem.s.Env.regs[9];
2863 pCtx->r10 = pVM->rem.s.Env.regs[10];
2864 pCtx->r11 = pVM->rem.s.Env.regs[11];
2865 pCtx->r12 = pVM->rem.s.Env.regs[12];
2866 pCtx->r13 = pVM->rem.s.Env.regs[13];
2867 pCtx->r14 = pVM->rem.s.Env.regs[14];
2868 pCtx->r15 = pVM->rem.s.Env.regs[15];
2869
2870 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2871#else
2872 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2873 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2874 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2875 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2876 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2877 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2878 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2879
2880 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2881#endif
2882
2883 SYNC_BACK_SREG(es, ES);
2884 SYNC_BACK_SREG(cs, CS);
2885 SYNC_BACK_SREG(ss, SS);
2886 SYNC_BACK_SREG(ds, DS);
2887 SYNC_BACK_SREG(fs, FS);
2888 SYNC_BACK_SREG(gs, GS);
2889
2890#ifdef TARGET_X86_64
2891 pCtx->rip = pVM->rem.s.Env.eip;
2892 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2893#else
2894 pCtx->eip = pVM->rem.s.Env.eip;
2895 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2896#endif
2897
2898 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2899 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2900 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2901#ifdef VBOX_WITH_RAW_MODE
2902 if (((pVM->rem.s.Env.cr[4] ^ pCtx->cr4) & X86_CR4_VME) && !HMIsEnabled(pVM))
2903 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2904#endif
2905 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2906
2907 for (i = 0; i < 8; i++)
2908 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2909
2910 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2911 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base)
2912 {
2913 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
2914 STAM_COUNTER_INC(&gStatREMGDTChange);
2915#ifdef VBOX_WITH_RAW_MODE
2916 if (!HMIsEnabled(pVM))
2917 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
2918#endif
2919 }
2920
2921 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2922 if (pCtx->idtr.pIdt != (RTGCPTR)pVM->rem.s.Env.idt.base)
2923 {
2924 pCtx->idtr.pIdt = (RTGCPTR)pVM->rem.s.Env.idt.base;
2925 STAM_COUNTER_INC(&gStatREMIDTChange);
2926#ifdef VBOX_WITH_RAW_MODE
2927 if (!HMIsEnabled(pVM))
2928 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
2929#endif
2930 }
2931
2932 if ( pCtx->ldtr.Sel != pVM->rem.s.Env.ldt.selector
2933 || pCtx->ldtr.ValidSel != pVM->rem.s.Env.ldt.selector
2934 || pCtx->ldtr.u64Base != pVM->rem.s.Env.ldt.base
2935 || pCtx->ldtr.u32Limit != pVM->rem.s.Env.ldt.limit
2936 || pCtx->ldtr.Attr.u != ((pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK)
2937 || !(pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID)
2938 )
2939 {
2940 pCtx->ldtr.Sel = pVM->rem.s.Env.ldt.selector;
2941 pCtx->ldtr.ValidSel = pVM->rem.s.Env.ldt.selector;
2942 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2943 pCtx->ldtr.u64Base = pVM->rem.s.Env.ldt.base;
2944 pCtx->ldtr.u32Limit = pVM->rem.s.Env.ldt.limit;
2945 pCtx->ldtr.Attr.u = (pVM->rem.s.Env.ldt.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2946 STAM_COUNTER_INC(&gStatREMLDTRChange);
2947#ifdef VBOX_WITH_RAW_MODE
2948 if (!HMIsEnabled(pVM))
2949 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
2950#endif
2951 }
2952
2953 if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
2954 || pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
2955 || pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
2956 || pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
2957 /* Qemu and AMD/Intel have different ideas about the busy flag ... */
2958 || pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2959 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
2960 : 0)
2961 || !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
2962 )
2963 {
2964 Log(("REM: TR changed! %#x{%#llx,%#x,%#x} -> %#x{%llx,%#x,%#x}\n",
2965 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2966 pVM->rem.s.Env.tr.selector, (uint64_t)pVM->rem.s.Env.tr.base, pVM->rem.s.Env.tr.limit,
2967 (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
2968 ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT : 0));
2969 pCtx->tr.Sel = pVM->rem.s.Env.tr.selector;
2970 pCtx->tr.ValidSel = pVM->rem.s.Env.tr.selector;
2971 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2972 pCtx->tr.u64Base = pVM->rem.s.Env.tr.base;
2973 pCtx->tr.u32Limit = pVM->rem.s.Env.tr.limit;
2974 pCtx->tr.Attr.u = (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & SEL_FLAGS_SMASK;
2975 if (pCtx->tr.Attr.u & ~DESC_INTEL_UNUSABLE)
2976 pCtx->tr.Attr.u |= DESC_TSS_BUSY_MASK >> SEL_FLAGS_SHIFT;
2977 STAM_COUNTER_INC(&gStatREMTRChange);
2978#ifdef VBOX_WITH_RAW_MODE
2979 if (!HMIsEnabled(pVM))
2980 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2981#endif
2982 }
2983
2984 /* Sysenter MSR */
2985 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2986 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2987 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2988
2989 /* System MSRs. */
2990 pCtx->msrEFER = pVM->rem.s.Env.efer;
2991 pCtx->msrSTAR = pVM->rem.s.Env.star;
2992 pCtx->msrPAT = pVM->rem.s.Env.pat;
2993#ifdef TARGET_X86_64
2994 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2995 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2996 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2997 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2998#endif
2999
3000}
3001
3002
3003/**
3004 * Update the VMM state information if we're currently in REM.
3005 *
3006 * This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
3007 * we're currently executing in REM and the VMM state is invalid. This method will of
3008 * course check that we're executing in REM before syncing any data over to the VMM.
3009 *
3010 * @param pVM The VM handle.
3011 * @param pVCpu The VMCPU handle.
3012 */
3013REMR3DECL(void) REMR3StateUpdate(PVM pVM, PVMCPU pVCpu)
3014{
3015 if (pVM->rem.s.fInREM)
3016 remR3StateUpdate(pVM, pVCpu);
3017}
3018
3019
3020#undef LOG_GROUP
3021#define LOG_GROUP LOG_GROUP_REM
3022
3023
3024/**
3025 * Notify the recompiler about Address Gate 20 state change.
3026 *
3027 * This notification is required since A20 gate changes are
3028 * initialized from a device driver and the VM might just as
3029 * well be in REM mode as in RAW mode.
3030 *
3031 * @param pVM VM handle.
3032 * @param pVCpu VMCPU handle.
3033 * @param fEnable True if the gate should be enabled.
3034 * False if the gate should be disabled.
3035 */
3036REMR3DECL(void) REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable)
3037{
3038 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
3039 VM_ASSERT_EMT(pVM);
3040
3041 /** @todo SMP and the A20 gate... */
3042 if (pVM->rem.s.Env.pVCpu == pVCpu)
3043 {
3044 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3045 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
3046 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3047 }
3048}
3049
3050
3051/**
3052 * Replays the handler notification changes
3053 * Called in response to VM_FF_REM_HANDLER_NOTIFY from the RAW execution loop.
3054 *
3055 * @param pVM VM handle.
3056 */
3057REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
3058{
3059 /*
3060 * Replay the flushes.
3061 */
3062 LogFlow(("REMR3ReplayHandlerNotifications:\n"));
3063 VM_ASSERT_EMT(pVM);
3064
3065 /** @todo this isn't ensuring correct replay order. */
3066 if (VM_FF_TEST_AND_CLEAR(pVM, VM_FF_REM_HANDLER_NOTIFY))
3067 {
3068 uint32_t idxNext;
3069 uint32_t idxRevHead;
3070 uint32_t idxHead;
3071#ifdef VBOX_STRICT
3072 int32_t c = 0;
3073#endif
3074
3075 /* Lockless purging of pending notifications. */
3076 idxHead = ASMAtomicXchgU32(&pVM->rem.s.idxPendingList, UINT32_MAX);
3077 if (idxHead == UINT32_MAX)
3078 return;
3079 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3080
3081 /*
3082 * Reverse the list to process it in FIFO order.
3083 */
3084 idxRevHead = UINT32_MAX;
3085 do
3086 {
3087 /* Save the index of the next rec. */
3088 idxNext = pVM->rem.s.aHandlerNotifications[idxHead].idxNext;
3089 Assert(idxNext < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || idxNext == UINT32_MAX);
3090 /* Push the record onto the reversed list. */
3091 pVM->rem.s.aHandlerNotifications[idxHead].idxNext = idxRevHead;
3092 idxRevHead = idxHead;
3093 Assert(++c <= RT_ELEMENTS(pVM->rem.s.aHandlerNotifications));
3094 /* Advance. */
3095 idxHead = idxNext;
3096 } while (idxHead != UINT32_MAX);
3097
3098 /*
3099 * Loop thru the list, reinserting the record into the free list as they are
3100 * processed to avoid having other EMTs running out of entries while we're flushing.
3101 */
3102 idxHead = idxRevHead;
3103 do
3104 {
3105 PREMHANDLERNOTIFICATION pCur = &pVM->rem.s.aHandlerNotifications[idxHead];
3106 uint32_t idxCur;
3107 Assert(--c >= 0);
3108
3109 switch (pCur->enmKind)
3110 {
3111 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
3112 remR3NotifyHandlerPhysicalRegister(pVM,
3113 pCur->u.PhysicalRegister.enmKind,
3114 pCur->u.PhysicalRegister.GCPhys,
3115 pCur->u.PhysicalRegister.cb,
3116 pCur->u.PhysicalRegister.fHasHCHandler);
3117 break;
3118
3119 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
3120 remR3NotifyHandlerPhysicalDeregister(pVM,
3121 pCur->u.PhysicalDeregister.enmKind,
3122 pCur->u.PhysicalDeregister.GCPhys,
3123 pCur->u.PhysicalDeregister.cb,
3124 pCur->u.PhysicalDeregister.fHasHCHandler,
3125 pCur->u.PhysicalDeregister.fRestoreAsRAM);
3126 break;
3127
3128 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
3129 remR3NotifyHandlerPhysicalModify(pVM,
3130 pCur->u.PhysicalModify.enmKind,
3131 pCur->u.PhysicalModify.GCPhysOld,
3132 pCur->u.PhysicalModify.GCPhysNew,
3133 pCur->u.PhysicalModify.cb,
3134 pCur->u.PhysicalModify.fHasHCHandler,
3135 pCur->u.PhysicalModify.fRestoreAsRAM);
3136 break;
3137
3138 default:
3139 AssertReleaseMsgFailed(("enmKind=%d\n", pCur->enmKind));
3140 break;
3141 }
3142
3143 /*
3144 * Advance idxHead.
3145 */
3146 idxCur = idxHead;
3147 idxHead = pCur->idxNext;
3148 Assert(idxHead < RT_ELEMENTS(pVM->rem.s.aHandlerNotifications) || (idxHead == UINT32_MAX && c == 0));
3149
3150 /*
3151 * Put the record back into the free list.
3152 */
3153 do
3154 {
3155 idxNext = ASMAtomicUoReadU32(&pVM->rem.s.idxFreeList);
3156 ASMAtomicWriteU32(&pCur->idxNext, idxNext);
3157 ASMCompilerBarrier();
3158 } while (!ASMAtomicCmpXchgU32(&pVM->rem.s.idxFreeList, idxCur, idxNext));
3159 } while (idxHead != UINT32_MAX);
3160
3161#ifdef VBOX_STRICT
3162 if (pVM->cCpus == 1)
3163 {
3164 unsigned c;
3165 /* Check that all records are now on the free list. */
3166 for (c = 0, idxNext = pVM->rem.s.idxFreeList; idxNext != UINT32_MAX;
3167 idxNext = pVM->rem.s.aHandlerNotifications[idxNext].idxNext)
3168 c++;
3169 AssertReleaseMsg(c == RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), ("%#x != %#x, idxFreeList=%#x\n", c, RT_ELEMENTS(pVM->rem.s.aHandlerNotifications), pVM->rem.s.idxFreeList));
3170 }
3171#endif
3172 }
3173}
3174
3175
3176/**
3177 * Notify REM about changed code page.
3178 *
3179 * @returns VBox status code.
3180 * @param pVM VM handle.
3181 * @param pVCpu VMCPU handle.
3182 * @param pvCodePage Code page address
3183 */
3184REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage)
3185{
3186#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
3187 int rc;
3188 RTGCPHYS PhysGC;
3189 uint64_t flags;
3190
3191 VM_ASSERT_EMT(pVM);
3192
3193 /*
3194 * Get the physical page address.
3195 */
3196 rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
3197 if (rc == VINF_SUCCESS)
3198 {
3199 /*
3200 * Sync the required registers and flush the whole page.
3201 * (Easier to do the whole page than notifying it about each physical
3202 * byte that was changed.
3203 */
3204 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
3205 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
3206 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
3207 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
3208
3209 tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
3210 }
3211#endif
3212 return VINF_SUCCESS;
3213}
3214
3215
3216/**
3217 * Notification about a successful MMR3PhysRegister() call.
3218 *
3219 * @param pVM VM handle.
3220 * @param GCPhys The physical address the RAM.
3221 * @param cb Size of the memory.
3222 * @param fFlags Flags of the REM_NOTIFY_PHYS_RAM_FLAGS_* defines.
3223 */
3224REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, unsigned fFlags)
3225{
3226 Log(("REMR3NotifyPhysRamRegister: GCPhys=%RGp cb=%RGp fFlags=%#x\n", GCPhys, cb, fFlags));
3227 VM_ASSERT_EMT(pVM);
3228
3229 /*
3230 * Validate input - we trust the caller.
3231 */
3232 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3233 Assert(cb);
3234 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3235 AssertMsg(fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_RAM || fFlags == REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2, ("%#x\n", fFlags));
3236
3237 /*
3238 * Base ram? Update GCPhysLastRam.
3239 */
3240 if (fFlags & REM_NOTIFY_PHYS_RAM_FLAGS_RAM)
3241 {
3242 if (GCPhys + (cb - 1) > pVM->rem.s.GCPhysLastRam)
3243 {
3244 AssertReleaseMsg(!pVM->rem.s.fGCPhysLastRamFixed, ("GCPhys=%RGp cb=%RGp\n", GCPhys, cb));
3245 pVM->rem.s.GCPhysLastRam = GCPhys + (cb - 1);
3246 }
3247 }
3248
3249 /*
3250 * Register the ram.
3251 */
3252 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3253
3254 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3255 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys, GCPhys);
3256 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3257
3258 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3259}
3260
3261
3262/**
3263 * Notification about a successful MMR3PhysRomRegister() call.
3264 *
3265 * @param pVM VM handle.
3266 * @param GCPhys The physical address of the ROM.
3267 * @param cb The size of the ROM.
3268 * @param pvCopy Pointer to the ROM copy.
3269 * @param fShadow Whether it's currently writable shadow ROM or normal readonly ROM.
3270 * This function will be called when ever the protection of the
3271 * shadow ROM changes (at reset and end of POST).
3272 */
3273REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)
3274{
3275 Log(("REMR3NotifyPhysRomRegister: GCPhys=%RGp cb=%d fShadow=%RTbool\n", GCPhys, cb, fShadow));
3276 VM_ASSERT_EMT(pVM);
3277
3278 /*
3279 * Validate input - we trust the caller.
3280 */
3281 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3282 Assert(cb);
3283 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3284
3285 /*
3286 * Register the rom.
3287 */
3288 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3289
3290 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3291 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys | (fShadow ? 0 : IO_MEM_ROM), GCPhys);
3292 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3293
3294 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3295}
3296
3297
3298/**
3299 * Notification about a successful memory deregistration or reservation.
3300 *
3301 * @param pVM VM Handle.
3302 * @param GCPhys Start physical address.
3303 * @param cb The size of the range.
3304 */
3305REMR3DECL(void) REMR3NotifyPhysRamDeregister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
3306{
3307 Log(("REMR3NotifyPhysRamDeregister: GCPhys=%RGp cb=%d\n", GCPhys, cb));
3308 VM_ASSERT_EMT(pVM);
3309
3310 /*
3311 * Validate input - we trust the caller.
3312 */
3313 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3314 Assert(cb);
3315 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
3316
3317 /*
3318 * Unassigning the memory.
3319 */
3320 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3321
3322 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3323 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3324 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3325
3326 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3327}
3328
3329
3330/**
3331 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
3332 *
3333 * @param pVM VM Handle.
3334 * @param enmKind Kind of access handler.
3335 * @param GCPhys Handler range address.
3336 * @param cb Size of the handler range.
3337 * @param fHasHCHandler Set if the handler has a HC callback function.
3338 *
3339 * @remark MMR3PhysRomRegister assumes that this function will not apply the
3340 * Handler memory type to memory which has no HC handler.
3341 */
3342static void remR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3343 bool fHasHCHandler)
3344{
3345 Log(("REMR3NotifyHandlerPhysicalRegister: enmKind=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%d\n",
3346 enmKind, GCPhys, cb, fHasHCHandler));
3347
3348 VM_ASSERT_EMT(pVM);
3349 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3350 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3351
3352
3353 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3354
3355 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3356 if (enmKind == PGMPHYSHANDLERKIND_MMIO)
3357 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iMMIOMemType, GCPhys);
3358 else if (fHasHCHandler)
3359 cpu_register_physical_memory_offset(GCPhys, cb, pVM->rem.s.iHandlerMemType, GCPhys);
3360 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3361
3362 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3363}
3364
3365/**
3366 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
3367 *
3368 * @param pVM VM Handle.
3369 * @param enmKind Kind of access handler.
3370 * @param GCPhys Handler range address.
3371 * @param cb Size of the handler range.
3372 * @param fHasHCHandler Set if the handler has a HC callback function.
3373 *
3374 * @remark MMR3PhysRomRegister assumes that this function will not apply the
3375 * Handler memory type to memory which has no HC handler.
3376 */
3377REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3378 bool fHasHCHandler)
3379{
3380 REMR3ReplayHandlerNotifications(pVM);
3381
3382 remR3NotifyHandlerPhysicalRegister(pVM, enmKind, GCPhys, cb, fHasHCHandler);
3383}
3384
3385/**
3386 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3387 *
3388 * @param pVM VM Handle.
3389 * @param enmKind Kind of access handler.
3390 * @param GCPhys Handler range address.
3391 * @param cb Size of the handler range.
3392 * @param fHasHCHandler Set if the handler has a HC callback function.
3393 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3394 */
3395static void remR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3396 bool fHasHCHandler, bool fRestoreAsRAM)
3397{
3398 Log(("REMR3NotifyHandlerPhysicalDeregister: enmKind=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool RAM=%08x\n",
3399 enmKind, GCPhys, cb, fHasHCHandler, fRestoreAsRAM, MMR3PhysGetRamSize(pVM)));
3400 VM_ASSERT_EMT(pVM);
3401
3402
3403 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3404
3405 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3406 /** @todo this isn't right, MMIO can (in theory) be restored as RAM. */
3407 if (enmKind == PGMPHYSHANDLERKIND_MMIO)
3408 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3409 else if (fHasHCHandler)
3410 {
3411 if (!fRestoreAsRAM)
3412 {
3413 Assert(GCPhys > MMR3PhysGetRamSize(pVM));
3414 cpu_register_physical_memory_offset(GCPhys, cb, IO_MEM_UNASSIGNED, GCPhys);
3415 }
3416 else
3417 {
3418 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3419 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3420 cpu_register_physical_memory_offset(GCPhys, cb, GCPhys, GCPhys);
3421 }
3422 }
3423 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3424
3425 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3426}
3427
3428/**
3429 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
3430 *
3431 * @param pVM VM Handle.
3432 * @param enmKind Kind of access handler.
3433 * @param GCPhys Handler range address.
3434 * @param cb Size of the handler range.
3435 * @param fHasHCHandler Set if the handler has a HC callback function.
3436 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3437 */
3438REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3439{
3440 REMR3ReplayHandlerNotifications(pVM);
3441 remR3NotifyHandlerPhysicalDeregister(pVM, enmKind, GCPhys, cb, fHasHCHandler, fRestoreAsRAM);
3442}
3443
3444
3445/**
3446 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3447 *
3448 * @param pVM VM Handle.
3449 * @param enmKind Kind of access handler.
3450 * @param GCPhysOld Old handler range address.
3451 * @param GCPhysNew New handler range address.
3452 * @param cb Size of the handler range.
3453 * @param fHasHCHandler Set if the handler has a HC callback function.
3454 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3455 */
3456static void remR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3457{
3458 Log(("REMR3NotifyHandlerPhysicalModify: enmKind=%d GCPhysOld=%RGp GCPhysNew=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool\n",
3459 enmKind, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM));
3460 VM_ASSERT_EMT(pVM);
3461 AssertReleaseMsg(enmKind != PGMPHYSHANDLERKIND_MMIO, ("enmKind=%d\n", enmKind));
3462
3463 if (fHasHCHandler)
3464 {
3465 ASMAtomicIncU32(&pVM->rem.s.cIgnoreAll);
3466
3467 /*
3468 * Reset the old page.
3469 */
3470 PDMCritSectEnter(&pVM->rem.s.CritSectRegister, VERR_SEM_BUSY);
3471 if (!fRestoreAsRAM)
3472 cpu_register_physical_memory_offset(GCPhysOld, cb, IO_MEM_UNASSIGNED, GCPhysOld);
3473 else
3474 {
3475 /* This is not perfect, but it'll do for PD monitoring... */
3476 Assert(cb == PAGE_SIZE);
3477 Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
3478 cpu_register_physical_memory_offset(GCPhysOld, cb, GCPhysOld, GCPhysOld);
3479 }
3480
3481 /*
3482 * Update the new page.
3483 */
3484 Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
3485 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
3486 cpu_register_physical_memory_offset(GCPhysNew, cb, pVM->rem.s.iHandlerMemType, GCPhysNew);
3487 PDMCritSectLeave(&pVM->rem.s.CritSectRegister);
3488
3489 ASMAtomicDecU32(&pVM->rem.s.cIgnoreAll);
3490 }
3491}
3492
3493/**
3494 * Notification about a successful PGMR3HandlerPhysicalModify() call.
3495 *
3496 * @param pVM VM Handle.
3497 * @param enmKind Kind of access handler.
3498 * @param GCPhysOld Old handler range address.
3499 * @param GCPhysNew New handler range address.
3500 * @param cb Size of the handler range.
3501 * @param fHasHCHandler Set if the handler has a HC callback function.
3502 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
3503 */
3504REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
3505{
3506 REMR3ReplayHandlerNotifications(pVM);
3507
3508 remR3NotifyHandlerPhysicalModify(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM);
3509}
3510
3511/**
3512 * Checks if we're handling access to this page or not.
3513 *
3514 * @returns true if we're trapping access.
3515 * @returns false if we aren't.
3516 * @param pVM The VM handle.
3517 * @param GCPhys The physical address.
3518 *
3519 * @remark This function will only work correctly in VBOX_STRICT builds!
3520 */
3521REMR3DECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
3522{
3523#ifdef VBOX_STRICT
3524 ram_addr_t off;
3525 REMR3ReplayHandlerNotifications(pVM);
3526
3527 off = get_phys_page_offset(GCPhys);
3528 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
3529 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
3530 || (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
3531#else
3532 return false;
3533#endif
3534}
3535
3536
3537/**
3538 * Deals with a rare case in get_phys_addr_code where the code
3539 * is being monitored.
3540 *
3541 * It could also be an MMIO page, in which case we will raise a fatal error.
3542 *
3543 * @returns The physical address corresponding to addr.
3544 * @param env The cpu environment.
3545 * @param addr The virtual address.
3546 * @param pTLBEntry The TLB entry.
3547 * @param IoTlbEntry The I/O TLB entry address.
3548 */
3549target_ulong remR3PhysGetPhysicalAddressCode(CPUX86State *env,
3550 target_ulong addr,
3551 CPUTLBEntry *pTLBEntry,
3552 target_phys_addr_t IoTlbEntry)
3553{
3554 PVM pVM = env->pVM;
3555
3556 if ((IoTlbEntry & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
3557 {
3558 /* If code memory is being monitored, appropriate IOTLB entry will have
3559 handler IO type, and addend will provide real physical address, no
3560 matter if we store VA in TLB or not, as handlers are always passed PA */
3561 target_ulong ret = (IoTlbEntry & TARGET_PAGE_MASK) + addr;
3562 return ret;
3563 }
3564 LogRel(("\nTrying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv! (iHandlerMemType=%#x iMMIOMemType=%#x IOTLB=%RGp)\n"
3565 "*** handlers\n",
3566 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType, (RTGCPHYS)IoTlbEntry));
3567 DBGFR3Info(pVM->pUVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
3568 LogRel(("*** mmio\n"));
3569 DBGFR3Info(pVM->pUVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
3570 LogRel(("*** phys\n"));
3571 DBGFR3Info(pVM->pUVM, "phys", NULL, DBGFR3InfoLogRelHlp());
3572 cpu_abort(env, "Trying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
3573 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
3574 AssertFatalFailed();
3575}
3576
3577/**
3578 * Read guest RAM and ROM.
3579 *
3580 * @param SrcGCPhys The source address (guest physical).
3581 * @param pvDst The destination address.
3582 * @param cb Number of bytes
3583 */
3584void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb)
3585{
3586 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3587 VBOX_CHECK_ADDR(SrcGCPhys);
3588 VBOXSTRICTRC rcStrict = PGMPhysRead(cpu_single_env->pVM, SrcGCPhys, pvDst, cb, PGMACCESSORIGIN_REM);
3589 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3590#ifdef VBOX_DEBUG_PHYS
3591 LogRel(("read(%d): %08x\n", cb, (uint32_t)SrcGCPhys));
3592#endif
3593 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3594}
3595
3596
3597/**
3598 * Read guest RAM and ROM, unsigned 8-bit.
3599 *
3600 * @param SrcGCPhys The source address (guest physical).
3601 */
3602RTCCUINTREG remR3PhysReadU8(RTGCPHYS SrcGCPhys)
3603{
3604 uint8_t val;
3605 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3606 VBOX_CHECK_ADDR(SrcGCPhys);
3607 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3608 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3609#ifdef VBOX_DEBUG_PHYS
3610 LogRel(("readu8: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3611#endif
3612 return val;
3613}
3614
3615
3616/**
3617 * Read guest RAM and ROM, signed 8-bit.
3618 *
3619 * @param SrcGCPhys The source address (guest physical).
3620 */
3621RTCCINTREG remR3PhysReadS8(RTGCPHYS SrcGCPhys)
3622{
3623 int8_t val;
3624 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3625 VBOX_CHECK_ADDR(SrcGCPhys);
3626 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3627 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3628#ifdef VBOX_DEBUG_PHYS
3629 LogRel(("reads8: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3630#endif
3631 return val;
3632}
3633
3634
3635/**
3636 * Read guest RAM and ROM, unsigned 16-bit.
3637 *
3638 * @param SrcGCPhys The source address (guest physical).
3639 */
3640RTCCUINTREG remR3PhysReadU16(RTGCPHYS SrcGCPhys)
3641{
3642 uint16_t val;
3643 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3644 VBOX_CHECK_ADDR(SrcGCPhys);
3645 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3646 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3647#ifdef VBOX_DEBUG_PHYS
3648 LogRel(("readu16: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3649#endif
3650 return val;
3651}
3652
3653
3654/**
3655 * Read guest RAM and ROM, signed 16-bit.
3656 *
3657 * @param SrcGCPhys The source address (guest physical).
3658 */
3659RTCCINTREG remR3PhysReadS16(RTGCPHYS SrcGCPhys)
3660{
3661 int16_t val;
3662 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3663 VBOX_CHECK_ADDR(SrcGCPhys);
3664 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3665 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3666#ifdef VBOX_DEBUG_PHYS
3667 LogRel(("reads16: %x <- %08x\n", (uint16_t)val, (uint32_t)SrcGCPhys));
3668#endif
3669 return val;
3670}
3671
3672
3673/**
3674 * Read guest RAM and ROM, unsigned 32-bit.
3675 *
3676 * @param SrcGCPhys The source address (guest physical).
3677 */
3678RTCCUINTREG remR3PhysReadU32(RTGCPHYS SrcGCPhys)
3679{
3680 uint32_t val;
3681 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3682 VBOX_CHECK_ADDR(SrcGCPhys);
3683 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3684 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3685#ifdef VBOX_DEBUG_PHYS
3686 LogRel(("readu32: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3687#endif
3688 return val;
3689}
3690
3691
3692/**
3693 * Read guest RAM and ROM, signed 32-bit.
3694 *
3695 * @param SrcGCPhys The source address (guest physical).
3696 */
3697RTCCINTREG remR3PhysReadS32(RTGCPHYS SrcGCPhys)
3698{
3699 int32_t val;
3700 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3701 VBOX_CHECK_ADDR(SrcGCPhys);
3702 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3703 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3704#ifdef VBOX_DEBUG_PHYS
3705 LogRel(("reads32: %x <- %08x\n", val, (uint32_t)SrcGCPhys));
3706#endif
3707 return val;
3708}
3709
3710
3711/**
3712 * Read guest RAM and ROM, unsigned 64-bit.
3713 *
3714 * @param SrcGCPhys The source address (guest physical).
3715 */
3716uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys)
3717{
3718 uint64_t val;
3719 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3720 VBOX_CHECK_ADDR(SrcGCPhys);
3721 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3722 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3723#ifdef VBOX_DEBUG_PHYS
3724 LogRel(("readu64: %llx <- %08x\n", val, (uint32_t)SrcGCPhys));
3725#endif
3726 return val;
3727}
3728
3729
3730/**
3731 * Read guest RAM and ROM, signed 64-bit.
3732 *
3733 * @param SrcGCPhys The source address (guest physical).
3734 */
3735int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys)
3736{
3737 int64_t val;
3738 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3739 VBOX_CHECK_ADDR(SrcGCPhys);
3740 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys, PGMACCESSORIGIN_REM);
3741 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3742#ifdef VBOX_DEBUG_PHYS
3743 LogRel(("reads64: %llx <- %08x\n", val, (uint32_t)SrcGCPhys));
3744#endif
3745 return val;
3746}
3747
3748
3749/**
3750 * Write guest RAM.
3751 *
3752 * @param DstGCPhys The destination address (guest physical).
3753 * @param pvSrc The source address.
3754 * @param cb Number of bytes to write
3755 */
3756void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb)
3757{
3758 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3759 VBOX_CHECK_ADDR(DstGCPhys);
3760 VBOXSTRICTRC rcStrict = PGMPhysWrite(cpu_single_env->pVM, DstGCPhys, pvSrc, cb, PGMACCESSORIGIN_REM);
3761 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3762 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3763#ifdef VBOX_DEBUG_PHYS
3764 LogRel(("write(%d): %08x\n", cb, (uint32_t)DstGCPhys));
3765#endif
3766}
3767
3768
3769/**
3770 * Write guest RAM, unsigned 8-bit.
3771 *
3772 * @param DstGCPhys The destination address (guest physical).
3773 * @param val Value
3774 */
3775void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val)
3776{
3777 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3778 VBOX_CHECK_ADDR(DstGCPhys);
3779 PGMR3PhysWriteU8(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3780 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3781#ifdef VBOX_DEBUG_PHYS
3782 LogRel(("writeu8: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3783#endif
3784}
3785
3786
3787/**
3788 * Write guest RAM, unsigned 8-bit.
3789 *
3790 * @param DstGCPhys The destination address (guest physical).
3791 * @param val Value
3792 */
3793void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val)
3794{
3795 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3796 VBOX_CHECK_ADDR(DstGCPhys);
3797 PGMR3PhysWriteU16(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3798 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3799#ifdef VBOX_DEBUG_PHYS
3800 LogRel(("writeu16: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3801#endif
3802}
3803
3804
3805/**
3806 * Write guest RAM, unsigned 32-bit.
3807 *
3808 * @param DstGCPhys The destination address (guest physical).
3809 * @param val Value
3810 */
3811void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val)
3812{
3813 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3814 VBOX_CHECK_ADDR(DstGCPhys);
3815 PGMR3PhysWriteU32(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3816 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3817#ifdef VBOX_DEBUG_PHYS
3818 LogRel(("writeu32: %x -> %08x\n", val, (uint32_t)DstGCPhys));
3819#endif
3820}
3821
3822
3823/**
3824 * Write guest RAM, unsigned 64-bit.
3825 *
3826 * @param DstGCPhys The destination address (guest physical).
3827 * @param val Value
3828 */
3829void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val)
3830{
3831 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3832 VBOX_CHECK_ADDR(DstGCPhys);
3833 PGMR3PhysWriteU64(cpu_single_env->pVM, DstGCPhys, val, PGMACCESSORIGIN_REM);
3834 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3835#ifdef VBOX_DEBUG_PHYS
3836 LogRel(("writeu64: %llx -> %08x\n", val, (uint32_t)DstGCPhys));
3837#endif
3838}
3839
3840#undef LOG_GROUP
3841#define LOG_GROUP LOG_GROUP_REM_MMIO
3842
3843/** Read MMIO memory. */
3844static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys)
3845{
3846 CPUX86State *env = (CPUX86State *)pvEnv;
3847 uint32_t u32 = 0;
3848 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 1);
3849 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3850 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", (RTGCPHYS)GCPhys, u32));
3851 return u32;
3852}
3853
3854/** Read MMIO memory. */
3855static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys)
3856{
3857 CPUX86State *env = (CPUX86State *)pvEnv;
3858 uint32_t u32 = 0;
3859 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 2);
3860 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3861 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", (RTGCPHYS)GCPhys, u32));
3862 return u32;
3863}
3864
3865/** Read MMIO memory. */
3866static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys)
3867{
3868 CPUX86State *env = (CPUX86State *)pvEnv;
3869 uint32_t u32 = 0;
3870 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 4);
3871 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3872 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", (RTGCPHYS)GCPhys, u32));
3873 return u32;
3874}
3875
3876/** Write to MMIO memory. */
3877static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3878{
3879 CPUX86State *env = (CPUX86State *)pvEnv;
3880 int rc;
3881 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3882 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 1);
3883 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3884}
3885
3886/** Write to MMIO memory. */
3887static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3888{
3889 CPUX86State *env = (CPUX86State *)pvEnv;
3890 int rc;
3891 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3892 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 2);
3893 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3894}
3895
3896/** Write to MMIO memory. */
3897static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32)
3898{
3899 CPUX86State *env = (CPUX86State *)pvEnv;
3900 int rc;
3901 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3902 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 4);
3903 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3904}
3905
3906
3907#undef LOG_GROUP
3908#define LOG_GROUP LOG_GROUP_REM_HANDLER
3909
3910/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3911
3912static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3913{
3914 uint8_t u8;
3915 Log2(("remR3HandlerReadU8: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3916 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8), PGMACCESSORIGIN_REM);
3917 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3918 return u8;
3919}
3920
3921static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3922{
3923 uint16_t u16;
3924 Log2(("remR3HandlerReadU16: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3925 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16), PGMACCESSORIGIN_REM);
3926 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3927 return u16;
3928}
3929
3930static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3931{
3932 uint32_t u32;
3933 Log2(("remR3HandlerReadU32: GCPhys=%RGp\n", (RTGCPHYS)GCPhys));
3934 VBOXSTRICTRC rcStrict = PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32), PGMACCESSORIGIN_REM);
3935 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3936 return u32;
3937}
3938
3939static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3940{
3941 Log2(("remR3HandlerWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3942 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t), PGMACCESSORIGIN_REM);
3943 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3944}
3945
3946static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3947{
3948 Log2(("remR3HandlerWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3949 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t), PGMACCESSORIGIN_REM);
3950 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3951}
3952
3953static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3954{
3955 Log2(("remR3HandlerWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32));
3956 VBOXSTRICTRC rcStrict = PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t), PGMACCESSORIGIN_REM);
3957 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
3958}
3959
3960/* -+- disassembly -+- */
3961
3962#undef LOG_GROUP
3963#define LOG_GROUP LOG_GROUP_REM_DISAS
3964
3965
3966/**
3967 * Enables or disables singled stepped disassembly.
3968 *
3969 * @returns VBox status code.
3970 * @param pVM VM handle.
3971 * @param fEnable To enable set this flag, to disable clear it.
3972 */
3973static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3974{
3975 LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3976 VM_ASSERT_EMT(pVM);
3977
3978 if (fEnable)
3979 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3980 else
3981 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3982#ifdef REM_USE_QEMU_SINGLE_STEP_FOR_LOGGING
3983 cpu_single_step(&pVM->rem.s.Env, fEnable);
3984#endif
3985 return VINF_SUCCESS;
3986}
3987
3988
3989/**
3990 * Enables or disables singled stepped disassembly.
3991 *
3992 * @returns VBox status code.
3993 * @param pVM VM handle.
3994 * @param fEnable To enable set this flag, to disable clear it.
3995 */
3996REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3997{
3998 int rc;
3999
4000 LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
4001 if (VM_IS_EMT(pVM))
4002 return remR3DisasEnableStepping(pVM, fEnable);
4003
4004 rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
4005 AssertRC(rc);
4006 return rc;
4007}
4008
4009
4010#ifdef VBOX_WITH_DEBUGGER
4011/**
4012 * External Debugger Command: .remstep [on|off|1|0]
4013 */
4014static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM,
4015 PCDBGCVAR paArgs, unsigned cArgs)
4016{
4017 int rc;
4018 PVM pVM = pUVM->pVM;
4019
4020 if (cArgs == 0)
4021 /*
4022 * Print the current status.
4023 */
4024 rc = DBGCCmdHlpPrintf(pCmdHlp, "DisasStepping is %s\n",
4025 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
4026 else
4027 {
4028 /*
4029 * Convert the argument and change the mode.
4030 */
4031 bool fEnable;
4032 rc = DBGCCmdHlpVarToBool(pCmdHlp, &paArgs[0], &fEnable);
4033 if (RT_SUCCESS(rc))
4034 {
4035 rc = REMR3DisasEnableStepping(pVM, fEnable);
4036 if (RT_SUCCESS(rc))
4037 rc = DBGCCmdHlpPrintf(pCmdHlp, "DisasStepping was %s\n", fEnable ? "enabled" : "disabled");
4038 else
4039 rc = DBGCCmdHlpFailRc(pCmdHlp, pCmd, rc, "REMR3DisasEnableStepping");
4040 }
4041 else
4042 rc = DBGCCmdHlpFailRc(pCmdHlp, pCmd, rc, "DBGCCmdHlpVarToBool");
4043 }
4044 return rc;
4045}
4046#endif /* VBOX_WITH_DEBUGGER */
4047
4048
4049/**
4050 * Disassembles one instruction and prints it to the log.
4051 *
4052 * @returns Success indicator.
4053 * @param env Pointer to the recompiler CPU structure.
4054 * @param f32BitCode Indicates that whether or not the code should
4055 * be disassembled as 16 or 32 bit. If -1 the CS
4056 * selector will be inspected.
4057 * @param pszPrefix
4058 */
4059bool remR3DisasInstr(CPUX86State *env, int f32BitCode, char *pszPrefix)
4060{
4061 PVM pVM = env->pVM;
4062 const bool fLog = LogIsEnabled();
4063 const bool fLog2 = LogIs2Enabled();
4064 int rc = VINF_SUCCESS;
4065
4066 /*
4067 * Don't bother if there ain't any log output to do.
4068 */
4069 if (!fLog && !fLog2)
4070 return true;
4071
4072 /*
4073 * Update the state so DBGF reads the correct register values.
4074 */
4075 remR3StateUpdate(pVM, env->pVCpu);
4076
4077 /*
4078 * Log registers if requested.
4079 */
4080 if (fLog2)
4081 DBGFR3_INFO_LOG(pVM, env->pVCpu, "cpumguest", pszPrefix);
4082
4083 /*
4084 * Disassemble to log.
4085 */
4086 if (fLog)
4087 {
4088 PVMCPU pVCpu = VMMGetCpu(pVM);
4089 char szBuf[256];
4090 szBuf[0] = '\0';
4091 int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM,
4092 pVCpu->idCpu,
4093 0, /* Sel */ 0, /* GCPtr */
4094 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
4095 szBuf,
4096 sizeof(szBuf),
4097 NULL);
4098 if (RT_FAILURE(rc))
4099 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrEx failed with rc=%Rrc\n", rc);
4100 if (pszPrefix && *pszPrefix)
4101 RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
4102 else
4103 RTLogPrintf("CPU%d: %s\n", pVCpu->idCpu, szBuf);
4104 }
4105
4106 return RT_SUCCESS(rc);
4107}
4108
4109
4110/**
4111 * Disassemble recompiled code.
4112 *
4113 * @param phFileIgnored Ignored, logfile usually.
4114 * @param pvCode Pointer to the code block.
4115 * @param cb Size of the code block.
4116 */
4117void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
4118{
4119 if (LogIs2Enabled())
4120 {
4121 unsigned off = 0;
4122 char szOutput[256];
4123 DISCPUSTATE Cpu;
4124#ifdef RT_ARCH_X86
4125 DISCPUMODE enmCpuMode = DISCPUMODE_32BIT;
4126#else
4127 DISCPUMODE enmCpuMode = DISCPUMODE_64BIT;
4128#endif
4129
4130 RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
4131 while (off < cb)
4132 {
4133 uint32_t cbInstr;
4134 int rc = DISInstrToStr((uint8_t const *)pvCode + off, enmCpuMode,
4135 &Cpu, &cbInstr, szOutput, sizeof(szOutput));
4136 if (RT_SUCCESS(rc))
4137 RTLogPrintf("%s", szOutput);
4138 else
4139 {
4140 RTLogPrintf("disas error %Rrc\n", rc);
4141 cbInstr = 1;
4142 }
4143 off += cbInstr;
4144 }
4145 }
4146}
4147
4148
4149/**
4150 * Disassemble guest code.
4151 *
4152 * @param phFileIgnored Ignored, logfile usually.
4153 * @param uCode The guest address of the code to disassemble. (flat?)
4154 * @param cb Number of bytes to disassemble.
4155 * @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
4156 */
4157void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
4158{
4159 if (LogIs2Enabled())
4160 {
4161 PVM pVM = cpu_single_env->pVM;
4162 PVMCPU pVCpu = cpu_single_env->pVCpu;
4163 RTSEL cs;
4164 RTGCUINTPTR eip;
4165
4166 Assert(pVCpu);
4167
4168 /*
4169 * Update the state so DBGF reads the correct register values (flags).
4170 */
4171 remR3StateUpdate(pVM, pVCpu);
4172
4173 /*
4174 * Do the disassembling.
4175 */
4176 RTLogPrintf("Guest Code: PC=%llx %llx bytes fFlags=%d\n", (uint64_t)uCode, (uint64_t)cb, fFlags);
4177 cs = cpu_single_env->segs[R_CS].selector;
4178 eip = uCode - cpu_single_env->segs[R_CS].base;
4179 for (;;)
4180 {
4181 char szBuf[256];
4182 uint32_t cbInstr;
4183 int rc = DBGFR3DisasInstrEx(pVM->pUVM,
4184 pVCpu->idCpu,
4185 cs,
4186 eip,
4187 DBGF_DISAS_FLAGS_DEFAULT_MODE,
4188 szBuf, sizeof(szBuf),
4189 &cbInstr);
4190 if (RT_SUCCESS(rc))
4191 RTLogPrintf("%llx %s\n", (uint64_t)uCode, szBuf);
4192 else
4193 {
4194 RTLogPrintf("%llx %04x:%llx: %s\n", (uint64_t)uCode, cs, (uint64_t)eip, szBuf);
4195 cbInstr = 1;
4196 }
4197
4198 /* next */
4199 if (cb <= cbInstr)
4200 break;
4201 cb -= cbInstr;
4202 uCode += cbInstr;
4203 eip += cbInstr;
4204 }
4205 }
4206}
4207
4208
4209/**
4210 * Looks up a guest symbol.
4211 *
4212 * @returns Pointer to symbol name. This is a static buffer.
4213 * @param orig_addr The address in question.
4214 */
4215const char *lookup_symbol(target_ulong orig_addr)
4216{
4217 PVM pVM = cpu_single_env->pVM;
4218 RTGCINTPTR off = 0;
4219 RTDBGSYMBOL Sym;
4220 DBGFADDRESS Addr;
4221
4222 int rc = DBGFR3AsSymbolByAddr(pVM->pUVM, DBGF_AS_GLOBAL, DBGFR3AddrFromFlat(pVM->pUVM, &Addr, orig_addr),
4223 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL, &off, &Sym, NULL /*phMod*/);
4224 if (RT_SUCCESS(rc))
4225 {
4226 static char szSym[sizeof(Sym.szName) + 48];
4227 if (!off)
4228 RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
4229 else if (off > 0)
4230 RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
4231 else
4232 RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
4233 return szSym;
4234 }
4235 return "<N/A>";
4236}
4237
4238
4239#undef LOG_GROUP
4240#define LOG_GROUP LOG_GROUP_REM
4241
4242
4243/* -+- FF notifications -+- */
4244
4245
4246/**
4247 * Notification about a pending interrupt.
4248 *
4249 * @param pVM VM Handle.
4250 * @param pVCpu VMCPU Handle.
4251 * @param u8Interrupt Interrupt
4252 * @thread The emulation thread.
4253 */
4254REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCpu, uint8_t u8Interrupt)
4255{
4256 Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
4257 pVM->rem.s.u32PendingInterrupt = u8Interrupt;
4258}
4259
4260/**
4261 * Notification about a pending interrupt.
4262 *
4263 * @returns Pending interrupt or REM_NO_PENDING_IRQ
4264 * @param pVM VM Handle.
4265 * @param pVCpu VMCPU Handle.
4266 * @thread The emulation thread.
4267 */
4268REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM, PVMCPU pVCpu)
4269{
4270 return pVM->rem.s.u32PendingInterrupt;
4271}
4272
4273/**
4274 * Notification about the interrupt FF being set.
4275 *
4276 * @param pVM VM Handle.
4277 * @param pVCpu VMCPU Handle.
4278 * @thread The emulation thread.
4279 */
4280REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu)
4281{
4282#ifndef IEM_VERIFICATION_MODE
4283 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
4284 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
4285 if (pVM->rem.s.fInREM)
4286 {
4287 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4288 CPU_INTERRUPT_EXTERNAL_HARD);
4289 }
4290#endif
4291}
4292
4293
4294/**
4295 * Notification about the interrupt FF being set.
4296 *
4297 * @param pVM VM Handle.
4298 * @param pVCpu VMCPU Handle.
4299 * @thread Any.
4300 */
4301REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu)
4302{
4303 LogFlow(("REMR3NotifyInterruptClear:\n"));
4304 if (pVM->rem.s.fInREM)
4305 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
4306}
4307
4308
4309/**
4310 * Notification about pending timer(s).
4311 *
4312 * @param pVM VM Handle.
4313 * @param pVCpuDst The target cpu for this notification.
4314 * TM will not broadcast pending timer events, but use
4315 * a dedicated EMT for them. So, only interrupt REM
4316 * execution if the given CPU is executing in REM.
4317 * @thread Any.
4318 */
4319REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM, PVMCPU pVCpuDst)
4320{
4321#ifndef IEM_VERIFICATION_MODE
4322#ifndef DEBUG_bird
4323 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
4324#endif
4325 if (pVM->rem.s.fInREM)
4326 {
4327 if (pVM->rem.s.Env.pVCpu == pVCpuDst)
4328 {
4329 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: setting\n"));
4330 ASMAtomicOrS32((int32_t volatile *)&pVM->rem.s.Env.interrupt_request,
4331 CPU_INTERRUPT_EXTERNAL_TIMER);
4332 }
4333 else
4334 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: pVCpu:%p != pVCpuDst:%p\n", pVM->rem.s.Env.pVCpu, pVCpuDst));
4335 }
4336 else
4337 LogIt(RTLOGGRPFLAGS_LEVEL_5, LOG_GROUP_TM, ("REMR3NotifyTimerPending: !fInREM; cpu state=%d\n", VMCPU_GET_STATE(pVCpuDst)));
4338#endif
4339}
4340
4341
4342/**
4343 * Notification about pending DMA transfers.
4344 *
4345 * @param pVM VM Handle.
4346 * @thread Any.
4347 */
4348REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
4349{
4350#ifndef IEM_VERIFICATION_MODE
4351 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
4352 if (pVM->rem.s.fInREM)
4353 {
4354 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4355 CPU_INTERRUPT_EXTERNAL_DMA);
4356 }
4357#endif
4358}
4359
4360
4361/**
4362 * Notification about pending timer(s).
4363 *
4364 * @param pVM VM Handle.
4365 * @thread Any.
4366 */
4367REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
4368{
4369#ifndef IEM_VERIFICATION_MODE
4370 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
4371 if (pVM->rem.s.fInREM)
4372 {
4373 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4374 CPU_INTERRUPT_EXTERNAL_EXIT);
4375 }
4376#endif
4377}
4378
4379
4380/**
4381 * Notification about pending FF set by an external thread.
4382 *
4383 * @param pVM VM handle.
4384 * @thread Any.
4385 */
4386REMR3DECL(void) REMR3NotifyFF(PVM pVM)
4387{
4388#ifndef IEM_VERIFICATION_MODE
4389 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
4390 if (pVM->rem.s.fInREM)
4391 {
4392 ASMAtomicOrS32((int32_t volatile *)&cpu_single_env->interrupt_request,
4393 CPU_INTERRUPT_EXTERNAL_EXIT);
4394 }
4395#endif
4396}
4397
4398
4399#ifdef VBOX_WITH_STATISTICS
4400void remR3ProfileStart(int statcode)
4401{
4402 STAMPROFILEADV *pStat;
4403 switch(statcode)
4404 {
4405 case STATS_EMULATE_SINGLE_INSTR:
4406 pStat = &gStatExecuteSingleInstr;
4407 break;
4408 case STATS_QEMU_COMPILATION:
4409 pStat = &gStatCompilationQEmu;
4410 break;
4411 case STATS_QEMU_RUN_EMULATED_CODE:
4412 pStat = &gStatRunCodeQEmu;
4413 break;
4414 case STATS_QEMU_TOTAL:
4415 pStat = &gStatTotalTimeQEmu;
4416 break;
4417 case STATS_QEMU_RUN_TIMERS:
4418 pStat = &gStatTimers;
4419 break;
4420 case STATS_TLB_LOOKUP:
4421 pStat= &gStatTBLookup;
4422 break;
4423 case STATS_IRQ_HANDLING:
4424 pStat= &gStatIRQ;
4425 break;
4426 case STATS_RAW_CHECK:
4427 pStat = &gStatRawCheck;
4428 break;
4429
4430 default:
4431 AssertMsgFailed(("unknown stat %d\n", statcode));
4432 return;
4433 }
4434 STAM_PROFILE_ADV_START(pStat, a);
4435}
4436
4437
4438void remR3ProfileStop(int statcode)
4439{
4440 STAMPROFILEADV *pStat;
4441 switch(statcode)
4442 {
4443 case STATS_EMULATE_SINGLE_INSTR:
4444 pStat = &gStatExecuteSingleInstr;
4445 break;
4446 case STATS_QEMU_COMPILATION:
4447 pStat = &gStatCompilationQEmu;
4448 break;
4449 case STATS_QEMU_RUN_EMULATED_CODE:
4450 pStat = &gStatRunCodeQEmu;
4451 break;
4452 case STATS_QEMU_TOTAL:
4453 pStat = &gStatTotalTimeQEmu;
4454 break;
4455 case STATS_QEMU_RUN_TIMERS:
4456 pStat = &gStatTimers;
4457 break;
4458 case STATS_TLB_LOOKUP:
4459 pStat= &gStatTBLookup;
4460 break;
4461 case STATS_IRQ_HANDLING:
4462 pStat= &gStatIRQ;
4463 break;
4464 case STATS_RAW_CHECK:
4465 pStat = &gStatRawCheck;
4466 break;
4467 default:
4468 AssertMsgFailed(("unknown stat %d\n", statcode));
4469 return;
4470 }
4471 STAM_PROFILE_ADV_STOP(pStat, a);
4472}
4473#endif
4474
4475/**
4476 * Raise an RC, force rem exit.
4477 *
4478 * @param pVM VM handle.
4479 * @param rc The rc.
4480 */
4481void remR3RaiseRC(PVM pVM, int rc)
4482{
4483 Log(("remR3RaiseRC: rc=%Rrc\n", rc));
4484 Assert(pVM->rem.s.fInREM);
4485 VM_ASSERT_EMT(pVM);
4486 pVM->rem.s.rc = rc;
4487 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
4488}
4489
4490
4491/* -+- timers -+- */
4492
4493uint64_t cpu_get_tsc(CPUX86State *env)
4494{
4495 STAM_COUNTER_INC(&gStatCpuGetTSC);
4496 return TMCpuTickGet(env->pVCpu);
4497}
4498
4499
4500/* -+- interrupts -+- */
4501
4502void cpu_set_ferr(CPUX86State *env)
4503{
4504 int rc = PDMIsaSetIrq(env->pVM, 13, 1, 0 /*uTagSrc*/);
4505 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
4506}
4507
4508int cpu_get_pic_interrupt(CPUX86State *env)
4509{
4510 uint8_t u8Interrupt;
4511 int rc;
4512
4513#ifdef VBOX_WITH_NEW_APIC
4514 if (VMCPU_FF_TEST_AND_CLEAR(env->pVCpu, VMCPU_FF_UPDATE_APIC))
4515 APICUpdatePendingInterrupts(env->pVCpu);
4516#endif
4517
4518 /* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
4519 * In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
4520 * with the (a)pic.
4521 */
4522 /* Note! We assume we will go directly to the recompiler to handle the pending interrupt! */
4523 /** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
4524 * if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4525 * remove this kludge. */
4526 if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4527 {
4528 rc = VINF_SUCCESS;
4529 Assert(env->pVM->rem.s.u32PendingInterrupt <= 255);
4530 u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4531 env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4532 }
4533 else
4534 rc = PDMGetInterrupt(env->pVCpu, &u8Interrupt);
4535
4536 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Rrc pc=%04x:%08llx ~flags=%08llx\n",
4537 u8Interrupt, rc, env->segs[R_CS].selector, (uint64_t)env->eip, (uint64_t)env->eflags));
4538 if (RT_SUCCESS(rc))
4539 {
4540 if (VMCPU_FF_IS_PENDING(env->pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
4541 env->interrupt_request |= CPU_INTERRUPT_HARD;
4542 return u8Interrupt;
4543 }
4544 return -1;
4545}
4546
4547
4548/* -+- local apic -+- */
4549
4550#if 0 /* CPUMSetGuestMsr does this now. */
4551void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4552{
4553 int rc = PDMApicSetBase(env->pVM, val);
4554 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Rrc\n", val, rc)); NOREF(rc);
4555}
4556#endif
4557
4558uint64_t cpu_get_apic_base(CPUX86State *env)
4559{
4560 uint64_t u64;
4561 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64);
4562 if (RT_SUCCESS(rcStrict))
4563 {
4564 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4565 return u64;
4566 }
4567 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
4568 return 0;
4569}
4570
4571void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4572{
4573 int rc = PDMApicSetTPR(env->pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4574 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Rrc\n", val, rc)); NOREF(rc);
4575}
4576
4577uint8_t cpu_get_apic_tpr(CPUX86State *env)
4578{
4579 uint8_t u8;
4580 int rc = PDMApicGetTPR(env->pVCpu, &u8, NULL, NULL);
4581 if (RT_SUCCESS(rc))
4582 {
4583 LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4584 return u8 >> 4; /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
4585 }
4586 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Rrc)\n", rc));
4587 return 0;
4588}
4589
4590/**
4591 * Read an MSR.
4592 *
4593 * @retval 0 success.
4594 * @retval -1 failure, raise \#GP(0).
4595 * @param env The cpu state.
4596 * @param idMsr The MSR to read.
4597 * @param puValue Where to return the value.
4598 */
4599int cpu_rdmsr(CPUX86State *env, uint32_t idMsr, uint64_t *puValue)
4600{
4601 Assert(env->pVCpu);
4602 return CPUMQueryGuestMsr(env->pVCpu, idMsr, puValue) == VINF_SUCCESS ? 0 : -1;
4603}
4604
4605/**
4606 * Write to an MSR.
4607 *
4608 * @retval 0 success.
4609 * @retval -1 failure, raise \#GP(0).
4610 * @param env The cpu state.
4611 * @param idMsr The MSR to write to.
4612 * @param uValue The value to write.
4613 */
4614int cpu_wrmsr(CPUX86State *env, uint32_t idMsr, uint64_t uValue)
4615{
4616 Assert(env->pVCpu);
4617 return CPUMSetGuestMsr(env->pVCpu, idMsr, uValue) == VINF_SUCCESS ? 0 : -1;
4618}
4619
4620/* -+- I/O Ports -+- */
4621
4622#undef LOG_GROUP
4623#define LOG_GROUP LOG_GROUP_REM_IOPORT
4624
4625void cpu_outb(CPUX86State *env, pio_addr_t addr, uint8_t val)
4626{
4627 int rc;
4628
4629 if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4630 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4631
4632 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 1);
4633 if (RT_LIKELY(rc == VINF_SUCCESS))
4634 return;
4635 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4636 {
4637 Log(("cpu_outb: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4638 remR3RaiseRC(env->pVM, rc);
4639 return;
4640 }
4641 remAbort(rc, __FUNCTION__);
4642}
4643
4644void cpu_outw(CPUX86State *env, pio_addr_t addr, uint16_t val)
4645{
4646 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4647 int rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 2);
4648 if (RT_LIKELY(rc == VINF_SUCCESS))
4649 return;
4650 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4651 {
4652 Log(("cpu_outw: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4653 remR3RaiseRC(env->pVM, rc);
4654 return;
4655 }
4656 remAbort(rc, __FUNCTION__);
4657}
4658
4659void cpu_outl(CPUX86State *env, pio_addr_t addr, uint32_t val)
4660{
4661 int rc;
4662 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4663 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 4);
4664 if (RT_LIKELY(rc == VINF_SUCCESS))
4665 return;
4666 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4667 {
4668 Log(("cpu_outl: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4669 remR3RaiseRC(env->pVM, rc);
4670 return;
4671 }
4672 remAbort(rc, __FUNCTION__);
4673}
4674
4675uint8_t cpu_inb(CPUX86State *env, pio_addr_t addr)
4676{
4677 uint32_t u32 = 0;
4678 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 1);
4679 if (RT_LIKELY(rc == VINF_SUCCESS))
4680 {
4681 if (/*addr != 0x61 && */addr != 0x71)
4682 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4683 return (uint8_t)u32;
4684 }
4685 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4686 {
4687 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4688 remR3RaiseRC(env->pVM, rc);
4689 return (uint8_t)u32;
4690 }
4691 remAbort(rc, __FUNCTION__);
4692 return UINT8_C(0xff);
4693}
4694
4695uint16_t cpu_inw(CPUX86State *env, pio_addr_t addr)
4696{
4697 uint32_t u32 = 0;
4698 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 2);
4699 if (RT_LIKELY(rc == VINF_SUCCESS))
4700 {
4701 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4702 return (uint16_t)u32;
4703 }
4704 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4705 {
4706 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4707 remR3RaiseRC(env->pVM, rc);
4708 return (uint16_t)u32;
4709 }
4710 remAbort(rc, __FUNCTION__);
4711 return UINT16_C(0xffff);
4712}
4713
4714uint32_t cpu_inl(CPUX86State *env, pio_addr_t addr)
4715{
4716 uint32_t u32 = 0;
4717 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 4);
4718 if (RT_LIKELY(rc == VINF_SUCCESS))
4719 {
4720 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4721 return u32;
4722 }
4723 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4724 {
4725 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4726 remR3RaiseRC(env->pVM, rc);
4727 return u32;
4728 }
4729 remAbort(rc, __FUNCTION__);
4730 return UINT32_C(0xffffffff);
4731}
4732
4733#undef LOG_GROUP
4734#define LOG_GROUP LOG_GROUP_REM
4735
4736
4737/* -+- helpers and misc other interfaces -+- */
4738
4739/**
4740 * Perform the CPUID instruction.
4741 *
4742 * @param env Pointer to the recompiler CPU structure.
4743 * @param idx The CPUID leaf (eax).
4744 * @param idxSub The CPUID sub-leaf (ecx) where applicable.
4745 * @param pEAX Where to store eax.
4746 * @param pEBX Where to store ebx.
4747 * @param pECX Where to store ecx.
4748 * @param pEDX Where to store edx.
4749 */
4750void cpu_x86_cpuid(CPUX86State *env, uint32_t idx, uint32_t idxSub,
4751 uint32_t *pEAX, uint32_t *pEBX, uint32_t *pECX, uint32_t *pEDX)
4752{
4753 NOREF(idxSub);
4754 CPUMGetGuestCpuId(env->pVCpu, idx, idxSub, pEAX, pEBX, pECX, pEDX);
4755}
4756
4757
4758#if 0 /* not used */
4759/**
4760 * Interface for qemu hardware to report back fatal errors.
4761 */
4762void hw_error(const char *pszFormat, ...)
4763{
4764 /*
4765 * Bitch about it.
4766 */
4767 /** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4768 * this in my Odin32 tree at home! */
4769 va_list args;
4770 va_start(args, pszFormat);
4771 RTLogPrintf("fatal error in virtual hardware:");
4772 RTLogPrintfV(pszFormat, args);
4773 va_end(args);
4774 AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4775
4776 /*
4777 * If we're in REM context we'll sync back the state before 'jumping' to
4778 * the EMs failure handling.
4779 */
4780 PVM pVM = cpu_single_env->pVM;
4781 if (pVM->rem.s.fInREM)
4782 REMR3StateBack(pVM);
4783 EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4784 AssertMsgFailed(("EMR3FatalError returned!\n"));
4785}
4786#endif
4787
4788/**
4789 * Interface for the qemu cpu to report unhandled situation
4790 * raising a fatal VM error.
4791 */
4792void cpu_abort(CPUX86State *env, const char *pszFormat, ...)
4793{
4794 va_list va;
4795 PVM pVM;
4796 PVMCPU pVCpu;
4797 char szMsg[256];
4798
4799 /*
4800 * Bitch about it.
4801 */
4802 RTLogFlags(NULL, "nodisabled nobuffered");
4803 RTLogFlush(NULL);
4804
4805 va_start(va, pszFormat);
4806#if defined(RT_OS_WINDOWS) && ARCH_BITS == 64
4807 /* It's a bit complicated when mixing MSC and GCC on AMD64. This is a bit ugly, but it works. */
4808 unsigned cArgs = 0;
4809 uintptr_t auArgs[6] = {0,0,0,0,0,0};
4810 const char *psz = strchr(pszFormat, '%');
4811 while (psz && cArgs < 6)
4812 {
4813 auArgs[cArgs++] = va_arg(va, uintptr_t);
4814 psz = strchr(psz + 1, '%');
4815 }
4816 switch (cArgs)
4817 {
4818 case 1: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0]); break;
4819 case 2: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1]); break;
4820 case 3: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2]); break;
4821 case 4: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3]); break;
4822 case 5: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3], auArgs[4]); break;
4823 case 6: RTStrPrintf(szMsg, sizeof(szMsg), pszFormat, auArgs[0], auArgs[1], auArgs[2], auArgs[3], auArgs[4], auArgs[5]); break;
4824 default:
4825 case 0: RTStrPrintf(szMsg, sizeof(szMsg), "%s", pszFormat); break;
4826 }
4827#else
4828 RTStrPrintfV(szMsg, sizeof(szMsg), pszFormat, va);
4829#endif
4830 va_end(va);
4831
4832 RTLogPrintf("fatal error in recompiler cpu: %s\n", szMsg);
4833 RTLogRelPrintf("fatal error in recompiler cpu: %s\n", szMsg);
4834
4835 /*
4836 * If we're in REM context we'll sync back the state before 'jumping' to
4837 * the EMs failure handling.
4838 */
4839 pVM = cpu_single_env->pVM;
4840 pVCpu = cpu_single_env->pVCpu;
4841 Assert(pVCpu);
4842
4843 if (pVM->rem.s.fInREM)
4844 REMR3StateBack(pVM, pVCpu);
4845 EMR3FatalError(pVCpu, VERR_REM_VIRTUAL_CPU_ERROR);
4846 AssertMsgFailed(("EMR3FatalError returned!\n"));
4847}
4848
4849
4850/**
4851 * Aborts the VM.
4852 *
4853 * @param rc VBox error code.
4854 * @param pszTip Hint about why/when this happened.
4855 */
4856void remAbort(int rc, const char *pszTip)
4857{
4858 PVM pVM;
4859 PVMCPU pVCpu;
4860
4861 /*
4862 * Bitch about it.
4863 */
4864 RTLogPrintf("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip);
4865 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip));
4866
4867 /*
4868 * Jump back to where we entered the recompiler.
4869 */
4870 pVM = cpu_single_env->pVM;
4871 pVCpu = cpu_single_env->pVCpu;
4872 Assert(pVCpu);
4873
4874 if (pVM->rem.s.fInREM)
4875 REMR3StateBack(pVM, pVCpu);
4876
4877 EMR3FatalError(pVCpu, rc);
4878 AssertMsgFailed(("EMR3FatalError returned!\n"));
4879}
4880
4881
4882/**
4883 * Dumps a linux system call.
4884 * @param pVCpu VMCPU handle.
4885 */
4886void remR3DumpLnxSyscall(PVMCPU pVCpu)
4887{
4888 static const char *apsz[] =
4889 {
4890 "sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4891 "sys_exit",
4892 "sys_fork",
4893 "sys_read",
4894 "sys_write",
4895 "sys_open", /* 5 */
4896 "sys_close",
4897 "sys_waitpid",
4898 "sys_creat",
4899 "sys_link",
4900 "sys_unlink", /* 10 */
4901 "sys_execve",
4902 "sys_chdir",
4903 "sys_time",
4904 "sys_mknod",
4905 "sys_chmod", /* 15 */
4906 "sys_lchown16",
4907 "sys_ni_syscall", /* old break syscall holder */
4908 "sys_stat",
4909 "sys_lseek",
4910 "sys_getpid", /* 20 */
4911 "sys_mount",
4912 "sys_oldumount",
4913 "sys_setuid16",
4914 "sys_getuid16",
4915 "sys_stime", /* 25 */
4916 "sys_ptrace",
4917 "sys_alarm",
4918 "sys_fstat",
4919 "sys_pause",
4920 "sys_utime", /* 30 */
4921 "sys_ni_syscall", /* old stty syscall holder */
4922 "sys_ni_syscall", /* old gtty syscall holder */
4923 "sys_access",
4924 "sys_nice",
4925 "sys_ni_syscall", /* 35 - old ftime syscall holder */
4926 "sys_sync",
4927 "sys_kill",
4928 "sys_rename",
4929 "sys_mkdir",
4930 "sys_rmdir", /* 40 */
4931 "sys_dup",
4932 "sys_pipe",
4933 "sys_times",
4934 "sys_ni_syscall", /* old prof syscall holder */
4935 "sys_brk", /* 45 */
4936 "sys_setgid16",
4937 "sys_getgid16",
4938 "sys_signal",
4939 "sys_geteuid16",
4940 "sys_getegid16", /* 50 */
4941 "sys_acct",
4942 "sys_umount", /* recycled never used phys() */
4943 "sys_ni_syscall", /* old lock syscall holder */
4944 "sys_ioctl",
4945 "sys_fcntl", /* 55 */
4946 "sys_ni_syscall", /* old mpx syscall holder */
4947 "sys_setpgid",
4948 "sys_ni_syscall", /* old ulimit syscall holder */
4949 "sys_olduname",
4950 "sys_umask", /* 60 */
4951 "sys_chroot",
4952 "sys_ustat",
4953 "sys_dup2",
4954 "sys_getppid",
4955 "sys_getpgrp", /* 65 */
4956 "sys_setsid",
4957 "sys_sigaction",
4958 "sys_sgetmask",
4959 "sys_ssetmask",
4960 "sys_setreuid16", /* 70 */
4961 "sys_setregid16",
4962 "sys_sigsuspend",
4963 "sys_sigpending",
4964 "sys_sethostname",
4965 "sys_setrlimit", /* 75 */
4966 "sys_old_getrlimit",
4967 "sys_getrusage",
4968 "sys_gettimeofday",
4969 "sys_settimeofday",
4970 "sys_getgroups16", /* 80 */
4971 "sys_setgroups16",
4972 "old_select",
4973 "sys_symlink",
4974 "sys_lstat",
4975 "sys_readlink", /* 85 */
4976 "sys_uselib",
4977 "sys_swapon",
4978 "sys_reboot",
4979 "old_readdir",
4980 "old_mmap", /* 90 */
4981 "sys_munmap",
4982 "sys_truncate",
4983 "sys_ftruncate",
4984 "sys_fchmod",
4985 "sys_fchown16", /* 95 */
4986 "sys_getpriority",
4987 "sys_setpriority",
4988 "sys_ni_syscall", /* old profil syscall holder */
4989 "sys_statfs",
4990 "sys_fstatfs", /* 100 */
4991 "sys_ioperm",
4992 "sys_socketcall",
4993 "sys_syslog",
4994 "sys_setitimer",
4995 "sys_getitimer", /* 105 */
4996 "sys_newstat",
4997 "sys_newlstat",
4998 "sys_newfstat",
4999 "sys_uname",
5000 "sys_iopl", /* 110 */
5001 "sys_vhangup",
5002 "sys_ni_syscall", /* old "idle" system call */
5003 "sys_vm86old",
5004 "sys_wait4",
5005 "sys_swapoff", /* 115 */
5006 "sys_sysinfo",
5007 "sys_ipc",
5008 "sys_fsync",
5009 "sys_sigreturn",
5010 "sys_clone", /* 120 */
5011 "sys_setdomainname",
5012 "sys_newuname",
5013 "sys_modify_ldt",
5014 "sys_adjtimex",
5015 "sys_mprotect", /* 125 */
5016 "sys_sigprocmask",
5017 "sys_ni_syscall", /* old "create_module" */
5018 "sys_init_module",
5019 "sys_delete_module",
5020 "sys_ni_syscall", /* 130: old "get_kernel_syms" */
5021 "sys_quotactl",
5022 "sys_getpgid",
5023 "sys_fchdir",
5024 "sys_bdflush",
5025 "sys_sysfs", /* 135 */
5026 "sys_personality",
5027 "sys_ni_syscall", /* reserved for afs_syscall */
5028 "sys_setfsuid16",
5029 "sys_setfsgid16",
5030 "sys_llseek", /* 140 */
5031 "sys_getdents",
5032 "sys_select",
5033 "sys_flock",
5034 "sys_msync",
5035 "sys_readv", /* 145 */
5036 "sys_writev",
5037 "sys_getsid",
5038 "sys_fdatasync",
5039 "sys_sysctl",
5040 "sys_mlock", /* 150 */
5041 "sys_munlock",
5042 "sys_mlockall",
5043 "sys_munlockall",
5044 "sys_sched_setparam",
5045 "sys_sched_getparam", /* 155 */
5046 "sys_sched_setscheduler",
5047 "sys_sched_getscheduler",
5048 "sys_sched_yield",
5049 "sys_sched_get_priority_max",
5050 "sys_sched_get_priority_min", /* 160 */
5051 "sys_sched_rr_get_interval",
5052 "sys_nanosleep",
5053 "sys_mremap",
5054 "sys_setresuid16",
5055 "sys_getresuid16", /* 165 */
5056 "sys_vm86",
5057 "sys_ni_syscall", /* Old sys_query_module */
5058 "sys_poll",
5059 "sys_nfsservctl",
5060 "sys_setresgid16", /* 170 */
5061 "sys_getresgid16",
5062 "sys_prctl",
5063 "sys_rt_sigreturn",
5064 "sys_rt_sigaction",
5065 "sys_rt_sigprocmask", /* 175 */
5066 "sys_rt_sigpending",
5067 "sys_rt_sigtimedwait",
5068 "sys_rt_sigqueueinfo",
5069 "sys_rt_sigsuspend",
5070 "sys_pread64", /* 180 */
5071 "sys_pwrite64",
5072 "sys_chown16",
5073 "sys_getcwd",
5074 "sys_capget",
5075 "sys_capset", /* 185 */
5076 "sys_sigaltstack",
5077 "sys_sendfile",
5078 "sys_ni_syscall", /* reserved for streams1 */
5079 "sys_ni_syscall", /* reserved for streams2 */
5080 "sys_vfork", /* 190 */
5081 "sys_getrlimit",
5082 "sys_mmap2",
5083 "sys_truncate64",
5084 "sys_ftruncate64",
5085 "sys_stat64", /* 195 */
5086 "sys_lstat64",
5087 "sys_fstat64",
5088 "sys_lchown",
5089 "sys_getuid",
5090 "sys_getgid", /* 200 */
5091 "sys_geteuid",
5092 "sys_getegid",
5093 "sys_setreuid",
5094 "sys_setregid",
5095 "sys_getgroups", /* 205 */
5096 "sys_setgroups",
5097 "sys_fchown",
5098 "sys_setresuid",
5099 "sys_getresuid",
5100 "sys_setresgid", /* 210 */
5101 "sys_getresgid",
5102 "sys_chown",
5103 "sys_setuid",
5104 "sys_setgid",
5105 "sys_setfsuid", /* 215 */
5106 "sys_setfsgid",
5107 "sys_pivot_root",
5108 "sys_mincore",
5109 "sys_madvise",
5110 "sys_getdents64", /* 220 */
5111 "sys_fcntl64",
5112 "sys_ni_syscall", /* reserved for TUX */
5113 "sys_ni_syscall",
5114 "sys_gettid",
5115 "sys_readahead", /* 225 */
5116 "sys_setxattr",
5117 "sys_lsetxattr",
5118 "sys_fsetxattr",
5119 "sys_getxattr",
5120 "sys_lgetxattr", /* 230 */
5121 "sys_fgetxattr",
5122 "sys_listxattr",
5123 "sys_llistxattr",
5124 "sys_flistxattr",
5125 "sys_removexattr", /* 235 */
5126 "sys_lremovexattr",
5127 "sys_fremovexattr",
5128 "sys_tkill",
5129 "sys_sendfile64",
5130 "sys_futex", /* 240 */
5131 "sys_sched_setaffinity",
5132 "sys_sched_getaffinity",
5133 "sys_set_thread_area",
5134 "sys_get_thread_area",
5135 "sys_io_setup", /* 245 */
5136 "sys_io_destroy",
5137 "sys_io_getevents",
5138 "sys_io_submit",
5139 "sys_io_cancel",
5140 "sys_fadvise64", /* 250 */
5141 "sys_ni_syscall",
5142 "sys_exit_group",
5143 "sys_lookup_dcookie",
5144 "sys_epoll_create",
5145 "sys_epoll_ctl", /* 255 */
5146 "sys_epoll_wait",
5147 "sys_remap_file_pages",
5148 "sys_set_tid_address",
5149 "sys_timer_create",
5150 "sys_timer_settime", /* 260 */
5151 "sys_timer_gettime",
5152 "sys_timer_getoverrun",
5153 "sys_timer_delete",
5154 "sys_clock_settime",
5155 "sys_clock_gettime", /* 265 */
5156 "sys_clock_getres",
5157 "sys_clock_nanosleep",
5158 "sys_statfs64",
5159 "sys_fstatfs64",
5160 "sys_tgkill", /* 270 */
5161 "sys_utimes",
5162 "sys_fadvise64_64",
5163 "sys_ni_syscall" /* sys_vserver */
5164 };
5165
5166 uint32_t uEAX = CPUMGetGuestEAX(pVCpu);
5167 switch (uEAX)
5168 {
5169 default:
5170 if (uEAX < RT_ELEMENTS(apsz))
5171 Log(("REM: linux syscall %3d: %s (eip=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
5172 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), CPUMGetGuestEBX(pVCpu), CPUMGetGuestECX(pVCpu),
5173 CPUMGetGuestEDX(pVCpu), CPUMGetGuestESI(pVCpu), CPUMGetGuestEDI(pVCpu), CPUMGetGuestEBP(pVCpu)));
5174 else
5175 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX));
5176 break;
5177
5178 }
5179}
5180
5181
5182/**
5183 * Dumps an OpenBSD system call.
5184 * @param pVCpu VMCPU handle.
5185 */
5186void remR3DumpOBsdSyscall(PVMCPU pVCpu)
5187{
5188 static const char *apsz[] =
5189 {
5190 "SYS_syscall", //0
5191 "SYS_exit", //1
5192 "SYS_fork", //2
5193 "SYS_read", //3
5194 "SYS_write", //4
5195 "SYS_open", //5
5196 "SYS_close", //6
5197 "SYS_wait4", //7
5198 "SYS_8",
5199 "SYS_link", //9
5200 "SYS_unlink", //10
5201 "SYS_11",
5202 "SYS_chdir", //12
5203 "SYS_fchdir", //13
5204 "SYS_mknod", //14
5205 "SYS_chmod", //15
5206 "SYS_chown", //16
5207 "SYS_break", //17
5208 "SYS_18",
5209 "SYS_19",
5210 "SYS_getpid", //20
5211 "SYS_mount", //21
5212 "SYS_unmount", //22
5213 "SYS_setuid", //23
5214 "SYS_getuid", //24
5215 "SYS_geteuid", //25
5216 "SYS_ptrace", //26
5217 "SYS_recvmsg", //27
5218 "SYS_sendmsg", //28
5219 "SYS_recvfrom", //29
5220 "SYS_accept", //30
5221 "SYS_getpeername", //31
5222 "SYS_getsockname", //32
5223 "SYS_access", //33
5224 "SYS_chflags", //34
5225 "SYS_fchflags", //35
5226 "SYS_sync", //36
5227 "SYS_kill", //37
5228 "SYS_38",
5229 "SYS_getppid", //39
5230 "SYS_40",
5231 "SYS_dup", //41
5232 "SYS_opipe", //42
5233 "SYS_getegid", //43
5234 "SYS_profil", //44
5235 "SYS_ktrace", //45
5236 "SYS_sigaction", //46
5237 "SYS_getgid", //47
5238 "SYS_sigprocmask", //48
5239 "SYS_getlogin", //49
5240 "SYS_setlogin", //50
5241 "SYS_acct", //51
5242 "SYS_sigpending", //52
5243 "SYS_osigaltstack", //53
5244 "SYS_ioctl", //54
5245 "SYS_reboot", //55
5246 "SYS_revoke", //56
5247 "SYS_symlink", //57
5248 "SYS_readlink", //58
5249 "SYS_execve", //59
5250 "SYS_umask", //60
5251 "SYS_chroot", //61
5252 "SYS_62",
5253 "SYS_63",
5254 "SYS_64",
5255 "SYS_65",
5256 "SYS_vfork", //66
5257 "SYS_67",
5258 "SYS_68",
5259 "SYS_sbrk", //69
5260 "SYS_sstk", //70
5261 "SYS_61",
5262 "SYS_vadvise", //72
5263 "SYS_munmap", //73
5264 "SYS_mprotect", //74
5265 "SYS_madvise", //75
5266 "SYS_76",
5267 "SYS_77",
5268 "SYS_mincore", //78
5269 "SYS_getgroups", //79
5270 "SYS_setgroups", //80
5271 "SYS_getpgrp", //81
5272 "SYS_setpgid", //82
5273 "SYS_setitimer", //83
5274 "SYS_84",
5275 "SYS_85",
5276 "SYS_getitimer", //86
5277 "SYS_87",
5278 "SYS_88",
5279 "SYS_89",
5280 "SYS_dup2", //90
5281 "SYS_91",
5282 "SYS_fcntl", //92
5283 "SYS_select", //93
5284 "SYS_94",
5285 "SYS_fsync", //95
5286 "SYS_setpriority", //96
5287 "SYS_socket", //97
5288 "SYS_connect", //98
5289 "SYS_99",
5290 "SYS_getpriority", //100
5291 "SYS_101",
5292 "SYS_102",
5293 "SYS_sigreturn", //103
5294 "SYS_bind", //104
5295 "SYS_setsockopt", //105
5296 "SYS_listen", //106
5297 "SYS_107",
5298 "SYS_108",
5299 "SYS_109",
5300 "SYS_110",
5301 "SYS_sigsuspend", //111
5302 "SYS_112",
5303 "SYS_113",
5304 "SYS_114",
5305 "SYS_115",
5306 "SYS_gettimeofday", //116
5307 "SYS_getrusage", //117
5308 "SYS_getsockopt", //118
5309 "SYS_119",
5310 "SYS_readv", //120
5311 "SYS_writev", //121
5312 "SYS_settimeofday", //122
5313 "SYS_fchown", //123
5314 "SYS_fchmod", //124
5315 "SYS_125",
5316 "SYS_setreuid", //126
5317 "SYS_setregid", //127
5318 "SYS_rename", //128
5319 "SYS_129",
5320 "SYS_130",
5321 "SYS_flock", //131
5322 "SYS_mkfifo", //132
5323 "SYS_sendto", //133
5324 "SYS_shutdown", //134
5325 "SYS_socketpair", //135
5326 "SYS_mkdir", //136
5327 "SYS_rmdir", //137
5328 "SYS_utimes", //138
5329 "SYS_139",
5330 "SYS_adjtime", //140
5331 "SYS_141",
5332 "SYS_142",
5333 "SYS_143",
5334 "SYS_144",
5335 "SYS_145",
5336 "SYS_146",
5337 "SYS_setsid", //147
5338 "SYS_quotactl", //148
5339 "SYS_149",
5340 "SYS_150",
5341 "SYS_151",
5342 "SYS_152",
5343 "SYS_153",
5344 "SYS_154",
5345 "SYS_nfssvc", //155
5346 "SYS_156",
5347 "SYS_157",
5348 "SYS_158",
5349 "SYS_159",
5350 "SYS_160",
5351 "SYS_getfh", //161
5352 "SYS_162",
5353 "SYS_163",
5354 "SYS_164",
5355 "SYS_sysarch", //165
5356 "SYS_166",
5357 "SYS_167",
5358 "SYS_168",
5359 "SYS_169",
5360 "SYS_170",
5361 "SYS_171",
5362 "SYS_172",
5363 "SYS_pread", //173
5364 "SYS_pwrite", //174
5365 "SYS_175",
5366 "SYS_176",
5367 "SYS_177",
5368 "SYS_178",
5369 "SYS_179",
5370 "SYS_180",
5371 "SYS_setgid", //181
5372 "SYS_setegid", //182
5373 "SYS_seteuid", //183
5374 "SYS_lfs_bmapv", //184
5375 "SYS_lfs_markv", //185
5376 "SYS_lfs_segclean", //186
5377 "SYS_lfs_segwait", //187
5378 "SYS_188",
5379 "SYS_189",
5380 "SYS_190",
5381 "SYS_pathconf", //191
5382 "SYS_fpathconf", //192
5383 "SYS_swapctl", //193
5384 "SYS_getrlimit", //194
5385 "SYS_setrlimit", //195
5386 "SYS_getdirentries", //196
5387 "SYS_mmap", //197
5388 "SYS___syscall", //198
5389 "SYS_lseek", //199
5390 "SYS_truncate", //200
5391 "SYS_ftruncate", //201
5392 "SYS___sysctl", //202
5393 "SYS_mlock", //203
5394 "SYS_munlock", //204
5395 "SYS_205",
5396 "SYS_futimes", //206
5397 "SYS_getpgid", //207
5398 "SYS_xfspioctl", //208
5399 "SYS_209",
5400 "SYS_210",
5401 "SYS_211",
5402 "SYS_212",
5403 "SYS_213",
5404 "SYS_214",
5405 "SYS_215",
5406 "SYS_216",
5407 "SYS_217",
5408 "SYS_218",
5409 "SYS_219",
5410 "SYS_220",
5411 "SYS_semget", //221
5412 "SYS_222",
5413 "SYS_223",
5414 "SYS_224",
5415 "SYS_msgget", //225
5416 "SYS_msgsnd", //226
5417 "SYS_msgrcv", //227
5418 "SYS_shmat", //228
5419 "SYS_229",
5420 "SYS_shmdt", //230
5421 "SYS_231",
5422 "SYS_clock_gettime", //232
5423 "SYS_clock_settime", //233
5424 "SYS_clock_getres", //234
5425 "SYS_235",
5426 "SYS_236",
5427 "SYS_237",
5428 "SYS_238",
5429 "SYS_239",
5430 "SYS_nanosleep", //240
5431 "SYS_241",
5432 "SYS_242",
5433 "SYS_243",
5434 "SYS_244",
5435 "SYS_245",
5436 "SYS_246",
5437 "SYS_247",
5438 "SYS_248",
5439 "SYS_249",
5440 "SYS_minherit", //250
5441 "SYS_rfork", //251
5442 "SYS_poll", //252
5443 "SYS_issetugid", //253
5444 "SYS_lchown", //254
5445 "SYS_getsid", //255
5446 "SYS_msync", //256
5447 "SYS_257",
5448 "SYS_258",
5449 "SYS_259",
5450 "SYS_getfsstat", //260
5451 "SYS_statfs", //261
5452 "SYS_fstatfs", //262
5453 "SYS_pipe", //263
5454 "SYS_fhopen", //264
5455 "SYS_265",
5456 "SYS_fhstatfs", //266
5457 "SYS_preadv", //267
5458 "SYS_pwritev", //268
5459 "SYS_kqueue", //269
5460 "SYS_kevent", //270
5461 "SYS_mlockall", //271
5462 "SYS_munlockall", //272
5463 "SYS_getpeereid", //273
5464 "SYS_274",
5465 "SYS_275",
5466 "SYS_276",
5467 "SYS_277",
5468 "SYS_278",
5469 "SYS_279",
5470 "SYS_280",
5471 "SYS_getresuid", //281
5472 "SYS_setresuid", //282
5473 "SYS_getresgid", //283
5474 "SYS_setresgid", //284
5475 "SYS_285",
5476 "SYS_mquery", //286
5477 "SYS_closefrom", //287
5478 "SYS_sigaltstack", //288
5479 "SYS_shmget", //289
5480 "SYS_semop", //290
5481 "SYS_stat", //291
5482 "SYS_fstat", //292
5483 "SYS_lstat", //293
5484 "SYS_fhstat", //294
5485 "SYS___semctl", //295
5486 "SYS_shmctl", //296
5487 "SYS_msgctl", //297
5488 "SYS_MAXSYSCALL", //298
5489 //299
5490 //300
5491 };
5492 uint32_t uEAX;
5493 if (!LogIsEnabled())
5494 return;
5495 uEAX = CPUMGetGuestEAX(pVCpu);
5496 switch (uEAX)
5497 {
5498 default:
5499 if (uEAX < RT_ELEMENTS(apsz))
5500 {
5501 uint32_t au32Args[8] = {0};
5502 PGMPhysSimpleReadGCPtr(pVCpu, au32Args, CPUMGetGuestESP(pVCpu), sizeof(au32Args));
5503 RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
5504 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVCpu), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
5505 au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
5506 }
5507 else
5508 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVCpu), uEAX, uEAX);
5509 break;
5510 }
5511}
5512
5513
5514#if defined(IPRT_NO_CRT) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
5515/**
5516 * The Dll main entry point (stub).
5517 */
5518bool __stdcall _DllMainCRTStartup(void *hModule, uint32_t dwReason, void *pvReserved)
5519{
5520 return true;
5521}
5522
5523void *memcpy(void *dst, const void *src, size_t size)
5524{
5525 uint8_t*pbDst = dst, *pbSrc = src;
5526 while (size-- > 0)
5527 *pbDst++ = *pbSrc++;
5528 return dst;
5529}
5530
5531#endif
5532
5533void cpu_smm_update(CPUX86State *env)
5534{
5535}
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