VBoxRecompiler.c@ 843

Last change on this file since 843 was 835, checked in by vboxsync, 18 years ago
GC Phys to HC virt conversion changes for dynamic RAM allocation.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 154.9 KB

Line
1	/** @file
2	*
3	* VBox Recompiler - QEMU.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include "vl.h"
27	#include "exec-all.h"
28
29	#include <VBox/rem.h>
30	#include <VBox/vmapi.h>
31	#include <VBox/tm.h>
32	#include <VBox/ssm.h>
33	#include <VBox/em.h>
34	#include <VBox/trpm.h>
35	#include <VBox/iom.h>
36	#include <VBox/mm.h>
37	#include <VBox/pgm.h>
38	#include <VBox/pdm.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/dbg.h>
41	#include <VBox/hwaccm.h>
42	#include <VBox/patm.h>
43	#include <VBox/csam.h>
44	#include "REMInternal.h"
45	#include <VBox/vm.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49	#define LOG_GROUP LOG_GROUP_REM
50	#include <VBox/log.h>
51	#include <iprt/semaphore.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/thread.h>
55	#include <iprt/string.h>
56
57	////#define VBOX_RAW_V86
58
59	/* Don't wanna include everything. */
60	extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
61	extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
62	extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
63	extern void tlb_flush_page(CPUX86State *env, uint32_t addr);
64	extern void tlb_flush(CPUState *env, int flush_global);
65	extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
66	extern void sync_ldtr(CPUX86State *env1, int selector);
67	extern int sync_tr(CPUX86State *env1, int selector);
68
69	#ifdef VBOX_STRICT
70	unsigned long get_phys_page_offset(target_ulong addr);
71	#endif
72
73
74	/*******************************************************************************
75	* Defined Constants And Macros *
76	*******************************************************************************/
77
78	/** Copy 80-bit fpu register at pSrc to pDst.
79	* This is probably faster than calling memcpy.
80	*/
81	#define REM_COPY_FPU_REG(pDst, pSrc) \
82	do { (PX86FPUMMX)(pDst) = (const X86FPUMMX *)(pSrc); } while (0)
83
84
85	/*******************************************************************************
86	* Internal Functions *
87	*******************************************************************************/
88	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
89	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
90	static void remR3StateUpdate(PVM pVM);
91	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
92	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
93	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
94	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
97
98	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
99	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
100	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
101	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
104
105
106	/*******************************************************************************
107	* Global Variables *
108	*******************************************************************************/
109
110	/** The log level of the recompiler. */
111	#if 1
112	extern int loglevel;
113	#else
114	int loglevel = ~0;
115	FILE *logfile = NULL;
116	#endif
117
118
119	/** @todo Move stats to REM::s some rainy day we have nothing do to. */
120	#ifdef VBOX_WITH_STATISTICS
121	static STAMPROFILEADV gStatExecuteSingleInstr;
122	static STAMPROFILEADV gStatCompilationQEmu;
123	static STAMPROFILEADV gStatRunCodeQEmu;
124	static STAMPROFILEADV gStatTotalTimeQEmu;
125	static STAMPROFILEADV gStatTimers;
126	static STAMPROFILEADV gStatTBLookup;
127	static STAMPROFILEADV gStatIRQ;
128	static STAMPROFILEADV gStatRawCheck;
129	static STAMPROFILEADV gStatMemRead;
130	static STAMPROFILEADV gStatMemWrite;
131	static STAMCOUNTER gStatRefuseTFInhibit;
132	static STAMCOUNTER gStatRefuseVM86;
133	static STAMCOUNTER gStatRefusePaging;
134	static STAMCOUNTER gStatRefusePAE;
135	static STAMCOUNTER gStatRefuseIOPLNot0;
136	static STAMCOUNTER gStatRefuseIF0;
137	static STAMCOUNTER gStatRefuseCode16;
138	static STAMCOUNTER gStatRefuseWP0;
139	static STAMCOUNTER gStatRefuseRing1or2;
140	static STAMCOUNTER gStatRefuseCanExecute;
141	static STAMCOUNTER gStatREMGDTChange;
142	static STAMCOUNTER gStatREMIDTChange;
143	static STAMCOUNTER gStatREMLDTRChange;
144	static STAMCOUNTER gStatREMTRChange;
145	static STAMCOUNTER gStatSelOutOfSync[6];
146	static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
147	#endif
148
149	/*
150	* Global stuff.
151	*/
152
153	/** MMIO read callbacks. */
154	CPUReadMemoryFunc *g_apfnMMIORead[3] =
155	{
156	remR3MMIOReadU8,
157	remR3MMIOReadU16,
158	remR3MMIOReadU32
159	};
160
161	/** MMIO write callbacks. */
162	CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
163	{
164	remR3MMIOWriteU8,
165	remR3MMIOWriteU16,
166	remR3MMIOWriteU32
167	};
168
169	/** Handler read callbacks. */
170	CPUReadMemoryFunc *g_apfnHandlerRead[3] =
171	{
172	remR3HandlerReadU8,
173	remR3HandlerReadU16,
174	remR3HandlerReadU32
175	};
176
177	/** Handler write callbacks. */
178	CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
179	{
180	remR3HandlerWriteU8,
181	remR3HandlerWriteU16,
182	remR3HandlerWriteU32
183	};
184
185	#ifndef PGM_DYNAMIC_RAM_ALLOC
186	/* Guest physical RAM base. Not to be used in external code. */
187	static uint8_t *phys_ram_base;
188	#endif
189
190	/*
191	* Instance stuff.
192	*/
193	/** Pointer to the cpu state. */
194	CPUState *cpu_single_env;
195
196
197	#ifdef VBOX_WITH_DEBUGGER
198	/*
199	* Debugger commands.
200	*/
201	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
202
203	/** '.remstep' arguments. */
204	static const DBGCVARDESC g_aArgRemStep[] =
205	{
206	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
207	{ 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
208	};
209
210	/** Command descriptors. */
211	static const DBGCCMD g_aCmds[] =
212	{
213	{
214	.pszCmd ="remstep",
215	.cArgsMin = 0,
216	.cArgsMax = 1,
217	.paArgDescs = &g_aArgRemStep[0],
218	.cArgDescs = ELEMENTS(g_aArgRemStep),
219	.pResultDesc = NULL,
220	.fFlags = 0,
221	.pfnHandler = remR3CmdDisasEnableStepping,
222	.pszSyntax = "[on/off]",
223	.pszDescription = "Enable or disable the single stepping with logged disassembly. "
224	"If no arguments show the current state."
225	}
226	};
227	#endif
228
229
230	/*******************************************************************************
231	* Internal Functions *
232	*******************************************************************************/
233	static void remAbort(int rc, const char *pszTip);
234
235
236	/* Put them here to avoid unused variable warning. */
237	AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
238	//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
239	//AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
240
241	/**
242	* Initializes the REM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	REMR3DECL(int) REMR3Init(PVM pVM)
248	{
249	uint32_t u32Dummy;
250	AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
251	//AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
252	AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
253	#if 0 /* not merged yet */
254	Assert(!testmath());
255	#endif
256
257	/*
258	* Init some internal data members.
259	*/
260	pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
261	pVM->rem.s.Env.pVM = pVM;
262	#ifdef CPU_RAW_MODE_INIT
263	pVM->rem.s.state \|= CPU_RAW_MODE_INIT;
264	#endif
265
266	/* ctx. */
267	int rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);
268	if (VBOX_FAILURE(rc))
269	{
270	AssertMsgFailed(("Failed to obtain guest ctx pointer. rc=%Vrc\n", rc));
271	return rc;
272	}
273	AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
274
275	/*
276	* Init the recompiler.
277	*/
278	if (!cpu_x86_init(&pVM->rem.s.Env))
279	{
280	AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
281	return VERR_GENERAL_FAILURE;
282	}
283	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
284
285	/* allocate code buffer for single instruction emulation. */
286	pVM->rem.s.Env.cbCodeBuffer = 4096;
287	pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
288	AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
289
290	/* finally, set the cpu_single_env global. */
291	cpu_single_env = &pVM->rem.s.Env;
292
293	/* Nothing is pending by default */
294	pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
295
296	#ifdef DEBUG_bird
297	//cpu_breakpoint_insert(&pVM->rem.s.Env, some-address);
298	#endif
299
300	/*
301	* Register ram types.
302	*/
303	pVM->rem.s.iMMIOMemType = cpu_register_io_memory(0, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
304	AssertReleaseMsg(pVM->rem.s.iMMIOMemType > 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
305	pVM->rem.s.iHandlerMemType = cpu_register_io_memory(0, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
306	AssertReleaseMsg(pVM->rem.s.iHandlerMemType > 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
307	Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
308
309	/*
310	* Register the saved state data unit.
311	*/
312	rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
313	NULL, remR3Save, NULL,
314	NULL, remR3Load, NULL);
315	if (VBOX_FAILURE(rc))
316	return rc;
317
318	#ifdef VBOX_WITH_DEBUGGER
319	/*
320	* Debugger commands.
321	*/
322	static bool fRegisteredCmds = false;
323	if (!fRegisteredCmds)
324	{
325	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
326	if (VBOX_SUCCESS(rc))
327	fRegisteredCmds = true;
328	}
329	#endif
330
331	#ifdef VBOX_WITH_STATISTICS
332	/*
333	* Statistics.
334	*/
335	STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
336	STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
337	STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
338	STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
339	STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
340	STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
341	STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
342	STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
343	STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
344	STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
345
346	STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
347	STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
348	STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
349	STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
350	STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
351	STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
352	STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
353	STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
354	STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
355	STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
356
357	STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
358	STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
359	STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
360	STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
361
362	STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
363	STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
364	STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
365	STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
366	STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
367	STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
368
369	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
370	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
371	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
372	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
373	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
374	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
375
376	#endif
377	return rc;
378	}
379
380
381	/**
382	* Terminates the REM.
383	*
384	* Termination means cleaning up and freeing all resources,
385	* the VM it self is at this point powered off or suspended.
386	*
387	* @returns VBox status code.
388	* @param pVM The VM to operate on.
389	*/
390	REMR3DECL(int) REMR3Term(PVM pVM)
391	{
392	return VINF_SUCCESS;
393	}
394
395
396	/**
397	* The VM is being reset.
398	*
399	* For the REM component this means to call the cpu_reset() and
400	* reinitialize some state variables.
401	*
402	* @param pVM VM handle.
403	*/
404	REMR3DECL(void) REMR3Reset(PVM pVM)
405	{
406	pVM->rem.s.fIgnoreCR3Load = true;
407	pVM->rem.s.fIgnoreInvlPg = true;
408	pVM->rem.s.fIgnoreCpuMode = true;
409
410	/*
411	* Reset the REM cpu.
412	*/
413	cpu_reset(&pVM->rem.s.Env);
414	pVM->rem.s.cInvalidatedPages = 0;
415
416	pVM->rem.s.fIgnoreCR3Load = false;
417	pVM->rem.s.fIgnoreInvlPg = false;
418	pVM->rem.s.fIgnoreCpuMode = false;
419
420	#ifdef PGM_DYNAMIC_RAM_ALLOC
421	pVM->rem.s.cPhysRegistrations = 0;
422	#endif
423	}
424
425
426	/**
427	* Execute state save operation.
428	*
429	* @returns VBox status code.
430	* @param pVM VM Handle.
431	* @param pSSM SSM operation handle.
432	*/
433	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
434	{
435	LogFlow(("remR3Save:\n"));
436
437	/*
438	* Save the required CPU Env bits.
439	* (Not much because we're never in REM when doing the save.)
440	*/
441	PREM pRem = &pVM->rem.s;
442	Assert(!pRem->fInREM);
443	SSMR3PutU32(pSSM, pRem->Env.hflags);
444	SSMR3PutMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
445	SSMR3PutU32(pSSM, ~0); /* separator */
446
447	/*
448	* Save the REM stuff.
449	*/
450	SSMR3PutUInt(pSSM, pRem->cInvalidatedPages);
451	unsigned i;
452	for (i = 0; i < pRem->cInvalidatedPages; i++)
453	SSMR3PutGCPtr(pSSM, pRem->aGCPtrInvalidatedPages[i]);
454
455	SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
456
457	return SSMR3PutU32(pSSM, ~0); /* terminator */
458	}
459
460
461	/**
462	* Execute state load operation.
463	*
464	* @returns VBox status code.
465	* @param pVM VM Handle.
466	* @param pSSM SSM operation handle.
467	* @param u32Version Data layout version.
468	*/
469	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
470	{
471	uint32_t u32Dummy;
472	LogFlow(("remR3Load:\n"));
473
474	/*
475	* Validate version.
476	*/
477	if (u32Version != REM_SAVED_STATE_VERSION)
478	{
479	Log(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
480	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
481	}
482
483	/*
484	* Do a reset to be on the safe side...
485	*/
486	REMR3Reset(pVM);
487
488	/*
489	* Ignore all ignorable notifications.
490	* Not doing this will cause big trouble.
491	*/
492	pVM->rem.s.fIgnoreCR3Load = true;
493	pVM->rem.s.fIgnoreInvlPg = true;
494	pVM->rem.s.fIgnoreCpuMode = true;
495
496	/*
497	* Load the required CPU Env bits.
498	* (Not much because we're never in REM when doing the save.)
499	*/
500	PREM pRem = &pVM->rem.s;
501	Assert(!pRem->fInREM);
502	SSMR3GetU32(pSSM, &pRem->Env.hflags);
503	SSMR3GetMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
504	uint32_t u32Sep;
505	int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
506	if (VBOX_FAILURE(rc))
507	return rc;
508	if (u32Sep != ~0)
509	{
510	AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
511	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
512	}
513
514	/*
515	* Load the REM stuff.
516	*/
517	rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
518	if (VBOX_FAILURE(rc))
519	return rc;
520	if (pRem->cInvalidatedPages > ELEMENTS(pRem->aGCPtrInvalidatedPages))
521	{
522	AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
523	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
524	}
525	unsigned i;
526	for (i = 0; i < pRem->cInvalidatedPages; i++)
527	SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
528
529	rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
530	if (VBOX_FAILURE(rc))
531	return rc;
532
533	/* check the terminator. */
534	rc = SSMR3GetU32(pSSM, &u32Sep);
535	if (VBOX_FAILURE(rc))
536	return rc;
537	if (u32Sep != ~0)
538	{
539	AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
540	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
541	}
542
543	/*
544	* Get the CPUID features.
545	*/
546	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
547
548	/*
549	* Sync the Load Flush the TLB
550	*/
551	tlb_flush(&pRem->Env, 1);
552
553	#if 0 /** @todo r=bird: this doesn't make sense. WHY? */
554	/*
555	* Clear all lazy flags (only FPU sync for now).
556	*/
557	CPUMGetAndClearFPUUsedREM(pVM);
558	#endif
559
560	/*
561	* Stop ignoring ignornable notifications.
562	*/
563	pVM->rem.s.fIgnoreCpuMode = false;
564	pVM->rem.s.fIgnoreInvlPg = false;
565	pVM->rem.s.fIgnoreCR3Load = false;
566
567	return VINF_SUCCESS;
568	}
569
570
571
572	#undef LOG_GROUP
573	#define LOG_GROUP LOG_GROUP_REM_RUN
574
575	/**
576	* Single steps an instruction in recompiled mode.
577	*
578	* Before calling this function the REM state needs to be in sync with
579	* the VM. Call REMR3State() to perform the sync. It's only necessary
580	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
581	* and after calling REMR3StateBack().
582	*
583	* @returns VBox status code.
584	*
585	* @param pVM VM Handle.
586	*/
587	REMR3DECL(int) REMR3Step(PVM pVM)
588	{
589	/*
590	* Lock the REM - we don't wanna have anyone interrupting us
591	* while stepping - and enabled single stepping. We also ignore
592	* pending interrupts and suchlike.
593	*/
594	int interrupt_request = pVM->rem.s.Env.interrupt_request;
595	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
596	pVM->rem.s.Env.interrupt_request = 0;
597	cpu_single_step(&pVM->rem.s.Env, 1);
598
599	/*
600	* If we're standing at a breakpoint, that have to be disabled before we start stepping.
601	*/
602	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
603	bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
604
605	/*
606	* Execute and handle the return code.
607	* We execute without enabling the cpu tick, so on success we'll
608	* just flip it on and off to make sure it moves
609	*/
610	int rc = cpu_exec(&pVM->rem.s.Env);
611	if (rc == EXCP_DEBUG)
612	{
613	TMCpuTickResume(pVM);
614	TMCpuTickPause(pVM);
615	TMVirtualResume(pVM);
616	TMVirtualPause(pVM);
617	rc = VINF_EM_DBG_STEPPED;
618	}
619	else
620	{
621	AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
622	switch (rc)
623	{
624	case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
625	case EXCP_HLT: rc = VINF_EM_HALT; break;
626	case EXCP_RC:
627	rc = pVM->rem.s.rc;
628	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
629	break;
630	default:
631	AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
632	rc = VERR_INTERNAL_ERROR;
633	break;
634	}
635	}
636
637	/*
638	* Restore the stuff we changed to prevent interruption.
639	* Unlock the REM.
640	*/
641	if (fBp)
642	{
643	int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
644	Assert(rc2 == 0); NOREF(rc2);
645	}
646	cpu_single_step(&pVM->rem.s.Env, 0);
647	pVM->rem.s.Env.interrupt_request = interrupt_request;
648
649	return rc;
650	}
651
652
653	/**
654	* Set a breakpoint using the REM facilities.
655	*
656	* @returns VBox status code.
657	* @param pVM The VM handle.
658	* @param Address The breakpoint address.
659	* @thread The emulation thread.
660	*/
661	REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
662	{
663	VM_ASSERT_EMT(pVM);
664	if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
665	{
666	LogFlow(("REMR3BreakpointSet: Address=%VGv\n", Address));
667	return VINF_SUCCESS;
668	}
669	LogFlow(("REMR3BreakpointSet: Address=%VGv - failed!\n", Address));
670	return VERR_REM_NO_MORE_BP_SLOTS;
671	}
672
673
674	/**
675	* Clears a breakpoint set by REMR3BreakpointSet().
676	*
677	* @returns VBox status code.
678	* @param pVM The VM handle.
679	* @param Address The breakpoint address.
680	* @thread The emulation thread.
681	*/
682	REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
683	{
684	VM_ASSERT_EMT(pVM);
685	if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
686	{
687	LogFlow(("REMR3BreakpointClear: Address=%VGv\n", Address));
688	return VINF_SUCCESS;
689	}
690	LogFlow(("REMR3BreakpointClear: Address=%VGv - not found!\n", Address));
691	return VERR_REM_BP_NOT_FOUND;
692	}
693
694
695	/**
696	* Emulate an instruction.
697	*
698	* This function executes one instruction without letting anyone
699	* interrupt it. This is intended for being called while being in
700	* raw mode and thus will take care of all the state syncing between
701	* REM and the rest.
702	*
703	* @returns VBox status code.
704	* @param pVM VM handle.
705	*/
706	REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
707	{
708	Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
709
710	/*
711	* Sync the state and enable single instruction / single stepping.
712	*/
713	int rc = REMR3State(pVM);
714	if (VBOX_SUCCESS(rc))
715	{
716	int interrupt_request = pVM->rem.s.Env.interrupt_request;
717	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
718	Assert(!pVM->rem.s.Env.singlestep_enabled);
719	#if 1
720
721	/*
722	* Now we set the execute single instruction flag and enter the cpu_exec loop.
723	*/
724	pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
725	TMCpuTickResume(pVM);
726	rc = cpu_exec(&pVM->rem.s.Env);
727	TMCpuTickPause(pVM);
728	switch (rc)
729	{
730	/*
731	* Executed without anything out of the way happening.
732	*/
733	case EXCP_SINGLE_INSTR:
734	rc = VINF_EM_RESCHEDULE;
735	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
736	break;
737
738	/*
739	* If we take a trap or start servicing a pending interrupt, we might end up here.
740	* (Timer thread or some other thread wishing EMT's attention.)
741	*/
742	case EXCP_INTERRUPT:
743	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
744	rc = VINF_EM_RESCHEDULE;
745	break;
746
747	/*
748	* Single step, we assume!
749	* If there was a breakpoint there we're fucked now.
750	*/
751	case EXCP_DEBUG:
752	{
753	/* breakpoint or single step? */
754	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
755	int iBP;
756	rc = VINF_EM_DBG_STEPPED;
757	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
758	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
759	{
760	rc = VINF_EM_DBG_BREAKPOINT;
761	break;
762	}
763	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
764	break;
765	}
766
767	/*
768	* hlt instruction.
769	*/
770	case EXCP_HLT:
771	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
772	rc = VINF_EM_HALT;
773	break;
774
775	/*
776	* Switch to RAW-mode.
777	*/
778	case EXCP_EXECUTE_RAW:
779	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
780	rc = VINF_EM_RESCHEDULE_RAW;
781	break;
782
783	/*
784	* Switch to hardware accelerated RAW-mode.
785	*/
786	case EXCP_EXECUTE_HWACC:
787	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
788	rc = VINF_EM_RESCHEDULE_HWACC;
789	break;
790
791	/*
792	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
793	*/
794	case EXCP_RC:
795	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
796	rc = pVM->rem.s.rc;
797	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
798	break;
799
800	/*
801	* Figure out the rest when they arrive....
802	*/
803	default:
804	AssertMsgFailed(("rc=%d\n", rc));
805	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
806	rc = VINF_EM_RESCHEDULE;
807	break;
808	}
809
810	/*
811	* Switch back the state.
812	*/
813	#else
814	pVM->rem.s.Env.interrupt_request = 0;
815	cpu_single_step(&pVM->rem.s.Env, 1);
816
817	/*
818	* Execute and handle the return code.
819	* We execute without enabling the cpu tick, so on success we'll
820	* just flip it on and off to make sure it moves.
821	*
822	* (We do not use emulate_single_instr() because that doesn't enter the
823	* right way in will cause serious trouble if a longjmp was attempted.)
824	*/
825	#ifdef DEBUG_bird
826	remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
827	#endif
828	int cTimesMax = 16384;
829	uint32_t eip = pVM->rem.s.Env.eip;
830	do
831	{
832	TMCpuTickResume(pVM);
833	rc = cpu_exec(&pVM->rem.s.Env);
834	TMCpuTickPause(pVM);
835
836	} while ( eip == pVM->rem.s.Env.eip
837	&& (rc == EXCP_DEBUG \|\| rc == EXCP_EXECUTE_RAW)
838	&& --cTimesMax > 0);
839	switch (rc)
840	{
841	/*
842	* Single step, we assume!
843	* If there was a breakpoint there we're fucked now.
844	*/
845	case EXCP_DEBUG:
846	{
847	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
848	rc = VINF_EM_RESCHEDULE;
849	break;
850	}
851
852	/*
853	* We cannot be interrupted!
854	*/
855	case EXCP_INTERRUPT:
856	AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
857	rc = VERR_INTERNAL_ERROR;
858	break;
859
860	/*
861	* hlt instruction.
862	*/
863	case EXCP_HLT:
864	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
865	rc = VINF_EM_HALT;
866	break;
867
868	/*
869	* Switch to RAW-mode.
870	*/
871	case EXCP_EXECUTE_RAW:
872	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
873	rc = VINF_EM_RESCHEDULE_RAW;
874	break;
875
876	/*
877	* Switch to hardware accelerated RAW-mode.
878	*/
879	case EXCP_EXECUTE_HWACC:
880	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
881	rc = VINF_EM_RESCHEDULE_HWACC;
882	break;
883
884	/*
885	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
886	*/
887	case EXCP_RC:
888	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
889	rc = pVM->rem.s.rc;
890	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
891	break;
892
893	/*
894	* Figure out the rest when they arrive....
895	*/
896	default:
897	AssertMsgFailed(("rc=%d\n", rc));
898	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
899	rc = VINF_SUCCESS;
900	break;
901	}
902
903	/*
904	* Switch back the state.
905	*/
906	cpu_single_step(&pVM->rem.s.Env, 0);
907	#endif
908	pVM->rem.s.Env.interrupt_request = interrupt_request;
909	int rc2 = REMR3StateBack(pVM);
910	AssertRC(rc2);
911	}
912
913	Log2(("REMR3EmulateInstruction: returns %Vrc (cs:eip=%04x:%08x)\n",
914	rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
915	return rc;
916	}
917
918
919	/**
920	* Runs code in recompiled mode.
921	*
922	* Before calling this function the REM state needs to be in sync with
923	* the VM. Call REMR3State() to perform the sync. It's only necessary
924	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
925	* and after calling REMR3StateBack().
926	*
927	* @returns VBox status code.
928	*
929	* @param pVM VM Handle.
930	*/
931	REMR3DECL(int) REMR3Run(PVM pVM)
932	{
933	Log2(("REMR3Run: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
934	Assert(pVM->rem.s.fInREM);
935	////Keyboard / tb stuff:
936	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0xf000
937	// && pVM->rem.s.Env.eip >= 0xe860
938	// && pVM->rem.s.Env.eip <= 0xe880)
939	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
940	////A20:
941	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x9020
942	// && pVM->rem.s.Env.eip >= 0x970
943	// && pVM->rem.s.Env.eip <= 0x9a0)
944	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
945	////Speaker (port 61h)
946	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x0010
947	// && ( (pVM->rem.s.Env.eip >= 0x90278c10 && pVM->rem.s.Env.eip <= 0x90278c30)
948	// \|\| (pVM->rem.s.Env.eip >= 0x9010e250 && pVM->rem.s.Env.eip <= 0x9010e260)
949	// )
950	// )
951	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
952	//DBGFR3InfoLog(pVM, "timers", NULL);
953
954
955	TMCpuTickResume(pVM);
956	int rc = cpu_exec(&pVM->rem.s.Env);
957	TMCpuTickPause(pVM);
958	switch (rc)
959	{
960	/*
961	* This happens when the execution was interrupted
962	* by an external event, like pending timers.
963	*/
964	case EXCP_INTERRUPT:
965	Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
966	rc = VINF_SUCCESS;
967	break;
968
969	/*
970	* hlt instruction.
971	*/
972	case EXCP_HLT:
973	Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
974	rc = VINF_EM_HALT;
975	break;
976
977	/*
978	* Breakpoint/single step.
979	*/
980	case EXCP_DEBUG:
981	{
982	#if 0//def DEBUG_bird
983	static int iBP = 0;
984	printf("howdy, breakpoint! iBP=%d\n", iBP);
985	switch (iBP)
986	{
987	case 0:
988	cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
989	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
990	//pVM->rem.s.Env.interrupt_request = 0;
991	//pVM->rem.s.Env.exception_index = -1;
992	//g_fInterruptDisabled = 1;
993	rc = VINF_SUCCESS;
994	asm("int3");
995	break;
996	default:
997	asm("int3");
998	break;
999	}
1000	iBP++;
1001	#else
1002	/* breakpoint or single step? */
1003	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1004	int iBP;
1005	rc = VINF_EM_DBG_STEPPED;
1006	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
1007	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
1008	{
1009	rc = VINF_EM_DBG_BREAKPOINT;
1010	break;
1011	}
1012	Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
1013	#endif
1014	break;
1015	}
1016
1017	/*
1018	* Switch to RAW-mode.
1019	*/
1020	case EXCP_EXECUTE_RAW:
1021	Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1022	rc = VINF_EM_RESCHEDULE_RAW;
1023	break;
1024
1025	/*
1026	* Switch to hardware accelerated RAW-mode.
1027	*/
1028	case EXCP_EXECUTE_HWACC:
1029	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1030	rc = VINF_EM_RESCHEDULE_HWACC;
1031	break;
1032
1033	/*
1034	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
1035	*/
1036	case EXCP_RC:
1037	Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
1038	rc = pVM->rem.s.rc;
1039	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1040	break;
1041
1042	/*
1043	* Figure out the rest when they arrive....
1044	*/
1045	default:
1046	AssertMsgFailed(("rc=%d\n", rc));
1047	Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1048	rc = VINF_SUCCESS;
1049	break;
1050	}
1051
1052	Log2(("REMR3Run: returns %Vrc (cs:eip=%04x:%08x)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
1053	return rc;
1054	}
1055
1056
1057	/**
1058	* Check if the cpu state is suitable for Raw execution.
1059	*
1060	* @returns boolean
1061	* @param env The CPU env struct.
1062	* @param eip The EIP to check this for (might differ from env->eip).
1063	* @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1064	* @param pExceptionIndex Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1065	*
1066	* @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1067	*/
1068	bool remR3CanExecuteRaw(CPUState env, RTGCPTR eip, unsigned fFlags, uint32_t pExceptionIndex)
1069	{
1070	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1071	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1072	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1073
1074	/* Update counter. */
1075	env->pVM->rem.s.cCanExecuteRaw++;
1076
1077	if (HWACCMIsEnabled(env->pVM))
1078	{
1079	env->state \|= CPU_RAW_HWACC;
1080
1081	/*
1082	* Create partial context for HWACCMR3CanExecuteGuest
1083	*/
1084	CPUMCTX Ctx;
1085	Ctx.cr0 = env->cr[0];
1086	Ctx.cr3 = env->cr[3];
1087	Ctx.cr4 = env->cr[4];
1088
1089	Ctx.tr = env->tr.selector;
1090	Ctx.trHid.u32Base = (uint32_t)env->tr.base;
1091	Ctx.trHid.u32Limit = env->tr.limit;
1092	Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1093
1094	Ctx.idtr.cbIdt = env->idt.limit;
1095	Ctx.idtr.pIdt = (uint32_t)env->idt.base;
1096
1097	Ctx.eflags.u32 = env->eflags;
1098
1099	Ctx.cs = env->segs[R_CS].selector;
1100	Ctx.csHid.u32Base = (uint32_t)env->segs[R_CS].base;
1101	Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1102	Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1103
1104	Ctx.ss = env->segs[R_SS].selector;
1105	Ctx.ssHid.u32Base = (uint32_t)env->segs[R_SS].base;
1106	Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1107	Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1108
1109	/* Hardware accelerated raw-mode:
1110	*
1111	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1112	*/
1113	if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1114	{
1115	*pExceptionIndex = EXCP_EXECUTE_HWACC;
1116	return true;
1117	}
1118	return false;
1119	}
1120
1121	/*
1122	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1123	* or 32 bits protected mode ring 0 code
1124	*
1125	* The tests are ordered by the likelyhood of being true during normal execution.
1126	*/
1127	if (fFlags & (HF_TF_MASK \| HF_INHIBIT_IRQ_MASK))
1128	{
1129	STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1130	Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1131	return false;
1132	}
1133
1134	#ifndef VBOX_RAW_V86
1135	if (fFlags & VM_MASK) {
1136	STAM_COUNTER_INC(&gStatRefuseVM86);
1137	Log2(("raw mode refused: VM_MASK\n"));
1138	return false;
1139	}
1140	#endif
1141
1142	if (env->state & CPU_EMULATE_SINGLE_INSTR)
1143	{
1144	#ifndef DEBUG_bird
1145	Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1146	#endif
1147	return false;
1148	}
1149
1150	if (env->singlestep_enabled)
1151	{
1152	//Log2(("raw mode refused: Single step\n"));
1153	return false;
1154	}
1155
1156	if (env->nb_breakpoints > 0)
1157	{
1158	//Log2(("raw mode refused: Breakpoints\n"));
1159	return false;
1160	}
1161
1162	uint32_t u32CR0 = env->cr[0];
1163	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
1164	{
1165	STAM_COUNTER_INC(&gStatRefusePaging);
1166	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1167	return false;
1168	}
1169
1170	if (env->cr[4] & CR4_PAE_MASK)
1171	{
1172	STAM_COUNTER_INC(&gStatRefusePAE);
1173	//Log2(("raw mode refused: PAE\n"));
1174	return false;
1175	}
1176
1177	if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1178	{
1179	if (!EMIsRawRing3Enabled(env->pVM))
1180	return false;
1181
1182	if (!(env->eflags & IF_MASK))
1183	{
1184	#ifdef VBOX_RAW_V86
1185	if(!(fFlags & VM_MASK))
1186	return false;
1187	#else
1188	STAM_COUNTER_INC(&gStatRefuseIF0);
1189	Log2(("raw mode refused: IF (RawR3)\n"));
1190	return false;
1191	#endif
1192	}
1193
1194	if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1195	{
1196	STAM_COUNTER_INC(&gStatRefuseWP0);
1197	Log2(("raw mode refused: CR0.WP + RawR0\n"));
1198	return false;
1199	}
1200	}
1201	else
1202	{
1203	if (!EMIsRawRing0Enabled(env->pVM))
1204	return false;
1205
1206	// Let's start with pure 32 bits ring 0 code first
1207	if ((fFlags & (HF_SS32_MASK \| HF_CS32_MASK)) != (HF_SS32_MASK \| HF_CS32_MASK))
1208	{
1209	STAM_COUNTER_INC(&gStatRefuseCode16);
1210	Log2(("raw r0 mode refused: HF_[S\|C]S32_MASK fFlags=%#x\n", fFlags));
1211	return false;
1212	}
1213
1214	// Only R0
1215	if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1216	{
1217	STAM_COUNTER_INC(&gStatRefuseRing1or2);
1218	Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1219	return false;
1220	}
1221
1222	if (!(u32CR0 & CR0_WP_MASK))
1223	{
1224	STAM_COUNTER_INC(&gStatRefuseWP0);
1225	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1226	return false;
1227	}
1228
1229	if (PATMIsPatchGCAddr(env->pVM, eip))
1230	{
1231	Log2(("raw r0 mode forced: patch code\n"));
1232	*pExceptionIndex = EXCP_EXECUTE_RAW;
1233	return true;
1234	}
1235
1236	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1237	if (!(env->eflags & IF_MASK))
1238	{
1239	STAM_COUNTER_INC(&gStatRefuseIF0);
1240	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1241	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1242	return false;
1243	}
1244	#endif
1245
1246	env->state \|= CPU_RAW_RING0;
1247	}
1248
1249	/*
1250	* Don't reschedule the first time we're called, because there might be
1251	* special reasons why we're here that is not covered by the above checks.
1252	*/
1253	if (env->pVM->rem.s.cCanExecuteRaw == 1)
1254	{
1255	Log2(("raw mode refused: first scheduling\n"));
1256	STAM_COUNTER_INC(&gStatRefuseCanExecute);
1257	return false;
1258	}
1259
1260	Assert(PGMPhysIsA20Enabled(env->pVM));
1261	*pExceptionIndex = EXCP_EXECUTE_RAW;
1262	return true;
1263	}
1264
1265
1266	/**
1267	* Fetches a code byte.
1268	*
1269	* @returns Success indicator (bool) for ease of use.
1270	* @param env The CPU environment structure.
1271	* @param GCPtrInstr Where to fetch code.
1272	* @param pu8Byte Where to store the byte on success
1273	*/
1274	bool remR3GetOpcode(CPUState env, RTGCPTR GCPtrInstr, uint8_t pu8Byte)
1275	{
1276	int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1277	if (VBOX_SUCCESS(rc))
1278	return true;
1279	return false;
1280	}
1281
1282
1283	/**
1284	* Flush (or invalidate if you like) page table/dir entry.
1285	*
1286	* (invlpg instruction; tlb_flush_page)
1287	*
1288	* @param env Pointer to cpu environment.
1289	* @param GCPtr The virtual address which page table/dir entry should be invalidated.
1290	*/
1291	void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1292	{
1293	PVM pVM = env->pVM;
1294
1295	/*
1296	* When we're replaying invlpg instructions or restoring a saved
1297	* state we disable this path.
1298	*/
1299	if (pVM->rem.s.fIgnoreInvlPg)
1300	return;
1301	Log(("remR3FlushPage: GCPtr=%VGv\n", GCPtr));
1302
1303	//RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1304
1305	/*
1306	* Update the control registers before calling PGMFlushPage.
1307	*/
1308	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1309	pCtx->cr0 = env->cr[0];
1310	pCtx->cr3 = env->cr[3];
1311	pCtx->cr4 = env->cr[4];
1312
1313	/*
1314	* Let PGM do the rest.
1315	*/
1316	int rc = PGMInvalidatePage(pVM, GCPtr);
1317	if (VBOX_FAILURE(rc))
1318	{
1319	AssertMsgFailed(("remR3FlushPage %x %x %x %d failed!!\n", GCPtr));
1320	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1321	}
1322	//RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1323	}
1324
1325	/**
1326	* Set page table/dir entry. (called from tlb_set_page)
1327	*
1328	* @param env Pointer to cpu environment.
1329	*/
1330	void remR3SetPage(CPUState env, CPUTLBEntry pRead, CPUTLBEntry *pWrite, int prot, int is_user)
1331	{
1332	uint32_t virt_addr, addend;
1333
1334	Log2(("tlb_set_page_raw read (%x-%x) write (%x-%x) prot %x is_user %d\n", pRead->address, pRead->addend, pWrite->address, pWrite->addend, prot, is_user));
1335
1336	if (prot & PAGE_WRITE)
1337	{
1338	addend = pWrite->addend;
1339	virt_addr = pWrite->address;
1340	}
1341	else
1342	if (prot & PAGE_READ)
1343	{
1344	addend = pRead->addend;
1345	virt_addr = pRead->address;
1346	}
1347	else
1348	{
1349	// Should never happen!
1350	AssertMsgFailed(("tlb_set_page_raw unexpected protection flags %x\n", prot));
1351	return;
1352	}
1353
1354	// Clear IO_* flags (TODO: are they actually useful for us??)
1355	virt_addr &= ~0xFFF;
1356
1357	/*
1358	* Update the control registers before calling PGMFlushPage.
1359	*/
1360	PCPUMCTX pCtx = (PCPUMCTX)env->pVM->rem.s.pCtx;
1361	pCtx->cr0 = env->cr[0];
1362	pCtx->cr3 = env->cr[3];
1363	pCtx->cr4 = env->cr[4];
1364
1365	/*
1366	* Let PGM do the rest.
1367	*/
1368	int rc = PGMInvalidatePage(env->pVM, (RTGCPTR)virt_addr);
1369	if (VBOX_FAILURE(rc))
1370	{
1371	AssertMsgFailed(("RAWEx_SetPageEntry %x %x %d failed!!\n", virt_addr, prot, is_user));
1372	VM_FF_SET(env->pVM, VM_FF_PGM_SYNC_CR3);
1373	}
1374	}
1375
1376	/**
1377	* Called from tlb_protect_code in order to write monitor a code page.
1378	*
1379	* @param env Pointer to the CPU environment.
1380	* @param GCPtr Code page to monitor
1381	*/
1382	void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1383	{
1384	if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1385	&& !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1386	&& (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1387	&& !(env->eflags & VM_MASK) /* no V86 mode */
1388	&& !HWACCMIsEnabled(env->pVM))
1389	CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1390	}
1391
1392	/**
1393	* Called when the CPU is initialized, any of the CRx registers are changed or
1394	* when the A20 line is modified.
1395	*
1396	* @param env Pointer to the CPU environment.
1397	* @param fGlobal Set if the flush is global.
1398	*/
1399	void remR3FlushTLB(CPUState *env, bool fGlobal)
1400	{
1401	PVM pVM = env->pVM;
1402
1403	/*
1404	* When we're replaying invlpg instructions or restoring a saved
1405	* state we disable this path.
1406	*/
1407	if (pVM->rem.s.fIgnoreCR3Load)
1408	return;
1409
1410	/*
1411	* The caller doesn't check cr4, so we have to do that for ourselves.
1412	*/
1413	if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1414	fGlobal = true;
1415	Log(("remR3FlushTLB: CR0=%VGp CR3=%VGp CR4=%VGp %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1416
1417	/*
1418	* Update the control registers before calling PGMR3FlushTLB.
1419	*/
1420	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1421	pCtx->cr0 = env->cr[0];
1422	pCtx->cr3 = env->cr[3];
1423	pCtx->cr4 = env->cr[4];
1424
1425	/*
1426	* Let PGM do the rest.
1427	*/
1428	PGMFlushTLB(pVM, env->cr[3], fGlobal);
1429	}
1430
1431
1432	/**
1433	* Called when any of the cr0, cr4 or efer registers is updated.
1434	*
1435	* @param env Pointer to the CPU environment.
1436	*/
1437	void remR3ChangeCpuMode(CPUState *env)
1438	{
1439	int rc;
1440	PVM pVM = env->pVM;
1441
1442	/*
1443	* When we're replaying loads or restoring a saved
1444	* state this path is disabled.
1445	*/
1446	if (pVM->rem.s.fIgnoreCpuMode)
1447	return;
1448
1449	/*
1450	* Update the control registers before calling PGMR3ChangeMode()
1451	* as it may need to map whatever cr3 is pointing to.
1452	*/
1453	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1454	pCtx->cr0 = env->cr[0];
1455	pCtx->cr3 = env->cr[3];
1456	pCtx->cr4 = env->cr[4];
1457
1458	#ifdef TARGET_X86_64
1459	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1460	if (rc != VINF_SUCCESS)
1461	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], env->efer, rc);
1462	#else
1463	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1464	if (rc != VINF_SUCCESS)
1465	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], 0LL, rc);
1466	#endif
1467	}
1468
1469
1470	/**
1471	* Called from compiled code to run dma.
1472	*
1473	* @param env Pointer to the CPU environment.
1474	*/
1475	void remR3DmaRun(CPUState *env)
1476	{
1477	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1478	PDMR3DmaRun(env->pVM);
1479	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1480	}
1481
1482	/**
1483	* Called from compiled code to schedule pending timers in VMM
1484	*
1485	* @param env Pointer to the CPU environment.
1486	*/
1487	void remR3TimersRun(CPUState *env)
1488	{
1489	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1490	remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1491	TMR3TimerQueuesDo(env->pVM);
1492	remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1493	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1494	}
1495
1496	/**
1497	* Record trap occurance
1498	*
1499	* @returns VBox status code
1500	* @param env Pointer to the CPU environment.
1501	* @param uTrap Trap nr
1502	* @param uErrorCode Error code
1503	* @param pvNextEIP Next EIP
1504	*/
1505	int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1506	{
1507	PVM pVM = (PVM)env->pVM;
1508	#ifdef VBOX_WITH_STATISTICS
1509	static STAMCOUNTER aStatTrap[255];
1510	static bool aRegisters[ELEMENTS(aStatTrap)];
1511	#endif
1512
1513	#ifdef VBOX_WITH_STATISTICS
1514	if (uTrap < 255)
1515	{
1516	if (!aRegisters[uTrap])
1517	{
1518	aRegisters[uTrap] = true;
1519	char szStatName[64];
1520	RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1521	STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1522	}
1523	STAM_COUNTER_INC(&aStatTrap[uTrap]);
1524	}
1525	#endif
1526	Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1527	if(uTrap < 0x20)
1528	{
1529	remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1530
1531	if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 128)
1532	{
1533	LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1534	remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1535	return VERR_REM_TOO_MANY_TRAPS;
1536	}
1537	if(pVM->rem.s.uPendingException != uTrap \|\| pVM->rem.s.uPendingExcptEIP != env->eip \|\| pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1538	pVM->rem.s.cPendingExceptions = 1;
1539	pVM->rem.s.uPendingException = uTrap;
1540	pVM->rem.s.uPendingExcptEIP = env->eip;
1541	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1542	}
1543	else
1544	{
1545	pVM->rem.s.cPendingExceptions = 0;
1546	pVM->rem.s.uPendingException = uTrap;
1547	pVM->rem.s.uPendingExcptEIP = env->eip;
1548	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1549	}
1550	return VINF_SUCCESS;
1551	}
1552
1553	/*
1554	* Clear current active trap
1555	*
1556	* @param pVM VM Handle.
1557	*/
1558	void remR3TrapClear(PVM pVM)
1559	{
1560	pVM->rem.s.cPendingExceptions = 0;
1561	pVM->rem.s.uPendingException = 0;
1562	pVM->rem.s.uPendingExcptEIP = 0;
1563	pVM->rem.s.uPendingExcptCR2 = 0;
1564	}
1565
1566
1567	/**
1568	* Syncs the internal REM state with the VM.
1569	*
1570	* This must be called before REMR3Run() is invoked whenever when the REM
1571	* state is not up to date. Calling it several times in a row is not
1572	* permitted.
1573	*
1574	* @returns VBox status code.
1575	*
1576	* @param pVM VM Handle.
1577	*
1578	* @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1579	* no do this since the majority of the callers don't want any unnecessary of events
1580	* pending that would immediatly interrupt execution.
1581	*/
1582	REMR3DECL(int) REMR3State(PVM pVM)
1583	{
1584	Assert(!pVM->rem.s.fInREM);
1585	Log2(("REMR3State:\n"));
1586	STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1587	register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1588	register unsigned fFlags;
1589
1590	/*
1591	* Copy the registers which requires no special handling.
1592	*/
1593	Assert(R_EAX == 0);
1594	pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1595	Assert(R_ECX == 1);
1596	pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1597	Assert(R_EDX == 2);
1598	pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1599	Assert(R_EBX == 3);
1600	pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1601	Assert(R_ESP == 4);
1602	pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1603	Assert(R_EBP == 5);
1604	pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1605	Assert(R_ESI == 6);
1606	pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1607	Assert(R_EDI == 7);
1608	pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1609	pVM->rem.s.Env.eip = pCtx->eip;
1610
1611	pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1612
1613	pVM->rem.s.Env.cr[2] = pCtx->cr2;
1614
1615	/** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1616	pVM->rem.s.Env.dr[0] = pCtx->dr0;
1617	pVM->rem.s.Env.dr[1] = pCtx->dr1;
1618	pVM->rem.s.Env.dr[2] = pCtx->dr2;
1619	pVM->rem.s.Env.dr[3] = pCtx->dr3;
1620	pVM->rem.s.Env.dr[4] = pCtx->dr4;
1621	pVM->rem.s.Env.dr[5] = pCtx->dr5;
1622	pVM->rem.s.Env.dr[6] = pCtx->dr6;
1623	pVM->rem.s.Env.dr[7] = pCtx->dr7;
1624
1625	/*
1626	* Replay invlpg?
1627	*/
1628	if (pVM->rem.s.cInvalidatedPages)
1629	{
1630	pVM->rem.s.fIgnoreInvlPg = true;
1631	RTUINT i;
1632	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1633	{
1634	Log2(("REMR3State: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1635	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1636	}
1637	pVM->rem.s.fIgnoreInvlPg = false;
1638	pVM->rem.s.cInvalidatedPages = 0;
1639	}
1640
1641	/*
1642	* Registers which are seldomly changed and require special handling / order when changed.
1643	*/
1644	fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1645	if (fFlags & ( CPUM_CHANGED_CR4 \| CPUM_CHANGED_CR3 \| CPUM_CHANGED_CR0
1646	\| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_TR
1647	\| CPUM_CHANGED_FPU_REM \| CPUM_CHANGED_SYSENTER_MSR))
1648	{
1649	if (fFlags & CPUM_CHANGED_FPU_REM)
1650	save_raw_fp_state(&pVM->rem.s.Env, (uint8_t )&pCtx->fpu); / 'save' is an excellent name. */
1651
1652	if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1653	{
1654	pVM->rem.s.fIgnoreCR3Load = true;
1655	tlb_flush(&pVM->rem.s.Env, true);
1656	pVM->rem.s.fIgnoreCR3Load = false;
1657	}
1658
1659	if (fFlags & CPUM_CHANGED_CR4)
1660	{
1661	pVM->rem.s.fIgnoreCR3Load = true;
1662	pVM->rem.s.fIgnoreCpuMode = true;
1663	cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1664	pVM->rem.s.fIgnoreCpuMode = false;
1665	pVM->rem.s.fIgnoreCR3Load = false;
1666	}
1667
1668	if (fFlags & CPUM_CHANGED_CR0)
1669	{
1670	pVM->rem.s.fIgnoreCR3Load = true;
1671	pVM->rem.s.fIgnoreCpuMode = true;
1672	cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1673	pVM->rem.s.fIgnoreCpuMode = false;
1674	pVM->rem.s.fIgnoreCR3Load = false;
1675	}
1676
1677	if (fFlags & CPUM_CHANGED_CR3)
1678	{
1679	pVM->rem.s.fIgnoreCR3Load = true;
1680	cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1681	pVM->rem.s.fIgnoreCR3Load = false;
1682	}
1683
1684	if (fFlags & CPUM_CHANGED_GDTR)
1685	{
1686	pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1687	pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1688	}
1689
1690	if (fFlags & CPUM_CHANGED_IDTR)
1691	{
1692	pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1693	pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1694	}
1695
1696	if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1697	{
1698	pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1699	pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1700	pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1701	}
1702
1703	if (fFlags & CPUM_CHANGED_LDTR)
1704	{
1705	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1706	{
1707	pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1708	pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u32Base;
1709	pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1710	pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1711	}
1712	else
1713	sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1714	}
1715
1716	if (fFlags & CPUM_CHANGED_TR)
1717	{
1718	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1719	{
1720	pVM->rem.s.Env.tr.selector = pCtx->tr;
1721	pVM->rem.s.Env.tr.base = pCtx->trHid.u32Base;
1722	pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1723	pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1724	}
1725	else
1726	sync_tr(&pVM->rem.s.Env, pCtx->tr);
1727
1728	/** @note do_interrupt will fault if the busy flag is still set.... */
1729	pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1730	}
1731	}
1732
1733	/*
1734	* Update selector registers.
1735	* This must be done after we've synced gdt, ldt and crX registers
1736	* since we're reading the GDT/LDT om sync_seg. This will happen with
1737	* saved state which takes a quick dip into rawmode for instance.
1738	*/
1739	/*
1740	* Stack; Note first check this one as the CPL might have changed. The
1741	* wrong CPL can cause QEmu to raise an exception in sync_seg!!
1742	*/
1743
1744	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1745	{
1746	/* The hidden selector registers are valid in the CPU context. */
1747	/** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1748
1749	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1750	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1751	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1752	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1753	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1754	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1755
1756	/* Set current CPL. */
1757	if (pCtx->eflags.Bits.u1VM == 1)
1758	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1759	else
1760	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1761	}
1762	else
1763	{
1764	/* In 'normal' raw mode we don't have access to the hidden selector registers. */
1765	if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1766	{
1767	Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1768	if (pCtx->eflags.Bits.u1VM == 1)
1769	{
1770	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1771	pVM->rem.s.Env.segs[R_SS].selector = (uint16_t)pCtx->ss;
1772	}
1773	else
1774	{
1775	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1776	sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1777	#ifdef VBOX_WITH_STATISTICS
1778	if (pVM->rem.s.Env.segs[R_SS].newselector)
1779	{
1780	STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1781	}
1782	#endif
1783	}
1784	}
1785	else
1786	pVM->rem.s.Env.segs[R_SS].newselector = 0;
1787
1788	if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1789	{
1790	Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1791	if (pCtx->eflags.Bits.u1VM == 1)
1792	{
1793	pVM->rem.s.Env.segs[R_ES].selector = (uint16_t)pCtx->es;
1794	}
1795	else
1796	{
1797	sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1798	#ifdef VBOX_WITH_STATISTICS
1799	if (pVM->rem.s.Env.segs[R_ES].newselector)
1800	{
1801	STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1802	}
1803	#endif
1804	}
1805	}
1806	else
1807	pVM->rem.s.Env.segs[R_ES].newselector = 0;
1808
1809	if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1810	{
1811	Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1812	if (pCtx->eflags.Bits.u1VM == 1)
1813	{
1814	pVM->rem.s.Env.segs[R_CS].selector = (uint16_t)pCtx->cs;
1815	}
1816	else
1817	{
1818	sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1819	#ifdef VBOX_WITH_STATISTICS
1820	if (pVM->rem.s.Env.segs[R_CS].newselector)
1821	{
1822	STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1823	}
1824	#endif
1825	}
1826	}
1827	else
1828	pVM->rem.s.Env.segs[R_CS].newselector = 0;
1829
1830	if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1831	{
1832	Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1833	if (pCtx->eflags.Bits.u1VM == 1)
1834	{
1835	pVM->rem.s.Env.segs[R_DS].selector = (uint16_t)pCtx->ds;
1836	}
1837	else
1838	{
1839	sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1840	#ifdef VBOX_WITH_STATISTICS
1841	if (pVM->rem.s.Env.segs[R_DS].newselector)
1842	{
1843	STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1844	}
1845	#endif
1846	}
1847	}
1848	else
1849	pVM->rem.s.Env.segs[R_DS].newselector = 0;
1850
1851	/** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1852	* be the same but not the base/limit. */
1853	if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1854	{
1855	Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1856	if (pCtx->eflags.Bits.u1VM == 1)
1857	{
1858	pVM->rem.s.Env.segs[R_FS].selector = (uint16_t)pCtx->fs;
1859	}
1860	else
1861	{
1862	sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1863	#ifdef VBOX_WITH_STATISTICS
1864	if (pVM->rem.s.Env.segs[R_FS].newselector)
1865	{
1866	STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1867	}
1868	#endif
1869	}
1870	}
1871	else
1872	pVM->rem.s.Env.segs[R_FS].newselector = 0;
1873
1874	if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1875	{
1876	Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1877	if (pCtx->eflags.Bits.u1VM == 1)
1878	{
1879	pVM->rem.s.Env.segs[R_GS].selector = (uint16_t)pCtx->gs;
1880	}
1881	else
1882	{
1883	sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1884	#ifdef VBOX_WITH_STATISTICS
1885	if (pVM->rem.s.Env.segs[R_GS].newselector)
1886	{
1887	STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1888	}
1889	#endif
1890	}
1891	}
1892	else
1893	pVM->rem.s.Env.segs[R_GS].newselector = 0;
1894	}
1895
1896	/*
1897	* Check for traps.
1898	*/
1899	pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
1900	bool fIsSoftwareInterrupt;
1901	uint8_t u8TrapNo;
1902	int rc = TRPMQueryTrap(pVM, &u8TrapNo, &fIsSoftwareInterrupt);
1903	if (VBOX_SUCCESS(rc))
1904	{
1905	#ifdef DEBUG
1906	if (u8TrapNo == 0x80)
1907	{
1908	remR3DumpLnxSyscall(pVM);
1909	remR3DumpOBsdSyscall(pVM);
1910	}
1911	#endif
1912
1913	pVM->rem.s.Env.exception_index = u8TrapNo;
1914	if (!fIsSoftwareInterrupt)
1915	{
1916	pVM->rem.s.Env.exception_is_int = 0;
1917	pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
1918	}
1919	else
1920	{
1921	/*
1922	* The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
1923	* We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
1924	* for int03 and into.
1925	*/
1926	pVM->rem.s.Env.exception_is_int = 1;
1927	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 2;
1928	/* int 3 may be generated by one-byte 0xcc */
1929	if (u8TrapNo == 3)
1930	{
1931	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xcc)
1932	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1933	}
1934	/* int 4 may be generated by one-byte 0xce */
1935	else if (u8TrapNo == 4)
1936	{
1937	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xce)
1938	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1939	}
1940	}
1941
1942	/* get error code and cr2 if needed. */
1943	switch (u8TrapNo)
1944	{
1945	case 0x0e:
1946	pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
1947	/* fallthru */
1948	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
1949	pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
1950	break;
1951
1952	case 0x11: case 0x08:
1953	default:
1954	pVM->rem.s.Env.error_code = 0;
1955	break;
1956	}
1957
1958	/*
1959	* We can now reset the active trap since the recompiler is gonna have a go at it.
1960	*/
1961	rc = TRPMResetTrap(pVM);
1962	AssertRC(rc);
1963	Log2(("REMR3State: trap=%02x errcd=%VGv cr2=%VGv nexteip=%VGv%s\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.error_code,
1964	pVM->rem.s.Env.cr[2], pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
1965	//if (pVM->rem.s.Env.eip == 0x40005a2f)
1966	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP \| CPU_RAW_MODE_DISABLED \| CPU_RAWR0_MODE_DISABLED;
1967	}
1968
1969	/*
1970	* Clear old interrupt request flags; Check for pending hardware interrupts.
1971	* (See @remark for why we don't check for other FFs.)
1972	*/
1973	pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER);
1974	if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
1975	\|\| VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
1976	pVM->rem.s.Env.interrupt_request \|= CPU_INTERRUPT_HARD;
1977
1978	/*
1979	* We're now in REM mode.
1980	*/
1981	pVM->rem.s.fInREM = true;
1982	pVM->rem.s.cCanExecuteRaw = 0;
1983	STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
1984	Log2(("REMR3State: returns VINF_SUCCESS\n"));
1985	return VINF_SUCCESS;
1986	}
1987
1988
1989	/**
1990	* Syncs back changes in the REM state to the the VM state.
1991	*
1992	* This must be called after invoking REMR3Run().
1993	* Calling it several times in a row is not permitted.
1994	*
1995	* @returns VBox status code.
1996	*
1997	* @param pVM VM Handle.
1998	*/
1999	REMR3DECL(int) REMR3StateBack(PVM pVM)
2000	{
2001	Log2(("REMR3StateBack:\n"));
2002	Assert(pVM->rem.s.fInREM);
2003	STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2004	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2005
2006	/*
2007	* Copy back the registers.
2008	* This is done in the order they are declared in the CPUMCTX structure.
2009	*/
2010
2011	/** @todo FOP */
2012	/** @todo FPUIP */
2013	/** @todo CS */
2014	/** @todo FPUDP */
2015	/** @todo DS */
2016	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2017	pCtx->fpu.MXCSR = 0;
2018	pCtx->fpu.MXCSR_MASK = 0;
2019
2020	/** @todo check if FPU/XMM was actually used in the recompiler */
2021	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2022	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2023
2024	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2025	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2026	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2027	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2028	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2029	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2030	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2031
2032	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2033	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2034
2035	#ifdef VBOX_WITH_STATISTICS
2036	if (pVM->rem.s.Env.segs[R_SS].newselector)
2037	{
2038	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
2039	}
2040	if (pVM->rem.s.Env.segs[R_GS].newselector)
2041	{
2042	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
2043	}
2044	if (pVM->rem.s.Env.segs[R_FS].newselector)
2045	{
2046	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
2047	}
2048	if (pVM->rem.s.Env.segs[R_ES].newselector)
2049	{
2050	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
2051	}
2052	if (pVM->rem.s.Env.segs[R_DS].newselector)
2053	{
2054	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2055	}
2056	if (pVM->rem.s.Env.segs[R_CS].newselector)
2057	{
2058	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2059	}
2060	#endif
2061	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2062	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2063	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2064	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2065	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2066
2067	pCtx->eip = pVM->rem.s.Env.eip;
2068	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2069
2070	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2071	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2072	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2073	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2074
2075	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2076	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2077	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2078	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2079	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2080	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2081	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2082	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2083
2084	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2085	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2086	{
2087	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2088	STAM_COUNTER_INC(&gStatREMGDTChange);
2089	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2090	}
2091
2092	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2093	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2094	{
2095	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2096	STAM_COUNTER_INC(&gStatREMIDTChange);
2097	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2098	}
2099
2100	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2101	{
2102	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2103	STAM_COUNTER_INC(&gStatREMLDTRChange);
2104	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2105	}
2106	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2107	{
2108	pCtx->tr = pVM->rem.s.Env.tr.selector;
2109	STAM_COUNTER_INC(&gStatREMTRChange);
2110	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2111	}
2112
2113	/** @todo These values could still be out of sync! */
2114	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2115	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2116	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2117	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2118
2119	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2120	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2121	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2122
2123	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2124	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2125	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2126
2127	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2128	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2129	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2130
2131	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2132	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2133	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2134
2135	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2136	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2137	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2138
2139	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2140	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2141	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2142
2143	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2144	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2145	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2146
2147	/* Sysenter MSR */
2148	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2149	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2150	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2151
2152	remR3TrapClear(pVM);
2153
2154	/*
2155	* Check for traps.
2156	*/
2157	if ( pVM->rem.s.Env.exception_index >= 0
2158	&& pVM->rem.s.Env.exception_index < 256)
2159	{
2160	Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2161	int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int);
2162	AssertRC(rc);
2163	switch (pVM->rem.s.Env.exception_index)
2164	{
2165	case 0x0e:
2166	TRPMSetFaultAddress(pVM, pCtx->cr2);
2167	/* fallthru */
2168	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2169	case 0x11: case 0x08: /* 0 */
2170	TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2171	break;
2172	}
2173
2174	}
2175
2176	/*
2177	* We're not longer in REM mode.
2178	*/
2179	pVM->rem.s.fInREM = false;
2180	STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2181	Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2182	return VINF_SUCCESS;
2183	}
2184
2185
2186	/**
2187	* This is called by the disassembler when it wants to update the cpu state
2188	* before for instance doing a register dump.
2189	*/
2190	static void remR3StateUpdate(PVM pVM)
2191	{
2192	Assert(pVM->rem.s.fInREM);
2193	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2194
2195	/*
2196	* Copy back the registers.
2197	* This is done in the order they are declared in the CPUMCTX structure.
2198	*/
2199
2200	/** @todo FOP */
2201	/** @todo FPUIP */
2202	/** @todo CS */
2203	/** @todo FPUDP */
2204	/** @todo DS */
2205	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2206	pCtx->fpu.MXCSR = 0;
2207	pCtx->fpu.MXCSR_MASK = 0;
2208
2209	/** @todo check if FPU/XMM was actually used in the recompiler */
2210	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2211	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2212
2213	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2214	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2215	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2216	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2217	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2218	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2219	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2220
2221	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2222	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2223
2224	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2225	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2226	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2227	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2228	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2229
2230	pCtx->eip = pVM->rem.s.Env.eip;
2231	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2232
2233	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2234	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2235	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2236	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2237
2238	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2239	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2240	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2241	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2242	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2243	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2244	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2245	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2246
2247	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2248	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2249	{
2250	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2251	STAM_COUNTER_INC(&gStatREMGDTChange);
2252	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2253	}
2254
2255	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2256	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2257	{
2258	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2259	STAM_COUNTER_INC(&gStatREMIDTChange);
2260	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2261	}
2262
2263	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2264	{
2265	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2266	STAM_COUNTER_INC(&gStatREMLDTRChange);
2267	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2268	}
2269	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2270	{
2271	pCtx->tr = pVM->rem.s.Env.tr.selector;
2272	STAM_COUNTER_INC(&gStatREMTRChange);
2273	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2274	}
2275
2276	/** @todo These values could still be out of sync! */
2277	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2278	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2279	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2280	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2281
2282	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2283	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2284	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2285
2286	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2287	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2288	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2289
2290	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2291	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2292	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2293
2294	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2295	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2296	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2297
2298	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2299	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2300	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2301
2302	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2303	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2304	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2305
2306	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2307	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2308	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2309
2310	/* Sysenter MSR */
2311	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2312	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2313	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2314	}
2315
2316
2317	/**
2318	* Update the VMM state information if we're currently in REM.
2319	*
2320	* This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2321	* we're currently executing in REM and the VMM state is invalid. This method will of
2322	* course check that we're executing in REM before syncing any data over to the VMM.
2323	*
2324	* @param pVM The VM handle.
2325	*/
2326	REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2327	{
2328	if (pVM->rem.s.fInREM)
2329	remR3StateUpdate(pVM);
2330	}
2331
2332
2333	#undef LOG_GROUP
2334	#define LOG_GROUP LOG_GROUP_REM
2335
2336
2337	/**
2338	* Notify the recompiler about Address Gate 20 state change.
2339	*
2340	* This notification is required since A20 gate changes are
2341	* initialized from a device driver and the VM might just as
2342	* well be in REM mode as in RAW mode.
2343	*
2344	* @param pVM VM handle.
2345	* @param fEnable True if the gate should be enabled.
2346	* False if the gate should be disabled.
2347	*/
2348	REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2349	{
2350	LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2351	VM_ASSERT_EMT(pVM);
2352	cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2353	}
2354
2355
2356	/**
2357	* Replays the invalidated recorded pages.
2358	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2359	*
2360	* @param pVM VM handle.
2361	*/
2362	REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2363	{
2364	VM_ASSERT_EMT(pVM);
2365
2366	/*
2367	* Sync the required registers.
2368	*/
2369	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2370	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2371	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2372	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2373
2374	/*
2375	* Replay the flushes.
2376	*/
2377	pVM->rem.s.fIgnoreInvlPg = true;
2378	RTUINT i;
2379	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2380	{
2381	Log2(("REMR3ReplayInvalidatedPages: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2382	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2383	}
2384	pVM->rem.s.fIgnoreInvlPg = false;
2385	pVM->rem.s.cInvalidatedPages = 0;
2386	}
2387
2388
2389	/**
2390	* Replays the invalidated recorded pages.
2391	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2392	*
2393	* @param pVM VM handle.
2394	*/
2395	REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2396	{
2397	LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2398	VM_ASSERT_EMT(pVM);
2399
2400	/*
2401	* Replay the flushes.
2402	*/
2403	RTUINT i;
2404	const RTUINT c = pVM->rem.s.cHandlerNotifications;
2405	pVM->rem.s.cHandlerNotifications = 0;
2406	for (i = 0; i < c; i++)
2407	{
2408	PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2409	switch (pRec->enmKind)
2410	{
2411	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2412	REMR3NotifyHandlerPhysicalRegister(pVM,
2413	pRec->u.PhysicalRegister.enmType,
2414	pRec->u.PhysicalRegister.GCPhys,
2415	pRec->u.PhysicalRegister.cb,
2416	pRec->u.PhysicalRegister.fHasHCHandler);
2417	break;
2418
2419	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2420	REMR3NotifyHandlerPhysicalDeregister(pVM,
2421	pRec->u.PhysicalDeregister.enmType,
2422	pRec->u.PhysicalDeregister.GCPhys,
2423	pRec->u.PhysicalDeregister.cb,
2424	pRec->u.PhysicalDeregister.fHasHCHandler,
2425	pRec->u.PhysicalDeregister.pvHCPtr);
2426	break;
2427
2428	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2429	REMR3NotifyHandlerPhysicalModify(pVM,
2430	pRec->u.PhysicalModify.enmType,
2431	pRec->u.PhysicalModify.GCPhysOld,
2432	pRec->u.PhysicalModify.GCPhysNew,
2433	pRec->u.PhysicalModify.cb,
2434	pRec->u.PhysicalModify.fHasHCHandler,
2435	pRec->u.PhysicalModify.pvHCPtr);
2436	break;
2437
2438	default:
2439	AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2440	break;
2441	}
2442	}
2443	}
2444
2445
2446	/**
2447	* Notify REM about changed code page.
2448	*
2449	* @returns VBox status code.
2450	* @param pVM VM handle.
2451	* @param pvCodePage Code page address
2452	*/
2453	REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2454	{
2455	int rc;
2456	RTGCPHYS PhysGC;
2457	uint64_t flags;
2458
2459	VM_ASSERT_EMT(pVM);
2460
2461	/*
2462	* Get the physical page address.
2463	*/
2464	rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2465	if (rc == VINF_SUCCESS)
2466	{
2467	/*
2468	* Sync the required registers and flush the whole page.
2469	* (Easier to do the whole page than notifying it about each physical
2470	* byte that was changed.
2471	*/
2472	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2473	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2474	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2475	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2476
2477	tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2478	}
2479	return VINF_SUCCESS;
2480	}
2481
2482	/**
2483	* Notification about a successful MMR3PhysRegister() call.
2484	*
2485	* @param pVM VM handle.
2486	* @param GCPhys The physical address the RAM.
2487	* @param cb Size of the memory.
2488	* @param pvRam The HC address of the RAM.
2489	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2490	*/
2491	REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
2492	{
2493	Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2494	VM_ASSERT_EMT(pVM);
2495
2496	/*
2497	* Validate input - we trust the caller.
2498	*/
2499	Assert(!GCPhys \|\| pvRam);
2500	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2501	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2502	Assert(cb);
2503	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2504
2505	/*
2506	* Base ram?
2507	*/
2508	if (!GCPhys)
2509	{
2510	#ifndef PGM_DYNAMIC_RAM_ALLOC
2511	AssertRelease(!phys_ram_base);
2512	phys_ram_base = pvRam;
2513	#endif
2514	phys_ram_size = cb;
2515	phys_ram_dirty = MMR3HeapAllocZ(pVM, MM_TAG_REM, cb >> PAGE_SHIFT);
2516	AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", cb >> PAGE_SHIFT));
2517	}
2518	#ifndef PGM_DYNAMIC_RAM_ALLOC
2519	AssertRelease(phys_ram_base);
2520	#endif
2521
2522	/*
2523	* Register the ram.
2524	*/
2525	#ifdef PGM_DYNAMIC_RAM_ALLOC
2526	if (!GCPhys)
2527	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_RAM_MISSING);
2528	else
2529	{
2530	cpu_register_physical_memory(GCPhys, cb, GCPhys \| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2531
2532	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2533	pVM->rem.s.aPhysReg[pVM->rem.s.cPhysRegistrations].GCPhys = GCPhys;
2534	pVM->rem.s.aPhysReg[pVM->rem.s.cPhysRegistrations].HCVirt = (RTHCUINTPTR)pvRam;
2535	pVM->rem.s.aPhysReg[pVM->rem.s.cPhysRegistrations].cb = cb;
2536	pVM->rem.s.cPhysRegistrations++;
2537	}
2538	#else
2539	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvRam - (uintptr_t)phys_ram_base)
2540	\| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2541	#endif
2542	}
2543
2544
2545	/**
2546	* Notification about a successful PGMR3PhysRegisterChunk() call.
2547	*
2548	* @param pVM VM handle.
2549	* @param GCPhys The physical address the RAM.
2550	* @param cb Size of the memory.
2551	* @param pvRam The HC address of the RAM.
2552	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2553	*/
2554	REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2555	{
2556	uint32_t idx;
2557
2558	Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2559	VM_ASSERT_EMT(pVM);
2560
2561	/*
2562	* Validate input - we trust the caller.
2563	*/
2564	Assert(pvRam);
2565	Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2566	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2567	Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2568	Assert(fFlags == 0 /* normal RAM */);
2569
2570	if (!pVM->rem.s.paHCVirtToGCPhys)
2571	{
2572	uint32_t size = (_4G >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(REMCHUNKINFO);
2573
2574	Assert(phys_ram_size);
2575
2576	pVM->rem.s.paHCVirtToGCPhys = (PREMCHUNKINFO)MMR3HeapAllocZ(pVM, MM_TAG_REM, size);
2577	pVM->rem.s.paGCPhysToHCVirt = (RTHCPTR)MMR3HeapAllocZ(pVM, MM_TAG_REM, (phys_ram_size >> PGM_DYNAMIC_CHUNK_SHIFT)*sizeof(RTHCPTR));
2578	}
2579	pVM->rem.s.paGCPhysToHCVirt[GCPhys >> PGM_DYNAMIC_CHUNK_SHIFT] = pvRam;
2580
2581	idx = (pvRam >> PGM_DYNAMIC_CHUNK_SHIFT);
2582	if (!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1)
2583	{
2584	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1 = pvRam;
2585	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 = GCPhys;
2586	}
2587	else
2588	{
2589	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2);
2590	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2 = pvRam;
2591	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 = GCPhys;
2592	}
2593	/* Does the region spawn two chunks? */
2594	if (pvRam & PGM_DYNAMIC_CHUNK_OFFSET_MASK)
2595	{
2596	if (!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1)
2597	{
2598	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1 = pvRam;
2599	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys1 = GCPhys;
2600	}
2601	else
2602	{
2603	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2);
2604	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2 = pvRam;
2605	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys2 = GCPhys;
2606	}
2607	}
2608	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2609	}
2610
2611	/**
2612	* Convert GC physical address to HC virt
2613	*
2614	* @returns The HC virt address corresponding to addr.
2615	* @param env The cpu environment.
2616	* @param addr The physical address.
2617	*/
2618	void remR3GCPhys2HCVirt(void env, target_ulong addr)
2619	{
2620	#ifdef PGM_DYNAMIC_RAM_ALLOC
2621	PVM pVM = ((CPUState *)env)->pVM;
2622	uint32_t i;
2623
2624	/* lookup in pVM->rem.s.aPhysReg array first (for ROM range(s) inside the guest's RAM) */
2625	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2626	{
2627	uint32_t off = addr - pVM->rem.s.aPhysReg[i].GCPhys;
2628	if (off < pVM->rem.s.aPhysReg[i].cb)
2629	{
2630	Log(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].HCVirt + off));
2631	return (void *)(pVM->rem.s.aPhysReg[i].HCVirt + off);
2632	}
2633	}
2634	Assert(addr < phys_ram_size);
2635	Log(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK)));
2636	return (void *)(pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2637	#else
2638	return phys_ram_base + addr;
2639	#endif
2640	}
2641
2642	/**
2643	* Convert GC physical address to HC virt
2644	*
2645	* @returns The HC virt address corresponding to addr.
2646	* @param env The cpu environment.
2647	* @param addr The physical address.
2648	*/
2649	target_ulong remR3HCVirt2GCPhys(void env, void addr)
2650	{
2651	#ifdef PGM_DYNAMIC_RAM_ALLOC
2652	PVM pVM = ((CPUState *)env)->pVM;
2653	RTHCUINTPTR HCVirt = (RTHCUINTPTR)addr;
2654	uint32_t idx = (HCVirt >> PGM_DYNAMIC_CHUNK_SHIFT);
2655	RTHCUINTPTR off;
2656	RTUINT i;
2657
2658	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1;
2659
2660	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1
2661	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2662	{
2663	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off));
2664	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off;
2665	}
2666
2667	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2;
2668	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2
2669	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2670	{
2671	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off));
2672	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off;
2673	}
2674
2675	/* Must be externally registered RAM/ROM range */
2676	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2677	{
2678	uint32_t off = HCVirt - pVM->rem.s.aPhysReg[i].HCVirt;
2679	if (off < pVM->rem.s.aPhysReg[i].cb)
2680	{
2681	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].GCPhys + off));
2682	return pVM->rem.s.aPhysReg[i].GCPhys + off;
2683	}
2684	}
2685	AssertReleaseMsgFailed(("No translation for physical address %p???\n", addr));
2686	return 0;
2687	#else
2688	return (target_ulong)addr - (target_ulong)phys_ram_base;
2689	#endif
2690	}
2691
2692	/**
2693	* Grows dynamically allocated guest RAM.
2694	* Will raise a fatal error if the operation fails.
2695	*
2696	* @param physaddr The physical address.
2697	*/
2698	void remR3GrowDynRange(unsigned long physaddr)
2699	{
2700	int rc;
2701	PVM pVM = cpu_single_env->pVM;
2702
2703	Log(("remR3GrowDynRange %VGp\n", physaddr));
2704	rc = PGM3PhysGrowRange(pVM, (RTGCPHYS)physaddr);
2705	if (VBOX_SUCCESS(rc))
2706	return;
2707
2708	LogRel(("\nUnable to allocate guest RAM chunk at %VGp\n", physaddr));
2709	cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %VGp\n", physaddr);
2710	AssertFatalFailed();
2711	}
2712
2713	/**
2714	* Notification about a successful MMR3PhysRomRegister() call.
2715	*
2716	* @param pVM VM handle.
2717	* @param GCPhys The physical address of the ROM.
2718	* @param cb The size of the ROM.
2719	* @param pvCopy Pointer to the ROM copy.
2720	*/
2721	REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy)
2722	{
2723	Log(("REMR3NotifyPhysRomRegister: GCPhys=%VGp cb=%d pvCopy=%p\n", GCPhys, cb, pvCopy));
2724	VM_ASSERT_EMT(pVM);
2725
2726	/*
2727	* Validate input - we trust the caller.
2728	*/
2729	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2730	Assert(cb);
2731	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2732	Assert(pvCopy);
2733	Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2734
2735	/*
2736	* Register the rom.
2737	*/
2738	#ifdef PGM_DYNAMIC_RAM_ALLOC
2739	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_ROM);
2740	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2741	pVM->rem.s.aPhysReg[pVM->rem.s.cPhysRegistrations].GCPhys = GCPhys;
2742	pVM->rem.s.aPhysReg[pVM->rem.s.cPhysRegistrations].HCVirt = (RTHCUINTPTR)pvCopy;
2743	pVM->rem.s.aPhysReg[pVM->rem.s.cPhysRegistrations].cb = cb;
2744	pVM->rem.s.cPhysRegistrations++;
2745	#else
2746	AssertRelease(phys_ram_base);
2747	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvCopy - (uintptr_t)phys_ram_base) \| IO_MEM_ROM);
2748	#endif
2749	Log2(("%.64Vhxd\n", (char *)pvCopy + cb - 64));
2750	}
2751
2752
2753	/**
2754	* Notification about a successful MMR3PhysRegister() call.
2755	*
2756	* @param pVM VM Handle.
2757	* @param GCPhys Start physical address.
2758	* @param cb The size of the range.
2759	*/
2760	REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2761	{
2762	LogFlow(("REMR3NotifyPhysReserve: GCPhys=%VGp cb=%d\n", GCPhys, cb));
2763	VM_ASSERT_EMT(pVM);
2764
2765	/*
2766	* Validate input - we trust the caller.
2767	*/
2768	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2769	Assert(cb);
2770	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2771
2772	/*
2773	* Unassigning the memory.
2774	*/
2775	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2776	}
2777
2778
2779	/**
2780	* Notification about a successful PGMR3HandlerPhysicalRegister() call.
2781	*
2782	* @param pVM VM Handle.
2783	* @param enmType Handler type.
2784	* @param GCPhys Handler range address.
2785	* @param cb Size of the handler range.
2786	* @param fHasHCHandler Set if the handler has a HC callback function.
2787	*
2788	* @remark MMR3PhysRomRegister assumes that this function will not apply the
2789	* Handler memory type to memory which has no HC handler.
2790	*/
2791	REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2792	{
2793	LogFlow(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d\n",
2794	enmType, GCPhys, cb, fHasHCHandler));
2795	VM_ASSERT_EMT(pVM);
2796	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2797	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2798
2799	if (pVM->rem.s.cHandlerNotifications)
2800	REMR3ReplayHandlerNotifications(pVM);
2801
2802	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2803	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2804	else if (fHasHCHandler)
2805	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2806	}
2807
2808
2809	/**
2810	* Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2811	*
2812	* @param pVM VM Handle.
2813	* @param enmType Handler type.
2814	* @param GCPhys Handler range address.
2815	* @param cb Size of the handler range.
2816	* @param fHasHCHandler Set if the handler has a HC callback function.
2817	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2818	*/
2819	REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2820	{
2821	LogFlow(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p RAM=%08x\n",
2822	enmType, GCPhys, cb, fHasHCHandler, pvHCPtr, MMR3PhysGetRamSize(pVM)));
2823	VM_ASSERT_EMT(pVM);
2824
2825	if (pVM->rem.s.cHandlerNotifications)
2826	REMR3ReplayHandlerNotifications(pVM);
2827
2828	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2829	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2830	else if (fHasHCHandler)
2831	{
2832	if (!pvHCPtr)
2833	{
2834	Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2835	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2836	}
2837	else
2838	{
2839	/* This is not prefect, but it'll do for PD monitoring... */
2840	Assert(cb == PAGE_SIZE);
2841	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2842	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2843	#ifdef PGM_DYNAMIC_RAM_ALLOC
2844	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2845	#else
2846	cpu_register_physical_memory(GCPhys, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2847	#endif
2848	}
2849	}
2850	}
2851
2852
2853	/**
2854	* Notification about a successful PGMR3HandlerPhysicalModify() call.
2855	*
2856	* @param pVM VM Handle.
2857	* @param enmType Handler type.
2858	* @param GCPhysOld Old handler range address.
2859	* @param GCPhysNew New handler range address.
2860	* @param cb Size of the handler range.
2861	* @param fHasHCHandler Set if the handler has a HC callback function.
2862	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2863	*/
2864	REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2865	{
2866	LogFlow(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%VGp GCPhysNew=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p\n",
2867	enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, pvHCPtr));
2868	VM_ASSERT_EMT(pVM);
2869	AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2870
2871	if (pVM->rem.s.cHandlerNotifications)
2872	REMR3ReplayHandlerNotifications(pVM);
2873
2874	if (fHasHCHandler)
2875	{
2876	/*
2877	* Reset the old page.
2878	*/
2879	if (!pvHCPtr)
2880	cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2881	else
2882	{
2883	/* This is not prefect, but it'll do for PD monitoring... */
2884	Assert(cb == PAGE_SIZE);
2885	Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2886	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2887	#ifdef PGM_DYNAMIC_RAM_ALLOC
2888	cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2889	#else
2890	cpu_register_physical_memory(GCPhysOld, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2891	#endif
2892	}
2893
2894	/*
2895	* Update the new page.
2896	*/
2897	Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2898	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2899	cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2900	}
2901	}
2902
2903
2904	/**
2905	* Checks if we're handling access to this page or not.
2906	*
2907	* @returns true if we're trapping access.
2908	* @returns false if we aren't.
2909	* @param pVM The VM handle.
2910	* @param GCPhys The physical address.
2911	*
2912	* @remark This function will only work correctly in VBOX_STRICT builds!
2913	*/
2914	REMDECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
2915	{
2916	#ifdef VBOX_STRICT
2917	if (pVM->rem.s.cHandlerNotifications)
2918	REMR3ReplayHandlerNotifications(pVM);
2919
2920	unsigned long off = get_phys_page_offset(GCPhys);
2921	return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
2922	\|\| (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
2923	\|\| (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
2924	#else
2925	return false;
2926	#endif
2927	}
2928
2929
2930	/**
2931	* Deals with a rare case in get_phys_addr_code where the code
2932	* is being monitored.
2933	*
2934	* It could also be an MMIO page, in which case we will raise a fatal error.
2935	*
2936	* @returns The physical address corresponding to addr.
2937	* @param env The cpu environment.
2938	* @param addr The virtual address.
2939	* @param pTLBEntry The TLB entry.
2940	*/
2941	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry)
2942	{
2943	PVM pVM = env->pVM;
2944	if ((pTLBEntry->address & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
2945	{
2946	target_ulong ret = pTLBEntry->addend + addr;
2947	AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%VGv address=%VGv addend=%VGp ret=%VGp\n",
2948	(RTGCPTR)addr, (RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, ret);
2949	return ret;
2950	}
2951	LogRel(("\nTrying to execute code with memory type address=%VGv addend=%VGp at %VGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
2952	"*** handlers\n",
2953	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
2954	DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
2955	LogRel(("*** mmio\n"));
2956	DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
2957	LogRel(("*** phys\n"));
2958	DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
2959	cpu_abort(env, "Trying to execute code with memory type address=%VGv addend=%VGp at %VGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
2960	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
2961	AssertFatalFailed();
2962	}
2963
2964	/**
2965	* Read guest RAM and ROM.
2966	*
2967	* @param pbSrcPhys The source address. Relative to guest RAM.
2968	* @param pvDst The destination address.
2969	* @param cb Number of bytes
2970	*/
2971	void remR3PhysReadBytes(uint8_t pbSrcPhys, void pvDst, unsigned cb)
2972	{
2973	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2974
2975	/*
2976	* Calc the physical address ('off') and check that it's within the RAM.
2977	* ROM is accessed this way, even if it's not part of the RAM.
2978	*/
2979	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2980	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2981	if (off < (uintptr_t)phys_ram_size)
2982	PGMPhysRead(cpu_single_env->pVM, (RTGCPHYS)off, pvDst, cb);
2983	else
2984	{
2985	/* ROM range outside physical RAM, HC address passed directly */
2986	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2987	memcpy(pvDst, pbSrcPhys, cb);
2988	}
2989	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2990	}
2991
2992	/** @todo r=bird: s/Byte/U8/ s/Word/U16/ s/Dword/U32/, see MMIO and other functions.
2993	* It could be an idea to inline these wrapper functions... */
2994
2995	/**
2996	* Read guest RAM and ROM.
2997	*
2998	* @param pbSrcPhys The source address. Relative to guest RAM.
2999	*/
3000	uint8_t remR3PhysReadUByte(uint8_t *pbSrcPhys)
3001	{
3002	uint8_t val;
3003
3004	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3005
3006	/*
3007	* Calc the physical address ('off') and check that it's within the RAM.
3008	* ROM is accessed this way, even if it's not part of the RAM.
3009	*/
3010	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3011	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3012	if (off < (uintptr_t)phys_ram_size)
3013	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3014	else
3015	{
3016	/* ROM range outside physical RAM, HC address passed directly */
3017	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3018	val = *pbSrcPhys;
3019	}
3020	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3021	return val;
3022	}
3023
3024	/**
3025	* Read guest RAM and ROM.
3026	*
3027	* @param pbSrcPhys The source address. Relative to guest RAM.
3028	*/
3029	int8_t remR3PhysReadSByte(uint8_t *pbSrcPhys)
3030	{
3031	int8_t val;
3032
3033	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3034
3035	/*
3036	* Calc the physical address ('off') and check that it's within the RAM.
3037	* ROM is accessed this way, even if it's not part of the RAM.
3038	*/
3039	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3040	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3041	if (off < (uintptr_t)phys_ram_size)
3042	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3043	else
3044	{
3045	/* ROM range outside physical RAM, HC address passed directly */
3046	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3047	val = (int8_t )pbSrcPhys;
3048	}
3049	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3050	return val;
3051	}
3052
3053	/**
3054	* Read guest RAM and ROM.
3055	*
3056	* @param pbSrcPhys The source address. Relative to guest RAM.
3057	*/
3058	uint16_t remR3PhysReadUWord(uint8_t *pbSrcPhys)
3059	{
3060	uint16_t val;
3061
3062	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3063
3064	/*
3065	* Calc the physical address ('off') and check that it's within the RAM.
3066	* ROM is accessed this way, even if it's not part of the RAM.
3067	*/
3068	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3069	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3070	if (off < (uintptr_t)phys_ram_size)
3071	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3072	else
3073	{
3074	/* ROM range outside physical RAM, HC address passed directly */
3075	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3076	val = (uint16_t )pbSrcPhys;
3077	}
3078	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3079	return val;
3080	}
3081
3082	/**
3083	* Read guest RAM and ROM.
3084	*
3085	* @param pbSrcPhys The source address. Relative to guest RAM.
3086	*/
3087	int16_t remR3PhysReadSWord(uint8_t *pbSrcPhys)
3088	{
3089	int16_t val;
3090
3091	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3092
3093	/*
3094	* Calc the physical address ('off') and check that it's within the RAM.
3095	* ROM is accessed this way, even if it's not part of the RAM.
3096	*/
3097	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3098	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3099	if (off < (uintptr_t)phys_ram_size)
3100	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3101	else
3102	{
3103	/* ROM range outside physical RAM, HC address passed directly */
3104	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3105	val = (int16_t )pbSrcPhys;
3106	}
3107	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3108	return val;
3109	}
3110
3111	/**
3112	* Read guest RAM and ROM.
3113	*
3114	* @param pbSrcPhys The source address. Relative to guest RAM.
3115	*/
3116	uint32_t remR3PhysReadULong(uint8_t *pbSrcPhys)
3117	{
3118	uint32_t val;
3119
3120	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3121
3122	/*
3123	* Calc the physical address ('off') and check that it's within the RAM.
3124	* ROM is accessed this way, even if it's not part of the RAM.
3125	*/
3126	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3127	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3128	if (off < (uintptr_t)phys_ram_size)
3129	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3130	else
3131	{
3132	/* ROM range outside physical RAM, HC address passed directly */
3133	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3134	val = (uint32_t )pbSrcPhys;
3135	}
3136	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3137	return val;
3138	}
3139
3140	/**
3141	* Read guest RAM and ROM.
3142	*
3143	* @param pbSrcPhys The source address. Relative to guest RAM.
3144	*/
3145	int32_t remR3PhysReadSLong(uint8_t *pbSrcPhys)
3146	{
3147	int32_t val;
3148
3149	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3150
3151	/*
3152	* Calc the physical address ('off') and check that it's within the RAM.
3153	* ROM is accessed this way, even if it's not part of the RAM.
3154	*/
3155	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3156	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3157	if (off < (uintptr_t)phys_ram_size)
3158	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3159	else
3160	{
3161	/* ROM range outside physical RAM, HC address passed directly */
3162	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3163	val = (int32_t )pbSrcPhys;
3164	}
3165	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3166	return val;
3167	}
3168
3169	/**
3170	* Write guest RAM.
3171	*
3172	* @param pbDstPhys The destination address. Relative to guest RAM.
3173	* @param pvSrc The source address.
3174	* @param cb Number of bytes to write
3175	*/
3176	void remR3PhysWriteBytes(uint8_t pbDstPhys, const void pvSrc, unsigned cb)
3177	{
3178	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3179	/*
3180	* Calc the physical address ('off') and check that it's within the RAM.
3181	*/
3182	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3183	if (off < (uintptr_t)phys_ram_size)
3184	PGMPhysWrite(cpu_single_env->pVM, (RTGCPHYS)off, pvSrc, cb);
3185	else
3186	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, cb));
3187	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3188	}
3189
3190
3191	/**
3192	* Write guest RAM.
3193	*
3194	* @param pbDstPhys The destination address. Relative to guest RAM.
3195	* @param val Value
3196	*/
3197	void remR3PhysWriteByte(uint8_t *pbDstPhys, uint8_t val)
3198	{
3199	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3200	/*
3201	* Calc the physical address ('off') and check that it's within the RAM.
3202	*/
3203	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3204	if (off < (uintptr_t)phys_ram_size)
3205	PGMR3PhysWriteByte(cpu_single_env->pVM, (RTGCPHYS)off, val);
3206	else
3207	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 1));
3208	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3209	}
3210
3211	/**
3212	* Write guest RAM.
3213	*
3214	* @param pbDstPhys The destination address. Relative to guest RAM.
3215	* @param val Value
3216	*/
3217	void remR3PhysWriteWord(uint8_t *pbDstPhys, uint16_t val)
3218	{
3219	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3220	/*
3221	* Calc the physical address ('off') and check that it's within the RAM.
3222	*/
3223	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3224	if (off < (uintptr_t)phys_ram_size)
3225	PGMR3PhysWriteWord(cpu_single_env->pVM, (RTGCPHYS)off, val);
3226	else
3227	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 2));
3228	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3229	}
3230
3231	/**
3232	* Write guest RAM.
3233	*
3234	* @param pbDstPhys The destination address. Relative to guest RAM.
3235	* @param val Value
3236	*/
3237	void remR3PhysWriteDword(uint8_t *pbDstPhys, uint32_t val)
3238	{
3239	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3240	/*
3241	* Calc the physical address ('off') and check that it's within the RAM.
3242	*/
3243	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3244	if (off < (uintptr_t)phys_ram_size)
3245	PGMR3PhysWriteDword(cpu_single_env->pVM, (RTGCPHYS)off, val);
3246	else
3247	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 4));
3248	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3249	}
3250
3251
3252
3253	#undef LOG_GROUP
3254	#define LOG_GROUP LOG_GROUP_REM_MMIO
3255
3256	/** Read MMIO memory. */
3257	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3258	{
3259	uint32_t u32 = 0;
3260	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3261	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3262	Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32));
3263	return u32;
3264	}
3265
3266	/** Read MMIO memory. */
3267	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3268	{
3269	uint32_t u32 = 0;
3270	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3271	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3272	Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32));
3273	return u32;
3274	}
3275
3276	/** Read MMIO memory. */
3277	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3278	{
3279	uint32_t u32 = 0;
3280	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3281	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3282	Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32));
3283	return u32;
3284	}
3285
3286	/** Write to MMIO memory. */
3287	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3288	{
3289	Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3290	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3291	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3292	}
3293
3294	/** Write to MMIO memory. */
3295	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3296	{
3297	Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3298	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3299	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3300	}
3301
3302	/** Write to MMIO memory. */
3303	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3304	{
3305	Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3306	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3307	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3308	}
3309
3310
3311	#undef LOG_GROUP
3312	#define LOG_GROUP LOG_GROUP_REM_HANDLER
3313
3314	/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3315
3316	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3317	{
3318	Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys));
3319	uint8_t u8;
3320	PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3321	return u8;
3322	}
3323
3324	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3325	{
3326	Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys));
3327	uint16_t u16;
3328	PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3329	return u16;
3330	}
3331
3332	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3333	{
3334	Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys));
3335	uint32_t u32;
3336	PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3337	return u32;
3338	}
3339
3340	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3341	{
3342	Log2(("remR3HandlerWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3343	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3344	}
3345
3346	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3347	{
3348	Log2(("remR3HandlerWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3349	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3350	}
3351
3352	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3353	{
3354	Log2(("remR3HandlerWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3355	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3356	}
3357
3358	/* -+- disassembly -+- */
3359
3360	#undef LOG_GROUP
3361	#define LOG_GROUP LOG_GROUP_REM_DISAS
3362
3363
3364	/**
3365	* Enables or disables singled stepped disassembly.
3366	*
3367	* @returns VBox status code.
3368	* @param pVM VM handle.
3369	* @param fEnable To enable set this flag, to disable clear it.
3370	*/
3371	static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3372	{
3373	LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3374	VM_ASSERT_EMT(pVM);
3375
3376	if (fEnable)
3377	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
3378	else
3379	pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3380	return VINF_SUCCESS;
3381	}
3382
3383
3384	/**
3385	* Enables or disables singled stepped disassembly.
3386	*
3387	* @returns VBox status code.
3388	* @param pVM VM handle.
3389	* @param fEnable To enable set this flag, to disable clear it.
3390	*/
3391	REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3392	{
3393	PVMREQ pReq;
3394	int rc;
3395
3396	LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3397	if (VM_IS_EMT(pVM))
3398	return remR3DisasEnableStepping(pVM, fEnable);
3399
3400	rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3401	AssertRC(rc);
3402	if (VBOX_SUCCESS(rc))
3403	rc = pReq->iStatus;
3404	VMR3ReqFree(pReq);
3405	return rc;
3406	}
3407
3408
3409	#ifdef VBOX_WITH_DEBUGGER
3410	/**
3411	* External Debugger Command: .remstep [on\|off\|1\|0]
3412	*/
3413	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3414	{
3415	bool fEnable;
3416	int rc;
3417
3418	/* print status */
3419	if (cArgs == 0)
3420	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3421	pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3422
3423	/* convert the argument and change the mode. */
3424	rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3425	if (VBOX_FAILURE(rc))
3426	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3427	rc = REMR3DisasEnableStepping(pVM, fEnable);
3428	if (VBOX_FAILURE(rc))
3429	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3430	return rc;
3431	}
3432	#endif
3433
3434
3435	/**
3436	* Disassembles n instructions and prints them to the log.
3437	*
3438	* @returns Success indicator.
3439	* @param env Pointer to the recompiler CPU structure.
3440	* @param f32BitCode Indicates that whether or not the code should
3441	* be disassembled as 16 or 32 bit. If -1 the CS
3442	* selector will be inspected.
3443	* @param nrInstructions Nr of instructions to disassemble
3444	* @param pszPrefix
3445	* @remark not currently used for anything but ad-hoc debugging.
3446	*/
3447	bool remR3DisasBlock(CPUState env, int f32BitCode, int nrInstructions, char pszPrefix)
3448	{
3449	int i;
3450
3451	/*
3452	* Determin 16/32 bit mode.
3453	*/
3454	if (f32BitCode == -1)
3455	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3456
3457	/*
3458	* Convert cs:eip to host context address.
3459	* We don't care to much about cross page correctness presently.
3460	*/
3461	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3462	void *pvPC;
3463	if (f32BitCode && (env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3464	{
3465	/* convert eip to physical address. */
3466	int rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,
3467	GCPtrPC,
3468	env->cr[3],
3469	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE), /** @todo add longmode flag */
3470	&pvPC);
3471	if (VBOX_FAILURE(rc))
3472	{
3473	if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3474	return false;
3475	pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3476	+ (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3477	}
3478	}
3479	else
3480	{
3481	/* physical address */
3482	int rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions*16, &pvPC);
3483	if (VBOX_FAILURE(rc))
3484	return false;
3485	}
3486
3487	/*
3488	* Disassemble.
3489	*/
3490	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3491	DISCPUSTATE Cpu;
3492	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3493	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3494	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3495	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3496	//Cpu.dwUserData[2] = GCPtrPC;
3497
3498	for (i=0;i<nrInstructions;i++)
3499	{
3500	char szOutput[256];
3501	uint32_t cbOp;
3502	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3503	return false;
3504	if (pszPrefix)
3505	Log(("%s: %s", pszPrefix, szOutput));
3506	else
3507	Log(("%s", szOutput));
3508
3509	pvPC += cbOp;
3510	}
3511	return true;
3512	}
3513
3514
3515	/** @todo need to test the new code, using the old code in the mean while. */
3516	#define USE_OLD_DUMP_AND_DISASSEMBLY
3517
3518	/**
3519	* Disassembles one instruction and prints it to the log.
3520	*
3521	* @returns Success indicator.
3522	* @param env Pointer to the recompiler CPU structure.
3523	* @param f32BitCode Indicates that whether or not the code should
3524	* be disassembled as 16 or 32 bit. If -1 the CS
3525	* selector will be inspected.
3526	* @param pszPrefix
3527	*/
3528	bool remR3DisasInstr(CPUState env, int f32BitCode, char pszPrefix)
3529	{
3530	#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3531	PVM pVM = env->pVM;
3532
3533	/*
3534	* Determin 16/32 bit mode.
3535	*/
3536	if (f32BitCode == -1)
3537	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3538
3539	/*
3540	* Log registers
3541	*/
3542	if (LogIs2Enabled())
3543	{
3544	remR3StateUpdate(pVM);
3545	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3546	}
3547
3548	/*
3549	* Convert cs:eip to host context address.
3550	* We don't care to much about cross page correctness presently.
3551	*/
3552	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3553	void *pvPC;
3554	if ((env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3555	{
3556	/* convert eip to physical address. */
3557	int rc = PGMPhysGCPtr2HCPtrByGstCR3(pVM,
3558	GCPtrPC,
3559	env->cr[3],
3560	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE),
3561	&pvPC);
3562	if (VBOX_FAILURE(rc))
3563	{
3564	if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3565	return false;
3566	pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3567	+ (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3568	}
3569	}
3570	else
3571	{
3572
3573	/* physical address */
3574	int rc = PGMPhysGCPhys2HCPtr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3575	if (VBOX_FAILURE(rc))
3576	return false;
3577	}
3578
3579	/*
3580	* Disassemble.
3581	*/
3582	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3583	DISCPUSTATE Cpu;
3584	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3585	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3586	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3587	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3588	//Cpu.dwUserData[2] = GCPtrPC;
3589	char szOutput[256];
3590	uint32_t cbOp;
3591	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3592	return false;
3593
3594	if (!f32BitCode)
3595	{
3596	if (pszPrefix)
3597	Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3598	else
3599	Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3600	}
3601	else
3602	{
3603	if (pszPrefix)
3604	Log(("%s: %s", pszPrefix, szOutput));
3605	else
3606	Log(("%s", szOutput));
3607	}
3608	return true;
3609
3610	#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3611	PVM pVM = env->pVM;
3612	const bool fLog = LogIsEnabled();
3613	const bool fLog2 = LogIs2Enabled();
3614	int rc = VINF_SUCCESS;
3615
3616	/*
3617	* Don't bother if there ain't any log output to do.
3618	*/
3619	if (!fLog && !fLog2)
3620	return true;
3621
3622	/*
3623	* Update the state so DBGF reads the correct register values.
3624	*/
3625	remR3StateUpdate(pVM);
3626
3627	/*
3628	* Log registers if requested.
3629	*/
3630	if (!fLog2)
3631	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3632
3633	/*
3634	* Disassemble to log.
3635	*/
3636	if (fLog)
3637	rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3638
3639	return VBOX_SUCCESS(rc);
3640	#endif
3641	}
3642
3643
3644	/**
3645	* Disassemble recompiled code.
3646	*
3647	* @param phFileIgnored Ignored, logfile usually.
3648	* @param pvCode Pointer to the code block.
3649	* @param cb Size of the code block.
3650	*/
3651	void disas(FILE phFileIgnored, void pvCode, unsigned long cb)
3652	{
3653	if (LogIs2Enabled())
3654	{
3655	unsigned off = 0;
3656	char szOutput[256];
3657	DISCPUSTATE Cpu = {0};
3658	Cpu.mode = CPUMODE_32BIT;
3659
3660	RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3661	while (off < cb)
3662	{
3663	uint32_t cbInstr;
3664	if (DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput))
3665	RTLogPrintf("%s", szOutput);
3666	else
3667	{
3668	RTLogPrintf("disas error\n");
3669	cbInstr = 1;
3670	}
3671	off += cbInstr;
3672	}
3673	}
3674	NOREF(phFileIgnored);
3675	}
3676
3677
3678	/**
3679	* Disassemble guest code.
3680	*
3681	* @param phFileIgnored Ignored, logfile usually.
3682	* @param uCode The guest address of the code to disassemble. (flat?)
3683	* @param cb Number of bytes to disassemble.
3684	* @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3685	*/
3686	void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3687	{
3688	if (LogIs2Enabled())
3689	{
3690	PVM pVM = cpu_single_env->pVM;
3691
3692	/*
3693	* Update the state so DBGF reads the correct register values (flags).
3694	*/
3695	remR3StateUpdate(pVM);
3696
3697	/*
3698	* Do the disassembling.
3699	*/
3700	RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3701	RTSEL cs = cpu_single_env->segs[R_CS].selector;
3702	RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3703	for (;;)
3704	{
3705	char szBuf[256];
3706	size_t cbInstr;
3707	int rc = DBGFR3DisasInstrEx(pVM,
3708	cs,
3709	eip,
3710	0,
3711	szBuf, sizeof(szBuf),
3712	&cbInstr);
3713	if (VBOX_SUCCESS(rc))
3714	RTLogPrintf("%VGp %s\n", uCode, szBuf);
3715	else
3716	{
3717	RTLogPrintf("%VGp %04x:%VGp: %s\n", uCode, cs, eip, szBuf);
3718	cbInstr = 1;
3719	}
3720
3721	/* next */
3722	if (cb <= cbInstr)
3723	break;
3724	cb -= cbInstr;
3725	uCode += cbInstr;
3726	eip += cbInstr;
3727	}
3728	}
3729	NOREF(phFileIgnored);
3730	}
3731
3732
3733	/**
3734	* Looks up a guest symbol.
3735	*
3736	* @returns Pointer to symbol name. This is a static buffer.
3737	* @param orig_addr The address in question.
3738	*/
3739	const char *lookup_symbol(target_ulong orig_addr)
3740	{
3741	RTGCINTPTR off = 0;
3742	DBGFSYMBOL Sym;
3743	PVM pVM = cpu_single_env->pVM;
3744	int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3745	if (VBOX_SUCCESS(rc))
3746	{
3747	static char szSym[sizeof(Sym.szName) + 48];
3748	if (!off)
3749	RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3750	else if (off > 0)
3751	RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3752	else
3753	RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3754	return szSym;
3755	}
3756	return "<N/A>";
3757	}
3758
3759
3760	#undef LOG_GROUP
3761	#define LOG_GROUP LOG_GROUP_REM
3762
3763
3764	/* -+- FF notifications -+- */
3765
3766
3767	/**
3768	* Notification about a pending interrupt.
3769	*
3770	* @param pVM VM Handle.
3771	* @param u8Interrupt Interrupt
3772	* @thread The emulation thread.
3773	*/
3774	REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3775	{
3776	Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3777	pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3778	}
3779
3780	/**
3781	* Notification about a pending interrupt.
3782	*
3783	* @returns Pending interrupt or REM_NO_PENDING_IRQ
3784	* @param pVM VM Handle.
3785	* @thread The emulation thread.
3786	*/
3787	REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3788	{
3789	return pVM->rem.s.u32PendingInterrupt;
3790	}
3791
3792	/**
3793	* Notification about the interrupt FF being set.
3794	*
3795	* @param pVM VM Handle.
3796	* @thread The emulation thread.
3797	*/
3798	REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3799	{
3800	LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3801	(pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3802	if (pVM->rem.s.fInREM)
3803	{
3804	if (VM_IS_EMT(pVM))
3805	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3806	else
3807	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3808	}
3809	}
3810
3811
3812	/**
3813	* Notification about the interrupt FF being set.
3814	*
3815	* @param pVM VM Handle.
3816	* @thread The emulation thread.
3817	*/
3818	REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3819	{
3820	LogFlow(("REMR3NotifyInterruptClear:\n"));
3821	VM_ASSERT_EMT(pVM);
3822	if (pVM->rem.s.fInREM)
3823	cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3824	}
3825
3826
3827	/**
3828	* Notification about pending timer(s).
3829	*
3830	* @param pVM VM Handle.
3831	* @thread Any.
3832	*/
3833	REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3834	{
3835	#ifndef DEBUG_bird
3836	LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3837	#endif
3838	if (pVM->rem.s.fInREM)
3839	{
3840	if (VM_IS_EMT(pVM))
3841	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3842	else
3843	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3844	}
3845	}
3846
3847
3848	/**
3849	* Notification about pending DMA transfers.
3850	*
3851	* @param pVM VM Handle.
3852	* @thread Any.
3853	*/
3854	REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3855	{
3856	LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3857	if (pVM->rem.s.fInREM)
3858	{
3859	if (VM_IS_EMT(pVM))
3860	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3861	else
3862	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3863	}
3864	}
3865
3866
3867	/**
3868	* Notification about pending timer(s).
3869	*
3870	* @param pVM VM Handle.
3871	* @thread Any.
3872	*/
3873	REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3874	{
3875	LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3876	if (pVM->rem.s.fInREM)
3877	{
3878	if (VM_IS_EMT(pVM))
3879	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3880	else
3881	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3882	}
3883	}
3884
3885
3886	/**
3887	* Notification about pending FF set by an external thread.
3888	*
3889	* @param pVM VM handle.
3890	* @thread Any.
3891	*/
3892	REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3893	{
3894	LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3895	if (pVM->rem.s.fInREM)
3896	{
3897	if (VM_IS_EMT(pVM))
3898	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3899	else
3900	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3901	}
3902	}
3903
3904
3905	#ifdef VBOX_WITH_STATISTICS
3906	void remR3ProfileStart(int statcode)
3907	{
3908	STAMPROFILEADV *pStat;
3909	switch(statcode)
3910	{
3911	case STATS_EMULATE_SINGLE_INSTR:
3912	pStat = &gStatExecuteSingleInstr;
3913	break;
3914	case STATS_QEMU_COMPILATION:
3915	pStat = &gStatCompilationQEmu;
3916	break;
3917	case STATS_QEMU_RUN_EMULATED_CODE:
3918	pStat = &gStatRunCodeQEmu;
3919	break;
3920	case STATS_QEMU_TOTAL:
3921	pStat = &gStatTotalTimeQEmu;
3922	break;
3923	case STATS_QEMU_RUN_TIMERS:
3924	pStat = &gStatTimers;
3925	break;
3926	case STATS_TLB_LOOKUP:
3927	pStat= &gStatTBLookup;
3928	break;
3929	case STATS_IRQ_HANDLING:
3930	pStat= &gStatIRQ;
3931	break;
3932	case STATS_RAW_CHECK:
3933	pStat = &gStatRawCheck;
3934	break;
3935
3936	default:
3937	AssertMsgFailed(("unknown stat %d\n", statcode));
3938	return;
3939	}
3940	STAM_PROFILE_ADV_START(pStat, a);
3941	}
3942
3943
3944	void remR3ProfileStop(int statcode)
3945	{
3946	STAMPROFILEADV *pStat;
3947	switch(statcode)
3948	{
3949	case STATS_EMULATE_SINGLE_INSTR:
3950	pStat = &gStatExecuteSingleInstr;
3951	break;
3952	case STATS_QEMU_COMPILATION:
3953	pStat = &gStatCompilationQEmu;
3954	break;
3955	case STATS_QEMU_RUN_EMULATED_CODE:
3956	pStat = &gStatRunCodeQEmu;
3957	break;
3958	case STATS_QEMU_TOTAL:
3959	pStat = &gStatTotalTimeQEmu;
3960	break;
3961	case STATS_QEMU_RUN_TIMERS:
3962	pStat = &gStatTimers;
3963	break;
3964	case STATS_TLB_LOOKUP:
3965	pStat= &gStatTBLookup;
3966	break;
3967	case STATS_IRQ_HANDLING:
3968	pStat= &gStatIRQ;
3969	break;
3970	case STATS_RAW_CHECK:
3971	pStat = &gStatRawCheck;
3972	break;
3973	default:
3974	AssertMsgFailed(("unknown stat %d\n", statcode));
3975	return;
3976	}
3977	STAM_PROFILE_ADV_STOP(pStat, a);
3978	}
3979	#endif
3980
3981	/**
3982	* Raise an RC, force rem exit.
3983	*
3984	* @param pVM VM handle.
3985	* @param rc The rc.
3986	*/
3987	void remR3RaiseRC(PVM pVM, int rc)
3988	{
3989	Log(("remR3RaiseRC: rc=%Vrc\n", rc));
3990	Assert(pVM->rem.s.fInREM);
3991	VM_ASSERT_EMT(pVM);
3992	pVM->rem.s.rc = rc;
3993	cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
3994	}
3995
3996
3997	/* -+- timers -+- */
3998
3999	uint64_t cpu_get_tsc(CPUX86State *env)
4000	{
4001	return TMCpuTickGet(env->pVM);
4002	}
4003
4004
4005	/* -+- interrupts -+- */
4006
4007	void cpu_set_ferr(CPUX86State *env)
4008	{
4009	int rc = PDMIsaSetIrq(env->pVM, 13, 1);
4010	LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
4011	}
4012
4013	int cpu_get_pic_interrupt(CPUState *env)
4014	{
4015	uint8_t u8Interrupt;
4016	int rc;
4017
4018	/* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
4019	* In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
4020	* with the (a)pic.
4021	*/
4022	/** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
4023	/** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
4024	* if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4025	* remove this kludge. */
4026	if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4027	{
4028	rc = VINF_SUCCESS;
4029	Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
4030	u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4031	env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4032	}
4033	else
4034	rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
4035
4036	LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Vrc\n", u8Interrupt, rc));
4037	if (VBOX_SUCCESS(rc))
4038	{
4039	if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
4040	env->interrupt_request \|= CPU_INTERRUPT_HARD;
4041	return u8Interrupt;
4042	}
4043	return -1;
4044	}
4045
4046
4047	/* -+- local apic -+- */
4048
4049	void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4050	{
4051	int rc = PDMApicSetBase(env->pVM, val);
4052	LogFlow(("cpu_set_apic_base: val=%#llx rc=%Vrc\n", val, rc)); NOREF(rc);
4053	}
4054
4055	uint64_t cpu_get_apic_base(CPUX86State *env)
4056	{
4057	uint64_t u64;
4058	int rc = PDMApicGetBase(env->pVM, &u64);
4059	if (VBOX_SUCCESS(rc))
4060	{
4061	LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4062	return u64;
4063	}
4064	LogFlow(("cpu_get_apic_base: returns 0 (rc=%Vrc)\n", rc));
4065	return 0;
4066	}
4067
4068	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4069	{
4070	int rc = PDMApicSetTPR(env->pVM, val);
4071	LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Vrc\n", val, rc)); NOREF(rc);
4072	}
4073
4074	uint8_t cpu_get_apic_tpr(CPUX86State *env)
4075	{
4076	uint8_t u8;
4077	int rc = PDMApicGetTPR(env->pVM, &u8);
4078	if (VBOX_SUCCESS(rc))
4079	{
4080	LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4081	return u8;
4082	}
4083	LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Vrc)\n", rc));
4084	return 0;
4085	}
4086
4087
4088	/* -+- I/O Ports -+- */
4089
4090	#undef LOG_GROUP
4091	#define LOG_GROUP LOG_GROUP_REM_IOPORT
4092
4093	void cpu_outb(CPUState *env, int addr, int val)
4094	{
4095	if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4096	Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4097
4098	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4099	if (rc == VINF_SUCCESS)
4100	return;
4101	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4102	{
4103	Log(("cpu_outb: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4104	remR3RaiseRC(env->pVM, rc);
4105	return;
4106	}
4107	remAbort(rc, __FUNCTION__);
4108	}
4109
4110	void cpu_outw(CPUState *env, int addr, int val)
4111	{
4112	//Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4113	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4114	if (rc == VINF_SUCCESS)
4115	return;
4116	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4117	{
4118	Log(("cpu_outw: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4119	remR3RaiseRC(env->pVM, rc);
4120	return;
4121	}
4122	remAbort(rc, __FUNCTION__);
4123	}
4124
4125	void cpu_outl(CPUState *env, int addr, int val)
4126	{
4127	Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4128	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4129	if (rc == VINF_SUCCESS)
4130	return;
4131	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4132	{
4133	Log(("cpu_outl: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4134	remR3RaiseRC(env->pVM, rc);
4135	return;
4136	}
4137	remAbort(rc, __FUNCTION__);
4138	}
4139
4140	int cpu_inb(CPUState *env, int addr)
4141	{
4142	uint32_t u32 = 0;
4143	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4144	if (rc == VINF_SUCCESS)
4145	{
4146	if (/addr != 0x61 && /addr != 0x71)
4147	Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4148	return (int)u32;
4149	}
4150	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4151	{
4152	Log(("cpu_inb: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4153	remR3RaiseRC(env->pVM, rc);
4154	return (int)u32;
4155	}
4156	remAbort(rc, __FUNCTION__);
4157	return 0xff;
4158	}
4159
4160	int cpu_inw(CPUState *env, int addr)
4161	{
4162	uint32_t u32 = 0;
4163	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4164	if (rc == VINF_SUCCESS)
4165	{
4166	Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4167	return (int)u32;
4168	}
4169	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4170	{
4171	Log(("cpu_inw: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4172	remR3RaiseRC(env->pVM, rc);
4173	return (int)u32;
4174	}
4175	remAbort(rc, __FUNCTION__);
4176	return 0xffff;
4177	}
4178
4179	int cpu_inl(CPUState *env, int addr)
4180	{
4181	uint32_t u32 = 0;
4182	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4183	if (rc == VINF_SUCCESS)
4184	{
4185	//if (addr==0x01f0 && u32 == 0x6b6d)
4186	// loglevel = ~0;
4187	Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4188	return (int)u32;
4189	}
4190	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4191	{
4192	Log(("cpu_inl: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4193	remR3RaiseRC(env->pVM, rc);
4194	return (int)u32;
4195	}
4196	remAbort(rc, __FUNCTION__);
4197	return 0xffffffff;
4198	}
4199
4200	#undef LOG_GROUP
4201	#define LOG_GROUP LOG_GROUP_REM
4202
4203
4204	/* -+- helpers and misc other interfaces -+- */
4205
4206	/**
4207	* Perform the CPUID instruction.
4208	*
4209	* ASMCpuId cannot be invoked from some source files where this is used because of global
4210	* register allocations.
4211	*
4212	* @param env Pointer to the recompiler CPU structure.
4213	* @param uOperator CPUID operation (eax).
4214	* @param pvEAX Where to store eax.
4215	* @param pvEBX Where to store ebx.
4216	* @param pvECX Where to store ecx.
4217	* @param pvEDX Where to store edx.
4218	*/
4219	void remR3CpuId(CPUState env, unsigned uOperator, void pvEAX, void pvEBX, void pvECX, void *pvEDX)
4220	{
4221	CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t )pvEAX, (uint32_t )pvEBX, (uint32_t )pvECX, (uint32_t )pvEDX);
4222	}
4223
4224
4225	#if 0 /* not used */
4226	/**
4227	* Interface for qemu hardware to report back fatal errors.
4228	*/
4229	void hw_error(const char *pszFormat, ...)
4230	{
4231	/*
4232	* Bitch about it.
4233	*/
4234	/** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4235	* this in my Odin32 tree at home! */
4236	va_list args;
4237	va_start(args, pszFormat);
4238	RTLogPrintf("fatal error in virtual hardware:");
4239	RTLogPrintfV(pszFormat, args);
4240	va_end(args);
4241	AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4242
4243	/*
4244	* If we're in REM context we'll sync back the state before 'jumping' to
4245	* the EMs failure handling.
4246	*/
4247	PVM pVM = cpu_single_env->pVM;
4248	if (pVM->rem.s.fInREM)
4249	REMR3StateBack(pVM);
4250	EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4251	AssertMsgFailed(("EMR3FatalError returned!\n"));
4252	}
4253	#endif
4254
4255	/**
4256	* Interface for the qemu cpu to report unhandled situation
4257	* raising a fatal VM error.
4258	*/
4259	void cpu_abort(CPUState env, const char pszFormat, ...)
4260	{
4261	/*
4262	* Bitch about it.
4263	*/
4264	RTLogFlags(NULL, "nodisabled nobuffered");
4265	va_list args;
4266	va_start(args, pszFormat);
4267	RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4268	va_end(args);
4269	va_start(args, pszFormat);
4270	AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4271	va_end(args);
4272
4273	/*
4274	* If we're in REM context we'll sync back the state before 'jumping' to
4275	* the EMs failure handling.
4276	*/
4277	PVM pVM = cpu_single_env->pVM;
4278	if (pVM->rem.s.fInREM)
4279	REMR3StateBack(pVM);
4280	EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4281	AssertMsgFailed(("EMR3FatalError returned!\n"));
4282	}
4283
4284
4285	/**
4286	* Aborts the VM.
4287	*
4288	* @param rc VBox error code.
4289	* @param pszTip Hint about why/when this happend.
4290	*/
4291	static void remAbort(int rc, const char *pszTip)
4292	{
4293	/*
4294	* Bitch about it.
4295	*/
4296	RTLogPrintf("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip);
4297	AssertReleaseMsgFailed(("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip));
4298
4299	/*
4300	* Jump back to where we entered the recompiler.
4301	*/
4302	PVM pVM = cpu_single_env->pVM;
4303	if (pVM->rem.s.fInREM)
4304	REMR3StateBack(pVM);
4305	EMR3FatalError(pVM, rc);
4306	AssertMsgFailed(("EMR3FatalError returned!\n"));
4307	}
4308
4309
4310	/**
4311	* Dumps a linux system call.
4312	* @param pVM VM handle.
4313	*/
4314	void remR3DumpLnxSyscall(PVM pVM)
4315	{
4316	static const char *apsz[] =
4317	{
4318	"sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4319	"sys_exit",
4320	"sys_fork",
4321	"sys_read",
4322	"sys_write",
4323	"sys_open", /* 5 */
4324	"sys_close",
4325	"sys_waitpid",
4326	"sys_creat",
4327	"sys_link",
4328	"sys_unlink", /* 10 */
4329	"sys_execve",
4330	"sys_chdir",
4331	"sys_time",
4332	"sys_mknod",
4333	"sys_chmod", /* 15 */
4334	"sys_lchown16",
4335	"sys_ni_syscall", /* old break syscall holder */
4336	"sys_stat",
4337	"sys_lseek",
4338	"sys_getpid", /* 20 */
4339	"sys_mount",
4340	"sys_oldumount",
4341	"sys_setuid16",
4342	"sys_getuid16",
4343	"sys_stime", /* 25 */
4344	"sys_ptrace",
4345	"sys_alarm",
4346	"sys_fstat",
4347	"sys_pause",
4348	"sys_utime", /* 30 */
4349	"sys_ni_syscall", /* old stty syscall holder */
4350	"sys_ni_syscall", /* old gtty syscall holder */
4351	"sys_access",
4352	"sys_nice",
4353	"sys_ni_syscall", /* 35 - old ftime syscall holder */
4354	"sys_sync",
4355	"sys_kill",
4356	"sys_rename",
4357	"sys_mkdir",
4358	"sys_rmdir", /* 40 */
4359	"sys_dup",
4360	"sys_pipe",
4361	"sys_times",
4362	"sys_ni_syscall", /* old prof syscall holder */
4363	"sys_brk", /* 45 */
4364	"sys_setgid16",
4365	"sys_getgid16",
4366	"sys_signal",
4367	"sys_geteuid16",
4368	"sys_getegid16", /* 50 */
4369	"sys_acct",
4370	"sys_umount", /* recycled never used phys() */
4371	"sys_ni_syscall", /* old lock syscall holder */
4372	"sys_ioctl",
4373	"sys_fcntl", /* 55 */
4374	"sys_ni_syscall", /* old mpx syscall holder */
4375	"sys_setpgid",
4376	"sys_ni_syscall", /* old ulimit syscall holder */
4377	"sys_olduname",
4378	"sys_umask", /* 60 */
4379	"sys_chroot",
4380	"sys_ustat",
4381	"sys_dup2",
4382	"sys_getppid",
4383	"sys_getpgrp", /* 65 */
4384	"sys_setsid",
4385	"sys_sigaction",
4386	"sys_sgetmask",
4387	"sys_ssetmask",
4388	"sys_setreuid16", /* 70 */
4389	"sys_setregid16",
4390	"sys_sigsuspend",
4391	"sys_sigpending",
4392	"sys_sethostname",
4393	"sys_setrlimit", /* 75 */
4394	"sys_old_getrlimit",
4395	"sys_getrusage",
4396	"sys_gettimeofday",
4397	"sys_settimeofday",
4398	"sys_getgroups16", /* 80 */
4399	"sys_setgroups16",
4400	"old_select",
4401	"sys_symlink",
4402	"sys_lstat",
4403	"sys_readlink", /* 85 */
4404	"sys_uselib",
4405	"sys_swapon",
4406	"sys_reboot",
4407	"old_readdir",
4408	"old_mmap", /* 90 */
4409	"sys_munmap",
4410	"sys_truncate",
4411	"sys_ftruncate",
4412	"sys_fchmod",
4413	"sys_fchown16", /* 95 */
4414	"sys_getpriority",
4415	"sys_setpriority",
4416	"sys_ni_syscall", /* old profil syscall holder */
4417	"sys_statfs",
4418	"sys_fstatfs", /* 100 */
4419	"sys_ioperm",
4420	"sys_socketcall",
4421	"sys_syslog",
4422	"sys_setitimer",
4423	"sys_getitimer", /* 105 */
4424	"sys_newstat",
4425	"sys_newlstat",
4426	"sys_newfstat",
4427	"sys_uname",
4428	"sys_iopl", /* 110 */
4429	"sys_vhangup",
4430	"sys_ni_syscall", /* old "idle" system call */
4431	"sys_vm86old",
4432	"sys_wait4",
4433	"sys_swapoff", /* 115 */
4434	"sys_sysinfo",
4435	"sys_ipc",
4436	"sys_fsync",
4437	"sys_sigreturn",
4438	"sys_clone", /* 120 */
4439	"sys_setdomainname",
4440	"sys_newuname",
4441	"sys_modify_ldt",
4442	"sys_adjtimex",
4443	"sys_mprotect", /* 125 */
4444	"sys_sigprocmask",
4445	"sys_ni_syscall", /* old "create_module" */
4446	"sys_init_module",
4447	"sys_delete_module",
4448	"sys_ni_syscall", /* 130: old "get_kernel_syms" */
4449	"sys_quotactl",
4450	"sys_getpgid",
4451	"sys_fchdir",
4452	"sys_bdflush",
4453	"sys_sysfs", /* 135 */
4454	"sys_personality",
4455	"sys_ni_syscall", /* reserved for afs_syscall */
4456	"sys_setfsuid16",
4457	"sys_setfsgid16",
4458	"sys_llseek", /* 140 */
4459	"sys_getdents",
4460	"sys_select",
4461	"sys_flock",
4462	"sys_msync",
4463	"sys_readv", /* 145 */
4464	"sys_writev",
4465	"sys_getsid",
4466	"sys_fdatasync",
4467	"sys_sysctl",
4468	"sys_mlock", /* 150 */
4469	"sys_munlock",
4470	"sys_mlockall",
4471	"sys_munlockall",
4472	"sys_sched_setparam",
4473	"sys_sched_getparam", /* 155 */
4474	"sys_sched_setscheduler",
4475	"sys_sched_getscheduler",
4476	"sys_sched_yield",
4477	"sys_sched_get_priority_max",
4478	"sys_sched_get_priority_min", /* 160 */
4479	"sys_sched_rr_get_interval",
4480	"sys_nanosleep",
4481	"sys_mremap",
4482	"sys_setresuid16",
4483	"sys_getresuid16", /* 165 */
4484	"sys_vm86",
4485	"sys_ni_syscall", /* Old sys_query_module */
4486	"sys_poll",
4487	"sys_nfsservctl",
4488	"sys_setresgid16", /* 170 */
4489	"sys_getresgid16",
4490	"sys_prctl",
4491	"sys_rt_sigreturn",
4492	"sys_rt_sigaction",
4493	"sys_rt_sigprocmask", /* 175 */
4494	"sys_rt_sigpending",
4495	"sys_rt_sigtimedwait",
4496	"sys_rt_sigqueueinfo",
4497	"sys_rt_sigsuspend",
4498	"sys_pread64", /* 180 */
4499	"sys_pwrite64",
4500	"sys_chown16",
4501	"sys_getcwd",
4502	"sys_capget",
4503	"sys_capset", /* 185 */
4504	"sys_sigaltstack",
4505	"sys_sendfile",
4506	"sys_ni_syscall", /* reserved for streams1 */
4507	"sys_ni_syscall", /* reserved for streams2 */
4508	"sys_vfork", /* 190 */
4509	"sys_getrlimit",
4510	"sys_mmap2",
4511	"sys_truncate64",
4512	"sys_ftruncate64",
4513	"sys_stat64", /* 195 */
4514	"sys_lstat64",
4515	"sys_fstat64",
4516	"sys_lchown",
4517	"sys_getuid",
4518	"sys_getgid", /* 200 */
4519	"sys_geteuid",
4520	"sys_getegid",
4521	"sys_setreuid",
4522	"sys_setregid",
4523	"sys_getgroups", /* 205 */
4524	"sys_setgroups",
4525	"sys_fchown",
4526	"sys_setresuid",
4527	"sys_getresuid",
4528	"sys_setresgid", /* 210 */
4529	"sys_getresgid",
4530	"sys_chown",
4531	"sys_setuid",
4532	"sys_setgid",
4533	"sys_setfsuid", /* 215 */
4534	"sys_setfsgid",
4535	"sys_pivot_root",
4536	"sys_mincore",
4537	"sys_madvise",
4538	"sys_getdents64", /* 220 */
4539	"sys_fcntl64",
4540	"sys_ni_syscall", /* reserved for TUX */
4541	"sys_ni_syscall",
4542	"sys_gettid",
4543	"sys_readahead", /* 225 */
4544	"sys_setxattr",
4545	"sys_lsetxattr",
4546	"sys_fsetxattr",
4547	"sys_getxattr",
4548	"sys_lgetxattr", /* 230 */
4549	"sys_fgetxattr",
4550	"sys_listxattr",
4551	"sys_llistxattr",
4552	"sys_flistxattr",
4553	"sys_removexattr", /* 235 */
4554	"sys_lremovexattr",
4555	"sys_fremovexattr",
4556	"sys_tkill",
4557	"sys_sendfile64",
4558	"sys_futex", /* 240 */
4559	"sys_sched_setaffinity",
4560	"sys_sched_getaffinity",
4561	"sys_set_thread_area",
4562	"sys_get_thread_area",
4563	"sys_io_setup", /* 245 */
4564	"sys_io_destroy",
4565	"sys_io_getevents",
4566	"sys_io_submit",
4567	"sys_io_cancel",
4568	"sys_fadvise64", /* 250 */
4569	"sys_ni_syscall",
4570	"sys_exit_group",
4571	"sys_lookup_dcookie",
4572	"sys_epoll_create",
4573	"sys_epoll_ctl", /* 255 */
4574	"sys_epoll_wait",
4575	"sys_remap_file_pages",
4576	"sys_set_tid_address",
4577	"sys_timer_create",
4578	"sys_timer_settime", /* 260 */
4579	"sys_timer_gettime",
4580	"sys_timer_getoverrun",
4581	"sys_timer_delete",
4582	"sys_clock_settime",
4583	"sys_clock_gettime", /* 265 */
4584	"sys_clock_getres",
4585	"sys_clock_nanosleep",
4586	"sys_statfs64",
4587	"sys_fstatfs64",
4588	"sys_tgkill", /* 270 */
4589	"sys_utimes",
4590	"sys_fadvise64_64",
4591	"sys_ni_syscall" /* sys_vserver */
4592	};
4593
4594	uint32_t uEAX = CPUMGetGuestEAX(pVM);
4595	switch (uEAX)
4596	{
4597	default:
4598	if (uEAX < ELEMENTS(apsz))
4599	Log(("REM: linux syscall %3d: %s (eip=%VGv ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4600	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4601	CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4602	else
4603	Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4604	break;
4605
4606	}
4607	}
4608
4609
4610	/**
4611	* Dumps an OpenBSD system call.
4612	* @param pVM VM handle.
4613	*/
4614	void remR3DumpOBsdSyscall(PVM pVM)
4615	{
4616	static const char *apsz[] =
4617	{
4618	"SYS_syscall", //0
4619	"SYS_exit", //1
4620	"SYS_fork", //2
4621	"SYS_read", //3
4622	"SYS_write", //4
4623	"SYS_open", //5
4624	"SYS_close", //6
4625	"SYS_wait4", //7
4626	"SYS_8",
4627	"SYS_link", //9
4628	"SYS_unlink", //10
4629	"SYS_11",
4630	"SYS_chdir", //12
4631	"SYS_fchdir", //13
4632	"SYS_mknod", //14
4633	"SYS_chmod", //15
4634	"SYS_chown", //16
4635	"SYS_break", //17
4636	"SYS_18",
4637	"SYS_19",
4638	"SYS_getpid", //20
4639	"SYS_mount", //21
4640	"SYS_unmount", //22
4641	"SYS_setuid", //23
4642	"SYS_getuid", //24
4643	"SYS_geteuid", //25
4644	"SYS_ptrace", //26
4645	"SYS_recvmsg", //27
4646	"SYS_sendmsg", //28
4647	"SYS_recvfrom", //29
4648	"SYS_accept", //30
4649	"SYS_getpeername", //31
4650	"SYS_getsockname", //32
4651	"SYS_access", //33
4652	"SYS_chflags", //34
4653	"SYS_fchflags", //35
4654	"SYS_sync", //36
4655	"SYS_kill", //37
4656	"SYS_38",
4657	"SYS_getppid", //39
4658	"SYS_40",
4659	"SYS_dup", //41
4660	"SYS_opipe", //42
4661	"SYS_getegid", //43
4662	"SYS_profil", //44
4663	"SYS_ktrace", //45
4664	"SYS_sigaction", //46
4665	"SYS_getgid", //47
4666	"SYS_sigprocmask", //48
4667	"SYS_getlogin", //49
4668	"SYS_setlogin", //50
4669	"SYS_acct", //51
4670	"SYS_sigpending", //52
4671	"SYS_osigaltstack", //53
4672	"SYS_ioctl", //54
4673	"SYS_reboot", //55
4674	"SYS_revoke", //56
4675	"SYS_symlink", //57
4676	"SYS_readlink", //58
4677	"SYS_execve", //59
4678	"SYS_umask", //60
4679	"SYS_chroot", //61
4680	"SYS_62",
4681	"SYS_63",
4682	"SYS_64",
4683	"SYS_65",
4684	"SYS_vfork", //66
4685	"SYS_67",
4686	"SYS_68",
4687	"SYS_sbrk", //69
4688	"SYS_sstk", //70
4689	"SYS_61",
4690	"SYS_vadvise", //72
4691	"SYS_munmap", //73
4692	"SYS_mprotect", //74
4693	"SYS_madvise", //75
4694	"SYS_76",
4695	"SYS_77",
4696	"SYS_mincore", //78
4697	"SYS_getgroups", //79
4698	"SYS_setgroups", //80
4699	"SYS_getpgrp", //81
4700	"SYS_setpgid", //82
4701	"SYS_setitimer", //83
4702	"SYS_84",
4703	"SYS_85",
4704	"SYS_getitimer", //86
4705	"SYS_87",
4706	"SYS_88",
4707	"SYS_89",
4708	"SYS_dup2", //90
4709	"SYS_91",
4710	"SYS_fcntl", //92
4711	"SYS_select", //93
4712	"SYS_94",
4713	"SYS_fsync", //95
4714	"SYS_setpriority", //96
4715	"SYS_socket", //97
4716	"SYS_connect", //98
4717	"SYS_99",
4718	"SYS_getpriority", //100
4719	"SYS_101",
4720	"SYS_102",
4721	"SYS_sigreturn", //103
4722	"SYS_bind", //104
4723	"SYS_setsockopt", //105
4724	"SYS_listen", //106
4725	"SYS_107",
4726	"SYS_108",
4727	"SYS_109",
4728	"SYS_110",
4729	"SYS_sigsuspend", //111
4730	"SYS_112",
4731	"SYS_113",
4732	"SYS_114",
4733	"SYS_115",
4734	"SYS_gettimeofday", //116
4735	"SYS_getrusage", //117
4736	"SYS_getsockopt", //118
4737	"SYS_119",
4738	"SYS_readv", //120
4739	"SYS_writev", //121
4740	"SYS_settimeofday", //122
4741	"SYS_fchown", //123
4742	"SYS_fchmod", //124
4743	"SYS_125",
4744	"SYS_setreuid", //126
4745	"SYS_setregid", //127
4746	"SYS_rename", //128
4747	"SYS_129",
4748	"SYS_130",
4749	"SYS_flock", //131
4750	"SYS_mkfifo", //132
4751	"SYS_sendto", //133
4752	"SYS_shutdown", //134
4753	"SYS_socketpair", //135
4754	"SYS_mkdir", //136
4755	"SYS_rmdir", //137
4756	"SYS_utimes", //138
4757	"SYS_139",
4758	"SYS_adjtime", //140
4759	"SYS_141",
4760	"SYS_142",
4761	"SYS_143",
4762	"SYS_144",
4763	"SYS_145",
4764	"SYS_146",
4765	"SYS_setsid", //147
4766	"SYS_quotactl", //148
4767	"SYS_149",
4768	"SYS_150",
4769	"SYS_151",
4770	"SYS_152",
4771	"SYS_153",
4772	"SYS_154",
4773	"SYS_nfssvc", //155
4774	"SYS_156",
4775	"SYS_157",
4776	"SYS_158",
4777	"SYS_159",
4778	"SYS_160",
4779	"SYS_getfh", //161
4780	"SYS_162",
4781	"SYS_163",
4782	"SYS_164",
4783	"SYS_sysarch", //165
4784	"SYS_166",
4785	"SYS_167",
4786	"SYS_168",
4787	"SYS_169",
4788	"SYS_170",
4789	"SYS_171",
4790	"SYS_172",
4791	"SYS_pread", //173
4792	"SYS_pwrite", //174
4793	"SYS_175",
4794	"SYS_176",
4795	"SYS_177",
4796	"SYS_178",
4797	"SYS_179",
4798	"SYS_180",
4799	"SYS_setgid", //181
4800	"SYS_setegid", //182
4801	"SYS_seteuid", //183
4802	"SYS_lfs_bmapv", //184
4803	"SYS_lfs_markv", //185
4804	"SYS_lfs_segclean", //186
4805	"SYS_lfs_segwait", //187
4806	"SYS_188",
4807	"SYS_189",
4808	"SYS_190",
4809	"SYS_pathconf", //191
4810	"SYS_fpathconf", //192
4811	"SYS_swapctl", //193
4812	"SYS_getrlimit", //194
4813	"SYS_setrlimit", //195
4814	"SYS_getdirentries", //196
4815	"SYS_mmap", //197
4816	"SYS___syscall", //198
4817	"SYS_lseek", //199
4818	"SYS_truncate", //200
4819	"SYS_ftruncate", //201
4820	"SYS___sysctl", //202
4821	"SYS_mlock", //203
4822	"SYS_munlock", //204
4823	"SYS_205",
4824	"SYS_futimes", //206
4825	"SYS_getpgid", //207
4826	"SYS_xfspioctl", //208
4827	"SYS_209",
4828	"SYS_210",
4829	"SYS_211",
4830	"SYS_212",
4831	"SYS_213",
4832	"SYS_214",
4833	"SYS_215",
4834	"SYS_216",
4835	"SYS_217",
4836	"SYS_218",
4837	"SYS_219",
4838	"SYS_220",
4839	"SYS_semget", //221
4840	"SYS_222",
4841	"SYS_223",
4842	"SYS_224",
4843	"SYS_msgget", //225
4844	"SYS_msgsnd", //226
4845	"SYS_msgrcv", //227
4846	"SYS_shmat", //228
4847	"SYS_229",
4848	"SYS_shmdt", //230
4849	"SYS_231",
4850	"SYS_clock_gettime", //232
4851	"SYS_clock_settime", //233
4852	"SYS_clock_getres", //234
4853	"SYS_235",
4854	"SYS_236",
4855	"SYS_237",
4856	"SYS_238",
4857	"SYS_239",
4858	"SYS_nanosleep", //240
4859	"SYS_241",
4860	"SYS_242",
4861	"SYS_243",
4862	"SYS_244",
4863	"SYS_245",
4864	"SYS_246",
4865	"SYS_247",
4866	"SYS_248",
4867	"SYS_249",
4868	"SYS_minherit", //250
4869	"SYS_rfork", //251
4870	"SYS_poll", //252
4871	"SYS_issetugid", //253
4872	"SYS_lchown", //254
4873	"SYS_getsid", //255
4874	"SYS_msync", //256
4875	"SYS_257",
4876	"SYS_258",
4877	"SYS_259",
4878	"SYS_getfsstat", //260
4879	"SYS_statfs", //261
4880	"SYS_fstatfs", //262
4881	"SYS_pipe", //263
4882	"SYS_fhopen", //264
4883	"SYS_265",
4884	"SYS_fhstatfs", //266
4885	"SYS_preadv", //267
4886	"SYS_pwritev", //268
4887	"SYS_kqueue", //269
4888	"SYS_kevent", //270
4889	"SYS_mlockall", //271
4890	"SYS_munlockall", //272
4891	"SYS_getpeereid", //273
4892	"SYS_274",
4893	"SYS_275",
4894	"SYS_276",
4895	"SYS_277",
4896	"SYS_278",
4897	"SYS_279",
4898	"SYS_280",
4899	"SYS_getresuid", //281
4900	"SYS_setresuid", //282
4901	"SYS_getresgid", //283
4902	"SYS_setresgid", //284
4903	"SYS_285",
4904	"SYS_mquery", //286
4905	"SYS_closefrom", //287
4906	"SYS_sigaltstack", //288
4907	"SYS_shmget", //289
4908	"SYS_semop", //290
4909	"SYS_stat", //291
4910	"SYS_fstat", //292
4911	"SYS_lstat", //293
4912	"SYS_fhstat", //294
4913	"SYS___semctl", //295
4914	"SYS_shmctl", //296
4915	"SYS_msgctl", //297
4916	"SYS_MAXSYSCALL", //298
4917	//299
4918	//300
4919	};
4920	uint32_t uEAX;
4921	#ifndef DEBUG_bird
4922	if (!LogIsEnabled())
4923	return;
4924	#endif
4925	uEAX = CPUMGetGuestEAX(pVM);
4926	switch (uEAX)
4927	{
4928	default:
4929	if (uEAX < ELEMENTS(apsz))
4930	{
4931	uint32_t au32Args[8] = {0};
4932	PGMPhysReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4933	RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4934	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4935	au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4936	}
4937	else
4938	RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4939	break;
4940	}
4941	}

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source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 843

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