VirtualBox

source: vbox/trunk/src/recompiler/cpu-all.h@ 35555

Last change on this file since 35555 was 35346, checked in by vboxsync, 14 years ago

VMM reorg: Moving the public include files from include/VBox to include/VBox/vmm.
  • Property svn:eol-style set to native
File size: 36.3 KB
Line 
1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29
30#ifndef CPU_ALL_H
31#define CPU_ALL_H
32
33#ifdef VBOX
34# ifndef LOG_GROUP
35# define LOG_GROUP LOG_GROUP_REM
36# endif
37# include <VBox/log.h>
38# include <VBox/vmm/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
39#endif
40
41#if defined(__arm__) || defined(__sparc__)
42#define WORDS_ALIGNED
43#endif
44
45/* some important defines:
46 *
47 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
48 * memory accesses.
49 *
50 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
51 * otherwise little endian.
52 *
53 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
54 *
55 * TARGET_WORDS_BIGENDIAN : same for target cpu
56 */
57
58#include "bswap.h"
59
60#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
61#define BSWAP_NEEDED
62#endif
63
64#ifdef BSWAP_NEEDED
65
66static inline uint16_t tswap16(uint16_t s)
67{
68 return bswap16(s);
69}
70
71static inline uint32_t tswap32(uint32_t s)
72{
73 return bswap32(s);
74}
75
76static inline uint64_t tswap64(uint64_t s)
77{
78 return bswap64(s);
79}
80
81static inline void tswap16s(uint16_t *s)
82{
83 *s = bswap16(*s);
84}
85
86static inline void tswap32s(uint32_t *s)
87{
88 *s = bswap32(*s);
89}
90
91static inline void tswap64s(uint64_t *s)
92{
93 *s = bswap64(*s);
94}
95
96#else
97
98#ifndef VBOX
99static inline uint16_t tswap16(uint16_t s)
100#else
101DECLINLINE(uint16_t) tswap16(uint16_t s)
102#endif
103{
104 return s;
105}
106
107#ifndef VBOX
108static inline uint32_t tswap32(uint32_t s)
109#else
110DECLINLINE(uint32_t) tswap32(uint32_t s)
111#endif
112{
113 return s;
114}
115
116#ifndef VBOX
117static inline uint64_t tswap64(uint64_t s)
118#else
119DECLINLINE(uint64_t) tswap64(uint64_t s)
120#endif
121{
122 return s;
123}
124
125#ifndef VBOX
126static inline void tswap16s(uint16_t *s)
127#else
128DECLINLINE(void) tswap16s(uint16_t *s)
129#endif
130{
131}
132
133#ifndef VBOX
134static inline void tswap32s(uint32_t *s)
135#else
136DECLINLINE(void) tswap32s(uint32_t *s)
137#endif
138{
139}
140
141#ifndef VBOX
142static inline void tswap64s(uint64_t *s)
143#else
144DECLINLINE(void) tswap64s(uint64_t *s)
145#endif
146{
147}
148
149#endif
150
151#if TARGET_LONG_SIZE == 4
152#define tswapl(s) tswap32(s)
153#define tswapls(s) tswap32s((uint32_t *)(s))
154#define bswaptls(s) bswap32s(s)
155#else
156#define tswapl(s) tswap64(s)
157#define tswapls(s) tswap64s((uint64_t *)(s))
158#define bswaptls(s) bswap64s(s)
159#endif
160
161typedef union {
162 float32 f;
163 uint32_t l;
164} CPU_FloatU;
165
166/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
167 endian ! */
168typedef union {
169 float64 d;
170#if defined(WORDS_BIGENDIAN) \
171 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
172 struct {
173 uint32_t upper;
174 uint32_t lower;
175 } l;
176#else
177 struct {
178 uint32_t lower;
179 uint32_t upper;
180 } l;
181#endif
182 uint64_t ll;
183} CPU_DoubleU;
184
185#ifdef TARGET_SPARC
186typedef union {
187 float128 q;
188#if defined(WORDS_BIGENDIAN) \
189 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
190 struct {
191 uint32_t upmost;
192 uint32_t upper;
193 uint32_t lower;
194 uint32_t lowest;
195 } l;
196 struct {
197 uint64_t upper;
198 uint64_t lower;
199 } ll;
200#else
201 struct {
202 uint32_t lowest;
203 uint32_t lower;
204 uint32_t upper;
205 uint32_t upmost;
206 } l;
207 struct {
208 uint64_t lower;
209 uint64_t upper;
210 } ll;
211#endif
212} CPU_QuadU;
213#endif
214
215/* CPU memory access without any memory or io remapping */
216
217/*
218 * the generic syntax for the memory accesses is:
219 *
220 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
221 *
222 * store: st{type}{size}{endian}_{access_type}(ptr, val)
223 *
224 * type is:
225 * (empty): integer access
226 * f : float access
227 *
228 * sign is:
229 * (empty): for floats or 32 bit size
230 * u : unsigned
231 * s : signed
232 *
233 * size is:
234 * b: 8 bits
235 * w: 16 bits
236 * l: 32 bits
237 * q: 64 bits
238 *
239 * endian is:
240 * (empty): target cpu endianness or 8 bit access
241 * r : reversed target cpu endianness (not implemented yet)
242 * be : big endian (not implemented yet)
243 * le : little endian (not implemented yet)
244 *
245 * access_type is:
246 * raw : host memory access
247 * user : user mode access using soft MMU
248 * kernel : kernel mode access using soft MMU
249 */
250
251#ifdef VBOX
252void remAbort(int rc, const char *pszTip) __attribute__((__noreturn__));
253
254void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb);
255RTCCUINTREG remR3PhysReadU8(RTGCPHYS SrcGCPhys);
256RTCCINTREG remR3PhysReadS8(RTGCPHYS SrcGCPhys);
257RTCCUINTREG remR3PhysReadU16(RTGCPHYS SrcGCPhys);
258RTCCINTREG remR3PhysReadS16(RTGCPHYS SrcGCPhys);
259RTCCUINTREG remR3PhysReadU32(RTGCPHYS SrcGCPhys);
260RTCCINTREG remR3PhysReadS32(RTGCPHYS SrcGCPhys);
261uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys);
262int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys);
263void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb);
264void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val);
265void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val);
266void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val);
267void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val);
268
269#ifndef REM_PHYS_ADDR_IN_TLB
270void *remR3TlbGCPhys2Ptr(CPUState *env1, target_ulong physAddr, int fWritable);
271#endif
272
273#endif /* VBOX */
274
275#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
276
277DECLINLINE(uint8_t) ldub_p(void *ptr)
278{
279 VBOX_CHECK_ADDR(ptr);
280 return remR3PhysReadU8((uintptr_t)ptr);
281}
282
283DECLINLINE(int8_t) ldsb_p(void *ptr)
284{
285 VBOX_CHECK_ADDR(ptr);
286 return remR3PhysReadS8((uintptr_t)ptr);
287}
288
289DECLINLINE(void) stb_p(void *ptr, int v)
290{
291 VBOX_CHECK_ADDR(ptr);
292 remR3PhysWriteU8((uintptr_t)ptr, v);
293}
294
295DECLINLINE(uint32_t) lduw_le_p(void *ptr)
296{
297 VBOX_CHECK_ADDR(ptr);
298 return remR3PhysReadU16((uintptr_t)ptr);
299}
300
301DECLINLINE(int32_t) ldsw_le_p(void *ptr)
302{
303 VBOX_CHECK_ADDR(ptr);
304 return remR3PhysReadS16((uintptr_t)ptr);
305}
306
307DECLINLINE(void) stw_le_p(void *ptr, int v)
308{
309 VBOX_CHECK_ADDR(ptr);
310 remR3PhysWriteU16((uintptr_t)ptr, v);
311}
312
313DECLINLINE(uint32_t) ldl_le_p(void *ptr)
314{
315 VBOX_CHECK_ADDR(ptr);
316 return remR3PhysReadU32((uintptr_t)ptr);
317}
318
319DECLINLINE(void) stl_le_p(void *ptr, int v)
320{
321 VBOX_CHECK_ADDR(ptr);
322 remR3PhysWriteU32((uintptr_t)ptr, v);
323}
324
325DECLINLINE(void) stq_le_p(void *ptr, uint64_t v)
326{
327 VBOX_CHECK_ADDR(ptr);
328 remR3PhysWriteU64((uintptr_t)ptr, v);
329}
330
331DECLINLINE(uint64_t) ldq_le_p(void *ptr)
332{
333 VBOX_CHECK_ADDR(ptr);
334 return remR3PhysReadU64((uintptr_t)ptr);
335}
336
337#undef VBOX_CHECK_ADDR
338
339/* float access */
340
341DECLINLINE(float32) ldfl_le_p(void *ptr)
342{
343 union {
344 float32 f;
345 uint32_t i;
346 } u;
347 u.i = ldl_le_p(ptr);
348 return u.f;
349}
350
351DECLINLINE(void) stfl_le_p(void *ptr, float32 v)
352{
353 union {
354 float32 f;
355 uint32_t i;
356 } u;
357 u.f = v;
358 stl_le_p(ptr, u.i);
359}
360
361DECLINLINE(float64) ldfq_le_p(void *ptr)
362{
363 CPU_DoubleU u;
364 u.l.lower = ldl_le_p(ptr);
365 u.l.upper = ldl_le_p((uint8_t*)ptr + 4);
366 return u.d;
367}
368
369DECLINLINE(void) stfq_le_p(void *ptr, float64 v)
370{
371 CPU_DoubleU u;
372 u.d = v;
373 stl_le_p(ptr, u.l.lower);
374 stl_le_p((uint8_t*)ptr + 4, u.l.upper);
375}
376
377#else /* !(VBOX && REM_PHYS_ADDR_IN_TLB) */
378
379static inline int ldub_p(void *ptr)
380{
381 return *(uint8_t *)ptr;
382}
383
384static inline int ldsb_p(void *ptr)
385{
386 return *(int8_t *)ptr;
387}
388
389static inline void stb_p(void *ptr, int v)
390{
391 *(uint8_t *)ptr = v;
392}
393
394/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
395 kernel handles unaligned load/stores may give better results, but
396 it is a system wide setting : bad */
397#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
398
399/* conservative code for little endian unaligned accesses */
400static inline int lduw_le_p(void *ptr)
401{
402#ifdef __powerpc__
403 int val;
404 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
405 return val;
406#else
407 uint8_t *p = ptr;
408 return p[0] | (p[1] << 8);
409#endif
410}
411
412static inline int ldsw_le_p(void *ptr)
413{
414#ifdef __powerpc__
415 int val;
416 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
417 return (int16_t)val;
418#else
419 uint8_t *p = ptr;
420 return (int16_t)(p[0] | (p[1] << 8));
421#endif
422}
423
424static inline int ldl_le_p(void *ptr)
425{
426#ifdef __powerpc__
427 int val;
428 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
429 return val;
430#else
431 uint8_t *p = ptr;
432 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
433#endif
434}
435
436static inline uint64_t ldq_le_p(void *ptr)
437{
438 uint8_t *p = ptr;
439 uint32_t v1, v2;
440 v1 = ldl_le_p(p);
441 v2 = ldl_le_p(p + 4);
442 return v1 | ((uint64_t)v2 << 32);
443}
444
445static inline void stw_le_p(void *ptr, int v)
446{
447#ifdef __powerpc__
448 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
449#else
450 uint8_t *p = ptr;
451 p[0] = v;
452 p[1] = v >> 8;
453#endif
454}
455
456static inline void stl_le_p(void *ptr, int v)
457{
458#ifdef __powerpc__
459 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
460#else
461 uint8_t *p = ptr;
462 p[0] = v;
463 p[1] = v >> 8;
464 p[2] = v >> 16;
465 p[3] = v >> 24;
466#endif
467}
468
469static inline void stq_le_p(void *ptr, uint64_t v)
470{
471 uint8_t *p = ptr;
472 stl_le_p(p, (uint32_t)v);
473 stl_le_p(p + 4, v >> 32);
474}
475
476/* float access */
477
478static inline float32 ldfl_le_p(void *ptr)
479{
480 union {
481 float32 f;
482 uint32_t i;
483 } u;
484 u.i = ldl_le_p(ptr);
485 return u.f;
486}
487
488static inline void stfl_le_p(void *ptr, float32 v)
489{
490 union {
491 float32 f;
492 uint32_t i;
493 } u;
494 u.f = v;
495 stl_le_p(ptr, u.i);
496}
497
498static inline float64 ldfq_le_p(void *ptr)
499{
500 CPU_DoubleU u;
501 u.l.lower = ldl_le_p(ptr);
502 u.l.upper = ldl_le_p(ptr + 4);
503 return u.d;
504}
505
506static inline void stfq_le_p(void *ptr, float64 v)
507{
508 CPU_DoubleU u;
509 u.d = v;
510 stl_le_p(ptr, u.l.lower);
511 stl_le_p(ptr + 4, u.l.upper);
512}
513
514#else
515
516static inline int lduw_le_p(void *ptr)
517{
518 return *(uint16_t *)ptr;
519}
520
521static inline int ldsw_le_p(void *ptr)
522{
523 return *(int16_t *)ptr;
524}
525
526static inline int ldl_le_p(void *ptr)
527{
528 return *(uint32_t *)ptr;
529}
530
531static inline uint64_t ldq_le_p(void *ptr)
532{
533 return *(uint64_t *)ptr;
534}
535
536static inline void stw_le_p(void *ptr, int v)
537{
538 *(uint16_t *)ptr = v;
539}
540
541static inline void stl_le_p(void *ptr, int v)
542{
543 *(uint32_t *)ptr = v;
544}
545
546static inline void stq_le_p(void *ptr, uint64_t v)
547{
548 *(uint64_t *)ptr = v;
549}
550
551/* float access */
552
553static inline float32 ldfl_le_p(void *ptr)
554{
555 return *(float32 *)ptr;
556}
557
558static inline float64 ldfq_le_p(void *ptr)
559{
560 return *(float64 *)ptr;
561}
562
563static inline void stfl_le_p(void *ptr, float32 v)
564{
565 *(float32 *)ptr = v;
566}
567
568static inline void stfq_le_p(void *ptr, float64 v)
569{
570 *(float64 *)ptr = v;
571}
572#endif
573#endif /* !VBOX */
574
575#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
576
577#ifndef VBOX
578static inline int lduw_be_p(void *ptr)
579{
580#if defined(__i386__)
581 int val;
582 asm volatile ("movzwl %1, %0\n"
583 "xchgb %b0, %h0\n"
584 : "=q" (val)
585 : "m" (*(uint16_t *)ptr));
586 return val;
587#else
588 uint8_t *b = (uint8_t *) ptr;
589 return ((b[0] << 8) | b[1]);
590#endif
591}
592#else /* VBOX */
593DECLINLINE(int) lduw_be_p(void *ptr)
594{
595#if defined(__i386__) && !defined(_MSC_VER)
596 int val;
597 asm volatile ("movzwl %1, %0\n"
598 "xchgb %b0, %h0\n"
599 : "=q" (val)
600 : "m" (*(uint16_t *)ptr));
601 return val;
602#else
603 uint8_t *b = (uint8_t *) ptr;
604 return ((b[0] << 8) | b[1]);
605#endif
606}
607#endif
608
609#ifndef VBOX
610static inline int ldsw_be_p(void *ptr)
611{
612#if defined(__i386__)
613 int val;
614 asm volatile ("movzwl %1, %0\n"
615 "xchgb %b0, %h0\n"
616 : "=q" (val)
617 : "m" (*(uint16_t *)ptr));
618 return (int16_t)val;
619#else
620 uint8_t *b = (uint8_t *) ptr;
621 return (int16_t)((b[0] << 8) | b[1]);
622#endif
623}
624#else
625DECLINLINE(int) ldsw_be_p(void *ptr)
626{
627#if defined(__i386__) && !defined(_MSC_VER)
628 int val;
629 asm volatile ("movzwl %1, %0\n"
630 "xchgb %b0, %h0\n"
631 : "=q" (val)
632 : "m" (*(uint16_t *)ptr));
633 return (int16_t)val;
634#else
635 uint8_t *b = (uint8_t *) ptr;
636 return (int16_t)((b[0] << 8) | b[1]);
637#endif
638}
639#endif
640
641#ifndef VBOX
642static inline int ldl_be_p(void *ptr)
643{
644#if defined(__i386__) || defined(__x86_64__)
645 int val;
646 asm volatile ("movl %1, %0\n"
647 "bswap %0\n"
648 : "=r" (val)
649 : "m" (*(uint32_t *)ptr));
650 return val;
651#else
652 uint8_t *b = (uint8_t *) ptr;
653 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
654#endif
655}
656#else
657DECLINLINE(int) ldl_be_p(void *ptr)
658{
659#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
660 int val;
661 asm volatile ("movl %1, %0\n"
662 "bswap %0\n"
663 : "=r" (val)
664 : "m" (*(uint32_t *)ptr));
665 return val;
666#else
667 uint8_t *b = (uint8_t *) ptr;
668 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
669#endif
670}
671#endif
672
673#ifndef VBOX
674static inline uint64_t ldq_be_p(void *ptr)
675#else
676DECLINLINE(uint64_t) ldq_be_p(void *ptr)
677#endif
678{
679 uint32_t a,b;
680 a = ldl_be_p(ptr);
681 b = ldl_be_p((uint8_t*)ptr+4);
682 return (((uint64_t)a<<32)|b);
683}
684
685#ifndef VBOX
686static inline void stw_be_p(void *ptr, int v)
687{
688#if defined(__i386__)
689 asm volatile ("xchgb %b0, %h0\n"
690 "movw %w0, %1\n"
691 : "=q" (v)
692 : "m" (*(uint16_t *)ptr), "0" (v));
693#else
694 uint8_t *d = (uint8_t *) ptr;
695 d[0] = v >> 8;
696 d[1] = v;
697#endif
698}
699#else
700DECLINLINE(void) stw_be_p(void *ptr, int v)
701{
702#if defined(__i386__) && !defined(_MSC_VER)
703 asm volatile ("xchgb %b0, %h0\n"
704 "movw %w0, %1\n"
705 : "=q" (v)
706 : "m" (*(uint16_t *)ptr), "0" (v));
707#else
708 uint8_t *d = (uint8_t *) ptr;
709 d[0] = v >> 8;
710 d[1] = v;
711#endif
712}
713
714#endif /* VBOX */
715
716#ifndef VBOX
717static inline void stl_be_p(void *ptr, int v)
718{
719#if defined(__i386__) || defined(__x86_64__)
720 asm volatile ("bswap %0\n"
721 "movl %0, %1\n"
722 : "=r" (v)
723 : "m" (*(uint32_t *)ptr), "0" (v));
724#else
725 uint8_t *d = (uint8_t *) ptr;
726 d[0] = v >> 24;
727 d[1] = v >> 16;
728 d[2] = v >> 8;
729 d[3] = v;
730#endif
731}
732#else
733DECLINLINE(void) stl_be_p(void *ptr, int v)
734{
735#if !defined(_MSC_VER) && (defined(__i386__) || defined(__x86_64__))
736 asm volatile ("bswap %0\n"
737 "movl %0, %1\n"
738 : "=r" (v)
739 : "m" (*(uint32_t *)ptr), "0" (v));
740#else
741 uint8_t *d = (uint8_t *) ptr;
742 d[0] = v >> 24;
743 d[1] = v >> 16;
744 d[2] = v >> 8;
745 d[3] = v;
746#endif
747}
748#endif /* VBOX */
749
750#ifndef VBOX
751static inline void stq_be_p(void *ptr, uint64_t v)
752#else
753DECLINLINE(void) stq_be_p(void *ptr, uint64_t v)
754#endif
755{
756 stl_be_p(ptr, v >> 32);
757 stl_be_p((uint8_t*)ptr + 4, v);
758}
759
760/* float access */
761#ifndef VBOX
762static inline float32 ldfl_be_p(void *ptr)
763#else
764DECLINLINE(float32) ldfl_be_p(void *ptr)
765#endif
766{
767 union {
768 float32 f;
769 uint32_t i;
770 } u;
771 u.i = ldl_be_p(ptr);
772 return u.f;
773}
774
775#ifndef VBOX
776static inline void stfl_be_p(void *ptr, float32 v)
777#else
778DECLINLINE(void) stfl_be_p(void *ptr, float32 v)
779#endif
780{
781 union {
782 float32 f;
783 uint32_t i;
784 } u;
785 u.f = v;
786 stl_be_p(ptr, u.i);
787}
788
789#ifndef VBOX
790static inline float64 ldfq_be_p(void *ptr)
791#else
792DECLINLINE(float64) ldfq_be_p(void *ptr)
793#endif
794{
795 CPU_DoubleU u;
796 u.l.upper = ldl_be_p(ptr);
797 u.l.lower = ldl_be_p((uint8_t*)ptr + 4);
798 return u.d;
799}
800
801#ifndef VBOX
802static inline void stfq_be_p(void *ptr, float64 v)
803#else
804DECLINLINE(void) stfq_be_p(void *ptr, float64 v)
805#endif
806{
807 CPU_DoubleU u;
808 u.d = v;
809 stl_be_p(ptr, u.l.upper);
810 stl_be_p((uint8_t*)ptr + 4, u.l.lower);
811}
812
813#else
814
815static inline int lduw_be_p(void *ptr)
816{
817 return *(uint16_t *)ptr;
818}
819
820static inline int ldsw_be_p(void *ptr)
821{
822 return *(int16_t *)ptr;
823}
824
825static inline int ldl_be_p(void *ptr)
826{
827 return *(uint32_t *)ptr;
828}
829
830static inline uint64_t ldq_be_p(void *ptr)
831{
832 return *(uint64_t *)ptr;
833}
834
835static inline void stw_be_p(void *ptr, int v)
836{
837 *(uint16_t *)ptr = v;
838}
839
840static inline void stl_be_p(void *ptr, int v)
841{
842 *(uint32_t *)ptr = v;
843}
844
845static inline void stq_be_p(void *ptr, uint64_t v)
846{
847 *(uint64_t *)ptr = v;
848}
849
850/* float access */
851
852static inline float32 ldfl_be_p(void *ptr)
853{
854 return *(float32 *)ptr;
855}
856
857static inline float64 ldfq_be_p(void *ptr)
858{
859 return *(float64 *)ptr;
860}
861
862static inline void stfl_be_p(void *ptr, float32 v)
863{
864 *(float32 *)ptr = v;
865}
866
867static inline void stfq_be_p(void *ptr, float64 v)
868{
869 *(float64 *)ptr = v;
870}
871
872#endif
873
874/* target CPU memory access functions */
875#if defined(TARGET_WORDS_BIGENDIAN)
876#define lduw_p(p) lduw_be_p(p)
877#define ldsw_p(p) ldsw_be_p(p)
878#define ldl_p(p) ldl_be_p(p)
879#define ldq_p(p) ldq_be_p(p)
880#define ldfl_p(p) ldfl_be_p(p)
881#define ldfq_p(p) ldfq_be_p(p)
882#define stw_p(p, v) stw_be_p(p, v)
883#define stl_p(p, v) stl_be_p(p, v)
884#define stq_p(p, v) stq_be_p(p, v)
885#define stfl_p(p, v) stfl_be_p(p, v)
886#define stfq_p(p, v) stfq_be_p(p, v)
887#else
888#define lduw_p(p) lduw_le_p(p)
889#define ldsw_p(p) ldsw_le_p(p)
890#define ldl_p(p) ldl_le_p(p)
891#define ldq_p(p) ldq_le_p(p)
892#define ldfl_p(p) ldfl_le_p(p)
893#define ldfq_p(p) ldfq_le_p(p)
894#define stw_p(p, v) stw_le_p(p, v)
895#define stl_p(p, v) stl_le_p(p, v)
896#define stq_p(p, v) stq_le_p(p, v)
897#define stfl_p(p, v) stfl_le_p(p, v)
898#define stfq_p(p, v) stfq_le_p(p, v)
899#endif
900
901/* MMU memory access macros */
902
903#if defined(CONFIG_USER_ONLY)
904/* On some host systems the guest address space is reserved on the host.
905 * This allows the guest address space to be offset to a convenient location.
906 */
907//#define GUEST_BASE 0x20000000
908#define GUEST_BASE 0
909
910/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
911#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
912#define h2g(x) ((target_ulong)(x - GUEST_BASE))
913#define saddr(x) g2h(x)
914#define laddr(x) g2h(x)
915
916#else /* !CONFIG_USER_ONLY */
917/* NOTE: we use double casts if pointers and target_ulong have
918 different sizes */
919#define saddr(x) (uint8_t *)(long)(x)
920#define laddr(x) (uint8_t *)(long)(x)
921#endif
922
923#define ldub_raw(p) ldub_p(laddr((p)))
924#define ldsb_raw(p) ldsb_p(laddr((p)))
925#define lduw_raw(p) lduw_p(laddr((p)))
926#define ldsw_raw(p) ldsw_p(laddr((p)))
927#define ldl_raw(p) ldl_p(laddr((p)))
928#define ldq_raw(p) ldq_p(laddr((p)))
929#define ldfl_raw(p) ldfl_p(laddr((p)))
930#define ldfq_raw(p) ldfq_p(laddr((p)))
931#define stb_raw(p, v) stb_p(saddr((p)), v)
932#define stw_raw(p, v) stw_p(saddr((p)), v)
933#define stl_raw(p, v) stl_p(saddr((p)), v)
934#define stq_raw(p, v) stq_p(saddr((p)), v)
935#define stfl_raw(p, v) stfl_p(saddr((p)), v)
936#define stfq_raw(p, v) stfq_p(saddr((p)), v)
937
938
939#if defined(CONFIG_USER_ONLY)
940
941/* if user mode, no other memory access functions */
942#define ldub(p) ldub_raw(p)
943#define ldsb(p) ldsb_raw(p)
944#define lduw(p) lduw_raw(p)
945#define ldsw(p) ldsw_raw(p)
946#define ldl(p) ldl_raw(p)
947#define ldq(p) ldq_raw(p)
948#define ldfl(p) ldfl_raw(p)
949#define ldfq(p) ldfq_raw(p)
950#define stb(p, v) stb_raw(p, v)
951#define stw(p, v) stw_raw(p, v)
952#define stl(p, v) stl_raw(p, v)
953#define stq(p, v) stq_raw(p, v)
954#define stfl(p, v) stfl_raw(p, v)
955#define stfq(p, v) stfq_raw(p, v)
956
957#define ldub_code(p) ldub_raw(p)
958#define ldsb_code(p) ldsb_raw(p)
959#define lduw_code(p) lduw_raw(p)
960#define ldsw_code(p) ldsw_raw(p)
961#define ldl_code(p) ldl_raw(p)
962
963#define ldub_kernel(p) ldub_raw(p)
964#define ldsb_kernel(p) ldsb_raw(p)
965#define lduw_kernel(p) lduw_raw(p)
966#define ldsw_kernel(p) ldsw_raw(p)
967#define ldl_kernel(p) ldl_raw(p)
968#define ldfl_kernel(p) ldfl_raw(p)
969#define ldfq_kernel(p) ldfq_raw(p)
970#define stb_kernel(p, v) stb_raw(p, v)
971#define stw_kernel(p, v) stw_raw(p, v)
972#define stl_kernel(p, v) stl_raw(p, v)
973#define stq_kernel(p, v) stq_raw(p, v)
974#define stfl_kernel(p, v) stfl_raw(p, v)
975#define stfq_kernel(p, vt) stfq_raw(p, v)
976
977#endif /* defined(CONFIG_USER_ONLY) */
978
979/* page related stuff */
980
981#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
982#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
983#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
984
985/* ??? These should be the larger of unsigned long and target_ulong. */
986extern unsigned long qemu_real_host_page_size;
987extern unsigned long qemu_host_page_bits;
988extern unsigned long qemu_host_page_size;
989extern unsigned long qemu_host_page_mask;
990
991#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
992
993/* same as PROT_xxx */
994#define PAGE_READ 0x0001
995#define PAGE_WRITE 0x0002
996#define PAGE_EXEC 0x0004
997#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
998#define PAGE_VALID 0x0008
999/* original state of the write flag (used when tracking self-modifying
1000 code */
1001#define PAGE_WRITE_ORG 0x0010
1002#define PAGE_RESERVED 0x0020
1003
1004void page_dump(FILE *f);
1005int page_get_flags(target_ulong address);
1006void page_set_flags(target_ulong start, target_ulong end, int flags);
1007int page_check_range(target_ulong start, target_ulong len, int flags);
1008void page_unprotect_range(target_ulong data, target_ulong data_size);
1009
1010#define SINGLE_CPU_DEFINES
1011#ifdef SINGLE_CPU_DEFINES
1012
1013#if defined(TARGET_I386)
1014
1015#define CPUState CPUX86State
1016#define cpu_init cpu_x86_init
1017#define cpu_exec cpu_x86_exec
1018#define cpu_gen_code cpu_x86_gen_code
1019#define cpu_signal_handler cpu_x86_signal_handler
1020
1021#elif defined(TARGET_ARM)
1022
1023#define CPUState CPUARMState
1024#define cpu_init cpu_arm_init
1025#define cpu_exec cpu_arm_exec
1026#define cpu_gen_code cpu_arm_gen_code
1027#define cpu_signal_handler cpu_arm_signal_handler
1028
1029#elif defined(TARGET_SPARC)
1030
1031#define CPUState CPUSPARCState
1032#define cpu_init cpu_sparc_init
1033#define cpu_exec cpu_sparc_exec
1034#define cpu_gen_code cpu_sparc_gen_code
1035#define cpu_signal_handler cpu_sparc_signal_handler
1036
1037#elif defined(TARGET_PPC)
1038
1039#define CPUState CPUPPCState
1040#define cpu_init cpu_ppc_init
1041#define cpu_exec cpu_ppc_exec
1042#define cpu_gen_code cpu_ppc_gen_code
1043#define cpu_signal_handler cpu_ppc_signal_handler
1044
1045#elif defined(TARGET_M68K)
1046#define CPUState CPUM68KState
1047#define cpu_init cpu_m68k_init
1048#define cpu_exec cpu_m68k_exec
1049#define cpu_gen_code cpu_m68k_gen_code
1050#define cpu_signal_handler cpu_m68k_signal_handler
1051
1052#elif defined(TARGET_MIPS)
1053#define CPUState CPUMIPSState
1054#define cpu_init cpu_mips_init
1055#define cpu_exec cpu_mips_exec
1056#define cpu_gen_code cpu_mips_gen_code
1057#define cpu_signal_handler cpu_mips_signal_handler
1058
1059#elif defined(TARGET_SH4)
1060#define CPUState CPUSH4State
1061#define cpu_init cpu_sh4_init
1062#define cpu_exec cpu_sh4_exec
1063#define cpu_gen_code cpu_sh4_gen_code
1064#define cpu_signal_handler cpu_sh4_signal_handler
1065
1066#else
1067
1068#error unsupported target CPU
1069
1070#endif
1071
1072#endif /* SINGLE_CPU_DEFINES */
1073
1074void cpu_dump_state(CPUState *env, FILE *f,
1075 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1076 int flags);
1077
1078DECLNORETURN(void) cpu_abort(CPUState *env, const char *fmt, ...);
1079extern CPUState *first_cpu;
1080extern CPUState *cpu_single_env;
1081extern int64_t qemu_icount;
1082extern int use_icount;
1083
1084#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
1085#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
1086#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
1087#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
1088#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
1089#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
1090#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
1091#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occurred. */
1092#define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
1093#define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
1094
1095#ifdef VBOX
1096/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
1097#define CPU_INTERRUPT_SINGLE_INSTR 0x0400
1098/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
1099#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0800
1100/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
1101#define CPU_INTERRUPT_RC 0x1000
1102/** Exit current TB to process an external interrupt request (also in op.c!!) */
1103#define CPU_INTERRUPT_EXTERNAL_EXIT 0x2000
1104/** Exit current TB to process an external interrupt request (also in op.c!!) */
1105#define CPU_INTERRUPT_EXTERNAL_HARD 0x4000
1106/** Exit current TB to process an external interrupt request (also in op.c!!) */
1107#define CPU_INTERRUPT_EXTERNAL_TIMER 0x8000
1108/** Exit current TB to process an external interrupt request (also in op.c!!) */
1109#define CPU_INTERRUPT_EXTERNAL_DMA 0x10000
1110#endif /* VBOX */
1111void cpu_interrupt(CPUState *s, int mask);
1112void cpu_reset_interrupt(CPUState *env, int mask);
1113
1114int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type);
1115int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
1116void cpu_watchpoint_remove_all(CPUState *env);
1117int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
1118int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
1119void cpu_breakpoint_remove_all(CPUState *env);
1120
1121#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1122#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1123#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1124
1125void cpu_single_step(CPUState *env, int enabled);
1126void cpu_reset(CPUState *s);
1127
1128/* Return the physical page corresponding to a virtual one. Use it
1129 only for debugging because no protection checks are done. Return -1
1130 if no page found. */
1131target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
1132
1133#define CPU_LOG_TB_OUT_ASM (1 << 0)
1134#define CPU_LOG_TB_IN_ASM (1 << 1)
1135#define CPU_LOG_TB_OP (1 << 2)
1136#define CPU_LOG_TB_OP_OPT (1 << 3)
1137#define CPU_LOG_INT (1 << 4)
1138#define CPU_LOG_EXEC (1 << 5)
1139#define CPU_LOG_PCALL (1 << 6)
1140#define CPU_LOG_IOPORT (1 << 7)
1141#define CPU_LOG_TB_CPU (1 << 8)
1142
1143/* define log items */
1144typedef struct CPULogItem {
1145 int mask;
1146 const char *name;
1147 const char *help;
1148} CPULogItem;
1149
1150extern CPULogItem cpu_log_items[];
1151
1152void cpu_set_log(int log_flags);
1153void cpu_set_log_filename(const char *filename);
1154int cpu_str_to_log_mask(const char *str);
1155
1156/* IO ports API */
1157
1158/* NOTE: as these functions may be even used when there is an isa
1159 brige on non x86 targets, we always defined them */
1160#ifndef NO_CPU_IO_DEFS
1161void cpu_outb(CPUState *env, int addr, int val);
1162void cpu_outw(CPUState *env, int addr, int val);
1163void cpu_outl(CPUState *env, int addr, int val);
1164int cpu_inb(CPUState *env, int addr);
1165int cpu_inw(CPUState *env, int addr);
1166int cpu_inl(CPUState *env, int addr);
1167#endif
1168
1169/* address in the RAM (different from a physical address) */
1170#ifdef USE_KQEMU
1171typedef uint32_t ram_addr_t;
1172#else
1173typedef unsigned long ram_addr_t;
1174#endif
1175
1176/* memory API */
1177
1178#ifndef VBOX
1179extern int phys_ram_size;
1180extern int phys_ram_fd;
1181extern int phys_ram_size;
1182#else /* VBOX */
1183extern RTGCPHYS phys_ram_size;
1184/** This is required for bounds checking the phys_ram_dirty accesses. */
1185extern RTGCPHYS phys_ram_dirty_size;
1186#endif /* VBOX */
1187#if !defined(VBOX)
1188extern uint8_t *phys_ram_base;
1189#endif
1190extern uint8_t *phys_ram_dirty;
1191
1192/* physical memory access */
1193
1194/* MMIO pages are identified by a combination of an IO device index and
1195 3 flags. The ROMD code stores the page ram offset in iotlb entry,
1196 so only a limited number of ids are available. */
1197
1198#define IO_MEM_SHIFT 3
1199#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
1200
1201#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
1202#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
1203#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
1204#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
1205
1206/* Acts like a ROM when read and like a device when written. */
1207#define IO_MEM_ROMD (1)
1208#define IO_MEM_SUBPAGE (2)
1209#define IO_MEM_SUBWIDTH (4)
1210
1211/* Flags stored in the low bits of the TLB virtual address. These are
1212 defined so that fast path ram access is all zeros. */
1213/* Zero if TLB entry is valid. */
1214#define TLB_INVALID_MASK (1 << 3)
1215/* Set if TLB entry references a clean RAM page. The iotlb entry will
1216 contain the page physical address. */
1217#define TLB_NOTDIRTY (1 << 4)
1218/* Set if TLB entry is an IO callback. */
1219#define TLB_MMIO (1 << 5)
1220
1221typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
1222typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
1223
1224void cpu_register_physical_memory(target_phys_addr_t start_addr,
1225 ram_addr_t size,
1226 ram_addr_t phys_offset);
1227uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
1228ram_addr_t qemu_ram_alloc(ram_addr_t);
1229void qemu_ram_free(ram_addr_t addr);
1230int cpu_register_io_memory(int io_index,
1231 CPUReadMemoryFunc **mem_read,
1232 CPUWriteMemoryFunc **mem_write,
1233 void *opaque);
1234CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
1235CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
1236
1237void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1238 int len, int is_write);
1239#ifndef VBOX
1240static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1241 uint8_t *buf, int len)
1242#else
1243DECLINLINE(void) cpu_physical_memory_read(target_phys_addr_t addr,
1244 uint8_t *buf, int len)
1245#endif
1246{
1247 cpu_physical_memory_rw(addr, buf, len, 0);
1248}
1249#ifndef VBOX
1250static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1251 const uint8_t *buf, int len)
1252#else
1253DECLINLINE(void) cpu_physical_memory_write(target_phys_addr_t addr,
1254 const uint8_t *buf, int len)
1255#endif
1256{
1257 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1258}
1259uint32_t ldub_phys(target_phys_addr_t addr);
1260uint32_t lduw_phys(target_phys_addr_t addr);
1261uint32_t ldl_phys(target_phys_addr_t addr);
1262uint64_t ldq_phys(target_phys_addr_t addr);
1263void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1264void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
1265void stb_phys(target_phys_addr_t addr, uint32_t val);
1266void stw_phys(target_phys_addr_t addr, uint32_t val);
1267void stl_phys(target_phys_addr_t addr, uint32_t val);
1268void stq_phys(target_phys_addr_t addr, uint64_t val);
1269
1270void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1271 const uint8_t *buf, int len);
1272int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1273 uint8_t *buf, int len, int is_write);
1274
1275#define VGA_DIRTY_FLAG 0x01
1276#define CODE_DIRTY_FLAG 0x02
1277#define KQEMU_DIRTY_FLAG 0x04
1278#define MIGRATION_DIRTY_FLAG 0x08
1279
1280/* read dirty bit (return 0 or 1) */
1281#ifndef VBOX
1282static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1283{
1284 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1285}
1286#else
1287DECLINLINE(int) cpu_physical_memory_is_dirty(ram_addr_t addr)
1288{
1289 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1290 {
1291 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1292 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1293 return 0;
1294 }
1295 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1296}
1297#endif
1298
1299#ifndef VBOX
1300static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1301 int dirty_flags)
1302{
1303 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1304}
1305#else
1306DECLINLINE(int) cpu_physical_memory_get_dirty(ram_addr_t addr,
1307 int dirty_flags)
1308{
1309 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1310 {
1311 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1312 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1313 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1314 }
1315 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1316}
1317#endif
1318
1319#ifndef VBOX
1320static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1321{
1322 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1323}
1324#else
1325DECLINLINE(void) cpu_physical_memory_set_dirty(ram_addr_t addr)
1326{
1327 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1328 {
1329 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1330 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1331 return;
1332 }
1333 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1334}
1335#endif
1336
1337void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1338 int dirty_flags);
1339void cpu_tlb_update_dirty(CPUState *env);
1340
1341int cpu_physical_memory_set_dirty_tracking(int enable);
1342
1343int cpu_physical_memory_get_dirty_tracking(void);
1344
1345void dump_exec_info(FILE *f,
1346 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1347
1348/*******************************************/
1349/* host CPU ticks (if available) */
1350
1351#ifdef VBOX
1352# include <iprt/asm-amd64-x86.h>
1353
1354DECLINLINE(int64_t) cpu_get_real_ticks(void)
1355{
1356 return ASMReadTSC();
1357}
1358
1359#elif defined(__powerpc__)
1360
1361static inline uint32_t get_tbl(void)
1362{
1363 uint32_t tbl;
1364 asm volatile("mftb %0" : "=r" (tbl));
1365 return tbl;
1366}
1367
1368static inline uint32_t get_tbu(void)
1369{
1370 uint32_t tbl;
1371 asm volatile("mftbu %0" : "=r" (tbl));
1372 return tbl;
1373}
1374
1375static inline int64_t cpu_get_real_ticks(void)
1376{
1377 uint32_t l, h, h1;
1378 /* NOTE: we test if wrapping has occurred */
1379 do {
1380 h = get_tbu();
1381 l = get_tbl();
1382 h1 = get_tbu();
1383 } while (h != h1);
1384 return ((int64_t)h << 32) | l;
1385}
1386
1387#elif defined(__i386__)
1388
1389static inline int64_t cpu_get_real_ticks(void)
1390{
1391 int64_t val;
1392 asm volatile ("rdtsc" : "=A" (val));
1393 return val;
1394}
1395
1396#elif defined(__x86_64__)
1397
1398static inline int64_t cpu_get_real_ticks(void)
1399{
1400 uint32_t low,high;
1401 int64_t val;
1402 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1403 val = high;
1404 val <<= 32;
1405 val |= low;
1406 return val;
1407}
1408
1409#elif defined(__ia64)
1410
1411static inline int64_t cpu_get_real_ticks(void)
1412{
1413 int64_t val;
1414 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1415 return val;
1416}
1417
1418#elif defined(__s390__)
1419
1420static inline int64_t cpu_get_real_ticks(void)
1421{
1422 int64_t val;
1423 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1424 return val;
1425}
1426
1427#elif defined(__sparc_v9__)
1428
1429static inline int64_t cpu_get_real_ticks (void)
1430{
1431#if defined(_LP64)
1432 uint64_t rval;
1433 asm volatile("rd %%tick,%0" : "=r"(rval));
1434 return rval;
1435#else
1436 union {
1437 uint64_t i64;
1438 struct {
1439 uint32_t high;
1440 uint32_t low;
1441 } i32;
1442 } rval;
1443 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1444 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1445 return rval.i64;
1446#endif
1447}
1448#else
1449/* The host CPU doesn't have an easily accessible cycle counter.
1450 Just return a monotonically increasing vlue. This will be totally wrong,
1451 but hopefully better than nothing. */
1452static inline int64_t cpu_get_real_ticks (void)
1453{
1454 static int64_t ticks = 0;
1455 return ticks++;
1456}
1457#endif
1458
1459/* profiling */
1460#ifdef CONFIG_PROFILER
1461static inline int64_t profile_getclock(void)
1462{
1463 return cpu_get_real_ticks();
1464}
1465
1466extern int64_t kqemu_time, kqemu_time_start;
1467extern int64_t qemu_time, qemu_time_start;
1468extern int64_t tlb_flush_time;
1469extern int64_t kqemu_exec_count;
1470extern int64_t dev_time;
1471extern int64_t kqemu_ret_int_count;
1472extern int64_t kqemu_ret_excp_count;
1473extern int64_t kqemu_ret_intr_count;
1474
1475#endif
1476
1477#ifdef VBOX
1478void tb_invalidate_virt(CPUState *env, uint32_t eip);
1479#endif /* VBOX */
1480
1481#endif /* CPU_ALL_H */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette