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source: vbox/trunk/src/recompiler/exec-all.h@ 49523

Last change on this file since 49523 was 42601, checked in by vboxsync, 12 years ago

REM: Initial changes to make it work (seemingly) with MinGW-w64.
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1/*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
22 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
23 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
24 * a choice of LGPL license versions is made available with the language indicating
25 * that LGPLv2 or any later version may be used, or where a choice of which version
26 * of the LGPL is applied is otherwise unspecified.
27 */
28
29#ifndef _EXEC_ALL_H_
30#define _EXEC_ALL_H_
31
32#include "qemu-common.h"
33#ifdef VBOX
34# include <VBox/vmm/tm.h>
35# include <VBox/vmm/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
36# include <VBox/vmm/em.h> /* EMRemIsLockOwner */
37# ifndef LOG_GROUP
38# define LOG_GROUP LOG_GROUP_REM
39# endif
40# include <VBox/log.h>
41# include "REMInternal.h"
42# include <VBox/vmm/vm.h>
43#endif /* VBOX */
44
45/* allow to see translation results - the slowdown should be negligible, so we leave it */
46#ifndef VBOX
47#define DEBUG_DISAS
48#endif /* !VBOX */
49
50/* Page tracking code uses ram addresses in system mode, and virtual
51 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
52 type. */
53#if defined(CONFIG_USER_ONLY)
54typedef abi_ulong tb_page_addr_t;
55#else
56typedef ram_addr_t tb_page_addr_t;
57#endif
58
59/* is_jmp field values */
60#define DISAS_NEXT 0 /* next instruction can be analyzed */
61#define DISAS_JUMP 1 /* only pc was modified dynamically */
62#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
63#define DISAS_TB_JUMP 3 /* only pc was modified statically */
64
65typedef struct TranslationBlock TranslationBlock;
66
67/* XXX: make safe guess about sizes */
68#define MAX_OP_PER_INSTR 96
69
70#if HOST_LONG_BITS == 32
71#define MAX_OPC_PARAM_PER_ARG 2
72#else
73#define MAX_OPC_PARAM_PER_ARG 1
74#endif
75#define MAX_OPC_PARAM_IARGS 4
76#define MAX_OPC_PARAM_OARGS 1
77#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
78
79/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
80 * and up to 4 + N parameters on 64-bit archs
81 * (N = number of input arguments + output arguments). */
82#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
83#define OPC_BUF_SIZE 640
84#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
85
86/* Maximum size a TCG op can expand to. This is complicated because a
87 single op may require several host instructions and register reloads.
88 For now take a wild guess at 192 bytes, which should allow at least
89 a couple of fixup instructions per argument. */
90#define TCG_MAX_OP_SIZE 192
91
92#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
93
94extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
95extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
96extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
97
98#include "qemu-log.h"
99
100void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
101void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
102void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
103 uintptr_t searched_pc, int pc_pos, void *puc);
104
105void cpu_gen_init(void);
106int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
107 int *gen_code_size_ptr);
108int cpu_restore_state(struct TranslationBlock *tb,
109 CPUState *env, uintptr_t searched_pc,
110 void *puc);
111void cpu_resume_from_signal(CPUState *env1, void *puc);
112void cpu_io_recompile(CPUState *env, void *retaddr);
113TranslationBlock *tb_gen_code(CPUState *env,
114 target_ulong pc, target_ulong cs_base, int flags,
115 int cflags);
116void cpu_exec_init(CPUState *env);
117void QEMU_NORETURN cpu_loop_exit(void);
118int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
119void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
120 int is_cpu_write_access);
121void tb_invalidate_page_range(target_ulong start, target_ulong end);
122void tlb_flush_page(CPUState *env, target_ulong addr);
123void tlb_flush(CPUState *env, int flush_global);
124#if !defined(CONFIG_USER_ONLY)
125void tlb_set_page(CPUState *env, target_ulong vaddr,
126 target_phys_addr_t paddr, int prot,
127 int mmu_idx, target_ulong size);
128#endif
129
130#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
131
132#define CODE_GEN_PHYS_HASH_BITS 15
133#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
134
135#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
136
137/* estimated block size for TB allocation */
138/* XXX: use a per code average code fragment size and modulate it
139 according to the host CPU */
140#if defined(CONFIG_SOFTMMU)
141#define CODE_GEN_AVG_BLOCK_SIZE 128
142#else
143#define CODE_GEN_AVG_BLOCK_SIZE 64
144#endif
145
146#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
147#define USE_DIRECT_JUMP
148#endif
149
150#ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
151# undef USE_DIRECT_JUMP
152#endif /* VBOX */
153
154struct TranslationBlock {
155 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
156 target_ulong cs_base; /* CS base for this block */
157 uint64_t flags; /* flags defining in which context the code was generated */
158 uint16_t size; /* size of target code for this block (1 <=
159 size <= TARGET_PAGE_SIZE) */
160 uint16_t cflags; /* compile flags */
161#define CF_COUNT_MASK 0x7fff
162#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
163#ifdef VBOX
164# define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
165#endif
166
167 uint8_t *tc_ptr; /* pointer to the translated code */
168 /* next matching tb for physical address. */
169 struct TranslationBlock *phys_hash_next;
170 /* first and second physical page containing code. The lower bit
171 of the pointer tells the index in page_next[] */
172 struct TranslationBlock *page_next[2];
173 tb_page_addr_t page_addr[2];
174
175 /* the following data are used to directly call another TB from
176 the code of this one. */
177 uint16_t tb_next_offset[2]; /* offset of original jump target */
178#ifdef USE_DIRECT_JUMP
179 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
180#else
181 uintptr_t tb_next[2]; /* address of jump generated code */
182#endif
183 /* list of TBs jumping to this one. This is a circular list using
184 the two least significant bits of the pointers to tell what is
185 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
186 jmp_first */
187 struct TranslationBlock *jmp_next[2];
188 struct TranslationBlock *jmp_first;
189 uint32_t icount;
190};
191
192static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
193{
194 target_ulong tmp;
195 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
196 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
197}
198
199static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
200{
201 target_ulong tmp;
202 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
203 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
204 | (tmp & TB_JMP_ADDR_MASK));
205}
206
207static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
208{
209 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
210}
211
212TranslationBlock *tb_alloc(target_ulong pc);
213void tb_free(TranslationBlock *tb);
214void tb_flush(CPUState *env);
215void tb_link_page(TranslationBlock *tb,
216 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
217void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
218
219extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
220
221#if defined(USE_DIRECT_JUMP)
222
223#if defined(_ARCH_PPC)
224extern void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
225#define tb_set_jmp_target1 ppc_tb_set_jmp_target
226#elif defined(__i386__) || defined(__x86_64__)
227static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
228{
229 /* patch the branch destination */
230 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
231 /* no need to flush icache explicitly */
232}
233#elif defined(__arm__)
234static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
235{
236#if QEMU_GNUC_PREREQ(4, 1)
237 void __clear_cache(char *beg, char *end);
238#else
239 register unsigned long _beg __asm ("a1");
240 register unsigned long _end __asm ("a2");
241 register unsigned long _flg __asm ("a3");
242#endif
243
244 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
245 *(uint32_t *)jmp_addr =
246 (*(uint32_t *)jmp_addr & ~0xffffff)
247 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
248
249#if QEMU_GNUC_PREREQ(4, 1)
250 __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
251#else
252 /* flush icache */
253 _beg = jmp_addr;
254 _end = jmp_addr + 4;
255 _flg = 0;
256 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
257#endif
258}
259#endif
260
261static inline void tb_set_jmp_target(TranslationBlock *tb,
262 int n, uintptr_t addr)
263{
264 uintptr_t offset;
265
266 offset = tb->tb_jmp_offset[n];
267 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
268}
269
270#else
271
272/* set the jump target */
273static inline void tb_set_jmp_target(TranslationBlock *tb,
274 int n, uintptr_t addr)
275{
276 tb->tb_next[n] = addr;
277}
278
279#endif
280
281static inline void tb_add_jump(TranslationBlock *tb, int n,
282 TranslationBlock *tb_next)
283{
284 /* NOTE: this test is only needed for thread safety */
285 if (!tb->jmp_next[n]) {
286 /* patch the native jump address */
287 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
288
289 /* add in TB jmp circular list */
290 tb->jmp_next[n] = tb_next->jmp_first;
291 tb_next->jmp_first = (TranslationBlock *)((intptr_t)(tb) | (n));
292 }
293}
294
295TranslationBlock *tb_find_pc(uintptr_t pc_ptr);
296
297#include "qemu-lock.h"
298
299extern spinlock_t tb_lock;
300
301extern int tb_invalidated_flag;
302
303#if !defined(CONFIG_USER_ONLY)
304
305extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
306extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
307extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
308
309void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
310 void *retaddr);
311
312#include "softmmu_defs.h"
313
314#define ACCESS_TYPE (NB_MMU_MODES + 1)
315#define MEMSUFFIX _code
316#define env cpu_single_env
317
318#define DATA_SIZE 1
319#include "softmmu_header.h"
320
321#define DATA_SIZE 2
322#include "softmmu_header.h"
323
324#define DATA_SIZE 4
325#include "softmmu_header.h"
326
327#define DATA_SIZE 8
328#include "softmmu_header.h"
329
330#undef ACCESS_TYPE
331#undef MEMSUFFIX
332#undef env
333
334#endif
335
336#if defined(CONFIG_USER_ONLY)
337static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
338{
339 return addr;
340}
341#else
342# ifdef VBOX
343target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry, target_phys_addr_t ioTLBEntry);
344# endif
345/* NOTE: this function can trigger an exception */
346/* NOTE2: the returned address is not exactly the physical address: it
347 is the offset relative to phys_ram_base */
348static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
349{
350 int mmu_idx, page_index, pd;
351# ifndef VBOX
352 void *p;
353# endif
354
355 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
356 mmu_idx = cpu_mmu_index(env1);
357 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
358 (addr & TARGET_PAGE_MASK))) {
359 ldub_code(addr);
360 }
361 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
362 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
363# ifdef VBOX
364 /* deal with non-MMIO access handlers. */
365 return remR3PhysGetPhysicalAddressCode(env1, addr,
366 &env1->tlb_table[mmu_idx][page_index],
367 env1->iotlb[mmu_idx][page_index]);
368# elif defined(TARGET_SPARC) || defined(TARGET_MIPS)
369 do_unassigned_access(addr, 0, 1, 0, 4);
370#else
371 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
372#endif
373 }
374# if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
375 return addr + env1->tlb_table[mmu_idx][page_index].addend;
376# elif defined(VBOX)
377 Assert(env1->phys_addends[mmu_idx][page_index] != -1);
378 return addr + env1->phys_addends[mmu_idx][page_index];
379# else
380 p = (void *)(uintptr_t)addr
381 + env1->tlb_table[mmu_idx][page_index].addend;
382 return qemu_ram_addr_from_host(p);
383# endif
384}
385#endif
386
387typedef void (CPUDebugExcpHandler)(CPUState *env);
388
389CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
390
391#ifndef VBOX
392/* vl.c */
393extern int singlestep;
394
395/* cpu-exec.c */
396extern volatile sig_atomic_t exit_request;
397#endif /*!VBOX*/
398
399
400#endif
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