VirtualBox

source: vbox/trunk/src/recompiler/new/cpu-all.h@ 1349

Last change on this file since 1349 was 1182, checked in by vboxsync, 18 years ago

Restore the PGM_DYNAMIC_RAM_ALLOC tests and #include <VBox/pgm.h> to make sure it's defined.

  • Property svn:eol-style set to native
File size: 29.7 KB
Line 
1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_ALL_H
21#define CPU_ALL_H
22
23#ifdef VBOX
24# ifndef LOG_GROUP
25# include <VBox/log.h>
26# define LOG_GROUP LOG_GROUP_REM
27# endif
28# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
29#endif
30
31#if defined(__arm__) || defined(__sparc__)
32#define WORDS_ALIGNED
33#endif
34
35/* some important defines:
36 *
37 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
38 * memory accesses.
39 *
40 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
41 * otherwise little endian.
42 *
43 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
44 *
45 * TARGET_WORDS_BIGENDIAN : same for target cpu
46 */
47
48#include "bswap.h"
49
50#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
51#define BSWAP_NEEDED
52#endif
53
54#ifdef BSWAP_NEEDED
55
56static inline uint16_t tswap16(uint16_t s)
57{
58 return bswap16(s);
59}
60
61static inline uint32_t tswap32(uint32_t s)
62{
63 return bswap32(s);
64}
65
66static inline uint64_t tswap64(uint64_t s)
67{
68 return bswap64(s);
69}
70
71static inline void tswap16s(uint16_t *s)
72{
73 *s = bswap16(*s);
74}
75
76static inline void tswap32s(uint32_t *s)
77{
78 *s = bswap32(*s);
79}
80
81static inline void tswap64s(uint64_t *s)
82{
83 *s = bswap64(*s);
84}
85
86#else
87
88static inline uint16_t tswap16(uint16_t s)
89{
90 return s;
91}
92
93static inline uint32_t tswap32(uint32_t s)
94{
95 return s;
96}
97
98static inline uint64_t tswap64(uint64_t s)
99{
100 return s;
101}
102
103static inline void tswap16s(uint16_t *s)
104{
105}
106
107static inline void tswap32s(uint32_t *s)
108{
109}
110
111static inline void tswap64s(uint64_t *s)
112{
113}
114
115#endif
116
117#if TARGET_LONG_SIZE == 4
118#define tswapl(s) tswap32(s)
119#define tswapls(s) tswap32s((uint32_t *)(s))
120#define bswaptls(s) bswap32s(s)
121#else
122#define tswapl(s) tswap64(s)
123#define tswapls(s) tswap64s((uint64_t *)(s))
124#define bswaptls(s) bswap64s(s)
125#endif
126
127/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
128 endian ! */
129typedef union {
130 float64 d;
131#if defined(WORDS_BIGENDIAN) \
132 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
133 struct {
134 uint32_t upper;
135 uint32_t lower;
136 } l;
137#else
138 struct {
139 uint32_t lower;
140 uint32_t upper;
141 } l;
142#endif
143 uint64_t ll;
144} CPU_DoubleU;
145
146/* CPU memory access without any memory or io remapping */
147
148/*
149 * the generic syntax for the memory accesses is:
150 *
151 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
152 *
153 * store: st{type}{size}{endian}_{access_type}(ptr, val)
154 *
155 * type is:
156 * (empty): integer access
157 * f : float access
158 *
159 * sign is:
160 * (empty): for floats or 32 bit size
161 * u : unsigned
162 * s : signed
163 *
164 * size is:
165 * b: 8 bits
166 * w: 16 bits
167 * l: 32 bits
168 * q: 64 bits
169 *
170 * endian is:
171 * (empty): target cpu endianness or 8 bit access
172 * r : reversed target cpu endianness (not implemented yet)
173 * be : big endian (not implemented yet)
174 * le : little endian (not implemented yet)
175 *
176 * access_type is:
177 * raw : host memory access
178 * user : user mode access using soft MMU
179 * kernel : kernel mode access using soft MMU
180 */
181#ifdef VBOX
182
183#if !defined(REMR3PHYSREADWRITE_DEFINED)
184#define REMR3PHYSREADWRITE_DEFINED
185/* Header sharing between vbox & qemu is rather ugly. */
186void remR3PhysRead(uint8_t *pbSrcPhys, void *pvDst, unsigned cb);
187uint8_t remR3PhysReadU8(uint8_t *pbSrcPhys);
188int8_t remR3PhysReadS8(uint8_t *pbSrcPhys);
189uint16_t remR3PhysReadU16(uint8_t *pbSrcPhys);
190int16_t remR3PhysReadS16(uint8_t *pbSrcPhys);
191uint32_t remR3PhysReadU32(uint8_t *pbSrcPhys);
192int32_t remR3PhysReadS32(uint8_t *pbSrcPhys);
193uint64_t remR3PhysReadU64(uint8_t *pbSrcPhys);
194int64_t remR3PhysReadS64(uint8_t *pbSrcPhys);
195void remR3PhysWrite(uint8_t *pbDstPhys, const void *pvSrc, unsigned cb);
196void remR3PhysWriteU8(uint8_t *pbDstPhys, uint8_t val);
197void remR3PhysWriteU16(uint8_t *pbDstPhys, uint16_t val);
198void remR3PhysWriteU32(uint8_t *pbDstPhys, uint32_t val);
199void remR3PhysWriteU64(uint8_t *pbDstPhys, uint64_t val);
200# ifdef PGM_DYNAMIC_RAM_ALLOC
201void *remR3GCPhys2HCVirt(void *env, target_ulong addr);
202target_ulong remR3HCVirt2GCPhys(void *env, void *addr);
203void remR3GrowDynRange(unsigned long physaddr);
204# endif
205#endif
206
207static inline int ldub_p(void *ptr)
208{
209 return remR3PhysReadU8(ptr);
210}
211
212static inline int ldsb_p(void *ptr)
213{
214 return remR3PhysReadS8(ptr);
215}
216
217static inline void stb_p(void *ptr, int v)
218{
219 remR3PhysWriteU8(ptr, v);
220}
221
222static inline int lduw_le_p(void *ptr)
223{
224 return remR3PhysReadU16(ptr);
225}
226
227static inline int ldsw_le_p(void *ptr)
228{
229 return remR3PhysReadS16(ptr);
230}
231
232static inline void stw_le_p(void *ptr, int v)
233{
234 remR3PhysWriteU16(ptr, v);
235}
236
237static inline int ldl_le_p(void *ptr)
238{
239 return remR3PhysReadU32(ptr);
240}
241
242static inline void stl_le_p(void *ptr, int v)
243{
244 remR3PhysWriteU32(ptr, v);
245}
246
247static inline void stq_le_p(void *ptr, uint64_t v)
248{
249 remR3PhysWriteU64(ptr, v);
250}
251
252static inline uint64_t ldq_le_p(void *ptr)
253{
254 return remR3PhysReadU64(ptr);
255}
256
257/* float access */
258
259static inline float32 ldfl_le_p(void *ptr)
260{
261 union {
262 float32 f;
263 uint32_t i;
264 } u;
265 u.i = ldl_le_p(ptr);
266 return u.f;
267}
268
269static inline void stfl_le_p(void *ptr, float32 v)
270{
271 union {
272 float32 f;
273 uint32_t i;
274 } u;
275 u.f = v;
276 stl_le_p(ptr, u.i);
277}
278
279static inline float64 ldfq_le_p(void *ptr)
280{
281 CPU_DoubleU u;
282 u.l.lower = ldl_le_p(ptr);
283 u.l.upper = ldl_le_p(ptr + 4);
284 return u.d;
285}
286
287static inline void stfq_le_p(void *ptr, float64 v)
288{
289 CPU_DoubleU u;
290 u.d = v;
291 stl_le_p(ptr, u.l.lower);
292 stl_le_p(ptr + 4, u.l.upper);
293}
294
295#else /* !VBOX */
296
297static inline int ldub_p(void *ptr)
298{
299 return *(uint8_t *)ptr;
300}
301
302static inline int ldsb_p(void *ptr)
303{
304 return *(int8_t *)ptr;
305}
306
307static inline void stb_p(void *ptr, int v)
308{
309 *(uint8_t *)ptr = v;
310}
311
312/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
313 kernel handles unaligned load/stores may give better results, but
314 it is a system wide setting : bad */
315#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
316
317/* conservative code for little endian unaligned accesses */
318static inline int lduw_le_p(void *ptr)
319{
320#ifdef __powerpc__
321 int val;
322 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
323 return val;
324#else
325 uint8_t *p = ptr;
326 return p[0] | (p[1] << 8);
327#endif
328}
329
330static inline int ldsw_le_p(void *ptr)
331{
332#ifdef __powerpc__
333 int val;
334 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
335 return (int16_t)val;
336#else
337 uint8_t *p = ptr;
338 return (int16_t)(p[0] | (p[1] << 8));
339#endif
340}
341
342static inline int ldl_le_p(void *ptr)
343{
344#ifdef __powerpc__
345 int val;
346 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
347 return val;
348#else
349 uint8_t *p = ptr;
350 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
351#endif
352}
353
354static inline uint64_t ldq_le_p(void *ptr)
355{
356 uint8_t *p = ptr;
357 uint32_t v1, v2;
358 v1 = ldl_le_p(p);
359 v2 = ldl_le_p(p + 4);
360 return v1 | ((uint64_t)v2 << 32);
361}
362
363static inline void stw_le_p(void *ptr, int v)
364{
365#ifdef __powerpc__
366 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
367#else
368 uint8_t *p = ptr;
369 p[0] = v;
370 p[1] = v >> 8;
371#endif
372}
373
374static inline void stl_le_p(void *ptr, int v)
375{
376#ifdef __powerpc__
377 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
378#else
379 uint8_t *p = ptr;
380 p[0] = v;
381 p[1] = v >> 8;
382 p[2] = v >> 16;
383 p[3] = v >> 24;
384#endif
385}
386
387static inline void stq_le_p(void *ptr, uint64_t v)
388{
389 uint8_t *p = ptr;
390 stl_le_p(p, (uint32_t)v);
391 stl_le_p(p + 4, v >> 32);
392}
393
394/* float access */
395
396static inline float32 ldfl_le_p(void *ptr)
397{
398 union {
399 float32 f;
400 uint32_t i;
401 } u;
402 u.i = ldl_le_p(ptr);
403 return u.f;
404}
405
406static inline void stfl_le_p(void *ptr, float32 v)
407{
408 union {
409 float32 f;
410 uint32_t i;
411 } u;
412 u.f = v;
413 stl_le_p(ptr, u.i);
414}
415
416static inline float64 ldfq_le_p(void *ptr)
417{
418 CPU_DoubleU u;
419 u.l.lower = ldl_le_p(ptr);
420 u.l.upper = ldl_le_p(ptr + 4);
421 return u.d;
422}
423
424static inline void stfq_le_p(void *ptr, float64 v)
425{
426 CPU_DoubleU u;
427 u.d = v;
428 stl_le_p(ptr, u.l.lower);
429 stl_le_p(ptr + 4, u.l.upper);
430}
431
432#else
433
434static inline int lduw_le_p(void *ptr)
435{
436 return *(uint16_t *)ptr;
437}
438
439static inline int ldsw_le_p(void *ptr)
440{
441 return *(int16_t *)ptr;
442}
443
444static inline int ldl_le_p(void *ptr)
445{
446 return *(uint32_t *)ptr;
447}
448
449static inline uint64_t ldq_le_p(void *ptr)
450{
451 return *(uint64_t *)ptr;
452}
453
454static inline void stw_le_p(void *ptr, int v)
455{
456 *(uint16_t *)ptr = v;
457}
458
459static inline void stl_le_p(void *ptr, int v)
460{
461 *(uint32_t *)ptr = v;
462}
463
464static inline void stq_le_p(void *ptr, uint64_t v)
465{
466 *(uint64_t *)ptr = v;
467}
468
469/* float access */
470
471static inline float32 ldfl_le_p(void *ptr)
472{
473 return *(float32 *)ptr;
474}
475
476static inline float64 ldfq_le_p(void *ptr)
477{
478 return *(float64 *)ptr;
479}
480
481static inline void stfl_le_p(void *ptr, float32 v)
482{
483 *(float32 *)ptr = v;
484}
485
486static inline void stfq_le_p(void *ptr, float64 v)
487{
488 *(float64 *)ptr = v;
489}
490#endif
491#endif /* !VBOX */
492
493#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
494
495static inline int lduw_be_p(void *ptr)
496{
497#if defined(__i386__)
498 int val;
499 asm volatile ("movzwl %1, %0\n"
500 "xchgb %b0, %h0\n"
501 : "=q" (val)
502 : "m" (*(uint16_t *)ptr));
503 return val;
504#else
505 uint8_t *b = (uint8_t *) ptr;
506 return ((b[0] << 8) | b[1]);
507#endif
508}
509
510static inline int ldsw_be_p(void *ptr)
511{
512#if defined(__i386__)
513 int val;
514 asm volatile ("movzwl %1, %0\n"
515 "xchgb %b0, %h0\n"
516 : "=q" (val)
517 : "m" (*(uint16_t *)ptr));
518 return (int16_t)val;
519#else
520 uint8_t *b = (uint8_t *) ptr;
521 return (int16_t)((b[0] << 8) | b[1]);
522#endif
523}
524
525static inline int ldl_be_p(void *ptr)
526{
527#if defined(__i386__) || defined(__x86_64__)
528 int val;
529 asm volatile ("movl %1, %0\n"
530 "bswap %0\n"
531 : "=r" (val)
532 : "m" (*(uint32_t *)ptr));
533 return val;
534#else
535 uint8_t *b = (uint8_t *) ptr;
536 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
537#endif
538}
539
540static inline uint64_t ldq_be_p(void *ptr)
541{
542 uint32_t a,b;
543 a = ldl_be_p(ptr);
544 b = ldl_be_p(ptr+4);
545 return (((uint64_t)a<<32)|b);
546}
547
548static inline void stw_be_p(void *ptr, int v)
549{
550#if defined(__i386__)
551 asm volatile ("xchgb %b0, %h0\n"
552 "movw %w0, %1\n"
553 : "=q" (v)
554 : "m" (*(uint16_t *)ptr), "0" (v));
555#else
556 uint8_t *d = (uint8_t *) ptr;
557 d[0] = v >> 8;
558 d[1] = v;
559#endif
560}
561
562static inline void stl_be_p(void *ptr, int v)
563{
564#if defined(__i386__) || defined(__x86_64__)
565 asm volatile ("bswap %0\n"
566 "movl %0, %1\n"
567 : "=r" (v)
568 : "m" (*(uint32_t *)ptr), "0" (v));
569#else
570 uint8_t *d = (uint8_t *) ptr;
571 d[0] = v >> 24;
572 d[1] = v >> 16;
573 d[2] = v >> 8;
574 d[3] = v;
575#endif
576}
577
578static inline void stq_be_p(void *ptr, uint64_t v)
579{
580 stl_be_p(ptr, v >> 32);
581 stl_be_p(ptr + 4, v);
582}
583
584/* float access */
585
586static inline float32 ldfl_be_p(void *ptr)
587{
588 union {
589 float32 f;
590 uint32_t i;
591 } u;
592 u.i = ldl_be_p(ptr);
593 return u.f;
594}
595
596static inline void stfl_be_p(void *ptr, float32 v)
597{
598 union {
599 float32 f;
600 uint32_t i;
601 } u;
602 u.f = v;
603 stl_be_p(ptr, u.i);
604}
605
606static inline float64 ldfq_be_p(void *ptr)
607{
608 CPU_DoubleU u;
609 u.l.upper = ldl_be_p(ptr);
610 u.l.lower = ldl_be_p(ptr + 4);
611 return u.d;
612}
613
614static inline void stfq_be_p(void *ptr, float64 v)
615{
616 CPU_DoubleU u;
617 u.d = v;
618 stl_be_p(ptr, u.l.upper);
619 stl_be_p(ptr + 4, u.l.lower);
620}
621
622#else
623
624static inline int lduw_be_p(void *ptr)
625{
626 return *(uint16_t *)ptr;
627}
628
629static inline int ldsw_be_p(void *ptr)
630{
631 return *(int16_t *)ptr;
632}
633
634static inline int ldl_be_p(void *ptr)
635{
636 return *(uint32_t *)ptr;
637}
638
639static inline uint64_t ldq_be_p(void *ptr)
640{
641 return *(uint64_t *)ptr;
642}
643
644static inline void stw_be_p(void *ptr, int v)
645{
646 *(uint16_t *)ptr = v;
647}
648
649static inline void stl_be_p(void *ptr, int v)
650{
651 *(uint32_t *)ptr = v;
652}
653
654static inline void stq_be_p(void *ptr, uint64_t v)
655{
656 *(uint64_t *)ptr = v;
657}
658
659/* float access */
660
661static inline float32 ldfl_be_p(void *ptr)
662{
663 return *(float32 *)ptr;
664}
665
666static inline float64 ldfq_be_p(void *ptr)
667{
668 return *(float64 *)ptr;
669}
670
671static inline void stfl_be_p(void *ptr, float32 v)
672{
673 *(float32 *)ptr = v;
674}
675
676static inline void stfq_be_p(void *ptr, float64 v)
677{
678 *(float64 *)ptr = v;
679}
680
681#endif
682
683/* target CPU memory access functions */
684#if defined(TARGET_WORDS_BIGENDIAN)
685#define lduw_p(p) lduw_be_p(p)
686#define ldsw_p(p) ldsw_be_p(p)
687#define ldl_p(p) ldl_be_p(p)
688#define ldq_p(p) ldq_be_p(p)
689#define ldfl_p(p) ldfl_be_p(p)
690#define ldfq_p(p) ldfq_be_p(p)
691#define stw_p(p, v) stw_be_p(p, v)
692#define stl_p(p, v) stl_be_p(p, v)
693#define stq_p(p, v) stq_be_p(p, v)
694#define stfl_p(p, v) stfl_be_p(p, v)
695#define stfq_p(p, v) stfq_be_p(p, v)
696#else
697#define lduw_p(p) lduw_le_p(p)
698#define ldsw_p(p) ldsw_le_p(p)
699#define ldl_p(p) ldl_le_p(p)
700#define ldq_p(p) ldq_le_p(p)
701#define ldfl_p(p) ldfl_le_p(p)
702#define ldfq_p(p) ldfq_le_p(p)
703#define stw_p(p, v) stw_le_p(p, v)
704#define stl_p(p, v) stl_le_p(p, v)
705#define stq_p(p, v) stq_le_p(p, v)
706#define stfl_p(p, v) stfl_le_p(p, v)
707#define stfq_p(p, v) stfq_le_p(p, v)
708#endif
709
710/* MMU memory access macros */
711
712#if defined(CONFIG_USER_ONLY)
713/* On some host systems the guest address space is reserved on the host.
714 * This allows the guest address space to be offset to a convenient location.
715 */
716//#define GUEST_BASE 0x20000000
717#define GUEST_BASE 0
718
719/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
720#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
721#define h2g(x) ((target_ulong)(x - GUEST_BASE))
722
723#define saddr(x) g2h(x)
724#define laddr(x) g2h(x)
725
726#else /* !CONFIG_USER_ONLY */
727/* NOTE: we use double casts if pointers and target_ulong have
728 different sizes */
729#define saddr(x) (uint8_t *)(long)(x)
730#define laddr(x) (uint8_t *)(long)(x)
731#endif
732
733#define ldub_raw(p) ldub_p(laddr((p)))
734#define ldsb_raw(p) ldsb_p(laddr((p)))
735#define lduw_raw(p) lduw_p(laddr((p)))
736#define ldsw_raw(p) ldsw_p(laddr((p)))
737#define ldl_raw(p) ldl_p(laddr((p)))
738#define ldq_raw(p) ldq_p(laddr((p)))
739#define ldfl_raw(p) ldfl_p(laddr((p)))
740#define ldfq_raw(p) ldfq_p(laddr((p)))
741#define stb_raw(p, v) stb_p(saddr((p)), v)
742#define stw_raw(p, v) stw_p(saddr((p)), v)
743#define stl_raw(p, v) stl_p(saddr((p)), v)
744#define stq_raw(p, v) stq_p(saddr((p)), v)
745#define stfl_raw(p, v) stfl_p(saddr((p)), v)
746#define stfq_raw(p, v) stfq_p(saddr((p)), v)
747
748
749#if defined(CONFIG_USER_ONLY)
750
751/* if user mode, no other memory access functions */
752#define ldub(p) ldub_raw(p)
753#define ldsb(p) ldsb_raw(p)
754#define lduw(p) lduw_raw(p)
755#define ldsw(p) ldsw_raw(p)
756#define ldl(p) ldl_raw(p)
757#define ldq(p) ldq_raw(p)
758#define ldfl(p) ldfl_raw(p)
759#define ldfq(p) ldfq_raw(p)
760#define stb(p, v) stb_raw(p, v)
761#define stw(p, v) stw_raw(p, v)
762#define stl(p, v) stl_raw(p, v)
763#define stq(p, v) stq_raw(p, v)
764#define stfl(p, v) stfl_raw(p, v)
765#define stfq(p, v) stfq_raw(p, v)
766
767#define ldub_code(p) ldub_raw(p)
768#define ldsb_code(p) ldsb_raw(p)
769#define lduw_code(p) lduw_raw(p)
770#define ldsw_code(p) ldsw_raw(p)
771#define ldl_code(p) ldl_raw(p)
772
773#define ldub_kernel(p) ldub_raw(p)
774#define ldsb_kernel(p) ldsb_raw(p)
775#define lduw_kernel(p) lduw_raw(p)
776#define ldsw_kernel(p) ldsw_raw(p)
777#define ldl_kernel(p) ldl_raw(p)
778#define ldfl_kernel(p) ldfl_raw(p)
779#define ldfq_kernel(p) ldfq_raw(p)
780#define stb_kernel(p, v) stb_raw(p, v)
781#define stw_kernel(p, v) stw_raw(p, v)
782#define stl_kernel(p, v) stl_raw(p, v)
783#define stq_kernel(p, v) stq_raw(p, v)
784#define stfl_kernel(p, v) stfl_raw(p, v)
785#define stfq_kernel(p, vt) stfq_raw(p, v)
786
787#endif /* defined(CONFIG_USER_ONLY) */
788
789/* page related stuff */
790
791#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
792#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
793#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
794
795/* ??? These should be the larger of unsigned long and target_ulong. */
796extern unsigned long qemu_real_host_page_size;
797extern unsigned long qemu_host_page_bits;
798extern unsigned long qemu_host_page_size;
799extern unsigned long qemu_host_page_mask;
800
801#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
802
803/* same as PROT_xxx */
804#define PAGE_READ 0x0001
805#define PAGE_WRITE 0x0002
806#define PAGE_EXEC 0x0004
807#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
808#define PAGE_VALID 0x0008
809/* original state of the write flag (used when tracking self-modifying
810 code */
811#define PAGE_WRITE_ORG 0x0010
812
813void page_dump(FILE *f);
814int page_get_flags(target_ulong address);
815void page_set_flags(target_ulong start, target_ulong end, int flags);
816void page_unprotect_range(target_ulong data, target_ulong data_size);
817
818#define SINGLE_CPU_DEFINES
819#ifdef SINGLE_CPU_DEFINES
820
821#if defined(TARGET_I386)
822
823#define CPUState CPUX86State
824#define cpu_init cpu_x86_init
825#define cpu_exec cpu_x86_exec
826#define cpu_gen_code cpu_x86_gen_code
827#define cpu_signal_handler cpu_x86_signal_handler
828
829#elif defined(TARGET_ARM)
830
831#define CPUState CPUARMState
832#define cpu_init cpu_arm_init
833#define cpu_exec cpu_arm_exec
834#define cpu_gen_code cpu_arm_gen_code
835#define cpu_signal_handler cpu_arm_signal_handler
836
837#elif defined(TARGET_SPARC)
838
839#define CPUState CPUSPARCState
840#define cpu_init cpu_sparc_init
841#define cpu_exec cpu_sparc_exec
842#define cpu_gen_code cpu_sparc_gen_code
843#define cpu_signal_handler cpu_sparc_signal_handler
844
845#elif defined(TARGET_PPC)
846
847#define CPUState CPUPPCState
848#define cpu_init cpu_ppc_init
849#define cpu_exec cpu_ppc_exec
850#define cpu_gen_code cpu_ppc_gen_code
851#define cpu_signal_handler cpu_ppc_signal_handler
852
853#elif defined(TARGET_M68K)
854#define CPUState CPUM68KState
855#define cpu_init cpu_m68k_init
856#define cpu_exec cpu_m68k_exec
857#define cpu_gen_code cpu_m68k_gen_code
858#define cpu_signal_handler cpu_m68k_signal_handler
859
860#elif defined(TARGET_MIPS)
861#define CPUState CPUMIPSState
862#define cpu_init cpu_mips_init
863#define cpu_exec cpu_mips_exec
864#define cpu_gen_code cpu_mips_gen_code
865#define cpu_signal_handler cpu_mips_signal_handler
866
867#elif defined(TARGET_SH4)
868#define CPUState CPUSH4State
869#define cpu_init cpu_sh4_init
870#define cpu_exec cpu_sh4_exec
871#define cpu_gen_code cpu_sh4_gen_code
872#define cpu_signal_handler cpu_sh4_signal_handler
873
874#else
875
876#error unsupported target CPU
877
878#endif
879
880#endif /* SINGLE_CPU_DEFINES */
881
882void cpu_dump_state(CPUState *env, FILE *f,
883 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
884 int flags);
885
886void cpu_abort(CPUState *env, const char *fmt, ...);
887extern CPUState *first_cpu;
888extern CPUState *cpu_single_env;
889extern int code_copy_enabled;
890
891#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
892#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
893#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
894#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
895#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
896#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
897#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
898
899#ifdef VBOX
900/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
901#define CPU_INTERRUPT_SINGLE_INSTR 0x0200
902/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
903#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0400
904/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
905#define CPU_INTERRUPT_RC 0x0800
906/** Exit current TB to process an external interrupt request (also in op.c!!) */
907#define CPU_INTERRUPT_EXTERNAL_EXIT 0x1000
908/** Exit current TB to process an external interrupt request (also in op.c!!) */
909#define CPU_INTERRUPT_EXTERNAL_HARD 0x2000
910/** Exit current TB to process an external interrupt request (also in op.c!!) */
911#define CPU_INTERRUPT_EXTERNAL_TIMER 0x4000
912/** Exit current TB to process an external interrupt request (also in op.c!!) */
913#define CPU_INTERRUPT_EXTERNAL_DMA 0x8000
914#endif /* VBOX */
915void cpu_interrupt(CPUState *s, int mask);
916void cpu_reset_interrupt(CPUState *env, int mask);
917
918int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
919int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
920void cpu_single_step(CPUState *env, int enabled);
921void cpu_reset(CPUState *s);
922
923/* Return the physical page corresponding to a virtual one. Use it
924 only for debugging because no protection checks are done. Return -1
925 if no page found. */
926target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
927
928#define CPU_LOG_TB_OUT_ASM (1 << 0)
929#define CPU_LOG_TB_IN_ASM (1 << 1)
930#define CPU_LOG_TB_OP (1 << 2)
931#define CPU_LOG_TB_OP_OPT (1 << 3)
932#define CPU_LOG_INT (1 << 4)
933#define CPU_LOG_EXEC (1 << 5)
934#define CPU_LOG_PCALL (1 << 6)
935#define CPU_LOG_IOPORT (1 << 7)
936#define CPU_LOG_TB_CPU (1 << 8)
937
938/* define log items */
939typedef struct CPULogItem {
940 int mask;
941 const char *name;
942 const char *help;
943} CPULogItem;
944
945extern CPULogItem cpu_log_items[];
946
947void cpu_set_log(int log_flags);
948void cpu_set_log_filename(const char *filename);
949int cpu_str_to_log_mask(const char *str);
950
951/* IO ports API */
952
953/* NOTE: as these functions may be even used when there is an isa
954 brige on non x86 targets, we always defined them */
955#ifndef NO_CPU_IO_DEFS
956void cpu_outb(CPUState *env, int addr, int val);
957void cpu_outw(CPUState *env, int addr, int val);
958void cpu_outl(CPUState *env, int addr, int val);
959int cpu_inb(CPUState *env, int addr);
960int cpu_inw(CPUState *env, int addr);
961int cpu_inl(CPUState *env, int addr);
962#endif
963
964/* memory API */
965
966#ifndef VBOX
967extern int phys_ram_size;
968extern int phys_ram_fd;
969extern int phys_ram_size;
970#else /* VBOX */
971extern RTGCPHYS phys_ram_size;
972/** This is required for bounds checking the phys_ram_dirty accesses. */
973extern uint32_t phys_ram_dirty_size;
974#endif /* VBOX */
975#if !defined(VBOX) || !defined(PGM_DYNAMIC_RAM_ALLOC)
976extern uint8_t *phys_ram_base;
977#endif
978extern uint8_t *phys_ram_dirty;
979
980/* physical memory access */
981#define TLB_INVALID_MASK (1 << 3)
982#define IO_MEM_SHIFT 4
983#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
984
985#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
986#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
987#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
988#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
989#if defined(VBOX) && defined(PGM_DYNAMIC_RAM_ALLOC)
990#define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
991#endif
992/* acts like a ROM when read and like a device when written. As an
993 exception, the write memory callback gets the ram offset instead of
994 the physical address */
995#define IO_MEM_ROMD (1)
996
997typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
998typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
999
1000void cpu_register_physical_memory(target_phys_addr_t start_addr,
1001 unsigned long size,
1002 unsigned long phys_offset);
1003uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
1004int cpu_register_io_memory(int io_index,
1005 CPUReadMemoryFunc **mem_read,
1006 CPUWriteMemoryFunc **mem_write,
1007 void *opaque);
1008CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
1009CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
1010
1011void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1012 int len, int is_write);
1013static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1014 uint8_t *buf, int len)
1015{
1016 cpu_physical_memory_rw(addr, buf, len, 0);
1017}
1018static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1019 const uint8_t *buf, int len)
1020{
1021 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1022}
1023uint32_t ldub_phys(target_phys_addr_t addr);
1024uint32_t lduw_phys(target_phys_addr_t addr);
1025uint32_t ldl_phys(target_phys_addr_t addr);
1026uint64_t ldq_phys(target_phys_addr_t addr);
1027void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1028void stb_phys(target_phys_addr_t addr, uint32_t val);
1029void stw_phys(target_phys_addr_t addr, uint32_t val);
1030void stl_phys(target_phys_addr_t addr, uint32_t val);
1031void stq_phys(target_phys_addr_t addr, uint64_t val);
1032
1033void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1034 const uint8_t *buf, int len);
1035int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1036 uint8_t *buf, int len, int is_write);
1037
1038#define VGA_DIRTY_FLAG 0x01
1039#define CODE_DIRTY_FLAG 0x02
1040
1041/* read dirty bit (return 0 or 1) */
1042static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1043{
1044#ifdef VBOX
1045 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1046 {
1047 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1048 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1049 return 0;
1050 }
1051#endif
1052 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1053}
1054
1055static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1056 int dirty_flags)
1057{
1058#ifdef VBOX
1059 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1060 {
1061 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1062 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1063 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1064 }
1065#endif
1066 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1067}
1068
1069static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1070{
1071#ifdef VBOX
1072 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1073 {
1074 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1075 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1076 return;
1077 }
1078#endif
1079 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1080}
1081
1082void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1083 int dirty_flags);
1084void cpu_tlb_update_dirty(CPUState *env);
1085
1086void dump_exec_info(FILE *f,
1087 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1088
1089/*******************************************/
1090/* host CPU ticks (if available) */
1091
1092#if defined(__powerpc__)
1093
1094static inline uint32_t get_tbl(void)
1095{
1096 uint32_t tbl;
1097 asm volatile("mftb %0" : "=r" (tbl));
1098 return tbl;
1099}
1100
1101static inline uint32_t get_tbu(void)
1102{
1103 uint32_t tbl;
1104 asm volatile("mftbu %0" : "=r" (tbl));
1105 return tbl;
1106}
1107
1108static inline int64_t cpu_get_real_ticks(void)
1109{
1110 uint32_t l, h, h1;
1111 /* NOTE: we test if wrapping has occurred */
1112 do {
1113 h = get_tbu();
1114 l = get_tbl();
1115 h1 = get_tbu();
1116 } while (h != h1);
1117 return ((int64_t)h << 32) | l;
1118}
1119
1120#elif defined(__i386__)
1121
1122static inline int64_t cpu_get_real_ticks(void)
1123{
1124 int64_t val;
1125 asm volatile ("rdtsc" : "=A" (val));
1126 return val;
1127}
1128
1129#elif defined(__x86_64__)
1130
1131static inline int64_t cpu_get_real_ticks(void)
1132{
1133 uint32_t low,high;
1134 int64_t val;
1135 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1136 val = high;
1137 val <<= 32;
1138 val |= low;
1139 return val;
1140}
1141
1142#elif defined(__ia64)
1143
1144static inline int64_t cpu_get_real_ticks(void)
1145{
1146 int64_t val;
1147 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1148 return val;
1149}
1150
1151#elif defined(__s390__)
1152
1153static inline int64_t cpu_get_real_ticks(void)
1154{
1155 int64_t val;
1156 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1157 return val;
1158}
1159
1160#elif defined(__sparc_v9__)
1161
1162static inline int64_t cpu_get_real_ticks (void)
1163{
1164#if defined(_LP64)
1165 uint64_t rval;
1166 asm volatile("rd %%tick,%0" : "=r"(rval));
1167 return rval;
1168#else
1169 union {
1170 uint64_t i64;
1171 struct {
1172 uint32_t high;
1173 uint32_t low;
1174 } i32;
1175 } rval;
1176 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1177 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1178 return rval.i64;
1179#endif
1180}
1181#else
1182/* The host CPU doesn't have an easily accessible cycle counter.
1183 Just return a monotonically increasing vlue. This will be totally wrong,
1184 but hopefully better than nothing. */
1185static inline int64_t cpu_get_real_ticks (void)
1186{
1187 static int64_t ticks = 0;
1188 return ticks++;
1189}
1190#endif
1191
1192/* profiling */
1193#ifdef CONFIG_PROFILER
1194static inline int64_t profile_getclock(void)
1195{
1196 return cpu_get_real_ticks();
1197}
1198
1199extern int64_t kqemu_time, kqemu_time_start;
1200extern int64_t qemu_time, qemu_time_start;
1201extern int64_t tlb_flush_time;
1202extern int64_t kqemu_exec_count;
1203extern int64_t dev_time;
1204extern int64_t kqemu_ret_int_count;
1205extern int64_t kqemu_ret_excp_count;
1206extern int64_t kqemu_ret_intr_count;
1207
1208#endif
1209
1210#ifdef VBOX
1211void tb_invalidate_virt(CPUState *env, uint32_t eip);
1212#endif /* VBOX */
1213
1214#endif /* CPU_ALL_H */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette