helper.c@ 1591

Last change on this file since 1591 was 1588, checked in by vboxsync, 18 years ago
Merged in http://linserv/vbox/changeset?old_path=trunk%2Fsrc%2Frecompiler&old=18834&new_path=trunk%2Fsrc%2Frecompiler&new=19696
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1	/*
2	* i386 helpers
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20	#ifdef VBOX
21	# include <VBox/err.h>
22	#endif
23	#include "exec.h"
24
25	//#define DEBUG_PCALL
26
27	#if 0
28	#define raise_exception_err(a, b)\
29	do {\
30	if (logfile)\
31	fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
32	(raise_exception_err)(a, b);\
33	} while (0)
34	#endif
35
36	const uint8_t parity_table[256] = {
37	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
38	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
40	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
41	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
42	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
44	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
45	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
46	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
48	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
52	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
56	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
57	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
58	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
59	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
61	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
64	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
66	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
68	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
69	};
70
71	/* modulo 17 table */
72	const uint8_t rclw_table[32] = {
73	0, 1, 2, 3, 4, 5, 6, 7,
74	8, 9,10,11,12,13,14,15,
75	16, 0, 1, 2, 3, 4, 5, 6,
76	7, 8, 9,10,11,12,13,14,
77	};
78
79	/* modulo 9 table */
80	const uint8_t rclb_table[32] = {
81	0, 1, 2, 3, 4, 5, 6, 7,
82	8, 0, 1, 2, 3, 4, 5, 6,
83	7, 8, 0, 1, 2, 3, 4, 5,
84	6, 7, 8, 0, 1, 2, 3, 4,
85	};
86
87	const CPU86_LDouble f15rk[7] =
88	{
89	0.00000000000000000000L,
90	1.00000000000000000000L,
91	3.14159265358979323851L, /pi/
92	0.30102999566398119523L, /lg2/
93	0.69314718055994530943L, /ln2/
94	1.44269504088896340739L, /l2e/
95	3.32192809488736234781L, /l2t/
96	};
97
98	/* thread support */
99
100	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
101
102	void cpu_lock(void)
103	{
104	spin_lock(&global_cpu_lock);
105	}
106
107	void cpu_unlock(void)
108	{
109	spin_unlock(&global_cpu_lock);
110	}
111
112	void cpu_loop_exit(void)
113	{
114	/* NOTE: the register at this point must be saved by hand because
115	longjmp restore them */
116	regs_to_env();
117	longjmp(env->jmp_env, 1);
118	}
119
120	/* return non zero if error */
121	static inline int load_segment(uint32_t e1_ptr, uint32_t e2_ptr,
122	int selector)
123	{
124	SegmentCache *dt;
125	int index;
126	target_ulong ptr;
127
128	if (selector & 0x4)
129	dt = &env->ldt;
130	else
131	dt = &env->gdt;
132	index = selector & ~7;
133	if ((index + 7) > dt->limit)
134	return -1;
135	ptr = dt->base + index;
136	*e1_ptr = ldl_kernel(ptr);
137	*e2_ptr = ldl_kernel(ptr + 4);
138	return 0;
139	}
140
141	static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
142	{
143	unsigned int limit;
144	limit = (e1 & 0xffff) \| (e2 & 0x000f0000);
145	if (e2 & DESC_G_MASK)
146	limit = (limit << 12) \| 0xfff;
147	return limit;
148	}
149
150	static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
151	{
152	return ((e1 >> 16) \| ((e2 & 0xff) << 16) \| (e2 & 0xff000000));
153	}
154
155	static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
156	{
157	sc->base = get_seg_base(e1, e2);
158	sc->limit = get_seg_limit(e1, e2);
159	sc->flags = e2;
160	}
161
162	/* init the segment cache in vm86 mode. */
163	static inline void load_seg_vm(int seg, int selector)
164	{
165	selector &= 0xffff;
166	cpu_x86_load_seg_cache(env, seg, selector,
167	(selector << 4), 0xffff, 0);
168	}
169
170	static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
171	uint32_t *esp_ptr, int dpl)
172	{
173	int type, index, shift;
174
175	#if 0
176	{
177	int i;
178	printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
179	for(i=0;i<env->tr.limit;i++) {
180	printf("%02x ", env->tr.base[i]);
181	if ((i & 7) == 7) printf("\n");
182	}
183	printf("\n");
184	}
185	#endif
186
187	if (!(env->tr.flags & DESC_P_MASK))
188	cpu_abort(env, "invalid tss");
189	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
190	if ((type & 7) != 1)
191	cpu_abort(env, "invalid tss type %d", type);
192	shift = type >> 3;
193	index = (dpl * 4 + 2) << shift;
194	if (index + (4 << shift) - 1 > env->tr.limit)
195	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
196	if (shift == 0) {
197	*esp_ptr = lduw_kernel(env->tr.base + index);
198	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
199	} else {
200	*esp_ptr = ldl_kernel(env->tr.base + index);
201	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
202	}
203	}
204
205	/* XXX: merge with load_seg() */
206	static void tss_load_seg(int seg_reg, int selector)
207	{
208	uint32_t e1, e2;
209	int rpl, dpl, cpl;
210
211	if ((selector & 0xfffc) != 0) {
212	if (load_segment(&e1, &e2, selector) != 0)
213	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
214	if (!(e2 & DESC_S_MASK))
215	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
216	rpl = selector & 3;
217	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
218	cpl = env->hflags & HF_CPL_MASK;
219	if (seg_reg == R_CS) {
220	if (!(e2 & DESC_CS_MASK))
221	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
222	/* XXX: is it correct ? */
223	if (dpl != rpl)
224	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
225	if ((e2 & DESC_C_MASK) && dpl > rpl)
226	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
227	} else if (seg_reg == R_SS) {
228	/* SS must be writable data */
229	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
230	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231	if (dpl != cpl \|\| dpl != rpl)
232	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
233	} else {
234	/* not readable code */
235	if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
236	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
237	/* if data or non conforming code, checks the rights */
238	if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
239	if (dpl < cpl \|\| dpl < rpl)
240	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
241	}
242	}
243	if (!(e2 & DESC_P_MASK))
244	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
245	cpu_x86_load_seg_cache(env, seg_reg, selector,
246	get_seg_base(e1, e2),
247	get_seg_limit(e1, e2),
248	e2);
249	} else {
250	if (seg_reg == R_SS \|\| seg_reg == R_CS)
251	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
252	}
253	}
254
255	#define SWITCH_TSS_JMP 0
256	#define SWITCH_TSS_IRET 1
257	#define SWITCH_TSS_CALL 2
258
259	/* XXX: restore CPU state in registers (PowerPC case) */
260	static void switch_tss(int tss_selector,
261	uint32_t e1, uint32_t e2, int source,
262	uint32_t next_eip)
263	{
264	int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
265	target_ulong tss_base;
266	uint32_t new_regs[8], new_segs[6];
267	uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
268	uint32_t old_eflags, eflags_mask;
269	SegmentCache *dt;
270	int index;
271	target_ulong ptr;
272
273	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
274	#ifdef DEBUG_PCALL
275	if (loglevel & CPU_LOG_PCALL)
276	fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
277	#endif
278
279	#if defined(VBOX) && defined(DEBUG)
280	printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
281	#endif
282
283	/* if task gate, we read the TSS segment and we load it */
284	if (type == 5) {
285	if (!(e2 & DESC_P_MASK))
286	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
287	tss_selector = e1 >> 16;
288	if (tss_selector & 4)
289	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
290	if (load_segment(&e1, &e2, tss_selector) != 0)
291	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
292	if (e2 & DESC_S_MASK)
293	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
294	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
295	if ((type & 7) != 1)
296	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
297	}
298
299	if (!(e2 & DESC_P_MASK))
300	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
301
302	if (type & 8)
303	tss_limit_max = 103;
304	else
305	tss_limit_max = 43;
306	tss_limit = get_seg_limit(e1, e2);
307	tss_base = get_seg_base(e1, e2);
308	if ((tss_selector & 4) != 0 \|\|
309	tss_limit < tss_limit_max)
310	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
311	old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
312	if (old_type & 8)
313	old_tss_limit_max = 103;
314	else
315	old_tss_limit_max = 43;
316
317	/* read all the registers from the new TSS */
318	if (type & 8) {
319	/* 32 bit */
320	new_cr3 = ldl_kernel(tss_base + 0x1c);
321	new_eip = ldl_kernel(tss_base + 0x20);
322	new_eflags = ldl_kernel(tss_base + 0x24);
323	for(i = 0; i < 8; i++)
324	new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
325	for(i = 0; i < 6; i++)
326	new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
327	new_ldt = lduw_kernel(tss_base + 0x60);
328	new_trap = ldl_kernel(tss_base + 0x64);
329	} else {
330	/* 16 bit */
331	new_cr3 = 0;
332	new_eip = lduw_kernel(tss_base + 0x0e);
333	new_eflags = lduw_kernel(tss_base + 0x10);
334	for(i = 0; i < 8; i++)
335	new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) \| 0xffff0000;
336	for(i = 0; i < 4; i++)
337	new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
338	new_ldt = lduw_kernel(tss_base + 0x2a);
339	new_segs[R_FS] = 0;
340	new_segs[R_GS] = 0;
341	new_trap = 0;
342	}
343
344	/* NOTE: we must avoid memory exceptions during the task switch,
345	so we make dummy accesses before */
346	/* XXX: it can still fail in some cases, so a bigger hack is
347	necessary to valid the TLB after having done the accesses */
348
349	v1 = ldub_kernel(env->tr.base);
350	v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
351	stb_kernel(env->tr.base, v1);
352	stb_kernel(env->tr.base + old_tss_limit_max, v2);
353
354	/* clear busy bit (it is restartable) */
355	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_IRET) {
356	target_ulong ptr;
357	uint32_t e2;
358	ptr = env->gdt.base + (env->tr.selector & ~7);
359	e2 = ldl_kernel(ptr + 4);
360	e2 &= ~DESC_TSS_BUSY_MASK;
361	stl_kernel(ptr + 4, e2);
362	}
363	old_eflags = compute_eflags();
364	if (source == SWITCH_TSS_IRET)
365	old_eflags &= ~NT_MASK;
366
367	/* save the current state in the old TSS */
368	if (type & 8) {
369	/* 32 bit */
370	stl_kernel(env->tr.base + 0x20, next_eip);
371	stl_kernel(env->tr.base + 0x24, old_eflags);
372	stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
373	stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
374	stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
375	stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
376	stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
377	stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
378	stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
379	stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
380	for(i = 0; i < 6; i++)
381	stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
382	#if defined(VBOX) && defined(DEBUG)
383	printf("TSS 32 bits switch\n");
384	printf("Saving CS=%08X\n", env->segs[R_CS].selector);
385	#endif
386	} else {
387	/* 16 bit */
388	stw_kernel(env->tr.base + 0x0e, next_eip);
389	stw_kernel(env->tr.base + 0x10, old_eflags);
390	stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
391	stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
392	stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
393	stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
394	stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
395	stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
396	stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
397	stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
398	for(i = 0; i < 4; i++)
399	stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
400	}
401
402	/* now if an exception occurs, it will occurs in the next task
403	context */
404
405	if (source == SWITCH_TSS_CALL) {
406	stw_kernel(tss_base, env->tr.selector);
407	new_eflags \|= NT_MASK;
408	}
409
410	/* set busy bit */
411	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_CALL) {
412	target_ulong ptr;
413	uint32_t e2;
414	ptr = env->gdt.base + (tss_selector & ~7);
415	e2 = ldl_kernel(ptr + 4);
416	e2 \|= DESC_TSS_BUSY_MASK;
417	stl_kernel(ptr + 4, e2);
418	}
419
420	/* set the new CPU state */
421	/* from this point, any exception which occurs can give problems */
422	env->cr[0] \|= CR0_TS_MASK;
423	env->hflags \|= HF_TS_MASK;
424	env->tr.selector = tss_selector;
425	env->tr.base = tss_base;
426	env->tr.limit = tss_limit;
427	env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
428
429	if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
430	cpu_x86_update_cr3(env, new_cr3);
431	}
432
433	/* load all registers without an exception, then reload them with
434	possible exception */
435	env->eip = new_eip;
436	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \|
437	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK;
438	if (!(type & 8))
439	eflags_mask &= 0xffff;
440	load_eflags(new_eflags, eflags_mask);
441	/* XXX: what to do in 16 bit case ? */
442	EAX = new_regs[0];
443	ECX = new_regs[1];
444	EDX = new_regs[2];
445	EBX = new_regs[3];
446	ESP = new_regs[4];
447	EBP = new_regs[5];
448	ESI = new_regs[6];
449	EDI = new_regs[7];
450	if (new_eflags & VM_MASK) {
451	for(i = 0; i < 6; i++)
452	load_seg_vm(i, new_segs[i]);
453	/* in vm86, CPL is always 3 */
454	cpu_x86_set_cpl(env, 3);
455	} else {
456	/* CPL is set the RPL of CS */
457	cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
458	/* first just selectors as the rest may trigger exceptions */
459	for(i = 0; i < 6; i++)
460	cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
461	}
462
463	env->ldt.selector = new_ldt & ~4;
464	env->ldt.base = 0;
465	env->ldt.limit = 0;
466	env->ldt.flags = 0;
467
468	/* load the LDT */
469	if (new_ldt & 4)
470	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
471
472	if ((new_ldt & 0xfffc) != 0) {
473	dt = &env->gdt;
474	index = new_ldt & ~7;
475	if ((index + 7) > dt->limit)
476	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
477	ptr = dt->base + index;
478	e1 = ldl_kernel(ptr);
479	e2 = ldl_kernel(ptr + 4);
480	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
481	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
482	if (!(e2 & DESC_P_MASK))
483	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
484	load_seg_cache_raw_dt(&env->ldt, e1, e2);
485	}
486
487	/* load the segments */
488	if (!(new_eflags & VM_MASK)) {
489	tss_load_seg(R_CS, new_segs[R_CS]);
490	tss_load_seg(R_SS, new_segs[R_SS]);
491	tss_load_seg(R_ES, new_segs[R_ES]);
492	tss_load_seg(R_DS, new_segs[R_DS]);
493	tss_load_seg(R_FS, new_segs[R_FS]);
494	tss_load_seg(R_GS, new_segs[R_GS]);
495	}
496
497	/* check that EIP is in the CS segment limits */
498	if (new_eip > env->segs[R_CS].limit) {
499	/* XXX: different exception if CALL ? */
500	raise_exception_err(EXCP0D_GPF, 0);
501	}
502	}
503
504	/* check if Port I/O is allowed in TSS */
505	static inline void check_io(int addr, int size)
506	{
507	int io_offset, val, mask;
508
509	/* TSS must be a valid 32 bit one */
510	if (!(env->tr.flags & DESC_P_MASK) \|\|
511	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
512	env->tr.limit < 103)
513	goto fail;
514	io_offset = lduw_kernel(env->tr.base + 0x66);
515	io_offset += (addr >> 3);
516	/* Note: the check needs two bytes */
517	if ((io_offset + 1) > env->tr.limit)
518	goto fail;
519	val = lduw_kernel(env->tr.base + io_offset);
520	val >>= (addr & 7);
521	mask = (1 << size) - 1;
522	/* all bits must be zero to allow the I/O */
523	if ((val & mask) != 0) {
524	fail:
525	raise_exception_err(EXCP0D_GPF, 0);
526	}
527	}
528
529	void check_iob_T0(void)
530	{
531	check_io(T0, 1);
532	}
533
534	void check_iow_T0(void)
535	{
536	check_io(T0, 2);
537	}
538
539	void check_iol_T0(void)
540	{
541	check_io(T0, 4);
542	}
543
544	void check_iob_DX(void)
545	{
546	check_io(EDX & 0xffff, 1);
547	}
548
549	void check_iow_DX(void)
550	{
551	check_io(EDX & 0xffff, 2);
552	}
553
554	void check_iol_DX(void)
555	{
556	check_io(EDX & 0xffff, 4);
557	}
558
559	static inline unsigned int get_sp_mask(unsigned int e2)
560	{
561	if (e2 & DESC_B_MASK)
562	return 0xffffffff;
563	else
564	return 0xffff;
565	}
566
567	#ifdef TARGET_X86_64
568	#define SET_ESP(val, sp_mask)\
569	do {\
570	if ((sp_mask) == 0xffff)\
571	ESP = (ESP & ~0xffff) \| ((val) & 0xffff);\
572	else if ((sp_mask) == 0xffffffffLL)\
573	ESP = (uint32_t)(val);\
574	else\
575	ESP = (val);\
576	} while (0)
577	#else
578	#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) \| ((val) & (sp_mask))
579	#endif
580
581	/* XXX: add a is_user flag to have proper security support */
582	#define PUSHW(ssp, sp, sp_mask, val)\
583	{\
584	sp -= 2;\
585	stw_kernel((ssp) + (sp & (sp_mask)), (val));\
586	}
587
588	#define PUSHL(ssp, sp, sp_mask, val)\
589	{\
590	sp -= 4;\
591	stl_kernel((ssp) + (sp & (sp_mask)), (val));\
592	}
593
594	#define POPW(ssp, sp, sp_mask, val)\
595	{\
596	val = lduw_kernel((ssp) + (sp & (sp_mask)));\
597	sp += 2;\
598	}
599
600	#define POPL(ssp, sp, sp_mask, val)\
601	{\
602	val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
603	sp += 4;\
604	}
605
606	/* protected mode interrupt */
607	static void do_interrupt_protected(int intno, int is_int, int error_code,
608	unsigned int next_eip, int is_hw)
609	{
610	SegmentCache *dt;
611	target_ulong ptr, ssp;
612	int type, dpl, selector, ss_dpl, cpl;
613	int has_error_code, new_stack, shift;
614	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
615	uint32_t old_eip, sp_mask;
616
617	#ifdef VBOX
618	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
619	cpu_loop_exit();
620	#endif
621
622	has_error_code = 0;
623	if (!is_int && !is_hw) {
624	switch(intno) {
625	case 8:
626	case 10:
627	case 11:
628	case 12:
629	case 13:
630	case 14:
631	case 17:
632	has_error_code = 1;
633	break;
634	}
635	}
636	if (is_int)
637	old_eip = next_eip;
638	else
639	old_eip = env->eip;
640
641	dt = &env->idt;
642	if (intno * 8 + 7 > dt->limit)
643	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
644	ptr = dt->base + intno * 8;
645	e1 = ldl_kernel(ptr);
646	e2 = ldl_kernel(ptr + 4);
647	/* check gate type */
648	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
649	switch(type) {
650	case 5: /* task gate */
651	/* must do that check here to return the correct error code */
652	if (!(e2 & DESC_P_MASK))
653	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
654	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
655	if (has_error_code) {
656	int type;
657	uint32_t mask;
658	/* push the error code */
659	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
660	shift = type >> 3;
661	if (env->segs[R_SS].flags & DESC_B_MASK)
662	mask = 0xffffffff;
663	else
664	mask = 0xffff;
665	esp = (ESP - (2 << shift)) & mask;
666	ssp = env->segs[R_SS].base + esp;
667	if (shift)
668	stl_kernel(ssp, error_code);
669	else
670	stw_kernel(ssp, error_code);
671	SET_ESP(esp, mask);
672	}
673	return;
674	case 6: /* 286 interrupt gate */
675	case 7: /* 286 trap gate */
676	case 14: /* 386 interrupt gate */
677	case 15: /* 386 trap gate */
678	break;
679	default:
680	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
681	break;
682	}
683	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
684	cpl = env->hflags & HF_CPL_MASK;
685	/* check privledge if software int */
686	if (is_int && dpl < cpl)
687	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
688	/* check valid bit */
689	if (!(e2 & DESC_P_MASK))
690	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
691	selector = e1 >> 16;
692	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
693	if ((selector & 0xfffc) == 0)
694	raise_exception_err(EXCP0D_GPF, 0);
695
696	if (load_segment(&e1, &e2, selector) != 0)
697	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
698	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
699	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
700	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
701	if (dpl > cpl)
702	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
703	if (!(e2 & DESC_P_MASK))
704	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
705	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
706	/* to inner priviledge */
707	get_ss_esp_from_tss(&ss, &esp, dpl);
708	if ((ss & 0xfffc) == 0)
709	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
710	if ((ss & 3) != dpl)
711	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
712	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
713	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
714	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
715	if (ss_dpl != dpl)
716	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
717	if (!(ss_e2 & DESC_S_MASK) \|\|
718	(ss_e2 & DESC_CS_MASK) \|\|
719	!(ss_e2 & DESC_W_MASK))
720	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
721	if (!(ss_e2 & DESC_P_MASK))
722	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
723	new_stack = 1;
724	sp_mask = get_sp_mask(ss_e2);
725	ssp = get_seg_base(ss_e1, ss_e2);
726	#if defined(VBOX) && defined(DEBUG)
727	printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
728	#endif
729	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
730	/* to same priviledge */
731	if (env->eflags & VM_MASK)
732	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
733	new_stack = 0;
734	sp_mask = get_sp_mask(env->segs[R_SS].flags);
735	ssp = env->segs[R_SS].base;
736	esp = ESP;
737	dpl = cpl;
738	} else {
739	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
740	new_stack = 0; /* avoid warning */
741	sp_mask = 0; /* avoid warning */
742	ssp = 0; /* avoid warning */
743	esp = 0; /* avoid warning */
744	}
745
746	shift = type >> 3;
747
748	#if 0
749	/* XXX: check that enough room is available */
750	push_size = 6 + (new_stack << 2) + (has_error_code << 1);
751	if (env->eflags & VM_MASK)
752	push_size += 8;
753	push_size <<= shift;
754	#endif
755	if (shift == 1) {
756	if (new_stack) {
757	if (env->eflags & VM_MASK) {
758	PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
759	PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
760	PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
761	PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
762	}
763	PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
764	PUSHL(ssp, esp, sp_mask, ESP);
765	}
766	PUSHL(ssp, esp, sp_mask, compute_eflags());
767	PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
768	PUSHL(ssp, esp, sp_mask, old_eip);
769	if (has_error_code) {
770	PUSHL(ssp, esp, sp_mask, error_code);
771	}
772	} else {
773	if (new_stack) {
774	if (env->eflags & VM_MASK) {
775	PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
776	PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
777	PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
778	PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
779	}
780	PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
781	PUSHW(ssp, esp, sp_mask, ESP);
782	}
783	PUSHW(ssp, esp, sp_mask, compute_eflags());
784	PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
785	PUSHW(ssp, esp, sp_mask, old_eip);
786	if (has_error_code) {
787	PUSHW(ssp, esp, sp_mask, error_code);
788	}
789	}
790
791	if (new_stack) {
792	if (env->eflags & VM_MASK) {
793	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
794	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
795	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
796	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
797	}
798	ss = (ss & ~3) \| dpl;
799	cpu_x86_load_seg_cache(env, R_SS, ss,
800	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
801	}
802	SET_ESP(esp, sp_mask);
803
804	selector = (selector & ~3) \| dpl;
805	cpu_x86_load_seg_cache(env, R_CS, selector,
806	get_seg_base(e1, e2),
807	get_seg_limit(e1, e2),
808	e2);
809	cpu_x86_set_cpl(env, dpl);
810	env->eip = offset;
811
812	/* interrupt gate clear IF mask */
813	if ((type & 1) == 0) {
814	env->eflags &= ~IF_MASK;
815	}
816	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
817	}
818
819	#ifdef VBOX
820
821	/* check if VME interrupt redirection is enabled in TSS */
822	static inline bool is_vme_irq_redirected(int intno)
823	{
824	int io_offset, intredir_offset;
825	unsigned char val, mask;
826
827	/* TSS must be a valid 32 bit one */
828	if (!(env->tr.flags & DESC_P_MASK) \|\|
829	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
830	env->tr.limit < 103)
831	goto fail;
832	io_offset = lduw_kernel(env->tr.base + 0x66);
833	/* the virtual interrupt redirection bitmap is located below the io bitmap */
834	intredir_offset = io_offset - 0x20;
835
836	intredir_offset += (intno >> 3);
837	if ((intredir_offset) > env->tr.limit)
838	goto fail;
839
840	val = ldub_kernel(env->tr.base + intredir_offset);
841	mask = 1 << (unsigned char)(intno & 7);
842
843	/* bit set means no redirection. */
844	if ((val & mask) != 0) {
845	return false;
846	}
847	return true;
848
849	fail:
850	raise_exception_err(EXCP0D_GPF, 0);
851	return true;
852	}
853
854	/* V86 mode software interrupt with CR4.VME=1 */
855	static void do_soft_interrupt_vme(int intno, int error_code, unsigned int next_eip)
856	{
857	target_ulong ptr, ssp;
858	int selector;
859	uint32_t offset, esp;
860	uint32_t old_cs, old_eflags;
861	uint32_t iopl;
862
863	iopl = ((env->eflags >> IOPL_SHIFT) & 3);
864
865	if (!is_vme_irq_redirected(intno))
866	{
867	if (iopl == 3)
868	/* normal protected mode handler call */
869	return do_interrupt_protected(intno, 1, error_code, next_eip, 0);
870	else
871	raise_exception_err(EXCP0D_GPF, 0);
872	}
873
874	/* virtual mode idt is at linear address 0 */
875	ptr = 0 + intno * 4;
876	offset = lduw_kernel(ptr);
877	selector = lduw_kernel(ptr + 2);
878	esp = ESP;
879	ssp = env->segs[R_SS].base;
880	old_cs = env->segs[R_CS].selector;
881
882	old_eflags = compute_eflags();
883	if (iopl < 3)
884	{
885	/* copy VIF into IF and set IOPL to 3 */
886	if (env->eflags & VIF_MASK)
887	old_eflags \|= IF_MASK;
888	else
889	old_eflags &= ~IF_MASK;
890
891	old_eflags \|= (3 << IOPL_SHIFT);
892	}
893
894	/* XXX: use SS segment size ? */
895	PUSHW(ssp, esp, 0xffff, old_eflags);
896	PUSHW(ssp, esp, 0xffff, old_cs);
897	PUSHW(ssp, esp, 0xffff, next_eip);
898
899	/* update processor state */
900	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
901	env->eip = offset;
902	env->segs[R_CS].selector = selector;
903	env->segs[R_CS].base = (selector << 4);
904	env->eflags &= ~(TF_MASK \| RF_MASK);
905
906	if (iopl < 3)
907	env->eflags &= ~IF_MASK;
908	else
909	env->eflags &= ~VIF_MASK;
910	}
911	#endif /* VBOX */
912
913	#ifdef TARGET_X86_64
914
915	#define PUSHQ(sp, val)\
916	{\
917	sp -= 8;\
918	stq_kernel(sp, (val));\
919	}
920
921	#define POPQ(sp, val)\
922	{\
923	val = ldq_kernel(sp);\
924	sp += 8;\
925	}
926
927	static inline target_ulong get_rsp_from_tss(int level)
928	{
929	int index;
930
931	#if 0
932	printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
933	env->tr.base, env->tr.limit);
934	#endif
935
936	if (!(env->tr.flags & DESC_P_MASK))
937	cpu_abort(env, "invalid tss");
938	index = 8 * level + 4;
939	if ((index + 7) > env->tr.limit)
940	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
941	return ldq_kernel(env->tr.base + index);
942	}
943
944	/* 64 bit interrupt */
945	static void do_interrupt64(int intno, int is_int, int error_code,
946	target_ulong next_eip, int is_hw)
947	{
948	SegmentCache *dt;
949	target_ulong ptr;
950	int type, dpl, selector, cpl, ist;
951	int has_error_code, new_stack;
952	uint32_t e1, e2, e3, ss;
953	target_ulong old_eip, esp, offset;
954
955	has_error_code = 0;
956	if (!is_int && !is_hw) {
957	switch(intno) {
958	case 8:
959	case 10:
960	case 11:
961	case 12:
962	case 13:
963	case 14:
964	case 17:
965	has_error_code = 1;
966	break;
967	}
968	}
969	if (is_int)
970	old_eip = next_eip;
971	else
972	old_eip = env->eip;
973
974	dt = &env->idt;
975	if (intno * 16 + 15 > dt->limit)
976	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
977	ptr = dt->base + intno * 16;
978	e1 = ldl_kernel(ptr);
979	e2 = ldl_kernel(ptr + 4);
980	e3 = ldl_kernel(ptr + 8);
981	/* check gate type */
982	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
983	switch(type) {
984	case 14: /* 386 interrupt gate */
985	case 15: /* 386 trap gate */
986	break;
987	default:
988	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
989	break;
990	}
991	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
992	cpl = env->hflags & HF_CPL_MASK;
993	/* check privledge if software int */
994	if (is_int && dpl < cpl)
995	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
996	/* check valid bit */
997	if (!(e2 & DESC_P_MASK))
998	raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
999	selector = e1 >> 16;
1000	offset = ((target_ulong)e3 << 32) \| (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
1001	ist = e2 & 7;
1002	if ((selector & 0xfffc) == 0)
1003	raise_exception_err(EXCP0D_GPF, 0);
1004
1005	if (load_segment(&e1, &e2, selector) != 0)
1006	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1007	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
1008	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1009	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1010	if (dpl > cpl)
1011	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1012	if (!(e2 & DESC_P_MASK))
1013	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1014	if (!(e2 & DESC_L_MASK) \|\| (e2 & DESC_B_MASK))
1015	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1016	if ((!(e2 & DESC_C_MASK) && dpl < cpl) \|\| ist != 0) {
1017	/* to inner priviledge */
1018	if (ist != 0)
1019	esp = get_rsp_from_tss(ist + 3);
1020	else
1021	esp = get_rsp_from_tss(dpl);
1022	esp &= ~0xfLL; /* align stack */
1023	ss = 0;
1024	new_stack = 1;
1025	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
1026	/* to same priviledge */
1027	if (env->eflags & VM_MASK)
1028	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1029	new_stack = 0;
1030	if (ist != 0)
1031	esp = get_rsp_from_tss(ist + 3);
1032	else
1033	esp = ESP;
1034	esp &= ~0xfLL; /* align stack */
1035	dpl = cpl;
1036	} else {
1037	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1038	new_stack = 0; /* avoid warning */
1039	esp = 0; /* avoid warning */
1040	}
1041
1042	PUSHQ(esp, env->segs[R_SS].selector);
1043	PUSHQ(esp, ESP);
1044	PUSHQ(esp, compute_eflags());
1045	PUSHQ(esp, env->segs[R_CS].selector);
1046	PUSHQ(esp, old_eip);
1047	if (has_error_code) {
1048	PUSHQ(esp, error_code);
1049	}
1050
1051	if (new_stack) {
1052	ss = 0 \| dpl;
1053	cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1054	}
1055	ESP = esp;
1056
1057	selector = (selector & ~3) \| dpl;
1058	cpu_x86_load_seg_cache(env, R_CS, selector,
1059	get_seg_base(e1, e2),
1060	get_seg_limit(e1, e2),
1061	e2);
1062	cpu_x86_set_cpl(env, dpl);
1063	env->eip = offset;
1064
1065	/* interrupt gate clear IF mask */
1066	if ((type & 1) == 0) {
1067	env->eflags &= ~IF_MASK;
1068	}
1069	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1070	}
1071	#endif
1072
1073	void helper_syscall(int next_eip_addend)
1074	{
1075	int selector;
1076
1077	if (!(env->efer & MSR_EFER_SCE)) {
1078	raise_exception_err(EXCP06_ILLOP, 0);
1079	}
1080	selector = (env->star >> 32) & 0xffff;
1081	#ifdef TARGET_X86_64
1082	if (env->hflags & HF_LMA_MASK) {
1083	int code64;
1084
1085	ECX = env->eip + next_eip_addend;
1086	env->regs[11] = compute_eflags();
1087
1088	code64 = env->hflags & HF_CS64_MASK;
1089
1090	cpu_x86_set_cpl(env, 0);
1091	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1092	0, 0xffffffff,
1093	DESC_G_MASK \| DESC_P_MASK \|
1094	DESC_S_MASK \|
1095	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \| DESC_L_MASK);
1096	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1097	0, 0xffffffff,
1098	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1099	DESC_S_MASK \|
1100	DESC_W_MASK \| DESC_A_MASK);
1101	env->eflags &= ~env->fmask;
1102	if (code64)
1103	env->eip = env->lstar;
1104	else
1105	env->eip = env->cstar;
1106	} else
1107	#endif
1108	{
1109	ECX = (uint32_t)(env->eip + next_eip_addend);
1110
1111	cpu_x86_set_cpl(env, 0);
1112	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1113	0, 0xffffffff,
1114	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1115	DESC_S_MASK \|
1116	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1117	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1118	0, 0xffffffff,
1119	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1120	DESC_S_MASK \|
1121	DESC_W_MASK \| DESC_A_MASK);
1122	env->eflags &= ~(IF_MASK \| RF_MASK \| VM_MASK);
1123	env->eip = (uint32_t)env->star;
1124	}
1125	}
1126
1127	void helper_sysret(int dflag)
1128	{
1129	int cpl, selector;
1130
1131	if (!(env->efer & MSR_EFER_SCE)) {
1132	raise_exception_err(EXCP06_ILLOP, 0);
1133	}
1134	cpl = env->hflags & HF_CPL_MASK;
1135	if (!(env->cr[0] & CR0_PE_MASK) \|\| cpl != 0) {
1136	raise_exception_err(EXCP0D_GPF, 0);
1137	}
1138	selector = (env->star >> 48) & 0xffff;
1139	#ifdef TARGET_X86_64
1140	if (env->hflags & HF_LMA_MASK) {
1141	if (dflag == 2) {
1142	cpu_x86_load_seg_cache(env, R_CS, (selector + 16) \| 3,
1143	0, 0xffffffff,
1144	DESC_G_MASK \| DESC_P_MASK \|
1145	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1146	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \|
1147	DESC_L_MASK);
1148	env->eip = ECX;
1149	} else {
1150	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1151	0, 0xffffffff,
1152	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1153	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1154	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1155	env->eip = (uint32_t)ECX;
1156	}
1157	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1158	0, 0xffffffff,
1159	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1160	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1161	DESC_W_MASK \| DESC_A_MASK);
1162	load_eflags((uint32_t)(env->regs[11]), TF_MASK \| AC_MASK \| ID_MASK \|
1163	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1164	cpu_x86_set_cpl(env, 3);
1165	} else
1166	#endif
1167	{
1168	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1169	0, 0xffffffff,
1170	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1171	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1172	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1173	env->eip = (uint32_t)ECX;
1174	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1175	0, 0xffffffff,
1176	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1177	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1178	DESC_W_MASK \| DESC_A_MASK);
1179	env->eflags \|= IF_MASK;
1180	cpu_x86_set_cpl(env, 3);
1181	}
1182	#ifdef USE_KQEMU
1183	if (kqemu_is_ok(env)) {
1184	if (env->hflags & HF_LMA_MASK)
1185	CC_OP = CC_OP_EFLAGS;
1186	env->exception_index = -1;
1187	cpu_loop_exit();
1188	}
1189	#endif
1190	}
1191
1192	#ifdef VBOX
1193	/**
1194	* Checks and processes external VMM events.
1195	* Called by op_check_external_event() when any of the flags is set and can be serviced.
1196	*/
1197	void helper_external_event(void)
1198	{
1199	#if defined(__DARWIN__) && defined(VBOX_STRICT)
1200	# if 0
1201	//uintptr_t uFrameAddr = (uintptr_t)__builtin_frame_address(0); - this is broken (uses %ebp)
1202	//AssertMsg(!( (uFrameAddr - sizeof(uintptr_t)) & 7 ), ("uFrameAddr=%#p\n", uFrameAddr));
1203	# else
1204	uintptr_t uESP;
1205	__asm__ __volatile__("movl %%esp, %0" : "=r" (uESP));
1206	AssertMsg(!(uESP & 15), ("esp=%#p\n", uESP));
1207	# endif
1208	#endif
1209	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1210	{
1211	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1212	cpu_interrupt(env, CPU_INTERRUPT_HARD);
1213	}
1214	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1215	{
1216	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1217	cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1218	}
1219	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1220	{
1221	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1222	remR3DmaRun(env);
1223	}
1224	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1225	{
1226	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1227	remR3TimersRun(env);
1228	}
1229	}
1230	#endif /* VBOX */
1231
1232	/* real mode interrupt */
1233	static void do_interrupt_real(int intno, int is_int, int error_code,
1234	unsigned int next_eip)
1235	{
1236	SegmentCache *dt;
1237	target_ulong ptr, ssp;
1238	int selector;
1239	uint32_t offset, esp;
1240	uint32_t old_cs, old_eip;
1241
1242	/* real mode (simpler !) */
1243	dt = &env->idt;
1244	if (intno * 4 + 3 > dt->limit)
1245	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1246	ptr = dt->base + intno * 4;
1247	offset = lduw_kernel(ptr);
1248	selector = lduw_kernel(ptr + 2);
1249	esp = ESP;
1250	ssp = env->segs[R_SS].base;
1251	if (is_int)
1252	old_eip = next_eip;
1253	else
1254	old_eip = env->eip;
1255	old_cs = env->segs[R_CS].selector;
1256	/* XXX: use SS segment size ? */
1257	PUSHW(ssp, esp, 0xffff, compute_eflags());
1258	PUSHW(ssp, esp, 0xffff, old_cs);
1259	PUSHW(ssp, esp, 0xffff, old_eip);
1260
1261	/* update processor state */
1262	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
1263	env->eip = offset;
1264	env->segs[R_CS].selector = selector;
1265	env->segs[R_CS].base = (selector << 4);
1266	env->eflags &= ~(IF_MASK \| TF_MASK \| AC_MASK \| RF_MASK);
1267	}
1268
1269	/* fake user mode interrupt */
1270	void do_interrupt_user(int intno, int is_int, int error_code,
1271	target_ulong next_eip)
1272	{
1273	SegmentCache *dt;
1274	target_ulong ptr;
1275	int dpl, cpl;
1276	uint32_t e2;
1277
1278	dt = &env->idt;
1279	ptr = dt->base + (intno * 8);
1280	e2 = ldl_kernel(ptr + 4);
1281
1282	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1283	cpl = env->hflags & HF_CPL_MASK;
1284	/* check privledge if software int */
1285	if (is_int && dpl < cpl)
1286	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1287
1288	/* Since we emulate only user space, we cannot do more than
1289	exiting the emulation with the suitable exception and error
1290	code */
1291	if (is_int)
1292	EIP = next_eip;
1293	}
1294
1295	/*
1296	* Begin execution of an interruption. is_int is TRUE if coming from
1297	* the int instruction. next_eip is the EIP value AFTER the interrupt
1298	* instruction. It is only relevant if is_int is TRUE.
1299	*/
1300	void do_interrupt(int intno, int is_int, int error_code,
1301	target_ulong next_eip, int is_hw)
1302	{
1303	if (loglevel & CPU_LOG_INT) {
1304	if ((env->cr[0] & CR0_PE_MASK)) {
1305	static int count;
1306	fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1307	count, intno, error_code, is_int,
1308	env->hflags & HF_CPL_MASK,
1309	env->segs[R_CS].selector, EIP,
1310	(int)env->segs[R_CS].base + EIP,
1311	env->segs[R_SS].selector, ESP);
1312	if (intno == 0x0e) {
1313	fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1314	} else {
1315	fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1316	}
1317	fprintf(logfile, "\n");
1318	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1319	#if 0
1320	{
1321	int i;
1322	uint8_t *ptr;
1323	fprintf(logfile, " code=");
1324	ptr = env->segs[R_CS].base + env->eip;
1325	for(i = 0; i < 16; i++) {
1326	fprintf(logfile, " %02x", ldub(ptr + i));
1327	}
1328	fprintf(logfile, "\n");
1329	}
1330	#endif
1331	count++;
1332	}
1333	}
1334	if (env->cr[0] & CR0_PE_MASK) {
1335	#if TARGET_X86_64
1336	if (env->hflags & HF_LMA_MASK) {
1337	do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1338	} else
1339	#endif
1340	{
1341	#ifdef VBOX
1342	/* int xx , v86 code and VME enabled? /
1343	if ( (env->eflags & VM_MASK)
1344	&& (env->cr[4] & CR4_VME_MASK)
1345	&& is_int
1346	&& !is_hw
1347	&& env->eip + 1 != next_eip /* single byte int 3 goes straight to the protected mode handler */
1348	)
1349	do_soft_interrupt_vme(intno, error_code, next_eip);
1350	else
1351	#endif /* VBOX */
1352	do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1353	}
1354	} else {
1355	do_interrupt_real(intno, is_int, error_code, next_eip);
1356	}
1357	}
1358
1359	/*
1360	* Signal an interruption. It is executed in the main CPU loop.
1361	* is_int is TRUE if coming from the int instruction. next_eip is the
1362	* EIP value AFTER the interrupt instruction. It is only relevant if
1363	* is_int is TRUE.
1364	*/
1365	void raise_interrupt(int intno, int is_int, int error_code,
1366	int next_eip_addend)
1367	{
1368	#if defined(VBOX) && defined(DEBUG) && !defined(DEBUG_dmik)
1369	Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend));
1370	#endif
1371	env->exception_index = intno;
1372	env->error_code = error_code;
1373	env->exception_is_int = is_int;
1374	env->exception_next_eip = env->eip + next_eip_addend;
1375	cpu_loop_exit();
1376	}
1377
1378	/* same as raise_exception_err, but do not restore global registers */
1379	static void raise_exception_err_norestore(int exception_index, int error_code)
1380	{
1381	env->exception_index = exception_index;
1382	env->error_code = error_code;
1383	env->exception_is_int = 0;
1384	env->exception_next_eip = 0;
1385	longjmp(env->jmp_env, 1);
1386	}
1387
1388	/* shortcuts to generate exceptions */
1389
1390	void (raise_exception_err)(int exception_index, int error_code)
1391	{
1392	raise_interrupt(exception_index, 0, error_code, 0);
1393	}
1394
1395	void raise_exception(int exception_index)
1396	{
1397	raise_interrupt(exception_index, 0, 0, 0);
1398	}
1399
1400	/* SMM support */
1401
1402	#if defined(CONFIG_USER_ONLY)
1403
1404	void do_smm_enter(void)
1405	{
1406	}
1407
1408	void helper_rsm(void)
1409	{
1410	}
1411
1412	#else
1413
1414	#ifdef TARGET_X86_64
1415	#define SMM_REVISION_ID 0x00020064
1416	#else
1417	#define SMM_REVISION_ID 0x00020000
1418	#endif
1419
1420	void do_smm_enter(void)
1421	{
1422	#ifdef VBOX
1423	cpu_abort(env, "do_ssm_enter");
1424	#else /* !VBOX */
1425	target_ulong sm_state;
1426	SegmentCache *dt;
1427	int i, offset;
1428
1429	if (loglevel & CPU_LOG_INT) {
1430	fprintf(logfile, "SMM: enter\n");
1431	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1432	}
1433
1434	env->hflags \|= HF_SMM_MASK;
1435	cpu_smm_update(env);
1436
1437	sm_state = env->smbase + 0x8000;
1438
1439	#ifdef TARGET_X86_64
1440	for(i = 0; i < 6; i++) {
1441	dt = &env->segs[i];
1442	offset = 0x7e00 + i * 16;
1443	stw_phys(sm_state + offset, dt->selector);
1444	stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1445	stl_phys(sm_state + offset + 4, dt->limit);
1446	stq_phys(sm_state + offset + 8, dt->base);
1447	}
1448
1449	stq_phys(sm_state + 0x7e68, env->gdt.base);
1450	stl_phys(sm_state + 0x7e64, env->gdt.limit);
1451
1452	stw_phys(sm_state + 0x7e70, env->ldt.selector);
1453	stq_phys(sm_state + 0x7e78, env->ldt.base);
1454	stl_phys(sm_state + 0x7e74, env->ldt.limit);
1455	stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1456
1457	stq_phys(sm_state + 0x7e88, env->idt.base);
1458	stl_phys(sm_state + 0x7e84, env->idt.limit);
1459
1460	stw_phys(sm_state + 0x7e90, env->tr.selector);
1461	stq_phys(sm_state + 0x7e98, env->tr.base);
1462	stl_phys(sm_state + 0x7e94, env->tr.limit);
1463	stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1464
1465	stq_phys(sm_state + 0x7ed0, env->efer);
1466
1467	stq_phys(sm_state + 0x7ff8, EAX);
1468	stq_phys(sm_state + 0x7ff0, ECX);
1469	stq_phys(sm_state + 0x7fe8, EDX);
1470	stq_phys(sm_state + 0x7fe0, EBX);
1471	stq_phys(sm_state + 0x7fd8, ESP);
1472	stq_phys(sm_state + 0x7fd0, EBP);
1473	stq_phys(sm_state + 0x7fc8, ESI);
1474	stq_phys(sm_state + 0x7fc0, EDI);
1475	for(i = 8; i < 16; i++)
1476	stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1477	stq_phys(sm_state + 0x7f78, env->eip);
1478	stl_phys(sm_state + 0x7f70, compute_eflags());
1479	stl_phys(sm_state + 0x7f68, env->dr[6]);
1480	stl_phys(sm_state + 0x7f60, env->dr[7]);
1481
1482	stl_phys(sm_state + 0x7f48, env->cr[4]);
1483	stl_phys(sm_state + 0x7f50, env->cr[3]);
1484	stl_phys(sm_state + 0x7f58, env->cr[0]);
1485
1486	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1487	stl_phys(sm_state + 0x7f00, env->smbase);
1488	#else
1489	stl_phys(sm_state + 0x7ffc, env->cr[0]);
1490	stl_phys(sm_state + 0x7ff8, env->cr[3]);
1491	stl_phys(sm_state + 0x7ff4, compute_eflags());
1492	stl_phys(sm_state + 0x7ff0, env->eip);
1493	stl_phys(sm_state + 0x7fec, EDI);
1494	stl_phys(sm_state + 0x7fe8, ESI);
1495	stl_phys(sm_state + 0x7fe4, EBP);
1496	stl_phys(sm_state + 0x7fe0, ESP);
1497	stl_phys(sm_state + 0x7fdc, EBX);
1498	stl_phys(sm_state + 0x7fd8, EDX);
1499	stl_phys(sm_state + 0x7fd4, ECX);
1500	stl_phys(sm_state + 0x7fd0, EAX);
1501	stl_phys(sm_state + 0x7fcc, env->dr[6]);
1502	stl_phys(sm_state + 0x7fc8, env->dr[7]);
1503
1504	stl_phys(sm_state + 0x7fc4, env->tr.selector);
1505	stl_phys(sm_state + 0x7f64, env->tr.base);
1506	stl_phys(sm_state + 0x7f60, env->tr.limit);
1507	stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1508
1509	stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1510	stl_phys(sm_state + 0x7f80, env->ldt.base);
1511	stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1512	stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1513
1514	stl_phys(sm_state + 0x7f74, env->gdt.base);
1515	stl_phys(sm_state + 0x7f70, env->gdt.limit);
1516
1517	stl_phys(sm_state + 0x7f58, env->idt.base);
1518	stl_phys(sm_state + 0x7f54, env->idt.limit);
1519
1520	for(i = 0; i < 6; i++) {
1521	dt = &env->segs[i];
1522	if (i < 3)
1523	offset = 0x7f84 + i * 12;
1524	else
1525	offset = 0x7f2c + (i - 3) * 12;
1526	stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1527	stl_phys(sm_state + offset + 8, dt->base);
1528	stl_phys(sm_state + offset + 4, dt->limit);
1529	stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1530	}
1531	stl_phys(sm_state + 0x7f14, env->cr[4]);
1532
1533	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1534	stl_phys(sm_state + 0x7ef8, env->smbase);
1535	#endif
1536	/* init SMM cpu state */
1537
1538	#ifdef TARGET_X86_64
1539	env->efer = 0;
1540	env->hflags &= ~HF_LMA_MASK;
1541	#endif
1542	load_eflags(0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1543	env->eip = 0x00008000;
1544	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1545	0xffffffff, 0);
1546	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1547	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1548	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1549	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1550	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1551
1552	cpu_x86_update_cr0(env,
1553	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \| CR0_PG_MASK));
1554	cpu_x86_update_cr4(env, 0);
1555	env->dr[7] = 0x00000400;
1556	CC_OP = CC_OP_EFLAGS;
1557	#endif /* VBOX */
1558	}
1559
1560	void helper_rsm(void)
1561	{
1562	#ifdef VBOX
1563	cpu_abort(env, "helper_rsm");
1564	#else /* !VBOX */
1565	target_ulong sm_state;
1566	int i, offset;
1567	uint32_t val;
1568
1569	sm_state = env->smbase + 0x8000;
1570	#ifdef TARGET_X86_64
1571	env->efer = ldq_phys(sm_state + 0x7ed0);
1572	if (env->efer & MSR_EFER_LMA)
1573	env->hflags \|= HF_LMA_MASK;
1574	else
1575	env->hflags &= ~HF_LMA_MASK;
1576
1577	for(i = 0; i < 6; i++) {
1578	offset = 0x7e00 + i * 16;
1579	cpu_x86_load_seg_cache(env, i,
1580	lduw_phys(sm_state + offset),
1581	ldq_phys(sm_state + offset + 8),
1582	ldl_phys(sm_state + offset + 4),
1583	(lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1584	}
1585
1586	env->gdt.base = ldq_phys(sm_state + 0x7e68);
1587	env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1588
1589	env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1590	env->ldt.base = ldq_phys(sm_state + 0x7e78);
1591	env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1592	env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1593
1594	env->idt.base = ldq_phys(sm_state + 0x7e88);
1595	env->idt.limit = ldl_phys(sm_state + 0x7e84);
1596
1597	env->tr.selector = lduw_phys(sm_state + 0x7e90);
1598	env->tr.base = ldq_phys(sm_state + 0x7e98);
1599	env->tr.limit = ldl_phys(sm_state + 0x7e94);
1600	env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1601
1602	EAX = ldq_phys(sm_state + 0x7ff8);
1603	ECX = ldq_phys(sm_state + 0x7ff0);
1604	EDX = ldq_phys(sm_state + 0x7fe8);
1605	EBX = ldq_phys(sm_state + 0x7fe0);
1606	ESP = ldq_phys(sm_state + 0x7fd8);
1607	EBP = ldq_phys(sm_state + 0x7fd0);
1608	ESI = ldq_phys(sm_state + 0x7fc8);
1609	EDI = ldq_phys(sm_state + 0x7fc0);
1610	for(i = 8; i < 16; i++)
1611	env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1612	env->eip = ldq_phys(sm_state + 0x7f78);
1613	load_eflags(ldl_phys(sm_state + 0x7f70),
1614	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1615	env->dr[6] = ldl_phys(sm_state + 0x7f68);
1616	env->dr[7] = ldl_phys(sm_state + 0x7f60);
1617
1618	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1619	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1620	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1621
1622	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1623	if (val & 0x20000) {
1624	env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1625	}
1626	#else
1627	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1628	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1629	load_eflags(ldl_phys(sm_state + 0x7ff4),
1630	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1631	env->eip = ldl_phys(sm_state + 0x7ff0);
1632	EDI = ldl_phys(sm_state + 0x7fec);
1633	ESI = ldl_phys(sm_state + 0x7fe8);
1634	EBP = ldl_phys(sm_state + 0x7fe4);
1635	ESP = ldl_phys(sm_state + 0x7fe0);
1636	EBX = ldl_phys(sm_state + 0x7fdc);
1637	EDX = ldl_phys(sm_state + 0x7fd8);
1638	ECX = ldl_phys(sm_state + 0x7fd4);
1639	EAX = ldl_phys(sm_state + 0x7fd0);
1640	env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1641	env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1642
1643	env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1644	env->tr.base = ldl_phys(sm_state + 0x7f64);
1645	env->tr.limit = ldl_phys(sm_state + 0x7f60);
1646	env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1647
1648	env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1649	env->ldt.base = ldl_phys(sm_state + 0x7f80);
1650	env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1651	env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1652
1653	env->gdt.base = ldl_phys(sm_state + 0x7f74);
1654	env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1655
1656	env->idt.base = ldl_phys(sm_state + 0x7f58);
1657	env->idt.limit = ldl_phys(sm_state + 0x7f54);
1658
1659	for(i = 0; i < 6; i++) {
1660	if (i < 3)
1661	offset = 0x7f84 + i * 12;
1662	else
1663	offset = 0x7f2c + (i - 3) * 12;
1664	cpu_x86_load_seg_cache(env, i,
1665	ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1666	ldl_phys(sm_state + offset + 8),
1667	ldl_phys(sm_state + offset + 4),
1668	(ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1669	}
1670	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1671
1672	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1673	if (val & 0x20000) {
1674	env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1675	}
1676	#endif
1677	CC_OP = CC_OP_EFLAGS;
1678	env->hflags &= ~HF_SMM_MASK;
1679	cpu_smm_update(env);
1680
1681	if (loglevel & CPU_LOG_INT) {
1682	fprintf(logfile, "SMM: after RSM\n");
1683	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1684	}
1685	#endif /* !VBOX */
1686	}
1687
1688	#endif /* !CONFIG_USER_ONLY */
1689
1690
1691	#ifdef BUGGY_GCC_DIV64
1692	/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1693	call it from another function */
1694	uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1695	{
1696	*q_ptr = num / den;
1697	return num % den;
1698	}
1699
1700	int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1701	{
1702	*q_ptr = num / den;
1703	return num % den;
1704	}
1705	#endif
1706
1707	void helper_divl_EAX_T0(void)
1708	{
1709	unsigned int den, r;
1710	uint64_t num, q;
1711
1712	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1713	den = T0;
1714	if (den == 0) {
1715	raise_exception(EXCP00_DIVZ);
1716	}
1717	#ifdef BUGGY_GCC_DIV64
1718	r = div32(&q, num, den);
1719	#else
1720	q = (num / den);
1721	r = (num % den);
1722	#endif
1723	if (q > 0xffffffff)
1724	raise_exception(EXCP00_DIVZ);
1725	EAX = (uint32_t)q;
1726	EDX = (uint32_t)r;
1727	}
1728
1729	void helper_idivl_EAX_T0(void)
1730	{
1731	int den, r;
1732	int64_t num, q;
1733
1734	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1735	den = T0;
1736	if (den == 0) {
1737	raise_exception(EXCP00_DIVZ);
1738	}
1739	#ifdef BUGGY_GCC_DIV64
1740	r = idiv32(&q, num, den);
1741	#else
1742	q = (num / den);
1743	r = (num % den);
1744	#endif
1745	if (q != (int32_t)q)
1746	raise_exception(EXCP00_DIVZ);
1747	EAX = (uint32_t)q;
1748	EDX = (uint32_t)r;
1749	}
1750
1751	void helper_cmpxchg8b(void)
1752	{
1753	uint64_t d;
1754	int eflags;
1755
1756	eflags = cc_table[CC_OP].compute_all();
1757	d = ldq(A0);
1758	if (d == (((uint64_t)EDX << 32) \| EAX)) {
1759	stq(A0, ((uint64_t)ECX << 32) \| EBX);
1760	eflags \|= CC_Z;
1761	} else {
1762	EDX = d >> 32;
1763	EAX = d;
1764	eflags &= ~CC_Z;
1765	}
1766	CC_SRC = eflags;
1767	}
1768
1769	void helper_cpuid(void)
1770	{
1771	#ifndef VBOX
1772	uint32_t index;
1773	index = (uint32_t)EAX;
1774
1775	/* test if maximum index reached */
1776	if (index & 0x80000000) {
1777	if (index > env->cpuid_xlevel)
1778	index = env->cpuid_level;
1779	} else {
1780	if (index > env->cpuid_level)
1781	index = env->cpuid_level;
1782	}
1783
1784	switch(index) {
1785	case 0:
1786	EAX = env->cpuid_level;
1787	EBX = env->cpuid_vendor1;
1788	EDX = env->cpuid_vendor2;
1789	ECX = env->cpuid_vendor3;
1790	break;
1791	case 1:
1792	EAX = env->cpuid_version;
1793	EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1794	ECX = env->cpuid_ext_features;
1795	EDX = env->cpuid_features;
1796	break;
1797	case 2:
1798	/* cache info: needed for Pentium Pro compatibility */
1799	EAX = 0x410601;
1800	EBX = 0;
1801	ECX = 0;
1802	EDX = 0;
1803	break;
1804	case 0x80000000:
1805	EAX = env->cpuid_xlevel;
1806	EBX = env->cpuid_vendor1;
1807	EDX = env->cpuid_vendor2;
1808	ECX = env->cpuid_vendor3;
1809	break;
1810	case 0x80000001:
1811	EAX = env->cpuid_features;
1812	EBX = 0;
1813	ECX = 0;
1814	EDX = env->cpuid_ext2_features;
1815	break;
1816	case 0x80000002:
1817	case 0x80000003:
1818	case 0x80000004:
1819	EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1820	EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1821	ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1822	EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1823	break;
1824	case 0x80000005:
1825	/* cache info (L1 cache) */
1826	EAX = 0x01ff01ff;
1827	EBX = 0x01ff01ff;
1828	ECX = 0x40020140;
1829	EDX = 0x40020140;
1830	break;
1831	case 0x80000006:
1832	/* cache info (L2 cache) */
1833	EAX = 0;
1834	EBX = 0x42004200;
1835	ECX = 0x02008140;
1836	EDX = 0;
1837	break;
1838	case 0x80000008:
1839	/* virtual & phys address size in low 2 bytes. */
1840	EAX = 0x00003028;
1841	EBX = 0;
1842	ECX = 0;
1843	EDX = 0;
1844	break;
1845	default:
1846	/* reserved values: zero */
1847	EAX = 0;
1848	EBX = 0;
1849	ECX = 0;
1850	EDX = 0;
1851	break;
1852	}
1853	#else /* VBOX */
1854	remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1855	#endif /* VBOX */
1856	}
1857
1858	void helper_enter_level(int level, int data32)
1859	{
1860	target_ulong ssp;
1861	uint32_t esp_mask, esp, ebp;
1862
1863	esp_mask = get_sp_mask(env->segs[R_SS].flags);
1864	ssp = env->segs[R_SS].base;
1865	ebp = EBP;
1866	esp = ESP;
1867	if (data32) {
1868	/* 32 bit */
1869	esp -= 4;
1870	while (--level) {
1871	esp -= 4;
1872	ebp -= 4;
1873	stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1874	}
1875	esp -= 4;
1876	stl(ssp + (esp & esp_mask), T1);
1877	} else {
1878	/* 16 bit */
1879	esp -= 2;
1880	while (--level) {
1881	esp -= 2;
1882	ebp -= 2;
1883	stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1884	}
1885	esp -= 2;
1886	stw(ssp + (esp & esp_mask), T1);
1887	}
1888	}
1889
1890	#ifdef TARGET_X86_64
1891	void helper_enter64_level(int level, int data64)
1892	{
1893	target_ulong esp, ebp;
1894	ebp = EBP;
1895	esp = ESP;
1896
1897	if (data64) {
1898	/* 64 bit */
1899	esp -= 8;
1900	while (--level) {
1901	esp -= 8;
1902	ebp -= 8;
1903	stq(esp, ldq(ebp));
1904	}
1905	esp -= 8;
1906	stq(esp, T1);
1907	} else {
1908	/* 16 bit */
1909	esp -= 2;
1910	while (--level) {
1911	esp -= 2;
1912	ebp -= 2;
1913	stw(esp, lduw(ebp));
1914	}
1915	esp -= 2;
1916	stw(esp, T1);
1917	}
1918	}
1919	#endif
1920
1921	void helper_lldt_T0(void)
1922	{
1923	int selector;
1924	SegmentCache *dt;
1925	uint32_t e1, e2;
1926	int index, entry_limit;
1927	target_ulong ptr;
1928	#ifdef VBOX
1929	Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1930	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1931	#endif
1932
1933	selector = T0 & 0xffff;
1934	if ((selector & 0xfffc) == 0) {
1935	/* XXX: NULL selector case: invalid LDT */
1936	env->ldt.base = 0;
1937	env->ldt.limit = 0;
1938	} else {
1939	if (selector & 0x4)
1940	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1941	dt = &env->gdt;
1942	index = selector & ~7;
1943	#ifdef TARGET_X86_64
1944	if (env->hflags & HF_LMA_MASK)
1945	entry_limit = 15;
1946	else
1947	#endif
1948	entry_limit = 7;
1949	if ((index + entry_limit) > dt->limit)
1950	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1951	ptr = dt->base + index;
1952	e1 = ldl_kernel(ptr);
1953	e2 = ldl_kernel(ptr + 4);
1954	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1955	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1956	if (!(e2 & DESC_P_MASK))
1957	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1958	#ifdef TARGET_X86_64
1959	if (env->hflags & HF_LMA_MASK) {
1960	uint32_t e3;
1961	e3 = ldl_kernel(ptr + 8);
1962	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1963	env->ldt.base \|= (target_ulong)e3 << 32;
1964	} else
1965	#endif
1966	{
1967	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1968	}
1969	}
1970	env->ldt.selector = selector;
1971	#ifdef VBOX
1972	Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
1973	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
1974	#endif
1975	}
1976
1977	void helper_ltr_T0(void)
1978	{
1979	int selector;
1980	SegmentCache *dt;
1981	uint32_t e1, e2;
1982	int index, type, entry_limit;
1983	target_ulong ptr;
1984
1985	#ifdef VBOX
1986	Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
1987	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
1988	env->tr.flags, (RTSEL)(T0 & 0xffff)));
1989	#endif
1990
1991	selector = T0 & 0xffff;
1992	if ((selector & 0xfffc) == 0) {
1993	/* NULL selector case: invalid TR */
1994	env->tr.base = 0;
1995	env->tr.limit = 0;
1996	env->tr.flags = 0;
1997	} else {
1998	if (selector & 0x4)
1999	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2000	dt = &env->gdt;
2001	index = selector & ~7;
2002	#ifdef TARGET_X86_64
2003	if (env->hflags & HF_LMA_MASK)
2004	entry_limit = 15;
2005	else
2006	#endif
2007	entry_limit = 7;
2008	if ((index + entry_limit) > dt->limit)
2009	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2010	ptr = dt->base + index;
2011	e1 = ldl_kernel(ptr);
2012	e2 = ldl_kernel(ptr + 4);
2013	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2014	if ((e2 & DESC_S_MASK) \|\|
2015	(type != 1 && type != 9))
2016	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2017	if (!(e2 & DESC_P_MASK))
2018	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2019	#ifdef TARGET_X86_64
2020	if (env->hflags & HF_LMA_MASK) {
2021	uint32_t e3;
2022	e3 = ldl_kernel(ptr + 8);
2023	load_seg_cache_raw_dt(&env->tr, e1, e2);
2024	env->tr.base \|= (target_ulong)e3 << 32;
2025	} else
2026	#endif
2027	{
2028	load_seg_cache_raw_dt(&env->tr, e1, e2);
2029	}
2030	e2 \|= DESC_TSS_BUSY_MASK;
2031	stl_kernel(ptr + 4, e2);
2032	}
2033	env->tr.selector = selector;
2034	#ifdef VBOX
2035	Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2036	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2037	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2038	#endif
2039	}
2040
2041	/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2042	void load_seg(int seg_reg, int selector)
2043	{
2044	uint32_t e1, e2;
2045	int cpl, dpl, rpl;
2046	SegmentCache *dt;
2047	int index;
2048	target_ulong ptr;
2049
2050	selector &= 0xffff;
2051	cpl = env->hflags & HF_CPL_MASK;
2052	if ((selector & 0xfffc) == 0) {
2053	/* null selector case */
2054	if (seg_reg == R_SS
2055	#ifdef TARGET_X86_64
2056	&& (!(env->hflags & HF_CS64_MASK) \|\| cpl == 3)
2057	#endif
2058	)
2059	raise_exception_err(EXCP0D_GPF, 0);
2060	cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2061	} else {
2062
2063	if (selector & 0x4)
2064	dt = &env->ldt;
2065	else
2066	dt = &env->gdt;
2067	index = selector & ~7;
2068	if ((index + 7) > dt->limit)
2069	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2070	ptr = dt->base + index;
2071	e1 = ldl_kernel(ptr);
2072	e2 = ldl_kernel(ptr + 4);
2073
2074	if (!(e2 & DESC_S_MASK))
2075	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2076	rpl = selector & 3;
2077	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2078	if (seg_reg == R_SS) {
2079	/* must be writable segment */
2080	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
2081	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2082	if (rpl != cpl \|\| dpl != cpl)
2083	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2084	} else {
2085	/* must be readable segment */
2086	if ((e2 & (DESC_CS_MASK \| DESC_R_MASK)) == DESC_CS_MASK)
2087	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2088
2089	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2090	/* if not conforming code, test rights */
2091	if (dpl < cpl \|\| dpl < rpl)
2092	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2093	}
2094	}
2095
2096	if (!(e2 & DESC_P_MASK)) {
2097	if (seg_reg == R_SS)
2098	raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
2099	else
2100	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2101	}
2102
2103	/* set the access bit if not already set */
2104	if (!(e2 & DESC_A_MASK)) {
2105	e2 \|= DESC_A_MASK;
2106	stl_kernel(ptr + 4, e2);
2107	}
2108
2109	cpu_x86_load_seg_cache(env, seg_reg, selector,
2110	get_seg_base(e1, e2),
2111	get_seg_limit(e1, e2),
2112	e2);
2113	#if 0
2114	fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
2115	selector, (unsigned long)sc->base, sc->limit, sc->flags);
2116	#endif
2117	}
2118	}
2119
2120	/* protected mode jump */
2121	void helper_ljmp_protected_T0_T1(int next_eip_addend)
2122	{
2123	int new_cs, gate_cs, type;
2124	uint32_t e1, e2, cpl, dpl, rpl, limit;
2125	target_ulong new_eip, next_eip;
2126
2127	new_cs = T0;
2128	new_eip = T1;
2129	if ((new_cs & 0xfffc) == 0)
2130	raise_exception_err(EXCP0D_GPF, 0);
2131	if (load_segment(&e1, &e2, new_cs) != 0)
2132	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2133	cpl = env->hflags & HF_CPL_MASK;
2134	if (e2 & DESC_S_MASK) {
2135	if (!(e2 & DESC_CS_MASK))
2136	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2137	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2138	if (e2 & DESC_C_MASK) {
2139	/* conforming code segment */
2140	if (dpl > cpl)
2141	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2142	} else {
2143	/* non conforming code segment */
2144	rpl = new_cs & 3;
2145	if (rpl > cpl)
2146	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2147	if (dpl != cpl)
2148	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2149	}
2150	if (!(e2 & DESC_P_MASK))
2151	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2152	limit = get_seg_limit(e1, e2);
2153	if (new_eip > limit &&
2154	!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2155	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2156	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2157	get_seg_base(e1, e2), limit, e2);
2158	EIP = new_eip;
2159	} else {
2160	/* jump to call or task gate */
2161	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2162	rpl = new_cs & 3;
2163	cpl = env->hflags & HF_CPL_MASK;
2164	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2165	switch(type) {
2166	case 1: /* 286 TSS */
2167	case 9: /* 386 TSS */
2168	case 5: /* task gate */
2169	if (dpl < cpl \|\| dpl < rpl)
2170	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2171	next_eip = env->eip + next_eip_addend;
2172	switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2173	CC_OP = CC_OP_EFLAGS;
2174	break;
2175	case 4: /* 286 call gate */
2176	case 12: /* 386 call gate */
2177	if ((dpl < cpl) \|\| (dpl < rpl))
2178	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2179	if (!(e2 & DESC_P_MASK))
2180	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2181	gate_cs = e1 >> 16;
2182	new_eip = (e1 & 0xffff);
2183	if (type == 12)
2184	new_eip \|= (e2 & 0xffff0000);
2185	if (load_segment(&e1, &e2, gate_cs) != 0)
2186	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2187	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2188	/* must be code segment */
2189	if (((e2 & (DESC_S_MASK \| DESC_CS_MASK)) !=
2190	(DESC_S_MASK \| DESC_CS_MASK)))
2191	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2192	if (((e2 & DESC_C_MASK) && (dpl > cpl)) \|\|
2193	(!(e2 & DESC_C_MASK) && (dpl != cpl)))
2194	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2195	if (!(e2 & DESC_P_MASK))
2196	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2197	limit = get_seg_limit(e1, e2);
2198	if (new_eip > limit)
2199	raise_exception_err(EXCP0D_GPF, 0);
2200	cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) \| cpl,
2201	get_seg_base(e1, e2), limit, e2);
2202	EIP = new_eip;
2203	break;
2204	default:
2205	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2206	break;
2207	}
2208	}
2209	}
2210
2211	/* real mode call */
2212	void helper_lcall_real_T0_T1(int shift, int next_eip)
2213	{
2214	int new_cs, new_eip;
2215	uint32_t esp, esp_mask;
2216	target_ulong ssp;
2217
2218	new_cs = T0;
2219	new_eip = T1;
2220	esp = ESP;
2221	esp_mask = get_sp_mask(env->segs[R_SS].flags);
2222	ssp = env->segs[R_SS].base;
2223	if (shift) {
2224	PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2225	PUSHL(ssp, esp, esp_mask, next_eip);
2226	} else {
2227	PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2228	PUSHW(ssp, esp, esp_mask, next_eip);
2229	}
2230
2231	SET_ESP(esp, esp_mask);
2232	env->eip = new_eip;
2233	env->segs[R_CS].selector = new_cs;
2234	env->segs[R_CS].base = (new_cs << 4);
2235	}
2236
2237	/* protected mode call */
2238	void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2239	{
2240	int new_cs, new_stack, i;
2241	uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2242	uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2243	uint32_t val, limit, old_sp_mask;
2244	target_ulong ssp, old_ssp, next_eip, new_eip;
2245
2246	new_cs = T0;
2247	new_eip = T1;
2248	next_eip = env->eip + next_eip_addend;
2249	#ifdef DEBUG_PCALL
2250	if (loglevel & CPU_LOG_PCALL) {
2251	fprintf(logfile, "lcall %04x:%08x s=%d\n",
2252	new_cs, (uint32_t)new_eip, shift);
2253	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2254	}
2255	#endif
2256	if ((new_cs & 0xfffc) == 0)
2257	raise_exception_err(EXCP0D_GPF, 0);
2258	if (load_segment(&e1, &e2, new_cs) != 0)
2259	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2260	cpl = env->hflags & HF_CPL_MASK;
2261	#ifdef DEBUG_PCALL
2262	if (loglevel & CPU_LOG_PCALL) {
2263	fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2264	}
2265	#endif
2266	if (e2 & DESC_S_MASK) {
2267	if (!(e2 & DESC_CS_MASK))
2268	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2269	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2270	if (e2 & DESC_C_MASK) {
2271	/* conforming code segment */
2272	if (dpl > cpl)
2273	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2274	} else {
2275	/* non conforming code segment */
2276	rpl = new_cs & 3;
2277	if (rpl > cpl)
2278	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2279	if (dpl != cpl)
2280	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2281	}
2282	if (!(e2 & DESC_P_MASK))
2283	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2284
2285	#ifdef TARGET_X86_64
2286	/* XXX: check 16/32 bit cases in long mode */
2287	if (shift == 2) {
2288	target_ulong rsp;
2289	/* 64 bit case */
2290	rsp = ESP;
2291	PUSHQ(rsp, env->segs[R_CS].selector);
2292	PUSHQ(rsp, next_eip);
2293	/* from this point, not restartable */
2294	ESP = rsp;
2295	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2296	get_seg_base(e1, e2),
2297	get_seg_limit(e1, e2), e2);
2298	EIP = new_eip;
2299	} else
2300	#endif
2301	{
2302	sp = ESP;
2303	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2304	ssp = env->segs[R_SS].base;
2305	if (shift) {
2306	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2307	PUSHL(ssp, sp, sp_mask, next_eip);
2308	} else {
2309	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2310	PUSHW(ssp, sp, sp_mask, next_eip);
2311	}
2312
2313	limit = get_seg_limit(e1, e2);
2314	if (new_eip > limit)
2315	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2316	/* from this point, not restartable */
2317	SET_ESP(sp, sp_mask);
2318	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2319	get_seg_base(e1, e2), limit, e2);
2320	EIP = new_eip;
2321	}
2322	} else {
2323	/* check gate type */
2324	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
2325	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2326	rpl = new_cs & 3;
2327	switch(type) {
2328	case 1: /* available 286 TSS */
2329	case 9: /* available 386 TSS */
2330	case 5: /* task gate */
2331	if (dpl < cpl \|\| dpl < rpl)
2332	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2333	switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
2334	CC_OP = CC_OP_EFLAGS;
2335	return;
2336	case 4: /* 286 call gate */
2337	case 12: /* 386 call gate */
2338	break;
2339	default:
2340	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2341	break;
2342	}
2343	shift = type >> 3;
2344
2345	if (dpl < cpl \|\| dpl < rpl)
2346	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2347	/* check valid bit */
2348	if (!(e2 & DESC_P_MASK))
2349	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2350	selector = e1 >> 16;
2351	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
2352	param_count = e2 & 0x1f;
2353	if ((selector & 0xfffc) == 0)
2354	raise_exception_err(EXCP0D_GPF, 0);
2355
2356	if (load_segment(&e1, &e2, selector) != 0)
2357	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2358	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
2359	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2360	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2361	if (dpl > cpl)
2362	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2363	if (!(e2 & DESC_P_MASK))
2364	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2365
2366	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2367	/* to inner priviledge */
2368	get_ss_esp_from_tss(&ss, &sp, dpl);
2369	#ifdef DEBUG_PCALL
2370	if (loglevel & CPU_LOG_PCALL)
2371	fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2372	ss, sp, param_count, ESP);
2373	#endif
2374	if ((ss & 0xfffc) == 0)
2375	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2376	if ((ss & 3) != dpl)
2377	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2378	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2379	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2380	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2381	if (ss_dpl != dpl)
2382	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2383	if (!(ss_e2 & DESC_S_MASK) \|\|
2384	(ss_e2 & DESC_CS_MASK) \|\|
2385	!(ss_e2 & DESC_W_MASK))
2386	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2387	if (!(ss_e2 & DESC_P_MASK))
2388	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2389
2390	// push_size = ((param_count * 2) + 8) << shift;
2391
2392	old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2393	old_ssp = env->segs[R_SS].base;
2394
2395	sp_mask = get_sp_mask(ss_e2);
2396	ssp = get_seg_base(ss_e1, ss_e2);
2397	if (shift) {
2398	PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2399	PUSHL(ssp, sp, sp_mask, ESP);
2400	for(i = param_count - 1; i >= 0; i--) {
2401	val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2402	PUSHL(ssp, sp, sp_mask, val);
2403	}
2404	} else {
2405	PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2406	PUSHW(ssp, sp, sp_mask, ESP);
2407	for(i = param_count - 1; i >= 0; i--) {
2408	val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2409	PUSHW(ssp, sp, sp_mask, val);
2410	}
2411	}
2412	new_stack = 1;
2413	} else {
2414	/* to same priviledge */
2415	sp = ESP;
2416	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2417	ssp = env->segs[R_SS].base;
2418	// push_size = (4 << shift);
2419	new_stack = 0;
2420	}
2421
2422	if (shift) {
2423	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2424	PUSHL(ssp, sp, sp_mask, next_eip);
2425	} else {
2426	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2427	PUSHW(ssp, sp, sp_mask, next_eip);
2428	}
2429
2430	/* from this point, not restartable */
2431
2432	if (new_stack) {
2433	ss = (ss & ~3) \| dpl;
2434	cpu_x86_load_seg_cache(env, R_SS, ss,
2435	ssp,
2436	get_seg_limit(ss_e1, ss_e2),
2437	ss_e2);
2438	}
2439
2440	selector = (selector & ~3) \| dpl;
2441	cpu_x86_load_seg_cache(env, R_CS, selector,
2442	get_seg_base(e1, e2),
2443	get_seg_limit(e1, e2),
2444	e2);
2445	cpu_x86_set_cpl(env, dpl);
2446	SET_ESP(sp, sp_mask);
2447	EIP = offset;
2448	}
2449	#ifdef USE_KQEMU
2450	if (kqemu_is_ok(env)) {
2451	env->exception_index = -1;
2452	cpu_loop_exit();
2453	}
2454	#endif
2455	}
2456
2457	/* real and vm86 mode iret */
2458	void helper_iret_real(int shift)
2459	{
2460	uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2461	target_ulong ssp;
2462	int eflags_mask;
2463	#ifdef VBOX
2464	bool fVME = false;
2465
2466	remR3TrapClear(env->pVM);
2467	#endif /* VBOX */
2468
2469	sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2470	sp = ESP;
2471	ssp = env->segs[R_SS].base;
2472	if (shift == 1) {
2473	/* 32 bits */
2474	POPL(ssp, sp, sp_mask, new_eip);
2475	POPL(ssp, sp, sp_mask, new_cs);
2476	new_cs &= 0xffff;
2477	POPL(ssp, sp, sp_mask, new_eflags);
2478	} else {
2479	/* 16 bits */
2480	POPW(ssp, sp, sp_mask, new_eip);
2481	POPW(ssp, sp, sp_mask, new_cs);
2482	POPW(ssp, sp, sp_mask, new_eflags);
2483	}
2484	#ifdef VBOX
2485	if ( (env->eflags & VM_MASK)
2486	&& ((env->eflags >> IOPL_SHIFT) & 3) != 3
2487	&& (env->cr[4] & CR4_VME_MASK)) /* implied or else we would fault earlier */
2488	{
2489	fVME = true;
2490	/* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
2491	/* if TF will be set -> #GP */
2492	if ( ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
2493	\|\| (new_eflags & TF_MASK))
2494	raise_exception(EXCP0D_GPF);
2495	}
2496	#endif /* VBOX */
2497
2498	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);
2499	load_seg_vm(R_CS, new_cs);
2500	env->eip = new_eip;
2501	#ifdef VBOX
2502	if (fVME)
2503	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2504	else
2505	#endif
2506	if (env->eflags & VM_MASK)
2507	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| RF_MASK \| NT_MASK;
2508	else
2509	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| IOPL_MASK \| RF_MASK \| NT_MASK;
2510	if (shift == 0)
2511	eflags_mask &= 0xffff;
2512	load_eflags(new_eflags, eflags_mask);
2513
2514	#ifdef VBOX
2515	if (fVME)
2516	{
2517	if (new_eflags & IF_MASK)
2518	env->eflags \|= VIF_MASK;
2519	else
2520	env->eflags &= ~VIF_MASK;
2521	}
2522	#endif /* VBOX */
2523	}
2524
2525	static inline void validate_seg(int seg_reg, int cpl)
2526	{
2527	int dpl;
2528	uint32_t e2;
2529
2530	/* XXX: on x86_64, we do not want to nullify FS and GS because
2531	they may still contain a valid base. I would be interested to
2532	know how a real x86_64 CPU behaves */
2533	if ((seg_reg == R_FS \|\| seg_reg == R_GS) &&
2534	(env->segs[seg_reg].selector & 0xfffc) == 0)
2535	return;
2536
2537	e2 = env->segs[seg_reg].flags;
2538	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2539	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2540	/* data or non conforming code segment */
2541	if (dpl < cpl) {
2542	cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2543	}
2544	}
2545	}
2546
2547	/* protected mode iret */
2548	static inline void helper_ret_protected(int shift, int is_iret, int addend)
2549	{
2550	uint32_t new_cs, new_eflags, new_ss;
2551	uint32_t new_es, new_ds, new_fs, new_gs;
2552	uint32_t e1, e2, ss_e1, ss_e2;
2553	int cpl, dpl, rpl, eflags_mask, iopl;
2554	target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2555
2556	#ifdef TARGET_X86_64
2557	if (shift == 2)
2558	sp_mask = -1;
2559	else
2560	#endif
2561	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2562	sp = ESP;
2563	ssp = env->segs[R_SS].base;
2564	new_eflags = 0; /* avoid warning */
2565	#ifdef TARGET_X86_64
2566	if (shift == 2) {
2567	POPQ(sp, new_eip);
2568	POPQ(sp, new_cs);
2569	new_cs &= 0xffff;
2570	if (is_iret) {
2571	POPQ(sp, new_eflags);
2572	}
2573	} else
2574	#endif
2575	if (shift == 1) {
2576	/* 32 bits */
2577	POPL(ssp, sp, sp_mask, new_eip);
2578	POPL(ssp, sp, sp_mask, new_cs);
2579	new_cs &= 0xffff;
2580	if (is_iret) {
2581	POPL(ssp, sp, sp_mask, new_eflags);
2582	#if defined(VBOX) && defined(DEBUG)
2583	printf("iret: new CS %04X\n", new_cs);
2584	printf("iret: new EIP %08X\n", new_eip);
2585	printf("iret: new EFLAGS %08X\n", new_eflags);
2586	printf("iret: EAX=%08x\n", EAX);
2587	#endif
2588
2589	if (new_eflags & VM_MASK)
2590	goto return_to_vm86;
2591	}
2592	} else {
2593	/* 16 bits */
2594	POPW(ssp, sp, sp_mask, new_eip);
2595	POPW(ssp, sp, sp_mask, new_cs);
2596	if (is_iret)
2597	POPW(ssp, sp, sp_mask, new_eflags);
2598	}
2599	#ifdef DEBUG_PCALL
2600	if (loglevel & CPU_LOG_PCALL) {
2601	fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2602	new_cs, new_eip, shift, addend);
2603	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2604	}
2605	#endif
2606	if ((new_cs & 0xfffc) == 0)
2607	{
2608	#if defined(VBOX) && defined(DEBUG)
2609	printf("new_cs & 0xfffc) == 0\n");
2610	#endif
2611	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2612	}
2613	if (load_segment(&e1, &e2, new_cs) != 0)
2614	{
2615	#if defined(VBOX) && defined(DEBUG)
2616	printf("load_segment failed\n");
2617	#endif
2618	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2619	}
2620	if (!(e2 & DESC_S_MASK) \|\|
2621	!(e2 & DESC_CS_MASK))
2622	{
2623	#if defined(VBOX) && defined(DEBUG)
2624	printf("e2 mask %08x\n", e2);
2625	#endif
2626	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2627	}
2628	cpl = env->hflags & HF_CPL_MASK;
2629	rpl = new_cs & 3;
2630	if (rpl < cpl)
2631	{
2632	#if defined(VBOX) && defined(DEBUG)
2633	printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2634	#endif
2635	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2636	}
2637	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2638	if (e2 & DESC_C_MASK) {
2639	if (dpl > rpl)
2640	{
2641	#if defined(VBOX) && defined(DEBUG)
2642	printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2643	#endif
2644	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2645	}
2646	} else {
2647	if (dpl != rpl)
2648	{
2649	#if defined(VBOX) && defined(DEBUG)
2650	printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2651	#endif
2652	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2653	}
2654	}
2655	if (!(e2 & DESC_P_MASK))
2656	{
2657	#if defined(VBOX) && defined(DEBUG)
2658	printf("DESC_P_MASK e2=%08x\n", e2);
2659	#endif
2660	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2661	}
2662	sp += addend;
2663	if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) \|\|
2664	((env->hflags & HF_CS64_MASK) && !is_iret))) {
2665	/* return to same priledge level */
2666	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2667	get_seg_base(e1, e2),
2668	get_seg_limit(e1, e2),
2669	e2);
2670	} else {
2671	/* return to different priviledge level */
2672	#ifdef TARGET_X86_64
2673	if (shift == 2) {
2674	POPQ(sp, new_esp);
2675	POPQ(sp, new_ss);
2676	new_ss &= 0xffff;
2677	} else
2678	#endif
2679	if (shift == 1) {
2680	/* 32 bits */
2681	POPL(ssp, sp, sp_mask, new_esp);
2682	POPL(ssp, sp, sp_mask, new_ss);
2683	new_ss &= 0xffff;
2684	} else {
2685	/* 16 bits */
2686	POPW(ssp, sp, sp_mask, new_esp);
2687	POPW(ssp, sp, sp_mask, new_ss);
2688	}
2689	#ifdef DEBUG_PCALL
2690	if (loglevel & CPU_LOG_PCALL) {
2691	fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2692	new_ss, new_esp);
2693	}
2694	#endif
2695	if ((new_ss & 0xfffc) == 0) {
2696	#ifdef TARGET_X86_64
2697	/* NULL ss is allowed in long mode if cpl != 3*/
2698	/* XXX: test CS64 ? */
2699	if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2700	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2701	0, 0xffffffff,
2702	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2703	DESC_S_MASK \| (rpl << DESC_DPL_SHIFT) \|
2704	DESC_W_MASK \| DESC_A_MASK);
2705	ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
2706	} else
2707	#endif
2708	{
2709	raise_exception_err(EXCP0D_GPF, 0);
2710	}
2711	} else {
2712	if ((new_ss & 3) != rpl)
2713	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2714	if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2715	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2716	if (!(ss_e2 & DESC_S_MASK) \|\|
2717	(ss_e2 & DESC_CS_MASK) \|\|
2718	!(ss_e2 & DESC_W_MASK))
2719	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2720	dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2721	if (dpl != rpl)
2722	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2723	if (!(ss_e2 & DESC_P_MASK))
2724	raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2725	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2726	get_seg_base(ss_e1, ss_e2),
2727	get_seg_limit(ss_e1, ss_e2),
2728	ss_e2);
2729	}
2730
2731	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2732	get_seg_base(e1, e2),
2733	get_seg_limit(e1, e2),
2734	e2);
2735	cpu_x86_set_cpl(env, rpl);
2736	sp = new_esp;
2737	#ifdef TARGET_X86_64
2738	if (env->hflags & HF_CS64_MASK)
2739	sp_mask = -1;
2740	else
2741	#endif
2742	sp_mask = get_sp_mask(ss_e2);
2743
2744	/* validate data segments */
2745	validate_seg(R_ES, rpl);
2746	validate_seg(R_DS, rpl);
2747	validate_seg(R_FS, rpl);
2748	validate_seg(R_GS, rpl);
2749
2750	sp += addend;
2751	}
2752	SET_ESP(sp, sp_mask);
2753	env->eip = new_eip;
2754	if (is_iret) {
2755	/* NOTE: 'cpl' is the _old_ CPL */
2756	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2757	if (cpl == 0)
2758	#ifdef VBOX
2759	eflags_mask \|= IOPL_MASK \| VIF_MASK \| VIP_MASK;
2760	#else
2761	eflags_mask \|= IOPL_MASK;
2762	#endif
2763	iopl = (env->eflags >> IOPL_SHIFT) & 3;
2764	if (cpl <= iopl)
2765	eflags_mask \|= IF_MASK;
2766	if (shift == 0)
2767	eflags_mask &= 0xffff;
2768	load_eflags(new_eflags, eflags_mask);
2769	}
2770	return;
2771
2772	return_to_vm86:
2773
2774	#if 0 // defined(VBOX) && defined(DEBUG)
2775	printf("V86: new CS %04X\n", new_cs);
2776	printf("V86: Descriptor %08X:%08X\n", e2, e1);
2777	printf("V86: new EIP %08X\n", new_eip);
2778	printf("V86: new EFLAGS %08X\n", new_eflags);
2779	#endif
2780
2781	POPL(ssp, sp, sp_mask, new_esp);
2782	POPL(ssp, sp, sp_mask, new_ss);
2783	POPL(ssp, sp, sp_mask, new_es);
2784	POPL(ssp, sp, sp_mask, new_ds);
2785	POPL(ssp, sp, sp_mask, new_fs);
2786	POPL(ssp, sp, sp_mask, new_gs);
2787
2788	/* modify processor state */
2789	load_eflags(new_eflags, TF_MASK \| AC_MASK \| ID_MASK \|
2790	IF_MASK \| IOPL_MASK \| VM_MASK \| NT_MASK \| VIF_MASK \| VIP_MASK);
2791	load_seg_vm(R_CS, new_cs & 0xffff);
2792	cpu_x86_set_cpl(env, 3);
2793	load_seg_vm(R_SS, new_ss & 0xffff);
2794	load_seg_vm(R_ES, new_es & 0xffff);
2795	load_seg_vm(R_DS, new_ds & 0xffff);
2796	load_seg_vm(R_FS, new_fs & 0xffff);
2797	load_seg_vm(R_GS, new_gs & 0xffff);
2798
2799	env->eip = new_eip & 0xffff;
2800	ESP = new_esp;
2801	}
2802
2803	void helper_iret_protected(int shift, int next_eip)
2804	{
2805	int tss_selector, type;
2806	uint32_t e1, e2;
2807
2808	#ifdef VBOX
2809	remR3TrapClear(env->pVM);
2810	#endif
2811
2812	/* specific case for TSS */
2813	if (env->eflags & NT_MASK) {
2814	#ifdef TARGET_X86_64
2815	if (env->hflags & HF_LMA_MASK)
2816	raise_exception_err(EXCP0D_GPF, 0);
2817	#endif
2818	tss_selector = lduw_kernel(env->tr.base + 0);
2819	if (tss_selector & 4)
2820	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2821	if (load_segment(&e1, &e2, tss_selector) != 0)
2822	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2823	type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2824	/* NOTE: we check both segment and busy TSS */
2825	if (type != 3)
2826	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2827	switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2828	} else {
2829	helper_ret_protected(shift, 1, 0);
2830	}
2831	#ifdef USE_KQEMU
2832	if (kqemu_is_ok(env)) {
2833	CC_OP = CC_OP_EFLAGS;
2834	env->exception_index = -1;
2835	cpu_loop_exit();
2836	}
2837	#endif
2838	}
2839
2840	void helper_lret_protected(int shift, int addend)
2841	{
2842	helper_ret_protected(shift, 0, addend);
2843	#ifdef USE_KQEMU
2844	if (kqemu_is_ok(env)) {
2845	env->exception_index = -1;
2846	cpu_loop_exit();
2847	}
2848	#endif
2849	}
2850
2851	void helper_sysenter(void)
2852	{
2853	if (env->sysenter_cs == 0) {
2854	raise_exception_err(EXCP0D_GPF, 0);
2855	}
2856	env->eflags &= ~(VM_MASK \| IF_MASK \| RF_MASK);
2857	cpu_x86_set_cpl(env, 0);
2858	cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2859	0, 0xffffffff,
2860	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2861	DESC_S_MASK \|
2862	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2863	cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2864	0, 0xffffffff,
2865	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2866	DESC_S_MASK \|
2867	DESC_W_MASK \| DESC_A_MASK);
2868	ESP = env->sysenter_esp;
2869	EIP = env->sysenter_eip;
2870	}
2871
2872	void helper_sysexit(void)
2873	{
2874	int cpl;
2875
2876	cpl = env->hflags & HF_CPL_MASK;
2877	if (env->sysenter_cs == 0 \|\| cpl != 0) {
2878	raise_exception_err(EXCP0D_GPF, 0);
2879	}
2880	cpu_x86_set_cpl(env, 3);
2881	cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) \| 3,
2882	0, 0xffffffff,
2883	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2884	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2885	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2886	cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) \| 3,
2887	0, 0xffffffff,
2888	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2889	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2890	DESC_W_MASK \| DESC_A_MASK);
2891	ESP = ECX;
2892	EIP = EDX;
2893	#ifdef USE_KQEMU
2894	if (kqemu_is_ok(env)) {
2895	env->exception_index = -1;
2896	cpu_loop_exit();
2897	}
2898	#endif
2899	}
2900
2901	void helper_movl_crN_T0(int reg)
2902	{
2903	#if !defined(CONFIG_USER_ONLY)
2904	switch(reg) {
2905	case 0:
2906	cpu_x86_update_cr0(env, T0);
2907	break;
2908	case 3:
2909	cpu_x86_update_cr3(env, T0);
2910	break;
2911	case 4:
2912	cpu_x86_update_cr4(env, T0);
2913	break;
2914	case 8:
2915	cpu_set_apic_tpr(env, T0);
2916	break;
2917	default:
2918	env->cr[reg] = T0;
2919	break;
2920	}
2921	#endif
2922	}
2923
2924	/* XXX: do more */
2925	void helper_movl_drN_T0(int reg)
2926	{
2927	env->dr[reg] = T0;
2928	}
2929
2930	void helper_invlpg(target_ulong addr)
2931	{
2932	cpu_x86_flush_tlb(env, addr);
2933	}
2934
2935	void helper_rdtsc(void)
2936	{
2937	uint64_t val;
2938
2939	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2940	raise_exception(EXCP0D_GPF);
2941	}
2942	val = cpu_get_tsc(env);
2943	EAX = (uint32_t)(val);
2944	EDX = (uint32_t)(val >> 32);
2945	}
2946
2947	#if defined(CONFIG_USER_ONLY)
2948	void helper_wrmsr(void)
2949	{
2950	}
2951
2952	void helper_rdmsr(void)
2953	{
2954	}
2955	#else
2956	void helper_wrmsr(void)
2957	{
2958	uint64_t val;
2959
2960	val = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
2961
2962	switch((uint32_t)ECX) {
2963	case MSR_IA32_SYSENTER_CS:
2964	env->sysenter_cs = val & 0xffff;
2965	break;
2966	case MSR_IA32_SYSENTER_ESP:
2967	env->sysenter_esp = val;
2968	break;
2969	case MSR_IA32_SYSENTER_EIP:
2970	env->sysenter_eip = val;
2971	break;
2972	case MSR_IA32_APICBASE:
2973	cpu_set_apic_base(env, val);
2974	break;
2975	case MSR_EFER:
2976	{
2977	uint64_t update_mask;
2978	update_mask = 0;
2979	if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
2980	update_mask \|= MSR_EFER_SCE;
2981	if (env->cpuid_ext2_features & CPUID_EXT2_LM)
2982	update_mask \|= MSR_EFER_LME;
2983	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
2984	update_mask \|= MSR_EFER_FFXSR;
2985	if (env->cpuid_ext2_features & CPUID_EXT2_NX)
2986	update_mask \|= MSR_EFER_NXE;
2987	env->efer = (env->efer & ~update_mask) \|
2988	(val & update_mask);
2989	}
2990	break;
2991	case MSR_STAR:
2992	env->star = val;
2993	break;
2994	case MSR_PAT:
2995	env->pat = val;
2996	break;
2997	#ifdef TARGET_X86_64
2998	case MSR_LSTAR:
2999	env->lstar = val;
3000	break;
3001	case MSR_CSTAR:
3002	env->cstar = val;
3003	break;
3004	case MSR_FMASK:
3005	env->fmask = val;
3006	break;
3007	case MSR_FSBASE:
3008	env->segs[R_FS].base = val;
3009	break;
3010	case MSR_GSBASE:
3011	env->segs[R_GS].base = val;
3012	break;
3013	case MSR_KERNELGSBASE:
3014	env->kernelgsbase = val;
3015	break;
3016	#endif
3017	default:
3018	/* XXX: exception ? */
3019	break;
3020	}
3021	}
3022
3023	void helper_rdmsr(void)
3024	{
3025	uint64_t val;
3026	switch((uint32_t)ECX) {
3027	case MSR_IA32_SYSENTER_CS:
3028	val = env->sysenter_cs;
3029	break;
3030	case MSR_IA32_SYSENTER_ESP:
3031	val = env->sysenter_esp;
3032	break;
3033	case MSR_IA32_SYSENTER_EIP:
3034	val = env->sysenter_eip;
3035	break;
3036	case MSR_IA32_APICBASE:
3037	val = cpu_get_apic_base(env);
3038	break;
3039	case MSR_EFER:
3040	val = env->efer;
3041	break;
3042	case MSR_STAR:
3043	val = env->star;
3044	break;
3045	case MSR_PAT:
3046	val = env->pat;
3047	break;
3048	#ifdef TARGET_X86_64
3049	case MSR_LSTAR:
3050	val = env->lstar;
3051	break;
3052	case MSR_CSTAR:
3053	val = env->cstar;
3054	break;
3055	case MSR_FMASK:
3056	val = env->fmask;
3057	break;
3058	case MSR_FSBASE:
3059	val = env->segs[R_FS].base;
3060	break;
3061	case MSR_GSBASE:
3062	val = env->segs[R_GS].base;
3063	break;
3064	case MSR_KERNELGSBASE:
3065	val = env->kernelgsbase;
3066	break;
3067	#endif
3068	default:
3069	/* XXX: exception ? */
3070	val = 0;
3071	break;
3072	}
3073	EAX = (uint32_t)(val);
3074	EDX = (uint32_t)(val >> 32);
3075	}
3076	#endif
3077
3078	void helper_lsl(void)
3079	{
3080	unsigned int selector, limit;
3081	uint32_t e1, e2, eflags;
3082	int rpl, dpl, cpl, type;
3083
3084	eflags = cc_table[CC_OP].compute_all();
3085	selector = T0 & 0xffff;
3086	if (load_segment(&e1, &e2, selector) != 0)
3087	goto fail;
3088	rpl = selector & 3;
3089	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3090	cpl = env->hflags & HF_CPL_MASK;
3091	if (e2 & DESC_S_MASK) {
3092	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3093	/* conforming */
3094	} else {
3095	if (dpl < cpl \|\| dpl < rpl)
3096	goto fail;
3097	}
3098	} else {
3099	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3100	switch(type) {
3101	case 1:
3102	case 2:
3103	case 3:
3104	case 9:
3105	case 11:
3106	break;
3107	default:
3108	goto fail;
3109	}
3110	if (dpl < cpl \|\| dpl < rpl) {
3111	fail:
3112	CC_SRC = eflags & ~CC_Z;
3113	return;
3114	}
3115	}
3116	limit = get_seg_limit(e1, e2);
3117	T1 = limit;
3118	CC_SRC = eflags \| CC_Z;
3119	}
3120
3121	void helper_lar(void)
3122	{
3123	unsigned int selector;
3124	uint32_t e1, e2, eflags;
3125	int rpl, dpl, cpl, type;
3126
3127	eflags = cc_table[CC_OP].compute_all();
3128	selector = T0 & 0xffff;
3129	if ((selector & 0xfffc) == 0)
3130	goto fail;
3131	if (load_segment(&e1, &e2, selector) != 0)
3132	goto fail;
3133	rpl = selector & 3;
3134	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3135	cpl = env->hflags & HF_CPL_MASK;
3136	if (e2 & DESC_S_MASK) {
3137	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3138	/* conforming */
3139	} else {
3140	if (dpl < cpl \|\| dpl < rpl)
3141	goto fail;
3142	}
3143	} else {
3144	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3145	switch(type) {
3146	case 1:
3147	case 2:
3148	case 3:
3149	case 4:
3150	case 5:
3151	case 9:
3152	case 11:
3153	case 12:
3154	break;
3155	default:
3156	goto fail;
3157	}
3158	if (dpl < cpl \|\| dpl < rpl) {
3159	fail:
3160	CC_SRC = eflags & ~CC_Z;
3161	return;
3162	}
3163	}
3164	T1 = e2 & 0x00f0ff00;
3165	CC_SRC = eflags \| CC_Z;
3166	}
3167
3168	void helper_verr(void)
3169	{
3170	unsigned int selector;
3171	uint32_t e1, e2, eflags;
3172	int rpl, dpl, cpl;
3173
3174	eflags = cc_table[CC_OP].compute_all();
3175	selector = T0 & 0xffff;
3176	if ((selector & 0xfffc) == 0)
3177	goto fail;
3178	if (load_segment(&e1, &e2, selector) != 0)
3179	goto fail;
3180	if (!(e2 & DESC_S_MASK))
3181	goto fail;
3182	rpl = selector & 3;
3183	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3184	cpl = env->hflags & HF_CPL_MASK;
3185	if (e2 & DESC_CS_MASK) {
3186	if (!(e2 & DESC_R_MASK))
3187	goto fail;
3188	if (!(e2 & DESC_C_MASK)) {
3189	if (dpl < cpl \|\| dpl < rpl)
3190	goto fail;
3191	}
3192	} else {
3193	if (dpl < cpl \|\| dpl < rpl) {
3194	fail:
3195	CC_SRC = eflags & ~CC_Z;
3196	return;
3197	}
3198	}
3199	CC_SRC = eflags \| CC_Z;
3200	}
3201
3202	void helper_verw(void)
3203	{
3204	unsigned int selector;
3205	uint32_t e1, e2, eflags;
3206	int rpl, dpl, cpl;
3207
3208	eflags = cc_table[CC_OP].compute_all();
3209	selector = T0 & 0xffff;
3210	if ((selector & 0xfffc) == 0)
3211	goto fail;
3212	if (load_segment(&e1, &e2, selector) != 0)
3213	goto fail;
3214	if (!(e2 & DESC_S_MASK))
3215	goto fail;
3216	rpl = selector & 3;
3217	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3218	cpl = env->hflags & HF_CPL_MASK;
3219	if (e2 & DESC_CS_MASK) {
3220	goto fail;
3221	} else {
3222	if (dpl < cpl \|\| dpl < rpl)
3223	goto fail;
3224	if (!(e2 & DESC_W_MASK)) {
3225	fail:
3226	CC_SRC = eflags & ~CC_Z;
3227	return;
3228	}
3229	}
3230	CC_SRC = eflags \| CC_Z;
3231	}
3232
3233	/* FPU helpers */
3234
3235	void helper_fldt_ST0_A0(void)
3236	{
3237	int new_fpstt;
3238	new_fpstt = (env->fpstt - 1) & 7;
3239	env->fpregs[new_fpstt].d = helper_fldt(A0);
3240	env->fpstt = new_fpstt;
3241	env->fptags[new_fpstt] = 0; /* validate stack entry */
3242	}
3243
3244	void helper_fstt_ST0_A0(void)
3245	{
3246	helper_fstt(ST0, A0);
3247	}
3248
3249	void fpu_set_exception(int mask)
3250	{
3251	env->fpus \|= mask;
3252	if (env->fpus & (~env->fpuc & FPUC_EM))
3253	env->fpus \|= FPUS_SE \| FPUS_B;
3254	}
3255
3256	CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
3257	{
3258	if (b == 0.0)
3259	fpu_set_exception(FPUS_ZE);
3260	return a / b;
3261	}
3262
3263	void fpu_raise_exception(void)
3264	{
3265	if (env->cr[0] & CR0_NE_MASK) {
3266	raise_exception(EXCP10_COPR);
3267	}
3268	#if !defined(CONFIG_USER_ONLY)
3269	else {
3270	cpu_set_ferr(env);
3271	}
3272	#endif
3273	}
3274
3275	/* BCD ops */
3276
3277	void helper_fbld_ST0_A0(void)
3278	{
3279	CPU86_LDouble tmp;
3280	uint64_t val;
3281	unsigned int v;
3282	int i;
3283
3284	val = 0;
3285	for(i = 8; i >= 0; i--) {
3286	v = ldub(A0 + i);
3287	val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
3288	}
3289	tmp = val;
3290	if (ldub(A0 + 9) & 0x80)
3291	tmp = -tmp;
3292	fpush();
3293	ST0 = tmp;
3294	}
3295
3296	void helper_fbst_ST0_A0(void)
3297	{
3298	int v;
3299	target_ulong mem_ref, mem_end;
3300	int64_t val;
3301
3302	val = floatx_to_int64(ST0, &env->fp_status);
3303	mem_ref = A0;
3304	mem_end = mem_ref + 9;
3305	if (val < 0) {
3306	stb(mem_end, 0x80);
3307	val = -val;
3308	} else {
3309	stb(mem_end, 0x00);
3310	}
3311	while (mem_ref < mem_end) {
3312	if (val == 0)
3313	break;
3314	v = val % 100;
3315	val = val / 100;
3316	v = ((v / 10) << 4) \| (v % 10);
3317	stb(mem_ref++, v);
3318	}
3319	while (mem_ref < mem_end) {
3320	stb(mem_ref++, 0);
3321	}
3322	}
3323
3324	void helper_f2xm1(void)
3325	{
3326	ST0 = pow(2.0,ST0) - 1.0;
3327	}
3328
3329	void helper_fyl2x(void)
3330	{
3331	CPU86_LDouble fptemp;
3332
3333	fptemp = ST0;
3334	if (fptemp>0.0){
3335	fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3336	ST1 *= fptemp;
3337	fpop();
3338	} else {
3339	env->fpus &= (~0x4700);
3340	env->fpus \|= 0x400;
3341	}
3342	}
3343
3344	void helper_fptan(void)
3345	{
3346	CPU86_LDouble fptemp;
3347
3348	fptemp = ST0;
3349	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3350	env->fpus \|= 0x400;
3351	} else {
3352	ST0 = tan(fptemp);
3353	fpush();
3354	ST0 = 1.0;
3355	env->fpus &= (~0x400); /* C2 <-- 0 */
3356	/* the above code is for \|arg\| < 2*52 only /
3357	}
3358	}
3359
3360	void helper_fpatan(void)
3361	{
3362	CPU86_LDouble fptemp, fpsrcop;
3363
3364	fpsrcop = ST1;
3365	fptemp = ST0;
3366	ST1 = atan2(fpsrcop,fptemp);
3367	fpop();
3368	}
3369
3370	void helper_fxtract(void)
3371	{
3372	CPU86_LDoubleU temp;
3373	unsigned int expdif;
3374
3375	temp.d = ST0;
3376	expdif = EXPD(temp) - EXPBIAS;
3377	/DP exponent bias/
3378	ST0 = expdif;
3379	fpush();
3380	BIASEXPONENT(temp);
3381	ST0 = temp.d;
3382	}
3383
3384	void helper_fprem1(void)
3385	{
3386	CPU86_LDouble dblq, fpsrcop, fptemp;
3387	CPU86_LDoubleU fpsrcop1, fptemp1;
3388	int expdif;
3389	int q;
3390
3391	fpsrcop = ST0;
3392	fptemp = ST1;
3393	fpsrcop1.d = fpsrcop;
3394	fptemp1.d = fptemp;
3395	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3396	if (expdif < 53) {
3397	dblq = fpsrcop / fptemp;
3398	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3399	ST0 = fpsrcop - fptemp*dblq;
3400	q = (int)dblq; /* cutting off top bits is assumed here */
3401	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3402	/* (C0,C1,C3) <-- (q2,q1,q0) */
3403	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3404	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3405	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3406	} else {
3407	env->fpus \|= 0x400; /* C2 <-- 1 */
3408	fptemp = pow(2.0, expdif-50);
3409	fpsrcop = (ST0 / ST1) / fptemp;
3410	/* fpsrcop = integer obtained by rounding to the nearest */
3411	fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3412	floor(fpsrcop): ceil(fpsrcop);
3413	ST0 -= (ST1 * fpsrcop * fptemp);
3414	}
3415	}
3416
3417	void helper_fprem(void)
3418	{
3419	CPU86_LDouble dblq, fpsrcop, fptemp;
3420	CPU86_LDoubleU fpsrcop1, fptemp1;
3421	int expdif;
3422	int q;
3423
3424	fpsrcop = ST0;
3425	fptemp = ST1;
3426	fpsrcop1.d = fpsrcop;
3427	fptemp1.d = fptemp;
3428	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3429	if ( expdif < 53 ) {
3430	dblq = fpsrcop / fptemp;
3431	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3432	ST0 = fpsrcop - fptemp*dblq;
3433	q = (int)dblq; /* cutting off top bits is assumed here */
3434	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3435	/* (C0,C1,C3) <-- (q2,q1,q0) */
3436	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3437	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3438	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3439	} else {
3440	env->fpus \|= 0x400; /* C2 <-- 1 */
3441	fptemp = pow(2.0, expdif-50);
3442	fpsrcop = (ST0 / ST1) / fptemp;
3443	/* fpsrcop = integer obtained by chopping */
3444	fpsrcop = (fpsrcop < 0.0)?
3445	-(floor(fabs(fpsrcop))): floor(fpsrcop);
3446	ST0 -= (ST1 * fpsrcop * fptemp);
3447	}
3448	}
3449
3450	void helper_fyl2xp1(void)
3451	{
3452	CPU86_LDouble fptemp;
3453
3454	fptemp = ST0;
3455	if ((fptemp+1.0)>0.0) {
3456	fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3457	ST1 *= fptemp;
3458	fpop();
3459	} else {
3460	env->fpus &= (~0x4700);
3461	env->fpus \|= 0x400;
3462	}
3463	}
3464
3465	void helper_fsqrt(void)
3466	{
3467	CPU86_LDouble fptemp;
3468
3469	fptemp = ST0;
3470	if (fptemp<0.0) {
3471	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3472	env->fpus \|= 0x400;
3473	}
3474	ST0 = sqrt(fptemp);
3475	}
3476
3477	void helper_fsincos(void)
3478	{
3479	CPU86_LDouble fptemp;
3480
3481	fptemp = ST0;
3482	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3483	env->fpus \|= 0x400;
3484	} else {
3485	ST0 = sin(fptemp);
3486	fpush();
3487	ST0 = cos(fptemp);
3488	env->fpus &= (~0x400); /* C2 <-- 0 */
3489	/* the above code is for \|arg\| < 2*63 only /
3490	}
3491	}
3492
3493	void helper_frndint(void)
3494	{
3495	ST0 = floatx_round_to_int(ST0, &env->fp_status);
3496	}
3497
3498	void helper_fscale(void)
3499	{
3500	ST0 = ldexp (ST0, (int)(ST1));
3501	}
3502
3503	void helper_fsin(void)
3504	{
3505	CPU86_LDouble fptemp;
3506
3507	fptemp = ST0;
3508	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3509	env->fpus \|= 0x400;
3510	} else {
3511	ST0 = sin(fptemp);
3512	env->fpus &= (~0x400); /* C2 <-- 0 */
3513	/* the above code is for \|arg\| < 2*53 only /
3514	}
3515	}
3516
3517	void helper_fcos(void)
3518	{
3519	CPU86_LDouble fptemp;
3520
3521	fptemp = ST0;
3522	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3523	env->fpus \|= 0x400;
3524	} else {
3525	ST0 = cos(fptemp);
3526	env->fpus &= (~0x400); /* C2 <-- 0 */
3527	/* the above code is for \|arg5 < 2*63 only /
3528	}
3529	}
3530
3531	void helper_fxam_ST0(void)
3532	{
3533	CPU86_LDoubleU temp;
3534	int expdif;
3535
3536	temp.d = ST0;
3537
3538	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3539	if (SIGND(temp))
3540	env->fpus \|= 0x200; /* C1 <-- 1 */
3541
3542	/* XXX: test fptags too */
3543	expdif = EXPD(temp);
3544	if (expdif == MAXEXPD) {
3545	#ifdef USE_X86LDOUBLE
3546	if (MANTD(temp) == 0x8000000000000000ULL)
3547	#else
3548	if (MANTD(temp) == 0)
3549	#endif
3550	env->fpus \|= 0x500 /Infinity/;
3551	else
3552	env->fpus \|= 0x100 /NaN/;
3553	} else if (expdif == 0) {
3554	if (MANTD(temp) == 0)
3555	env->fpus \|= 0x4000 /Zero/;
3556	else
3557	env->fpus \|= 0x4400 /Denormal/;
3558	} else {
3559	env->fpus \|= 0x400;
3560	}
3561	}
3562
3563	void helper_fstenv(target_ulong ptr, int data32)
3564	{
3565	int fpus, fptag, exp, i;
3566	uint64_t mant;
3567	CPU86_LDoubleU tmp;
3568
3569	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3570	fptag = 0;
3571	for (i=7; i>=0; i--) {
3572	fptag <<= 2;
3573	if (env->fptags[i]) {
3574	fptag \|= 3;
3575	} else {
3576	tmp.d = env->fpregs[i].d;
3577	exp = EXPD(tmp);
3578	mant = MANTD(tmp);
3579	if (exp == 0 && mant == 0) {
3580	/* zero */
3581	fptag \|= 1;
3582	} else if (exp == 0 \|\| exp == MAXEXPD
3583	#ifdef USE_X86LDOUBLE
3584	\|\| (mant & (1LL << 63)) == 0
3585	#endif
3586	) {
3587	/* NaNs, infinity, denormal */
3588	fptag \|= 2;
3589	}
3590	}
3591	}
3592	if (data32) {
3593	/* 32 bit */
3594	stl(ptr, env->fpuc);
3595	stl(ptr + 4, fpus);
3596	stl(ptr + 8, fptag);
3597	stl(ptr + 12, 0); /* fpip */
3598	stl(ptr + 16, 0); /* fpcs */
3599	stl(ptr + 20, 0); /* fpoo */
3600	stl(ptr + 24, 0); /* fpos */
3601	} else {
3602	/* 16 bit */
3603	stw(ptr, env->fpuc);
3604	stw(ptr + 2, fpus);
3605	stw(ptr + 4, fptag);
3606	stw(ptr + 6, 0);
3607	stw(ptr + 8, 0);
3608	stw(ptr + 10, 0);
3609	stw(ptr + 12, 0);
3610	}
3611	}
3612
3613	void helper_fldenv(target_ulong ptr, int data32)
3614	{
3615	int i, fpus, fptag;
3616
3617	if (data32) {
3618	env->fpuc = lduw(ptr);
3619	fpus = lduw(ptr + 4);
3620	fptag = lduw(ptr + 8);
3621	}
3622	else {
3623	env->fpuc = lduw(ptr);
3624	fpus = lduw(ptr + 2);
3625	fptag = lduw(ptr + 4);
3626	}
3627	env->fpstt = (fpus >> 11) & 7;
3628	env->fpus = fpus & ~0x3800;
3629	for(i = 0;i < 8; i++) {
3630	env->fptags[i] = ((fptag & 3) == 3);
3631	fptag >>= 2;
3632	}
3633	}
3634
3635	void helper_fsave(target_ulong ptr, int data32)
3636	{
3637	CPU86_LDouble tmp;
3638	int i;
3639
3640	helper_fstenv(ptr, data32);
3641
3642	ptr += (14 << data32);
3643	for(i = 0;i < 8; i++) {
3644	tmp = ST(i);
3645	helper_fstt(tmp, ptr);
3646	ptr += 10;
3647	}
3648
3649	/* fninit */
3650	env->fpus = 0;
3651	env->fpstt = 0;
3652	env->fpuc = 0x37f;
3653	env->fptags[0] = 1;
3654	env->fptags[1] = 1;
3655	env->fptags[2] = 1;
3656	env->fptags[3] = 1;
3657	env->fptags[4] = 1;
3658	env->fptags[5] = 1;
3659	env->fptags[6] = 1;
3660	env->fptags[7] = 1;
3661	}
3662
3663	void helper_frstor(target_ulong ptr, int data32)
3664	{
3665	CPU86_LDouble tmp;
3666	int i;
3667
3668	helper_fldenv(ptr, data32);
3669	ptr += (14 << data32);
3670
3671	for(i = 0;i < 8; i++) {
3672	tmp = helper_fldt(ptr);
3673	ST(i) = tmp;
3674	ptr += 10;
3675	}
3676	}
3677
3678	void helper_fxsave(target_ulong ptr, int data64)
3679	{
3680	int fpus, fptag, i, nb_xmm_regs;
3681	CPU86_LDouble tmp;
3682	target_ulong addr;
3683
3684	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3685	fptag = 0;
3686	for(i = 0; i < 8; i++) {
3687	fptag \|= (env->fptags[i] << i);
3688	}
3689	stw(ptr, env->fpuc);
3690	stw(ptr + 2, fpus);
3691	stw(ptr + 4, fptag ^ 0xff);
3692
3693	addr = ptr + 0x20;
3694	for(i = 0;i < 8; i++) {
3695	tmp = ST(i);
3696	helper_fstt(tmp, addr);
3697	addr += 16;
3698	}
3699
3700	if (env->cr[4] & CR4_OSFXSR_MASK) {
3701	/* XXX: finish it */
3702	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3703	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3704	nb_xmm_regs = 8 << data64;
3705	addr = ptr + 0xa0;
3706	for(i = 0; i < nb_xmm_regs; i++) {
3707	stq(addr, env->xmm_regs[i].XMM_Q(0));
3708	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3709	addr += 16;
3710	}
3711	}
3712	}
3713
3714	void helper_fxrstor(target_ulong ptr, int data64)
3715	{
3716	int i, fpus, fptag, nb_xmm_regs;
3717	CPU86_LDouble tmp;
3718	target_ulong addr;
3719
3720	env->fpuc = lduw(ptr);
3721	fpus = lduw(ptr + 2);
3722	fptag = lduw(ptr + 4);
3723	env->fpstt = (fpus >> 11) & 7;
3724	env->fpus = fpus & ~0x3800;
3725	fptag ^= 0xff;
3726	for(i = 0;i < 8; i++) {
3727	env->fptags[i] = ((fptag >> i) & 1);
3728	}
3729
3730	addr = ptr + 0x20;
3731	for(i = 0;i < 8; i++) {
3732	tmp = helper_fldt(addr);
3733	ST(i) = tmp;
3734	addr += 16;
3735	}
3736
3737	if (env->cr[4] & CR4_OSFXSR_MASK) {
3738	/* XXX: finish it */
3739	env->mxcsr = ldl(ptr + 0x18);
3740	//ldl(ptr + 0x1c);
3741	nb_xmm_regs = 8 << data64;
3742	addr = ptr + 0xa0;
3743	for(i = 0; i < nb_xmm_regs; i++) {
3744	#if !defined(VBOX) \|\| __GNUC__ < 4
3745	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3746	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3747	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3748	# if 1
3749	env->xmm_regs[i].XMM_L(0) = ldl(addr);
3750	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3751	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3752	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3753	# else
3754	/* this works fine on Mac OS X, gcc 4.0.1 */
3755	uint64_t u64 = ldq(addr);
3756	env->xmm_regs[i].XMM_Q(0);
3757	u64 = ldq(addr + 4);
3758	env->xmm_regs[i].XMM_Q(1) = u64;
3759	# endif
3760	#endif
3761	addr += 16;
3762	}
3763	}
3764	}
3765
3766	#ifndef USE_X86LDOUBLE
3767
3768	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3769	{
3770	CPU86_LDoubleU temp;
3771	int e;
3772
3773	temp.d = f;
3774	/* mantissa */
3775	*pmant = (MANTD(temp) << 11) \| (1LL << 63);
3776	/* exponent + sign */
3777	e = EXPD(temp) - EXPBIAS + 16383;
3778	e \|= SIGND(temp) >> 16;
3779	*pexp = e;
3780	}
3781
3782	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3783	{
3784	CPU86_LDoubleU temp;
3785	int e;
3786	uint64_t ll;
3787
3788	/* XXX: handle overflow ? */
3789	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3790	e \|= (upper >> 4) & 0x800; /* sign */
3791	ll = (mant >> 11) & ((1LL << 52) - 1);
3792	#ifdef __arm__
3793	temp.l.upper = (e << 20) \| (ll >> 32);
3794	temp.l.lower = ll;
3795	#else
3796	temp.ll = ll \| ((uint64_t)e << 52);
3797	#endif
3798	return temp.d;
3799	}
3800
3801	#else
3802
3803	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3804	{
3805	CPU86_LDoubleU temp;
3806
3807	temp.d = f;
3808	*pmant = temp.l.lower;
3809	*pexp = temp.l.upper;
3810	}
3811
3812	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3813	{
3814	CPU86_LDoubleU temp;
3815
3816	temp.l.upper = upper;
3817	temp.l.lower = mant;
3818	return temp.d;
3819	}
3820	#endif
3821
3822	#ifdef TARGET_X86_64
3823
3824	//#define DEBUG_MULDIV
3825
3826	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3827	{
3828	*plow += a;
3829	/* carry test */
3830	if (*plow < a)
3831	(*phigh)++;
3832	*phigh += b;
3833	}
3834
3835	static void neg128(uint64_t plow, uint64_t phigh)
3836	{
3837	plow = ~ plow;
3838	phigh = ~ phigh;
3839	add128(plow, phigh, 1, 0);
3840	}
3841
3842	static void mul64(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3843	{
3844	uint32_t a0, a1, b0, b1;
3845	uint64_t v;
3846
3847	a0 = a;
3848	a1 = a >> 32;
3849
3850	b0 = b;
3851	b1 = b >> 32;
3852
3853	v = (uint64_t)a0 * (uint64_t)b0;
3854	*plow = v;
3855	*phigh = 0;
3856
3857	v = (uint64_t)a0 * (uint64_t)b1;
3858	add128(plow, phigh, v << 32, v >> 32);
3859
3860	v = (uint64_t)a1 * (uint64_t)b0;
3861	add128(plow, phigh, v << 32, v >> 32);
3862
3863	v = (uint64_t)a1 * (uint64_t)b1;
3864	*phigh += v;
3865	#ifdef DEBUG_MULDIV
3866	printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
3867	a, b, phigh, plow);
3868	#endif
3869	}
3870
3871	static void imul64(uint64_t plow, uint64_t phigh, int64_t a, int64_t b)
3872	{
3873	int sa, sb;
3874	sa = (a < 0);
3875	if (sa)
3876	a = -a;
3877	sb = (b < 0);
3878	if (sb)
3879	b = -b;
3880	mul64(plow, phigh, a, b);
3881	if (sa ^ sb) {
3882	neg128(plow, phigh);
3883	}
3884	}
3885
3886	/* return TRUE if overflow */
3887	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
3888	{
3889	uint64_t q, r, a1, a0;
3890	int i, qb, ab;
3891
3892	a0 = *plow;
3893	a1 = *phigh;
3894	if (a1 == 0) {
3895	q = a0 / b;
3896	r = a0 % b;
3897	*plow = q;
3898	*phigh = r;
3899	} else {
3900	if (a1 >= b)
3901	return 1;
3902	/* XXX: use a better algorithm */
3903	for(i = 0; i < 64; i++) {
3904	ab = a1 >> 63;
3905	a1 = (a1 << 1) \| (a0 >> 63);
3906	if (ab \|\| a1 >= b) {
3907	a1 -= b;
3908	qb = 1;
3909	} else {
3910	qb = 0;
3911	}
3912	a0 = (a0 << 1) \| qb;
3913	}
3914	#if defined(DEBUG_MULDIV)
3915	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
3916	phigh, plow, b, a0, a1);
3917	#endif
3918	*plow = a0;
3919	*phigh = a1;
3920	}
3921	return 0;
3922	}
3923
3924	/* return TRUE if overflow */
3925	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
3926	{
3927	int sa, sb;
3928	sa = ((int64_t)*phigh < 0);
3929	if (sa)
3930	neg128(plow, phigh);
3931	sb = (b < 0);
3932	if (sb)
3933	b = -b;
3934	if (div64(plow, phigh, b) != 0)
3935	return 1;
3936	if (sa ^ sb) {
3937	if (*plow > (1ULL << 63))
3938	return 1;
3939	plow = - plow;
3940	} else {
3941	if (*plow >= (1ULL << 63))
3942	return 1;
3943	}
3944	if (sa)
3945	phigh = - phigh;
3946	return 0;
3947	}
3948
3949	void helper_mulq_EAX_T0(void)
3950	{
3951	uint64_t r0, r1;
3952
3953	mul64(&r0, &r1, EAX, T0);
3954	EAX = r0;
3955	EDX = r1;
3956	CC_DST = r0;
3957	CC_SRC = r1;
3958	}
3959
3960	void helper_imulq_EAX_T0(void)
3961	{
3962	uint64_t r0, r1;
3963
3964	imul64(&r0, &r1, EAX, T0);
3965	EAX = r0;
3966	EDX = r1;
3967	CC_DST = r0;
3968	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3969	}
3970
3971	void helper_imulq_T0_T1(void)
3972	{
3973	uint64_t r0, r1;
3974
3975	imul64(&r0, &r1, T0, T1);
3976	T0 = r0;
3977	CC_DST = r0;
3978	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3979	}
3980
3981	void helper_divq_EAX_T0(void)
3982	{
3983	uint64_t r0, r1;
3984	if (T0 == 0) {
3985	raise_exception(EXCP00_DIVZ);
3986	}
3987	r0 = EAX;
3988	r1 = EDX;
3989	if (div64(&r0, &r1, T0))
3990	raise_exception(EXCP00_DIVZ);
3991	EAX = r0;
3992	EDX = r1;
3993	}
3994
3995	void helper_idivq_EAX_T0(void)
3996	{
3997	uint64_t r0, r1;
3998	if (T0 == 0) {
3999	raise_exception(EXCP00_DIVZ);
4000	}
4001	r0 = EAX;
4002	r1 = EDX;
4003	if (idiv64(&r0, &r1, T0))
4004	raise_exception(EXCP00_DIVZ);
4005	EAX = r0;
4006	EDX = r1;
4007	}
4008
4009	void helper_bswapq_T0(void)
4010	{
4011	T0 = bswap64(T0);
4012	}
4013	#endif
4014
4015	void helper_hlt(void)
4016	{
4017	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
4018	env->hflags \|= HF_HALTED_MASK;
4019	env->exception_index = EXCP_HLT;
4020	cpu_loop_exit();
4021	}
4022
4023	void helper_monitor(void)
4024	{
4025	if ((uint32_t)ECX != 0)
4026	raise_exception(EXCP0D_GPF);
4027	/* XXX: store address ? */
4028	}
4029
4030	void helper_mwait(void)
4031	{
4032	if ((uint32_t)ECX != 0)
4033	raise_exception(EXCP0D_GPF);
4034	#ifdef VBOX
4035	helper_hlt();
4036	#else
4037	/* XXX: not complete but not completely erroneous */
4038	if (env->cpu_index != 0 \|\| env->next_cpu != NULL) {
4039	/* more than one CPU: do not sleep because another CPU may
4040	wake this one */
4041	} else {
4042	helper_hlt();
4043	}
4044	#endif
4045	}
4046
4047	float approx_rsqrt(float a)
4048	{
4049	return 1.0 / sqrt(a);
4050	}
4051
4052	float approx_rcp(float a)
4053	{
4054	return 1.0 / a;
4055	}
4056
4057	void update_fp_status(void)
4058	{
4059	int rnd_type;
4060
4061	/* set rounding mode */
4062	switch(env->fpuc & RC_MASK) {
4063	default:
4064	case RC_NEAR:
4065	rnd_type = float_round_nearest_even;
4066	break;
4067	case RC_DOWN:
4068	rnd_type = float_round_down;
4069	break;
4070	case RC_UP:
4071	rnd_type = float_round_up;
4072	break;
4073	case RC_CHOP:
4074	rnd_type = float_round_to_zero;
4075	break;
4076	}
4077	set_float_rounding_mode(rnd_type, &env->fp_status);
4078	#ifdef FLOATX80
4079	switch((env->fpuc >> 8) & 3) {
4080	case 0:
4081	rnd_type = 32;
4082	break;
4083	case 2:
4084	rnd_type = 64;
4085	break;
4086	case 3:
4087	default:
4088	rnd_type = 80;
4089	break;
4090	}
4091	set_floatx80_rounding_precision(rnd_type, &env->fp_status);
4092	#endif
4093	}
4094
4095	#if !defined(CONFIG_USER_ONLY)
4096
4097	#define MMUSUFFIX _mmu
4098	#define GETPC() (__builtin_return_address(0))
4099
4100	#define SHIFT 0
4101	#include "softmmu_template.h"
4102
4103	#define SHIFT 1
4104	#include "softmmu_template.h"
4105
4106	#define SHIFT 2
4107	#include "softmmu_template.h"
4108
4109	#define SHIFT 3
4110	#include "softmmu_template.h"
4111
4112	#endif
4113
4114	/* try to fill the TLB and return an exception if error. If retaddr is
4115	NULL, it means that the function was called in C code (i.e. not
4116	from generated code or from helper.c) */
4117	/* XXX: fix it to restore all registers */
4118	void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
4119	{
4120	TranslationBlock *tb;
4121	int ret;
4122	unsigned long pc;
4123	CPUX86State *saved_env;
4124
4125	/* XXX: hack to restore env in all cases, even if not called from
4126	generated code */
4127	saved_env = env;
4128	env = cpu_single_env;
4129
4130	ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
4131	if (ret) {
4132	if (retaddr) {
4133	/* now we have a real cpu fault */
4134	pc = (unsigned long)retaddr;
4135	tb = tb_find_pc(pc);
4136	if (tb) {
4137	/* the PC is inside the translated code. It means that we have
4138	a virtual CPU fault */
4139	cpu_restore_state(tb, env, pc, NULL);
4140	}
4141	}
4142	if (retaddr)
4143	raise_exception_err(env->exception_index, env->error_code);
4144	else
4145	raise_exception_err_norestore(env->exception_index, env->error_code);
4146	}
4147	env = saved_env;
4148	}
4149
4150	#ifdef VBOX
4151
4152	/**
4153	* Correctly computes the eflags.
4154	* @returns eflags.
4155	* @param env1 CPU environment.
4156	*/
4157	uint32_t raw_compute_eflags(CPUX86State *env1)
4158	{
4159	CPUX86State *savedenv = env;
4160	env = env1;
4161	uint32_t efl = compute_eflags();
4162	env = savedenv;
4163	return efl;
4164	}
4165
4166	/**
4167	* Reads byte from virtual address in guest memory area.
4168	* XXX: is it working for any addresses? swapped out pages?
4169	* @returns readed data byte.
4170	* @param env1 CPU environment.
4171	* @param pvAddr GC Virtual address.
4172	*/
4173	uint8_t read_byte(CPUX86State *env1, target_ulong addr)
4174	{
4175	CPUX86State *savedenv = env;
4176	env = env1;
4177	uint8_t u8 = ldub_kernel(addr);
4178	env = savedenv;
4179	return u8;
4180	}
4181
4182	/**
4183	* Reads byte from virtual address in guest memory area.
4184	* XXX: is it working for any addresses? swapped out pages?
4185	* @returns readed data byte.
4186	* @param env1 CPU environment.
4187	* @param pvAddr GC Virtual address.
4188	*/
4189	uint16_t read_word(CPUX86State *env1, target_ulong addr)
4190	{
4191	CPUX86State *savedenv = env;
4192	env = env1;
4193	uint16_t u16 = lduw_kernel(addr);
4194	env = savedenv;
4195	return u16;
4196	}
4197
4198	/**
4199	* Reads byte from virtual address in guest memory area.
4200	* XXX: is it working for any addresses? swapped out pages?
4201	* @returns readed data byte.
4202	* @param env1 CPU environment.
4203	* @param pvAddr GC Virtual address.
4204	*/
4205	uint32_t read_dword(CPUX86State *env1, target_ulong addr)
4206	{
4207	CPUX86State *savedenv = env;
4208	env = env1;
4209	uint32_t u32 = ldl_kernel(addr);
4210	env = savedenv;
4211	return u32;
4212	}
4213
4214	/**
4215	* Writes byte to virtual address in guest memory area.
4216	* XXX: is it working for any addresses? swapped out pages?
4217	* @returns readed data byte.
4218	* @param env1 CPU environment.
4219	* @param pvAddr GC Virtual address.
4220	* @param val byte value
4221	*/
4222	void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
4223	{
4224	CPUX86State *savedenv = env;
4225	env = env1;
4226	stb(addr, val);
4227	env = savedenv;
4228	}
4229
4230	void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
4231	{
4232	CPUX86State *savedenv = env;
4233	env = env1;
4234	stw(addr, val);
4235	env = savedenv;
4236	}
4237
4238	void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
4239	{
4240	CPUX86State *savedenv = env;
4241	env = env1;
4242	stl(addr, val);
4243	env = savedenv;
4244	}
4245
4246	/**
4247	* Correctly loads selector into segment register with updating internal
4248	* qemu data/caches.
4249	* @param env1 CPU environment.
4250	* @param seg_reg Segment register.
4251	* @param selector Selector to load.
4252	*/
4253	void sync_seg(CPUX86State *env1, int seg_reg, int selector)
4254	{
4255	CPUX86State *savedenv = env;
4256	env = env1;
4257
4258	if (env->eflags & X86_EFL_VM)
4259	{
4260	load_seg_vm(seg_reg, selector);
4261
4262	env = savedenv;
4263
4264	/* Successful sync. */
4265	env1->segs[seg_reg].newselector = 0;
4266	}
4267	else
4268	{
4269	if (setjmp(env1->jmp_env) == 0)
4270	{
4271	if (seg_reg == R_CS)
4272	{
4273	uint32_t e1, e2;
4274	load_segment(&e1, &e2, selector);
4275	cpu_x86_load_seg_cache(env, R_CS, selector,
4276	get_seg_base(e1, e2),
4277	get_seg_limit(e1, e2),
4278	e2);
4279	}
4280	else
4281	load_seg(seg_reg, selector);
4282	env = savedenv;
4283
4284	/* Successful sync. */
4285	env1->segs[seg_reg].newselector = 0;
4286	}
4287	else
4288	{
4289	env = savedenv;
4290
4291	/* Postpone sync until the guest uses the selector. */
4292	env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
4293	env1->segs[seg_reg].newselector = selector;
4294	Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
4295	}
4296	}
4297
4298	}
4299
4300
4301	/**
4302	* Correctly loads a new ldtr selector.
4303	*
4304	* @param env1 CPU environment.
4305	* @param selector Selector to load.
4306	*/
4307	void sync_ldtr(CPUX86State *env1, int selector)
4308	{
4309	CPUX86State *saved_env = env;
4310	target_ulong saved_T0 = T0;
4311	if (setjmp(env1->jmp_env) == 0)
4312	{
4313	env = env1;
4314	T0 = selector;
4315	helper_lldt_T0();
4316	T0 = saved_T0;
4317	env = saved_env;
4318	}
4319	else
4320	{
4321	T0 = saved_T0;
4322	env = saved_env;
4323	#ifdef VBOX_STRICT
4324	cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
4325	#endif
4326	}
4327	}
4328
4329	/**
4330	* Correctly loads a new tr selector.
4331	*
4332	* @param env1 CPU environment.
4333	* @param selector Selector to load.
4334	*/
4335	int sync_tr(CPUX86State *env1, int selector)
4336	{
4337	/* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
4338	SegmentCache *dt;
4339	uint32_t e1, e2;
4340	int index, type, entry_limit;
4341	target_ulong ptr;
4342	CPUX86State *saved_env = env;
4343	env = env1;
4344
4345	selector &= 0xffff;
4346	if ((selector & 0xfffc) == 0) {
4347	/* NULL selector case: invalid TR */
4348	env->tr.base = 0;
4349	env->tr.limit = 0;
4350	env->tr.flags = 0;
4351	} else {
4352	if (selector & 0x4)
4353	goto l_failure;
4354	dt = &env->gdt;
4355	index = selector & ~7;
4356	#ifdef TARGET_X86_64
4357	if (env->hflags & HF_LMA_MASK)
4358	entry_limit = 15;
4359	else
4360	#endif
4361	entry_limit = 7;
4362	if ((index + entry_limit) > dt->limit)
4363	goto l_failure;
4364	ptr = dt->base + index;
4365	e1 = ldl_kernel(ptr);
4366	e2 = ldl_kernel(ptr + 4);
4367	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
4368	if ((e2 & DESC_S_MASK) /*\|\|
4369	(type != 1 && type != 9)*/)
4370	goto l_failure;
4371	if (!(e2 & DESC_P_MASK))
4372	goto l_failure;
4373	#ifdef TARGET_X86_64
4374	if (env->hflags & HF_LMA_MASK) {
4375	uint32_t e3;
4376	e3 = ldl_kernel(ptr + 8);
4377	load_seg_cache_raw_dt(&env->tr, e1, e2);
4378	env->tr.base \|= (target_ulong)e3 << 32;
4379	} else
4380	#endif
4381	{
4382	load_seg_cache_raw_dt(&env->tr, e1, e2);
4383	}
4384	e2 \|= DESC_TSS_BUSY_MASK;
4385	stl_kernel(ptr + 4, e2);
4386	}
4387	env->tr.selector = selector;
4388
4389	env = saved_env;
4390	return 0;
4391	l_failure:
4392	AssertMsgFailed(("selector=%d\n", selector));
4393	return -1;
4394	}
4395
4396	int emulate_single_instr(CPUX86State *env1)
4397	{
4398	TranslationBlock *current;
4399	TranslationBlock tb_temp;
4400	int csize;
4401	void (*gen_func)(void);
4402	uint8_t *tc_ptr;
4403	uint32_t old_eip;
4404
4405	/* ensures env is loaded in ebp! */
4406	CPUX86State *savedenv = env;
4407	env = env1;
4408
4409	RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
4410
4411	tc_ptr = env->pvCodeBuffer;
4412
4413	/*
4414	* Setup temporary translation block.
4415	*/
4416	/* tb_alloc: */
4417	tb_temp.pc = env->segs[R_CS].base + env->eip;
4418	tb_temp.cflags = 0;
4419
4420	/* tb_find_slow: */
4421	tb_temp.tc_ptr = tc_ptr;
4422	tb_temp.cs_base = env->segs[R_CS].base;
4423	tb_temp.flags = env->hflags \| (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
4424
4425	/* Initialize the rest with sensible values. */
4426	tb_temp.size = 0;
4427	tb_temp.phys_hash_next = NULL;
4428	tb_temp.page_next[0] = NULL;
4429	tb_temp.page_next[1] = NULL;
4430	tb_temp.page_addr[0] = 0;
4431	tb_temp.page_addr[1] = 0;
4432	tb_temp.tb_next_offset[0] = 0xffff;
4433	tb_temp.tb_next_offset[1] = 0xffff;
4434	tb_temp.tb_next[0] = 0xffff;
4435	tb_temp.tb_next[1] = 0xffff;
4436	tb_temp.jmp_next[0] = NULL;
4437	tb_temp.jmp_next[1] = NULL;
4438	tb_temp.jmp_first = NULL;
4439
4440	current = env->current_tb;
4441	env->current_tb = NULL;
4442
4443	/*
4444	* Translate only one instruction.
4445	*/
4446	ASMAtomicOrU32(&env->state, CPU_EMULATE_SINGLE_INSTR);
4447	if (cpu_gen_code(env, &tb_temp, env->cbCodeBuffer, &csize) < 0)
4448	{
4449	AssertFailed();
4450	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4451	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4452	env = savedenv;
4453	return -1;
4454	}
4455	#ifdef DEBUG
4456	if(csize > env->cbCodeBuffer)
4457	{
4458	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4459	AssertFailed();
4460	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4461	env = savedenv;
4462	return -1;
4463	}
4464	if (tb_temp.tc_ptr != tc_ptr)
4465	{
4466	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4467	AssertFailed();
4468	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4469	env = savedenv;
4470	return -1;
4471	}
4472	#endif
4473	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4474
4475	/* tb_link_phys: */
4476	tb_temp.jmp_first = (TranslationBlock *)((intptr_t)&tb_temp \| 2);
4477	Assert(tb_temp.jmp_next[0] == NULL); Assert(tb_temp.jmp_next[1] == NULL);
4478	if (tb_temp.tb_next_offset[0] != 0xffff)
4479	tb_set_jmp_target(&tb_temp, 0, (uintptr_t)(tb_temp.tc_ptr + tb_temp.tb_next_offset[0]));
4480	if (tb_temp.tb_next_offset[1] != 0xffff)
4481	tb_set_jmp_target(&tb_temp, 1, (uintptr_t)(tb_temp.tc_ptr + tb_temp.tb_next_offset[1]));
4482
4483	/*
4484	* Execute it using emulation
4485	*/
4486	old_eip = env->eip;
4487	gen_func = (void *)tb_temp.tc_ptr;
4488	env->current_tb = &tb_temp;
4489
4490	// eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
4491	// perhaps not a very safe hack
4492	while(old_eip == env->eip)
4493	{
4494	gen_func();
4495	/*
4496	* Exit once we detect an external interrupt and interrupts are enabled
4497	*/
4498	if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT\|CPU_INTERRUPT_EXTERNAL_TIMER)) \|\|
4499	( (env->eflags & IF_MASK) &&
4500	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
4501	(env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
4502	{
4503	break;
4504	}
4505	}
4506	env->current_tb = current;
4507
4508	Assert(tb_temp.phys_hash_next == NULL);
4509	Assert(tb_temp.page_next[0] == NULL);
4510	Assert(tb_temp.page_next[1] == NULL);
4511	Assert(tb_temp.page_addr[0] == 0);
4512	Assert(tb_temp.page_addr[1] == 0);
4513	/*
4514	Assert(tb_temp.tb_next_offset[0] == 0xffff);
4515	Assert(tb_temp.tb_next_offset[1] == 0xffff);
4516	Assert(tb_temp.tb_next[0] == 0xffff);
4517	Assert(tb_temp.tb_next[1] == 0xffff);
4518	Assert(tb_temp.jmp_next[0] == NULL);
4519	Assert(tb_temp.jmp_next[1] == NULL);
4520	Assert(tb_temp.jmp_first == NULL); */
4521
4522	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4523
4524	/*
4525	* Execute the next instruction when we encounter instruction fusing.
4526	*/
4527	if (env->hflags & HF_INHIBIT_IRQ_MASK)
4528	{
4529	Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK)\n"));
4530	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
4531	emulate_single_instr(env);
4532	}
4533
4534	env = savedenv;
4535	return 0;
4536	}
4537
4538	int get_ss_esp_from_tss_raw(CPUX86State env1, uint32_t ss_ptr,
4539	uint32_t *esp_ptr, int dpl)
4540	{
4541	int type, index, shift;
4542
4543	CPUX86State *savedenv = env;
4544	env = env1;
4545
4546	if (!(env->tr.flags & DESC_P_MASK))
4547	cpu_abort(env, "invalid tss");
4548	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
4549	if ((type & 7) != 1)
4550	cpu_abort(env, "invalid tss type %d", type);
4551	shift = type >> 3;
4552	index = (dpl * 4 + 2) << shift;
4553	if (index + (4 << shift) - 1 > env->tr.limit)
4554	{
4555	env = savedenv;
4556	return 0;
4557	}
4558	//raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
4559
4560	if (shift == 0) {
4561	*esp_ptr = lduw_kernel(env->tr.base + index);
4562	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
4563	} else {
4564	*esp_ptr = ldl_kernel(env->tr.base + index);
4565	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
4566	}
4567
4568	env = savedenv;
4569	return 1;
4570	}
4571
4572	//*****************************************************************************
4573	// Needs to be at the bottom of the file (overriding macros)
4574
4575	static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4576	{
4577	return (CPU86_LDouble )ptr;
4578	}
4579
4580	static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4581	{
4582	(CPU86_LDouble )ptr = f;
4583	}
4584
4585	#undef stw
4586	#undef stl
4587	#undef stq
4588	#define stw(a,b) (uint16_t )(a) = (uint16_t)(b)
4589	#define stl(a,b) (uint32_t )(a) = (uint32_t)(b)
4590	#define stq(a,b) (uint64_t )(a) = (uint64_t)(b)
4591	#define data64 0
4592
4593	//*****************************************************************************
4594	void restore_raw_fp_state(CPUX86State env, uint8_t ptr)
4595	{
4596	int fpus, fptag, i, nb_xmm_regs;
4597	CPU86_LDouble tmp;
4598	uint8_t *addr;
4599
4600	if (env->cpuid_features & CPUID_FXSR)
4601	{
4602	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4603	fptag = 0;
4604	for(i = 0; i < 8; i++) {
4605	fptag \|= (env->fptags[i] << i);
4606	}
4607	stw(ptr, env->fpuc);
4608	stw(ptr + 2, fpus);
4609	stw(ptr + 4, fptag ^ 0xff);
4610
4611	addr = ptr + 0x20;
4612	for(i = 0;i < 8; i++) {
4613	tmp = ST(i);
4614	helper_fstt_raw(tmp, addr);
4615	addr += 16;
4616	}
4617
4618	if (env->cr[4] & CR4_OSFXSR_MASK) {
4619	/* XXX: finish it */
4620	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4621	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4622	nb_xmm_regs = 8 << data64;
4623	addr = ptr + 0xa0;
4624	for(i = 0; i < nb_xmm_regs; i++) {
4625	#if __GNUC__ < 4
4626	stq(addr, env->xmm_regs[i].XMM_Q(0));
4627	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4628	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4629	stl(addr, env->xmm_regs[i].XMM_L(0));
4630	stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4631	stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4632	stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4633	#endif
4634	addr += 16;
4635	}
4636	}
4637	}
4638	else
4639	{
4640	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4641	int fptag;
4642
4643	fp->FCW = env->fpuc;
4644	fp->FSW = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4645	fptag = 0;
4646	for (i=7; i>=0; i--) {
4647	fptag <<= 2;
4648	if (env->fptags[i]) {
4649	fptag \|= 3;
4650	} else {
4651	/* the FPU automatically computes it */
4652	}
4653	}
4654	fp->FTW = fptag;
4655
4656	for(i = 0;i < 8; i++) {
4657	tmp = ST(i);
4658	helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4659	}
4660	}
4661	}
4662
4663	//*****************************************************************************
4664	#undef lduw
4665	#undef ldl
4666	#undef ldq
4667	#define lduw(a) (uint16_t )(a)
4668	#define ldl(a) (uint32_t )(a)
4669	#define ldq(a) (uint64_t )(a)
4670	//*****************************************************************************
4671	void save_raw_fp_state(CPUX86State env, uint8_t ptr)
4672	{
4673	int i, fpus, fptag, nb_xmm_regs;
4674	CPU86_LDouble tmp;
4675	uint8_t *addr;
4676
4677	if (env->cpuid_features & CPUID_FXSR)
4678	{
4679	env->fpuc = lduw(ptr);
4680	fpus = lduw(ptr + 2);
4681	fptag = lduw(ptr + 4);
4682	env->fpstt = (fpus >> 11) & 7;
4683	env->fpus = fpus & ~0x3800;
4684	fptag ^= 0xff;
4685	for(i = 0;i < 8; i++) {
4686	env->fptags[i] = ((fptag >> i) & 1);
4687	}
4688
4689	addr = ptr + 0x20;
4690	for(i = 0;i < 8; i++) {
4691	tmp = helper_fldt_raw(addr);
4692	ST(i) = tmp;
4693	addr += 16;
4694	}
4695
4696	if (env->cr[4] & CR4_OSFXSR_MASK) {
4697	/* XXX: finish it, endianness */
4698	env->mxcsr = ldl(ptr + 0x18);
4699	//ldl(ptr + 0x1c);
4700	nb_xmm_regs = 8 << data64;
4701	addr = ptr + 0xa0;
4702	for(i = 0; i < nb_xmm_regs; i++) {
4703	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4704	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4705	addr += 16;
4706	}
4707	}
4708	}
4709	else
4710	{
4711	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4712	int fptag, j;
4713
4714	env->fpuc = fp->FCW;
4715	env->fpstt = (fp->FSW >> 11) & 7;
4716	env->fpus = fp->FSW & ~0x3800;
4717	fptag = fp->FTW;
4718	for(i = 0;i < 8; i++) {
4719	env->fptags[i] = ((fptag & 3) == 3);
4720	fptag >>= 2;
4721	}
4722	j = env->fpstt;
4723	for(i = 0;i < 8; i++) {
4724	tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4725	ST(i) = tmp;
4726	}
4727	}
4728	}
4729	//*****************************************************************************
4730	//*****************************************************************************
4731
4732	#endif /* VBOX */
4733

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source: vbox/trunk/src/recompiler/new/target-i386/helper.c@ 1591

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