VirtualBox

source: vbox/trunk/src/recompiler/target-i386/cpu.h@ 12519

Last change on this file since 12519 was 11982, checked in by vboxsync, 16 years ago

All: license header changes for 2.0 (OSE headers, add Sun GPL/LGPL disclaimer)
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1/*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#ifndef CPU_I386_H
30#define CPU_I386_H
31
32#include "config.h"
33
34#ifdef TARGET_X86_64
35#define TARGET_LONG_BITS 64
36#else
37#define TARGET_LONG_BITS 32
38#endif
39
40/* target supports implicit self modifying code */
41#define TARGET_HAS_SMC
42/* support for self modifying code even if the modified instruction is
43 close to the modifying instruction */
44#define TARGET_HAS_PRECISE_SMC
45
46#define TARGET_HAS_ICE 1
47
48#ifdef TARGET_X86_64
49#define ELF_MACHINE EM_X86_64
50#else
51#define ELF_MACHINE EM_386
52#endif
53
54#include "cpu-defs.h"
55
56#include "softfloat.h"
57
58#if defined(VBOX)
59# include <iprt/critsect.h>
60# include <iprt/thread.h>
61# include <iprt/assert.h>
62# include <iprt/asm.h>
63# include <VBox/vmm.h>
64#endif /* VBOX */
65
66#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
67#define USE_CODE_COPY
68#endif
69
70#define R_EAX 0
71#define R_ECX 1
72#define R_EDX 2
73#define R_EBX 3
74#define R_ESP 4
75#define R_EBP 5
76#define R_ESI 6
77#define R_EDI 7
78
79#define R_AL 0
80#define R_CL 1
81#define R_DL 2
82#define R_BL 3
83#define R_AH 4
84#define R_CH 5
85#define R_DH 6
86#define R_BH 7
87
88#define R_ES 0
89#define R_CS 1
90#define R_SS 2
91#define R_DS 3
92#define R_FS 4
93#define R_GS 5
94
95/* segment descriptor fields */
96#define DESC_G_MASK (1 << 23)
97#define DESC_B_SHIFT 22
98#define DESC_B_MASK (1 << DESC_B_SHIFT)
99#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
100#define DESC_L_MASK (1 << DESC_L_SHIFT)
101#define DESC_AVL_MASK (1 << 20)
102#define DESC_P_MASK (1 << 15)
103#define DESC_DPL_SHIFT 13
104#define DESC_S_MASK (1 << 12)
105#define DESC_TYPE_SHIFT 8
106#define DESC_A_MASK (1 << 8)
107
108#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
109#define DESC_C_MASK (1 << 10) /* code: conforming */
110#define DESC_R_MASK (1 << 9) /* code: readable */
111
112#define DESC_E_MASK (1 << 10) /* data: expansion direction */
113#define DESC_W_MASK (1 << 9) /* data: writable */
114
115#define DESC_TSS_BUSY_MASK (1 << 9)
116
117/* eflags masks */
118#define CC_C 0x0001
119#define CC_P 0x0004
120#define CC_A 0x0010
121#define CC_Z 0x0040
122#define CC_S 0x0080
123#define CC_O 0x0800
124
125#define TF_SHIFT 8
126#define IOPL_SHIFT 12
127#define VM_SHIFT 17
128
129#define TF_MASK 0x00000100
130#define IF_MASK 0x00000200
131#define DF_MASK 0x00000400
132#define IOPL_MASK 0x00003000
133#define NT_MASK 0x00004000
134#define RF_MASK 0x00010000
135#define VM_MASK 0x00020000
136#define AC_MASK 0x00040000
137#define VIF_MASK 0x00080000
138#define VIP_MASK 0x00100000
139#define ID_MASK 0x00200000
140
141/* hidden flags - used internally by qemu to represent additionnal cpu
142 states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
143 using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
144 with eflags. */
145/* current cpl */
146#define HF_CPL_SHIFT 0
147/* true if soft mmu is being used */
148#define HF_SOFTMMU_SHIFT 2
149/* true if hardware interrupts must be disabled for next instruction */
150#define HF_INHIBIT_IRQ_SHIFT 3
151/* 16 or 32 segments */
152#define HF_CS32_SHIFT 4
153#define HF_SS32_SHIFT 5
154/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
155#define HF_ADDSEG_SHIFT 6
156/* copy of CR0.PE (protected mode) */
157#define HF_PE_SHIFT 7
158#define HF_TF_SHIFT 8 /* must be same as eflags */
159#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
160#define HF_EM_SHIFT 10
161#define HF_TS_SHIFT 11
162#define HF_IOPL_SHIFT 12 /* must be same as eflags */
163#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
164#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
165#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
166#define HF_VM_SHIFT 17 /* must be same as eflags */
167#define HF_HALTED_SHIFT 18 /* CPU halted */
168#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
169
170#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
171#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
172#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
173#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
174#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
175#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
176#define HF_PE_MASK (1 << HF_PE_SHIFT)
177#define HF_TF_MASK (1 << HF_TF_SHIFT)
178#define HF_MP_MASK (1 << HF_MP_SHIFT)
179#define HF_EM_MASK (1 << HF_EM_SHIFT)
180#define HF_TS_MASK (1 << HF_TS_SHIFT)
181#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
182#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
183#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
184#define HF_HALTED_MASK (1 << HF_HALTED_SHIFT)
185#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
186
187#define CR0_PE_MASK (1 << 0)
188#define CR0_MP_MASK (1 << 1)
189#define CR0_EM_MASK (1 << 2)
190#define CR0_TS_MASK (1 << 3)
191#define CR0_ET_MASK (1 << 4)
192#define CR0_NE_MASK (1 << 5)
193#define CR0_WP_MASK (1 << 16)
194#define CR0_AM_MASK (1 << 18)
195#define CR0_PG_MASK (1 << 31)
196
197#define CR4_VME_MASK (1 << 0)
198#define CR4_PVI_MASK (1 << 1)
199#define CR4_TSD_MASK (1 << 2)
200#define CR4_DE_MASK (1 << 3)
201#define CR4_PSE_MASK (1 << 4)
202#define CR4_PAE_MASK (1 << 5)
203#define CR4_PGE_MASK (1 << 7)
204#define CR4_PCE_MASK (1 << 8)
205#define CR4_OSFXSR_MASK (1 << 9)
206#define CR4_OSXMMEXCPT_MASK (1 << 10)
207
208#define PG_PRESENT_BIT 0
209#define PG_RW_BIT 1
210#define PG_USER_BIT 2
211#define PG_PWT_BIT 3
212#define PG_PCD_BIT 4
213#define PG_ACCESSED_BIT 5
214#define PG_DIRTY_BIT 6
215#define PG_PSE_BIT 7
216#define PG_GLOBAL_BIT 8
217#define PG_NX_BIT 63
218
219#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
220#define PG_RW_MASK (1 << PG_RW_BIT)
221#define PG_USER_MASK (1 << PG_USER_BIT)
222#define PG_PWT_MASK (1 << PG_PWT_BIT)
223#define PG_PCD_MASK (1 << PG_PCD_BIT)
224#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
225#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
226#define PG_PSE_MASK (1 << PG_PSE_BIT)
227#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
228#define PG_NX_MASK (1LL << PG_NX_BIT)
229
230#define PG_ERROR_W_BIT 1
231
232#define PG_ERROR_P_MASK 0x01
233#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
234#define PG_ERROR_U_MASK 0x04
235#define PG_ERROR_RSVD_MASK 0x08
236#define PG_ERROR_I_D_MASK 0x10
237
238#define MSR_IA32_APICBASE 0x1b
239#define MSR_IA32_APICBASE_BSP (1<<8)
240#define MSR_IA32_APICBASE_ENABLE (1<<11)
241#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
242
243#ifndef MSR_IA32_SYSENTER_CS /* VBox x86.h klugde */
244#define MSR_IA32_SYSENTER_CS 0x174
245#define MSR_IA32_SYSENTER_ESP 0x175
246#define MSR_IA32_SYSENTER_EIP 0x176
247#endif
248
249#define MSR_MCG_CAP 0x179
250#define MSR_MCG_STATUS 0x17a
251#define MSR_MCG_CTL 0x17b
252
253#define MSR_PAT 0x277
254
255#define MSR_EFER 0xc0000080
256
257#define MSR_EFER_SCE (1 << 0)
258#define MSR_EFER_LME (1 << 8)
259#define MSR_EFER_LMA (1 << 10)
260#define MSR_EFER_NXE (1 << 11)
261#define MSR_EFER_FFXSR (1 << 14)
262
263#define MSR_STAR 0xc0000081
264#define MSR_LSTAR 0xc0000082
265#define MSR_CSTAR 0xc0000083
266#define MSR_FMASK 0xc0000084
267#define MSR_FSBASE 0xc0000100
268#define MSR_GSBASE 0xc0000101
269#define MSR_KERNELGSBASE 0xc0000102
270
271/* cpuid_features bits */
272#define CPUID_FP87 (1 << 0)
273#define CPUID_VME (1 << 1)
274#define CPUID_DE (1 << 2)
275#define CPUID_PSE (1 << 3)
276#define CPUID_TSC (1 << 4)
277#define CPUID_MSR (1 << 5)
278#define CPUID_PAE (1 << 6)
279#define CPUID_MCE (1 << 7)
280#define CPUID_CX8 (1 << 8)
281#define CPUID_APIC (1 << 9)
282#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
283#define CPUID_MTRR (1 << 12)
284#define CPUID_PGE (1 << 13)
285#define CPUID_MCA (1 << 14)
286#define CPUID_CMOV (1 << 15)
287#define CPUID_PAT (1 << 16)
288#define CPUID_PSE36 (1 << 17)
289#define CPUID_CLFLUSH (1 << 19)
290/* ... */
291#define CPUID_MMX (1 << 23)
292#define CPUID_FXSR (1 << 24)
293#define CPUID_SSE (1 << 25)
294#define CPUID_SSE2 (1 << 26)
295
296#ifdef VBOX
297#define CPUID_HTT (1 << 28)
298#endif
299
300#define CPUID_EXT_SSE3 (1 << 0)
301#define CPUID_EXT_MONITOR (1 << 3)
302#define CPUID_EXT_DSCPL (1 << 4)
303#define CPUID_EXT_VMX (1 << 5)
304#define CPUID_EXT_SMX (1 << 6)
305#define CPUID_EXT_EST (1 << 7)
306#define CPUID_EXT_TM2 (1 << 8)
307#define CPUID_EXT_SSSE3 (1 << 9)
308#define CPUID_EXT_CID (1 << 10)
309#define CPUID_EXT_CX16 (1 << 13)
310#define CPUID_EXT_XTPR (1 << 14)
311#define CPUID_EXT_DCA (1 << 17)
312#define CPUID_EXT_POPCNT (1 << 22)
313
314#define CPUID_EXT2_SYSCALL (1 << 11)
315#define CPUID_EXT2_MP (1 << 19)
316#define CPUID_EXT2_NX (1 << 20)
317#define CPUID_EXT2_MMXEXT (1 << 22)
318#define CPUID_EXT2_FFXSR (1 << 25)
319#define CPUID_EXT2_PDPE1GB (1 << 26)
320#define CPUID_EXT2_RDTSCP (1 << 27)
321#define CPUID_EXT2_LM (1 << 29)
322#define CPUID_EXT2_3DNOWEXT (1 << 30)
323#define CPUID_EXT2_3DNOW (1 << 31)
324
325#define CPUID_EXT3_LAHF_LM (1 << 0)
326#define CPUID_EXT3_CMP_LEG (1 << 1)
327#define CPUID_EXT3_SVM (1 << 2)
328#define CPUID_EXT3_EXTAPIC (1 << 3)
329#define CPUID_EXT3_CR8LEG (1 << 4)
330#define CPUID_EXT3_ABM (1 << 5)
331#define CPUID_EXT3_SSE4A (1 << 6)
332#define CPUID_EXT3_MISALIGNSSE (1 << 7)
333#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
334#define CPUID_EXT3_OSVW (1 << 9)
335#define CPUID_EXT3_IBS (1 << 10)
336
337#define EXCP00_DIVZ 0
338#define EXCP01_SSTP 1
339#define EXCP02_NMI 2
340#define EXCP03_INT3 3
341#define EXCP04_INTO 4
342#define EXCP05_BOUND 5
343#define EXCP06_ILLOP 6
344#define EXCP07_PREX 7
345#define EXCP08_DBLE 8
346#define EXCP09_XERR 9
347#define EXCP0A_TSS 10
348#define EXCP0B_NOSEG 11
349#define EXCP0C_STACK 12
350#define EXCP0D_GPF 13
351#define EXCP0E_PAGE 14
352#define EXCP10_COPR 16
353#define EXCP11_ALGN 17
354#define EXCP12_MCHK 18
355
356enum {
357 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
358 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
359
360 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
361 CC_OP_MULW,
362 CC_OP_MULL,
363 CC_OP_MULQ,
364
365 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
366 CC_OP_ADDW,
367 CC_OP_ADDL,
368 CC_OP_ADDQ,
369
370 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
371 CC_OP_ADCW,
372 CC_OP_ADCL,
373 CC_OP_ADCQ,
374
375 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
376 CC_OP_SUBW,
377 CC_OP_SUBL,
378 CC_OP_SUBQ,
379
380 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
381 CC_OP_SBBW,
382 CC_OP_SBBL,
383 CC_OP_SBBQ,
384
385 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
386 CC_OP_LOGICW,
387 CC_OP_LOGICL,
388 CC_OP_LOGICQ,
389
390 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
391 CC_OP_INCW,
392 CC_OP_INCL,
393 CC_OP_INCQ,
394
395 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
396 CC_OP_DECW,
397 CC_OP_DECL,
398 CC_OP_DECQ,
399
400 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
401 CC_OP_SHLW,
402 CC_OP_SHLL,
403 CC_OP_SHLQ,
404
405 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
406 CC_OP_SARW,
407 CC_OP_SARL,
408 CC_OP_SARQ,
409
410 CC_OP_NB,
411};
412
413#ifdef FLOATX80
414#define USE_X86LDOUBLE
415#endif
416
417#ifdef USE_X86LDOUBLE
418typedef floatx80 CPU86_LDouble;
419#else
420typedef float64 CPU86_LDouble;
421#endif
422
423typedef struct SegmentCache {
424 uint32_t selector;
425 target_ulong base;
426 uint32_t limit;
427 uint32_t flags;
428#ifdef VBOX
429 /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
430 uint32_t newselector;
431#endif
432} SegmentCache;
433
434typedef union {
435 uint8_t _b[16];
436 uint16_t _w[8];
437 uint32_t _l[4];
438 uint64_t _q[2];
439 float32 _s[4];
440 float64 _d[2];
441} XMMReg;
442
443typedef union {
444 uint8_t _b[8];
445 uint16_t _w[2];
446 uint32_t _l[1];
447 uint64_t q;
448} MMXReg;
449
450#ifdef WORDS_BIGENDIAN
451#define XMM_B(n) _b[15 - (n)]
452#define XMM_W(n) _w[7 - (n)]
453#define XMM_L(n) _l[3 - (n)]
454#define XMM_S(n) _s[3 - (n)]
455#define XMM_Q(n) _q[1 - (n)]
456#define XMM_D(n) _d[1 - (n)]
457
458#define MMX_B(n) _b[7 - (n)]
459#define MMX_W(n) _w[3 - (n)]
460#define MMX_L(n) _l[1 - (n)]
461#else
462#define XMM_B(n) _b[n]
463#define XMM_W(n) _w[n]
464#define XMM_L(n) _l[n]
465#define XMM_S(n) _s[n]
466#define XMM_Q(n) _q[n]
467#define XMM_D(n) _d[n]
468
469#define MMX_B(n) _b[n]
470#define MMX_W(n) _w[n]
471#define MMX_L(n) _l[n]
472#endif
473#define MMX_Q(n) q
474
475#ifdef TARGET_X86_64
476#define CPU_NB_REGS 16
477#else
478#define CPU_NB_REGS 8
479#endif
480
481typedef struct CPUX86State {
482#if TARGET_LONG_BITS > HOST_LONG_BITS
483 /* temporaries if we cannot store them in host registers */
484 target_ulong t0, t1, t2;
485#endif
486
487 /* standard registers */
488 target_ulong regs[CPU_NB_REGS];
489 target_ulong eip;
490 target_ulong eflags; /* eflags register. During CPU emulation, CC
491 flags and DF are set to zero because they are
492 stored elsewhere */
493
494 /* emulator internal eflags handling */
495 target_ulong cc_src;
496 target_ulong cc_dst;
497 uint32_t cc_op;
498 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
499 uint32_t hflags; /* hidden flags, see HF_xxx constants */
500
501 /* segments */
502 SegmentCache segs[6]; /* selector values */
503 SegmentCache ldt;
504 SegmentCache tr;
505 SegmentCache gdt; /* only base and limit are used */
506 SegmentCache idt; /* only base and limit are used */
507
508 target_ulong cr[5]; /* NOTE: cr1 is unused */
509 uint32_t a20_mask;
510
511 /* FPU state */
512 unsigned int fpstt; /* top of stack index */
513 unsigned int fpus;
514 unsigned int fpuc;
515 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
516 union {
517#ifdef USE_X86LDOUBLE
518 CPU86_LDouble d __attribute__((aligned(16)));
519#else
520 CPU86_LDouble d;
521#endif
522 MMXReg mmx;
523 } fpregs[8];
524
525 /* emulator internal variables */
526 float_status fp_status;
527#ifdef VBOX
528 uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
529#endif
530 CPU86_LDouble ft0;
531#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
532 uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
533#endif
534 union {
535 float f;
536 double d;
537 int i32;
538 int64_t i64;
539 } fp_convert;
540
541 float_status sse_status;
542 uint32_t mxcsr;
543 XMMReg xmm_regs[CPU_NB_REGS];
544 XMMReg xmm_t0;
545 MMXReg mmx_t0;
546
547 /* sysenter registers */
548 uint32_t sysenter_cs;
549 uint64_t sysenter_esp;
550 uint64_t sysenter_eip;
551#ifdef VBOX
552 uint32_t alignment0;
553#endif
554 uint64_t efer;
555 uint64_t star;
556#ifdef TARGET_X86_64
557 target_ulong lstar;
558 target_ulong cstar;
559 target_ulong fmask;
560 target_ulong kernelgsbase;
561#endif
562
563 uint64_t pat;
564
565 /* temporary data for USE_CODE_COPY mode */
566#ifdef USE_CODE_COPY
567 uint32_t tmp0;
568 uint32_t saved_esp;
569 int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
570#endif
571
572 /* exception/interrupt handling */
573 jmp_buf jmp_env;
574#if defined(VBOX) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
575 /* This will be removed when switching to the no-crt code everywhere. */
576 uint32_t alignment1[23];
577#endif
578 int exception_index;
579 int error_code;
580 int exception_is_int;
581 target_ulong exception_next_eip;
582 target_ulong dr[8]; /* debug registers */
583 uint32_t smbase;
584 int interrupt_request;
585 int user_mode_only; /* user mode only simulation */
586
587 CPU_COMMON
588
589#ifdef VBOX
590 /** cpu state flags. (see defines below) */
591 uint32_t state;
592 /** The VM handle. */
593 PVM pVM;
594 /** code buffer for instruction emulation */
595 void *pvCodeBuffer;
596 /** code buffer size */
597 uint32_t cbCodeBuffer;
598#endif /* VBOX */
599
600 /* processor features (e.g. for CPUID insn) */
601#ifndef VBOX /* remR3CpuId deals with these */
602 uint32_t cpuid_level;
603 uint32_t cpuid_vendor1;
604 uint32_t cpuid_vendor2;
605 uint32_t cpuid_vendor3;
606 uint32_t cpuid_version;
607#endif /* !VBOX */
608 uint32_t cpuid_features;
609 uint32_t cpuid_ext_features;
610#ifndef VBOX
611 uint32_t cpuid_xlevel;
612 uint32_t cpuid_model[12];
613#endif /* !VBOX */
614 uint32_t cpuid_ext2_features;
615 uint32_t cpuid_ext3_features;
616
617#ifndef VBOX
618#ifdef USE_KQEMU
619 int kqemu_enabled;
620 int last_io_time;
621#endif
622 /* in order to simplify APIC support, we leave this pointer to the
623 user */
624 struct APICState *apic_state;
625#else
626 uint32_t alignment2[3];
627#endif
628} CPUX86State;
629
630#ifdef VBOX
631
632/* Version 1.6 structure; just for loading the old saved state */
633typedef struct SegmentCache_Ver16 {
634 uint32_t selector;
635 uint32_t base;
636 uint32_t limit;
637 uint32_t flags;
638#ifdef VBOX
639 /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
640 uint32_t newselector;
641#endif
642} SegmentCache_Ver16;
643
644#define CPU_NB_REGS_VER16 8
645
646/* Version 1.6 structure; just for loading the old saved state */
647typedef struct CPUX86State_Ver16 {
648#if TARGET_LONG_BITS > HOST_LONG_BITS
649 /* temporaries if we cannot store them in host registers */
650 uint32_t t0, t1, t2;
651#endif
652
653 /* standard registers */
654 uint32_t regs[CPU_NB_REGS_VER16];
655 uint32_t eip;
656 uint32_t eflags; /* eflags register. During CPU emulation, CC
657 flags and DF are set to zero because they are
658 stored elsewhere */
659
660 /* emulator internal eflags handling */
661 uint32_t cc_src;
662 uint32_t cc_dst;
663 uint32_t cc_op;
664 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
665 uint32_t hflags; /* hidden flags, see HF_xxx constants */
666
667 /* segments */
668 SegmentCache_Ver16 segs[6]; /* selector values */
669 SegmentCache_Ver16 ldt;
670 SegmentCache_Ver16 tr;
671 SegmentCache_Ver16 gdt; /* only base and limit are used */
672 SegmentCache_Ver16 idt; /* only base and limit are used */
673
674 uint32_t cr[5]; /* NOTE: cr1 is unused */
675 uint32_t a20_mask;
676
677 /* FPU state */
678 unsigned int fpstt; /* top of stack index */
679 unsigned int fpus;
680 unsigned int fpuc;
681 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
682 union {
683#ifdef USE_X86LDOUBLE
684 CPU86_LDouble d __attribute__((aligned(16)));
685#else
686 CPU86_LDouble d;
687#endif
688 MMXReg mmx;
689 } fpregs[8];
690
691 /* emulator internal variables */
692 float_status fp_status;
693#ifdef VBOX
694 uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
695#endif
696 CPU86_LDouble ft0;
697#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
698 uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
699#endif
700 union {
701 float f;
702 double d;
703 int i32;
704 int64_t i64;
705 } fp_convert;
706
707 float_status sse_status;
708 uint32_t mxcsr;
709 XMMReg xmm_regs[CPU_NB_REGS_VER16];
710 XMMReg xmm_t0;
711 MMXReg mmx_t0;
712
713 /* sysenter registers */
714 uint32_t sysenter_cs;
715 uint32_t sysenter_esp;
716 uint32_t sysenter_eip;
717#ifdef VBOX
718 uint32_t alignment0;
719#endif
720 uint64_t efer;
721 uint64_t star;
722
723 uint64_t pat;
724
725 /* temporary data for USE_CODE_COPY mode */
726#ifdef USE_CODE_COPY
727 uint32_t tmp0;
728 uint32_t saved_esp;
729 int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
730#endif
731
732 /* exception/interrupt handling */
733 jmp_buf jmp_env;
734} CPUX86State_Ver16;
735
736/** CPUX86State state flags
737 * @{ */
738#define CPU_RAW_RING0 0x0002 /* Set after first time RawR0 is executed, never cleared. */
739#define CPU_EMULATE_SINGLE_INSTR 0x0040 /* Execute a single instruction in emulation mode */
740#define CPU_EMULATE_SINGLE_STEP 0x0080 /* go into single step mode */
741#define CPU_RAW_HWACC 0x0100 /* Set after first time HWACC is executed, never cleared. */
742/** @} */
743#endif /* !VBOX */
744
745#ifdef VBOX
746CPUX86State *cpu_x86_init(CPUX86State *env);
747#else /* !VBOX */
748CPUX86State *cpu_x86_init(void);
749#endif /* !VBOX */
750int cpu_x86_exec(CPUX86State *s);
751void cpu_x86_close(CPUX86State *s);
752int cpu_get_pic_interrupt(CPUX86State *s);
753/* MSDOS compatibility mode FPU exception support */
754void cpu_set_ferr(CPUX86State *s);
755
756/* this function must always be used to load data in the segment
757 cache: it synchronizes the hflags with the segment cache values */
758static inline void cpu_x86_load_seg_cache(CPUX86State *env,
759 int seg_reg, unsigned int selector,
760 target_ulong base,
761 unsigned int limit,
762 unsigned int flags)
763{
764 SegmentCache *sc;
765 unsigned int new_hflags;
766
767 sc = &env->segs[seg_reg];
768 sc->selector = selector;
769 sc->base = base;
770 sc->limit = limit;
771 sc->flags = flags;
772#ifdef VBOX
773 sc->newselector = 0;
774#endif
775
776 /* update the hidden flags */
777 {
778 if (seg_reg == R_CS) {
779#ifdef TARGET_X86_64
780 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
781 /* long mode */
782 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
783 env->hflags &= ~(HF_ADDSEG_MASK);
784 } else
785#endif
786 {
787 /* legacy / compatibility case */
788 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
789 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
790 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
791 new_hflags;
792 }
793 }
794 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
795 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
796 if (env->hflags & HF_CS64_MASK) {
797 /* zero base assumed for DS, ES and SS in long mode */
798 } else if (!(env->cr[0] & CR0_PE_MASK) ||
799 (env->eflags & VM_MASK) ||
800 !(env->hflags & HF_CS32_MASK)) {
801 /* XXX: try to avoid this test. The problem comes from the
802 fact that is real mode or vm86 mode we only modify the
803 'base' and 'selector' fields of the segment cache to go
804 faster. A solution may be to force addseg to one in
805 translate-i386.c. */
806 new_hflags |= HF_ADDSEG_MASK;
807 } else {
808 new_hflags |= ((env->segs[R_DS].base |
809 env->segs[R_ES].base |
810 env->segs[R_SS].base) != 0) <<
811 HF_ADDSEG_SHIFT;
812 }
813 env->hflags = (env->hflags &
814 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
815 }
816}
817
818/* wrapper, just in case memory mappings must be changed */
819static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
820{
821#if HF_CPL_MASK == 3
822 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
823#else
824#error HF_CPL_MASK is hardcoded
825#endif
826}
827
828/* used for debug or cpu save/restore */
829void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
830CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
831
832/* the following helpers are only usable in user mode simulation as
833 they can trigger unexpected exceptions */
834void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
835void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
836void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
837
838/* you can call this signal handler from your SIGBUS and SIGSEGV
839 signal handlers to inform the virtual CPU of exceptions. non zero
840 is returned if the signal was handled by the virtual CPU. */
841int cpu_x86_signal_handler(int host_signum, void *pinfo,
842 void *puc);
843void cpu_x86_set_a20(CPUX86State *env, int a20_state);
844
845uint64_t cpu_get_tsc(CPUX86State *env);
846
847void cpu_set_apic_base(CPUX86State *env, uint64_t val);
848uint64_t cpu_get_apic_base(CPUX86State *env);
849void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
850#ifndef NO_CPU_IO_DEFS
851uint8_t cpu_get_apic_tpr(CPUX86State *env);
852#endif
853void cpu_smm_update(CPUX86State *env);
854
855/* will be suppressed */
856void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
857
858/* used to debug */
859#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
860#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
861
862#ifdef USE_KQEMU
863static inline int cpu_get_time_fast(void)
864{
865 int low, high;
866 asm volatile("rdtsc" : "=a" (low), "=d" (high));
867 return low;
868}
869#endif
870
871#ifdef VBOX
872void cpu_trap_raw(CPUX86State *env1);
873
874/* in helper.c */
875uint8_t read_byte(CPUX86State *env1, target_ulong addr);
876uint16_t read_word(CPUX86State *env1, target_ulong addr);
877void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val);
878uint32_t read_dword(CPUX86State *env1, target_ulong addr);
879void write_word(CPUX86State *env1, target_ulong addr, uint16_t val);
880void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val);
881/* in helper.c */
882int emulate_single_instr(CPUX86State *env1);
883int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl);
884
885void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr);
886void save_raw_fp_state(CPUX86State *env, uint8_t *ptr);
887
888#endif
889
890#define TARGET_PAGE_BITS 12
891#include "cpu-all.h"
892
893#endif /* CPU_I386_H */
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