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source: vbox/trunk/src/recompiler/target-i386/cpu.h@ 13321

Last change on this file since 13321 was 13034, checked in by vboxsync, 16 years ago

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1/*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#ifndef CPU_I386_H
30#define CPU_I386_H
31
32#include "config.h"
33
34#ifdef TARGET_X86_64
35#define TARGET_LONG_BITS 64
36#else
37#define TARGET_LONG_BITS 32
38#endif
39
40/* target supports implicit self modifying code */
41#define TARGET_HAS_SMC
42/* support for self modifying code even if the modified instruction is
43 close to the modifying instruction */
44#define TARGET_HAS_PRECISE_SMC
45
46#define TARGET_HAS_ICE 1
47
48#ifdef TARGET_X86_64
49#define ELF_MACHINE EM_X86_64
50#else
51#define ELF_MACHINE EM_386
52#endif
53
54#include "cpu-defs.h"
55
56#include "softfloat.h"
57
58#if defined(VBOX)
59# include <iprt/critsect.h>
60# include <iprt/thread.h>
61# include <iprt/assert.h>
62# include <iprt/asm.h>
63# include <VBox/vmm.h>
64#endif /* VBOX */
65
66#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
67#define USE_CODE_COPY
68#endif
69
70#define R_EAX 0
71#define R_ECX 1
72#define R_EDX 2
73#define R_EBX 3
74#define R_ESP 4
75#define R_EBP 5
76#define R_ESI 6
77#define R_EDI 7
78
79#define R_AL 0
80#define R_CL 1
81#define R_DL 2
82#define R_BL 3
83#define R_AH 4
84#define R_CH 5
85#define R_DH 6
86#define R_BH 7
87
88#define R_ES 0
89#define R_CS 1
90#define R_SS 2
91#define R_DS 3
92#define R_FS 4
93#define R_GS 5
94
95/* segment descriptor fields */
96#define DESC_G_MASK (1 << 23)
97#define DESC_B_SHIFT 22
98#define DESC_B_MASK (1 << DESC_B_SHIFT)
99#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
100#define DESC_L_MASK (1 << DESC_L_SHIFT)
101#define DESC_AVL_MASK (1 << 20)
102#define DESC_P_MASK (1 << 15)
103#define DESC_DPL_SHIFT 13
104#define DESC_S_MASK (1 << 12)
105#define DESC_TYPE_SHIFT 8
106#define DESC_A_MASK (1 << 8)
107
108#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
109#define DESC_C_MASK (1 << 10) /* code: conforming */
110#define DESC_R_MASK (1 << 9) /* code: readable */
111
112#define DESC_E_MASK (1 << 10) /* data: expansion direction */
113#define DESC_W_MASK (1 << 9) /* data: writable */
114
115#define DESC_TSS_BUSY_MASK (1 << 9)
116
117/* eflags masks */
118#define CC_C 0x0001
119#define CC_P 0x0004
120#define CC_A 0x0010
121#define CC_Z 0x0040
122#define CC_S 0x0080
123#define CC_O 0x0800
124
125#define TF_SHIFT 8
126#define IOPL_SHIFT 12
127#define VM_SHIFT 17
128
129#define TF_MASK 0x00000100
130#define IF_MASK 0x00000200
131#define DF_MASK 0x00000400
132#define IOPL_MASK 0x00003000
133#define NT_MASK 0x00004000
134#define RF_MASK 0x00010000
135#define VM_MASK 0x00020000
136#define AC_MASK 0x00040000
137#define VIF_MASK 0x00080000
138#define VIP_MASK 0x00100000
139#define ID_MASK 0x00200000
140
141/* hidden flags - used internally by qemu to represent additionnal cpu
142 states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
143 using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
144 with eflags. */
145/* current cpl */
146#define HF_CPL_SHIFT 0
147/* true if soft mmu is being used */
148#define HF_SOFTMMU_SHIFT 2
149/* true if hardware interrupts must be disabled for next instruction */
150#define HF_INHIBIT_IRQ_SHIFT 3
151/* 16 or 32 segments */
152#define HF_CS32_SHIFT 4
153#define HF_SS32_SHIFT 5
154/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
155#define HF_ADDSEG_SHIFT 6
156/* copy of CR0.PE (protected mode) */
157#define HF_PE_SHIFT 7
158#define HF_TF_SHIFT 8 /* must be same as eflags */
159#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
160#define HF_EM_SHIFT 10
161#define HF_TS_SHIFT 11
162#define HF_IOPL_SHIFT 12 /* must be same as eflags */
163#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
164#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
165#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
166#define HF_VM_SHIFT 17 /* must be same as eflags */
167#define HF_HALTED_SHIFT 18 /* CPU halted */
168#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
169
170#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
171#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
172#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
173#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
174#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
175#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
176#define HF_PE_MASK (1 << HF_PE_SHIFT)
177#define HF_TF_MASK (1 << HF_TF_SHIFT)
178#define HF_MP_MASK (1 << HF_MP_SHIFT)
179#define HF_EM_MASK (1 << HF_EM_SHIFT)
180#define HF_TS_MASK (1 << HF_TS_SHIFT)
181#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
182#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
183#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
184#define HF_HALTED_MASK (1 << HF_HALTED_SHIFT)
185#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
186
187#define CR0_PE_MASK (1 << 0)
188#define CR0_MP_MASK (1 << 1)
189#define CR0_EM_MASK (1 << 2)
190#define CR0_TS_MASK (1 << 3)
191#define CR0_ET_MASK (1 << 4)
192#define CR0_NE_MASK (1 << 5)
193#define CR0_WP_MASK (1 << 16)
194#define CR0_AM_MASK (1 << 18)
195#define CR0_PG_MASK (1 << 31)
196
197#define CR4_VME_MASK (1 << 0)
198#define CR4_PVI_MASK (1 << 1)
199#define CR4_TSD_MASK (1 << 2)
200#define CR4_DE_MASK (1 << 3)
201#define CR4_PSE_MASK (1 << 4)
202#define CR4_PAE_MASK (1 << 5)
203#define CR4_PGE_MASK (1 << 7)
204#define CR4_PCE_MASK (1 << 8)
205#define CR4_OSFXSR_MASK (1 << 9)
206#define CR4_OSXMMEXCPT_MASK (1 << 10)
207
208#define PG_PRESENT_BIT 0
209#define PG_RW_BIT 1
210#define PG_USER_BIT 2
211#define PG_PWT_BIT 3
212#define PG_PCD_BIT 4
213#define PG_ACCESSED_BIT 5
214#define PG_DIRTY_BIT 6
215#define PG_PSE_BIT 7
216#define PG_GLOBAL_BIT 8
217#define PG_NX_BIT 63
218
219#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
220#define PG_RW_MASK (1 << PG_RW_BIT)
221#define PG_USER_MASK (1 << PG_USER_BIT)
222#define PG_PWT_MASK (1 << PG_PWT_BIT)
223#define PG_PCD_MASK (1 << PG_PCD_BIT)
224#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
225#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
226#define PG_PSE_MASK (1 << PG_PSE_BIT)
227#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
228#define PG_NX_MASK (1LL << PG_NX_BIT)
229
230#define PG_ERROR_W_BIT 1
231
232#define PG_ERROR_P_MASK 0x01
233#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
234#define PG_ERROR_U_MASK 0x04
235#define PG_ERROR_RSVD_MASK 0x08
236#define PG_ERROR_I_D_MASK 0x10
237
238#define MSR_IA32_APICBASE 0x1b
239#define MSR_IA32_APICBASE_BSP (1<<8)
240#define MSR_IA32_APICBASE_ENABLE (1<<11)
241#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
242
243#ifndef MSR_IA32_SYSENTER_CS /* VBox x86.h klugde */
244#define MSR_IA32_SYSENTER_CS 0x174
245#define MSR_IA32_SYSENTER_ESP 0x175
246#define MSR_IA32_SYSENTER_EIP 0x176
247#endif
248
249#define MSR_MCG_CAP 0x179
250#define MSR_MCG_STATUS 0x17a
251#define MSR_MCG_CTL 0x17b
252
253#define MSR_PAT 0x277
254
255#define MSR_EFER 0xc0000080
256
257#define MSR_EFER_SCE (1 << 0)
258#define MSR_EFER_LME (1 << 8)
259#define MSR_EFER_LMA (1 << 10)
260#define MSR_EFER_NXE (1 << 11)
261#define MSR_EFER_FFXSR (1 << 14)
262#define MSR_APIC_RANGE_START 0x800
263#define MSR_APIC_RANGE_END 0x900
264
265#define MSR_STAR 0xc0000081
266#define MSR_LSTAR 0xc0000082
267#define MSR_CSTAR 0xc0000083
268#define MSR_FMASK 0xc0000084
269#define MSR_FSBASE 0xc0000100
270#define MSR_GSBASE 0xc0000101
271#define MSR_KERNELGSBASE 0xc0000102
272
273/* cpuid_features bits */
274#define CPUID_FP87 (1 << 0)
275#define CPUID_VME (1 << 1)
276#define CPUID_DE (1 << 2)
277#define CPUID_PSE (1 << 3)
278#define CPUID_TSC (1 << 4)
279#define CPUID_MSR (1 << 5)
280#define CPUID_PAE (1 << 6)
281#define CPUID_MCE (1 << 7)
282#define CPUID_CX8 (1 << 8)
283#define CPUID_APIC (1 << 9)
284#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
285#define CPUID_MTRR (1 << 12)
286#define CPUID_PGE (1 << 13)
287#define CPUID_MCA (1 << 14)
288#define CPUID_CMOV (1 << 15)
289#define CPUID_PAT (1 << 16)
290#define CPUID_PSE36 (1 << 17)
291#define CPUID_CLFLUSH (1 << 19)
292/* ... */
293#define CPUID_MMX (1 << 23)
294#define CPUID_FXSR (1 << 24)
295#define CPUID_SSE (1 << 25)
296#define CPUID_SSE2 (1 << 26)
297
298#ifdef VBOX
299#define CPUID_HTT (1 << 28)
300#endif
301
302#define CPUID_EXT_SSE3 (1 << 0)
303#define CPUID_EXT_MONITOR (1 << 3)
304#define CPUID_EXT_DSCPL (1 << 4)
305#define CPUID_EXT_VMX (1 << 5)
306#define CPUID_EXT_SMX (1 << 6)
307#define CPUID_EXT_EST (1 << 7)
308#define CPUID_EXT_TM2 (1 << 8)
309#define CPUID_EXT_SSSE3 (1 << 9)
310#define CPUID_EXT_CID (1 << 10)
311#define CPUID_EXT_CX16 (1 << 13)
312#define CPUID_EXT_XTPR (1 << 14)
313#define CPUID_EXT_DCA (1 << 17)
314#define CPUID_EXT_POPCNT (1 << 22)
315
316#define CPUID_EXT2_SYSCALL (1 << 11)
317#define CPUID_EXT2_MP (1 << 19)
318#define CPUID_EXT2_NX (1 << 20)
319#define CPUID_EXT2_MMXEXT (1 << 22)
320#define CPUID_EXT2_FFXSR (1 << 25)
321#define CPUID_EXT2_PDPE1GB (1 << 26)
322#define CPUID_EXT2_RDTSCP (1 << 27)
323#define CPUID_EXT2_LM (1 << 29)
324#define CPUID_EXT2_3DNOWEXT (1 << 30)
325#define CPUID_EXT2_3DNOW (1 << 31)
326
327#define CPUID_EXT3_LAHF_LM (1 << 0)
328#define CPUID_EXT3_CMP_LEG (1 << 1)
329#define CPUID_EXT3_SVM (1 << 2)
330#define CPUID_EXT3_EXTAPIC (1 << 3)
331#define CPUID_EXT3_CR8LEG (1 << 4)
332#define CPUID_EXT3_ABM (1 << 5)
333#define CPUID_EXT3_SSE4A (1 << 6)
334#define CPUID_EXT3_MISALIGNSSE (1 << 7)
335#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
336#define CPUID_EXT3_OSVW (1 << 9)
337#define CPUID_EXT3_IBS (1 << 10)
338
339#define EXCP00_DIVZ 0
340#define EXCP01_SSTP 1
341#define EXCP02_NMI 2
342#define EXCP03_INT3 3
343#define EXCP04_INTO 4
344#define EXCP05_BOUND 5
345#define EXCP06_ILLOP 6
346#define EXCP07_PREX 7
347#define EXCP08_DBLE 8
348#define EXCP09_XERR 9
349#define EXCP0A_TSS 10
350#define EXCP0B_NOSEG 11
351#define EXCP0C_STACK 12
352#define EXCP0D_GPF 13
353#define EXCP0E_PAGE 14
354#define EXCP10_COPR 16
355#define EXCP11_ALGN 17
356#define EXCP12_MCHK 18
357
358enum {
359 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
360 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
361
362 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
363 CC_OP_MULW,
364 CC_OP_MULL,
365 CC_OP_MULQ,
366
367 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
368 CC_OP_ADDW,
369 CC_OP_ADDL,
370 CC_OP_ADDQ,
371
372 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
373 CC_OP_ADCW,
374 CC_OP_ADCL,
375 CC_OP_ADCQ,
376
377 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
378 CC_OP_SUBW,
379 CC_OP_SUBL,
380 CC_OP_SUBQ,
381
382 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
383 CC_OP_SBBW,
384 CC_OP_SBBL,
385 CC_OP_SBBQ,
386
387 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
388 CC_OP_LOGICW,
389 CC_OP_LOGICL,
390 CC_OP_LOGICQ,
391
392 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
393 CC_OP_INCW,
394 CC_OP_INCL,
395 CC_OP_INCQ,
396
397 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
398 CC_OP_DECW,
399 CC_OP_DECL,
400 CC_OP_DECQ,
401
402 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
403 CC_OP_SHLW,
404 CC_OP_SHLL,
405 CC_OP_SHLQ,
406
407 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
408 CC_OP_SARW,
409 CC_OP_SARL,
410 CC_OP_SARQ,
411
412 CC_OP_NB
413};
414
415#ifdef FLOATX80
416#define USE_X86LDOUBLE
417#endif
418
419#ifdef USE_X86LDOUBLE
420typedef floatx80 CPU86_LDouble;
421#else
422typedef float64 CPU86_LDouble;
423#endif
424
425typedef struct SegmentCache {
426 uint32_t selector;
427 target_ulong base;
428 uint32_t limit;
429 uint32_t flags;
430#ifdef VBOX
431 /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
432 uint32_t newselector;
433#endif
434} SegmentCache;
435
436typedef union {
437 uint8_t _b[16];
438 uint16_t _w[8];
439 uint32_t _l[4];
440 uint64_t _q[2];
441 float32 _s[4];
442 float64 _d[2];
443} XMMReg;
444
445typedef union {
446 uint8_t _b[8];
447 uint16_t _w[2];
448 uint32_t _l[1];
449 uint64_t q;
450} MMXReg;
451
452#ifdef WORDS_BIGENDIAN
453#define XMM_B(n) _b[15 - (n)]
454#define XMM_W(n) _w[7 - (n)]
455#define XMM_L(n) _l[3 - (n)]
456#define XMM_S(n) _s[3 - (n)]
457#define XMM_Q(n) _q[1 - (n)]
458#define XMM_D(n) _d[1 - (n)]
459
460#define MMX_B(n) _b[7 - (n)]
461#define MMX_W(n) _w[3 - (n)]
462#define MMX_L(n) _l[1 - (n)]
463#else
464#define XMM_B(n) _b[n]
465#define XMM_W(n) _w[n]
466#define XMM_L(n) _l[n]
467#define XMM_S(n) _s[n]
468#define XMM_Q(n) _q[n]
469#define XMM_D(n) _d[n]
470
471#define MMX_B(n) _b[n]
472#define MMX_W(n) _w[n]
473#define MMX_L(n) _l[n]
474#endif
475#define MMX_Q(n) q
476
477#ifdef TARGET_X86_64
478#define CPU_NB_REGS 16
479#else
480#define CPU_NB_REGS 8
481#endif
482
483typedef struct CPUX86State {
484#if TARGET_LONG_BITS > HOST_LONG_BITS
485 /* temporaries if we cannot store them in host registers */
486 target_ulong t0, t1, t2;
487#endif
488
489 /* standard registers */
490 target_ulong regs[CPU_NB_REGS];
491 target_ulong eip;
492 target_ulong eflags; /* eflags register. During CPU emulation, CC
493 flags and DF are set to zero because they are
494 stored elsewhere */
495
496 /* emulator internal eflags handling */
497 target_ulong cc_src;
498 target_ulong cc_dst;
499 uint32_t cc_op;
500 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
501 uint32_t hflags; /* hidden flags, see HF_xxx constants */
502
503 /* segments */
504 SegmentCache segs[6]; /* selector values */
505 SegmentCache ldt;
506 SegmentCache tr;
507 SegmentCache gdt; /* only base and limit are used */
508 SegmentCache idt; /* only base and limit are used */
509
510 target_ulong cr[5]; /* NOTE: cr1 is unused */
511 uint32_t a20_mask;
512
513 /* FPU state */
514 unsigned int fpstt; /* top of stack index */
515 unsigned int fpus;
516 unsigned int fpuc;
517 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
518 union {
519#ifdef USE_X86LDOUBLE
520 CPU86_LDouble d __attribute__((aligned(16)));
521#else
522 CPU86_LDouble d;
523#endif
524 MMXReg mmx;
525 } fpregs[8];
526
527 /* emulator internal variables */
528 float_status fp_status;
529#ifdef VBOX
530 uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
531#endif
532 CPU86_LDouble ft0;
533#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
534 uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
535#endif
536 union {
537 float f;
538 double d;
539 int i32;
540 int64_t i64;
541 } fp_convert;
542
543 float_status sse_status;
544 uint32_t mxcsr;
545 XMMReg xmm_regs[CPU_NB_REGS];
546 XMMReg xmm_t0;
547 MMXReg mmx_t0;
548
549 /* sysenter registers */
550 uint32_t sysenter_cs;
551 uint64_t sysenter_esp;
552 uint64_t sysenter_eip;
553#ifdef VBOX
554 uint32_t alignment0;
555#endif
556 uint64_t efer;
557 uint64_t star;
558#ifdef TARGET_X86_64
559 target_ulong lstar;
560 target_ulong cstar;
561 target_ulong fmask;
562 target_ulong kernelgsbase;
563#endif
564
565 uint64_t pat;
566
567 /* temporary data for USE_CODE_COPY mode */
568#ifdef USE_CODE_COPY
569 uint32_t tmp0;
570 uint32_t saved_esp;
571 int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
572#endif
573
574 /* exception/interrupt handling */
575 jmp_buf jmp_env;
576#if defined(VBOX) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
577 /* This will be removed when switching to the no-crt code everywhere. */
578 uint32_t alignment1[23];
579#endif
580 int exception_index;
581 int error_code;
582 int exception_is_int;
583 target_ulong exception_next_eip;
584 target_ulong dr[8]; /* debug registers */
585 uint32_t smbase;
586 int interrupt_request;
587 int user_mode_only; /* user mode only simulation */
588
589 CPU_COMMON
590
591#ifdef VBOX
592 /** cpu state flags. (see defines below) */
593 uint32_t state;
594 /** The VM handle. */
595 PVM pVM;
596 /** code buffer for instruction emulation */
597 void *pvCodeBuffer;
598 /** code buffer size */
599 uint32_t cbCodeBuffer;
600#endif /* VBOX */
601
602 /* processor features (e.g. for CPUID insn) */
603#ifndef VBOX /* remR3CpuId deals with these */
604 uint32_t cpuid_level;
605 uint32_t cpuid_vendor1;
606 uint32_t cpuid_vendor2;
607 uint32_t cpuid_vendor3;
608 uint32_t cpuid_version;
609#endif /* !VBOX */
610 uint32_t cpuid_features;
611 uint32_t cpuid_ext_features;
612#ifndef VBOX
613 uint32_t cpuid_xlevel;
614 uint32_t cpuid_model[12];
615#endif /* !VBOX */
616 uint32_t cpuid_ext2_features;
617 uint32_t cpuid_ext3_features;
618
619#ifndef VBOX
620#ifdef USE_KQEMU
621 int kqemu_enabled;
622 int last_io_time;
623#endif
624 /* in order to simplify APIC support, we leave this pointer to the
625 user */
626 struct APICState *apic_state;
627#else
628 uint32_t alignment2[3];
629#endif
630} CPUX86State;
631
632#ifdef VBOX
633
634/* Version 1.6 structure; just for loading the old saved state */
635typedef struct SegmentCache_Ver16 {
636 uint32_t selector;
637 uint32_t base;
638 uint32_t limit;
639 uint32_t flags;
640#ifdef VBOX
641 /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
642 uint32_t newselector;
643#endif
644} SegmentCache_Ver16;
645
646#define CPU_NB_REGS_VER16 8
647
648/* Version 1.6 structure; just for loading the old saved state */
649typedef struct CPUX86State_Ver16 {
650#if TARGET_LONG_BITS > HOST_LONG_BITS
651 /* temporaries if we cannot store them in host registers */
652 uint32_t t0, t1, t2;
653#endif
654
655 /* standard registers */
656 uint32_t regs[CPU_NB_REGS_VER16];
657 uint32_t eip;
658 uint32_t eflags; /* eflags register. During CPU emulation, CC
659 flags and DF are set to zero because they are
660 stored elsewhere */
661
662 /* emulator internal eflags handling */
663 uint32_t cc_src;
664 uint32_t cc_dst;
665 uint32_t cc_op;
666 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
667 uint32_t hflags; /* hidden flags, see HF_xxx constants */
668
669 /* segments */
670 SegmentCache_Ver16 segs[6]; /* selector values */
671 SegmentCache_Ver16 ldt;
672 SegmentCache_Ver16 tr;
673 SegmentCache_Ver16 gdt; /* only base and limit are used */
674 SegmentCache_Ver16 idt; /* only base and limit are used */
675
676 uint32_t cr[5]; /* NOTE: cr1 is unused */
677 uint32_t a20_mask;
678
679 /* FPU state */
680 unsigned int fpstt; /* top of stack index */
681 unsigned int fpus;
682 unsigned int fpuc;
683 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
684 union {
685#ifdef USE_X86LDOUBLE
686 CPU86_LDouble d __attribute__((aligned(16)));
687#else
688 CPU86_LDouble d;
689#endif
690 MMXReg mmx;
691 } fpregs[8];
692
693 /* emulator internal variables */
694 float_status fp_status;
695#ifdef VBOX
696 uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
697#endif
698 CPU86_LDouble ft0;
699#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
700 uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
701#endif
702 union {
703 float f;
704 double d;
705 int i32;
706 int64_t i64;
707 } fp_convert;
708
709 float_status sse_status;
710 uint32_t mxcsr;
711 XMMReg xmm_regs[CPU_NB_REGS_VER16];
712 XMMReg xmm_t0;
713 MMXReg mmx_t0;
714
715 /* sysenter registers */
716 uint32_t sysenter_cs;
717 uint32_t sysenter_esp;
718 uint32_t sysenter_eip;
719#ifdef VBOX
720 uint32_t alignment0;
721#endif
722 uint64_t efer;
723 uint64_t star;
724
725 uint64_t pat;
726
727 /* temporary data for USE_CODE_COPY mode */
728#ifdef USE_CODE_COPY
729 uint32_t tmp0;
730 uint32_t saved_esp;
731 int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
732#endif
733
734 /* exception/interrupt handling */
735 jmp_buf jmp_env;
736} CPUX86State_Ver16;
737
738/** CPUX86State state flags
739 * @{ */
740#define CPU_RAW_RING0 0x0002 /* Set after first time RawR0 is executed, never cleared. */
741#define CPU_EMULATE_SINGLE_INSTR 0x0040 /* Execute a single instruction in emulation mode */
742#define CPU_EMULATE_SINGLE_STEP 0x0080 /* go into single step mode */
743#define CPU_RAW_HWACC 0x0100 /* Set after first time HWACC is executed, never cleared. */
744/** @} */
745#endif /* !VBOX */
746
747#ifdef VBOX
748CPUX86State *cpu_x86_init(CPUX86State *env);
749#else /* !VBOX */
750CPUX86State *cpu_x86_init(void);
751#endif /* !VBOX */
752int cpu_x86_exec(CPUX86State *s);
753void cpu_x86_close(CPUX86State *s);
754int cpu_get_pic_interrupt(CPUX86State *s);
755/* MSDOS compatibility mode FPU exception support */
756void cpu_set_ferr(CPUX86State *s);
757
758/* this function must always be used to load data in the segment
759 cache: it synchronizes the hflags with the segment cache values */
760static inline void cpu_x86_load_seg_cache(CPUX86State *env,
761 int seg_reg, unsigned int selector,
762 target_ulong base,
763 unsigned int limit,
764 unsigned int flags)
765{
766 SegmentCache *sc;
767 unsigned int new_hflags;
768
769 sc = &env->segs[seg_reg];
770 sc->selector = selector;
771 sc->base = base;
772 sc->limit = limit;
773 sc->flags = flags;
774#ifdef VBOX
775 sc->newselector = 0;
776#endif
777
778 /* update the hidden flags */
779 {
780 if (seg_reg == R_CS) {
781#ifdef TARGET_X86_64
782 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
783 /* long mode */
784 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
785 env->hflags &= ~(HF_ADDSEG_MASK);
786 } else
787#endif
788 {
789 /* legacy / compatibility case */
790 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
791 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
792 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
793 new_hflags;
794 }
795 }
796 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
797 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
798 if (env->hflags & HF_CS64_MASK) {
799 /* zero base assumed for DS, ES and SS in long mode */
800 } else if (!(env->cr[0] & CR0_PE_MASK) ||
801 (env->eflags & VM_MASK) ||
802 !(env->hflags & HF_CS32_MASK)) {
803 /* XXX: try to avoid this test. The problem comes from the
804 fact that is real mode or vm86 mode we only modify the
805 'base' and 'selector' fields of the segment cache to go
806 faster. A solution may be to force addseg to one in
807 translate-i386.c. */
808 new_hflags |= HF_ADDSEG_MASK;
809 } else {
810 new_hflags |= ((env->segs[R_DS].base |
811 env->segs[R_ES].base |
812 env->segs[R_SS].base) != 0) <<
813 HF_ADDSEG_SHIFT;
814 }
815 env->hflags = (env->hflags &
816 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
817 }
818}
819
820/* wrapper, just in case memory mappings must be changed */
821static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
822{
823#if HF_CPL_MASK == 3
824 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
825#else
826#error HF_CPL_MASK is hardcoded
827#endif
828}
829
830/* used for debug or cpu save/restore */
831void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
832CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
833
834/* the following helpers are only usable in user mode simulation as
835 they can trigger unexpected exceptions */
836void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
837void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
838void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
839
840/* you can call this signal handler from your SIGBUS and SIGSEGV
841 signal handlers to inform the virtual CPU of exceptions. non zero
842 is returned if the signal was handled by the virtual CPU. */
843int cpu_x86_signal_handler(int host_signum, void *pinfo,
844 void *puc);
845void cpu_x86_set_a20(CPUX86State *env, int a20_state);
846
847uint64_t cpu_get_tsc(CPUX86State *env);
848
849void cpu_set_apic_base(CPUX86State *env, uint64_t val);
850uint64_t cpu_get_apic_base(CPUX86State *env);
851void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
852#ifndef NO_CPU_IO_DEFS
853uint8_t cpu_get_apic_tpr(CPUX86State *env);
854#endif
855uint64_t cpu_apic_rdmsr(CPUX86State *env, uint32_t reg);
856void cpu_apic_wrmsr(CPUX86State *env, uint32_t reg, uint64_t value);
857void cpu_smm_update(CPUX86State *env);
858
859/* will be suppressed */
860void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
861
862/* used to debug */
863#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
864#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
865
866#ifdef USE_KQEMU
867static inline int cpu_get_time_fast(void)
868{
869 int low, high;
870 asm volatile("rdtsc" : "=a" (low), "=d" (high));
871 return low;
872}
873#endif
874
875#ifdef VBOX
876void cpu_trap_raw(CPUX86State *env1);
877
878/* in helper.c */
879uint8_t read_byte(CPUX86State *env1, target_ulong addr);
880uint16_t read_word(CPUX86State *env1, target_ulong addr);
881void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val);
882uint32_t read_dword(CPUX86State *env1, target_ulong addr);
883void write_word(CPUX86State *env1, target_ulong addr, uint16_t val);
884void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val);
885/* in helper.c */
886int emulate_single_instr(CPUX86State *env1);
887int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl);
888
889void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr);
890void save_raw_fp_state(CPUX86State *env, uint8_t *ptr);
891
892#endif
893
894#define TARGET_PAGE_BITS 12
895#include "cpu-all.h"
896
897#endif /* CPU_I386_H */
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