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source: vbox/trunk/src/recompiler/target-i386/exec.h@ 12519

Last change on this file since 12519 was 11982, checked in by vboxsync, 16 years ago

All: license header changes for 2.0 (OSE headers, add Sun GPL/LGPL disclaimer)
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1/*
2 * i386 execution defines
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#include "config.h"
30#include "dyngen-exec.h"
31
32/* XXX: factorize this mess */
33#ifdef TARGET_X86_64
34#define TARGET_LONG_BITS 64
35#else
36#define TARGET_LONG_BITS 32
37#endif
38
39#include "cpu-defs.h"
40
41/* at least 4 register variables are defined */
42register struct CPUX86State *env asm(AREG0);
43
44#if TARGET_LONG_BITS > HOST_LONG_BITS
45
46/* no registers can be used */
47#define T0 (env->t0)
48#define T1 (env->t1)
49#define T2 (env->t2)
50
51#else
52
53/* XXX: use unsigned long instead of target_ulong - better code will
54 be generated for 64 bit CPUs */
55register target_ulong T0 asm(AREG1);
56register target_ulong T1 asm(AREG2);
57register target_ulong T2 asm(AREG3);
58
59/* if more registers are available, we define some registers too */
60#ifdef AREG4
61register target_ulong EAX asm(AREG4);
62#define reg_EAX
63#endif
64
65#ifdef AREG5
66register target_ulong ESP asm(AREG5);
67#define reg_ESP
68#endif
69
70#ifdef AREG6
71register target_ulong EBP asm(AREG6);
72#define reg_EBP
73#endif
74
75#ifdef AREG7
76register target_ulong ECX asm(AREG7);
77#define reg_ECX
78#endif
79
80#ifdef AREG8
81register target_ulong EDX asm(AREG8);
82#define reg_EDX
83#endif
84
85#ifdef AREG9
86register target_ulong EBX asm(AREG9);
87#define reg_EBX
88#endif
89
90#ifdef AREG10
91register target_ulong ESI asm(AREG10);
92#define reg_ESI
93#endif
94
95#ifdef AREG11
96register target_ulong EDI asm(AREG11);
97#define reg_EDI
98#endif
99
100#endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */
101
102#define A0 T2
103
104extern FILE *logfile;
105extern int loglevel;
106
107#ifndef reg_EAX
108#define EAX (env->regs[R_EAX])
109#endif
110#ifndef reg_ECX
111#define ECX (env->regs[R_ECX])
112#endif
113#ifndef reg_EDX
114#define EDX (env->regs[R_EDX])
115#endif
116#ifndef reg_EBX
117#define EBX (env->regs[R_EBX])
118#endif
119#ifndef reg_ESP
120#define ESP (env->regs[R_ESP])
121#endif
122#ifndef reg_EBP
123#define EBP (env->regs[R_EBP])
124#endif
125#ifndef reg_ESI
126#define ESI (env->regs[R_ESI])
127#endif
128#ifndef reg_EDI
129#define EDI (env->regs[R_EDI])
130#endif
131#define EIP (env->eip)
132#define DF (env->df)
133
134#define CC_SRC (env->cc_src)
135#define CC_DST (env->cc_dst)
136#define CC_OP (env->cc_op)
137
138/* float macros */
139#define FT0 (env->ft0)
140#define ST0 (env->fpregs[env->fpstt].d)
141#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
142#define ST1 ST(1)
143
144#ifdef USE_FP_CONVERT
145#define FP_CONVERT (env->fp_convert)
146#endif
147
148#include "cpu.h"
149#include "exec-all.h"
150
151typedef struct CCTable {
152 int (*compute_all)(void); /* return all the flags */
153 int (*compute_c)(void); /* return the C flag */
154} CCTable;
155
156extern CCTable cc_table[];
157
158void load_seg(int seg_reg, int selector);
159void helper_ljmp_protected_T0_T1(int next_eip);
160void helper_lcall_real_T0_T1(int shift, int next_eip);
161void helper_lcall_protected_T0_T1(int shift, int next_eip);
162void helper_iret_real(int shift);
163void helper_iret_protected(int shift, int next_eip);
164void helper_lret_protected(int shift, int addend);
165void helper_lldt_T0(void);
166void helper_ltr_T0(void);
167void helper_movl_crN_T0(int reg);
168void helper_movl_drN_T0(int reg);
169void helper_invlpg(target_ulong addr);
170void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
171void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
172void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
173void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
174int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
175 int is_write, int is_user, int is_softmmu);
176void tlb_fill(target_ulong addr, int is_write, int is_user,
177 void *retaddr);
178void __hidden cpu_lock(void);
179void __hidden cpu_unlock(void);
180void do_interrupt(int intno, int is_int, int error_code,
181 target_ulong next_eip, int is_hw);
182void do_interrupt_user(int intno, int is_int, int error_code,
183 target_ulong next_eip);
184void raise_interrupt(int intno, int is_int, int error_code,
185 int next_eip_addend);
186void raise_exception_err(int exception_index, int error_code);
187void raise_exception(int exception_index);
188void do_smm_enter(void);
189void __hidden cpu_loop_exit(void);
190
191void OPPROTO op_movl_eflags_T0(void);
192void OPPROTO op_movl_T0_eflags(void);
193#ifdef VBOX
194void OPPROTO op_movl_T0_eflags_vme(void);
195void OPPROTO op_movw_eflags_T0_vme(void);
196void OPPROTO op_cli_vme(void);
197void OPPROTO op_sti_vme(void);
198#endif
199void helper_divl_EAX_T0(void);
200void helper_idivl_EAX_T0(void);
201void helper_mulq_EAX_T0(void);
202void helper_imulq_EAX_T0(void);
203void helper_imulq_T0_T1(void);
204void helper_divq_EAX_T0(void);
205void helper_idivq_EAX_T0(void);
206void helper_bswapq_T0(void);
207void helper_cmpxchg8b(void);
208void helper_single_step(void);
209void helper_cpuid(void);
210void helper_enter_level(int level, int data32);
211void helper_enter64_level(int level, int data64);
212void helper_sysenter(void);
213void helper_sysexit(void);
214void helper_syscall(int next_eip_addend);
215void helper_sysret(int dflag);
216void helper_rdtsc(void);
217void helper_rdmsr(void);
218void helper_wrmsr(void);
219void helper_lsl(void);
220void helper_lar(void);
221void helper_verr(void);
222void helper_verw(void);
223void helper_rsm(void);
224
225#ifdef VBOX
226void helper_external_event(void);
227void helper_record_call(void);
228
229/* in helper.c */
230void sync_seg(CPUX86State *env1, int seg_reg, int selector);
231void sync_ldtr(CPUX86State *env1, int selector);
232int sync_tr(CPUX86State *env1, int selector);
233
234#endif
235
236void check_iob_T0(void);
237void check_iow_T0(void);
238void check_iol_T0(void);
239void check_iob_DX(void);
240void check_iow_DX(void);
241void check_iol_DX(void);
242
243#if !defined(CONFIG_USER_ONLY)
244
245#include "softmmu_exec.h"
246
247static inline double ldfq(target_ulong ptr)
248{
249 union {
250 double d;
251 uint64_t i;
252 } u;
253 u.i = ldq(ptr);
254 return u.d;
255}
256
257static inline void stfq(target_ulong ptr, double v)
258{
259 union {
260 double d;
261 uint64_t i;
262 } u;
263 u.d = v;
264 stq(ptr, u.i);
265}
266
267static inline float ldfl(target_ulong ptr)
268{
269 union {
270 float f;
271 uint32_t i;
272 } u;
273 u.i = ldl(ptr);
274 return u.f;
275}
276
277static inline void stfl(target_ulong ptr, float v)
278{
279 union {
280 float f;
281 uint32_t i;
282 } u;
283 u.f = v;
284 stl(ptr, u.i);
285}
286
287#endif /* !defined(CONFIG_USER_ONLY) */
288
289#ifdef USE_X86LDOUBLE
290/* use long double functions */
291#define floatx_to_int32 floatx80_to_int32
292#define floatx_to_int64 floatx80_to_int64
293#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
294#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
295#define floatx_abs floatx80_abs
296#define floatx_chs floatx80_chs
297#define floatx_round_to_int floatx80_round_to_int
298#define floatx_compare floatx80_compare
299#define floatx_compare_quiet floatx80_compare_quiet
300#ifdef VBOX
301#undef sin
302#undef cos
303#undef sqrt
304#undef pow
305#undef log
306#undef tan
307#undef atan2
308#undef floor
309#undef ceil
310#undef ldexp
311#endif /* !VBOX */
312#define sin sinl
313#define cos cosl
314#define sqrt sqrtl
315#define pow powl
316#define log logl
317#define tan tanl
318#define atan2 atan2l
319#define floor floorl
320#define ceil ceill
321#define ldexp ldexpl
322#else
323#define floatx_to_int32 float64_to_int32
324#define floatx_to_int64 float64_to_int64
325#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
326#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
327#define floatx_abs float64_abs
328#define floatx_chs float64_chs
329#define floatx_round_to_int float64_round_to_int
330#define floatx_compare float64_compare
331#define floatx_compare_quiet float64_compare_quiet
332#endif
333
334extern CPU86_LDouble sin(CPU86_LDouble x);
335extern CPU86_LDouble cos(CPU86_LDouble x);
336extern CPU86_LDouble sqrt(CPU86_LDouble x);
337extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
338extern CPU86_LDouble log(CPU86_LDouble x);
339extern CPU86_LDouble tan(CPU86_LDouble x);
340extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
341extern CPU86_LDouble floor(CPU86_LDouble x);
342extern CPU86_LDouble ceil(CPU86_LDouble x);
343
344#define RC_MASK 0xc00
345#define RC_NEAR 0x000
346#define RC_DOWN 0x400
347#define RC_UP 0x800
348#define RC_CHOP 0xc00
349
350#define MAXTAN 9223372036854775808.0
351
352#ifdef USE_X86LDOUBLE
353
354/* only for x86 */
355typedef union {
356 long double d;
357 struct {
358 unsigned long long lower;
359 unsigned short upper;
360 } l;
361} CPU86_LDoubleU;
362
363/* the following deal with x86 long double-precision numbers */
364#define MAXEXPD 0x7fff
365#define EXPBIAS 16383
366#define EXPD(fp) (fp.l.upper & 0x7fff)
367#define SIGND(fp) ((fp.l.upper) & 0x8000)
368#define MANTD(fp) (fp.l.lower)
369#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
370
371#else
372
373/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
374typedef union {
375 double d;
376#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
377 struct {
378 uint32_t lower;
379 int32_t upper;
380 } l;
381#else
382 struct {
383 int32_t upper;
384 uint32_t lower;
385 } l;
386#endif
387#ifndef __arm__
388 int64_t ll;
389#endif
390} CPU86_LDoubleU;
391
392/* the following deal with IEEE double-precision numbers */
393#define MAXEXPD 0x7ff
394#define EXPBIAS 1023
395#define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
396#define SIGND(fp) ((fp.l.upper) & 0x80000000)
397#ifdef __arm__
398#define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
399#else
400#define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
401#endif
402#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
403#endif
404
405static inline void fpush(void)
406{
407 env->fpstt = (env->fpstt - 1) & 7;
408 env->fptags[env->fpstt] = 0; /* validate stack entry */
409}
410
411static inline void fpop(void)
412{
413 env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
414 env->fpstt = (env->fpstt + 1) & 7;
415}
416
417#ifndef USE_X86LDOUBLE
418static inline CPU86_LDouble helper_fldt(target_ulong ptr)
419{
420 CPU86_LDoubleU temp;
421 int upper, e;
422 uint64_t ll;
423
424 /* mantissa */
425 upper = lduw(ptr + 8);
426 /* XXX: handle overflow ? */
427 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
428 e |= (upper >> 4) & 0x800; /* sign */
429 ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
430#ifdef __arm__
431 temp.l.upper = (e << 20) | (ll >> 32);
432 temp.l.lower = ll;
433#else
434 temp.ll = ll | ((uint64_t)e << 52);
435#endif
436 return temp.d;
437}
438
439static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
440{
441 CPU86_LDoubleU temp;
442 int e;
443
444 temp.d = f;
445 /* mantissa */
446 stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
447 /* exponent + sign */
448 e = EXPD(temp) - EXPBIAS + 16383;
449 e |= SIGND(temp) >> 16;
450 stw(ptr + 8, e);
451}
452#else
453
454/* XXX: same endianness assumed */
455
456#ifdef CONFIG_USER_ONLY
457
458static inline CPU86_LDouble helper_fldt(target_ulong ptr)
459{
460 return *(CPU86_LDouble *)ptr;
461}
462
463static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
464{
465 *(CPU86_LDouble *)ptr = f;
466}
467
468#else
469
470/* we use memory access macros */
471
472static inline CPU86_LDouble helper_fldt(target_ulong ptr)
473{
474 CPU86_LDoubleU temp;
475
476 temp.l.lower = ldq(ptr);
477 temp.l.upper = lduw(ptr + 8);
478 return temp.d;
479}
480
481static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
482{
483 CPU86_LDoubleU temp;
484
485 temp.d = f;
486 stq(ptr, temp.l.lower);
487 stw(ptr + 8, temp.l.upper);
488}
489
490#endif /* !CONFIG_USER_ONLY */
491
492#endif /* USE_X86LDOUBLE */
493
494#define FPUS_IE (1 << 0)
495#define FPUS_DE (1 << 1)
496#define FPUS_ZE (1 << 2)
497#define FPUS_OE (1 << 3)
498#define FPUS_UE (1 << 4)
499#define FPUS_PE (1 << 5)
500#define FPUS_SF (1 << 6)
501#define FPUS_SE (1 << 7)
502#define FPUS_B (1 << 15)
503
504#define FPUC_EM 0x3f
505
506extern const CPU86_LDouble f15rk[7];
507
508void helper_fldt_ST0_A0(void);
509void helper_fstt_ST0_A0(void);
510void fpu_raise_exception(void);
511CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b);
512void helper_fbld_ST0_A0(void);
513void helper_fbst_ST0_A0(void);
514void helper_f2xm1(void);
515void helper_fyl2x(void);
516void helper_fptan(void);
517void helper_fpatan(void);
518void helper_fxtract(void);
519void helper_fprem1(void);
520void helper_fprem(void);
521void helper_fyl2xp1(void);
522void helper_fsqrt(void);
523void helper_fsincos(void);
524void helper_frndint(void);
525void helper_fscale(void);
526void helper_fsin(void);
527void helper_fcos(void);
528void helper_fxam_ST0(void);
529void helper_fstenv(target_ulong ptr, int data32);
530void helper_fldenv(target_ulong ptr, int data32);
531void helper_fsave(target_ulong ptr, int data32);
532void helper_frstor(target_ulong ptr, int data32);
533void helper_fxsave(target_ulong ptr, int data64);
534void helper_fxrstor(target_ulong ptr, int data64);
535void restore_native_fp_state(CPUState *env);
536void save_native_fp_state(CPUState *env);
537float approx_rsqrt(float a);
538float approx_rcp(float a);
539void update_fp_status(void);
540void helper_hlt(void);
541void helper_monitor(void);
542void helper_mwait(void);
543
544extern const uint8_t parity_table[256];
545extern const uint8_t rclw_table[32];
546extern const uint8_t rclb_table[32];
547
548static inline uint32_t compute_eflags(void)
549{
550 return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
551}
552
553/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
554static inline void load_eflags(int eflags, int update_mask)
555{
556 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
557 DF = 1 - (2 * ((eflags >> 10) & 1));
558 env->eflags = (env->eflags & ~update_mask) |
559 (eflags & update_mask);
560}
561
562static inline void env_to_regs(void)
563{
564#ifdef reg_EAX
565 EAX = env->regs[R_EAX];
566#endif
567#ifdef reg_ECX
568 ECX = env->regs[R_ECX];
569#endif
570#ifdef reg_EDX
571 EDX = env->regs[R_EDX];
572#endif
573#ifdef reg_EBX
574 EBX = env->regs[R_EBX];
575#endif
576#ifdef reg_ESP
577 ESP = env->regs[R_ESP];
578#endif
579#ifdef reg_EBP
580 EBP = env->regs[R_EBP];
581#endif
582#ifdef reg_ESI
583 ESI = env->regs[R_ESI];
584#endif
585#ifdef reg_EDI
586 EDI = env->regs[R_EDI];
587#endif
588}
589
590static inline void regs_to_env(void)
591{
592#ifdef reg_EAX
593 env->regs[R_EAX] = EAX;
594#endif
595#ifdef reg_ECX
596 env->regs[R_ECX] = ECX;
597#endif
598#ifdef reg_EDX
599 env->regs[R_EDX] = EDX;
600#endif
601#ifdef reg_EBX
602 env->regs[R_EBX] = EBX;
603#endif
604#ifdef reg_ESP
605 env->regs[R_ESP] = ESP;
606#endif
607#ifdef reg_EBP
608 env->regs[R_EBP] = EBP;
609#endif
610#ifdef reg_ESI
611 env->regs[R_ESI] = ESI;
612#endif
613#ifdef reg_EDI
614 env->regs[R_EDI] = EDI;
615#endif
616}
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