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source: vbox/trunk/src/recompiler/target-i386/exec.h@ 17390

Last change on this file since 17390 was 17039, checked in by vboxsync, 16 years ago

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1/*
2 * i386 execution defines
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#include "config.h"
30#include "dyngen-exec.h"
31
32/* XXX: factorize this mess */
33#ifdef TARGET_X86_64
34#define TARGET_LONG_BITS 64
35#else
36#define TARGET_LONG_BITS 32
37#endif
38
39#include "cpu-defs.h"
40
41/* at least 4 register variables are defined */
42register struct CPUX86State *env asm(AREG0);
43
44#if TARGET_LONG_BITS > HOST_LONG_BITS
45
46/* no registers can be used */
47#define T0 (env->t0)
48#define T1 (env->t1)
49#define T2 (env->t2)
50
51#else
52
53/* XXX: use unsigned long instead of target_ulong - better code will
54 be generated for 64 bit CPUs */
55register target_ulong T0 asm(AREG1);
56register target_ulong T1 asm(AREG2);
57register target_ulong T2 asm(AREG3);
58
59/* if more registers are available, we define some registers too */
60#ifdef AREG4
61register target_ulong EAX asm(AREG4);
62#define reg_EAX
63#endif
64
65#ifdef AREG5
66register target_ulong ESP asm(AREG5);
67#define reg_ESP
68#endif
69
70#ifdef AREG6
71register target_ulong EBP asm(AREG6);
72#define reg_EBP
73#endif
74
75#ifdef AREG7
76register target_ulong ECX asm(AREG7);
77#define reg_ECX
78#endif
79
80#ifdef AREG8
81register target_ulong EDX asm(AREG8);
82#define reg_EDX
83#endif
84
85#ifdef AREG9
86register target_ulong EBX asm(AREG9);
87#define reg_EBX
88#endif
89
90#ifdef AREG10
91register target_ulong ESI asm(AREG10);
92#define reg_ESI
93#endif
94
95#ifdef AREG11
96register target_ulong EDI asm(AREG11);
97#define reg_EDI
98#endif
99
100#endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */
101
102#define A0 T2
103
104extern FILE *logfile;
105extern int loglevel;
106
107#ifndef reg_EAX
108#define EAX (env->regs[R_EAX])
109#endif
110#ifndef reg_ECX
111#define ECX (env->regs[R_ECX])
112#endif
113#ifndef reg_EDX
114#define EDX (env->regs[R_EDX])
115#endif
116#ifndef reg_EBX
117#define EBX (env->regs[R_EBX])
118#endif
119#ifndef reg_ESP
120#define ESP (env->regs[R_ESP])
121#endif
122#ifndef reg_EBP
123#define EBP (env->regs[R_EBP])
124#endif
125#ifndef reg_ESI
126#define ESI (env->regs[R_ESI])
127#endif
128#ifndef reg_EDI
129#define EDI (env->regs[R_EDI])
130#endif
131#define EIP (env->eip)
132#define DF (env->df)
133
134#define CC_SRC (env->cc_src)
135#define CC_DST (env->cc_dst)
136#define CC_OP (env->cc_op)
137
138/* float macros */
139#define FT0 (env->ft0)
140#define ST0 (env->fpregs[env->fpstt].d)
141#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
142#define ST1 ST(1)
143
144#ifdef USE_FP_CONVERT
145#define FP_CONVERT (env->fp_convert)
146#endif
147
148#include "cpu.h"
149#include "exec-all.h"
150
151typedef struct CCTable {
152 int (*compute_all)(void); /* return all the flags */
153 int (*compute_c)(void); /* return the C flag */
154} CCTable;
155
156extern CCTable cc_table[];
157
158void load_seg(int seg_reg, int selector);
159void helper_ljmp_protected_T0_T1(int next_eip);
160void helper_lcall_real_T0_T1(int shift, int next_eip);
161void helper_lcall_protected_T0_T1(int shift, int next_eip);
162void helper_iret_real(int shift);
163void helper_iret_protected(int shift, int next_eip);
164void helper_lret_protected(int shift, int addend);
165void helper_lldt_T0(void);
166void helper_ltr_T0(void);
167void helper_movl_crN_T0(int reg);
168void helper_movl_drN_T0(int reg);
169void helper_invlpg(target_ulong addr);
170void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
171void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
172void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
173void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
174int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
175 int is_write, int is_user, int is_softmmu);
176void tlb_fill(target_ulong addr, int is_write, int is_user,
177 void *retaddr);
178void __hidden cpu_lock(void);
179void __hidden cpu_unlock(void);
180void do_interrupt(int intno, int is_int, int error_code,
181 target_ulong next_eip, int is_hw);
182void do_interrupt_user(int intno, int is_int, int error_code,
183 target_ulong next_eip);
184void raise_interrupt(int intno, int is_int, int error_code,
185 int next_eip_addend);
186void raise_exception_err(int exception_index, int error_code);
187void raise_exception(int exception_index);
188void do_smm_enter(void);
189void __hidden cpu_loop_exit(void);
190
191void OPPROTO op_movl_eflags_T0(void);
192void OPPROTO op_movl_T0_eflags(void);
193#ifdef VBOX
194void OPPROTO op_movl_T0_eflags_vme(void);
195void OPPROTO op_movw_eflags_T0_vme(void);
196void OPPROTO op_cli_vme(void);
197void OPPROTO op_sti_vme(void);
198#endif
199void helper_divl_EAX_T0(void);
200void helper_idivl_EAX_T0(void);
201void helper_mulq_EAX_T0(void);
202void helper_imulq_EAX_T0(void);
203void helper_imulq_T0_T1(void);
204void helper_divq_EAX_T0(void);
205void helper_idivq_EAX_T0(void);
206void helper_bswapq_T0(void);
207void helper_cmpxchg8b(void);
208void helper_single_step(void);
209void helper_cpuid(void);
210void helper_enter_level(int level, int data32);
211void helper_enter64_level(int level, int data64);
212void helper_sysenter(void);
213void helper_sysexit(void);
214void helper_syscall(int next_eip_addend);
215void helper_sysret(int dflag);
216void helper_rdtsc(void);
217#ifdef VBOX
218void helper_rdtscp(void);
219#endif
220void helper_rdmsr(void);
221void helper_wrmsr(void);
222void helper_lsl(void);
223void helper_lar(void);
224void helper_verr(void);
225void helper_verw(void);
226void helper_rsm(void);
227
228#ifdef VBOX
229void helper_external_event(void);
230void helper_record_call(void);
231
232/* in helper.c */
233void sync_seg(CPUX86State *env1, int seg_reg, int selector);
234void sync_ldtr(CPUX86State *env1, int selector);
235
236#endif
237
238void check_iob_T0(void);
239void check_iow_T0(void);
240void check_iol_T0(void);
241void check_iob_DX(void);
242void check_iow_DX(void);
243void check_iol_DX(void);
244
245#if !defined(CONFIG_USER_ONLY)
246
247#include "softmmu_exec.h"
248
249static inline double ldfq(target_ulong ptr)
250{
251 union {
252 double d;
253 uint64_t i;
254 } u;
255 u.i = ldq(ptr);
256 return u.d;
257}
258
259static inline void stfq(target_ulong ptr, double v)
260{
261 union {
262 double d;
263 uint64_t i;
264 } u;
265 u.d = v;
266 stq(ptr, u.i);
267}
268
269static inline float ldfl(target_ulong ptr)
270{
271 union {
272 float f;
273 uint32_t i;
274 } u;
275 u.i = ldl(ptr);
276 return u.f;
277}
278
279static inline void stfl(target_ulong ptr, float v)
280{
281 union {
282 float f;
283 uint32_t i;
284 } u;
285 u.f = v;
286 stl(ptr, u.i);
287}
288
289#endif /* !defined(CONFIG_USER_ONLY) */
290
291#ifdef USE_X86LDOUBLE
292/* use long double functions */
293#define floatx_to_int32 floatx80_to_int32
294#define floatx_to_int64 floatx80_to_int64
295#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
296#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
297#define floatx_abs floatx80_abs
298#define floatx_chs floatx80_chs
299#define floatx_round_to_int floatx80_round_to_int
300#define floatx_compare floatx80_compare
301#define floatx_compare_quiet floatx80_compare_quiet
302#ifdef VBOX
303#undef sin
304#undef cos
305#undef sqrt
306#undef pow
307#undef log
308#undef tan
309#undef atan2
310#undef floor
311#undef ceil
312#undef ldexp
313#endif /* !VBOX */
314#define sin sinl
315#define cos cosl
316#define sqrt sqrtl
317#define pow powl
318#define log logl
319#define tan tanl
320#define atan2 atan2l
321#define floor floorl
322#define ceil ceill
323#define ldexp ldexpl
324#else
325#define floatx_to_int32 float64_to_int32
326#define floatx_to_int64 float64_to_int64
327#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
328#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
329#define floatx_abs float64_abs
330#define floatx_chs float64_chs
331#define floatx_round_to_int float64_round_to_int
332#define floatx_compare float64_compare
333#define floatx_compare_quiet float64_compare_quiet
334#endif
335
336extern CPU86_LDouble sin(CPU86_LDouble x);
337extern CPU86_LDouble cos(CPU86_LDouble x);
338extern CPU86_LDouble sqrt(CPU86_LDouble x);
339extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
340extern CPU86_LDouble log(CPU86_LDouble x);
341extern CPU86_LDouble tan(CPU86_LDouble x);
342extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
343extern CPU86_LDouble floor(CPU86_LDouble x);
344extern CPU86_LDouble ceil(CPU86_LDouble x);
345
346#define RC_MASK 0xc00
347#define RC_NEAR 0x000
348#define RC_DOWN 0x400
349#define RC_UP 0x800
350#define RC_CHOP 0xc00
351
352#define MAXTAN 9223372036854775808.0
353
354#ifdef USE_X86LDOUBLE
355
356/* only for x86 */
357typedef union {
358 long double d;
359 struct {
360 unsigned long long lower;
361 unsigned short upper;
362 } l;
363} CPU86_LDoubleU;
364
365/* the following deal with x86 long double-precision numbers */
366#define MAXEXPD 0x7fff
367#define EXPBIAS 16383
368#define EXPD(fp) (fp.l.upper & 0x7fff)
369#define SIGND(fp) ((fp.l.upper) & 0x8000)
370#define MANTD(fp) (fp.l.lower)
371#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
372
373#else
374
375/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
376typedef union {
377 double d;
378#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
379 struct {
380 uint32_t lower;
381 int32_t upper;
382 } l;
383#else
384 struct {
385 int32_t upper;
386 uint32_t lower;
387 } l;
388#endif
389#ifndef __arm__
390 int64_t ll;
391#endif
392} CPU86_LDoubleU;
393
394/* the following deal with IEEE double-precision numbers */
395#define MAXEXPD 0x7ff
396#define EXPBIAS 1023
397#define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
398#define SIGND(fp) ((fp.l.upper) & 0x80000000)
399#ifdef __arm__
400#define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
401#else
402#define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
403#endif
404#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
405#endif
406
407static inline void fpush(void)
408{
409 env->fpstt = (env->fpstt - 1) & 7;
410 env->fptags[env->fpstt] = 0; /* validate stack entry */
411}
412
413static inline void fpop(void)
414{
415 env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
416 env->fpstt = (env->fpstt + 1) & 7;
417}
418
419#ifndef USE_X86LDOUBLE
420static inline CPU86_LDouble helper_fldt(target_ulong ptr)
421{
422 CPU86_LDoubleU temp;
423 int upper, e;
424 uint64_t ll;
425
426 /* mantissa */
427 upper = lduw(ptr + 8);
428 /* XXX: handle overflow ? */
429 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
430 e |= (upper >> 4) & 0x800; /* sign */
431 ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
432#ifdef __arm__
433 temp.l.upper = (e << 20) | (ll >> 32);
434 temp.l.lower = ll;
435#else
436 temp.ll = ll | ((uint64_t)e << 52);
437#endif
438 return temp.d;
439}
440
441static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
442{
443 CPU86_LDoubleU temp;
444 int e;
445
446 temp.d = f;
447 /* mantissa */
448 stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
449 /* exponent + sign */
450 e = EXPD(temp) - EXPBIAS + 16383;
451 e |= SIGND(temp) >> 16;
452 stw(ptr + 8, e);
453}
454#else
455
456/* XXX: same endianness assumed */
457
458#ifdef CONFIG_USER_ONLY
459
460static inline CPU86_LDouble helper_fldt(target_ulong ptr)
461{
462 return *(CPU86_LDouble *)ptr;
463}
464
465static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
466{
467 *(CPU86_LDouble *)ptr = f;
468}
469
470#else
471
472/* we use memory access macros */
473
474static inline CPU86_LDouble helper_fldt(target_ulong ptr)
475{
476 CPU86_LDoubleU temp;
477
478 temp.l.lower = ldq(ptr);
479 temp.l.upper = lduw(ptr + 8);
480 return temp.d;
481}
482
483static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
484{
485 CPU86_LDoubleU temp;
486
487 temp.d = f;
488 stq(ptr, temp.l.lower);
489 stw(ptr + 8, temp.l.upper);
490}
491
492#endif /* !CONFIG_USER_ONLY */
493
494#endif /* USE_X86LDOUBLE */
495
496#define FPUS_IE (1 << 0)
497#define FPUS_DE (1 << 1)
498#define FPUS_ZE (1 << 2)
499#define FPUS_OE (1 << 3)
500#define FPUS_UE (1 << 4)
501#define FPUS_PE (1 << 5)
502#define FPUS_SF (1 << 6)
503#define FPUS_SE (1 << 7)
504#define FPUS_B (1 << 15)
505
506#define FPUC_EM 0x3f
507
508extern const CPU86_LDouble f15rk[7];
509
510void helper_fldt_ST0_A0(void);
511void helper_fstt_ST0_A0(void);
512void fpu_raise_exception(void);
513CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b);
514void helper_fbld_ST0_A0(void);
515void helper_fbst_ST0_A0(void);
516void helper_f2xm1(void);
517void helper_fyl2x(void);
518void helper_fptan(void);
519void helper_fpatan(void);
520void helper_fxtract(void);
521void helper_fprem1(void);
522void helper_fprem(void);
523void helper_fyl2xp1(void);
524void helper_fsqrt(void);
525void helper_fsincos(void);
526void helper_frndint(void);
527void helper_fscale(void);
528void helper_fsin(void);
529void helper_fcos(void);
530void helper_fxam_ST0(void);
531void helper_fstenv(target_ulong ptr, int data32);
532void helper_fldenv(target_ulong ptr, int data32);
533void helper_fsave(target_ulong ptr, int data32);
534void helper_frstor(target_ulong ptr, int data32);
535void helper_fxsave(target_ulong ptr, int data64);
536void helper_fxrstor(target_ulong ptr, int data64);
537void restore_native_fp_state(CPUState *env);
538void save_native_fp_state(CPUState *env);
539float approx_rsqrt(float a);
540float approx_rcp(float a);
541void update_fp_status(void);
542void helper_hlt(void);
543void helper_monitor(void);
544void helper_mwait(void);
545
546extern const uint8_t parity_table[256];
547extern const uint8_t rclw_table[32];
548extern const uint8_t rclb_table[32];
549
550static inline uint32_t compute_eflags(void)
551{
552 return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
553}
554
555/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
556static inline void load_eflags(int eflags, int update_mask)
557{
558 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
559 DF = 1 - (2 * ((eflags >> 10) & 1));
560 env->eflags = (env->eflags & ~update_mask) |
561 (eflags & update_mask);
562}
563
564static inline void env_to_regs(void)
565{
566#ifdef reg_EAX
567 EAX = env->regs[R_EAX];
568#endif
569#ifdef reg_ECX
570 ECX = env->regs[R_ECX];
571#endif
572#ifdef reg_EDX
573 EDX = env->regs[R_EDX];
574#endif
575#ifdef reg_EBX
576 EBX = env->regs[R_EBX];
577#endif
578#ifdef reg_ESP
579 ESP = env->regs[R_ESP];
580#endif
581#ifdef reg_EBP
582 EBP = env->regs[R_EBP];
583#endif
584#ifdef reg_ESI
585 ESI = env->regs[R_ESI];
586#endif
587#ifdef reg_EDI
588 EDI = env->regs[R_EDI];
589#endif
590}
591
592static inline void regs_to_env(void)
593{
594#ifdef reg_EAX
595 env->regs[R_EAX] = EAX;
596#endif
597#ifdef reg_ECX
598 env->regs[R_ECX] = ECX;
599#endif
600#ifdef reg_EDX
601 env->regs[R_EDX] = EDX;
602#endif
603#ifdef reg_EBX
604 env->regs[R_EBX] = EBX;
605#endif
606#ifdef reg_ESP
607 env->regs[R_ESP] = ESP;
608#endif
609#ifdef reg_EBP
610 env->regs[R_EBP] = EBP;
611#endif
612#ifdef reg_ESI
613 env->regs[R_ESI] = ESI;
614#endif
615#ifdef reg_EDI
616 env->regs[R_EDI] = EDI;
617#endif
618}
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