helper.c@ 12240

Last change on this file since 12240 was 12240, checked in by vboxsync, 16 years ago
cmpxchg8b bugfix (without the EAX cast the result is incorrect).
Property svn:eol-style set to `native`
File size: 134.9 KB

Line
1	/*
2	* i386 helpers
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/*
22	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
24	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25	* a choice of LGPL license versions is made available with the language indicating
26	* that LGPLv2 or any later version may be used, or where a choice of which version
27	* of the LGPL is applied is otherwise unspecified.
28	*/
29	#ifdef VBOX
30	# include <VBox/err.h>
31	#endif
32	#include "exec.h"
33
34	//#define DEBUG_PCALL
35
36	#if 0
37	#define raise_exception_err(a, b)\
38	do {\
39	if (logfile)\
40	fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
41	(raise_exception_err)(a, b);\
42	} while (0)
43	#endif
44
45	const uint8_t parity_table[256] = {
46	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
56	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
58	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
59	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
61	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
66	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
68	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
69	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
70	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
71	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
72	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
73	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
74	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
75	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
76	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
77	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
78	};
79
80	/* modulo 17 table */
81	const uint8_t rclw_table[32] = {
82	0, 1, 2, 3, 4, 5, 6, 7,
83	8, 9,10,11,12,13,14,15,
84	16, 0, 1, 2, 3, 4, 5, 6,
85	7, 8, 9,10,11,12,13,14,
86	};
87
88	/* modulo 9 table */
89	const uint8_t rclb_table[32] = {
90	0, 1, 2, 3, 4, 5, 6, 7,
91	8, 0, 1, 2, 3, 4, 5, 6,
92	7, 8, 0, 1, 2, 3, 4, 5,
93	6, 7, 8, 0, 1, 2, 3, 4,
94	};
95
96	const CPU86_LDouble f15rk[7] =
97	{
98	0.00000000000000000000L,
99	1.00000000000000000000L,
100	3.14159265358979323851L, /pi/
101	0.30102999566398119523L, /lg2/
102	0.69314718055994530943L, /ln2/
103	1.44269504088896340739L, /l2e/
104	3.32192809488736234781L, /l2t/
105	};
106
107	/* thread support */
108
109	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
110
111	void cpu_lock(void)
112	{
113	spin_lock(&global_cpu_lock);
114	}
115
116	void cpu_unlock(void)
117	{
118	spin_unlock(&global_cpu_lock);
119	}
120
121	void cpu_loop_exit(void)
122	{
123	/* NOTE: the register at this point must be saved by hand because
124	longjmp restore them */
125	regs_to_env();
126	longjmp(env->jmp_env, 1);
127	}
128
129	/* return non zero if error */
130	static inline int load_segment(uint32_t e1_ptr, uint32_t e2_ptr,
131	int selector)
132	{
133	SegmentCache *dt;
134	int index;
135	target_ulong ptr;
136
137	if (selector & 0x4)
138	dt = &env->ldt;
139	else
140	dt = &env->gdt;
141	index = selector & ~7;
142	if ((index + 7) > dt->limit)
143	return -1;
144	ptr = dt->base + index;
145	*e1_ptr = ldl_kernel(ptr);
146	*e2_ptr = ldl_kernel(ptr + 4);
147	return 0;
148	}
149
150	static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
151	{
152	unsigned int limit;
153	limit = (e1 & 0xffff) \| (e2 & 0x000f0000);
154	if (e2 & DESC_G_MASK)
155	limit = (limit << 12) \| 0xfff;
156	return limit;
157	}
158
159	static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
160	{
161	return ((e1 >> 16) \| ((e2 & 0xff) << 16) \| (e2 & 0xff000000));
162	}
163
164	static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
165	{
166	sc->base = get_seg_base(e1, e2);
167	sc->limit = get_seg_limit(e1, e2);
168	sc->flags = e2;
169	}
170
171	/* init the segment cache in vm86 mode. */
172	static inline void load_seg_vm(int seg, int selector)
173	{
174	selector &= 0xffff;
175	cpu_x86_load_seg_cache(env, seg, selector,
176	(selector << 4), 0xffff, 0);
177	}
178
179	static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
180	uint32_t *esp_ptr, int dpl)
181	{
182	int type, index, shift;
183
184	#if 0
185	{
186	int i;
187	printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
188	for(i=0;i<env->tr.limit;i++) {
189	printf("%02x ", env->tr.base[i]);
190	if ((i & 7) == 7) printf("\n");
191	}
192	printf("\n");
193	}
194	#endif
195
196	if (!(env->tr.flags & DESC_P_MASK))
197	cpu_abort(env, "invalid tss");
198	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
199	if ((type & 7) != 1)
200	cpu_abort(env, "invalid tss type %d", type);
201	shift = type >> 3;
202	index = (dpl * 4 + 2) << shift;
203	if (index + (4 << shift) - 1 > env->tr.limit)
204	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
205	if (shift == 0) {
206	*esp_ptr = lduw_kernel(env->tr.base + index);
207	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
208	} else {
209	*esp_ptr = ldl_kernel(env->tr.base + index);
210	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
211	}
212	}
213
214	/* XXX: merge with load_seg() */
215	static void tss_load_seg(int seg_reg, int selector)
216	{
217	uint32_t e1, e2;
218	int rpl, dpl, cpl;
219
220	if ((selector & 0xfffc) != 0) {
221	if (load_segment(&e1, &e2, selector) != 0)
222	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
223	if (!(e2 & DESC_S_MASK))
224	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
225	rpl = selector & 3;
226	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
227	cpl = env->hflags & HF_CPL_MASK;
228	if (seg_reg == R_CS) {
229	if (!(e2 & DESC_CS_MASK))
230	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231	/* XXX: is it correct ? */
232	if (dpl != rpl)
233	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
234	if ((e2 & DESC_C_MASK) && dpl > rpl)
235	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
236	} else if (seg_reg == R_SS) {
237	/* SS must be writable data */
238	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
239	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
240	if (dpl != cpl \|\| dpl != rpl)
241	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
242	} else {
243	/* not readable code */
244	if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
245	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
246	/* if data or non conforming code, checks the rights */
247	if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
248	if (dpl < cpl \|\| dpl < rpl)
249	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
250	}
251	}
252	if (!(e2 & DESC_P_MASK))
253	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
254	cpu_x86_load_seg_cache(env, seg_reg, selector,
255	get_seg_base(e1, e2),
256	get_seg_limit(e1, e2),
257	e2);
258	} else {
259	if (seg_reg == R_SS \|\| seg_reg == R_CS)
260	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
261	}
262	}
263
264	#define SWITCH_TSS_JMP 0
265	#define SWITCH_TSS_IRET 1
266	#define SWITCH_TSS_CALL 2
267
268	/* XXX: restore CPU state in registers (PowerPC case) */
269	static void switch_tss(int tss_selector,
270	uint32_t e1, uint32_t e2, int source,
271	uint32_t next_eip)
272	{
273	int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
274	target_ulong tss_base;
275	uint32_t new_regs[8], new_segs[6];
276	uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
277	uint32_t old_eflags, eflags_mask;
278	SegmentCache *dt;
279	int index;
280	target_ulong ptr;
281
282	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
283	#ifdef DEBUG_PCALL
284	if (loglevel & CPU_LOG_PCALL)
285	fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
286	#endif
287
288	#if defined(VBOX) && defined(DEBUG)
289	printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
290	#endif
291
292	/* if task gate, we read the TSS segment and we load it */
293	if (type == 5) {
294	if (!(e2 & DESC_P_MASK))
295	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
296	tss_selector = e1 >> 16;
297	if (tss_selector & 4)
298	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
299	if (load_segment(&e1, &e2, tss_selector) != 0)
300	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
301	if (e2 & DESC_S_MASK)
302	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
303	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
304	if ((type & 7) != 1)
305	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
306	}
307
308	if (!(e2 & DESC_P_MASK))
309	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
310
311	if (type & 8)
312	tss_limit_max = 103;
313	else
314	tss_limit_max = 43;
315	tss_limit = get_seg_limit(e1, e2);
316	tss_base = get_seg_base(e1, e2);
317	if ((tss_selector & 4) != 0 \|\|
318	tss_limit < tss_limit_max)
319	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
320	old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
321	if (old_type & 8)
322	old_tss_limit_max = 103;
323	else
324	old_tss_limit_max = 43;
325
326	/* read all the registers from the new TSS */
327	if (type & 8) {
328	/* 32 bit */
329	new_cr3 = ldl_kernel(tss_base + 0x1c);
330	new_eip = ldl_kernel(tss_base + 0x20);
331	new_eflags = ldl_kernel(tss_base + 0x24);
332	for(i = 0; i < 8; i++)
333	new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
334	for(i = 0; i < 6; i++)
335	new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
336	new_ldt = lduw_kernel(tss_base + 0x60);
337	new_trap = ldl_kernel(tss_base + 0x64);
338	} else {
339	/* 16 bit */
340	new_cr3 = 0;
341	new_eip = lduw_kernel(tss_base + 0x0e);
342	new_eflags = lduw_kernel(tss_base + 0x10);
343	for(i = 0; i < 8; i++)
344	new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) \| 0xffff0000;
345	for(i = 0; i < 4; i++)
346	new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
347	new_ldt = lduw_kernel(tss_base + 0x2a);
348	new_segs[R_FS] = 0;
349	new_segs[R_GS] = 0;
350	new_trap = 0;
351	}
352
353	/* NOTE: we must avoid memory exceptions during the task switch,
354	so we make dummy accesses before */
355	/* XXX: it can still fail in some cases, so a bigger hack is
356	necessary to valid the TLB after having done the accesses */
357
358	v1 = ldub_kernel(env->tr.base);
359	v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
360	stb_kernel(env->tr.base, v1);
361	stb_kernel(env->tr.base + old_tss_limit_max, v2);
362
363	/* clear busy bit (it is restartable) */
364	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_IRET) {
365	target_ulong ptr;
366	uint32_t e2;
367	ptr = env->gdt.base + (env->tr.selector & ~7);
368	e2 = ldl_kernel(ptr + 4);
369	e2 &= ~DESC_TSS_BUSY_MASK;
370	stl_kernel(ptr + 4, e2);
371	}
372	old_eflags = compute_eflags();
373	if (source == SWITCH_TSS_IRET)
374	old_eflags &= ~NT_MASK;
375
376	/* save the current state in the old TSS */
377	if (type & 8) {
378	/* 32 bit */
379	stl_kernel(env->tr.base + 0x20, next_eip);
380	stl_kernel(env->tr.base + 0x24, old_eflags);
381	stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
382	stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
383	stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
384	stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
385	stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
386	stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
387	stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
388	stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
389	for(i = 0; i < 6; i++)
390	stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
391	#if defined(VBOX) && defined(DEBUG)
392	printf("TSS 32 bits switch\n");
393	printf("Saving CS=%08X\n", env->segs[R_CS].selector);
394	#endif
395	} else {
396	/* 16 bit */
397	stw_kernel(env->tr.base + 0x0e, next_eip);
398	stw_kernel(env->tr.base + 0x10, old_eflags);
399	stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
400	stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
401	stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
402	stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
403	stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
404	stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
405	stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
406	stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
407	for(i = 0; i < 4; i++)
408	stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
409	}
410
411	/* now if an exception occurs, it will occurs in the next task
412	context */
413
414	if (source == SWITCH_TSS_CALL) {
415	stw_kernel(tss_base, env->tr.selector);
416	new_eflags \|= NT_MASK;
417	}
418
419	/* set busy bit */
420	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_CALL) {
421	target_ulong ptr;
422	uint32_t e2;
423	ptr = env->gdt.base + (tss_selector & ~7);
424	e2 = ldl_kernel(ptr + 4);
425	e2 \|= DESC_TSS_BUSY_MASK;
426	stl_kernel(ptr + 4, e2);
427	}
428
429	/* set the new CPU state */
430	/* from this point, any exception which occurs can give problems */
431	env->cr[0] \|= CR0_TS_MASK;
432	env->hflags \|= HF_TS_MASK;
433	env->tr.selector = tss_selector;
434	env->tr.base = tss_base;
435	env->tr.limit = tss_limit;
436	env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
437
438	if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
439	cpu_x86_update_cr3(env, new_cr3);
440	}
441
442	/* load all registers without an exception, then reload them with
443	possible exception */
444	env->eip = new_eip;
445	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \|
446	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK;
447	if (!(type & 8))
448	eflags_mask &= 0xffff;
449	load_eflags(new_eflags, eflags_mask);
450	/* XXX: what to do in 16 bit case ? */
451	EAX = new_regs[0];
452	ECX = new_regs[1];
453	EDX = new_regs[2];
454	EBX = new_regs[3];
455	ESP = new_regs[4];
456	EBP = new_regs[5];
457	ESI = new_regs[6];
458	EDI = new_regs[7];
459	if (new_eflags & VM_MASK) {
460	for(i = 0; i < 6; i++)
461	load_seg_vm(i, new_segs[i]);
462	/* in vm86, CPL is always 3 */
463	cpu_x86_set_cpl(env, 3);
464	} else {
465	/* CPL is set the RPL of CS */
466	cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
467	/* first just selectors as the rest may trigger exceptions */
468	for(i = 0; i < 6; i++)
469	cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
470	}
471
472	env->ldt.selector = new_ldt & ~4;
473	env->ldt.base = 0;
474	env->ldt.limit = 0;
475	env->ldt.flags = 0;
476
477	/* load the LDT */
478	if (new_ldt & 4)
479	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
480
481	if ((new_ldt & 0xfffc) != 0) {
482	dt = &env->gdt;
483	index = new_ldt & ~7;
484	if ((index + 7) > dt->limit)
485	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486	ptr = dt->base + index;
487	e1 = ldl_kernel(ptr);
488	e2 = ldl_kernel(ptr + 4);
489	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
490	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
491	if (!(e2 & DESC_P_MASK))
492	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
493	load_seg_cache_raw_dt(&env->ldt, e1, e2);
494	}
495
496	/* load the segments */
497	if (!(new_eflags & VM_MASK)) {
498	tss_load_seg(R_CS, new_segs[R_CS]);
499	tss_load_seg(R_SS, new_segs[R_SS]);
500	tss_load_seg(R_ES, new_segs[R_ES]);
501	tss_load_seg(R_DS, new_segs[R_DS]);
502	tss_load_seg(R_FS, new_segs[R_FS]);
503	tss_load_seg(R_GS, new_segs[R_GS]);
504	}
505
506	/* check that EIP is in the CS segment limits */
507	if (new_eip > env->segs[R_CS].limit) {
508	/* XXX: different exception if CALL ? */
509	raise_exception_err(EXCP0D_GPF, 0);
510	}
511	}
512
513	/* check if Port I/O is allowed in TSS */
514	static inline void check_io(int addr, int size)
515	{
516	int io_offset, val, mask;
517
518	/* TSS must be a valid 32 bit one */
519	if (!(env->tr.flags & DESC_P_MASK) \|\|
520	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
521	env->tr.limit < 103)
522	goto fail;
523	io_offset = lduw_kernel(env->tr.base + 0x66);
524	io_offset += (addr >> 3);
525	/* Note: the check needs two bytes */
526	if ((io_offset + 1) > env->tr.limit)
527	goto fail;
528	val = lduw_kernel(env->tr.base + io_offset);
529	val >>= (addr & 7);
530	mask = (1 << size) - 1;
531	/* all bits must be zero to allow the I/O */
532	if ((val & mask) != 0) {
533	fail:
534	raise_exception_err(EXCP0D_GPF, 0);
535	}
536	}
537
538	void check_iob_T0(void)
539	{
540	check_io(T0, 1);
541	}
542
543	void check_iow_T0(void)
544	{
545	check_io(T0, 2);
546	}
547
548	void check_iol_T0(void)
549	{
550	check_io(T0, 4);
551	}
552
553	void check_iob_DX(void)
554	{
555	check_io(EDX & 0xffff, 1);
556	}
557
558	void check_iow_DX(void)
559	{
560	check_io(EDX & 0xffff, 2);
561	}
562
563	void check_iol_DX(void)
564	{
565	check_io(EDX & 0xffff, 4);
566	}
567
568	static inline unsigned int get_sp_mask(unsigned int e2)
569	{
570	if (e2 & DESC_B_MASK)
571	return 0xffffffff;
572	else
573	return 0xffff;
574	}
575
576	#ifdef TARGET_X86_64
577	#define SET_ESP(val, sp_mask)\
578	do {\
579	if ((sp_mask) == 0xffff)\
580	ESP = (ESP & ~0xffff) \| ((val) & 0xffff);\
581	else if ((sp_mask) == 0xffffffffLL)\
582	ESP = (uint32_t)(val);\
583	else\
584	ESP = (val);\
585	} while (0)
586	#else
587	#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) \| ((val) & (sp_mask))
588	#endif
589
590	/* XXX: add a is_user flag to have proper security support */
591	#define PUSHW(ssp, sp, sp_mask, val)\
592	{\
593	sp -= 2;\
594	stw_kernel((ssp) + (sp & (sp_mask)), (val));\
595	}
596
597	#define PUSHL(ssp, sp, sp_mask, val)\
598	{\
599	sp -= 4;\
600	stl_kernel((ssp) + (sp & (sp_mask)), (val));\
601	}
602
603	#define POPW(ssp, sp, sp_mask, val)\
604	{\
605	val = lduw_kernel((ssp) + (sp & (sp_mask)));\
606	sp += 2;\
607	}
608
609	#define POPL(ssp, sp, sp_mask, val)\
610	{\
611	val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
612	sp += 4;\
613	}
614
615	/* protected mode interrupt */
616	static void do_interrupt_protected(int intno, int is_int, int error_code,
617	unsigned int next_eip, int is_hw)
618	{
619	SegmentCache *dt;
620	target_ulong ptr, ssp;
621	int type, dpl, selector, ss_dpl, cpl;
622	int has_error_code, new_stack, shift;
623	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
624	uint32_t old_eip, sp_mask;
625
626	#ifdef VBOX
627	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
628	cpu_loop_exit();
629	#endif
630
631	has_error_code = 0;
632	if (!is_int && !is_hw) {
633	switch(intno) {
634	case 8:
635	case 10:
636	case 11:
637	case 12:
638	case 13:
639	case 14:
640	case 17:
641	has_error_code = 1;
642	break;
643	}
644	}
645	if (is_int)
646	old_eip = next_eip;
647	else
648	old_eip = env->eip;
649
650	dt = &env->idt;
651	if (intno * 8 + 7 > dt->limit)
652	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
653	ptr = dt->base + intno * 8;
654	e1 = ldl_kernel(ptr);
655	e2 = ldl_kernel(ptr + 4);
656	/* check gate type */
657	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
658	switch(type) {
659	case 5: /* task gate */
660	/* must do that check here to return the correct error code */
661	if (!(e2 & DESC_P_MASK))
662	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
663	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
664	if (has_error_code) {
665	int type;
666	uint32_t mask;
667	/* push the error code */
668	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
669	shift = type >> 3;
670	if (env->segs[R_SS].flags & DESC_B_MASK)
671	mask = 0xffffffff;
672	else
673	mask = 0xffff;
674	esp = (ESP - (2 << shift)) & mask;
675	ssp = env->segs[R_SS].base + esp;
676	if (shift)
677	stl_kernel(ssp, error_code);
678	else
679	stw_kernel(ssp, error_code);
680	SET_ESP(esp, mask);
681	}
682	return;
683	case 6: /* 286 interrupt gate */
684	case 7: /* 286 trap gate */
685	case 14: /* 386 interrupt gate */
686	case 15: /* 386 trap gate */
687	break;
688	default:
689	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
690	break;
691	}
692	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
693	cpl = env->hflags & HF_CPL_MASK;
694	/* check privledge if software int */
695	if (is_int && dpl < cpl)
696	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
697	/* check valid bit */
698	if (!(e2 & DESC_P_MASK))
699	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
700	selector = e1 >> 16;
701	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
702	if ((selector & 0xfffc) == 0)
703	raise_exception_err(EXCP0D_GPF, 0);
704
705	if (load_segment(&e1, &e2, selector) != 0)
706	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
707	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
708	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
709	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
710	if (dpl > cpl)
711	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
712	if (!(e2 & DESC_P_MASK))
713	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
714	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
715	/* to inner priviledge */
716	get_ss_esp_from_tss(&ss, &esp, dpl);
717	if ((ss & 0xfffc) == 0)
718	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
719	if ((ss & 3) != dpl)
720	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
721	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
722	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
723	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
724	if (ss_dpl != dpl)
725	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
726	if (!(ss_e2 & DESC_S_MASK) \|\|
727	(ss_e2 & DESC_CS_MASK) \|\|
728	!(ss_e2 & DESC_W_MASK))
729	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
730	if (!(ss_e2 & DESC_P_MASK))
731	#ifdef VBOX /* See page 3-477 of 253666.pdf */
732	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
733	#else
734	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
735	#endif
736	new_stack = 1;
737	sp_mask = get_sp_mask(ss_e2);
738	ssp = get_seg_base(ss_e1, ss_e2);
739	#if defined(VBOX) && defined(DEBUG)
740	printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
741	#endif
742	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
743	/* to same priviledge */
744	if (env->eflags & VM_MASK)
745	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
746	new_stack = 0;
747	sp_mask = get_sp_mask(env->segs[R_SS].flags);
748	ssp = env->segs[R_SS].base;
749	esp = ESP;
750	dpl = cpl;
751	} else {
752	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
753	new_stack = 0; /* avoid warning */
754	sp_mask = 0; /* avoid warning */
755	ssp = 0; /* avoid warning */
756	esp = 0; /* avoid warning */
757	}
758
759	shift = type >> 3;
760
761	#if 0
762	/* XXX: check that enough room is available */
763	push_size = 6 + (new_stack << 2) + (has_error_code << 1);
764	if (env->eflags & VM_MASK)
765	push_size += 8;
766	push_size <<= shift;
767	#endif
768	if (shift == 1) {
769	if (new_stack) {
770	if (env->eflags & VM_MASK) {
771	PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
772	PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
773	PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
774	PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
775	}
776	PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
777	PUSHL(ssp, esp, sp_mask, ESP);
778	}
779	PUSHL(ssp, esp, sp_mask, compute_eflags());
780	PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
781	PUSHL(ssp, esp, sp_mask, old_eip);
782	if (has_error_code) {
783	PUSHL(ssp, esp, sp_mask, error_code);
784	}
785	} else {
786	if (new_stack) {
787	if (env->eflags & VM_MASK) {
788	PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
789	PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
790	PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
791	PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
792	}
793	PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
794	PUSHW(ssp, esp, sp_mask, ESP);
795	}
796	PUSHW(ssp, esp, sp_mask, compute_eflags());
797	PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
798	PUSHW(ssp, esp, sp_mask, old_eip);
799	if (has_error_code) {
800	PUSHW(ssp, esp, sp_mask, error_code);
801	}
802	}
803
804	if (new_stack) {
805	if (env->eflags & VM_MASK) {
806	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
807	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
808	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
809	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
810	}
811	ss = (ss & ~3) \| dpl;
812	cpu_x86_load_seg_cache(env, R_SS, ss,
813	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
814	}
815	SET_ESP(esp, sp_mask);
816
817	selector = (selector & ~3) \| dpl;
818	cpu_x86_load_seg_cache(env, R_CS, selector,
819	get_seg_base(e1, e2),
820	get_seg_limit(e1, e2),
821	e2);
822	cpu_x86_set_cpl(env, dpl);
823	env->eip = offset;
824
825	/* interrupt gate clear IF mask */
826	if ((type & 1) == 0) {
827	env->eflags &= ~IF_MASK;
828	}
829	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
830	}
831
832	#ifdef VBOX
833
834	/* check if VME interrupt redirection is enabled in TSS */
835	static inline bool is_vme_irq_redirected(int intno)
836	{
837	int io_offset, intredir_offset;
838	unsigned char val, mask;
839
840	/* TSS must be a valid 32 bit one */
841	if (!(env->tr.flags & DESC_P_MASK) \|\|
842	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
843	env->tr.limit < 103)
844	goto fail;
845	io_offset = lduw_kernel(env->tr.base + 0x66);
846	/* the virtual interrupt redirection bitmap is located below the io bitmap */
847	intredir_offset = io_offset - 0x20;
848
849	intredir_offset += (intno >> 3);
850	if ((intredir_offset) > env->tr.limit)
851	goto fail;
852
853	val = ldub_kernel(env->tr.base + intredir_offset);
854	mask = 1 << (unsigned char)(intno & 7);
855
856	/* bit set means no redirection. */
857	if ((val & mask) != 0) {
858	return false;
859	}
860	return true;
861
862	fail:
863	raise_exception_err(EXCP0D_GPF, 0);
864	return true;
865	}
866
867	/* V86 mode software interrupt with CR4.VME=1 */
868	static void do_soft_interrupt_vme(int intno, int error_code, unsigned int next_eip)
869	{
870	target_ulong ptr, ssp;
871	int selector;
872	uint32_t offset, esp;
873	uint32_t old_cs, old_eflags;
874	uint32_t iopl;
875
876	iopl = ((env->eflags >> IOPL_SHIFT) & 3);
877
878	if (!is_vme_irq_redirected(intno))
879	{
880	if (iopl == 3)
881	/* normal protected mode handler call */
882	return do_interrupt_protected(intno, 1, error_code, next_eip, 0);
883	else
884	raise_exception_err(EXCP0D_GPF, 0);
885	}
886
887	/* virtual mode idt is at linear address 0 */
888	ptr = 0 + intno * 4;
889	offset = lduw_kernel(ptr);
890	selector = lduw_kernel(ptr + 2);
891	esp = ESP;
892	ssp = env->segs[R_SS].base;
893	old_cs = env->segs[R_CS].selector;
894
895	old_eflags = compute_eflags();
896	if (iopl < 3)
897	{
898	/* copy VIF into IF and set IOPL to 3 */
899	if (env->eflags & VIF_MASK)
900	old_eflags \|= IF_MASK;
901	else
902	old_eflags &= ~IF_MASK;
903
904	old_eflags \|= (3 << IOPL_SHIFT);
905	}
906
907	/* XXX: use SS segment size ? */
908	PUSHW(ssp, esp, 0xffff, old_eflags);
909	PUSHW(ssp, esp, 0xffff, old_cs);
910	PUSHW(ssp, esp, 0xffff, next_eip);
911
912	/* update processor state */
913	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
914	env->eip = offset;
915	env->segs[R_CS].selector = selector;
916	env->segs[R_CS].base = (selector << 4);
917	env->eflags &= ~(TF_MASK \| RF_MASK);
918
919	if (iopl < 3)
920	env->eflags &= ~VIF_MASK;
921	else
922	env->eflags &= ~IF_MASK;
923	}
924	#endif /* VBOX */
925
926	#ifdef TARGET_X86_64
927
928	#define PUSHQ(sp, val)\
929	{\
930	sp -= 8;\
931	stq_kernel(sp, (val));\
932	}
933
934	#define POPQ(sp, val)\
935	{\
936	val = ldq_kernel(sp);\
937	sp += 8;\
938	}
939
940	static inline target_ulong get_rsp_from_tss(int level)
941	{
942	int index;
943
944	#if 0
945	printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
946	env->tr.base, env->tr.limit);
947	#endif
948
949	if (!(env->tr.flags & DESC_P_MASK))
950	cpu_abort(env, "invalid tss");
951	index = 8 * level + 4;
952	if ((index + 7) > env->tr.limit)
953	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
954	return ldq_kernel(env->tr.base + index);
955	}
956
957	/* 64 bit interrupt */
958	static void do_interrupt64(int intno, int is_int, int error_code,
959	target_ulong next_eip, int is_hw)
960	{
961	SegmentCache *dt;
962	target_ulong ptr;
963	int type, dpl, selector, cpl, ist;
964	int has_error_code, new_stack;
965	uint32_t e1, e2, e3, ss;
966	target_ulong old_eip, esp, offset;
967
968	has_error_code = 0;
969	if (!is_int && !is_hw) {
970	switch(intno) {
971	case 8:
972	case 10:
973	case 11:
974	case 12:
975	case 13:
976	case 14:
977	case 17:
978	has_error_code = 1;
979	break;
980	}
981	}
982	if (is_int)
983	old_eip = next_eip;
984	else
985	old_eip = env->eip;
986
987	dt = &env->idt;
988	if (intno * 16 + 15 > dt->limit)
989	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
990	ptr = dt->base + intno * 16;
991	e1 = ldl_kernel(ptr);
992	e2 = ldl_kernel(ptr + 4);
993	e3 = ldl_kernel(ptr + 8);
994	/* check gate type */
995	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
996	switch(type) {
997	case 14: /* 386 interrupt gate */
998	case 15: /* 386 trap gate */
999	break;
1000	default:
1001	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1002	break;
1003	}
1004	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1005	cpl = env->hflags & HF_CPL_MASK;
1006	/* check privledge if software int */
1007	if (is_int && dpl < cpl)
1008	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1009	/* check valid bit */
1010	if (!(e2 & DESC_P_MASK))
1011	raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
1012	selector = e1 >> 16;
1013	offset = ((target_ulong)e3 << 32) \| (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
1014	ist = e2 & 7;
1015	if ((selector & 0xfffc) == 0)
1016	raise_exception_err(EXCP0D_GPF, 0);
1017
1018	if (load_segment(&e1, &e2, selector) != 0)
1019	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1020	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
1021	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1022	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1023	if (dpl > cpl)
1024	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1025	if (!(e2 & DESC_P_MASK))
1026	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1027	if (!(e2 & DESC_L_MASK) \|\| (e2 & DESC_B_MASK))
1028	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1029	if ((!(e2 & DESC_C_MASK) && dpl < cpl) \|\| ist != 0) {
1030	/* to inner priviledge */
1031	if (ist != 0)
1032	esp = get_rsp_from_tss(ist + 3);
1033	else
1034	esp = get_rsp_from_tss(dpl);
1035	esp &= ~0xfLL; /* align stack */
1036	ss = 0;
1037	new_stack = 1;
1038	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
1039	/* to same priviledge */
1040	if (env->eflags & VM_MASK)
1041	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1042	new_stack = 0;
1043	if (ist != 0)
1044	esp = get_rsp_from_tss(ist + 3);
1045	else
1046	esp = ESP;
1047	esp &= ~0xfLL; /* align stack */
1048	dpl = cpl;
1049	} else {
1050	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1051	new_stack = 0; /* avoid warning */
1052	esp = 0; /* avoid warning */
1053	}
1054
1055	PUSHQ(esp, env->segs[R_SS].selector);
1056	PUSHQ(esp, ESP);
1057	PUSHQ(esp, compute_eflags());
1058	PUSHQ(esp, env->segs[R_CS].selector);
1059	PUSHQ(esp, old_eip);
1060	if (has_error_code) {
1061	PUSHQ(esp, error_code);
1062	}
1063
1064	if (new_stack) {
1065	ss = 0 \| dpl;
1066	cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1067	}
1068	ESP = esp;
1069
1070	selector = (selector & ~3) \| dpl;
1071	cpu_x86_load_seg_cache(env, R_CS, selector,
1072	get_seg_base(e1, e2),
1073	get_seg_limit(e1, e2),
1074	e2);
1075	cpu_x86_set_cpl(env, dpl);
1076	env->eip = offset;
1077
1078	/* interrupt gate clear IF mask */
1079	if ((type & 1) == 0) {
1080	env->eflags &= ~IF_MASK;
1081	}
1082	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1083	}
1084	#endif
1085
1086	void helper_syscall(int next_eip_addend)
1087	{
1088	int selector;
1089
1090	if (!(env->efer & MSR_EFER_SCE)) {
1091	raise_exception_err(EXCP06_ILLOP, 0);
1092	}
1093	selector = (env->star >> 32) & 0xffff;
1094	#ifdef TARGET_X86_64
1095	if (env->hflags & HF_LMA_MASK) {
1096	int code64;
1097
1098	ECX = env->eip + next_eip_addend;
1099	env->regs[11] = compute_eflags();
1100
1101	code64 = env->hflags & HF_CS64_MASK;
1102
1103	cpu_x86_set_cpl(env, 0);
1104	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1105	0, 0xffffffff,
1106	DESC_G_MASK \| DESC_P_MASK \|
1107	DESC_S_MASK \|
1108	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \| DESC_L_MASK);
1109	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1110	0, 0xffffffff,
1111	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1112	DESC_S_MASK \|
1113	DESC_W_MASK \| DESC_A_MASK);
1114	env->eflags &= ~env->fmask;
1115	if (code64)
1116	env->eip = env->lstar;
1117	else
1118	env->eip = env->cstar;
1119	} else
1120	#endif
1121	{
1122	ECX = (uint32_t)(env->eip + next_eip_addend);
1123
1124	cpu_x86_set_cpl(env, 0);
1125	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1126	0, 0xffffffff,
1127	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1128	DESC_S_MASK \|
1129	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1130	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1131	0, 0xffffffff,
1132	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1133	DESC_S_MASK \|
1134	DESC_W_MASK \| DESC_A_MASK);
1135	env->eflags &= ~(IF_MASK \| RF_MASK \| VM_MASK);
1136	env->eip = (uint32_t)env->star;
1137	}
1138	}
1139
1140	void helper_sysret(int dflag)
1141	{
1142	int cpl, selector;
1143
1144	if (!(env->efer & MSR_EFER_SCE)) {
1145	raise_exception_err(EXCP06_ILLOP, 0);
1146	}
1147	cpl = env->hflags & HF_CPL_MASK;
1148	if (!(env->cr[0] & CR0_PE_MASK) \|\| cpl != 0) {
1149	raise_exception_err(EXCP0D_GPF, 0);
1150	}
1151	selector = (env->star >> 48) & 0xffff;
1152	#ifdef TARGET_X86_64
1153	if (env->hflags & HF_LMA_MASK) {
1154	if (dflag == 2) {
1155	cpu_x86_load_seg_cache(env, R_CS, (selector + 16) \| 3,
1156	0, 0xffffffff,
1157	DESC_G_MASK \| DESC_P_MASK \|
1158	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1159	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \|
1160	DESC_L_MASK);
1161	env->eip = ECX;
1162	} else {
1163	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1164	0, 0xffffffff,
1165	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1166	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1167	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1168	env->eip = (uint32_t)ECX;
1169	}
1170	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1171	0, 0xffffffff,
1172	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1173	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1174	DESC_W_MASK \| DESC_A_MASK);
1175	load_eflags((uint32_t)(env->regs[11]), TF_MASK \| AC_MASK \| ID_MASK \|
1176	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1177	cpu_x86_set_cpl(env, 3);
1178	} else
1179	#endif
1180	{
1181	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1182	0, 0xffffffff,
1183	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1184	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1185	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1186	env->eip = (uint32_t)ECX;
1187	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1188	0, 0xffffffff,
1189	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1190	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1191	DESC_W_MASK \| DESC_A_MASK);
1192	env->eflags \|= IF_MASK;
1193	cpu_x86_set_cpl(env, 3);
1194	}
1195	#ifdef USE_KQEMU
1196	if (kqemu_is_ok(env)) {
1197	if (env->hflags & HF_LMA_MASK)
1198	CC_OP = CC_OP_EFLAGS;
1199	env->exception_index = -1;
1200	cpu_loop_exit();
1201	}
1202	#endif
1203	}
1204
1205	#ifdef VBOX
1206	/**
1207	* Checks and processes external VMM events.
1208	* Called by op_check_external_event() when any of the flags is set and can be serviced.
1209	*/
1210	void helper_external_event(void)
1211	{
1212	#if defined(RT_OS_DARWIN) && defined(VBOX_STRICT)
1213	uintptr_t uESP;
1214	__asm__ __volatile__("movl %%esp, %0" : "=r" (uESP));
1215	AssertMsg(!(uESP & 15), ("esp=%#p\n", uESP));
1216	#endif
1217	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1218	{
1219	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1220	cpu_interrupt(env, CPU_INTERRUPT_HARD);
1221	}
1222	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1223	{
1224	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1225	cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1226	}
1227	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1228	{
1229	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1230	remR3DmaRun(env);
1231	}
1232	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1233	{
1234	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1235	remR3TimersRun(env);
1236	}
1237	}
1238	/* helper for recording call instruction addresses for later scanning */
1239	void helper_record_call()
1240	{
1241	if ( !(env->state & CPU_RAW_RING0)
1242	&& (env->cr[0] & CR0_PG_MASK)
1243	&& !(env->eflags & X86_EFL_IF))
1244	remR3RecordCall(env);
1245	}
1246	#endif /* VBOX */
1247
1248	/* real mode interrupt */
1249	static void do_interrupt_real(int intno, int is_int, int error_code,
1250	unsigned int next_eip)
1251	{
1252	SegmentCache *dt;
1253	target_ulong ptr, ssp;
1254	int selector;
1255	uint32_t offset, esp;
1256	uint32_t old_cs, old_eip;
1257
1258	/* real mode (simpler !) */
1259	dt = &env->idt;
1260	if (intno * 4 + 3 > dt->limit)
1261	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1262	ptr = dt->base + intno * 4;
1263	offset = lduw_kernel(ptr);
1264	selector = lduw_kernel(ptr + 2);
1265	esp = ESP;
1266	ssp = env->segs[R_SS].base;
1267	if (is_int)
1268	old_eip = next_eip;
1269	else
1270	old_eip = env->eip;
1271	old_cs = env->segs[R_CS].selector;
1272	/* XXX: use SS segment size ? */
1273	PUSHW(ssp, esp, 0xffff, compute_eflags());
1274	PUSHW(ssp, esp, 0xffff, old_cs);
1275	PUSHW(ssp, esp, 0xffff, old_eip);
1276
1277	/* update processor state */
1278	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
1279	env->eip = offset;
1280	env->segs[R_CS].selector = selector;
1281	env->segs[R_CS].base = (selector << 4);
1282	env->eflags &= ~(IF_MASK \| TF_MASK \| AC_MASK \| RF_MASK);
1283	}
1284
1285	/* fake user mode interrupt */
1286	void do_interrupt_user(int intno, int is_int, int error_code,
1287	target_ulong next_eip)
1288	{
1289	SegmentCache *dt;
1290	target_ulong ptr;
1291	int dpl, cpl;
1292	uint32_t e2;
1293
1294	dt = &env->idt;
1295	ptr = dt->base + (intno * 8);
1296	e2 = ldl_kernel(ptr + 4);
1297
1298	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1299	cpl = env->hflags & HF_CPL_MASK;
1300	/* check privledge if software int */
1301	if (is_int && dpl < cpl)
1302	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1303
1304	/* Since we emulate only user space, we cannot do more than
1305	exiting the emulation with the suitable exception and error
1306	code */
1307	if (is_int)
1308	EIP = next_eip;
1309	}
1310
1311	/*
1312	* Begin execution of an interruption. is_int is TRUE if coming from
1313	* the int instruction. next_eip is the EIP value AFTER the interrupt
1314	* instruction. It is only relevant if is_int is TRUE.
1315	*/
1316	void do_interrupt(int intno, int is_int, int error_code,
1317	target_ulong next_eip, int is_hw)
1318	{
1319	if (loglevel & CPU_LOG_INT) {
1320	if ((env->cr[0] & CR0_PE_MASK)) {
1321	static int count;
1322	fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1323	count, intno, error_code, is_int,
1324	env->hflags & HF_CPL_MASK,
1325	env->segs[R_CS].selector, EIP,
1326	(int)env->segs[R_CS].base + EIP,
1327	env->segs[R_SS].selector, ESP);
1328	if (intno == 0x0e) {
1329	fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1330	} else {
1331	fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1332	}
1333	fprintf(logfile, "\n");
1334	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1335	#if 0
1336	{
1337	int i;
1338	uint8_t *ptr;
1339	fprintf(logfile, " code=");
1340	ptr = env->segs[R_CS].base + env->eip;
1341	for(i = 0; i < 16; i++) {
1342	fprintf(logfile, " %02x", ldub(ptr + i));
1343	}
1344	fprintf(logfile, "\n");
1345	}
1346	#endif
1347	count++;
1348	}
1349	}
1350	if (env->cr[0] & CR0_PE_MASK) {
1351	#ifdef TARGET_X86_64
1352	if (env->hflags & HF_LMA_MASK) {
1353	do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1354	} else
1355	#endif
1356	{
1357	#ifdef VBOX
1358	/* int xx , v86 code and VME enabled? /
1359	if ( (env->eflags & VM_MASK)
1360	&& (env->cr[4] & CR4_VME_MASK)
1361	&& is_int
1362	&& !is_hw
1363	&& env->eip + 1 != next_eip /* single byte int 3 goes straight to the protected mode handler */
1364	)
1365	do_soft_interrupt_vme(intno, error_code, next_eip);
1366	else
1367	#endif /* VBOX */
1368	do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1369	}
1370	} else {
1371	do_interrupt_real(intno, is_int, error_code, next_eip);
1372	}
1373	}
1374
1375	/*
1376	* Signal an interruption. It is executed in the main CPU loop.
1377	* is_int is TRUE if coming from the int instruction. next_eip is the
1378	* EIP value AFTER the interrupt instruction. It is only relevant if
1379	* is_int is TRUE.
1380	*/
1381	void raise_interrupt(int intno, int is_int, int error_code,
1382	int next_eip_addend)
1383	{
1384	#if defined(VBOX) && defined(DEBUG)
1385	NOT_DMIK(Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend)));
1386	#endif
1387	env->exception_index = intno;
1388	env->error_code = error_code;
1389	env->exception_is_int = is_int;
1390	env->exception_next_eip = env->eip + next_eip_addend;
1391	cpu_loop_exit();
1392	}
1393
1394	/* same as raise_exception_err, but do not restore global registers */
1395	static void raise_exception_err_norestore(int exception_index, int error_code)
1396	{
1397	env->exception_index = exception_index;
1398	env->error_code = error_code;
1399	env->exception_is_int = 0;
1400	env->exception_next_eip = 0;
1401	longjmp(env->jmp_env, 1);
1402	}
1403
1404	/* shortcuts to generate exceptions */
1405
1406	void (raise_exception_err)(int exception_index, int error_code)
1407	{
1408	raise_interrupt(exception_index, 0, error_code, 0);
1409	}
1410
1411	void raise_exception(int exception_index)
1412	{
1413	raise_interrupt(exception_index, 0, 0, 0);
1414	}
1415
1416	/* SMM support */
1417
1418	#if defined(CONFIG_USER_ONLY)
1419
1420	void do_smm_enter(void)
1421	{
1422	}
1423
1424	void helper_rsm(void)
1425	{
1426	}
1427
1428	#else
1429
1430	#ifdef TARGET_X86_64
1431	#define SMM_REVISION_ID 0x00020064
1432	#else
1433	#define SMM_REVISION_ID 0x00020000
1434	#endif
1435
1436	void do_smm_enter(void)
1437	{
1438	#ifdef VBOX
1439	cpu_abort(env, "do_ssm_enter");
1440	#else /* !VBOX */
1441	target_ulong sm_state;
1442	SegmentCache *dt;
1443	int i, offset;
1444
1445	if (loglevel & CPU_LOG_INT) {
1446	fprintf(logfile, "SMM: enter\n");
1447	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1448	}
1449
1450	env->hflags \|= HF_SMM_MASK;
1451	cpu_smm_update(env);
1452
1453	sm_state = env->smbase + 0x8000;
1454
1455	#ifdef TARGET_X86_64
1456	for(i = 0; i < 6; i++) {
1457	dt = &env->segs[i];
1458	offset = 0x7e00 + i * 16;
1459	stw_phys(sm_state + offset, dt->selector);
1460	stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1461	stl_phys(sm_state + offset + 4, dt->limit);
1462	stq_phys(sm_state + offset + 8, dt->base);
1463	}
1464
1465	stq_phys(sm_state + 0x7e68, env->gdt.base);
1466	stl_phys(sm_state + 0x7e64, env->gdt.limit);
1467
1468	stw_phys(sm_state + 0x7e70, env->ldt.selector);
1469	stq_phys(sm_state + 0x7e78, env->ldt.base);
1470	stl_phys(sm_state + 0x7e74, env->ldt.limit);
1471	stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1472
1473	stq_phys(sm_state + 0x7e88, env->idt.base);
1474	stl_phys(sm_state + 0x7e84, env->idt.limit);
1475
1476	stw_phys(sm_state + 0x7e90, env->tr.selector);
1477	stq_phys(sm_state + 0x7e98, env->tr.base);
1478	stl_phys(sm_state + 0x7e94, env->tr.limit);
1479	stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1480
1481	stq_phys(sm_state + 0x7ed0, env->efer);
1482
1483	stq_phys(sm_state + 0x7ff8, EAX);
1484	stq_phys(sm_state + 0x7ff0, ECX);
1485	stq_phys(sm_state + 0x7fe8, EDX);
1486	stq_phys(sm_state + 0x7fe0, EBX);
1487	stq_phys(sm_state + 0x7fd8, ESP);
1488	stq_phys(sm_state + 0x7fd0, EBP);
1489	stq_phys(sm_state + 0x7fc8, ESI);
1490	stq_phys(sm_state + 0x7fc0, EDI);
1491	for(i = 8; i < 16; i++)
1492	stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1493	stq_phys(sm_state + 0x7f78, env->eip);
1494	stl_phys(sm_state + 0x7f70, compute_eflags());
1495	stl_phys(sm_state + 0x7f68, env->dr[6]);
1496	stl_phys(sm_state + 0x7f60, env->dr[7]);
1497
1498	stl_phys(sm_state + 0x7f48, env->cr[4]);
1499	stl_phys(sm_state + 0x7f50, env->cr[3]);
1500	stl_phys(sm_state + 0x7f58, env->cr[0]);
1501
1502	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1503	stl_phys(sm_state + 0x7f00, env->smbase);
1504	#else
1505	stl_phys(sm_state + 0x7ffc, env->cr[0]);
1506	stl_phys(sm_state + 0x7ff8, env->cr[3]);
1507	stl_phys(sm_state + 0x7ff4, compute_eflags());
1508	stl_phys(sm_state + 0x7ff0, env->eip);
1509	stl_phys(sm_state + 0x7fec, EDI);
1510	stl_phys(sm_state + 0x7fe8, ESI);
1511	stl_phys(sm_state + 0x7fe4, EBP);
1512	stl_phys(sm_state + 0x7fe0, ESP);
1513	stl_phys(sm_state + 0x7fdc, EBX);
1514	stl_phys(sm_state + 0x7fd8, EDX);
1515	stl_phys(sm_state + 0x7fd4, ECX);
1516	stl_phys(sm_state + 0x7fd0, EAX);
1517	stl_phys(sm_state + 0x7fcc, env->dr[6]);
1518	stl_phys(sm_state + 0x7fc8, env->dr[7]);
1519
1520	stl_phys(sm_state + 0x7fc4, env->tr.selector);
1521	stl_phys(sm_state + 0x7f64, env->tr.base);
1522	stl_phys(sm_state + 0x7f60, env->tr.limit);
1523	stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1524
1525	stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1526	stl_phys(sm_state + 0x7f80, env->ldt.base);
1527	stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1528	stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1529
1530	stl_phys(sm_state + 0x7f74, env->gdt.base);
1531	stl_phys(sm_state + 0x7f70, env->gdt.limit);
1532
1533	stl_phys(sm_state + 0x7f58, env->idt.base);
1534	stl_phys(sm_state + 0x7f54, env->idt.limit);
1535
1536	for(i = 0; i < 6; i++) {
1537	dt = &env->segs[i];
1538	if (i < 3)
1539	offset = 0x7f84 + i * 12;
1540	else
1541	offset = 0x7f2c + (i - 3) * 12;
1542	stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1543	stl_phys(sm_state + offset + 8, dt->base);
1544	stl_phys(sm_state + offset + 4, dt->limit);
1545	stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1546	}
1547	stl_phys(sm_state + 0x7f14, env->cr[4]);
1548
1549	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1550	stl_phys(sm_state + 0x7ef8, env->smbase);
1551	#endif
1552	/* init SMM cpu state */
1553
1554	#ifdef TARGET_X86_64
1555	env->efer = 0;
1556	env->hflags &= ~HF_LMA_MASK;
1557	#endif
1558	load_eflags(0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1559	env->eip = 0x00008000;
1560	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1561	0xffffffff, 0);
1562	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1563	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1564	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1565	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1566	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1567
1568	cpu_x86_update_cr0(env,
1569	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \| CR0_PG_MASK));
1570	cpu_x86_update_cr4(env, 0);
1571	env->dr[7] = 0x00000400;
1572	CC_OP = CC_OP_EFLAGS;
1573	#endif /* VBOX */
1574	}
1575
1576	void helper_rsm(void)
1577	{
1578	#ifdef VBOX
1579	cpu_abort(env, "helper_rsm");
1580	#else /* !VBOX */
1581	target_ulong sm_state;
1582	int i, offset;
1583	uint32_t val;
1584
1585	sm_state = env->smbase + 0x8000;
1586	#ifdef TARGET_X86_64
1587	env->efer = ldq_phys(sm_state + 0x7ed0);
1588	if (env->efer & MSR_EFER_LMA)
1589	env->hflags \|= HF_LMA_MASK;
1590	else
1591	env->hflags &= ~HF_LMA_MASK;
1592
1593	for(i = 0; i < 6; i++) {
1594	offset = 0x7e00 + i * 16;
1595	cpu_x86_load_seg_cache(env, i,
1596	lduw_phys(sm_state + offset),
1597	ldq_phys(sm_state + offset + 8),
1598	ldl_phys(sm_state + offset + 4),
1599	(lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1600	}
1601
1602	env->gdt.base = ldq_phys(sm_state + 0x7e68);
1603	env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1604
1605	env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1606	env->ldt.base = ldq_phys(sm_state + 0x7e78);
1607	env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1608	env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1609
1610	env->idt.base = ldq_phys(sm_state + 0x7e88);
1611	env->idt.limit = ldl_phys(sm_state + 0x7e84);
1612
1613	env->tr.selector = lduw_phys(sm_state + 0x7e90);
1614	env->tr.base = ldq_phys(sm_state + 0x7e98);
1615	env->tr.limit = ldl_phys(sm_state + 0x7e94);
1616	env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1617
1618	EAX = ldq_phys(sm_state + 0x7ff8);
1619	ECX = ldq_phys(sm_state + 0x7ff0);
1620	EDX = ldq_phys(sm_state + 0x7fe8);
1621	EBX = ldq_phys(sm_state + 0x7fe0);
1622	ESP = ldq_phys(sm_state + 0x7fd8);
1623	EBP = ldq_phys(sm_state + 0x7fd0);
1624	ESI = ldq_phys(sm_state + 0x7fc8);
1625	EDI = ldq_phys(sm_state + 0x7fc0);
1626	for(i = 8; i < 16; i++)
1627	env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1628	env->eip = ldq_phys(sm_state + 0x7f78);
1629	load_eflags(ldl_phys(sm_state + 0x7f70),
1630	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1631	env->dr[6] = ldl_phys(sm_state + 0x7f68);
1632	env->dr[7] = ldl_phys(sm_state + 0x7f60);
1633
1634	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1635	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1636	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1637
1638	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1639	if (val & 0x20000) {
1640	env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1641	}
1642	#else
1643	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1644	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1645	load_eflags(ldl_phys(sm_state + 0x7ff4),
1646	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1647	env->eip = ldl_phys(sm_state + 0x7ff0);
1648	EDI = ldl_phys(sm_state + 0x7fec);
1649	ESI = ldl_phys(sm_state + 0x7fe8);
1650	EBP = ldl_phys(sm_state + 0x7fe4);
1651	ESP = ldl_phys(sm_state + 0x7fe0);
1652	EBX = ldl_phys(sm_state + 0x7fdc);
1653	EDX = ldl_phys(sm_state + 0x7fd8);
1654	ECX = ldl_phys(sm_state + 0x7fd4);
1655	EAX = ldl_phys(sm_state + 0x7fd0);
1656	env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1657	env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1658
1659	env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1660	env->tr.base = ldl_phys(sm_state + 0x7f64);
1661	env->tr.limit = ldl_phys(sm_state + 0x7f60);
1662	env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1663
1664	env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1665	env->ldt.base = ldl_phys(sm_state + 0x7f80);
1666	env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1667	env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1668
1669	env->gdt.base = ldl_phys(sm_state + 0x7f74);
1670	env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1671
1672	env->idt.base = ldl_phys(sm_state + 0x7f58);
1673	env->idt.limit = ldl_phys(sm_state + 0x7f54);
1674
1675	for(i = 0; i < 6; i++) {
1676	if (i < 3)
1677	offset = 0x7f84 + i * 12;
1678	else
1679	offset = 0x7f2c + (i - 3) * 12;
1680	cpu_x86_load_seg_cache(env, i,
1681	ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1682	ldl_phys(sm_state + offset + 8),
1683	ldl_phys(sm_state + offset + 4),
1684	(ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1685	}
1686	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1687
1688	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1689	if (val & 0x20000) {
1690	env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1691	}
1692	#endif
1693	CC_OP = CC_OP_EFLAGS;
1694	env->hflags &= ~HF_SMM_MASK;
1695	cpu_smm_update(env);
1696
1697	if (loglevel & CPU_LOG_INT) {
1698	fprintf(logfile, "SMM: after RSM\n");
1699	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1700	}
1701	#endif /* !VBOX */
1702	}
1703
1704	#endif /* !CONFIG_USER_ONLY */
1705
1706
1707	#ifdef BUGGY_GCC_DIV64
1708	/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1709	call it from another function */
1710	uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1711	{
1712	*q_ptr = num / den;
1713	return num % den;
1714	}
1715
1716	int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1717	{
1718	*q_ptr = num / den;
1719	return num % den;
1720	}
1721	#endif
1722
1723	void helper_divl_EAX_T0(void)
1724	{
1725	unsigned int den, r;
1726	uint64_t num, q;
1727
1728	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1729	den = T0;
1730	if (den == 0) {
1731	raise_exception(EXCP00_DIVZ);
1732	}
1733	#ifdef BUGGY_GCC_DIV64
1734	r = div32(&q, num, den);
1735	#else
1736	q = (num / den);
1737	r = (num % den);
1738	#endif
1739	if (q > 0xffffffff)
1740	raise_exception(EXCP00_DIVZ);
1741	EAX = (uint32_t)q;
1742	EDX = (uint32_t)r;
1743	}
1744
1745	void helper_idivl_EAX_T0(void)
1746	{
1747	int den, r;
1748	int64_t num, q;
1749
1750	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1751	den = T0;
1752	if (den == 0) {
1753	raise_exception(EXCP00_DIVZ);
1754	}
1755	#ifdef BUGGY_GCC_DIV64
1756	r = idiv32(&q, num, den);
1757	#else
1758	q = (num / den);
1759	r = (num % den);
1760	#endif
1761	if (q != (int32_t)q)
1762	raise_exception(EXCP00_DIVZ);
1763	EAX = (uint32_t)q;
1764	EDX = (uint32_t)r;
1765	}
1766
1767	void helper_cmpxchg8b(void)
1768	{
1769	uint64_t d;
1770	int eflags;
1771
1772	eflags = cc_table[CC_OP].compute_all();
1773	d = ldq(A0);
1774	if (d == (((uint64_t)EDX << 32) \| EAX)) {
1775	stq(A0, ((uint64_t)ECX << 32) \| EBX);
1776	eflags \|= CC_Z;
1777	} else {
1778	/* always do the store */
1779	stq(A0, d);
1780	EDX = (uint32_t)(d >> 32);
1781	EAX = (uint32_t)d;
1782	eflags &= ~CC_Z;
1783	}
1784	CC_SRC = eflags;
1785	}
1786
1787	void helper_single_step()
1788	{
1789	env->dr[6] \|= 0x4000;
1790	raise_exception(EXCP01_SSTP);
1791	}
1792
1793	void helper_cpuid(void)
1794	{
1795	#ifndef VBOX
1796	uint32_t index;
1797	index = (uint32_t)EAX;
1798
1799	/* test if maximum index reached */
1800	if (index & 0x80000000) {
1801	if (index > env->cpuid_xlevel)
1802	index = env->cpuid_level;
1803	} else {
1804	if (index > env->cpuid_level)
1805	index = env->cpuid_level;
1806	}
1807
1808	switch(index) {
1809	case 0:
1810	EAX = env->cpuid_level;
1811	EBX = env->cpuid_vendor1;
1812	EDX = env->cpuid_vendor2;
1813	ECX = env->cpuid_vendor3;
1814	break;
1815	case 1:
1816	EAX = env->cpuid_version;
1817	EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1818	ECX = env->cpuid_ext_features;
1819	EDX = env->cpuid_features;
1820	break;
1821	case 2:
1822	/* cache info: needed for Pentium Pro compatibility */
1823	EAX = 0x410601;
1824	EBX = 0;
1825	ECX = 0;
1826	EDX = 0;
1827	break;
1828	case 0x80000000:
1829	EAX = env->cpuid_xlevel;
1830	EBX = env->cpuid_vendor1;
1831	EDX = env->cpuid_vendor2;
1832	ECX = env->cpuid_vendor3;
1833	break;
1834	case 0x80000001:
1835	EAX = env->cpuid_features;
1836	EBX = 0;
1837	ECX = 0;
1838	EDX = env->cpuid_ext2_features;
1839	break;
1840	case 0x80000002:
1841	case 0x80000003:
1842	case 0x80000004:
1843	EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1844	EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1845	ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1846	EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1847	break;
1848	case 0x80000005:
1849	/* cache info (L1 cache) */
1850	EAX = 0x01ff01ff;
1851	EBX = 0x01ff01ff;
1852	ECX = 0x40020140;
1853	EDX = 0x40020140;
1854	break;
1855	case 0x80000006:
1856	/* cache info (L2 cache) */
1857	EAX = 0;
1858	EBX = 0x42004200;
1859	ECX = 0x02008140;
1860	EDX = 0;
1861	break;
1862	case 0x80000008:
1863	/* virtual & phys address size in low 2 bytes. */
1864	EAX = 0x00003028;
1865	EBX = 0;
1866	ECX = 0;
1867	EDX = 0;
1868	break;
1869	default:
1870	/* reserved values: zero */
1871	EAX = 0;
1872	EBX = 0;
1873	ECX = 0;
1874	EDX = 0;
1875	break;
1876	}
1877	#else /* VBOX */
1878	remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1879	#endif /* VBOX */
1880	}
1881
1882	void helper_enter_level(int level, int data32)
1883	{
1884	target_ulong ssp;
1885	uint32_t esp_mask, esp, ebp;
1886
1887	esp_mask = get_sp_mask(env->segs[R_SS].flags);
1888	ssp = env->segs[R_SS].base;
1889	ebp = EBP;
1890	esp = ESP;
1891	if (data32) {
1892	/* 32 bit */
1893	esp -= 4;
1894	while (--level) {
1895	esp -= 4;
1896	ebp -= 4;
1897	stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1898	}
1899	esp -= 4;
1900	stl(ssp + (esp & esp_mask), T1);
1901	} else {
1902	/* 16 bit */
1903	esp -= 2;
1904	while (--level) {
1905	esp -= 2;
1906	ebp -= 2;
1907	stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1908	}
1909	esp -= 2;
1910	stw(ssp + (esp & esp_mask), T1);
1911	}
1912	}
1913
1914	#ifdef TARGET_X86_64
1915	void helper_enter64_level(int level, int data64)
1916	{
1917	target_ulong esp, ebp;
1918	ebp = EBP;
1919	esp = ESP;
1920
1921	if (data64) {
1922	/* 64 bit */
1923	esp -= 8;
1924	while (--level) {
1925	esp -= 8;
1926	ebp -= 8;
1927	stq(esp, ldq(ebp));
1928	}
1929	esp -= 8;
1930	stq(esp, T1);
1931	} else {
1932	/* 16 bit */
1933	esp -= 2;
1934	while (--level) {
1935	esp -= 2;
1936	ebp -= 2;
1937	stw(esp, lduw(ebp));
1938	}
1939	esp -= 2;
1940	stw(esp, T1);
1941	}
1942	}
1943	#endif
1944
1945	void helper_lldt_T0(void)
1946	{
1947	int selector;
1948	SegmentCache *dt;
1949	uint32_t e1, e2;
1950	int index, entry_limit;
1951	target_ulong ptr;
1952	#ifdef VBOX
1953	Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1954	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1955	#endif
1956
1957	selector = T0 & 0xffff;
1958	if ((selector & 0xfffc) == 0) {
1959	/* XXX: NULL selector case: invalid LDT */
1960	env->ldt.base = 0;
1961	env->ldt.limit = 0;
1962	} else {
1963	if (selector & 0x4)
1964	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1965	dt = &env->gdt;
1966	index = selector & ~7;
1967	#ifdef TARGET_X86_64
1968	if (env->hflags & HF_LMA_MASK)
1969	entry_limit = 15;
1970	else
1971	#endif
1972	entry_limit = 7;
1973	if ((index + entry_limit) > dt->limit)
1974	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1975	ptr = dt->base + index;
1976	e1 = ldl_kernel(ptr);
1977	e2 = ldl_kernel(ptr + 4);
1978	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1979	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1980	if (!(e2 & DESC_P_MASK))
1981	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1982	#ifdef TARGET_X86_64
1983	if (env->hflags & HF_LMA_MASK) {
1984	uint32_t e3;
1985	e3 = ldl_kernel(ptr + 8);
1986	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1987	env->ldt.base \|= (target_ulong)e3 << 32;
1988	} else
1989	#endif
1990	{
1991	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1992	}
1993	}
1994	env->ldt.selector = selector;
1995	#ifdef VBOX
1996	Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
1997	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
1998	#endif
1999	}
2000
2001	void helper_ltr_T0(void)
2002	{
2003	int selector;
2004	SegmentCache *dt;
2005	uint32_t e1, e2;
2006	int index, type, entry_limit;
2007	target_ulong ptr;
2008
2009	#ifdef VBOX
2010	Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2011	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2012	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2013	#endif
2014
2015	selector = T0 & 0xffff;
2016	if ((selector & 0xfffc) == 0) {
2017	/* NULL selector case: invalid TR */
2018	env->tr.base = 0;
2019	env->tr.limit = 0;
2020	env->tr.flags = 0;
2021	} else {
2022	if (selector & 0x4)
2023	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2024	dt = &env->gdt;
2025	index = selector & ~7;
2026	#ifdef TARGET_X86_64
2027	if (env->hflags & HF_LMA_MASK)
2028	entry_limit = 15;
2029	else
2030	#endif
2031	entry_limit = 7;
2032	if ((index + entry_limit) > dt->limit)
2033	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2034	ptr = dt->base + index;
2035	e1 = ldl_kernel(ptr);
2036	e2 = ldl_kernel(ptr + 4);
2037	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2038	if ((e2 & DESC_S_MASK) \|\|
2039	(type != 1 && type != 9))
2040	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2041	if (!(e2 & DESC_P_MASK))
2042	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2043	#ifdef TARGET_X86_64
2044	if (env->hflags & HF_LMA_MASK) {
2045	uint32_t e3;
2046	e3 = ldl_kernel(ptr + 8);
2047	load_seg_cache_raw_dt(&env->tr, e1, e2);
2048	env->tr.base \|= (target_ulong)e3 << 32;
2049	} else
2050	#endif
2051	{
2052	load_seg_cache_raw_dt(&env->tr, e1, e2);
2053	}
2054	e2 \|= DESC_TSS_BUSY_MASK;
2055	stl_kernel(ptr + 4, e2);
2056	}
2057	env->tr.selector = selector;
2058	#ifdef VBOX
2059	Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2060	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2061	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2062	#endif
2063	}
2064
2065	/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2066	void load_seg(int seg_reg, int selector)
2067	{
2068	uint32_t e1, e2;
2069	int cpl, dpl, rpl;
2070	SegmentCache *dt;
2071	int index;
2072	target_ulong ptr;
2073
2074	selector &= 0xffff;
2075	cpl = env->hflags & HF_CPL_MASK;
2076
2077	#ifdef VBOX
2078	/* Trying to load a selector with CPL=1? */
2079	if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0))
2080	{
2081	Log(("RPL 1 -> sel %04X -> %04X\n", selector, selector & 0xfffc));
2082	selector = selector & 0xfffc;
2083	}
2084	#endif
2085
2086	if ((selector & 0xfffc) == 0) {
2087	/* null selector case */
2088	if (seg_reg == R_SS
2089	#ifdef TARGET_X86_64
2090	&& (!(env->hflags & HF_CS64_MASK) \|\| cpl == 3)
2091	#endif
2092	)
2093	raise_exception_err(EXCP0D_GPF, 0);
2094	cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2095	} else {
2096
2097	if (selector & 0x4)
2098	dt = &env->ldt;
2099	else
2100	dt = &env->gdt;
2101	index = selector & ~7;
2102	if ((index + 7) > dt->limit)
2103	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2104	ptr = dt->base + index;
2105	e1 = ldl_kernel(ptr);
2106	e2 = ldl_kernel(ptr + 4);
2107
2108	if (!(e2 & DESC_S_MASK))
2109	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2110	rpl = selector & 3;
2111	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2112	if (seg_reg == R_SS) {
2113	/* must be writable segment */
2114	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
2115	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2116	if (rpl != cpl \|\| dpl != cpl)
2117	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2118	} else {
2119	/* must be readable segment */
2120	if ((e2 & (DESC_CS_MASK \| DESC_R_MASK)) == DESC_CS_MASK)
2121	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2122
2123	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2124	/* if not conforming code, test rights */
2125	if (dpl < cpl \|\| dpl < rpl)
2126	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2127	}
2128	}
2129
2130	if (!(e2 & DESC_P_MASK)) {
2131	if (seg_reg == R_SS)
2132	raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
2133	else
2134	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2135	}
2136
2137	/* set the access bit if not already set */
2138	if (!(e2 & DESC_A_MASK)) {
2139	e2 \|= DESC_A_MASK;
2140	stl_kernel(ptr + 4, e2);
2141	}
2142
2143	cpu_x86_load_seg_cache(env, seg_reg, selector,
2144	get_seg_base(e1, e2),
2145	get_seg_limit(e1, e2),
2146	e2);
2147	#if 0
2148	fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
2149	selector, (unsigned long)sc->base, sc->limit, sc->flags);
2150	#endif
2151	}
2152	}
2153
2154	/* protected mode jump */
2155	void helper_ljmp_protected_T0_T1(int next_eip_addend)
2156	{
2157	int new_cs, gate_cs, type;
2158	uint32_t e1, e2, cpl, dpl, rpl, limit;
2159	target_ulong new_eip, next_eip;
2160
2161	new_cs = T0;
2162	new_eip = T1;
2163	if ((new_cs & 0xfffc) == 0)
2164	raise_exception_err(EXCP0D_GPF, 0);
2165	if (load_segment(&e1, &e2, new_cs) != 0)
2166	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2167	cpl = env->hflags & HF_CPL_MASK;
2168	if (e2 & DESC_S_MASK) {
2169	if (!(e2 & DESC_CS_MASK))
2170	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2171	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2172	if (e2 & DESC_C_MASK) {
2173	/* conforming code segment */
2174	if (dpl > cpl)
2175	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2176	} else {
2177	/* non conforming code segment */
2178	rpl = new_cs & 3;
2179	if (rpl > cpl)
2180	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2181	if (dpl != cpl)
2182	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2183	}
2184	if (!(e2 & DESC_P_MASK))
2185	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2186	limit = get_seg_limit(e1, e2);
2187	if (new_eip > limit &&
2188	!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2189	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2190	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2191	get_seg_base(e1, e2), limit, e2);
2192	EIP = new_eip;
2193	} else {
2194	/* jump to call or task gate */
2195	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2196	rpl = new_cs & 3;
2197	cpl = env->hflags & HF_CPL_MASK;
2198	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2199	switch(type) {
2200	case 1: /* 286 TSS */
2201	case 9: /* 386 TSS */
2202	case 5: /* task gate */
2203	if (dpl < cpl \|\| dpl < rpl)
2204	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2205	next_eip = env->eip + next_eip_addend;
2206	switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2207	CC_OP = CC_OP_EFLAGS;
2208	break;
2209	case 4: /* 286 call gate */
2210	case 12: /* 386 call gate */
2211	if ((dpl < cpl) \|\| (dpl < rpl))
2212	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2213	if (!(e2 & DESC_P_MASK))
2214	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2215	gate_cs = e1 >> 16;
2216	new_eip = (e1 & 0xffff);
2217	if (type == 12)
2218	new_eip \|= (e2 & 0xffff0000);
2219	if (load_segment(&e1, &e2, gate_cs) != 0)
2220	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2221	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2222	/* must be code segment */
2223	if (((e2 & (DESC_S_MASK \| DESC_CS_MASK)) !=
2224	(DESC_S_MASK \| DESC_CS_MASK)))
2225	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2226	if (((e2 & DESC_C_MASK) && (dpl > cpl)) \|\|
2227	(!(e2 & DESC_C_MASK) && (dpl != cpl)))
2228	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2229	if (!(e2 & DESC_P_MASK))
2230	#ifdef VBOX /* See page 3-514 of 253666.pdf */
2231	raise_exception_err(EXCP0B_NOSEG, gate_cs & 0xfffc);
2232	#else
2233	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2234	#endif
2235	limit = get_seg_limit(e1, e2);
2236	if (new_eip > limit)
2237	raise_exception_err(EXCP0D_GPF, 0);
2238	cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) \| cpl,
2239	get_seg_base(e1, e2), limit, e2);
2240	EIP = new_eip;
2241	break;
2242	default:
2243	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2244	break;
2245	}
2246	}
2247	}
2248
2249	/* real mode call */
2250	void helper_lcall_real_T0_T1(int shift, int next_eip)
2251	{
2252	int new_cs, new_eip;
2253	uint32_t esp, esp_mask;
2254	target_ulong ssp;
2255
2256	new_cs = T0;
2257	new_eip = T1;
2258	esp = ESP;
2259	esp_mask = get_sp_mask(env->segs[R_SS].flags);
2260	ssp = env->segs[R_SS].base;
2261	if (shift) {
2262	PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2263	PUSHL(ssp, esp, esp_mask, next_eip);
2264	} else {
2265	PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2266	PUSHW(ssp, esp, esp_mask, next_eip);
2267	}
2268
2269	SET_ESP(esp, esp_mask);
2270	env->eip = new_eip;
2271	env->segs[R_CS].selector = new_cs;
2272	env->segs[R_CS].base = (new_cs << 4);
2273	}
2274
2275	/* protected mode call */
2276	void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2277	{
2278	int new_cs, new_stack, i;
2279	uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2280	uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2281	uint32_t val, limit, old_sp_mask;
2282	target_ulong ssp, old_ssp, next_eip, new_eip;
2283
2284	new_cs = T0;
2285	new_eip = T1;
2286	next_eip = env->eip + next_eip_addend;
2287	#ifdef DEBUG_PCALL
2288	if (loglevel & CPU_LOG_PCALL) {
2289	fprintf(logfile, "lcall %04x:%08x s=%d\n",
2290	new_cs, (uint32_t)new_eip, shift);
2291	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2292	}
2293	#endif
2294	if ((new_cs & 0xfffc) == 0)
2295	raise_exception_err(EXCP0D_GPF, 0);
2296	if (load_segment(&e1, &e2, new_cs) != 0)
2297	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2298	cpl = env->hflags & HF_CPL_MASK;
2299	#ifdef DEBUG_PCALL
2300	if (loglevel & CPU_LOG_PCALL) {
2301	fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2302	}
2303	#endif
2304	if (e2 & DESC_S_MASK) {
2305	if (!(e2 & DESC_CS_MASK))
2306	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2307	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2308	if (e2 & DESC_C_MASK) {
2309	/* conforming code segment */
2310	if (dpl > cpl)
2311	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2312	} else {
2313	/* non conforming code segment */
2314	rpl = new_cs & 3;
2315	if (rpl > cpl)
2316	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2317	if (dpl != cpl)
2318	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2319	}
2320	if (!(e2 & DESC_P_MASK))
2321	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2322
2323	#ifdef TARGET_X86_64
2324	/* XXX: check 16/32 bit cases in long mode */
2325	if (shift == 2) {
2326	target_ulong rsp;
2327	/* 64 bit case */
2328	rsp = ESP;
2329	PUSHQ(rsp, env->segs[R_CS].selector);
2330	PUSHQ(rsp, next_eip);
2331	/* from this point, not restartable */
2332	ESP = rsp;
2333	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2334	get_seg_base(e1, e2),
2335	get_seg_limit(e1, e2), e2);
2336	EIP = new_eip;
2337	} else
2338	#endif
2339	{
2340	sp = ESP;
2341	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2342	ssp = env->segs[R_SS].base;
2343	if (shift) {
2344	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2345	PUSHL(ssp, sp, sp_mask, next_eip);
2346	} else {
2347	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2348	PUSHW(ssp, sp, sp_mask, next_eip);
2349	}
2350
2351	limit = get_seg_limit(e1, e2);
2352	if (new_eip > limit)
2353	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2354	/* from this point, not restartable */
2355	SET_ESP(sp, sp_mask);
2356	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2357	get_seg_base(e1, e2), limit, e2);
2358	EIP = new_eip;
2359	}
2360	} else {
2361	/* check gate type */
2362	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
2363	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2364	rpl = new_cs & 3;
2365	switch(type) {
2366	case 1: /* available 286 TSS */
2367	case 9: /* available 386 TSS */
2368	case 5: /* task gate */
2369	if (dpl < cpl \|\| dpl < rpl)
2370	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2371	switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
2372	CC_OP = CC_OP_EFLAGS;
2373	return;
2374	case 4: /* 286 call gate */
2375	case 12: /* 386 call gate */
2376	break;
2377	default:
2378	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2379	break;
2380	}
2381	shift = type >> 3;
2382
2383	if (dpl < cpl \|\| dpl < rpl)
2384	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2385	/* check valid bit */
2386	if (!(e2 & DESC_P_MASK))
2387	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2388	selector = e1 >> 16;
2389	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
2390	param_count = e2 & 0x1f;
2391	if ((selector & 0xfffc) == 0)
2392	raise_exception_err(EXCP0D_GPF, 0);
2393
2394	if (load_segment(&e1, &e2, selector) != 0)
2395	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2396	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
2397	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2398	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2399	if (dpl > cpl)
2400	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2401	if (!(e2 & DESC_P_MASK))
2402	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2403
2404	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2405	/* to inner priviledge */
2406	get_ss_esp_from_tss(&ss, &sp, dpl);
2407	#ifdef DEBUG_PCALL
2408	if (loglevel & CPU_LOG_PCALL)
2409	fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2410	ss, sp, param_count, ESP);
2411	#endif
2412	if ((ss & 0xfffc) == 0)
2413	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2414	if ((ss & 3) != dpl)
2415	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2416	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2417	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2418	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2419	if (ss_dpl != dpl)
2420	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2421	if (!(ss_e2 & DESC_S_MASK) \|\|
2422	(ss_e2 & DESC_CS_MASK) \|\|
2423	!(ss_e2 & DESC_W_MASK))
2424	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2425	if (!(ss_e2 & DESC_P_MASK))
2426	#ifdef VBOX /* See page 3-99 of 253666.pdf */
2427	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
2428	#else
2429	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2430	#endif
2431
2432	// push_size = ((param_count * 2) + 8) << shift;
2433
2434	old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2435	old_ssp = env->segs[R_SS].base;
2436
2437	sp_mask = get_sp_mask(ss_e2);
2438	ssp = get_seg_base(ss_e1, ss_e2);
2439	if (shift) {
2440	PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2441	PUSHL(ssp, sp, sp_mask, ESP);
2442	for(i = param_count - 1; i >= 0; i--) {
2443	val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2444	PUSHL(ssp, sp, sp_mask, val);
2445	}
2446	} else {
2447	PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2448	PUSHW(ssp, sp, sp_mask, ESP);
2449	for(i = param_count - 1; i >= 0; i--) {
2450	val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2451	PUSHW(ssp, sp, sp_mask, val);
2452	}
2453	}
2454	new_stack = 1;
2455	} else {
2456	/* to same priviledge */
2457	sp = ESP;
2458	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2459	ssp = env->segs[R_SS].base;
2460	// push_size = (4 << shift);
2461	new_stack = 0;
2462	}
2463
2464	if (shift) {
2465	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2466	PUSHL(ssp, sp, sp_mask, next_eip);
2467	} else {
2468	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2469	PUSHW(ssp, sp, sp_mask, next_eip);
2470	}
2471
2472	/* from this point, not restartable */
2473
2474	if (new_stack) {
2475	ss = (ss & ~3) \| dpl;
2476	cpu_x86_load_seg_cache(env, R_SS, ss,
2477	ssp,
2478	get_seg_limit(ss_e1, ss_e2),
2479	ss_e2);
2480	}
2481
2482	selector = (selector & ~3) \| dpl;
2483	cpu_x86_load_seg_cache(env, R_CS, selector,
2484	get_seg_base(e1, e2),
2485	get_seg_limit(e1, e2),
2486	e2);
2487	cpu_x86_set_cpl(env, dpl);
2488	SET_ESP(sp, sp_mask);
2489	EIP = offset;
2490	}
2491	#ifdef USE_KQEMU
2492	if (kqemu_is_ok(env)) {
2493	env->exception_index = -1;
2494	cpu_loop_exit();
2495	}
2496	#endif
2497	}
2498
2499	/* real and vm86 mode iret */
2500	void helper_iret_real(int shift)
2501	{
2502	uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2503	target_ulong ssp;
2504	int eflags_mask;
2505	#ifdef VBOX
2506	bool fVME = false;
2507
2508	remR3TrapClear(env->pVM);
2509	#endif /* VBOX */
2510
2511	sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2512	sp = ESP;
2513	ssp = env->segs[R_SS].base;
2514	if (shift == 1) {
2515	/* 32 bits */
2516	POPL(ssp, sp, sp_mask, new_eip);
2517	POPL(ssp, sp, sp_mask, new_cs);
2518	new_cs &= 0xffff;
2519	POPL(ssp, sp, sp_mask, new_eflags);
2520	} else {
2521	/* 16 bits */
2522	POPW(ssp, sp, sp_mask, new_eip);
2523	POPW(ssp, sp, sp_mask, new_cs);
2524	POPW(ssp, sp, sp_mask, new_eflags);
2525	}
2526	#ifdef VBOX
2527	if ( (env->eflags & VM_MASK)
2528	&& ((env->eflags >> IOPL_SHIFT) & 3) != 3
2529	&& (env->cr[4] & CR4_VME_MASK)) /* implied or else we would fault earlier */
2530	{
2531	fVME = true;
2532	/* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
2533	/* if TF will be set -> #GP */
2534	if ( ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
2535	\|\| (new_eflags & TF_MASK))
2536	raise_exception(EXCP0D_GPF);
2537	}
2538	#endif /* VBOX */
2539
2540	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);
2541	load_seg_vm(R_CS, new_cs);
2542	env->eip = new_eip;
2543	#ifdef VBOX
2544	if (fVME)
2545	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2546	else
2547	#endif
2548	if (env->eflags & VM_MASK)
2549	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| RF_MASK \| NT_MASK;
2550	else
2551	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| IOPL_MASK \| RF_MASK \| NT_MASK;
2552	if (shift == 0)
2553	eflags_mask &= 0xffff;
2554	load_eflags(new_eflags, eflags_mask);
2555
2556	#ifdef VBOX
2557	if (fVME)
2558	{
2559	if (new_eflags & IF_MASK)
2560	env->eflags \|= VIF_MASK;
2561	else
2562	env->eflags &= ~VIF_MASK;
2563	}
2564	#endif /* VBOX */
2565	}
2566
2567	static inline void validate_seg(int seg_reg, int cpl)
2568	{
2569	int dpl;
2570	uint32_t e2;
2571
2572	/* XXX: on x86_64, we do not want to nullify FS and GS because
2573	they may still contain a valid base. I would be interested to
2574	know how a real x86_64 CPU behaves */
2575	if ((seg_reg == R_FS \|\| seg_reg == R_GS) &&
2576	(env->segs[seg_reg].selector & 0xfffc) == 0)
2577	return;
2578
2579	e2 = env->segs[seg_reg].flags;
2580	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2581	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2582	/* data or non conforming code segment */
2583	if (dpl < cpl) {
2584	cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2585	}
2586	}
2587	}
2588
2589	/* protected mode iret */
2590	static inline void helper_ret_protected(int shift, int is_iret, int addend)
2591	{
2592	uint32_t new_cs, new_eflags, new_ss;
2593	uint32_t new_es, new_ds, new_fs, new_gs;
2594	uint32_t e1, e2, ss_e1, ss_e2;
2595	int cpl, dpl, rpl, eflags_mask, iopl;
2596	target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2597
2598	#ifdef TARGET_X86_64
2599	if (shift == 2)
2600	sp_mask = -1;
2601	else
2602	#endif
2603	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2604	sp = ESP;
2605	ssp = env->segs[R_SS].base;
2606	new_eflags = 0; /* avoid warning */
2607	#ifdef TARGET_X86_64
2608	if (shift == 2) {
2609	POPQ(sp, new_eip);
2610	POPQ(sp, new_cs);
2611	new_cs &= 0xffff;
2612	if (is_iret) {
2613	POPQ(sp, new_eflags);
2614	}
2615	} else
2616	#endif
2617	if (shift == 1) {
2618	/* 32 bits */
2619	POPL(ssp, sp, sp_mask, new_eip);
2620	POPL(ssp, sp, sp_mask, new_cs);
2621	new_cs &= 0xffff;
2622	if (is_iret) {
2623	POPL(ssp, sp, sp_mask, new_eflags);
2624	#if defined(VBOX) && defined(DEBUG)
2625	printf("iret: new CS %04X\n", new_cs);
2626	printf("iret: new EIP %08X\n", new_eip);
2627	printf("iret: new EFLAGS %08X\n", new_eflags);
2628	printf("iret: EAX=%08x\n", EAX);
2629	#endif
2630
2631	if (new_eflags & VM_MASK)
2632	goto return_to_vm86;
2633	}
2634	#ifdef VBOX
2635	if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
2636	{
2637	#ifdef DEBUG
2638	printf("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc);
2639	#endif
2640	new_cs = new_cs & 0xfffc;
2641	}
2642	#endif
2643	} else {
2644	/* 16 bits */
2645	POPW(ssp, sp, sp_mask, new_eip);
2646	POPW(ssp, sp, sp_mask, new_cs);
2647	if (is_iret)
2648	POPW(ssp, sp, sp_mask, new_eflags);
2649	}
2650	#ifdef DEBUG_PCALL
2651	if (loglevel & CPU_LOG_PCALL) {
2652	fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2653	new_cs, new_eip, shift, addend);
2654	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2655	}
2656	#endif
2657	if ((new_cs & 0xfffc) == 0)
2658	{
2659	#if defined(VBOX) && defined(DEBUG)
2660	printf("new_cs & 0xfffc) == 0\n");
2661	#endif
2662	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2663	}
2664	if (load_segment(&e1, &e2, new_cs) != 0)
2665	{
2666	#if defined(VBOX) && defined(DEBUG)
2667	printf("load_segment failed\n");
2668	#endif
2669	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2670	}
2671	if (!(e2 & DESC_S_MASK) \|\|
2672	!(e2 & DESC_CS_MASK))
2673	{
2674	#if defined(VBOX) && defined(DEBUG)
2675	printf("e2 mask %08x\n", e2);
2676	#endif
2677	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2678	}
2679	cpl = env->hflags & HF_CPL_MASK;
2680	rpl = new_cs & 3;
2681	if (rpl < cpl)
2682	{
2683	#if defined(VBOX) && defined(DEBUG)
2684	printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2685	#endif
2686	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2687	}
2688	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2689	if (e2 & DESC_C_MASK) {
2690	if (dpl > rpl)
2691	{
2692	#if defined(VBOX) && defined(DEBUG)
2693	printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2694	#endif
2695	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2696	}
2697	} else {
2698	if (dpl != rpl)
2699	{
2700	#if defined(VBOX) && defined(DEBUG)
2701	printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2702	#endif
2703	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2704	}
2705	}
2706	if (!(e2 & DESC_P_MASK))
2707	{
2708	#if defined(VBOX) && defined(DEBUG)
2709	printf("DESC_P_MASK e2=%08x\n", e2);
2710	#endif
2711	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2712	}
2713	sp += addend;
2714	if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) \|\|
2715	((env->hflags & HF_CS64_MASK) && !is_iret))) {
2716	/* return to same priledge level */
2717	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2718	get_seg_base(e1, e2),
2719	get_seg_limit(e1, e2),
2720	e2);
2721	} else {
2722	/* return to different priviledge level */
2723	#ifdef TARGET_X86_64
2724	if (shift == 2) {
2725	POPQ(sp, new_esp);
2726	POPQ(sp, new_ss);
2727	new_ss &= 0xffff;
2728	} else
2729	#endif
2730	if (shift == 1) {
2731	/* 32 bits */
2732	POPL(ssp, sp, sp_mask, new_esp);
2733	POPL(ssp, sp, sp_mask, new_ss);
2734	new_ss &= 0xffff;
2735	} else {
2736	/* 16 bits */
2737	POPW(ssp, sp, sp_mask, new_esp);
2738	POPW(ssp, sp, sp_mask, new_ss);
2739	}
2740	#ifdef DEBUG_PCALL
2741	if (loglevel & CPU_LOG_PCALL) {
2742	fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2743	new_ss, new_esp);
2744	}
2745	#endif
2746	if ((new_ss & 0xfffc) == 0) {
2747	#ifdef TARGET_X86_64
2748	/* NULL ss is allowed in long mode if cpl != 3*/
2749	/* XXX: test CS64 ? */
2750	if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2751	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2752	0, 0xffffffff,
2753	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2754	DESC_S_MASK \| (rpl << DESC_DPL_SHIFT) \|
2755	DESC_W_MASK \| DESC_A_MASK);
2756	ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
2757	} else
2758	#endif
2759	{
2760	raise_exception_err(EXCP0D_GPF, 0);
2761	}
2762	} else {
2763	if ((new_ss & 3) != rpl)
2764	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2765	if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2766	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2767	if (!(ss_e2 & DESC_S_MASK) \|\|
2768	(ss_e2 & DESC_CS_MASK) \|\|
2769	!(ss_e2 & DESC_W_MASK))
2770	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2771	dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2772	if (dpl != rpl)
2773	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2774	if (!(ss_e2 & DESC_P_MASK))
2775	raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2776	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2777	get_seg_base(ss_e1, ss_e2),
2778	get_seg_limit(ss_e1, ss_e2),
2779	ss_e2);
2780	}
2781
2782	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2783	get_seg_base(e1, e2),
2784	get_seg_limit(e1, e2),
2785	e2);
2786	cpu_x86_set_cpl(env, rpl);
2787	sp = new_esp;
2788	#ifdef TARGET_X86_64
2789	if (env->hflags & HF_CS64_MASK)
2790	sp_mask = -1;
2791	else
2792	#endif
2793	sp_mask = get_sp_mask(ss_e2);
2794
2795	/* validate data segments */
2796	validate_seg(R_ES, rpl);
2797	validate_seg(R_DS, rpl);
2798	validate_seg(R_FS, rpl);
2799	validate_seg(R_GS, rpl);
2800
2801	sp += addend;
2802	}
2803	SET_ESP(sp, sp_mask);
2804	env->eip = new_eip;
2805	if (is_iret) {
2806	/* NOTE: 'cpl' is the _old_ CPL */
2807	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2808	if (cpl == 0)
2809	#ifdef VBOX
2810	eflags_mask \|= IOPL_MASK \| VIF_MASK \| VIP_MASK;
2811	#else
2812	eflags_mask \|= IOPL_MASK;
2813	#endif
2814	iopl = (env->eflags >> IOPL_SHIFT) & 3;
2815	if (cpl <= iopl)
2816	eflags_mask \|= IF_MASK;
2817	if (shift == 0)
2818	eflags_mask &= 0xffff;
2819	load_eflags(new_eflags, eflags_mask);
2820	}
2821	return;
2822
2823	return_to_vm86:
2824
2825	#if 0 // defined(VBOX) && defined(DEBUG)
2826	printf("V86: new CS %04X\n", new_cs);
2827	printf("V86: Descriptor %08X:%08X\n", e2, e1);
2828	printf("V86: new EIP %08X\n", new_eip);
2829	printf("V86: new EFLAGS %08X\n", new_eflags);
2830	#endif
2831
2832	POPL(ssp, sp, sp_mask, new_esp);
2833	POPL(ssp, sp, sp_mask, new_ss);
2834	POPL(ssp, sp, sp_mask, new_es);
2835	POPL(ssp, sp, sp_mask, new_ds);
2836	POPL(ssp, sp, sp_mask, new_fs);
2837	POPL(ssp, sp, sp_mask, new_gs);
2838
2839	/* modify processor state */
2840	load_eflags(new_eflags, TF_MASK \| AC_MASK \| ID_MASK \|
2841	IF_MASK \| IOPL_MASK \| VM_MASK \| NT_MASK \| VIF_MASK \| VIP_MASK);
2842	load_seg_vm(R_CS, new_cs & 0xffff);
2843	cpu_x86_set_cpl(env, 3);
2844	load_seg_vm(R_SS, new_ss & 0xffff);
2845	load_seg_vm(R_ES, new_es & 0xffff);
2846	load_seg_vm(R_DS, new_ds & 0xffff);
2847	load_seg_vm(R_FS, new_fs & 0xffff);
2848	load_seg_vm(R_GS, new_gs & 0xffff);
2849
2850	env->eip = new_eip & 0xffff;
2851	ESP = new_esp;
2852	}
2853
2854	void helper_iret_protected(int shift, int next_eip)
2855	{
2856	int tss_selector, type;
2857	uint32_t e1, e2;
2858
2859	#ifdef VBOX
2860	remR3TrapClear(env->pVM);
2861	#endif
2862
2863	/* specific case for TSS */
2864	if (env->eflags & NT_MASK) {
2865	#ifdef TARGET_X86_64
2866	if (env->hflags & HF_LMA_MASK)
2867	raise_exception_err(EXCP0D_GPF, 0);
2868	#endif
2869	tss_selector = lduw_kernel(env->tr.base + 0);
2870	if (tss_selector & 4)
2871	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2872	if (load_segment(&e1, &e2, tss_selector) != 0)
2873	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2874	type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2875	/* NOTE: we check both segment and busy TSS */
2876	if (type != 3)
2877	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2878	switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2879	} else {
2880	helper_ret_protected(shift, 1, 0);
2881	}
2882	#ifdef USE_KQEMU
2883	if (kqemu_is_ok(env)) {
2884	CC_OP = CC_OP_EFLAGS;
2885	env->exception_index = -1;
2886	cpu_loop_exit();
2887	}
2888	#endif
2889	}
2890
2891	void helper_lret_protected(int shift, int addend)
2892	{
2893	helper_ret_protected(shift, 0, addend);
2894	#ifdef USE_KQEMU
2895	if (kqemu_is_ok(env)) {
2896	env->exception_index = -1;
2897	cpu_loop_exit();
2898	}
2899	#endif
2900	}
2901
2902	void helper_sysenter(void)
2903	{
2904	if (env->sysenter_cs == 0) {
2905	raise_exception_err(EXCP0D_GPF, 0);
2906	}
2907	env->eflags &= ~(VM_MASK \| IF_MASK \| RF_MASK);
2908	cpu_x86_set_cpl(env, 0);
2909	cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2910	0, 0xffffffff,
2911	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2912	DESC_S_MASK \|
2913	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2914	cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2915	0, 0xffffffff,
2916	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2917	DESC_S_MASK \|
2918	DESC_W_MASK \| DESC_A_MASK);
2919	ESP = env->sysenter_esp;
2920	EIP = env->sysenter_eip;
2921	}
2922
2923	void helper_sysexit(void)
2924	{
2925	int cpl;
2926
2927	cpl = env->hflags & HF_CPL_MASK;
2928	if (env->sysenter_cs == 0 \|\| cpl != 0) {
2929	raise_exception_err(EXCP0D_GPF, 0);
2930	}
2931	cpu_x86_set_cpl(env, 3);
2932	cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) \| 3,
2933	0, 0xffffffff,
2934	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2935	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2936	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2937	cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) \| 3,
2938	0, 0xffffffff,
2939	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2940	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2941	DESC_W_MASK \| DESC_A_MASK);
2942	ESP = ECX;
2943	EIP = EDX;
2944	#ifdef USE_KQEMU
2945	if (kqemu_is_ok(env)) {
2946	env->exception_index = -1;
2947	cpu_loop_exit();
2948	}
2949	#endif
2950	}
2951
2952	void helper_movl_crN_T0(int reg)
2953	{
2954	#if !defined(CONFIG_USER_ONLY)
2955	switch(reg) {
2956	case 0:
2957	cpu_x86_update_cr0(env, T0);
2958	break;
2959	case 3:
2960	cpu_x86_update_cr3(env, T0);
2961	break;
2962	case 4:
2963	cpu_x86_update_cr4(env, T0);
2964	break;
2965	case 8:
2966	cpu_set_apic_tpr(env, T0);
2967	break;
2968	default:
2969	env->cr[reg] = T0;
2970	break;
2971	}
2972	#endif
2973	}
2974
2975	/* XXX: do more */
2976	void helper_movl_drN_T0(int reg)
2977	{
2978	env->dr[reg] = T0;
2979	}
2980
2981	void helper_invlpg(target_ulong addr)
2982	{
2983	cpu_x86_flush_tlb(env, addr);
2984	}
2985
2986	void helper_rdtsc(void)
2987	{
2988	uint64_t val;
2989
2990	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2991	raise_exception(EXCP0D_GPF);
2992	}
2993	val = cpu_get_tsc(env);
2994	EAX = (uint32_t)(val);
2995	EDX = (uint32_t)(val >> 32);
2996	}
2997
2998	#if defined(CONFIG_USER_ONLY)
2999	void helper_wrmsr(void)
3000	{
3001	}
3002
3003	void helper_rdmsr(void)
3004	{
3005	}
3006	#else
3007	void helper_wrmsr(void)
3008	{
3009	uint64_t val;
3010
3011	val = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
3012
3013	switch((uint32_t)ECX) {
3014	case MSR_IA32_SYSENTER_CS:
3015	env->sysenter_cs = val & 0xffff;
3016	break;
3017	case MSR_IA32_SYSENTER_ESP:
3018	env->sysenter_esp = val;
3019	break;
3020	case MSR_IA32_SYSENTER_EIP:
3021	env->sysenter_eip = val;
3022	break;
3023	case MSR_IA32_APICBASE:
3024	cpu_set_apic_base(env, val);
3025	break;
3026	case MSR_EFER:
3027	{
3028	uint64_t update_mask;
3029	update_mask = 0;
3030	if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
3031	update_mask \|= MSR_EFER_SCE;
3032	if (env->cpuid_ext2_features & CPUID_EXT2_LM)
3033	update_mask \|= MSR_EFER_LME;
3034	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
3035	update_mask \|= MSR_EFER_FFXSR;
3036	if (env->cpuid_ext2_features & CPUID_EXT2_NX)
3037	update_mask \|= MSR_EFER_NXE;
3038	env->efer = (env->efer & ~update_mask) \|
3039	(val & update_mask);
3040	}
3041	break;
3042	case MSR_STAR:
3043	env->star = val;
3044	break;
3045	case MSR_PAT:
3046	env->pat = val;
3047	break;
3048	#ifdef TARGET_X86_64
3049	case MSR_LSTAR:
3050	env->lstar = val;
3051	break;
3052	case MSR_CSTAR:
3053	env->cstar = val;
3054	break;
3055	case MSR_FMASK:
3056	env->fmask = val;
3057	break;
3058	case MSR_FSBASE:
3059	env->segs[R_FS].base = val;
3060	break;
3061	case MSR_GSBASE:
3062	env->segs[R_GS].base = val;
3063	break;
3064	case MSR_KERNELGSBASE:
3065	env->kernelgsbase = val;
3066	break;
3067	#endif
3068	default:
3069	/* XXX: exception ? */
3070	break;
3071	}
3072	}
3073
3074	void helper_rdmsr(void)
3075	{
3076	uint64_t val;
3077	switch((uint32_t)ECX) {
3078	case MSR_IA32_SYSENTER_CS:
3079	val = env->sysenter_cs;
3080	break;
3081	case MSR_IA32_SYSENTER_ESP:
3082	val = env->sysenter_esp;
3083	break;
3084	case MSR_IA32_SYSENTER_EIP:
3085	val = env->sysenter_eip;
3086	break;
3087	case MSR_IA32_APICBASE:
3088	val = cpu_get_apic_base(env);
3089	break;
3090	case MSR_EFER:
3091	val = env->efer;
3092	break;
3093	case MSR_STAR:
3094	val = env->star;
3095	break;
3096	case MSR_PAT:
3097	val = env->pat;
3098	break;
3099	#ifdef TARGET_X86_64
3100	case MSR_LSTAR:
3101	val = env->lstar;
3102	break;
3103	case MSR_CSTAR:
3104	val = env->cstar;
3105	break;
3106	case MSR_FMASK:
3107	val = env->fmask;
3108	break;
3109	case MSR_FSBASE:
3110	val = env->segs[R_FS].base;
3111	break;
3112	case MSR_GSBASE:
3113	val = env->segs[R_GS].base;
3114	break;
3115	case MSR_KERNELGSBASE:
3116	val = env->kernelgsbase;
3117	break;
3118	#endif
3119	default:
3120	/* XXX: exception ? */
3121	val = 0;
3122	break;
3123	}
3124	EAX = (uint32_t)(val);
3125	EDX = (uint32_t)(val >> 32);
3126	}
3127	#endif
3128
3129	void helper_lsl(void)
3130	{
3131	unsigned int selector, limit;
3132	uint32_t e1, e2, eflags;
3133	int rpl, dpl, cpl, type;
3134
3135	eflags = cc_table[CC_OP].compute_all();
3136	selector = T0 & 0xffff;
3137	if (load_segment(&e1, &e2, selector) != 0)
3138	goto fail;
3139	rpl = selector & 3;
3140	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3141	cpl = env->hflags & HF_CPL_MASK;
3142	if (e2 & DESC_S_MASK) {
3143	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3144	/* conforming */
3145	} else {
3146	if (dpl < cpl \|\| dpl < rpl)
3147	goto fail;
3148	}
3149	} else {
3150	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3151	switch(type) {
3152	case 1:
3153	case 2:
3154	case 3:
3155	case 9:
3156	case 11:
3157	break;
3158	default:
3159	goto fail;
3160	}
3161	if (dpl < cpl \|\| dpl < rpl) {
3162	fail:
3163	CC_SRC = eflags & ~CC_Z;
3164	return;
3165	}
3166	}
3167	limit = get_seg_limit(e1, e2);
3168	T1 = limit;
3169	CC_SRC = eflags \| CC_Z;
3170	}
3171
3172	void helper_lar(void)
3173	{
3174	unsigned int selector;
3175	uint32_t e1, e2, eflags;
3176	int rpl, dpl, cpl, type;
3177
3178	eflags = cc_table[CC_OP].compute_all();
3179	selector = T0 & 0xffff;
3180	if ((selector & 0xfffc) == 0)
3181	goto fail;
3182	if (load_segment(&e1, &e2, selector) != 0)
3183	goto fail;
3184	rpl = selector & 3;
3185	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3186	cpl = env->hflags & HF_CPL_MASK;
3187	if (e2 & DESC_S_MASK) {
3188	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3189	/* conforming */
3190	} else {
3191	if (dpl < cpl \|\| dpl < rpl)
3192	goto fail;
3193	}
3194	} else {
3195	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3196	switch(type) {
3197	case 1:
3198	case 2:
3199	case 3:
3200	case 4:
3201	case 5:
3202	case 9:
3203	case 11:
3204	case 12:
3205	break;
3206	default:
3207	goto fail;
3208	}
3209	if (dpl < cpl \|\| dpl < rpl) {
3210	fail:
3211	CC_SRC = eflags & ~CC_Z;
3212	return;
3213	}
3214	}
3215	T1 = e2 & 0x00f0ff00;
3216	CC_SRC = eflags \| CC_Z;
3217	}
3218
3219	void helper_verr(void)
3220	{
3221	unsigned int selector;
3222	uint32_t e1, e2, eflags;
3223	int rpl, dpl, cpl;
3224
3225	eflags = cc_table[CC_OP].compute_all();
3226	selector = T0 & 0xffff;
3227	if ((selector & 0xfffc) == 0)
3228	goto fail;
3229	if (load_segment(&e1, &e2, selector) != 0)
3230	goto fail;
3231	if (!(e2 & DESC_S_MASK))
3232	goto fail;
3233	rpl = selector & 3;
3234	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3235	cpl = env->hflags & HF_CPL_MASK;
3236	if (e2 & DESC_CS_MASK) {
3237	if (!(e2 & DESC_R_MASK))
3238	goto fail;
3239	if (!(e2 & DESC_C_MASK)) {
3240	if (dpl < cpl \|\| dpl < rpl)
3241	goto fail;
3242	}
3243	} else {
3244	if (dpl < cpl \|\| dpl < rpl) {
3245	fail:
3246	CC_SRC = eflags & ~CC_Z;
3247	return;
3248	}
3249	}
3250	CC_SRC = eflags \| CC_Z;
3251	}
3252
3253	void helper_verw(void)
3254	{
3255	unsigned int selector;
3256	uint32_t e1, e2, eflags;
3257	int rpl, dpl, cpl;
3258
3259	eflags = cc_table[CC_OP].compute_all();
3260	selector = T0 & 0xffff;
3261	if ((selector & 0xfffc) == 0)
3262	goto fail;
3263	if (load_segment(&e1, &e2, selector) != 0)
3264	goto fail;
3265	if (!(e2 & DESC_S_MASK))
3266	goto fail;
3267	rpl = selector & 3;
3268	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3269	cpl = env->hflags & HF_CPL_MASK;
3270	if (e2 & DESC_CS_MASK) {
3271	goto fail;
3272	} else {
3273	if (dpl < cpl \|\| dpl < rpl)
3274	goto fail;
3275	if (!(e2 & DESC_W_MASK)) {
3276	fail:
3277	CC_SRC = eflags & ~CC_Z;
3278	return;
3279	}
3280	}
3281	CC_SRC = eflags \| CC_Z;
3282	}
3283
3284	/* FPU helpers */
3285
3286	void helper_fldt_ST0_A0(void)
3287	{
3288	int new_fpstt;
3289	new_fpstt = (env->fpstt - 1) & 7;
3290	env->fpregs[new_fpstt].d = helper_fldt(A0);
3291	env->fpstt = new_fpstt;
3292	env->fptags[new_fpstt] = 0; /* validate stack entry */
3293	}
3294
3295	void helper_fstt_ST0_A0(void)
3296	{
3297	helper_fstt(ST0, A0);
3298	}
3299
3300	void fpu_set_exception(int mask)
3301	{
3302	env->fpus \|= mask;
3303	if (env->fpus & (~env->fpuc & FPUC_EM))
3304	env->fpus \|= FPUS_SE \| FPUS_B;
3305	}
3306
3307	CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
3308	{
3309	if (b == 0.0)
3310	fpu_set_exception(FPUS_ZE);
3311	return a / b;
3312	}
3313
3314	void fpu_raise_exception(void)
3315	{
3316	if (env->cr[0] & CR0_NE_MASK) {
3317	raise_exception(EXCP10_COPR);
3318	}
3319	#if !defined(CONFIG_USER_ONLY)
3320	else {
3321	cpu_set_ferr(env);
3322	}
3323	#endif
3324	}
3325
3326	/* BCD ops */
3327
3328	void helper_fbld_ST0_A0(void)
3329	{
3330	CPU86_LDouble tmp;
3331	uint64_t val;
3332	unsigned int v;
3333	int i;
3334
3335	val = 0;
3336	for(i = 8; i >= 0; i--) {
3337	v = ldub(A0 + i);
3338	val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
3339	}
3340	tmp = val;
3341	if (ldub(A0 + 9) & 0x80)
3342	tmp = -tmp;
3343	fpush();
3344	ST0 = tmp;
3345	}
3346
3347	void helper_fbst_ST0_A0(void)
3348	{
3349	int v;
3350	target_ulong mem_ref, mem_end;
3351	int64_t val;
3352
3353	val = floatx_to_int64(ST0, &env->fp_status);
3354	mem_ref = A0;
3355	mem_end = mem_ref + 9;
3356	if (val < 0) {
3357	stb(mem_end, 0x80);
3358	val = -val;
3359	} else {
3360	stb(mem_end, 0x00);
3361	}
3362	while (mem_ref < mem_end) {
3363	if (val == 0)
3364	break;
3365	v = val % 100;
3366	val = val / 100;
3367	v = ((v / 10) << 4) \| (v % 10);
3368	stb(mem_ref++, v);
3369	}
3370	while (mem_ref < mem_end) {
3371	stb(mem_ref++, 0);
3372	}
3373	}
3374
3375	void helper_f2xm1(void)
3376	{
3377	ST0 = pow(2.0,ST0) - 1.0;
3378	}
3379
3380	void helper_fyl2x(void)
3381	{
3382	CPU86_LDouble fptemp;
3383
3384	fptemp = ST0;
3385	if (fptemp>0.0){
3386	fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3387	ST1 *= fptemp;
3388	fpop();
3389	} else {
3390	env->fpus &= (~0x4700);
3391	env->fpus \|= 0x400;
3392	}
3393	}
3394
3395	void helper_fptan(void)
3396	{
3397	CPU86_LDouble fptemp;
3398
3399	fptemp = ST0;
3400	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3401	env->fpus \|= 0x400;
3402	} else {
3403	ST0 = tan(fptemp);
3404	fpush();
3405	ST0 = 1.0;
3406	env->fpus &= (~0x400); /* C2 <-- 0 */
3407	/* the above code is for \|arg\| < 2*52 only /
3408	}
3409	}
3410
3411	void helper_fpatan(void)
3412	{
3413	CPU86_LDouble fptemp, fpsrcop;
3414
3415	fpsrcop = ST1;
3416	fptemp = ST0;
3417	ST1 = atan2(fpsrcop,fptemp);
3418	fpop();
3419	}
3420
3421	void helper_fxtract(void)
3422	{
3423	CPU86_LDoubleU temp;
3424	unsigned int expdif;
3425
3426	temp.d = ST0;
3427	expdif = EXPD(temp) - EXPBIAS;
3428	/DP exponent bias/
3429	ST0 = expdif;
3430	fpush();
3431	BIASEXPONENT(temp);
3432	ST0 = temp.d;
3433	}
3434
3435	void helper_fprem1(void)
3436	{
3437	CPU86_LDouble dblq, fpsrcop, fptemp;
3438	CPU86_LDoubleU fpsrcop1, fptemp1;
3439	int expdif;
3440	int q;
3441
3442	fpsrcop = ST0;
3443	fptemp = ST1;
3444	fpsrcop1.d = fpsrcop;
3445	fptemp1.d = fptemp;
3446	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3447	if (expdif < 53) {
3448	dblq = fpsrcop / fptemp;
3449	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3450	ST0 = fpsrcop - fptemp*dblq;
3451	q = (int)dblq; /* cutting off top bits is assumed here */
3452	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3453	/* (C0,C1,C3) <-- (q2,q1,q0) */
3454	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3455	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3456	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3457	} else {
3458	env->fpus \|= 0x400; /* C2 <-- 1 */
3459	fptemp = pow(2.0, expdif-50);
3460	fpsrcop = (ST0 / ST1) / fptemp;
3461	/* fpsrcop = integer obtained by rounding to the nearest */
3462	fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3463	floor(fpsrcop): ceil(fpsrcop);
3464	ST0 -= (ST1 * fpsrcop * fptemp);
3465	}
3466	}
3467
3468	void helper_fprem(void)
3469	{
3470	CPU86_LDouble dblq, fpsrcop, fptemp;
3471	CPU86_LDoubleU fpsrcop1, fptemp1;
3472	int expdif;
3473	int q;
3474
3475	fpsrcop = ST0;
3476	fptemp = ST1;
3477	fpsrcop1.d = fpsrcop;
3478	fptemp1.d = fptemp;
3479	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3480	if ( expdif < 53 ) {
3481	dblq = fpsrcop / fptemp;
3482	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3483	ST0 = fpsrcop - fptemp*dblq;
3484	q = (int)dblq; /* cutting off top bits is assumed here */
3485	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3486	/* (C0,C1,C3) <-- (q2,q1,q0) */
3487	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3488	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3489	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3490	} else {
3491	env->fpus \|= 0x400; /* C2 <-- 1 */
3492	fptemp = pow(2.0, expdif-50);
3493	fpsrcop = (ST0 / ST1) / fptemp;
3494	/* fpsrcop = integer obtained by chopping */
3495	fpsrcop = (fpsrcop < 0.0)?
3496	-(floor(fabs(fpsrcop))): floor(fpsrcop);
3497	ST0 -= (ST1 * fpsrcop * fptemp);
3498	}
3499	}
3500
3501	void helper_fyl2xp1(void)
3502	{
3503	CPU86_LDouble fptemp;
3504
3505	fptemp = ST0;
3506	if ((fptemp+1.0)>0.0) {
3507	fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3508	ST1 *= fptemp;
3509	fpop();
3510	} else {
3511	env->fpus &= (~0x4700);
3512	env->fpus \|= 0x400;
3513	}
3514	}
3515
3516	void helper_fsqrt(void)
3517	{
3518	CPU86_LDouble fptemp;
3519
3520	fptemp = ST0;
3521	if (fptemp<0.0) {
3522	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3523	env->fpus \|= 0x400;
3524	}
3525	ST0 = sqrt(fptemp);
3526	}
3527
3528	void helper_fsincos(void)
3529	{
3530	CPU86_LDouble fptemp;
3531
3532	fptemp = ST0;
3533	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3534	env->fpus \|= 0x400;
3535	} else {
3536	ST0 = sin(fptemp);
3537	fpush();
3538	ST0 = cos(fptemp);
3539	env->fpus &= (~0x400); /* C2 <-- 0 */
3540	/* the above code is for \|arg\| < 2*63 only /
3541	}
3542	}
3543
3544	void helper_frndint(void)
3545	{
3546	ST0 = floatx_round_to_int(ST0, &env->fp_status);
3547	}
3548
3549	void helper_fscale(void)
3550	{
3551	ST0 = ldexp (ST0, (int)(ST1));
3552	}
3553
3554	void helper_fsin(void)
3555	{
3556	CPU86_LDouble fptemp;
3557
3558	fptemp = ST0;
3559	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3560	env->fpus \|= 0x400;
3561	} else {
3562	ST0 = sin(fptemp);
3563	env->fpus &= (~0x400); /* C2 <-- 0 */
3564	/* the above code is for \|arg\| < 2*53 only /
3565	}
3566	}
3567
3568	void helper_fcos(void)
3569	{
3570	CPU86_LDouble fptemp;
3571
3572	fptemp = ST0;
3573	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3574	env->fpus \|= 0x400;
3575	} else {
3576	ST0 = cos(fptemp);
3577	env->fpus &= (~0x400); /* C2 <-- 0 */
3578	/* the above code is for \|arg5 < 2*63 only /
3579	}
3580	}
3581
3582	void helper_fxam_ST0(void)
3583	{
3584	CPU86_LDoubleU temp;
3585	int expdif;
3586
3587	temp.d = ST0;
3588
3589	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3590	if (SIGND(temp))
3591	env->fpus \|= 0x200; /* C1 <-- 1 */
3592
3593	/* XXX: test fptags too */
3594	expdif = EXPD(temp);
3595	if (expdif == MAXEXPD) {
3596	#ifdef USE_X86LDOUBLE
3597	if (MANTD(temp) == 0x8000000000000000ULL)
3598	#else
3599	if (MANTD(temp) == 0)
3600	#endif
3601	env->fpus \|= 0x500 /Infinity/;
3602	else
3603	env->fpus \|= 0x100 /NaN/;
3604	} else if (expdif == 0) {
3605	if (MANTD(temp) == 0)
3606	env->fpus \|= 0x4000 /Zero/;
3607	else
3608	env->fpus \|= 0x4400 /Denormal/;
3609	} else {
3610	env->fpus \|= 0x400;
3611	}
3612	}
3613
3614	void helper_fstenv(target_ulong ptr, int data32)
3615	{
3616	int fpus, fptag, exp, i;
3617	uint64_t mant;
3618	CPU86_LDoubleU tmp;
3619
3620	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3621	fptag = 0;
3622	for (i=7; i>=0; i--) {
3623	fptag <<= 2;
3624	if (env->fptags[i]) {
3625	fptag \|= 3;
3626	} else {
3627	tmp.d = env->fpregs[i].d;
3628	exp = EXPD(tmp);
3629	mant = MANTD(tmp);
3630	if (exp == 0 && mant == 0) {
3631	/* zero */
3632	fptag \|= 1;
3633	} else if (exp == 0 \|\| exp == MAXEXPD
3634	#ifdef USE_X86LDOUBLE
3635	\|\| (mant & (1LL << 63)) == 0
3636	#endif
3637	) {
3638	/* NaNs, infinity, denormal */
3639	fptag \|= 2;
3640	}
3641	}
3642	}
3643	if (data32) {
3644	/* 32 bit */
3645	stl(ptr, env->fpuc);
3646	stl(ptr + 4, fpus);
3647	stl(ptr + 8, fptag);
3648	stl(ptr + 12, 0); /* fpip */
3649	stl(ptr + 16, 0); /* fpcs */
3650	stl(ptr + 20, 0); /* fpoo */
3651	stl(ptr + 24, 0); /* fpos */
3652	} else {
3653	/* 16 bit */
3654	stw(ptr, env->fpuc);
3655	stw(ptr + 2, fpus);
3656	stw(ptr + 4, fptag);
3657	stw(ptr + 6, 0);
3658	stw(ptr + 8, 0);
3659	stw(ptr + 10, 0);
3660	stw(ptr + 12, 0);
3661	}
3662	}
3663
3664	void helper_fldenv(target_ulong ptr, int data32)
3665	{
3666	int i, fpus, fptag;
3667
3668	if (data32) {
3669	env->fpuc = lduw(ptr);
3670	fpus = lduw(ptr + 4);
3671	fptag = lduw(ptr + 8);
3672	}
3673	else {
3674	env->fpuc = lduw(ptr);
3675	fpus = lduw(ptr + 2);
3676	fptag = lduw(ptr + 4);
3677	}
3678	env->fpstt = (fpus >> 11) & 7;
3679	env->fpus = fpus & ~0x3800;
3680	for(i = 0;i < 8; i++) {
3681	env->fptags[i] = ((fptag & 3) == 3);
3682	fptag >>= 2;
3683	}
3684	}
3685
3686	void helper_fsave(target_ulong ptr, int data32)
3687	{
3688	CPU86_LDouble tmp;
3689	int i;
3690
3691	helper_fstenv(ptr, data32);
3692
3693	ptr += (14 << data32);
3694	for(i = 0;i < 8; i++) {
3695	tmp = ST(i);
3696	helper_fstt(tmp, ptr);
3697	ptr += 10;
3698	}
3699
3700	/* fninit */
3701	env->fpus = 0;
3702	env->fpstt = 0;
3703	env->fpuc = 0x37f;
3704	env->fptags[0] = 1;
3705	env->fptags[1] = 1;
3706	env->fptags[2] = 1;
3707	env->fptags[3] = 1;
3708	env->fptags[4] = 1;
3709	env->fptags[5] = 1;
3710	env->fptags[6] = 1;
3711	env->fptags[7] = 1;
3712	}
3713
3714	void helper_frstor(target_ulong ptr, int data32)
3715	{
3716	CPU86_LDouble tmp;
3717	int i;
3718
3719	helper_fldenv(ptr, data32);
3720	ptr += (14 << data32);
3721
3722	for(i = 0;i < 8; i++) {
3723	tmp = helper_fldt(ptr);
3724	ST(i) = tmp;
3725	ptr += 10;
3726	}
3727	}
3728
3729	void helper_fxsave(target_ulong ptr, int data64)
3730	{
3731	int fpus, fptag, i, nb_xmm_regs;
3732	CPU86_LDouble tmp;
3733	target_ulong addr;
3734
3735	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3736	fptag = 0;
3737	for(i = 0; i < 8; i++) {
3738	fptag \|= (env->fptags[i] << i);
3739	}
3740	stw(ptr, env->fpuc);
3741	stw(ptr + 2, fpus);
3742	stw(ptr + 4, fptag ^ 0xff);
3743
3744	addr = ptr + 0x20;
3745	for(i = 0;i < 8; i++) {
3746	tmp = ST(i);
3747	helper_fstt(tmp, addr);
3748	addr += 16;
3749	}
3750
3751	if (env->cr[4] & CR4_OSFXSR_MASK) {
3752	/* XXX: finish it */
3753	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3754	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3755	nb_xmm_regs = 8 << data64;
3756	addr = ptr + 0xa0;
3757	for(i = 0; i < nb_xmm_regs; i++) {
3758	stq(addr, env->xmm_regs[i].XMM_Q(0));
3759	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3760	addr += 16;
3761	}
3762	}
3763	}
3764
3765	void helper_fxrstor(target_ulong ptr, int data64)
3766	{
3767	int i, fpus, fptag, nb_xmm_regs;
3768	CPU86_LDouble tmp;
3769	target_ulong addr;
3770
3771	env->fpuc = lduw(ptr);
3772	fpus = lduw(ptr + 2);
3773	fptag = lduw(ptr + 4);
3774	env->fpstt = (fpus >> 11) & 7;
3775	env->fpus = fpus & ~0x3800;
3776	fptag ^= 0xff;
3777	for(i = 0;i < 8; i++) {
3778	env->fptags[i] = ((fptag >> i) & 1);
3779	}
3780
3781	addr = ptr + 0x20;
3782	for(i = 0;i < 8; i++) {
3783	tmp = helper_fldt(addr);
3784	ST(i) = tmp;
3785	addr += 16;
3786	}
3787
3788	if (env->cr[4] & CR4_OSFXSR_MASK) {
3789	/* XXX: finish it */
3790	env->mxcsr = ldl(ptr + 0x18);
3791	//ldl(ptr + 0x1c);
3792	nb_xmm_regs = 8 << data64;
3793	addr = ptr + 0xa0;
3794	for(i = 0; i < nb_xmm_regs; i++) {
3795	#if !defined(VBOX) \|\| __GNUC__ < 4
3796	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3797	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3798	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3799	# if 1
3800	env->xmm_regs[i].XMM_L(0) = ldl(addr);
3801	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3802	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3803	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3804	# else
3805	/* this works fine on Mac OS X, gcc 4.0.1 */
3806	uint64_t u64 = ldq(addr);
3807	env->xmm_regs[i].XMM_Q(0);
3808	u64 = ldq(addr + 4);
3809	env->xmm_regs[i].XMM_Q(1) = u64;
3810	# endif
3811	#endif
3812	addr += 16;
3813	}
3814	}
3815	}
3816
3817	#ifndef USE_X86LDOUBLE
3818
3819	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3820	{
3821	CPU86_LDoubleU temp;
3822	int e;
3823
3824	temp.d = f;
3825	/* mantissa */
3826	*pmant = (MANTD(temp) << 11) \| (1LL << 63);
3827	/* exponent + sign */
3828	e = EXPD(temp) - EXPBIAS + 16383;
3829	e \|= SIGND(temp) >> 16;
3830	*pexp = e;
3831	}
3832
3833	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3834	{
3835	CPU86_LDoubleU temp;
3836	int e;
3837	uint64_t ll;
3838
3839	/* XXX: handle overflow ? */
3840	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3841	e \|= (upper >> 4) & 0x800; /* sign */
3842	ll = (mant >> 11) & ((1LL << 52) - 1);
3843	#ifdef __arm__
3844	temp.l.upper = (e << 20) \| (ll >> 32);
3845	temp.l.lower = ll;
3846	#else
3847	temp.ll = ll \| ((uint64_t)e << 52);
3848	#endif
3849	return temp.d;
3850	}
3851
3852	#else
3853
3854	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3855	{
3856	CPU86_LDoubleU temp;
3857
3858	temp.d = f;
3859	*pmant = temp.l.lower;
3860	*pexp = temp.l.upper;
3861	}
3862
3863	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3864	{
3865	CPU86_LDoubleU temp;
3866
3867	temp.l.upper = upper;
3868	temp.l.lower = mant;
3869	return temp.d;
3870	}
3871	#endif
3872
3873	#ifdef TARGET_X86_64
3874
3875	//#define DEBUG_MULDIV
3876
3877	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3878	{
3879	*plow += a;
3880	/* carry test */
3881	if (*plow < a)
3882	(*phigh)++;
3883	*phigh += b;
3884	}
3885
3886	static void neg128(uint64_t plow, uint64_t phigh)
3887	{
3888	plow = ~ plow;
3889	phigh = ~ phigh;
3890	add128(plow, phigh, 1, 0);
3891	}
3892
3893	static void mul64(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3894	{
3895	uint32_t a0, a1, b0, b1;
3896	uint64_t v;
3897
3898	a0 = a;
3899	a1 = a >> 32;
3900
3901	b0 = b;
3902	b1 = b >> 32;
3903
3904	v = (uint64_t)a0 * (uint64_t)b0;
3905	*plow = v;
3906	*phigh = 0;
3907
3908	v = (uint64_t)a0 * (uint64_t)b1;
3909	add128(plow, phigh, v << 32, v >> 32);
3910
3911	v = (uint64_t)a1 * (uint64_t)b0;
3912	add128(plow, phigh, v << 32, v >> 32);
3913
3914	v = (uint64_t)a1 * (uint64_t)b1;
3915	*phigh += v;
3916	#ifdef DEBUG_MULDIV
3917	printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
3918	a, b, phigh, plow);
3919	#endif
3920	}
3921
3922	static void imul64(uint64_t plow, uint64_t phigh, int64_t a, int64_t b)
3923	{
3924	int sa, sb;
3925	sa = (a < 0);
3926	if (sa)
3927	a = -a;
3928	sb = (b < 0);
3929	if (sb)
3930	b = -b;
3931	mul64(plow, phigh, a, b);
3932	if (sa ^ sb) {
3933	neg128(plow, phigh);
3934	}
3935	}
3936
3937	/* return TRUE if overflow */
3938	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
3939	{
3940	uint64_t q, r, a1, a0;
3941	int i, qb, ab;
3942
3943	a0 = *plow;
3944	a1 = *phigh;
3945	if (a1 == 0) {
3946	q = a0 / b;
3947	r = a0 % b;
3948	*plow = q;
3949	*phigh = r;
3950	} else {
3951	if (a1 >= b)
3952	return 1;
3953	/* XXX: use a better algorithm */
3954	for(i = 0; i < 64; i++) {
3955	ab = a1 >> 63;
3956	a1 = (a1 << 1) \| (a0 >> 63);
3957	if (ab \|\| a1 >= b) {
3958	a1 -= b;
3959	qb = 1;
3960	} else {
3961	qb = 0;
3962	}
3963	a0 = (a0 << 1) \| qb;
3964	}
3965	#if defined(DEBUG_MULDIV)
3966	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
3967	phigh, plow, b, a0, a1);
3968	#endif
3969	*plow = a0;
3970	*phigh = a1;
3971	}
3972	return 0;
3973	}
3974
3975	/* return TRUE if overflow */
3976	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
3977	{
3978	int sa, sb;
3979	sa = ((int64_t)*phigh < 0);
3980	if (sa)
3981	neg128(plow, phigh);
3982	sb = (b < 0);
3983	if (sb)
3984	b = -b;
3985	if (div64(plow, phigh, b) != 0)
3986	return 1;
3987	if (sa ^ sb) {
3988	if (*plow > (1ULL << 63))
3989	return 1;
3990	plow = - plow;
3991	} else {
3992	if (*plow >= (1ULL << 63))
3993	return 1;
3994	}
3995	if (sa)
3996	phigh = - phigh;
3997	return 0;
3998	}
3999
4000	void helper_mulq_EAX_T0(void)
4001	{
4002	uint64_t r0, r1;
4003
4004	mul64(&r0, &r1, EAX, T0);
4005	EAX = r0;
4006	EDX = r1;
4007	CC_DST = r0;
4008	CC_SRC = r1;
4009	}
4010
4011	void helper_imulq_EAX_T0(void)
4012	{
4013	uint64_t r0, r1;
4014
4015	imul64(&r0, &r1, EAX, T0);
4016	EAX = r0;
4017	EDX = r1;
4018	CC_DST = r0;
4019	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4020	}
4021
4022	void helper_imulq_T0_T1(void)
4023	{
4024	uint64_t r0, r1;
4025
4026	imul64(&r0, &r1, T0, T1);
4027	T0 = r0;
4028	CC_DST = r0;
4029	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4030	}
4031
4032	void helper_divq_EAX_T0(void)
4033	{
4034	uint64_t r0, r1;
4035	if (T0 == 0) {
4036	raise_exception(EXCP00_DIVZ);
4037	}
4038	r0 = EAX;
4039	r1 = EDX;
4040	if (div64(&r0, &r1, T0))
4041	raise_exception(EXCP00_DIVZ);
4042	EAX = r0;
4043	EDX = r1;
4044	}
4045
4046	void helper_idivq_EAX_T0(void)
4047	{
4048	uint64_t r0, r1;
4049	if (T0 == 0) {
4050	raise_exception(EXCP00_DIVZ);
4051	}
4052	r0 = EAX;
4053	r1 = EDX;
4054	if (idiv64(&r0, &r1, T0))
4055	raise_exception(EXCP00_DIVZ);
4056	EAX = r0;
4057	EDX = r1;
4058	}
4059
4060	void helper_bswapq_T0(void)
4061	{
4062	T0 = bswap64(T0);
4063	}
4064	#endif
4065
4066	void helper_hlt(void)
4067	{
4068	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
4069	env->hflags \|= HF_HALTED_MASK;
4070	env->exception_index = EXCP_HLT;
4071	cpu_loop_exit();
4072	}
4073
4074	void helper_monitor(void)
4075	{
4076	if ((uint32_t)ECX != 0)
4077	raise_exception(EXCP0D_GPF);
4078	/* XXX: store address ? */
4079	}
4080
4081	void helper_mwait(void)
4082	{
4083	if ((uint32_t)ECX != 0)
4084	raise_exception(EXCP0D_GPF);
4085	#ifdef VBOX
4086	helper_hlt();
4087	#else
4088	/* XXX: not complete but not completely erroneous */
4089	if (env->cpu_index != 0 \|\| env->next_cpu != NULL) {
4090	/* more than one CPU: do not sleep because another CPU may
4091	wake this one */
4092	} else {
4093	helper_hlt();
4094	}
4095	#endif
4096	}
4097
4098	float approx_rsqrt(float a)
4099	{
4100	return 1.0 / sqrt(a);
4101	}
4102
4103	float approx_rcp(float a)
4104	{
4105	return 1.0 / a;
4106	}
4107
4108	void update_fp_status(void)
4109	{
4110	int rnd_type;
4111
4112	/* set rounding mode */
4113	switch(env->fpuc & RC_MASK) {
4114	default:
4115	case RC_NEAR:
4116	rnd_type = float_round_nearest_even;
4117	break;
4118	case RC_DOWN:
4119	rnd_type = float_round_down;
4120	break;
4121	case RC_UP:
4122	rnd_type = float_round_up;
4123	break;
4124	case RC_CHOP:
4125	rnd_type = float_round_to_zero;
4126	break;
4127	}
4128	set_float_rounding_mode(rnd_type, &env->fp_status);
4129	#ifdef FLOATX80
4130	switch((env->fpuc >> 8) & 3) {
4131	case 0:
4132	rnd_type = 32;
4133	break;
4134	case 2:
4135	rnd_type = 64;
4136	break;
4137	case 3:
4138	default:
4139	rnd_type = 80;
4140	break;
4141	}
4142	set_floatx80_rounding_precision(rnd_type, &env->fp_status);
4143	#endif
4144	}
4145
4146	#if !defined(CONFIG_USER_ONLY)
4147
4148	#define MMUSUFFIX _mmu
4149	#define GETPC() (__builtin_return_address(0))
4150
4151	#define SHIFT 0
4152	#include "softmmu_template.h"
4153
4154	#define SHIFT 1
4155	#include "softmmu_template.h"
4156
4157	#define SHIFT 2
4158	#include "softmmu_template.h"
4159
4160	#define SHIFT 3
4161	#include "softmmu_template.h"
4162
4163	#endif
4164
4165	/* try to fill the TLB and return an exception if error. If retaddr is
4166	NULL, it means that the function was called in C code (i.e. not
4167	from generated code or from helper.c) */
4168	/* XXX: fix it to restore all registers */
4169	void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
4170	{
4171	TranslationBlock *tb;
4172	int ret;
4173	unsigned long pc;
4174	CPUX86State *saved_env;
4175
4176	/* XXX: hack to restore env in all cases, even if not called from
4177	generated code */
4178	saved_env = env;
4179	env = cpu_single_env;
4180
4181	ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
4182	if (ret) {
4183	if (retaddr) {
4184	/* now we have a real cpu fault */
4185	pc = (unsigned long)retaddr;
4186	tb = tb_find_pc(pc);
4187	if (tb) {
4188	/* the PC is inside the translated code. It means that we have
4189	a virtual CPU fault */
4190	cpu_restore_state(tb, env, pc, NULL);
4191	}
4192	}
4193	if (retaddr)
4194	raise_exception_err(env->exception_index, env->error_code);
4195	else
4196	raise_exception_err_norestore(env->exception_index, env->error_code);
4197	}
4198	env = saved_env;
4199	}
4200
4201	#ifdef VBOX
4202
4203	/**
4204	* Correctly computes the eflags.
4205	* @returns eflags.
4206	* @param env1 CPU environment.
4207	*/
4208	uint32_t raw_compute_eflags(CPUX86State *env1)
4209	{
4210	CPUX86State *savedenv = env;
4211	env = env1;
4212	uint32_t efl = compute_eflags();
4213	env = savedenv;
4214	return efl;
4215	}
4216
4217	/**
4218	* Reads byte from virtual address in guest memory area.
4219	* XXX: is it working for any addresses? swapped out pages?
4220	* @returns readed data byte.
4221	* @param env1 CPU environment.
4222	* @param pvAddr GC Virtual address.
4223	*/
4224	uint8_t read_byte(CPUX86State *env1, target_ulong addr)
4225	{
4226	CPUX86State *savedenv = env;
4227	env = env1;
4228	uint8_t u8 = ldub_kernel(addr);
4229	env = savedenv;
4230	return u8;
4231	}
4232
4233	/**
4234	* Reads byte from virtual address in guest memory area.
4235	* XXX: is it working for any addresses? swapped out pages?
4236	* @returns readed data byte.
4237	* @param env1 CPU environment.
4238	* @param pvAddr GC Virtual address.
4239	*/
4240	uint16_t read_word(CPUX86State *env1, target_ulong addr)
4241	{
4242	CPUX86State *savedenv = env;
4243	env = env1;
4244	uint16_t u16 = lduw_kernel(addr);
4245	env = savedenv;
4246	return u16;
4247	}
4248
4249	/**
4250	* Reads byte from virtual address in guest memory area.
4251	* XXX: is it working for any addresses? swapped out pages?
4252	* @returns readed data byte.
4253	* @param env1 CPU environment.
4254	* @param pvAddr GC Virtual address.
4255	*/
4256	uint32_t read_dword(CPUX86State *env1, target_ulong addr)
4257	{
4258	CPUX86State *savedenv = env;
4259	env = env1;
4260	uint32_t u32 = ldl_kernel(addr);
4261	env = savedenv;
4262	return u32;
4263	}
4264
4265	/**
4266	* Writes byte to virtual address in guest memory area.
4267	* XXX: is it working for any addresses? swapped out pages?
4268	* @returns readed data byte.
4269	* @param env1 CPU environment.
4270	* @param pvAddr GC Virtual address.
4271	* @param val byte value
4272	*/
4273	void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
4274	{
4275	CPUX86State *savedenv = env;
4276	env = env1;
4277	stb(addr, val);
4278	env = savedenv;
4279	}
4280
4281	void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
4282	{
4283	CPUX86State *savedenv = env;
4284	env = env1;
4285	stw(addr, val);
4286	env = savedenv;
4287	}
4288
4289	void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
4290	{
4291	CPUX86State *savedenv = env;
4292	env = env1;
4293	stl(addr, val);
4294	env = savedenv;
4295	}
4296
4297	/**
4298	* Correctly loads selector into segment register with updating internal
4299	* qemu data/caches.
4300	* @param env1 CPU environment.
4301	* @param seg_reg Segment register.
4302	* @param selector Selector to load.
4303	*/
4304	void sync_seg(CPUX86State *env1, int seg_reg, int selector)
4305	{
4306	CPUX86State *savedenv = env;
4307	env = env1;
4308
4309	if ( env->eflags & X86_EFL_VM
4310	\|\| !(env->cr[0] & X86_CR0_PE))
4311	{
4312	load_seg_vm(seg_reg, selector);
4313
4314	env = savedenv;
4315
4316	/* Successful sync. */
4317	env1->segs[seg_reg].newselector = 0;
4318	}
4319	else
4320	{
4321	if (setjmp(env1->jmp_env) == 0)
4322	{
4323	if (seg_reg == R_CS)
4324	{
4325	uint32_t e1, e2;
4326	load_segment(&e1, &e2, selector);
4327	cpu_x86_load_seg_cache(env, R_CS, selector,
4328	get_seg_base(e1, e2),
4329	get_seg_limit(e1, e2),
4330	e2);
4331	}
4332	else
4333	load_seg(seg_reg, selector);
4334	env = savedenv;
4335
4336	/* Successful sync. */
4337	env1->segs[seg_reg].newselector = 0;
4338	}
4339	else
4340	{
4341	env = savedenv;
4342
4343	/* Postpone sync until the guest uses the selector. */
4344	env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
4345	env1->segs[seg_reg].newselector = selector;
4346	Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
4347	}
4348	}
4349
4350	}
4351
4352
4353	/**
4354	* Correctly loads a new ldtr selector.
4355	*
4356	* @param env1 CPU environment.
4357	* @param selector Selector to load.
4358	*/
4359	void sync_ldtr(CPUX86State *env1, int selector)
4360	{
4361	CPUX86State *saved_env = env;
4362	target_ulong saved_T0 = T0;
4363	if (setjmp(env1->jmp_env) == 0)
4364	{
4365	env = env1;
4366	T0 = selector;
4367	helper_lldt_T0();
4368	T0 = saved_T0;
4369	env = saved_env;
4370	}
4371	else
4372	{
4373	T0 = saved_T0;
4374	env = saved_env;
4375	#ifdef VBOX_STRICT
4376	cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
4377	#endif
4378	}
4379	}
4380
4381	/**
4382	* Correctly loads a new tr selector.
4383	*
4384	* @param env1 CPU environment.
4385	* @param selector Selector to load.
4386	*/
4387	int sync_tr(CPUX86State *env1, int selector)
4388	{
4389	/* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
4390	SegmentCache *dt;
4391	uint32_t e1, e2;
4392	int index, type, entry_limit;
4393	target_ulong ptr;
4394	CPUX86State *saved_env = env;
4395	env = env1;
4396
4397	selector &= 0xffff;
4398	if ((selector & 0xfffc) == 0) {
4399	/* NULL selector case: invalid TR */
4400	env->tr.base = 0;
4401	env->tr.limit = 0;
4402	env->tr.flags = 0;
4403	} else {
4404	if (selector & 0x4)
4405	goto l_failure;
4406	dt = &env->gdt;
4407	index = selector & ~7;
4408	#ifdef TARGET_X86_64
4409	if (env->hflags & HF_LMA_MASK)
4410	entry_limit = 15;
4411	else
4412	#endif
4413	entry_limit = 7;
4414	if ((index + entry_limit) > dt->limit)
4415	goto l_failure;
4416	ptr = dt->base + index;
4417	e1 = ldl_kernel(ptr);
4418	e2 = ldl_kernel(ptr + 4);
4419	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
4420	if ((e2 & DESC_S_MASK) /*\|\|
4421	(type != 1 && type != 9)*/)
4422	goto l_failure;
4423	if (!(e2 & DESC_P_MASK))
4424	goto l_failure;
4425	#ifdef TARGET_X86_64
4426	if (env->hflags & HF_LMA_MASK) {
4427	uint32_t e3;
4428	e3 = ldl_kernel(ptr + 8);
4429	load_seg_cache_raw_dt(&env->tr, e1, e2);
4430	env->tr.base \|= (target_ulong)e3 << 32;
4431	} else
4432	#endif
4433	{
4434	load_seg_cache_raw_dt(&env->tr, e1, e2);
4435	}
4436	e2 \|= DESC_TSS_BUSY_MASK;
4437	stl_kernel(ptr + 4, e2);
4438	}
4439	env->tr.selector = selector;
4440
4441	env = saved_env;
4442	return 0;
4443	l_failure:
4444	AssertMsgFailed(("selector=%d\n", selector));
4445	return -1;
4446	}
4447
4448	int emulate_single_instr(CPUX86State *env1)
4449	{
4450	#if 1 /* single stepping is broken when using a static tb... feel free to figure out why. :-) */
4451	/* This has to be static because it needs to be addressible
4452	using 32-bit immediate addresses on 64-bit machines. This
4453	is dictated by the gcc code model used when building this
4454	module / op.o. Using a static here pushes the problem
4455	onto the module loader. */
4456	static TranslationBlock tb_temp;
4457	#endif
4458	TranslationBlock *tb;
4459	TranslationBlock *current;
4460	int csize;
4461	void (*gen_func)(void);
4462	uint8_t *tc_ptr;
4463	target_ulong old_eip;
4464
4465	/* ensures env is loaded in ebp! */
4466	CPUX86State *savedenv = env;
4467	env = env1;
4468
4469	RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
4470
4471	#if 1 /* see above */
4472	tc_ptr = env->pvCodeBuffer;
4473	#else
4474	tc_ptr = code_gen_ptr;
4475	#endif
4476
4477	/*
4478	* Setup temporary translation block.
4479	*/
4480	/* tb_alloc: */
4481	#if 1 /* see above */
4482	tb = &tb_temp;
4483	tb->pc = env->segs[R_CS].base + env->eip;
4484	tb->cflags = 0;
4485	#else
4486	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4487	if (!tb)
4488	{
4489	tb_flush(env);
4490	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4491	}
4492	#endif
4493
4494	/* tb_find_slow: */
4495	tb->tc_ptr = tc_ptr;
4496	tb->cs_base = env->segs[R_CS].base;
4497	tb->flags = env->hflags \| (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
4498
4499	/* Initialize the rest with sensible values. */
4500	tb->size = 0;
4501	tb->phys_hash_next = NULL;
4502	tb->page_next[0] = NULL;
4503	tb->page_next[1] = NULL;
4504	tb->page_addr[0] = 0;
4505	tb->page_addr[1] = 0;
4506	tb->tb_next_offset[0] = 0xffff;
4507	tb->tb_next_offset[1] = 0xffff;
4508	tb->tb_next[0] = 0xffff;
4509	tb->tb_next[1] = 0xffff;
4510	tb->jmp_next[0] = NULL;
4511	tb->jmp_next[1] = NULL;
4512	tb->jmp_first = NULL;
4513
4514	current = env->current_tb;
4515	env->current_tb = NULL;
4516
4517	/*
4518	* Translate only one instruction.
4519	*/
4520	ASMAtomicOrU32(&env->state, CPU_EMULATE_SINGLE_INSTR);
4521	if (cpu_gen_code(env, tb, env->cbCodeBuffer, &csize) < 0)
4522	{
4523	AssertFailed();
4524	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4525	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4526	env = savedenv;
4527	return -1;
4528	}
4529	#ifdef DEBUG
4530	if(csize > env->cbCodeBuffer)
4531	{
4532	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4533	AssertFailed();
4534	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4535	env = savedenv;
4536	return -1;
4537	}
4538	if (tb->tc_ptr != tc_ptr)
4539	{
4540	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4541	AssertFailed();
4542	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4543	env = savedenv;
4544	return -1;
4545	}
4546	#endif
4547	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4548
4549	/* tb_link_phys: */
4550	tb->jmp_first = (TranslationBlock *)((intptr_t)tb \| 2);
4551	Assert(tb->jmp_next[0] == NULL); Assert(tb->jmp_next[1] == NULL);
4552	if (tb->tb_next_offset[0] != 0xffff)
4553	tb_set_jmp_target(tb, 0, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[0]));
4554	if (tb->tb_next_offset[1] != 0xffff)
4555	tb_set_jmp_target(tb, 1, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[1]));
4556
4557	/*
4558	* Execute it using emulation
4559	*/
4560	old_eip = env->eip;
4561	gen_func = (void *)tb->tc_ptr;
4562	env->current_tb = tb;
4563
4564	// eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
4565	// perhaps not a very safe hack
4566	while(old_eip == env->eip)
4567	{
4568	gen_func();
4569	/*
4570	* Exit once we detect an external interrupt and interrupts are enabled
4571	*/
4572	if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT\|CPU_INTERRUPT_EXTERNAL_TIMER)) \|\|
4573	( (env->eflags & IF_MASK) &&
4574	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
4575	(env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
4576	{
4577	break;
4578	}
4579	}
4580	env->current_tb = current;
4581
4582	Assert(tb->phys_hash_next == NULL);
4583	Assert(tb->page_next[0] == NULL);
4584	Assert(tb->page_next[1] == NULL);
4585	Assert(tb->page_addr[0] == 0);
4586	Assert(tb->page_addr[1] == 0);
4587	/*
4588	Assert(tb->tb_next_offset[0] == 0xffff);
4589	Assert(tb->tb_next_offset[1] == 0xffff);
4590	Assert(tb->tb_next[0] == 0xffff);
4591	Assert(tb->tb_next[1] == 0xffff);
4592	Assert(tb->jmp_next[0] == NULL);
4593	Assert(tb->jmp_next[1] == NULL);
4594	Assert(tb->jmp_first == NULL); */
4595
4596	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4597
4598	/*
4599	* Execute the next instruction when we encounter instruction fusing.
4600	*/
4601	if (env->hflags & HF_INHIBIT_IRQ_MASK)
4602	{
4603	Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK) at %VGv\n", env->eip));
4604	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
4605	emulate_single_instr(env);
4606	}
4607
4608	env = savedenv;
4609	return 0;
4610	}
4611
4612	int get_ss_esp_from_tss_raw(CPUX86State env1, uint32_t ss_ptr,
4613	uint32_t *esp_ptr, int dpl)
4614	{
4615	int type, index, shift;
4616
4617	CPUX86State *savedenv = env;
4618	env = env1;
4619
4620	if (!(env->tr.flags & DESC_P_MASK))
4621	cpu_abort(env, "invalid tss");
4622	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
4623	if ((type & 7) != 1)
4624	cpu_abort(env, "invalid tss type %d", type);
4625	shift = type >> 3;
4626	index = (dpl * 4 + 2) << shift;
4627	if (index + (4 << shift) - 1 > env->tr.limit)
4628	{
4629	env = savedenv;
4630	return 0;
4631	}
4632	//raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
4633
4634	if (shift == 0) {
4635	*esp_ptr = lduw_kernel(env->tr.base + index);
4636	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
4637	} else {
4638	*esp_ptr = ldl_kernel(env->tr.base + index);
4639	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
4640	}
4641
4642	env = savedenv;
4643	return 1;
4644	}
4645
4646	//*****************************************************************************
4647	// Needs to be at the bottom of the file (overriding macros)
4648
4649	static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4650	{
4651	return (CPU86_LDouble )ptr;
4652	}
4653
4654	static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4655	{
4656	(CPU86_LDouble )ptr = f;
4657	}
4658
4659	#undef stw
4660	#undef stl
4661	#undef stq
4662	#define stw(a,b) (uint16_t )(a) = (uint16_t)(b)
4663	#define stl(a,b) (uint32_t )(a) = (uint32_t)(b)
4664	#define stq(a,b) (uint64_t )(a) = (uint64_t)(b)
4665	#define data64 0
4666
4667	//*****************************************************************************
4668	void restore_raw_fp_state(CPUX86State env, uint8_t ptr)
4669	{
4670	int fpus, fptag, i, nb_xmm_regs;
4671	CPU86_LDouble tmp;
4672	uint8_t *addr;
4673
4674	if (env->cpuid_features & CPUID_FXSR)
4675	{
4676	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4677	fptag = 0;
4678	for(i = 0; i < 8; i++) {
4679	fptag \|= (env->fptags[i] << i);
4680	}
4681	stw(ptr, env->fpuc);
4682	stw(ptr + 2, fpus);
4683	stw(ptr + 4, fptag ^ 0xff);
4684
4685	addr = ptr + 0x20;
4686	for(i = 0;i < 8; i++) {
4687	tmp = ST(i);
4688	helper_fstt_raw(tmp, addr);
4689	addr += 16;
4690	}
4691
4692	if (env->cr[4] & CR4_OSFXSR_MASK) {
4693	/* XXX: finish it */
4694	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4695	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4696	nb_xmm_regs = 8 << data64;
4697	addr = ptr + 0xa0;
4698	for(i = 0; i < nb_xmm_regs; i++) {
4699	#if __GNUC__ < 4
4700	stq(addr, env->xmm_regs[i].XMM_Q(0));
4701	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4702	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4703	stl(addr, env->xmm_regs[i].XMM_L(0));
4704	stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4705	stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4706	stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4707	#endif
4708	addr += 16;
4709	}
4710	}
4711	}
4712	else
4713	{
4714	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4715	int fptag;
4716
4717	fp->FCW = env->fpuc;
4718	fp->FSW = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4719	fptag = 0;
4720	for (i=7; i>=0; i--) {
4721	fptag <<= 2;
4722	if (env->fptags[i]) {
4723	fptag \|= 3;
4724	} else {
4725	/* the FPU automatically computes it */
4726	}
4727	}
4728	fp->FTW = fptag;
4729
4730	for(i = 0;i < 8; i++) {
4731	tmp = ST(i);
4732	helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4733	}
4734	}
4735	}
4736
4737	//*****************************************************************************
4738	#undef lduw
4739	#undef ldl
4740	#undef ldq
4741	#define lduw(a) (uint16_t )(a)
4742	#define ldl(a) (uint32_t )(a)
4743	#define ldq(a) (uint64_t )(a)
4744	//*****************************************************************************
4745	void save_raw_fp_state(CPUX86State env, uint8_t ptr)
4746	{
4747	int i, fpus, fptag, nb_xmm_regs;
4748	CPU86_LDouble tmp;
4749	uint8_t *addr;
4750
4751	if (env->cpuid_features & CPUID_FXSR)
4752	{
4753	env->fpuc = lduw(ptr);
4754	fpus = lduw(ptr + 2);
4755	fptag = lduw(ptr + 4);
4756	env->fpstt = (fpus >> 11) & 7;
4757	env->fpus = fpus & ~0x3800;
4758	fptag ^= 0xff;
4759	for(i = 0;i < 8; i++) {
4760	env->fptags[i] = ((fptag >> i) & 1);
4761	}
4762
4763	addr = ptr + 0x20;
4764	for(i = 0;i < 8; i++) {
4765	tmp = helper_fldt_raw(addr);
4766	ST(i) = tmp;
4767	addr += 16;
4768	}
4769
4770	if (env->cr[4] & CR4_OSFXSR_MASK) {
4771	/* XXX: finish it, endianness */
4772	env->mxcsr = ldl(ptr + 0x18);
4773	//ldl(ptr + 0x1c);
4774	nb_xmm_regs = 8 << data64;
4775	addr = ptr + 0xa0;
4776	for(i = 0; i < nb_xmm_regs; i++) {
4777	#if HC_ARCH_BITS == 32
4778	/* this is a workaround for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35135 */
4779	env->xmm_regs[i].XMM_L(0) = ldl(addr);
4780	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
4781	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
4782	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
4783	#else
4784	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4785	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4786	#endif
4787	addr += 16;
4788	}
4789	}
4790	}
4791	else
4792	{
4793	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4794	int fptag, j;
4795
4796	env->fpuc = fp->FCW;
4797	env->fpstt = (fp->FSW >> 11) & 7;
4798	env->fpus = fp->FSW & ~0x3800;
4799	fptag = fp->FTW;
4800	for(i = 0;i < 8; i++) {
4801	env->fptags[i] = ((fptag & 3) == 3);
4802	fptag >>= 2;
4803	}
4804	j = env->fpstt;
4805	for(i = 0;i < 8; i++) {
4806	tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4807	ST(i) = tmp;
4808	}
4809	}
4810	}
4811	//*****************************************************************************
4812	//*****************************************************************************
4813
4814	#endif /* VBOX */
4815

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source: vbox/trunk/src/recompiler/target-i386/helper.c@ 12240

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