helper.c@ 13013

Last change on this file since 13013 was 13013, checked in by vboxsync, 16 years ago
infrastructure work for X2APIC support
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1	/*
2	* i386 helpers
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/*
22	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
24	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25	* a choice of LGPL license versions is made available with the language indicating
26	* that LGPLv2 or any later version may be used, or where a choice of which version
27	* of the LGPL is applied is otherwise unspecified.
28	*/
29	#ifdef VBOX
30	# include <VBox/err.h>
31	#endif
32	#include "exec.h"
33
34	//#define DEBUG_PCALL
35
36	#if 0
37	#define raise_exception_err(a, b)\
38	do {\
39	if (logfile)\
40	fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
41	(raise_exception_err)(a, b);\
42	} while (0)
43	#endif
44
45	const uint8_t parity_table[256] = {
46	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
56	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
58	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
59	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
61	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
66	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
68	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
69	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
70	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
71	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
72	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
73	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
74	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
75	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
76	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
77	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
78	};
79
80	/* modulo 17 table */
81	const uint8_t rclw_table[32] = {
82	0, 1, 2, 3, 4, 5, 6, 7,
83	8, 9,10,11,12,13,14,15,
84	16, 0, 1, 2, 3, 4, 5, 6,
85	7, 8, 9,10,11,12,13,14,
86	};
87
88	/* modulo 9 table */
89	const uint8_t rclb_table[32] = {
90	0, 1, 2, 3, 4, 5, 6, 7,
91	8, 0, 1, 2, 3, 4, 5, 6,
92	7, 8, 0, 1, 2, 3, 4, 5,
93	6, 7, 8, 0, 1, 2, 3, 4,
94	};
95
96	const CPU86_LDouble f15rk[7] =
97	{
98	0.00000000000000000000L,
99	1.00000000000000000000L,
100	3.14159265358979323851L, /pi/
101	0.30102999566398119523L, /lg2/
102	0.69314718055994530943L, /ln2/
103	1.44269504088896340739L, /l2e/
104	3.32192809488736234781L, /l2t/
105	};
106
107	/* thread support */
108
109	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
110
111	void cpu_lock(void)
112	{
113	spin_lock(&global_cpu_lock);
114	}
115
116	void cpu_unlock(void)
117	{
118	spin_unlock(&global_cpu_lock);
119	}
120
121	void cpu_loop_exit(void)
122	{
123	/* NOTE: the register at this point must be saved by hand because
124	longjmp restore them */
125	regs_to_env();
126	longjmp(env->jmp_env, 1);
127	}
128
129	/* return non zero if error */
130	static inline int load_segment(uint32_t e1_ptr, uint32_t e2_ptr,
131	int selector)
132	{
133	SegmentCache *dt;
134	int index;
135	target_ulong ptr;
136
137	if (selector & 0x4)
138	dt = &env->ldt;
139	else
140	dt = &env->gdt;
141	index = selector & ~7;
142	if ((index + 7) > dt->limit)
143	return -1;
144	ptr = dt->base + index;
145	*e1_ptr = ldl_kernel(ptr);
146	*e2_ptr = ldl_kernel(ptr + 4);
147	return 0;
148	}
149
150	static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
151	{
152	unsigned int limit;
153	limit = (e1 & 0xffff) \| (e2 & 0x000f0000);
154	if (e2 & DESC_G_MASK)
155	limit = (limit << 12) \| 0xfff;
156	return limit;
157	}
158
159	static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
160	{
161	return ((e1 >> 16) \| ((e2 & 0xff) << 16) \| (e2 & 0xff000000));
162	}
163
164	static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
165	{
166	sc->base = get_seg_base(e1, e2);
167	sc->limit = get_seg_limit(e1, e2);
168	sc->flags = e2;
169	}
170
171	/* init the segment cache in vm86 mode. */
172	static inline void load_seg_vm(int seg, int selector)
173	{
174	selector &= 0xffff;
175	cpu_x86_load_seg_cache(env, seg, selector,
176	(selector << 4), 0xffff, 0);
177	}
178
179	static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
180	uint32_t *esp_ptr, int dpl)
181	{
182	int type, index, shift;
183
184	#if 0
185	{
186	int i;
187	printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
188	for(i=0;i<env->tr.limit;i++) {
189	printf("%02x ", env->tr.base[i]);
190	if ((i & 7) == 7) printf("\n");
191	}
192	printf("\n");
193	}
194	#endif
195
196	if (!(env->tr.flags & DESC_P_MASK))
197	cpu_abort(env, "invalid tss");
198	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
199	if ((type & 7) != 1)
200	cpu_abort(env, "invalid tss type %d", type);
201	shift = type >> 3;
202	index = (dpl * 4 + 2) << shift;
203	if (index + (4 << shift) - 1 > env->tr.limit)
204	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
205	if (shift == 0) {
206	*esp_ptr = lduw_kernel(env->tr.base + index);
207	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
208	} else {
209	*esp_ptr = ldl_kernel(env->tr.base + index);
210	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
211	}
212	}
213
214	/* XXX: merge with load_seg() */
215	static void tss_load_seg(int seg_reg, int selector)
216	{
217	uint32_t e1, e2;
218	int rpl, dpl, cpl;
219
220	if ((selector & 0xfffc) != 0) {
221	if (load_segment(&e1, &e2, selector) != 0)
222	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
223	if (!(e2 & DESC_S_MASK))
224	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
225	rpl = selector & 3;
226	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
227	cpl = env->hflags & HF_CPL_MASK;
228	if (seg_reg == R_CS) {
229	if (!(e2 & DESC_CS_MASK))
230	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231	/* XXX: is it correct ? */
232	if (dpl != rpl)
233	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
234	if ((e2 & DESC_C_MASK) && dpl > rpl)
235	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
236	} else if (seg_reg == R_SS) {
237	/* SS must be writable data */
238	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
239	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
240	if (dpl != cpl \|\| dpl != rpl)
241	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
242	} else {
243	/* not readable code */
244	if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
245	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
246	/* if data or non conforming code, checks the rights */
247	if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
248	if (dpl < cpl \|\| dpl < rpl)
249	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
250	}
251	}
252	if (!(e2 & DESC_P_MASK))
253	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
254	cpu_x86_load_seg_cache(env, seg_reg, selector,
255	get_seg_base(e1, e2),
256	get_seg_limit(e1, e2),
257	e2);
258	} else {
259	if (seg_reg == R_SS \|\| seg_reg == R_CS)
260	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
261	}
262	}
263
264	#define SWITCH_TSS_JMP 0
265	#define SWITCH_TSS_IRET 1
266	#define SWITCH_TSS_CALL 2
267
268	/* XXX: restore CPU state in registers (PowerPC case) */
269	static void switch_tss(int tss_selector,
270	uint32_t e1, uint32_t e2, int source,
271	uint32_t next_eip)
272	{
273	int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
274	target_ulong tss_base;
275	uint32_t new_regs[8], new_segs[6];
276	uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
277	uint32_t old_eflags, eflags_mask;
278	SegmentCache *dt;
279	int index;
280	target_ulong ptr;
281
282	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
283	#ifdef DEBUG_PCALL
284	if (loglevel & CPU_LOG_PCALL)
285	fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
286	#endif
287
288	#if defined(VBOX) && defined(DEBUG)
289	printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
290	#endif
291
292	/* if task gate, we read the TSS segment and we load it */
293	if (type == 5) {
294	if (!(e2 & DESC_P_MASK))
295	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
296	tss_selector = e1 >> 16;
297	if (tss_selector & 4)
298	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
299	if (load_segment(&e1, &e2, tss_selector) != 0)
300	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
301	if (e2 & DESC_S_MASK)
302	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
303	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
304	if ((type & 7) != 1)
305	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
306	}
307
308	if (!(e2 & DESC_P_MASK))
309	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
310
311	if (type & 8)
312	tss_limit_max = 103;
313	else
314	tss_limit_max = 43;
315	tss_limit = get_seg_limit(e1, e2);
316	tss_base = get_seg_base(e1, e2);
317	if ((tss_selector & 4) != 0 \|\|
318	tss_limit < tss_limit_max)
319	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
320	old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
321	if (old_type & 8)
322	old_tss_limit_max = 103;
323	else
324	old_tss_limit_max = 43;
325
326	/* read all the registers from the new TSS */
327	if (type & 8) {
328	/* 32 bit */
329	new_cr3 = ldl_kernel(tss_base + 0x1c);
330	new_eip = ldl_kernel(tss_base + 0x20);
331	new_eflags = ldl_kernel(tss_base + 0x24);
332	for(i = 0; i < 8; i++)
333	new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
334	for(i = 0; i < 6; i++)
335	new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
336	new_ldt = lduw_kernel(tss_base + 0x60);
337	new_trap = ldl_kernel(tss_base + 0x64);
338	} else {
339	/* 16 bit */
340	new_cr3 = 0;
341	new_eip = lduw_kernel(tss_base + 0x0e);
342	new_eflags = lduw_kernel(tss_base + 0x10);
343	for(i = 0; i < 8; i++)
344	new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) \| 0xffff0000;
345	for(i = 0; i < 4; i++)
346	new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
347	new_ldt = lduw_kernel(tss_base + 0x2a);
348	new_segs[R_FS] = 0;
349	new_segs[R_GS] = 0;
350	new_trap = 0;
351	}
352
353	/* NOTE: we must avoid memory exceptions during the task switch,
354	so we make dummy accesses before */
355	/* XXX: it can still fail in some cases, so a bigger hack is
356	necessary to valid the TLB after having done the accesses */
357
358	v1 = ldub_kernel(env->tr.base);
359	v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
360	stb_kernel(env->tr.base, v1);
361	stb_kernel(env->tr.base + old_tss_limit_max, v2);
362
363	/* clear busy bit (it is restartable) */
364	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_IRET) {
365	target_ulong ptr;
366	uint32_t e2;
367	ptr = env->gdt.base + (env->tr.selector & ~7);
368	e2 = ldl_kernel(ptr + 4);
369	e2 &= ~DESC_TSS_BUSY_MASK;
370	stl_kernel(ptr + 4, e2);
371	}
372	old_eflags = compute_eflags();
373	if (source == SWITCH_TSS_IRET)
374	old_eflags &= ~NT_MASK;
375
376	/* save the current state in the old TSS */
377	if (type & 8) {
378	/* 32 bit */
379	stl_kernel(env->tr.base + 0x20, next_eip);
380	stl_kernel(env->tr.base + 0x24, old_eflags);
381	stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
382	stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
383	stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
384	stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
385	stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
386	stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
387	stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
388	stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
389	for(i = 0; i < 6; i++)
390	stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
391	#if defined(VBOX) && defined(DEBUG)
392	printf("TSS 32 bits switch\n");
393	printf("Saving CS=%08X\n", env->segs[R_CS].selector);
394	#endif
395	} else {
396	/* 16 bit */
397	stw_kernel(env->tr.base + 0x0e, next_eip);
398	stw_kernel(env->tr.base + 0x10, old_eflags);
399	stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
400	stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
401	stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
402	stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
403	stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
404	stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
405	stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
406	stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
407	for(i = 0; i < 4; i++)
408	stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
409	}
410
411	/* now if an exception occurs, it will occurs in the next task
412	context */
413
414	if (source == SWITCH_TSS_CALL) {
415	stw_kernel(tss_base, env->tr.selector);
416	new_eflags \|= NT_MASK;
417	}
418
419	/* set busy bit */
420	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_CALL) {
421	target_ulong ptr;
422	uint32_t e2;
423	ptr = env->gdt.base + (tss_selector & ~7);
424	e2 = ldl_kernel(ptr + 4);
425	e2 \|= DESC_TSS_BUSY_MASK;
426	stl_kernel(ptr + 4, e2);
427	}
428
429	/* set the new CPU state */
430	/* from this point, any exception which occurs can give problems */
431	env->cr[0] \|= CR0_TS_MASK;
432	env->hflags \|= HF_TS_MASK;
433	env->tr.selector = tss_selector;
434	env->tr.base = tss_base;
435	env->tr.limit = tss_limit;
436	env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
437
438	if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
439	cpu_x86_update_cr3(env, new_cr3);
440	}
441
442	/* load all registers without an exception, then reload them with
443	possible exception */
444	env->eip = new_eip;
445	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \|
446	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK;
447	if (!(type & 8))
448	eflags_mask &= 0xffff;
449	load_eflags(new_eflags, eflags_mask);
450	/* XXX: what to do in 16 bit case ? */
451	EAX = new_regs[0];
452	ECX = new_regs[1];
453	EDX = new_regs[2];
454	EBX = new_regs[3];
455	ESP = new_regs[4];
456	EBP = new_regs[5];
457	ESI = new_regs[6];
458	EDI = new_regs[7];
459	if (new_eflags & VM_MASK) {
460	for(i = 0; i < 6; i++)
461	load_seg_vm(i, new_segs[i]);
462	/* in vm86, CPL is always 3 */
463	cpu_x86_set_cpl(env, 3);
464	} else {
465	/* CPL is set the RPL of CS */
466	cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
467	/* first just selectors as the rest may trigger exceptions */
468	for(i = 0; i < 6; i++)
469	cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
470	}
471
472	env->ldt.selector = new_ldt & ~4;
473	env->ldt.base = 0;
474	env->ldt.limit = 0;
475	env->ldt.flags = 0;
476
477	/* load the LDT */
478	if (new_ldt & 4)
479	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
480
481	if ((new_ldt & 0xfffc) != 0) {
482	dt = &env->gdt;
483	index = new_ldt & ~7;
484	if ((index + 7) > dt->limit)
485	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486	ptr = dt->base + index;
487	e1 = ldl_kernel(ptr);
488	e2 = ldl_kernel(ptr + 4);
489	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
490	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
491	if (!(e2 & DESC_P_MASK))
492	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
493	load_seg_cache_raw_dt(&env->ldt, e1, e2);
494	}
495
496	/* load the segments */
497	if (!(new_eflags & VM_MASK)) {
498	tss_load_seg(R_CS, new_segs[R_CS]);
499	tss_load_seg(R_SS, new_segs[R_SS]);
500	tss_load_seg(R_ES, new_segs[R_ES]);
501	tss_load_seg(R_DS, new_segs[R_DS]);
502	tss_load_seg(R_FS, new_segs[R_FS]);
503	tss_load_seg(R_GS, new_segs[R_GS]);
504	}
505
506	/* check that EIP is in the CS segment limits */
507	if (new_eip > env->segs[R_CS].limit) {
508	/* XXX: different exception if CALL ? */
509	raise_exception_err(EXCP0D_GPF, 0);
510	}
511	}
512
513	/* check if Port I/O is allowed in TSS */
514	static inline void check_io(int addr, int size)
515	{
516	int io_offset, val, mask;
517
518	/* TSS must be a valid 32 bit one */
519	if (!(env->tr.flags & DESC_P_MASK) \|\|
520	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
521	env->tr.limit < 103)
522	goto fail;
523	io_offset = lduw_kernel(env->tr.base + 0x66);
524	io_offset += (addr >> 3);
525	/* Note: the check needs two bytes */
526	if ((io_offset + 1) > env->tr.limit)
527	goto fail;
528	val = lduw_kernel(env->tr.base + io_offset);
529	val >>= (addr & 7);
530	mask = (1 << size) - 1;
531	/* all bits must be zero to allow the I/O */
532	if ((val & mask) != 0) {
533	fail:
534	raise_exception_err(EXCP0D_GPF, 0);
535	}
536	}
537
538	void check_iob_T0(void)
539	{
540	check_io(T0, 1);
541	}
542
543	void check_iow_T0(void)
544	{
545	check_io(T0, 2);
546	}
547
548	void check_iol_T0(void)
549	{
550	check_io(T0, 4);
551	}
552
553	void check_iob_DX(void)
554	{
555	check_io(EDX & 0xffff, 1);
556	}
557
558	void check_iow_DX(void)
559	{
560	check_io(EDX & 0xffff, 2);
561	}
562
563	void check_iol_DX(void)
564	{
565	check_io(EDX & 0xffff, 4);
566	}
567
568	static inline unsigned int get_sp_mask(unsigned int e2)
569	{
570	if (e2 & DESC_B_MASK)
571	return 0xffffffff;
572	else
573	return 0xffff;
574	}
575
576	#ifdef TARGET_X86_64
577	#define SET_ESP(val, sp_mask)\
578	do {\
579	if ((sp_mask) == 0xffff)\
580	ESP = (ESP & ~0xffff) \| ((val) & 0xffff);\
581	else if ((sp_mask) == 0xffffffffLL)\
582	ESP = (uint32_t)(val);\
583	else\
584	ESP = (val);\
585	} while (0)
586	#else
587	#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) \| ((val) & (sp_mask))
588	#endif
589
590	/* XXX: add a is_user flag to have proper security support */
591	#define PUSHW(ssp, sp, sp_mask, val)\
592	{\
593	sp -= 2;\
594	stw_kernel((ssp) + (sp & (sp_mask)), (val));\
595	}
596
597	#define PUSHL(ssp, sp, sp_mask, val)\
598	{\
599	sp -= 4;\
600	stl_kernel((ssp) + (sp & (sp_mask)), (val));\
601	}
602
603	#define POPW(ssp, sp, sp_mask, val)\
604	{\
605	val = lduw_kernel((ssp) + (sp & (sp_mask)));\
606	sp += 2;\
607	}
608
609	#define POPL(ssp, sp, sp_mask, val)\
610	{\
611	val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
612	sp += 4;\
613	}
614
615	/* protected mode interrupt */
616	static void do_interrupt_protected(int intno, int is_int, int error_code,
617	unsigned int next_eip, int is_hw)
618	{
619	SegmentCache *dt;
620	target_ulong ptr, ssp;
621	int type, dpl, selector, ss_dpl, cpl;
622	int has_error_code, new_stack, shift;
623	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
624	uint32_t old_eip, sp_mask;
625
626	#ifdef VBOX
627	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
628	cpu_loop_exit();
629	#endif
630
631	has_error_code = 0;
632	if (!is_int && !is_hw) {
633	switch(intno) {
634	case 8:
635	case 10:
636	case 11:
637	case 12:
638	case 13:
639	case 14:
640	case 17:
641	has_error_code = 1;
642	break;
643	}
644	}
645	if (is_int)
646	old_eip = next_eip;
647	else
648	old_eip = env->eip;
649
650	dt = &env->idt;
651	if (intno * 8 + 7 > dt->limit)
652	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
653	ptr = dt->base + intno * 8;
654	e1 = ldl_kernel(ptr);
655	e2 = ldl_kernel(ptr + 4);
656	/* check gate type */
657	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
658	switch(type) {
659	case 5: /* task gate */
660	/* must do that check here to return the correct error code */
661	if (!(e2 & DESC_P_MASK))
662	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
663	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
664	if (has_error_code) {
665	int type;
666	uint32_t mask;
667	/* push the error code */
668	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
669	shift = type >> 3;
670	if (env->segs[R_SS].flags & DESC_B_MASK)
671	mask = 0xffffffff;
672	else
673	mask = 0xffff;
674	esp = (ESP - (2 << shift)) & mask;
675	ssp = env->segs[R_SS].base + esp;
676	if (shift)
677	stl_kernel(ssp, error_code);
678	else
679	stw_kernel(ssp, error_code);
680	SET_ESP(esp, mask);
681	}
682	return;
683	case 6: /* 286 interrupt gate */
684	case 7: /* 286 trap gate */
685	case 14: /* 386 interrupt gate */
686	case 15: /* 386 trap gate */
687	break;
688	default:
689	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
690	break;
691	}
692	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
693	cpl = env->hflags & HF_CPL_MASK;
694	/* check privledge if software int */
695	if (is_int && dpl < cpl)
696	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
697	/* check valid bit */
698	if (!(e2 & DESC_P_MASK))
699	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
700	selector = e1 >> 16;
701	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
702	if ((selector & 0xfffc) == 0)
703	raise_exception_err(EXCP0D_GPF, 0);
704
705	if (load_segment(&e1, &e2, selector) != 0)
706	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
707	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
708	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
709	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
710	if (dpl > cpl)
711	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
712	if (!(e2 & DESC_P_MASK))
713	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
714	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
715	/* to inner priviledge */
716	get_ss_esp_from_tss(&ss, &esp, dpl);
717	if ((ss & 0xfffc) == 0)
718	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
719	if ((ss & 3) != dpl)
720	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
721	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
722	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
723	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
724	if (ss_dpl != dpl)
725	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
726	if (!(ss_e2 & DESC_S_MASK) \|\|
727	(ss_e2 & DESC_CS_MASK) \|\|
728	!(ss_e2 & DESC_W_MASK))
729	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
730	if (!(ss_e2 & DESC_P_MASK))
731	#ifdef VBOX /* See page 3-477 of 253666.pdf */
732	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
733	#else
734	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
735	#endif
736	new_stack = 1;
737	sp_mask = get_sp_mask(ss_e2);
738	ssp = get_seg_base(ss_e1, ss_e2);
739	#if defined(VBOX) && defined(DEBUG)
740	printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
741	#endif
742	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
743	/* to same priviledge */
744	if (env->eflags & VM_MASK)
745	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
746	new_stack = 0;
747	sp_mask = get_sp_mask(env->segs[R_SS].flags);
748	ssp = env->segs[R_SS].base;
749	esp = ESP;
750	dpl = cpl;
751	} else {
752	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
753	new_stack = 0; /* avoid warning */
754	sp_mask = 0; /* avoid warning */
755	ssp = 0; /* avoid warning */
756	esp = 0; /* avoid warning */
757	}
758
759	shift = type >> 3;
760
761	#if 0
762	/* XXX: check that enough room is available */
763	push_size = 6 + (new_stack << 2) + (has_error_code << 1);
764	if (env->eflags & VM_MASK)
765	push_size += 8;
766	push_size <<= shift;
767	#endif
768	if (shift == 1) {
769	if (new_stack) {
770	if (env->eflags & VM_MASK) {
771	PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
772	PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
773	PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
774	PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
775	}
776	PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
777	PUSHL(ssp, esp, sp_mask, ESP);
778	}
779	PUSHL(ssp, esp, sp_mask, compute_eflags());
780	PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
781	PUSHL(ssp, esp, sp_mask, old_eip);
782	if (has_error_code) {
783	PUSHL(ssp, esp, sp_mask, error_code);
784	}
785	} else {
786	if (new_stack) {
787	if (env->eflags & VM_MASK) {
788	PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
789	PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
790	PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
791	PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
792	}
793	PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
794	PUSHW(ssp, esp, sp_mask, ESP);
795	}
796	PUSHW(ssp, esp, sp_mask, compute_eflags());
797	PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
798	PUSHW(ssp, esp, sp_mask, old_eip);
799	if (has_error_code) {
800	PUSHW(ssp, esp, sp_mask, error_code);
801	}
802	}
803
804	if (new_stack) {
805	if (env->eflags & VM_MASK) {
806	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
807	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
808	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
809	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
810	}
811	ss = (ss & ~3) \| dpl;
812	cpu_x86_load_seg_cache(env, R_SS, ss,
813	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
814	}
815	SET_ESP(esp, sp_mask);
816
817	selector = (selector & ~3) \| dpl;
818	cpu_x86_load_seg_cache(env, R_CS, selector,
819	get_seg_base(e1, e2),
820	get_seg_limit(e1, e2),
821	e2);
822	cpu_x86_set_cpl(env, dpl);
823	env->eip = offset;
824
825	/* interrupt gate clear IF mask */
826	if ((type & 1) == 0) {
827	env->eflags &= ~IF_MASK;
828	}
829	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
830	}
831
832	#ifdef VBOX
833
834	/* check if VME interrupt redirection is enabled in TSS */
835	static inline bool is_vme_irq_redirected(int intno)
836	{
837	int io_offset, intredir_offset;
838	unsigned char val, mask;
839
840	/* TSS must be a valid 32 bit one */
841	if (!(env->tr.flags & DESC_P_MASK) \|\|
842	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
843	env->tr.limit < 103)
844	goto fail;
845	io_offset = lduw_kernel(env->tr.base + 0x66);
846	/* the virtual interrupt redirection bitmap is located below the io bitmap */
847	intredir_offset = io_offset - 0x20;
848
849	intredir_offset += (intno >> 3);
850	if ((intredir_offset) > env->tr.limit)
851	goto fail;
852
853	val = ldub_kernel(env->tr.base + intredir_offset);
854	mask = 1 << (unsigned char)(intno & 7);
855
856	/* bit set means no redirection. */
857	if ((val & mask) != 0) {
858	return false;
859	}
860	return true;
861
862	fail:
863	raise_exception_err(EXCP0D_GPF, 0);
864	return true;
865	}
866
867	/* V86 mode software interrupt with CR4.VME=1 */
868	static void do_soft_interrupt_vme(int intno, int error_code, unsigned int next_eip)
869	{
870	target_ulong ptr, ssp;
871	int selector;
872	uint32_t offset, esp;
873	uint32_t old_cs, old_eflags;
874	uint32_t iopl;
875
876	iopl = ((env->eflags >> IOPL_SHIFT) & 3);
877
878	if (!is_vme_irq_redirected(intno))
879	{
880	if (iopl == 3)
881	/* normal protected mode handler call */
882	return do_interrupt_protected(intno, 1, error_code, next_eip, 0);
883	else
884	raise_exception_err(EXCP0D_GPF, 0);
885	}
886
887	/* virtual mode idt is at linear address 0 */
888	ptr = 0 + intno * 4;
889	offset = lduw_kernel(ptr);
890	selector = lduw_kernel(ptr + 2);
891	esp = ESP;
892	ssp = env->segs[R_SS].base;
893	old_cs = env->segs[R_CS].selector;
894
895	old_eflags = compute_eflags();
896	if (iopl < 3)
897	{
898	/* copy VIF into IF and set IOPL to 3 */
899	if (env->eflags & VIF_MASK)
900	old_eflags \|= IF_MASK;
901	else
902	old_eflags &= ~IF_MASK;
903
904	old_eflags \|= (3 << IOPL_SHIFT);
905	}
906
907	/* XXX: use SS segment size ? */
908	PUSHW(ssp, esp, 0xffff, old_eflags);
909	PUSHW(ssp, esp, 0xffff, old_cs);
910	PUSHW(ssp, esp, 0xffff, next_eip);
911
912	/* update processor state */
913	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
914	env->eip = offset;
915	env->segs[R_CS].selector = selector;
916	env->segs[R_CS].base = (selector << 4);
917	env->eflags &= ~(TF_MASK \| RF_MASK);
918
919	if (iopl < 3)
920	env->eflags &= ~VIF_MASK;
921	else
922	env->eflags &= ~IF_MASK;
923	}
924	#endif /* VBOX */
925
926	#ifdef TARGET_X86_64
927
928	#define PUSHQ(sp, val)\
929	{\
930	sp -= 8;\
931	stq_kernel(sp, (val));\
932	}
933
934	#define POPQ(sp, val)\
935	{\
936	val = ldq_kernel(sp);\
937	sp += 8;\
938	}
939
940	static inline target_ulong get_rsp_from_tss(int level)
941	{
942	int index;
943
944	#if 0
945	printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
946	env->tr.base, env->tr.limit);
947	#endif
948
949	if (!(env->tr.flags & DESC_P_MASK))
950	cpu_abort(env, "invalid tss");
951	index = 8 * level + 4;
952	if ((index + 7) > env->tr.limit)
953	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
954	return ldq_kernel(env->tr.base + index);
955	}
956
957	/* 64 bit interrupt */
958	static void do_interrupt64(int intno, int is_int, int error_code,
959	target_ulong next_eip, int is_hw)
960	{
961	SegmentCache *dt;
962	target_ulong ptr;
963	int type, dpl, selector, cpl, ist;
964	int has_error_code, new_stack;
965	uint32_t e1, e2, e3, ss;
966	target_ulong old_eip, esp, offset;
967
968	#ifdef VBOX
969	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
970	cpu_loop_exit();
971	#endif
972
973	has_error_code = 0;
974	if (!is_int && !is_hw) {
975	switch(intno) {
976	case 8:
977	case 10:
978	case 11:
979	case 12:
980	case 13:
981	case 14:
982	case 17:
983	has_error_code = 1;
984	break;
985	}
986	}
987	if (is_int)
988	old_eip = next_eip;
989	else
990	old_eip = env->eip;
991
992	dt = &env->idt;
993	if (intno * 16 + 15 > dt->limit)
994	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
995	ptr = dt->base + intno * 16;
996	e1 = ldl_kernel(ptr);
997	e2 = ldl_kernel(ptr + 4);
998	e3 = ldl_kernel(ptr + 8);
999	/* check gate type */
1000	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1001	switch(type) {
1002	case 14: /* 386 interrupt gate */
1003	case 15: /* 386 trap gate */
1004	break;
1005	default:
1006	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1007	break;
1008	}
1009	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1010	cpl = env->hflags & HF_CPL_MASK;
1011	/* check privledge if software int */
1012	if (is_int && dpl < cpl)
1013	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1014	/* check valid bit */
1015	if (!(e2 & DESC_P_MASK))
1016	raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
1017	selector = e1 >> 16;
1018	offset = ((target_ulong)e3 << 32) \| (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
1019	ist = e2 & 7;
1020	if ((selector & 0xfffc) == 0)
1021	raise_exception_err(EXCP0D_GPF, 0);
1022
1023	if (load_segment(&e1, &e2, selector) != 0)
1024	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1025	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
1026	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1027	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1028	if (dpl > cpl)
1029	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1030	if (!(e2 & DESC_P_MASK))
1031	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1032	if (!(e2 & DESC_L_MASK) \|\| (e2 & DESC_B_MASK))
1033	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1034	if ((!(e2 & DESC_C_MASK) && dpl < cpl) \|\| ist != 0) {
1035	/* to inner priviledge */
1036	if (ist != 0)
1037	esp = get_rsp_from_tss(ist + 3);
1038	else
1039	esp = get_rsp_from_tss(dpl);
1040	esp &= ~0xfLL; /* align stack */
1041	ss = 0;
1042	new_stack = 1;
1043	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
1044	/* to same priviledge */
1045	if (env->eflags & VM_MASK)
1046	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1047	new_stack = 0;
1048	if (ist != 0)
1049	esp = get_rsp_from_tss(ist + 3);
1050	else
1051	esp = ESP;
1052	esp &= ~0xfLL; /* align stack */
1053	dpl = cpl;
1054	} else {
1055	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1056	new_stack = 0; /* avoid warning */
1057	esp = 0; /* avoid warning */
1058	}
1059
1060	PUSHQ(esp, env->segs[R_SS].selector);
1061	PUSHQ(esp, ESP);
1062	PUSHQ(esp, compute_eflags());
1063	PUSHQ(esp, env->segs[R_CS].selector);
1064	PUSHQ(esp, old_eip);
1065	if (has_error_code) {
1066	PUSHQ(esp, error_code);
1067	}
1068
1069	if (new_stack) {
1070	ss = 0 \| dpl;
1071	cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1072	}
1073	ESP = esp;
1074
1075	selector = (selector & ~3) \| dpl;
1076	cpu_x86_load_seg_cache(env, R_CS, selector,
1077	get_seg_base(e1, e2),
1078	get_seg_limit(e1, e2),
1079	e2);
1080	cpu_x86_set_cpl(env, dpl);
1081	env->eip = offset;
1082
1083	/* interrupt gate clear IF mask */
1084	if ((type & 1) == 0) {
1085	env->eflags &= ~IF_MASK;
1086	}
1087	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1088	}
1089	#endif
1090
1091	void helper_syscall(int next_eip_addend)
1092	{
1093	int selector;
1094
1095	if (!(env->efer & MSR_EFER_SCE)) {
1096	raise_exception_err(EXCP06_ILLOP, 0);
1097	}
1098	selector = (env->star >> 32) & 0xffff;
1099	#ifdef TARGET_X86_64
1100	if (env->hflags & HF_LMA_MASK) {
1101	int code64;
1102
1103	ECX = env->eip + next_eip_addend;
1104	env->regs[11] = compute_eflags();
1105
1106	code64 = env->hflags & HF_CS64_MASK;
1107
1108	cpu_x86_set_cpl(env, 0);
1109	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1110	0, 0xffffffff,
1111	DESC_G_MASK \| DESC_P_MASK \|
1112	DESC_S_MASK \|
1113	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \| DESC_L_MASK);
1114	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1115	0, 0xffffffff,
1116	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1117	DESC_S_MASK \|
1118	DESC_W_MASK \| DESC_A_MASK);
1119	env->eflags &= ~env->fmask;
1120	load_eflags(env->eflags, 0);
1121	if (code64)
1122	env->eip = env->lstar;
1123	else
1124	env->eip = env->cstar;
1125	} else
1126	#endif
1127	{
1128	ECX = (uint32_t)(env->eip + next_eip_addend);
1129
1130	cpu_x86_set_cpl(env, 0);
1131	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1132	0, 0xffffffff,
1133	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1134	DESC_S_MASK \|
1135	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1136	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1137	0, 0xffffffff,
1138	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1139	DESC_S_MASK \|
1140	DESC_W_MASK \| DESC_A_MASK);
1141	env->eflags &= ~(IF_MASK \| RF_MASK \| VM_MASK);
1142	env->eip = (uint32_t)env->star;
1143	}
1144	}
1145
1146	void helper_sysret(int dflag)
1147	{
1148	int cpl, selector;
1149
1150	if (!(env->efer & MSR_EFER_SCE)) {
1151	raise_exception_err(EXCP06_ILLOP, 0);
1152	}
1153	cpl = env->hflags & HF_CPL_MASK;
1154	if (!(env->cr[0] & CR0_PE_MASK) \|\| cpl != 0) {
1155	raise_exception_err(EXCP0D_GPF, 0);
1156	}
1157	selector = (env->star >> 48) & 0xffff;
1158	#ifdef TARGET_X86_64
1159	if (env->hflags & HF_LMA_MASK) {
1160	if (dflag == 2) {
1161	cpu_x86_load_seg_cache(env, R_CS, (selector + 16) \| 3,
1162	0, 0xffffffff,
1163	DESC_G_MASK \| DESC_P_MASK \|
1164	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1165	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \|
1166	DESC_L_MASK);
1167	env->eip = ECX;
1168	} else {
1169	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1170	0, 0xffffffff,
1171	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1172	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1173	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1174	env->eip = (uint32_t)ECX;
1175	}
1176	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1177	0, 0xffffffff,
1178	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1179	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1180	DESC_W_MASK \| DESC_A_MASK);
1181	load_eflags((uint32_t)(env->regs[11]), TF_MASK \| AC_MASK \| ID_MASK \|
1182	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1183	cpu_x86_set_cpl(env, 3);
1184	} else
1185	#endif
1186	{
1187	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1188	0, 0xffffffff,
1189	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1190	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1191	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1192	env->eip = (uint32_t)ECX;
1193	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1194	0, 0xffffffff,
1195	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1196	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1197	DESC_W_MASK \| DESC_A_MASK);
1198	env->eflags \|= IF_MASK;
1199	cpu_x86_set_cpl(env, 3);
1200	}
1201	#ifdef USE_KQEMU
1202	if (kqemu_is_ok(env)) {
1203	if (env->hflags & HF_LMA_MASK)
1204	CC_OP = CC_OP_EFLAGS;
1205	env->exception_index = -1;
1206	cpu_loop_exit();
1207	}
1208	#endif
1209	}
1210
1211	#ifdef VBOX
1212	/**
1213	* Checks and processes external VMM events.
1214	* Called by op_check_external_event() when any of the flags is set and can be serviced.
1215	*/
1216	void helper_external_event(void)
1217	{
1218	#if defined(RT_OS_DARWIN) && defined(VBOX_STRICT)
1219	uintptr_t uESP;
1220	__asm__ __volatile__("movl %%esp, %0" : "=r" (uESP));
1221	AssertMsg(!(uESP & 15), ("esp=%#p\n", uESP));
1222	#endif
1223	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1224	{
1225	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1226	cpu_interrupt(env, CPU_INTERRUPT_HARD);
1227	}
1228	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1229	{
1230	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1231	cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1232	}
1233	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1234	{
1235	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1236	remR3DmaRun(env);
1237	}
1238	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1239	{
1240	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1241	remR3TimersRun(env);
1242	}
1243	}
1244	/* helper for recording call instruction addresses for later scanning */
1245	void helper_record_call()
1246	{
1247	if ( !(env->state & CPU_RAW_RING0)
1248	&& (env->cr[0] & CR0_PG_MASK)
1249	&& !(env->eflags & X86_EFL_IF))
1250	remR3RecordCall(env);
1251	}
1252	#endif /* VBOX */
1253
1254	/* real mode interrupt */
1255	static void do_interrupt_real(int intno, int is_int, int error_code,
1256	unsigned int next_eip)
1257	{
1258	SegmentCache *dt;
1259	target_ulong ptr, ssp;
1260	int selector;
1261	uint32_t offset, esp;
1262	uint32_t old_cs, old_eip;
1263
1264	/* real mode (simpler !) */
1265	dt = &env->idt;
1266	if (intno * 4 + 3 > dt->limit)
1267	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1268	ptr = dt->base + intno * 4;
1269	offset = lduw_kernel(ptr);
1270	selector = lduw_kernel(ptr + 2);
1271	esp = ESP;
1272	ssp = env->segs[R_SS].base;
1273	if (is_int)
1274	old_eip = next_eip;
1275	else
1276	old_eip = env->eip;
1277	old_cs = env->segs[R_CS].selector;
1278	/* XXX: use SS segment size ? */
1279	PUSHW(ssp, esp, 0xffff, compute_eflags());
1280	PUSHW(ssp, esp, 0xffff, old_cs);
1281	PUSHW(ssp, esp, 0xffff, old_eip);
1282
1283	/* update processor state */
1284	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
1285	env->eip = offset;
1286	env->segs[R_CS].selector = selector;
1287	env->segs[R_CS].base = (selector << 4);
1288	env->eflags &= ~(IF_MASK \| TF_MASK \| AC_MASK \| RF_MASK);
1289	}
1290
1291	/* fake user mode interrupt */
1292	void do_interrupt_user(int intno, int is_int, int error_code,
1293	target_ulong next_eip)
1294	{
1295	SegmentCache *dt;
1296	target_ulong ptr;
1297	int dpl, cpl;
1298	uint32_t e2;
1299
1300	dt = &env->idt;
1301	ptr = dt->base + (intno * 8);
1302	e2 = ldl_kernel(ptr + 4);
1303
1304	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1305	cpl = env->hflags & HF_CPL_MASK;
1306	/* check privledge if software int */
1307	if (is_int && dpl < cpl)
1308	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1309
1310	/* Since we emulate only user space, we cannot do more than
1311	exiting the emulation with the suitable exception and error
1312	code */
1313	if (is_int)
1314	EIP = next_eip;
1315	}
1316
1317	/*
1318	* Begin execution of an interruption. is_int is TRUE if coming from
1319	* the int instruction. next_eip is the EIP value AFTER the interrupt
1320	* instruction. It is only relevant if is_int is TRUE.
1321	*/
1322	void do_interrupt(int intno, int is_int, int error_code,
1323	target_ulong next_eip, int is_hw)
1324	{
1325	if (loglevel & CPU_LOG_INT) {
1326	if ((env->cr[0] & CR0_PE_MASK)) {
1327	static int count;
1328	fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1329	count, intno, error_code, is_int,
1330	env->hflags & HF_CPL_MASK,
1331	env->segs[R_CS].selector, EIP,
1332	(int)env->segs[R_CS].base + EIP,
1333	env->segs[R_SS].selector, ESP);
1334	if (intno == 0x0e) {
1335	fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1336	} else {
1337	fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1338	}
1339	fprintf(logfile, "\n");
1340	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1341	#if 0
1342	{
1343	int i;
1344	uint8_t *ptr;
1345	fprintf(logfile, " code=");
1346	ptr = env->segs[R_CS].base + env->eip;
1347	for(i = 0; i < 16; i++) {
1348	fprintf(logfile, " %02x", ldub(ptr + i));
1349	}
1350	fprintf(logfile, "\n");
1351	}
1352	#endif
1353	count++;
1354	}
1355	}
1356	if (env->cr[0] & CR0_PE_MASK) {
1357	#ifdef TARGET_X86_64
1358	if (env->hflags & HF_LMA_MASK) {
1359	do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1360	} else
1361	#endif
1362	{
1363	#ifdef VBOX
1364	/* int xx , v86 code and VME enabled? /
1365	if ( (env->eflags & VM_MASK)
1366	&& (env->cr[4] & CR4_VME_MASK)
1367	&& is_int
1368	&& !is_hw
1369	&& env->eip + 1 != next_eip /* single byte int 3 goes straight to the protected mode handler */
1370	)
1371	do_soft_interrupt_vme(intno, error_code, next_eip);
1372	else
1373	#endif /* VBOX */
1374	do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1375	}
1376	} else {
1377	do_interrupt_real(intno, is_int, error_code, next_eip);
1378	}
1379	}
1380
1381	/*
1382	* Signal an interruption. It is executed in the main CPU loop.
1383	* is_int is TRUE if coming from the int instruction. next_eip is the
1384	* EIP value AFTER the interrupt instruction. It is only relevant if
1385	* is_int is TRUE.
1386	*/
1387	void raise_interrupt(int intno, int is_int, int error_code,
1388	int next_eip_addend)
1389	{
1390	#if defined(VBOX) && defined(DEBUG)
1391	NOT_DMIK(Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend)));
1392	#endif
1393	env->exception_index = intno;
1394	env->error_code = error_code;
1395	env->exception_is_int = is_int;
1396	env->exception_next_eip = env->eip + next_eip_addend;
1397	cpu_loop_exit();
1398	}
1399
1400	/* same as raise_exception_err, but do not restore global registers */
1401	static void raise_exception_err_norestore(int exception_index, int error_code)
1402	{
1403	env->exception_index = exception_index;
1404	env->error_code = error_code;
1405	env->exception_is_int = 0;
1406	env->exception_next_eip = 0;
1407	longjmp(env->jmp_env, 1);
1408	}
1409
1410	/* shortcuts to generate exceptions */
1411
1412	void (raise_exception_err)(int exception_index, int error_code)
1413	{
1414	raise_interrupt(exception_index, 0, error_code, 0);
1415	}
1416
1417	void raise_exception(int exception_index)
1418	{
1419	raise_interrupt(exception_index, 0, 0, 0);
1420	}
1421
1422	/* SMM support */
1423
1424	#if defined(CONFIG_USER_ONLY)
1425
1426	void do_smm_enter(void)
1427	{
1428	}
1429
1430	void helper_rsm(void)
1431	{
1432	}
1433
1434	#else
1435
1436	#ifdef TARGET_X86_64
1437	#define SMM_REVISION_ID 0x00020064
1438	#else
1439	#define SMM_REVISION_ID 0x00020000
1440	#endif
1441
1442	void do_smm_enter(void)
1443	{
1444	#ifdef VBOX
1445	cpu_abort(env, "do_ssm_enter");
1446	#else /* !VBOX */
1447	target_ulong sm_state;
1448	SegmentCache *dt;
1449	int i, offset;
1450
1451	if (loglevel & CPU_LOG_INT) {
1452	fprintf(logfile, "SMM: enter\n");
1453	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1454	}
1455
1456	env->hflags \|= HF_SMM_MASK;
1457	cpu_smm_update(env);
1458
1459	sm_state = env->smbase + 0x8000;
1460
1461	#ifdef TARGET_X86_64
1462	for(i = 0; i < 6; i++) {
1463	dt = &env->segs[i];
1464	offset = 0x7e00 + i * 16;
1465	stw_phys(sm_state + offset, dt->selector);
1466	stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1467	stl_phys(sm_state + offset + 4, dt->limit);
1468	stq_phys(sm_state + offset + 8, dt->base);
1469	}
1470
1471	stq_phys(sm_state + 0x7e68, env->gdt.base);
1472	stl_phys(sm_state + 0x7e64, env->gdt.limit);
1473
1474	stw_phys(sm_state + 0x7e70, env->ldt.selector);
1475	stq_phys(sm_state + 0x7e78, env->ldt.base);
1476	stl_phys(sm_state + 0x7e74, env->ldt.limit);
1477	stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1478
1479	stq_phys(sm_state + 0x7e88, env->idt.base);
1480	stl_phys(sm_state + 0x7e84, env->idt.limit);
1481
1482	stw_phys(sm_state + 0x7e90, env->tr.selector);
1483	stq_phys(sm_state + 0x7e98, env->tr.base);
1484	stl_phys(sm_state + 0x7e94, env->tr.limit);
1485	stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1486
1487	stq_phys(sm_state + 0x7ed0, env->efer);
1488
1489	stq_phys(sm_state + 0x7ff8, EAX);
1490	stq_phys(sm_state + 0x7ff0, ECX);
1491	stq_phys(sm_state + 0x7fe8, EDX);
1492	stq_phys(sm_state + 0x7fe0, EBX);
1493	stq_phys(sm_state + 0x7fd8, ESP);
1494	stq_phys(sm_state + 0x7fd0, EBP);
1495	stq_phys(sm_state + 0x7fc8, ESI);
1496	stq_phys(sm_state + 0x7fc0, EDI);
1497	for(i = 8; i < 16; i++)
1498	stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1499	stq_phys(sm_state + 0x7f78, env->eip);
1500	stl_phys(sm_state + 0x7f70, compute_eflags());
1501	stl_phys(sm_state + 0x7f68, env->dr[6]);
1502	stl_phys(sm_state + 0x7f60, env->dr[7]);
1503
1504	stl_phys(sm_state + 0x7f48, env->cr[4]);
1505	stl_phys(sm_state + 0x7f50, env->cr[3]);
1506	stl_phys(sm_state + 0x7f58, env->cr[0]);
1507
1508	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1509	stl_phys(sm_state + 0x7f00, env->smbase);
1510	#else
1511	stl_phys(sm_state + 0x7ffc, env->cr[0]);
1512	stl_phys(sm_state + 0x7ff8, env->cr[3]);
1513	stl_phys(sm_state + 0x7ff4, compute_eflags());
1514	stl_phys(sm_state + 0x7ff0, env->eip);
1515	stl_phys(sm_state + 0x7fec, EDI);
1516	stl_phys(sm_state + 0x7fe8, ESI);
1517	stl_phys(sm_state + 0x7fe4, EBP);
1518	stl_phys(sm_state + 0x7fe0, ESP);
1519	stl_phys(sm_state + 0x7fdc, EBX);
1520	stl_phys(sm_state + 0x7fd8, EDX);
1521	stl_phys(sm_state + 0x7fd4, ECX);
1522	stl_phys(sm_state + 0x7fd0, EAX);
1523	stl_phys(sm_state + 0x7fcc, env->dr[6]);
1524	stl_phys(sm_state + 0x7fc8, env->dr[7]);
1525
1526	stl_phys(sm_state + 0x7fc4, env->tr.selector);
1527	stl_phys(sm_state + 0x7f64, env->tr.base);
1528	stl_phys(sm_state + 0x7f60, env->tr.limit);
1529	stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1530
1531	stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1532	stl_phys(sm_state + 0x7f80, env->ldt.base);
1533	stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1534	stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1535
1536	stl_phys(sm_state + 0x7f74, env->gdt.base);
1537	stl_phys(sm_state + 0x7f70, env->gdt.limit);
1538
1539	stl_phys(sm_state + 0x7f58, env->idt.base);
1540	stl_phys(sm_state + 0x7f54, env->idt.limit);
1541
1542	for(i = 0; i < 6; i++) {
1543	dt = &env->segs[i];
1544	if (i < 3)
1545	offset = 0x7f84 + i * 12;
1546	else
1547	offset = 0x7f2c + (i - 3) * 12;
1548	stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1549	stl_phys(sm_state + offset + 8, dt->base);
1550	stl_phys(sm_state + offset + 4, dt->limit);
1551	stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1552	}
1553	stl_phys(sm_state + 0x7f14, env->cr[4]);
1554
1555	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1556	stl_phys(sm_state + 0x7ef8, env->smbase);
1557	#endif
1558	/* init SMM cpu state */
1559
1560	#ifdef TARGET_X86_64
1561	env->efer = 0;
1562	env->hflags &= ~HF_LMA_MASK;
1563	#endif
1564	load_eflags(0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1565	env->eip = 0x00008000;
1566	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1567	0xffffffff, 0);
1568	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1569	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1570	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1571	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1572	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1573
1574	cpu_x86_update_cr0(env,
1575	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \| CR0_PG_MASK));
1576	cpu_x86_update_cr4(env, 0);
1577	env->dr[7] = 0x00000400;
1578	CC_OP = CC_OP_EFLAGS;
1579	#endif /* VBOX */
1580	}
1581
1582	void helper_rsm(void)
1583	{
1584	#ifdef VBOX
1585	cpu_abort(env, "helper_rsm");
1586	#else /* !VBOX */
1587	target_ulong sm_state;
1588	int i, offset;
1589	uint32_t val;
1590
1591	sm_state = env->smbase + 0x8000;
1592	#ifdef TARGET_X86_64
1593	env->efer = ldq_phys(sm_state + 0x7ed0);
1594	if (env->efer & MSR_EFER_LMA)
1595	env->hflags \|= HF_LMA_MASK;
1596	else
1597	env->hflags &= ~HF_LMA_MASK;
1598
1599	for(i = 0; i < 6; i++) {
1600	offset = 0x7e00 + i * 16;
1601	cpu_x86_load_seg_cache(env, i,
1602	lduw_phys(sm_state + offset),
1603	ldq_phys(sm_state + offset + 8),
1604	ldl_phys(sm_state + offset + 4),
1605	(lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1606	}
1607
1608	env->gdt.base = ldq_phys(sm_state + 0x7e68);
1609	env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1610
1611	env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1612	env->ldt.base = ldq_phys(sm_state + 0x7e78);
1613	env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1614	env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1615
1616	env->idt.base = ldq_phys(sm_state + 0x7e88);
1617	env->idt.limit = ldl_phys(sm_state + 0x7e84);
1618
1619	env->tr.selector = lduw_phys(sm_state + 0x7e90);
1620	env->tr.base = ldq_phys(sm_state + 0x7e98);
1621	env->tr.limit = ldl_phys(sm_state + 0x7e94);
1622	env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1623
1624	EAX = ldq_phys(sm_state + 0x7ff8);
1625	ECX = ldq_phys(sm_state + 0x7ff0);
1626	EDX = ldq_phys(sm_state + 0x7fe8);
1627	EBX = ldq_phys(sm_state + 0x7fe0);
1628	ESP = ldq_phys(sm_state + 0x7fd8);
1629	EBP = ldq_phys(sm_state + 0x7fd0);
1630	ESI = ldq_phys(sm_state + 0x7fc8);
1631	EDI = ldq_phys(sm_state + 0x7fc0);
1632	for(i = 8; i < 16; i++)
1633	env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1634	env->eip = ldq_phys(sm_state + 0x7f78);
1635	load_eflags(ldl_phys(sm_state + 0x7f70),
1636	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1637	env->dr[6] = ldl_phys(sm_state + 0x7f68);
1638	env->dr[7] = ldl_phys(sm_state + 0x7f60);
1639
1640	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1641	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1642	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1643
1644	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1645	if (val & 0x20000) {
1646	env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1647	}
1648	#else
1649	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1650	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1651	load_eflags(ldl_phys(sm_state + 0x7ff4),
1652	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1653	env->eip = ldl_phys(sm_state + 0x7ff0);
1654	EDI = ldl_phys(sm_state + 0x7fec);
1655	ESI = ldl_phys(sm_state + 0x7fe8);
1656	EBP = ldl_phys(sm_state + 0x7fe4);
1657	ESP = ldl_phys(sm_state + 0x7fe0);
1658	EBX = ldl_phys(sm_state + 0x7fdc);
1659	EDX = ldl_phys(sm_state + 0x7fd8);
1660	ECX = ldl_phys(sm_state + 0x7fd4);
1661	EAX = ldl_phys(sm_state + 0x7fd0);
1662	env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1663	env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1664
1665	env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1666	env->tr.base = ldl_phys(sm_state + 0x7f64);
1667	env->tr.limit = ldl_phys(sm_state + 0x7f60);
1668	env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1669
1670	env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1671	env->ldt.base = ldl_phys(sm_state + 0x7f80);
1672	env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1673	env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1674
1675	env->gdt.base = ldl_phys(sm_state + 0x7f74);
1676	env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1677
1678	env->idt.base = ldl_phys(sm_state + 0x7f58);
1679	env->idt.limit = ldl_phys(sm_state + 0x7f54);
1680
1681	for(i = 0; i < 6; i++) {
1682	if (i < 3)
1683	offset = 0x7f84 + i * 12;
1684	else
1685	offset = 0x7f2c + (i - 3) * 12;
1686	cpu_x86_load_seg_cache(env, i,
1687	ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1688	ldl_phys(sm_state + offset + 8),
1689	ldl_phys(sm_state + offset + 4),
1690	(ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1691	}
1692	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1693
1694	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1695	if (val & 0x20000) {
1696	env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1697	}
1698	#endif
1699	CC_OP = CC_OP_EFLAGS;
1700	env->hflags &= ~HF_SMM_MASK;
1701	cpu_smm_update(env);
1702
1703	if (loglevel & CPU_LOG_INT) {
1704	fprintf(logfile, "SMM: after RSM\n");
1705	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1706	}
1707	#endif /* !VBOX */
1708	}
1709
1710	#endif /* !CONFIG_USER_ONLY */
1711
1712
1713	#ifdef BUGGY_GCC_DIV64
1714	/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1715	call it from another function */
1716	uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1717	{
1718	*q_ptr = num / den;
1719	return num % den;
1720	}
1721
1722	int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1723	{
1724	*q_ptr = num / den;
1725	return num % den;
1726	}
1727	#endif
1728
1729	void helper_divl_EAX_T0(void)
1730	{
1731	unsigned int den, r;
1732	uint64_t num, q;
1733
1734	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1735	den = T0;
1736	if (den == 0) {
1737	raise_exception(EXCP00_DIVZ);
1738	}
1739	#ifdef BUGGY_GCC_DIV64
1740	r = div32(&q, num, den);
1741	#else
1742	q = (num / den);
1743	r = (num % den);
1744	#endif
1745	if (q > 0xffffffff)
1746	raise_exception(EXCP00_DIVZ);
1747	EAX = (uint32_t)q;
1748	EDX = (uint32_t)r;
1749	}
1750
1751	void helper_idivl_EAX_T0(void)
1752	{
1753	int den, r;
1754	int64_t num, q;
1755
1756	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1757	den = T0;
1758	if (den == 0) {
1759	raise_exception(EXCP00_DIVZ);
1760	}
1761	#ifdef BUGGY_GCC_DIV64
1762	r = idiv32(&q, num, den);
1763	#else
1764	q = (num / den);
1765	r = (num % den);
1766	#endif
1767	if (q != (int32_t)q)
1768	raise_exception(EXCP00_DIVZ);
1769	EAX = (uint32_t)q;
1770	EDX = (uint32_t)r;
1771	}
1772
1773	void helper_cmpxchg8b(void)
1774	{
1775	uint64_t d;
1776	int eflags;
1777
1778	eflags = cc_table[CC_OP].compute_all();
1779	d = ldq(A0);
1780	if (d == (((uint64_t)EDX << 32) \| EAX)) {
1781	stq(A0, ((uint64_t)ECX << 32) \| EBX);
1782	eflags \|= CC_Z;
1783	} else {
1784	/* always do the store */
1785	stq(A0, d);
1786	EDX = (uint32_t)(d >> 32);
1787	EAX = (uint32_t)d;
1788	eflags &= ~CC_Z;
1789	}
1790	CC_SRC = eflags;
1791	}
1792
1793	void helper_single_step()
1794	{
1795	env->dr[6] \|= 0x4000;
1796	raise_exception(EXCP01_SSTP);
1797	}
1798
1799	void helper_cpuid(void)
1800	{
1801	#ifndef VBOX
1802	uint32_t index;
1803	index = (uint32_t)EAX;
1804
1805	/* test if maximum index reached */
1806	if (index & 0x80000000) {
1807	if (index > env->cpuid_xlevel)
1808	index = env->cpuid_level;
1809	} else {
1810	if (index > env->cpuid_level)
1811	index = env->cpuid_level;
1812	}
1813
1814	switch(index) {
1815	case 0:
1816	EAX = env->cpuid_level;
1817	EBX = env->cpuid_vendor1;
1818	EDX = env->cpuid_vendor2;
1819	ECX = env->cpuid_vendor3;
1820	break;
1821	case 1:
1822	EAX = env->cpuid_version;
1823	EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1824	ECX = env->cpuid_ext_features;
1825	EDX = env->cpuid_features;
1826	break;
1827	case 2:
1828	/* cache info: needed for Pentium Pro compatibility */
1829	EAX = 0x410601;
1830	EBX = 0;
1831	ECX = 0;
1832	EDX = 0;
1833	break;
1834	case 0x80000000:
1835	EAX = env->cpuid_xlevel;
1836	EBX = env->cpuid_vendor1;
1837	EDX = env->cpuid_vendor2;
1838	ECX = env->cpuid_vendor3;
1839	break;
1840	case 0x80000001:
1841	EAX = env->cpuid_features;
1842	EBX = 0;
1843	ECX = 0;
1844	EDX = env->cpuid_ext2_features;
1845	break;
1846	case 0x80000002:
1847	case 0x80000003:
1848	case 0x80000004:
1849	EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1850	EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1851	ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1852	EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1853	break;
1854	case 0x80000005:
1855	/* cache info (L1 cache) */
1856	EAX = 0x01ff01ff;
1857	EBX = 0x01ff01ff;
1858	ECX = 0x40020140;
1859	EDX = 0x40020140;
1860	break;
1861	case 0x80000006:
1862	/* cache info (L2 cache) */
1863	EAX = 0;
1864	EBX = 0x42004200;
1865	ECX = 0x02008140;
1866	EDX = 0;
1867	break;
1868	case 0x80000008:
1869	/* virtual & phys address size in low 2 bytes. */
1870	EAX = 0x00003028;
1871	EBX = 0;
1872	ECX = 0;
1873	EDX = 0;
1874	break;
1875	default:
1876	/* reserved values: zero */
1877	EAX = 0;
1878	EBX = 0;
1879	ECX = 0;
1880	EDX = 0;
1881	break;
1882	}
1883	#else /* VBOX */
1884	remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1885	#endif /* VBOX */
1886	}
1887
1888	void helper_enter_level(int level, int data32)
1889	{
1890	target_ulong ssp;
1891	uint32_t esp_mask, esp, ebp;
1892
1893	esp_mask = get_sp_mask(env->segs[R_SS].flags);
1894	ssp = env->segs[R_SS].base;
1895	ebp = EBP;
1896	esp = ESP;
1897	if (data32) {
1898	/* 32 bit */
1899	esp -= 4;
1900	while (--level) {
1901	esp -= 4;
1902	ebp -= 4;
1903	stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1904	}
1905	esp -= 4;
1906	stl(ssp + (esp & esp_mask), T1);
1907	} else {
1908	/* 16 bit */
1909	esp -= 2;
1910	while (--level) {
1911	esp -= 2;
1912	ebp -= 2;
1913	stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1914	}
1915	esp -= 2;
1916	stw(ssp + (esp & esp_mask), T1);
1917	}
1918	}
1919
1920	#ifdef TARGET_X86_64
1921	void helper_enter64_level(int level, int data64)
1922	{
1923	target_ulong esp, ebp;
1924	ebp = EBP;
1925	esp = ESP;
1926
1927	if (data64) {
1928	/* 64 bit */
1929	esp -= 8;
1930	while (--level) {
1931	esp -= 8;
1932	ebp -= 8;
1933	stq(esp, ldq(ebp));
1934	}
1935	esp -= 8;
1936	stq(esp, T1);
1937	} else {
1938	/* 16 bit */
1939	esp -= 2;
1940	while (--level) {
1941	esp -= 2;
1942	ebp -= 2;
1943	stw(esp, lduw(ebp));
1944	}
1945	esp -= 2;
1946	stw(esp, T1);
1947	}
1948	}
1949	#endif
1950
1951	void helper_lldt_T0(void)
1952	{
1953	int selector;
1954	SegmentCache *dt;
1955	uint32_t e1, e2;
1956	int index, entry_limit;
1957	target_ulong ptr;
1958	#ifdef VBOX
1959	Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1960	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1961	#endif
1962
1963	selector = T0 & 0xffff;
1964	if ((selector & 0xfffc) == 0) {
1965	/* XXX: NULL selector case: invalid LDT */
1966	env->ldt.base = 0;
1967	env->ldt.limit = 0;
1968	} else {
1969	if (selector & 0x4)
1970	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1971	dt = &env->gdt;
1972	index = selector & ~7;
1973	#ifdef TARGET_X86_64
1974	if (env->hflags & HF_LMA_MASK)
1975	entry_limit = 15;
1976	else
1977	#endif
1978	entry_limit = 7;
1979	if ((index + entry_limit) > dt->limit)
1980	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1981	ptr = dt->base + index;
1982	e1 = ldl_kernel(ptr);
1983	e2 = ldl_kernel(ptr + 4);
1984	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1985	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1986	if (!(e2 & DESC_P_MASK))
1987	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1988	#ifdef TARGET_X86_64
1989	if (env->hflags & HF_LMA_MASK) {
1990	uint32_t e3;
1991	e3 = ldl_kernel(ptr + 8);
1992	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1993	env->ldt.base \|= (target_ulong)e3 << 32;
1994	} else
1995	#endif
1996	{
1997	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1998	}
1999	}
2000	env->ldt.selector = selector;
2001	#ifdef VBOX
2002	Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
2003	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
2004	#endif
2005	}
2006
2007	void helper_ltr_T0(void)
2008	{
2009	int selector;
2010	SegmentCache *dt;
2011	uint32_t e1, e2;
2012	int index, type, entry_limit;
2013	target_ulong ptr;
2014
2015	#ifdef VBOX
2016	Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2017	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2018	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2019	#endif
2020
2021	selector = T0 & 0xffff;
2022	if ((selector & 0xfffc) == 0) {
2023	/* NULL selector case: invalid TR */
2024	env->tr.base = 0;
2025	env->tr.limit = 0;
2026	env->tr.flags = 0;
2027	} else {
2028	if (selector & 0x4)
2029	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2030	dt = &env->gdt;
2031	index = selector & ~7;
2032	#ifdef TARGET_X86_64
2033	if (env->hflags & HF_LMA_MASK)
2034	entry_limit = 15;
2035	else
2036	#endif
2037	entry_limit = 7;
2038	if ((index + entry_limit) > dt->limit)
2039	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2040	ptr = dt->base + index;
2041	e1 = ldl_kernel(ptr);
2042	e2 = ldl_kernel(ptr + 4);
2043	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2044	if ((e2 & DESC_S_MASK) \|\|
2045	(type != 1 && type != 9))
2046	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2047	if (!(e2 & DESC_P_MASK))
2048	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2049	#ifdef TARGET_X86_64
2050	if (env->hflags & HF_LMA_MASK) {
2051	uint32_t e3;
2052	e3 = ldl_kernel(ptr + 8);
2053	load_seg_cache_raw_dt(&env->tr, e1, e2);
2054	env->tr.base \|= (target_ulong)e3 << 32;
2055	} else
2056	#endif
2057	{
2058	load_seg_cache_raw_dt(&env->tr, e1, e2);
2059	}
2060	e2 \|= DESC_TSS_BUSY_MASK;
2061	stl_kernel(ptr + 4, e2);
2062	}
2063	env->tr.selector = selector;
2064	#ifdef VBOX
2065	Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2066	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2067	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2068	#endif
2069	}
2070
2071	/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2072	void load_seg(int seg_reg, int selector)
2073	{
2074	uint32_t e1, e2;
2075	int cpl, dpl, rpl;
2076	SegmentCache *dt;
2077	int index;
2078	target_ulong ptr;
2079
2080	selector &= 0xffff;
2081	cpl = env->hflags & HF_CPL_MASK;
2082
2083	#ifdef VBOX
2084	/* Trying to load a selector with CPL=1? */
2085	if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0))
2086	{
2087	Log(("RPL 1 -> sel %04X -> %04X\n", selector, selector & 0xfffc));
2088	selector = selector & 0xfffc;
2089	}
2090	#endif
2091
2092	if ((selector & 0xfffc) == 0) {
2093	/* null selector case */
2094	if (seg_reg == R_SS
2095	#ifdef TARGET_X86_64
2096	&& (!(env->hflags & HF_CS64_MASK) \|\| cpl == 3)
2097	#endif
2098	)
2099	raise_exception_err(EXCP0D_GPF, 0);
2100	cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2101	} else {
2102
2103	if (selector & 0x4)
2104	dt = &env->ldt;
2105	else
2106	dt = &env->gdt;
2107	index = selector & ~7;
2108	if ((index + 7) > dt->limit)
2109	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2110	ptr = dt->base + index;
2111	e1 = ldl_kernel(ptr);
2112	e2 = ldl_kernel(ptr + 4);
2113
2114	if (!(e2 & DESC_S_MASK))
2115	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2116	rpl = selector & 3;
2117	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2118	if (seg_reg == R_SS) {
2119	/* must be writable segment */
2120	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
2121	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2122	if (rpl != cpl \|\| dpl != cpl)
2123	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2124	} else {
2125	/* must be readable segment */
2126	if ((e2 & (DESC_CS_MASK \| DESC_R_MASK)) == DESC_CS_MASK)
2127	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2128
2129	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2130	/* if not conforming code, test rights */
2131	if (dpl < cpl \|\| dpl < rpl)
2132	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2133	}
2134	}
2135
2136	if (!(e2 & DESC_P_MASK)) {
2137	if (seg_reg == R_SS)
2138	raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
2139	else
2140	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2141	}
2142
2143	/* set the access bit if not already set */
2144	if (!(e2 & DESC_A_MASK)) {
2145	e2 \|= DESC_A_MASK;
2146	stl_kernel(ptr + 4, e2);
2147	}
2148
2149	cpu_x86_load_seg_cache(env, seg_reg, selector,
2150	get_seg_base(e1, e2),
2151	get_seg_limit(e1, e2),
2152	e2);
2153	#if 0
2154	fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
2155	selector, (unsigned long)sc->base, sc->limit, sc->flags);
2156	#endif
2157	}
2158	}
2159
2160	/* protected mode jump */
2161	void helper_ljmp_protected_T0_T1(int next_eip_addend)
2162	{
2163	int new_cs, gate_cs, type;
2164	uint32_t e1, e2, cpl, dpl, rpl, limit;
2165	target_ulong new_eip, next_eip;
2166
2167	new_cs = T0;
2168	new_eip = T1;
2169	if ((new_cs & 0xfffc) == 0)
2170	raise_exception_err(EXCP0D_GPF, 0);
2171	if (load_segment(&e1, &e2, new_cs) != 0)
2172	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2173	cpl = env->hflags & HF_CPL_MASK;
2174	if (e2 & DESC_S_MASK) {
2175	if (!(e2 & DESC_CS_MASK))
2176	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2177	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2178	if (e2 & DESC_C_MASK) {
2179	/* conforming code segment */
2180	if (dpl > cpl)
2181	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2182	} else {
2183	/* non conforming code segment */
2184	rpl = new_cs & 3;
2185	if (rpl > cpl)
2186	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2187	if (dpl != cpl)
2188	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2189	}
2190	if (!(e2 & DESC_P_MASK))
2191	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2192	limit = get_seg_limit(e1, e2);
2193	if (new_eip > limit &&
2194	!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2195	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2196	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2197	get_seg_base(e1, e2), limit, e2);
2198	EIP = new_eip;
2199	} else {
2200	/* jump to call or task gate */
2201	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2202	rpl = new_cs & 3;
2203	cpl = env->hflags & HF_CPL_MASK;
2204	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2205	switch(type) {
2206	case 1: /* 286 TSS */
2207	case 9: /* 386 TSS */
2208	case 5: /* task gate */
2209	if (dpl < cpl \|\| dpl < rpl)
2210	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2211	next_eip = env->eip + next_eip_addend;
2212	switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2213	CC_OP = CC_OP_EFLAGS;
2214	break;
2215	case 4: /* 286 call gate */
2216	case 12: /* 386 call gate */
2217	if ((dpl < cpl) \|\| (dpl < rpl))
2218	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2219	if (!(e2 & DESC_P_MASK))
2220	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2221	gate_cs = e1 >> 16;
2222	new_eip = (e1 & 0xffff);
2223	if (type == 12)
2224	new_eip \|= (e2 & 0xffff0000);
2225	if (load_segment(&e1, &e2, gate_cs) != 0)
2226	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2227	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2228	/* must be code segment */
2229	if (((e2 & (DESC_S_MASK \| DESC_CS_MASK)) !=
2230	(DESC_S_MASK \| DESC_CS_MASK)))
2231	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2232	if (((e2 & DESC_C_MASK) && (dpl > cpl)) \|\|
2233	(!(e2 & DESC_C_MASK) && (dpl != cpl)))
2234	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2235	if (!(e2 & DESC_P_MASK))
2236	#ifdef VBOX /* See page 3-514 of 253666.pdf */
2237	raise_exception_err(EXCP0B_NOSEG, gate_cs & 0xfffc);
2238	#else
2239	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2240	#endif
2241	limit = get_seg_limit(e1, e2);
2242	if (new_eip > limit)
2243	raise_exception_err(EXCP0D_GPF, 0);
2244	cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) \| cpl,
2245	get_seg_base(e1, e2), limit, e2);
2246	EIP = new_eip;
2247	break;
2248	default:
2249	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2250	break;
2251	}
2252	}
2253	}
2254
2255	/* real mode call */
2256	void helper_lcall_real_T0_T1(int shift, int next_eip)
2257	{
2258	int new_cs, new_eip;
2259	uint32_t esp, esp_mask;
2260	target_ulong ssp;
2261
2262	new_cs = T0;
2263	new_eip = T1;
2264	esp = ESP;
2265	esp_mask = get_sp_mask(env->segs[R_SS].flags);
2266	ssp = env->segs[R_SS].base;
2267	if (shift) {
2268	PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2269	PUSHL(ssp, esp, esp_mask, next_eip);
2270	} else {
2271	PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2272	PUSHW(ssp, esp, esp_mask, next_eip);
2273	}
2274
2275	SET_ESP(esp, esp_mask);
2276	env->eip = new_eip;
2277	env->segs[R_CS].selector = new_cs;
2278	env->segs[R_CS].base = (new_cs << 4);
2279	}
2280
2281	/* protected mode call */
2282	void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2283	{
2284	int new_cs, new_stack, i;
2285	uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2286	uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2287	uint32_t val, limit, old_sp_mask;
2288	target_ulong ssp, old_ssp, next_eip, new_eip;
2289
2290	new_cs = T0;
2291	new_eip = T1;
2292	next_eip = env->eip + next_eip_addend;
2293	#ifdef DEBUG_PCALL
2294	if (loglevel & CPU_LOG_PCALL) {
2295	fprintf(logfile, "lcall %04x:%08x s=%d\n",
2296	new_cs, (uint32_t)new_eip, shift);
2297	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2298	}
2299	#endif
2300	if ((new_cs & 0xfffc) == 0)
2301	raise_exception_err(EXCP0D_GPF, 0);
2302	if (load_segment(&e1, &e2, new_cs) != 0)
2303	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2304	cpl = env->hflags & HF_CPL_MASK;
2305	#ifdef DEBUG_PCALL
2306	if (loglevel & CPU_LOG_PCALL) {
2307	fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2308	}
2309	#endif
2310	if (e2 & DESC_S_MASK) {
2311	if (!(e2 & DESC_CS_MASK))
2312	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2313	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2314	if (e2 & DESC_C_MASK) {
2315	/* conforming code segment */
2316	if (dpl > cpl)
2317	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2318	} else {
2319	/* non conforming code segment */
2320	rpl = new_cs & 3;
2321	if (rpl > cpl)
2322	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2323	if (dpl != cpl)
2324	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2325	}
2326	if (!(e2 & DESC_P_MASK))
2327	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2328
2329	#ifdef TARGET_X86_64
2330	/* XXX: check 16/32 bit cases in long mode */
2331	if (shift == 2) {
2332	target_ulong rsp;
2333	/* 64 bit case */
2334	rsp = ESP;
2335	PUSHQ(rsp, env->segs[R_CS].selector);
2336	PUSHQ(rsp, next_eip);
2337	/* from this point, not restartable */
2338	ESP = rsp;
2339	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2340	get_seg_base(e1, e2),
2341	get_seg_limit(e1, e2), e2);
2342	EIP = new_eip;
2343	} else
2344	#endif
2345	{
2346	sp = ESP;
2347	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2348	ssp = env->segs[R_SS].base;
2349	if (shift) {
2350	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2351	PUSHL(ssp, sp, sp_mask, next_eip);
2352	} else {
2353	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2354	PUSHW(ssp, sp, sp_mask, next_eip);
2355	}
2356
2357	limit = get_seg_limit(e1, e2);
2358	if (new_eip > limit)
2359	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2360	/* from this point, not restartable */
2361	SET_ESP(sp, sp_mask);
2362	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2363	get_seg_base(e1, e2), limit, e2);
2364	EIP = new_eip;
2365	}
2366	} else {
2367	/* check gate type */
2368	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
2369	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2370	rpl = new_cs & 3;
2371	switch(type) {
2372	case 1: /* available 286 TSS */
2373	case 9: /* available 386 TSS */
2374	case 5: /* task gate */
2375	if (dpl < cpl \|\| dpl < rpl)
2376	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2377	switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
2378	CC_OP = CC_OP_EFLAGS;
2379	return;
2380	case 4: /* 286 call gate */
2381	case 12: /* 386 call gate */
2382	break;
2383	default:
2384	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2385	break;
2386	}
2387	shift = type >> 3;
2388
2389	if (dpl < cpl \|\| dpl < rpl)
2390	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2391	/* check valid bit */
2392	if (!(e2 & DESC_P_MASK))
2393	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2394	selector = e1 >> 16;
2395	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
2396	param_count = e2 & 0x1f;
2397	if ((selector & 0xfffc) == 0)
2398	raise_exception_err(EXCP0D_GPF, 0);
2399
2400	if (load_segment(&e1, &e2, selector) != 0)
2401	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2402	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
2403	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2404	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2405	if (dpl > cpl)
2406	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2407	if (!(e2 & DESC_P_MASK))
2408	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2409
2410	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2411	/* to inner priviledge */
2412	get_ss_esp_from_tss(&ss, &sp, dpl);
2413	#ifdef DEBUG_PCALL
2414	if (loglevel & CPU_LOG_PCALL)
2415	fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2416	ss, sp, param_count, ESP);
2417	#endif
2418	if ((ss & 0xfffc) == 0)
2419	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2420	if ((ss & 3) != dpl)
2421	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2422	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2423	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2424	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2425	if (ss_dpl != dpl)
2426	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2427	if (!(ss_e2 & DESC_S_MASK) \|\|
2428	(ss_e2 & DESC_CS_MASK) \|\|
2429	!(ss_e2 & DESC_W_MASK))
2430	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2431	if (!(ss_e2 & DESC_P_MASK))
2432	#ifdef VBOX /* See page 3-99 of 253666.pdf */
2433	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
2434	#else
2435	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2436	#endif
2437
2438	// push_size = ((param_count * 2) + 8) << shift;
2439
2440	old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2441	old_ssp = env->segs[R_SS].base;
2442
2443	sp_mask = get_sp_mask(ss_e2);
2444	ssp = get_seg_base(ss_e1, ss_e2);
2445	if (shift) {
2446	PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2447	PUSHL(ssp, sp, sp_mask, ESP);
2448	for(i = param_count - 1; i >= 0; i--) {
2449	val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2450	PUSHL(ssp, sp, sp_mask, val);
2451	}
2452	} else {
2453	PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2454	PUSHW(ssp, sp, sp_mask, ESP);
2455	for(i = param_count - 1; i >= 0; i--) {
2456	val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2457	PUSHW(ssp, sp, sp_mask, val);
2458	}
2459	}
2460	new_stack = 1;
2461	} else {
2462	/* to same priviledge */
2463	sp = ESP;
2464	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2465	ssp = env->segs[R_SS].base;
2466	// push_size = (4 << shift);
2467	new_stack = 0;
2468	}
2469
2470	if (shift) {
2471	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2472	PUSHL(ssp, sp, sp_mask, next_eip);
2473	} else {
2474	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2475	PUSHW(ssp, sp, sp_mask, next_eip);
2476	}
2477
2478	/* from this point, not restartable */
2479
2480	if (new_stack) {
2481	ss = (ss & ~3) \| dpl;
2482	cpu_x86_load_seg_cache(env, R_SS, ss,
2483	ssp,
2484	get_seg_limit(ss_e1, ss_e2),
2485	ss_e2);
2486	}
2487
2488	selector = (selector & ~3) \| dpl;
2489	cpu_x86_load_seg_cache(env, R_CS, selector,
2490	get_seg_base(e1, e2),
2491	get_seg_limit(e1, e2),
2492	e2);
2493	cpu_x86_set_cpl(env, dpl);
2494	SET_ESP(sp, sp_mask);
2495	EIP = offset;
2496	}
2497	#ifdef USE_KQEMU
2498	if (kqemu_is_ok(env)) {
2499	env->exception_index = -1;
2500	cpu_loop_exit();
2501	}
2502	#endif
2503	}
2504
2505	/* real and vm86 mode iret */
2506	void helper_iret_real(int shift)
2507	{
2508	uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2509	target_ulong ssp;
2510	int eflags_mask;
2511	#ifdef VBOX
2512	bool fVME = false;
2513
2514	remR3TrapClear(env->pVM);
2515	#endif /* VBOX */
2516
2517	sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2518	sp = ESP;
2519	ssp = env->segs[R_SS].base;
2520	if (shift == 1) {
2521	/* 32 bits */
2522	POPL(ssp, sp, sp_mask, new_eip);
2523	POPL(ssp, sp, sp_mask, new_cs);
2524	new_cs &= 0xffff;
2525	POPL(ssp, sp, sp_mask, new_eflags);
2526	} else {
2527	/* 16 bits */
2528	POPW(ssp, sp, sp_mask, new_eip);
2529	POPW(ssp, sp, sp_mask, new_cs);
2530	POPW(ssp, sp, sp_mask, new_eflags);
2531	}
2532	#ifdef VBOX
2533	if ( (env->eflags & VM_MASK)
2534	&& ((env->eflags >> IOPL_SHIFT) & 3) != 3
2535	&& (env->cr[4] & CR4_VME_MASK)) /* implied or else we would fault earlier */
2536	{
2537	fVME = true;
2538	/* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
2539	/* if TF will be set -> #GP */
2540	if ( ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
2541	\|\| (new_eflags & TF_MASK))
2542	raise_exception(EXCP0D_GPF);
2543	}
2544	#endif /* VBOX */
2545
2546	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);
2547	load_seg_vm(R_CS, new_cs);
2548	env->eip = new_eip;
2549	#ifdef VBOX
2550	if (fVME)
2551	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2552	else
2553	#endif
2554	if (env->eflags & VM_MASK)
2555	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| RF_MASK \| NT_MASK;
2556	else
2557	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| IOPL_MASK \| RF_MASK \| NT_MASK;
2558	if (shift == 0)
2559	eflags_mask &= 0xffff;
2560	load_eflags(new_eflags, eflags_mask);
2561
2562	#ifdef VBOX
2563	if (fVME)
2564	{
2565	if (new_eflags & IF_MASK)
2566	env->eflags \|= VIF_MASK;
2567	else
2568	env->eflags &= ~VIF_MASK;
2569	}
2570	#endif /* VBOX */
2571	}
2572
2573	static inline void validate_seg(int seg_reg, int cpl)
2574	{
2575	int dpl;
2576	uint32_t e2;
2577
2578	/* XXX: on x86_64, we do not want to nullify FS and GS because
2579	they may still contain a valid base. I would be interested to
2580	know how a real x86_64 CPU behaves */
2581	if ((seg_reg == R_FS \|\| seg_reg == R_GS) &&
2582	(env->segs[seg_reg].selector & 0xfffc) == 0)
2583	return;
2584
2585	e2 = env->segs[seg_reg].flags;
2586	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2587	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2588	/* data or non conforming code segment */
2589	if (dpl < cpl) {
2590	cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2591	}
2592	}
2593	}
2594
2595	/* protected mode iret */
2596	static inline void helper_ret_protected(int shift, int is_iret, int addend)
2597	{
2598	uint32_t new_cs, new_eflags, new_ss;
2599	uint32_t new_es, new_ds, new_fs, new_gs;
2600	uint32_t e1, e2, ss_e1, ss_e2;
2601	int cpl, dpl, rpl, eflags_mask, iopl;
2602	target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2603
2604	#ifdef TARGET_X86_64
2605	if (shift == 2)
2606	sp_mask = -1;
2607	else
2608	#endif
2609	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2610	sp = ESP;
2611	ssp = env->segs[R_SS].base;
2612	new_eflags = 0; /* avoid warning */
2613	#ifdef TARGET_X86_64
2614	if (shift == 2) {
2615	POPQ(sp, new_eip);
2616	POPQ(sp, new_cs);
2617	new_cs &= 0xffff;
2618	if (is_iret) {
2619	POPQ(sp, new_eflags);
2620	}
2621	} else
2622	#endif
2623	if (shift == 1) {
2624	/* 32 bits */
2625	POPL(ssp, sp, sp_mask, new_eip);
2626	POPL(ssp, sp, sp_mask, new_cs);
2627	new_cs &= 0xffff;
2628	if (is_iret) {
2629	POPL(ssp, sp, sp_mask, new_eflags);
2630	#if defined(VBOX) && defined(DEBUG)
2631	printf("iret: new CS %04X\n", new_cs);
2632	printf("iret: new EIP %08X\n", new_eip);
2633	printf("iret: new EFLAGS %08X\n", new_eflags);
2634	printf("iret: EAX=%08x\n", EAX);
2635	#endif
2636
2637	if (new_eflags & VM_MASK)
2638	goto return_to_vm86;
2639	}
2640	#ifdef VBOX
2641	if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
2642	{
2643	#ifdef DEBUG
2644	printf("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc);
2645	#endif
2646	new_cs = new_cs & 0xfffc;
2647	}
2648	#endif
2649	} else {
2650	/* 16 bits */
2651	POPW(ssp, sp, sp_mask, new_eip);
2652	POPW(ssp, sp, sp_mask, new_cs);
2653	if (is_iret)
2654	POPW(ssp, sp, sp_mask, new_eflags);
2655	}
2656	#ifdef DEBUG_PCALL
2657	if (loglevel & CPU_LOG_PCALL) {
2658	fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2659	new_cs, new_eip, shift, addend);
2660	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2661	}
2662	#endif
2663	if ((new_cs & 0xfffc) == 0)
2664	{
2665	#if defined(VBOX) && defined(DEBUG)
2666	printf("new_cs & 0xfffc) == 0\n");
2667	#endif
2668	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2669	}
2670	if (load_segment(&e1, &e2, new_cs) != 0)
2671	{
2672	#if defined(VBOX) && defined(DEBUG)
2673	printf("load_segment failed\n");
2674	#endif
2675	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2676	}
2677	if (!(e2 & DESC_S_MASK) \|\|
2678	!(e2 & DESC_CS_MASK))
2679	{
2680	#if defined(VBOX) && defined(DEBUG)
2681	printf("e2 mask %08x\n", e2);
2682	#endif
2683	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2684	}
2685	cpl = env->hflags & HF_CPL_MASK;
2686	rpl = new_cs & 3;
2687	if (rpl < cpl)
2688	{
2689	#if defined(VBOX) && defined(DEBUG)
2690	printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2691	#endif
2692	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2693	}
2694	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2695	if (e2 & DESC_C_MASK) {
2696	if (dpl > rpl)
2697	{
2698	#if defined(VBOX) && defined(DEBUG)
2699	printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2700	#endif
2701	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2702	}
2703	} else {
2704	if (dpl != rpl)
2705	{
2706	#if defined(VBOX) && defined(DEBUG)
2707	printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2708	#endif
2709	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2710	}
2711	}
2712	if (!(e2 & DESC_P_MASK))
2713	{
2714	#if defined(VBOX) && defined(DEBUG)
2715	printf("DESC_P_MASK e2=%08x\n", e2);
2716	#endif
2717	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2718	}
2719	sp += addend;
2720	if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) \|\|
2721	((env->hflags & HF_CS64_MASK) && !is_iret))) {
2722	/* return to same priledge level */
2723	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2724	get_seg_base(e1, e2),
2725	get_seg_limit(e1, e2),
2726	e2);
2727	} else {
2728	/* return to different priviledge level */
2729	#ifdef TARGET_X86_64
2730	if (shift == 2) {
2731	POPQ(sp, new_esp);
2732	POPQ(sp, new_ss);
2733	new_ss &= 0xffff;
2734	} else
2735	#endif
2736	if (shift == 1) {
2737	/* 32 bits */
2738	POPL(ssp, sp, sp_mask, new_esp);
2739	POPL(ssp, sp, sp_mask, new_ss);
2740	new_ss &= 0xffff;
2741	} else {
2742	/* 16 bits */
2743	POPW(ssp, sp, sp_mask, new_esp);
2744	POPW(ssp, sp, sp_mask, new_ss);
2745	}
2746	#ifdef DEBUG_PCALL
2747	if (loglevel & CPU_LOG_PCALL) {
2748	fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2749	new_ss, new_esp);
2750	}
2751	#endif
2752	if ((new_ss & 0xfffc) == 0) {
2753	#ifdef TARGET_X86_64
2754	/* NULL ss is allowed in long mode if cpl != 3*/
2755	/* XXX: test CS64 ? */
2756	if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2757	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2758	0, 0xffffffff,
2759	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2760	DESC_S_MASK \| (rpl << DESC_DPL_SHIFT) \|
2761	DESC_W_MASK \| DESC_A_MASK);
2762	ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
2763	} else
2764	#endif
2765	{
2766	raise_exception_err(EXCP0D_GPF, 0);
2767	}
2768	} else {
2769	if ((new_ss & 3) != rpl)
2770	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2771	if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2772	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2773	if (!(ss_e2 & DESC_S_MASK) \|\|
2774	(ss_e2 & DESC_CS_MASK) \|\|
2775	!(ss_e2 & DESC_W_MASK))
2776	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2777	dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2778	if (dpl != rpl)
2779	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2780	if (!(ss_e2 & DESC_P_MASK))
2781	raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2782	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2783	get_seg_base(ss_e1, ss_e2),
2784	get_seg_limit(ss_e1, ss_e2),
2785	ss_e2);
2786	}
2787
2788	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2789	get_seg_base(e1, e2),
2790	get_seg_limit(e1, e2),
2791	e2);
2792	cpu_x86_set_cpl(env, rpl);
2793	sp = new_esp;
2794	#ifdef TARGET_X86_64
2795	if (env->hflags & HF_CS64_MASK)
2796	sp_mask = -1;
2797	else
2798	#endif
2799	sp_mask = get_sp_mask(ss_e2);
2800
2801	/* validate data segments */
2802	validate_seg(R_ES, rpl);
2803	validate_seg(R_DS, rpl);
2804	validate_seg(R_FS, rpl);
2805	validate_seg(R_GS, rpl);
2806
2807	sp += addend;
2808	}
2809	SET_ESP(sp, sp_mask);
2810	env->eip = new_eip;
2811	if (is_iret) {
2812	/* NOTE: 'cpl' is the _old_ CPL */
2813	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2814	if (cpl == 0)
2815	#ifdef VBOX
2816	eflags_mask \|= IOPL_MASK \| VIF_MASK \| VIP_MASK;
2817	#else
2818	eflags_mask \|= IOPL_MASK;
2819	#endif
2820	iopl = (env->eflags >> IOPL_SHIFT) & 3;
2821	if (cpl <= iopl)
2822	eflags_mask \|= IF_MASK;
2823	if (shift == 0)
2824	eflags_mask &= 0xffff;
2825	load_eflags(new_eflags, eflags_mask);
2826	}
2827	return;
2828
2829	return_to_vm86:
2830
2831	#if 0 // defined(VBOX) && defined(DEBUG)
2832	printf("V86: new CS %04X\n", new_cs);
2833	printf("V86: Descriptor %08X:%08X\n", e2, e1);
2834	printf("V86: new EIP %08X\n", new_eip);
2835	printf("V86: new EFLAGS %08X\n", new_eflags);
2836	#endif
2837
2838	POPL(ssp, sp, sp_mask, new_esp);
2839	POPL(ssp, sp, sp_mask, new_ss);
2840	POPL(ssp, sp, sp_mask, new_es);
2841	POPL(ssp, sp, sp_mask, new_ds);
2842	POPL(ssp, sp, sp_mask, new_fs);
2843	POPL(ssp, sp, sp_mask, new_gs);
2844
2845	/* modify processor state */
2846	load_eflags(new_eflags, TF_MASK \| AC_MASK \| ID_MASK \|
2847	IF_MASK \| IOPL_MASK \| VM_MASK \| NT_MASK \| VIF_MASK \| VIP_MASK);
2848	load_seg_vm(R_CS, new_cs & 0xffff);
2849	cpu_x86_set_cpl(env, 3);
2850	load_seg_vm(R_SS, new_ss & 0xffff);
2851	load_seg_vm(R_ES, new_es & 0xffff);
2852	load_seg_vm(R_DS, new_ds & 0xffff);
2853	load_seg_vm(R_FS, new_fs & 0xffff);
2854	load_seg_vm(R_GS, new_gs & 0xffff);
2855
2856	env->eip = new_eip & 0xffff;
2857	ESP = new_esp;
2858	}
2859
2860	void helper_iret_protected(int shift, int next_eip)
2861	{
2862	int tss_selector, type;
2863	uint32_t e1, e2;
2864
2865	#ifdef VBOX
2866	remR3TrapClear(env->pVM);
2867	#endif
2868
2869	/* specific case for TSS */
2870	if (env->eflags & NT_MASK) {
2871	#ifdef TARGET_X86_64
2872	if (env->hflags & HF_LMA_MASK)
2873	raise_exception_err(EXCP0D_GPF, 0);
2874	#endif
2875	tss_selector = lduw_kernel(env->tr.base + 0);
2876	if (tss_selector & 4)
2877	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2878	if (load_segment(&e1, &e2, tss_selector) != 0)
2879	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2880	type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2881	/* NOTE: we check both segment and busy TSS */
2882	if (type != 3)
2883	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2884	switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2885	} else {
2886	helper_ret_protected(shift, 1, 0);
2887	}
2888	#ifdef USE_KQEMU
2889	if (kqemu_is_ok(env)) {
2890	CC_OP = CC_OP_EFLAGS;
2891	env->exception_index = -1;
2892	cpu_loop_exit();
2893	}
2894	#endif
2895	}
2896
2897	void helper_lret_protected(int shift, int addend)
2898	{
2899	helper_ret_protected(shift, 0, addend);
2900	#ifdef USE_KQEMU
2901	if (kqemu_is_ok(env)) {
2902	env->exception_index = -1;
2903	cpu_loop_exit();
2904	}
2905	#endif
2906	}
2907
2908	void helper_sysenter(void)
2909	{
2910	if (env->sysenter_cs == 0) {
2911	raise_exception_err(EXCP0D_GPF, 0);
2912	}
2913	env->eflags &= ~(VM_MASK \| IF_MASK \| RF_MASK);
2914	cpu_x86_set_cpl(env, 0);
2915	cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2916	0, 0xffffffff,
2917	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2918	DESC_S_MASK \|
2919	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2920	cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2921	0, 0xffffffff,
2922	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2923	DESC_S_MASK \|
2924	DESC_W_MASK \| DESC_A_MASK);
2925	ESP = env->sysenter_esp;
2926	EIP = env->sysenter_eip;
2927	}
2928
2929	void helper_sysexit(void)
2930	{
2931	int cpl;
2932
2933	cpl = env->hflags & HF_CPL_MASK;
2934	if (env->sysenter_cs == 0 \|\| cpl != 0) {
2935	raise_exception_err(EXCP0D_GPF, 0);
2936	}
2937	cpu_x86_set_cpl(env, 3);
2938	cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) \| 3,
2939	0, 0xffffffff,
2940	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2941	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2942	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2943	cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) \| 3,
2944	0, 0xffffffff,
2945	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2946	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2947	DESC_W_MASK \| DESC_A_MASK);
2948	ESP = ECX;
2949	EIP = EDX;
2950	#ifdef USE_KQEMU
2951	if (kqemu_is_ok(env)) {
2952	env->exception_index = -1;
2953	cpu_loop_exit();
2954	}
2955	#endif
2956	}
2957
2958	void helper_movl_crN_T0(int reg)
2959	{
2960	#if !defined(CONFIG_USER_ONLY)
2961	switch(reg) {
2962	case 0:
2963	cpu_x86_update_cr0(env, T0);
2964	break;
2965	case 3:
2966	cpu_x86_update_cr3(env, T0);
2967	break;
2968	case 4:
2969	cpu_x86_update_cr4(env, T0);
2970	break;
2971	case 8:
2972	cpu_set_apic_tpr(env, T0);
2973	break;
2974	default:
2975	env->cr[reg] = T0;
2976	break;
2977	}
2978	#endif
2979	}
2980
2981	/* XXX: do more */
2982	void helper_movl_drN_T0(int reg)
2983	{
2984	env->dr[reg] = T0;
2985	}
2986
2987	void helper_invlpg(target_ulong addr)
2988	{
2989	cpu_x86_flush_tlb(env, addr);
2990	}
2991
2992	void helper_rdtsc(void)
2993	{
2994	uint64_t val;
2995
2996	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2997	raise_exception(EXCP0D_GPF);
2998	}
2999	val = cpu_get_tsc(env);
3000	EAX = (uint32_t)(val);
3001	EDX = (uint32_t)(val >> 32);
3002	}
3003
3004	#if defined(CONFIG_USER_ONLY)
3005	void helper_wrmsr(void)
3006	{
3007	}
3008
3009	void helper_rdmsr(void)
3010	{
3011	}
3012	#else
3013	void helper_wrmsr(void)
3014	{
3015	uint64_t val;
3016
3017	val = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
3018
3019	switch((uint32_t)ECX) {
3020	case MSR_IA32_SYSENTER_CS:
3021	env->sysenter_cs = val & 0xffff;
3022	break;
3023	case MSR_IA32_SYSENTER_ESP:
3024	env->sysenter_esp = val;
3025	break;
3026	case MSR_IA32_SYSENTER_EIP:
3027	env->sysenter_eip = val;
3028	break;
3029	case MSR_IA32_APICBASE:
3030	cpu_set_apic_base(env, val);
3031	break;
3032	case MSR_EFER:
3033	{
3034	uint64_t update_mask;
3035	update_mask = 0;
3036	if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
3037	update_mask \|= MSR_EFER_SCE;
3038	if (env->cpuid_ext2_features & CPUID_EXT2_LM)
3039	update_mask \|= MSR_EFER_LME;
3040	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
3041	update_mask \|= MSR_EFER_FFXSR;
3042	if (env->cpuid_ext2_features & CPUID_EXT2_NX)
3043	update_mask \|= MSR_EFER_NXE;
3044	env->efer = (env->efer & ~update_mask) \|
3045	(val & update_mask);
3046	}
3047	break;
3048	case MSR_STAR:
3049	env->star = val;
3050	break;
3051	case MSR_PAT:
3052	env->pat = val;
3053	break;
3054	#ifdef TARGET_X86_64
3055	case MSR_LSTAR:
3056	env->lstar = val;
3057	break;
3058	case MSR_CSTAR:
3059	env->cstar = val;
3060	break;
3061	case MSR_FMASK:
3062	env->fmask = val;
3063	break;
3064	case MSR_FSBASE:
3065	env->segs[R_FS].base = val;
3066	break;
3067	case MSR_GSBASE:
3068	env->segs[R_GS].base = val;
3069	break;
3070	case MSR_KERNELGSBASE:
3071	env->kernelgsbase = val;
3072	break;
3073	#endif
3074	default:
3075	{
3076	uint32_t ecx = (uint32_t)ECX;
3077	/* In X2APIC specification this range is reserved for APIC control. */
3078	if ((ecx >= MSR_APIC_RANGE_START) && (ecx < MSR_APIC_RANGE_END))
3079	{
3080	cpu_apic_wrmsr(env, ecx, val);
3081	}
3082	else
3083	{
3084	/* @todo: exception ? */
3085	}
3086	break;
3087	}
3088	}
3089	}
3090
3091	void helper_rdmsr(void)
3092	{
3093	uint64_t val;
3094	switch((uint32_t)ECX) {
3095	case MSR_IA32_SYSENTER_CS:
3096	val = env->sysenter_cs;
3097	break;
3098	case MSR_IA32_SYSENTER_ESP:
3099	val = env->sysenter_esp;
3100	break;
3101	case MSR_IA32_SYSENTER_EIP:
3102	val = env->sysenter_eip;
3103	break;
3104	case MSR_IA32_APICBASE:
3105	val = cpu_get_apic_base(env);
3106	break;
3107	case MSR_EFER:
3108	val = env->efer;
3109	break;
3110	case MSR_STAR:
3111	val = env->star;
3112	break;
3113	case MSR_PAT:
3114	val = env->pat;
3115	break;
3116	#ifdef TARGET_X86_64
3117	case MSR_LSTAR:
3118	val = env->lstar;
3119	break;
3120	case MSR_CSTAR:
3121	val = env->cstar;
3122	break;
3123	case MSR_FMASK:
3124	val = env->fmask;
3125	break;
3126	case MSR_FSBASE:
3127	val = env->segs[R_FS].base;
3128	break;
3129	case MSR_GSBASE:
3130	val = env->segs[R_GS].base;
3131	break;
3132	case MSR_KERNELGSBASE:
3133	val = env->kernelgsbase;
3134	break;
3135	#endif
3136	default:
3137	{
3138	uint32_t ecx = (uint32_t)ECX;
3139	/* In X2APIC specification this range is reserved for APIC control. */
3140	if ((ecx >= MSR_APIC_RANGE_START) && (ecx < MSR_APIC_RANGE_END))
3141	{
3142	val = cpu_apic_rdmsr(env, ecx);
3143	}
3144	else
3145	{
3146	/** @todo: exception ? */
3147	val = 0;
3148	break;
3149	}
3150	}
3151	}
3152	EAX = (uint32_t)(val);
3153	EDX = (uint32_t)(val >> 32);
3154	}
3155	#endif
3156
3157	void helper_lsl(void)
3158	{
3159	unsigned int selector, limit;
3160	uint32_t e1, e2, eflags;
3161	int rpl, dpl, cpl, type;
3162
3163	eflags = cc_table[CC_OP].compute_all();
3164	selector = T0 & 0xffff;
3165	if (load_segment(&e1, &e2, selector) != 0)
3166	goto fail;
3167	rpl = selector & 3;
3168	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3169	cpl = env->hflags & HF_CPL_MASK;
3170	if (e2 & DESC_S_MASK) {
3171	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3172	/* conforming */
3173	} else {
3174	if (dpl < cpl \|\| dpl < rpl)
3175	goto fail;
3176	}
3177	} else {
3178	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3179	switch(type) {
3180	case 1:
3181	case 2:
3182	case 3:
3183	case 9:
3184	case 11:
3185	break;
3186	default:
3187	goto fail;
3188	}
3189	if (dpl < cpl \|\| dpl < rpl) {
3190	fail:
3191	CC_SRC = eflags & ~CC_Z;
3192	return;
3193	}
3194	}
3195	limit = get_seg_limit(e1, e2);
3196	T1 = limit;
3197	CC_SRC = eflags \| CC_Z;
3198	}
3199
3200	void helper_lar(void)
3201	{
3202	unsigned int selector;
3203	uint32_t e1, e2, eflags;
3204	int rpl, dpl, cpl, type;
3205
3206	eflags = cc_table[CC_OP].compute_all();
3207	selector = T0 & 0xffff;
3208	if ((selector & 0xfffc) == 0)
3209	goto fail;
3210	if (load_segment(&e1, &e2, selector) != 0)
3211	goto fail;
3212	rpl = selector & 3;
3213	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3214	cpl = env->hflags & HF_CPL_MASK;
3215	if (e2 & DESC_S_MASK) {
3216	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3217	/* conforming */
3218	} else {
3219	if (dpl < cpl \|\| dpl < rpl)
3220	goto fail;
3221	}
3222	} else {
3223	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3224	switch(type) {
3225	case 1:
3226	case 2:
3227	case 3:
3228	case 4:
3229	case 5:
3230	case 9:
3231	case 11:
3232	case 12:
3233	break;
3234	default:
3235	goto fail;
3236	}
3237	if (dpl < cpl \|\| dpl < rpl) {
3238	fail:
3239	CC_SRC = eflags & ~CC_Z;
3240	return;
3241	}
3242	}
3243	T1 = e2 & 0x00f0ff00;
3244	CC_SRC = eflags \| CC_Z;
3245	}
3246
3247	void helper_verr(void)
3248	{
3249	unsigned int selector;
3250	uint32_t e1, e2, eflags;
3251	int rpl, dpl, cpl;
3252
3253	eflags = cc_table[CC_OP].compute_all();
3254	selector = T0 & 0xffff;
3255	if ((selector & 0xfffc) == 0)
3256	goto fail;
3257	if (load_segment(&e1, &e2, selector) != 0)
3258	goto fail;
3259	if (!(e2 & DESC_S_MASK))
3260	goto fail;
3261	rpl = selector & 3;
3262	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3263	cpl = env->hflags & HF_CPL_MASK;
3264	if (e2 & DESC_CS_MASK) {
3265	if (!(e2 & DESC_R_MASK))
3266	goto fail;
3267	if (!(e2 & DESC_C_MASK)) {
3268	if (dpl < cpl \|\| dpl < rpl)
3269	goto fail;
3270	}
3271	} else {
3272	if (dpl < cpl \|\| dpl < rpl) {
3273	fail:
3274	CC_SRC = eflags & ~CC_Z;
3275	return;
3276	}
3277	}
3278	CC_SRC = eflags \| CC_Z;
3279	}
3280
3281	void helper_verw(void)
3282	{
3283	unsigned int selector;
3284	uint32_t e1, e2, eflags;
3285	int rpl, dpl, cpl;
3286
3287	eflags = cc_table[CC_OP].compute_all();
3288	selector = T0 & 0xffff;
3289	if ((selector & 0xfffc) == 0)
3290	goto fail;
3291	if (load_segment(&e1, &e2, selector) != 0)
3292	goto fail;
3293	if (!(e2 & DESC_S_MASK))
3294	goto fail;
3295	rpl = selector & 3;
3296	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3297	cpl = env->hflags & HF_CPL_MASK;
3298	if (e2 & DESC_CS_MASK) {
3299	goto fail;
3300	} else {
3301	if (dpl < cpl \|\| dpl < rpl)
3302	goto fail;
3303	if (!(e2 & DESC_W_MASK)) {
3304	fail:
3305	CC_SRC = eflags & ~CC_Z;
3306	return;
3307	}
3308	}
3309	CC_SRC = eflags \| CC_Z;
3310	}
3311
3312	/* FPU helpers */
3313
3314	void helper_fldt_ST0_A0(void)
3315	{
3316	int new_fpstt;
3317	new_fpstt = (env->fpstt - 1) & 7;
3318	env->fpregs[new_fpstt].d = helper_fldt(A0);
3319	env->fpstt = new_fpstt;
3320	env->fptags[new_fpstt] = 0; /* validate stack entry */
3321	}
3322
3323	void helper_fstt_ST0_A0(void)
3324	{
3325	helper_fstt(ST0, A0);
3326	}
3327
3328	void fpu_set_exception(int mask)
3329	{
3330	env->fpus \|= mask;
3331	if (env->fpus & (~env->fpuc & FPUC_EM))
3332	env->fpus \|= FPUS_SE \| FPUS_B;
3333	}
3334
3335	CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
3336	{
3337	if (b == 0.0)
3338	fpu_set_exception(FPUS_ZE);
3339	return a / b;
3340	}
3341
3342	void fpu_raise_exception(void)
3343	{
3344	if (env->cr[0] & CR0_NE_MASK) {
3345	raise_exception(EXCP10_COPR);
3346	}
3347	#if !defined(CONFIG_USER_ONLY)
3348	else {
3349	cpu_set_ferr(env);
3350	}
3351	#endif
3352	}
3353
3354	/* BCD ops */
3355
3356	void helper_fbld_ST0_A0(void)
3357	{
3358	CPU86_LDouble tmp;
3359	uint64_t val;
3360	unsigned int v;
3361	int i;
3362
3363	val = 0;
3364	for(i = 8; i >= 0; i--) {
3365	v = ldub(A0 + i);
3366	val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
3367	}
3368	tmp = val;
3369	if (ldub(A0 + 9) & 0x80)
3370	tmp = -tmp;
3371	fpush();
3372	ST0 = tmp;
3373	}
3374
3375	void helper_fbst_ST0_A0(void)
3376	{
3377	int v;
3378	target_ulong mem_ref, mem_end;
3379	int64_t val;
3380
3381	val = floatx_to_int64(ST0, &env->fp_status);
3382	mem_ref = A0;
3383	mem_end = mem_ref + 9;
3384	if (val < 0) {
3385	stb(mem_end, 0x80);
3386	val = -val;
3387	} else {
3388	stb(mem_end, 0x00);
3389	}
3390	while (mem_ref < mem_end) {
3391	if (val == 0)
3392	break;
3393	v = val % 100;
3394	val = val / 100;
3395	v = ((v / 10) << 4) \| (v % 10);
3396	stb(mem_ref++, v);
3397	}
3398	while (mem_ref < mem_end) {
3399	stb(mem_ref++, 0);
3400	}
3401	}
3402
3403	void helper_f2xm1(void)
3404	{
3405	ST0 = pow(2.0,ST0) - 1.0;
3406	}
3407
3408	void helper_fyl2x(void)
3409	{
3410	CPU86_LDouble fptemp;
3411
3412	fptemp = ST0;
3413	if (fptemp>0.0){
3414	fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3415	ST1 *= fptemp;
3416	fpop();
3417	} else {
3418	env->fpus &= (~0x4700);
3419	env->fpus \|= 0x400;
3420	}
3421	}
3422
3423	void helper_fptan(void)
3424	{
3425	CPU86_LDouble fptemp;
3426
3427	fptemp = ST0;
3428	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3429	env->fpus \|= 0x400;
3430	} else {
3431	ST0 = tan(fptemp);
3432	fpush();
3433	ST0 = 1.0;
3434	env->fpus &= (~0x400); /* C2 <-- 0 */
3435	/* the above code is for \|arg\| < 2*52 only /
3436	}
3437	}
3438
3439	void helper_fpatan(void)
3440	{
3441	CPU86_LDouble fptemp, fpsrcop;
3442
3443	fpsrcop = ST1;
3444	fptemp = ST0;
3445	ST1 = atan2(fpsrcop,fptemp);
3446	fpop();
3447	}
3448
3449	void helper_fxtract(void)
3450	{
3451	CPU86_LDoubleU temp;
3452	unsigned int expdif;
3453
3454	temp.d = ST0;
3455	expdif = EXPD(temp) - EXPBIAS;
3456	/DP exponent bias/
3457	ST0 = expdif;
3458	fpush();
3459	BIASEXPONENT(temp);
3460	ST0 = temp.d;
3461	}
3462
3463	void helper_fprem1(void)
3464	{
3465	CPU86_LDouble dblq, fpsrcop, fptemp;
3466	CPU86_LDoubleU fpsrcop1, fptemp1;
3467	int expdif;
3468	int q;
3469
3470	fpsrcop = ST0;
3471	fptemp = ST1;
3472	fpsrcop1.d = fpsrcop;
3473	fptemp1.d = fptemp;
3474	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3475	if (expdif < 53) {
3476	dblq = fpsrcop / fptemp;
3477	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3478	ST0 = fpsrcop - fptemp*dblq;
3479	q = (int)dblq; /* cutting off top bits is assumed here */
3480	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3481	/* (C0,C1,C3) <-- (q2,q1,q0) */
3482	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3483	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3484	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3485	} else {
3486	env->fpus \|= 0x400; /* C2 <-- 1 */
3487	fptemp = pow(2.0, expdif-50);
3488	fpsrcop = (ST0 / ST1) / fptemp;
3489	/* fpsrcop = integer obtained by rounding to the nearest */
3490	fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3491	floor(fpsrcop): ceil(fpsrcop);
3492	ST0 -= (ST1 * fpsrcop * fptemp);
3493	}
3494	}
3495
3496	void helper_fprem(void)
3497	{
3498	CPU86_LDouble dblq, fpsrcop, fptemp;
3499	CPU86_LDoubleU fpsrcop1, fptemp1;
3500	int expdif;
3501	int q;
3502
3503	fpsrcop = ST0;
3504	fptemp = ST1;
3505	fpsrcop1.d = fpsrcop;
3506	fptemp1.d = fptemp;
3507	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3508	if ( expdif < 53 ) {
3509	dblq = fpsrcop / fptemp;
3510	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3511	ST0 = fpsrcop - fptemp*dblq;
3512	q = (int)dblq; /* cutting off top bits is assumed here */
3513	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3514	/* (C0,C1,C3) <-- (q2,q1,q0) */
3515	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3516	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3517	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3518	} else {
3519	env->fpus \|= 0x400; /* C2 <-- 1 */
3520	fptemp = pow(2.0, expdif-50);
3521	fpsrcop = (ST0 / ST1) / fptemp;
3522	/* fpsrcop = integer obtained by chopping */
3523	fpsrcop = (fpsrcop < 0.0)?
3524	-(floor(fabs(fpsrcop))): floor(fpsrcop);
3525	ST0 -= (ST1 * fpsrcop * fptemp);
3526	}
3527	}
3528
3529	void helper_fyl2xp1(void)
3530	{
3531	CPU86_LDouble fptemp;
3532
3533	fptemp = ST0;
3534	if ((fptemp+1.0)>0.0) {
3535	fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3536	ST1 *= fptemp;
3537	fpop();
3538	} else {
3539	env->fpus &= (~0x4700);
3540	env->fpus \|= 0x400;
3541	}
3542	}
3543
3544	void helper_fsqrt(void)
3545	{
3546	CPU86_LDouble fptemp;
3547
3548	fptemp = ST0;
3549	if (fptemp<0.0) {
3550	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3551	env->fpus \|= 0x400;
3552	}
3553	ST0 = sqrt(fptemp);
3554	}
3555
3556	void helper_fsincos(void)
3557	{
3558	CPU86_LDouble fptemp;
3559
3560	fptemp = ST0;
3561	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3562	env->fpus \|= 0x400;
3563	} else {
3564	ST0 = sin(fptemp);
3565	fpush();
3566	ST0 = cos(fptemp);
3567	env->fpus &= (~0x400); /* C2 <-- 0 */
3568	/* the above code is for \|arg\| < 2*63 only /
3569	}
3570	}
3571
3572	void helper_frndint(void)
3573	{
3574	ST0 = floatx_round_to_int(ST0, &env->fp_status);
3575	}
3576
3577	void helper_fscale(void)
3578	{
3579	ST0 = ldexp (ST0, (int)(ST1));
3580	}
3581
3582	void helper_fsin(void)
3583	{
3584	CPU86_LDouble fptemp;
3585
3586	fptemp = ST0;
3587	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3588	env->fpus \|= 0x400;
3589	} else {
3590	ST0 = sin(fptemp);
3591	env->fpus &= (~0x400); /* C2 <-- 0 */
3592	/* the above code is for \|arg\| < 2*53 only /
3593	}
3594	}
3595
3596	void helper_fcos(void)
3597	{
3598	CPU86_LDouble fptemp;
3599
3600	fptemp = ST0;
3601	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3602	env->fpus \|= 0x400;
3603	} else {
3604	ST0 = cos(fptemp);
3605	env->fpus &= (~0x400); /* C2 <-- 0 */
3606	/* the above code is for \|arg5 < 2*63 only /
3607	}
3608	}
3609
3610	void helper_fxam_ST0(void)
3611	{
3612	CPU86_LDoubleU temp;
3613	int expdif;
3614
3615	temp.d = ST0;
3616
3617	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3618	if (SIGND(temp))
3619	env->fpus \|= 0x200; /* C1 <-- 1 */
3620
3621	/* XXX: test fptags too */
3622	expdif = EXPD(temp);
3623	if (expdif == MAXEXPD) {
3624	#ifdef USE_X86LDOUBLE
3625	if (MANTD(temp) == 0x8000000000000000ULL)
3626	#else
3627	if (MANTD(temp) == 0)
3628	#endif
3629	env->fpus \|= 0x500 /Infinity/;
3630	else
3631	env->fpus \|= 0x100 /NaN/;
3632	} else if (expdif == 0) {
3633	if (MANTD(temp) == 0)
3634	env->fpus \|= 0x4000 /Zero/;
3635	else
3636	env->fpus \|= 0x4400 /Denormal/;
3637	} else {
3638	env->fpus \|= 0x400;
3639	}
3640	}
3641
3642	void helper_fstenv(target_ulong ptr, int data32)
3643	{
3644	int fpus, fptag, exp, i;
3645	uint64_t mant;
3646	CPU86_LDoubleU tmp;
3647
3648	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3649	fptag = 0;
3650	for (i=7; i>=0; i--) {
3651	fptag <<= 2;
3652	if (env->fptags[i]) {
3653	fptag \|= 3;
3654	} else {
3655	tmp.d = env->fpregs[i].d;
3656	exp = EXPD(tmp);
3657	mant = MANTD(tmp);
3658	if (exp == 0 && mant == 0) {
3659	/* zero */
3660	fptag \|= 1;
3661	} else if (exp == 0 \|\| exp == MAXEXPD
3662	#ifdef USE_X86LDOUBLE
3663	\|\| (mant & (1LL << 63)) == 0
3664	#endif
3665	) {
3666	/* NaNs, infinity, denormal */
3667	fptag \|= 2;
3668	}
3669	}
3670	}
3671	if (data32) {
3672	/* 32 bit */
3673	stl(ptr, env->fpuc);
3674	stl(ptr + 4, fpus);
3675	stl(ptr + 8, fptag);
3676	stl(ptr + 12, 0); /* fpip */
3677	stl(ptr + 16, 0); /* fpcs */
3678	stl(ptr + 20, 0); /* fpoo */
3679	stl(ptr + 24, 0); /* fpos */
3680	} else {
3681	/* 16 bit */
3682	stw(ptr, env->fpuc);
3683	stw(ptr + 2, fpus);
3684	stw(ptr + 4, fptag);
3685	stw(ptr + 6, 0);
3686	stw(ptr + 8, 0);
3687	stw(ptr + 10, 0);
3688	stw(ptr + 12, 0);
3689	}
3690	}
3691
3692	void helper_fldenv(target_ulong ptr, int data32)
3693	{
3694	int i, fpus, fptag;
3695
3696	if (data32) {
3697	env->fpuc = lduw(ptr);
3698	fpus = lduw(ptr + 4);
3699	fptag = lduw(ptr + 8);
3700	}
3701	else {
3702	env->fpuc = lduw(ptr);
3703	fpus = lduw(ptr + 2);
3704	fptag = lduw(ptr + 4);
3705	}
3706	env->fpstt = (fpus >> 11) & 7;
3707	env->fpus = fpus & ~0x3800;
3708	for(i = 0;i < 8; i++) {
3709	env->fptags[i] = ((fptag & 3) == 3);
3710	fptag >>= 2;
3711	}
3712	}
3713
3714	void helper_fsave(target_ulong ptr, int data32)
3715	{
3716	CPU86_LDouble tmp;
3717	int i;
3718
3719	helper_fstenv(ptr, data32);
3720
3721	ptr += (14 << data32);
3722	for(i = 0;i < 8; i++) {
3723	tmp = ST(i);
3724	helper_fstt(tmp, ptr);
3725	ptr += 10;
3726	}
3727
3728	/* fninit */
3729	env->fpus = 0;
3730	env->fpstt = 0;
3731	env->fpuc = 0x37f;
3732	env->fptags[0] = 1;
3733	env->fptags[1] = 1;
3734	env->fptags[2] = 1;
3735	env->fptags[3] = 1;
3736	env->fptags[4] = 1;
3737	env->fptags[5] = 1;
3738	env->fptags[6] = 1;
3739	env->fptags[7] = 1;
3740	}
3741
3742	void helper_frstor(target_ulong ptr, int data32)
3743	{
3744	CPU86_LDouble tmp;
3745	int i;
3746
3747	helper_fldenv(ptr, data32);
3748	ptr += (14 << data32);
3749
3750	for(i = 0;i < 8; i++) {
3751	tmp = helper_fldt(ptr);
3752	ST(i) = tmp;
3753	ptr += 10;
3754	}
3755	}
3756
3757	void helper_fxsave(target_ulong ptr, int data64)
3758	{
3759	int fpus, fptag, i, nb_xmm_regs;
3760	CPU86_LDouble tmp;
3761	target_ulong addr;
3762
3763	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3764	fptag = 0;
3765	for(i = 0; i < 8; i++) {
3766	fptag \|= (env->fptags[i] << i);
3767	}
3768	stw(ptr, env->fpuc);
3769	stw(ptr + 2, fpus);
3770	stw(ptr + 4, fptag ^ 0xff);
3771
3772	addr = ptr + 0x20;
3773	for(i = 0;i < 8; i++) {
3774	tmp = ST(i);
3775	helper_fstt(tmp, addr);
3776	addr += 16;
3777	}
3778
3779	if (env->cr[4] & CR4_OSFXSR_MASK) {
3780	/* XXX: finish it */
3781	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3782	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3783	nb_xmm_regs = 8 << data64;
3784	addr = ptr + 0xa0;
3785	for(i = 0; i < nb_xmm_regs; i++) {
3786	stq(addr, env->xmm_regs[i].XMM_Q(0));
3787	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3788	addr += 16;
3789	}
3790	}
3791	}
3792
3793	void helper_fxrstor(target_ulong ptr, int data64)
3794	{
3795	int i, fpus, fptag, nb_xmm_regs;
3796	CPU86_LDouble tmp;
3797	target_ulong addr;
3798
3799	env->fpuc = lduw(ptr);
3800	fpus = lduw(ptr + 2);
3801	fptag = lduw(ptr + 4);
3802	env->fpstt = (fpus >> 11) & 7;
3803	env->fpus = fpus & ~0x3800;
3804	fptag ^= 0xff;
3805	for(i = 0;i < 8; i++) {
3806	env->fptags[i] = ((fptag >> i) & 1);
3807	}
3808
3809	addr = ptr + 0x20;
3810	for(i = 0;i < 8; i++) {
3811	tmp = helper_fldt(addr);
3812	ST(i) = tmp;
3813	addr += 16;
3814	}
3815
3816	if (env->cr[4] & CR4_OSFXSR_MASK) {
3817	/* XXX: finish it */
3818	env->mxcsr = ldl(ptr + 0x18);
3819	//ldl(ptr + 0x1c);
3820	nb_xmm_regs = 8 << data64;
3821	addr = ptr + 0xa0;
3822	for(i = 0; i < nb_xmm_regs; i++) {
3823	#if !defined(VBOX) \|\| __GNUC__ < 4
3824	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3825	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3826	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3827	# if 1
3828	env->xmm_regs[i].XMM_L(0) = ldl(addr);
3829	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3830	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3831	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3832	# else
3833	/* this works fine on Mac OS X, gcc 4.0.1 */
3834	uint64_t u64 = ldq(addr);
3835	env->xmm_regs[i].XMM_Q(0);
3836	u64 = ldq(addr + 4);
3837	env->xmm_regs[i].XMM_Q(1) = u64;
3838	# endif
3839	#endif
3840	addr += 16;
3841	}
3842	}
3843	}
3844
3845	#ifndef USE_X86LDOUBLE
3846
3847	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3848	{
3849	CPU86_LDoubleU temp;
3850	int e;
3851
3852	temp.d = f;
3853	/* mantissa */
3854	*pmant = (MANTD(temp) << 11) \| (1LL << 63);
3855	/* exponent + sign */
3856	e = EXPD(temp) - EXPBIAS + 16383;
3857	e \|= SIGND(temp) >> 16;
3858	*pexp = e;
3859	}
3860
3861	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3862	{
3863	CPU86_LDoubleU temp;
3864	int e;
3865	uint64_t ll;
3866
3867	/* XXX: handle overflow ? */
3868	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3869	e \|= (upper >> 4) & 0x800; /* sign */
3870	ll = (mant >> 11) & ((1LL << 52) - 1);
3871	#ifdef __arm__
3872	temp.l.upper = (e << 20) \| (ll >> 32);
3873	temp.l.lower = ll;
3874	#else
3875	temp.ll = ll \| ((uint64_t)e << 52);
3876	#endif
3877	return temp.d;
3878	}
3879
3880	#else
3881
3882	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3883	{
3884	CPU86_LDoubleU temp;
3885
3886	temp.d = f;
3887	*pmant = temp.l.lower;
3888	*pexp = temp.l.upper;
3889	}
3890
3891	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3892	{
3893	CPU86_LDoubleU temp;
3894
3895	temp.l.upper = upper;
3896	temp.l.lower = mant;
3897	return temp.d;
3898	}
3899	#endif
3900
3901	#ifdef TARGET_X86_64
3902
3903	//#define DEBUG_MULDIV
3904
3905	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3906	{
3907	*plow += a;
3908	/* carry test */
3909	if (*plow < a)
3910	(*phigh)++;
3911	*phigh += b;
3912	}
3913
3914	static void neg128(uint64_t plow, uint64_t phigh)
3915	{
3916	plow = ~ plow;
3917	phigh = ~ phigh;
3918	add128(plow, phigh, 1, 0);
3919	}
3920
3921	static void mul64(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3922	{
3923	uint32_t a0, a1, b0, b1;
3924	uint64_t v;
3925
3926	a0 = a;
3927	a1 = a >> 32;
3928
3929	b0 = b;
3930	b1 = b >> 32;
3931
3932	v = (uint64_t)a0 * (uint64_t)b0;
3933	*plow = v;
3934	*phigh = 0;
3935
3936	v = (uint64_t)a0 * (uint64_t)b1;
3937	add128(plow, phigh, v << 32, v >> 32);
3938
3939	v = (uint64_t)a1 * (uint64_t)b0;
3940	add128(plow, phigh, v << 32, v >> 32);
3941
3942	v = (uint64_t)a1 * (uint64_t)b1;
3943	*phigh += v;
3944	#ifdef DEBUG_MULDIV
3945	printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
3946	a, b, phigh, plow);
3947	#endif
3948	}
3949
3950	static void imul64(uint64_t plow, uint64_t phigh, int64_t a, int64_t b)
3951	{
3952	int sa, sb;
3953	sa = (a < 0);
3954	if (sa)
3955	a = -a;
3956	sb = (b < 0);
3957	if (sb)
3958	b = -b;
3959	mul64(plow, phigh, a, b);
3960	if (sa ^ sb) {
3961	neg128(plow, phigh);
3962	}
3963	}
3964
3965	/* return TRUE if overflow */
3966	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
3967	{
3968	uint64_t q, r, a1, a0;
3969	int i, qb, ab;
3970
3971	a0 = *plow;
3972	a1 = *phigh;
3973	if (a1 == 0) {
3974	q = a0 / b;
3975	r = a0 % b;
3976	*plow = q;
3977	*phigh = r;
3978	} else {
3979	if (a1 >= b)
3980	return 1;
3981	/* XXX: use a better algorithm */
3982	for(i = 0; i < 64; i++) {
3983	ab = a1 >> 63;
3984	a1 = (a1 << 1) \| (a0 >> 63);
3985	if (ab \|\| a1 >= b) {
3986	a1 -= b;
3987	qb = 1;
3988	} else {
3989	qb = 0;
3990	}
3991	a0 = (a0 << 1) \| qb;
3992	}
3993	#if defined(DEBUG_MULDIV)
3994	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
3995	phigh, plow, b, a0, a1);
3996	#endif
3997	*plow = a0;
3998	*phigh = a1;
3999	}
4000	return 0;
4001	}
4002
4003	/* return TRUE if overflow */
4004	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
4005	{
4006	int sa, sb;
4007	sa = ((int64_t)*phigh < 0);
4008	if (sa)
4009	neg128(plow, phigh);
4010	sb = (b < 0);
4011	if (sb)
4012	b = -b;
4013	if (div64(plow, phigh, b) != 0)
4014	return 1;
4015	if (sa ^ sb) {
4016	if (*plow > (1ULL << 63))
4017	return 1;
4018	plow = - plow;
4019	} else {
4020	if (*plow >= (1ULL << 63))
4021	return 1;
4022	}
4023	if (sa)
4024	phigh = - phigh;
4025	return 0;
4026	}
4027
4028	void helper_mulq_EAX_T0(void)
4029	{
4030	uint64_t r0, r1;
4031
4032	mul64(&r0, &r1, EAX, T0);
4033	EAX = r0;
4034	EDX = r1;
4035	CC_DST = r0;
4036	CC_SRC = r1;
4037	}
4038
4039	void helper_imulq_EAX_T0(void)
4040	{
4041	uint64_t r0, r1;
4042
4043	imul64(&r0, &r1, EAX, T0);
4044	EAX = r0;
4045	EDX = r1;
4046	CC_DST = r0;
4047	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4048	}
4049
4050	void helper_imulq_T0_T1(void)
4051	{
4052	uint64_t r0, r1;
4053
4054	imul64(&r0, &r1, T0, T1);
4055	T0 = r0;
4056	CC_DST = r0;
4057	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4058	}
4059
4060	void helper_divq_EAX_T0(void)
4061	{
4062	uint64_t r0, r1;
4063	if (T0 == 0) {
4064	raise_exception(EXCP00_DIVZ);
4065	}
4066	r0 = EAX;
4067	r1 = EDX;
4068	if (div64(&r0, &r1, T0))
4069	raise_exception(EXCP00_DIVZ);
4070	EAX = r0;
4071	EDX = r1;
4072	}
4073
4074	void helper_idivq_EAX_T0(void)
4075	{
4076	uint64_t r0, r1;
4077	if (T0 == 0) {
4078	raise_exception(EXCP00_DIVZ);
4079	}
4080	r0 = EAX;
4081	r1 = EDX;
4082	if (idiv64(&r0, &r1, T0))
4083	raise_exception(EXCP00_DIVZ);
4084	EAX = r0;
4085	EDX = r1;
4086	}
4087
4088	void helper_bswapq_T0(void)
4089	{
4090	T0 = bswap64(T0);
4091	}
4092	#endif
4093
4094	void helper_hlt(void)
4095	{
4096	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
4097	env->hflags \|= HF_HALTED_MASK;
4098	env->exception_index = EXCP_HLT;
4099	cpu_loop_exit();
4100	}
4101
4102	void helper_monitor(void)
4103	{
4104	if ((uint32_t)ECX != 0)
4105	raise_exception(EXCP0D_GPF);
4106	/* XXX: store address ? */
4107	}
4108
4109	void helper_mwait(void)
4110	{
4111	if ((uint32_t)ECX != 0)
4112	raise_exception(EXCP0D_GPF);
4113	#ifdef VBOX
4114	helper_hlt();
4115	#else
4116	/* XXX: not complete but not completely erroneous */
4117	if (env->cpu_index != 0 \|\| env->next_cpu != NULL) {
4118	/* more than one CPU: do not sleep because another CPU may
4119	wake this one */
4120	} else {
4121	helper_hlt();
4122	}
4123	#endif
4124	}
4125
4126	float approx_rsqrt(float a)
4127	{
4128	return 1.0 / sqrt(a);
4129	}
4130
4131	float approx_rcp(float a)
4132	{
4133	return 1.0 / a;
4134	}
4135
4136	void update_fp_status(void)
4137	{
4138	int rnd_type;
4139
4140	/* set rounding mode */
4141	switch(env->fpuc & RC_MASK) {
4142	default:
4143	case RC_NEAR:
4144	rnd_type = float_round_nearest_even;
4145	break;
4146	case RC_DOWN:
4147	rnd_type = float_round_down;
4148	break;
4149	case RC_UP:
4150	rnd_type = float_round_up;
4151	break;
4152	case RC_CHOP:
4153	rnd_type = float_round_to_zero;
4154	break;
4155	}
4156	set_float_rounding_mode(rnd_type, &env->fp_status);
4157	#ifdef FLOATX80
4158	switch((env->fpuc >> 8) & 3) {
4159	case 0:
4160	rnd_type = 32;
4161	break;
4162	case 2:
4163	rnd_type = 64;
4164	break;
4165	case 3:
4166	default:
4167	rnd_type = 80;
4168	break;
4169	}
4170	set_floatx80_rounding_precision(rnd_type, &env->fp_status);
4171	#endif
4172	}
4173
4174	#if !defined(CONFIG_USER_ONLY)
4175
4176	#define MMUSUFFIX _mmu
4177	#define GETPC() (__builtin_return_address(0))
4178
4179	#define SHIFT 0
4180	#include "softmmu_template.h"
4181
4182	#define SHIFT 1
4183	#include "softmmu_template.h"
4184
4185	#define SHIFT 2
4186	#include "softmmu_template.h"
4187
4188	#define SHIFT 3
4189	#include "softmmu_template.h"
4190
4191	#endif
4192
4193	/* try to fill the TLB and return an exception if error. If retaddr is
4194	NULL, it means that the function was called in C code (i.e. not
4195	from generated code or from helper.c) */
4196	/* XXX: fix it to restore all registers */
4197	void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
4198	{
4199	TranslationBlock *tb;
4200	int ret;
4201	unsigned long pc;
4202	CPUX86State *saved_env;
4203
4204	/* XXX: hack to restore env in all cases, even if not called from
4205	generated code */
4206	saved_env = env;
4207	env = cpu_single_env;
4208
4209	ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
4210	if (ret) {
4211	if (retaddr) {
4212	/* now we have a real cpu fault */
4213	pc = (unsigned long)retaddr;
4214	tb = tb_find_pc(pc);
4215	if (tb) {
4216	/* the PC is inside the translated code. It means that we have
4217	a virtual CPU fault */
4218	cpu_restore_state(tb, env, pc, NULL);
4219	}
4220	}
4221	if (retaddr)
4222	raise_exception_err(env->exception_index, env->error_code);
4223	else
4224	raise_exception_err_norestore(env->exception_index, env->error_code);
4225	}
4226	env = saved_env;
4227	}
4228
4229	#ifdef VBOX
4230
4231	/**
4232	* Correctly computes the eflags.
4233	* @returns eflags.
4234	* @param env1 CPU environment.
4235	*/
4236	uint32_t raw_compute_eflags(CPUX86State *env1)
4237	{
4238	CPUX86State *savedenv = env;
4239	env = env1;
4240	uint32_t efl = compute_eflags();
4241	env = savedenv;
4242	return efl;
4243	}
4244
4245	/**
4246	* Reads byte from virtual address in guest memory area.
4247	* XXX: is it working for any addresses? swapped out pages?
4248	* @returns readed data byte.
4249	* @param env1 CPU environment.
4250	* @param pvAddr GC Virtual address.
4251	*/
4252	uint8_t read_byte(CPUX86State *env1, target_ulong addr)
4253	{
4254	CPUX86State *savedenv = env;
4255	env = env1;
4256	uint8_t u8 = ldub_kernel(addr);
4257	env = savedenv;
4258	return u8;
4259	}
4260
4261	/**
4262	* Reads byte from virtual address in guest memory area.
4263	* XXX: is it working for any addresses? swapped out pages?
4264	* @returns readed data byte.
4265	* @param env1 CPU environment.
4266	* @param pvAddr GC Virtual address.
4267	*/
4268	uint16_t read_word(CPUX86State *env1, target_ulong addr)
4269	{
4270	CPUX86State *savedenv = env;
4271	env = env1;
4272	uint16_t u16 = lduw_kernel(addr);
4273	env = savedenv;
4274	return u16;
4275	}
4276
4277	/**
4278	* Reads byte from virtual address in guest memory area.
4279	* XXX: is it working for any addresses? swapped out pages?
4280	* @returns readed data byte.
4281	* @param env1 CPU environment.
4282	* @param pvAddr GC Virtual address.
4283	*/
4284	uint32_t read_dword(CPUX86State *env1, target_ulong addr)
4285	{
4286	CPUX86State *savedenv = env;
4287	env = env1;
4288	uint32_t u32 = ldl_kernel(addr);
4289	env = savedenv;
4290	return u32;
4291	}
4292
4293	/**
4294	* Writes byte to virtual address in guest memory area.
4295	* XXX: is it working for any addresses? swapped out pages?
4296	* @returns readed data byte.
4297	* @param env1 CPU environment.
4298	* @param pvAddr GC Virtual address.
4299	* @param val byte value
4300	*/
4301	void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
4302	{
4303	CPUX86State *savedenv = env;
4304	env = env1;
4305	stb(addr, val);
4306	env = savedenv;
4307	}
4308
4309	void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
4310	{
4311	CPUX86State *savedenv = env;
4312	env = env1;
4313	stw(addr, val);
4314	env = savedenv;
4315	}
4316
4317	void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
4318	{
4319	CPUX86State *savedenv = env;
4320	env = env1;
4321	stl(addr, val);
4322	env = savedenv;
4323	}
4324
4325	/**
4326	* Correctly loads selector into segment register with updating internal
4327	* qemu data/caches.
4328	* @param env1 CPU environment.
4329	* @param seg_reg Segment register.
4330	* @param selector Selector to load.
4331	*/
4332	void sync_seg(CPUX86State *env1, int seg_reg, int selector)
4333	{
4334	CPUX86State *savedenv = env;
4335	env = env1;
4336
4337	if ( env->eflags & X86_EFL_VM
4338	\|\| !(env->cr[0] & X86_CR0_PE))
4339	{
4340	load_seg_vm(seg_reg, selector);
4341
4342	env = savedenv;
4343
4344	/* Successful sync. */
4345	env1->segs[seg_reg].newselector = 0;
4346	}
4347	else
4348	{
4349	if (setjmp(env1->jmp_env) == 0)
4350	{
4351	if (seg_reg == R_CS)
4352	{
4353	uint32_t e1, e2;
4354	load_segment(&e1, &e2, selector);
4355	cpu_x86_load_seg_cache(env, R_CS, selector,
4356	get_seg_base(e1, e2),
4357	get_seg_limit(e1, e2),
4358	e2);
4359	}
4360	else
4361	load_seg(seg_reg, selector);
4362	env = savedenv;
4363
4364	/* Successful sync. */
4365	env1->segs[seg_reg].newselector = 0;
4366	}
4367	else
4368	{
4369	env = savedenv;
4370
4371	/* Postpone sync until the guest uses the selector. */
4372	env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
4373	env1->segs[seg_reg].newselector = selector;
4374	Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
4375	}
4376	}
4377
4378	}
4379
4380
4381	/**
4382	* Correctly loads a new ldtr selector.
4383	*
4384	* @param env1 CPU environment.
4385	* @param selector Selector to load.
4386	*/
4387	void sync_ldtr(CPUX86State *env1, int selector)
4388	{
4389	CPUX86State *saved_env = env;
4390	target_ulong saved_T0 = T0;
4391	if (setjmp(env1->jmp_env) == 0)
4392	{
4393	env = env1;
4394	T0 = selector;
4395	helper_lldt_T0();
4396	T0 = saved_T0;
4397	env = saved_env;
4398	}
4399	else
4400	{
4401	T0 = saved_T0;
4402	env = saved_env;
4403	#ifdef VBOX_STRICT
4404	cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
4405	#endif
4406	}
4407	}
4408
4409	/**
4410	* Correctly loads a new tr selector.
4411	*
4412	* @param env1 CPU environment.
4413	* @param selector Selector to load.
4414	*/
4415	int sync_tr(CPUX86State *env1, int selector)
4416	{
4417	/* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
4418	SegmentCache *dt;
4419	uint32_t e1, e2;
4420	int index, type, entry_limit;
4421	target_ulong ptr;
4422	CPUX86State *saved_env = env;
4423	env = env1;
4424
4425	selector &= 0xffff;
4426	if ((selector & 0xfffc) == 0) {
4427	/* NULL selector case: invalid TR */
4428	env->tr.base = 0;
4429	env->tr.limit = 0;
4430	env->tr.flags = 0;
4431	} else {
4432	if (selector & 0x4)
4433	goto l_failure;
4434	dt = &env->gdt;
4435	index = selector & ~7;
4436	#ifdef TARGET_X86_64
4437	if (env->hflags & HF_LMA_MASK)
4438	entry_limit = 15;
4439	else
4440	#endif
4441	entry_limit = 7;
4442	if ((index + entry_limit) > dt->limit)
4443	goto l_failure;
4444	ptr = dt->base + index;
4445	e1 = ldl_kernel(ptr);
4446	e2 = ldl_kernel(ptr + 4);
4447	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
4448	if ((e2 & DESC_S_MASK) /*\|\|
4449	(type != 1 && type != 9)*/)
4450	goto l_failure;
4451	if (!(e2 & DESC_P_MASK))
4452	goto l_failure;
4453	#ifdef TARGET_X86_64
4454	if (env->hflags & HF_LMA_MASK) {
4455	uint32_t e3;
4456	e3 = ldl_kernel(ptr + 8);
4457	load_seg_cache_raw_dt(&env->tr, e1, e2);
4458	env->tr.base \|= (target_ulong)e3 << 32;
4459	} else
4460	#endif
4461	{
4462	load_seg_cache_raw_dt(&env->tr, e1, e2);
4463	}
4464	e2 \|= DESC_TSS_BUSY_MASK;
4465	stl_kernel(ptr + 4, e2);
4466	}
4467	env->tr.selector = selector;
4468
4469	env = saved_env;
4470	return 0;
4471	l_failure:
4472	AssertMsgFailed(("selector=%d\n", selector));
4473	return -1;
4474	}
4475
4476	int emulate_single_instr(CPUX86State *env1)
4477	{
4478	#if 1 /* single stepping is broken when using a static tb... feel free to figure out why. :-) */
4479	/* This has to be static because it needs to be addressible
4480	using 32-bit immediate addresses on 64-bit machines. This
4481	is dictated by the gcc code model used when building this
4482	module / op.o. Using a static here pushes the problem
4483	onto the module loader. */
4484	static TranslationBlock tb_temp;
4485	#endif
4486	TranslationBlock *tb;
4487	TranslationBlock *current;
4488	int csize;
4489	void (*gen_func)(void);
4490	uint8_t *tc_ptr;
4491	target_ulong old_eip;
4492
4493	/* ensures env is loaded in ebp! */
4494	CPUX86State *savedenv = env;
4495	env = env1;
4496
4497	RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
4498
4499	#if 1 /* see above */
4500	tc_ptr = env->pvCodeBuffer;
4501	#else
4502	tc_ptr = code_gen_ptr;
4503	#endif
4504
4505	/*
4506	* Setup temporary translation block.
4507	*/
4508	/* tb_alloc: */
4509	#if 1 /* see above */
4510	tb = &tb_temp;
4511	tb->pc = env->segs[R_CS].base + env->eip;
4512	tb->cflags = 0;
4513	#else
4514	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4515	if (!tb)
4516	{
4517	tb_flush(env);
4518	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4519	}
4520	#endif
4521
4522	/* tb_find_slow: */
4523	tb->tc_ptr = tc_ptr;
4524	tb->cs_base = env->segs[R_CS].base;
4525	tb->flags = env->hflags \| (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
4526
4527	/* Initialize the rest with sensible values. */
4528	tb->size = 0;
4529	tb->phys_hash_next = NULL;
4530	tb->page_next[0] = NULL;
4531	tb->page_next[1] = NULL;
4532	tb->page_addr[0] = 0;
4533	tb->page_addr[1] = 0;
4534	tb->tb_next_offset[0] = 0xffff;
4535	tb->tb_next_offset[1] = 0xffff;
4536	tb->tb_next[0] = 0xffff;
4537	tb->tb_next[1] = 0xffff;
4538	tb->jmp_next[0] = NULL;
4539	tb->jmp_next[1] = NULL;
4540	tb->jmp_first = NULL;
4541
4542	current = env->current_tb;
4543	env->current_tb = NULL;
4544
4545	/*
4546	* Translate only one instruction.
4547	*/
4548	ASMAtomicOrU32(&env->state, CPU_EMULATE_SINGLE_INSTR);
4549	if (cpu_gen_code(env, tb, env->cbCodeBuffer, &csize) < 0)
4550	{
4551	AssertFailed();
4552	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4553	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4554	env = savedenv;
4555	return -1;
4556	}
4557	#ifdef DEBUG
4558	if(csize > env->cbCodeBuffer)
4559	{
4560	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4561	AssertFailed();
4562	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4563	env = savedenv;
4564	return -1;
4565	}
4566	if (tb->tc_ptr != tc_ptr)
4567	{
4568	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4569	AssertFailed();
4570	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4571	env = savedenv;
4572	return -1;
4573	}
4574	#endif
4575	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4576
4577	/* tb_link_phys: */
4578	tb->jmp_first = (TranslationBlock *)((intptr_t)tb \| 2);
4579	Assert(tb->jmp_next[0] == NULL); Assert(tb->jmp_next[1] == NULL);
4580	if (tb->tb_next_offset[0] != 0xffff)
4581	tb_set_jmp_target(tb, 0, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[0]));
4582	if (tb->tb_next_offset[1] != 0xffff)
4583	tb_set_jmp_target(tb, 1, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[1]));
4584
4585	/*
4586	* Execute it using emulation
4587	*/
4588	old_eip = env->eip;
4589	gen_func = (void *)tb->tc_ptr;
4590	env->current_tb = tb;
4591
4592	// eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
4593	// perhaps not a very safe hack
4594	while(old_eip == env->eip)
4595	{
4596	gen_func();
4597	/*
4598	* Exit once we detect an external interrupt and interrupts are enabled
4599	*/
4600	if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT\|CPU_INTERRUPT_EXTERNAL_TIMER)) \|\|
4601	( (env->eflags & IF_MASK) &&
4602	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
4603	(env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
4604	{
4605	break;
4606	}
4607	}
4608	env->current_tb = current;
4609
4610	Assert(tb->phys_hash_next == NULL);
4611	Assert(tb->page_next[0] == NULL);
4612	Assert(tb->page_next[1] == NULL);
4613	Assert(tb->page_addr[0] == 0);
4614	Assert(tb->page_addr[1] == 0);
4615	/*
4616	Assert(tb->tb_next_offset[0] == 0xffff);
4617	Assert(tb->tb_next_offset[1] == 0xffff);
4618	Assert(tb->tb_next[0] == 0xffff);
4619	Assert(tb->tb_next[1] == 0xffff);
4620	Assert(tb->jmp_next[0] == NULL);
4621	Assert(tb->jmp_next[1] == NULL);
4622	Assert(tb->jmp_first == NULL); */
4623
4624	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4625
4626	/*
4627	* Execute the next instruction when we encounter instruction fusing.
4628	*/
4629	if (env->hflags & HF_INHIBIT_IRQ_MASK)
4630	{
4631	Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK) at %VGv\n", env->eip));
4632	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
4633	emulate_single_instr(env);
4634	}
4635
4636	env = savedenv;
4637	return 0;
4638	}
4639
4640	int get_ss_esp_from_tss_raw(CPUX86State env1, uint32_t ss_ptr,
4641	uint32_t *esp_ptr, int dpl)
4642	{
4643	int type, index, shift;
4644
4645	CPUX86State *savedenv = env;
4646	env = env1;
4647
4648	if (!(env->tr.flags & DESC_P_MASK))
4649	cpu_abort(env, "invalid tss");
4650	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
4651	if ((type & 7) != 1)
4652	cpu_abort(env, "invalid tss type %d", type);
4653	shift = type >> 3;
4654	index = (dpl * 4 + 2) << shift;
4655	if (index + (4 << shift) - 1 > env->tr.limit)
4656	{
4657	env = savedenv;
4658	return 0;
4659	}
4660	//raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
4661
4662	if (shift == 0) {
4663	*esp_ptr = lduw_kernel(env->tr.base + index);
4664	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
4665	} else {
4666	*esp_ptr = ldl_kernel(env->tr.base + index);
4667	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
4668	}
4669
4670	env = savedenv;
4671	return 1;
4672	}
4673
4674	//*****************************************************************************
4675	// Needs to be at the bottom of the file (overriding macros)
4676
4677	static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4678	{
4679	return (CPU86_LDouble )ptr;
4680	}
4681
4682	static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4683	{
4684	(CPU86_LDouble )ptr = f;
4685	}
4686
4687	#undef stw
4688	#undef stl
4689	#undef stq
4690	#define stw(a,b) (uint16_t )(a) = (uint16_t)(b)
4691	#define stl(a,b) (uint32_t )(a) = (uint32_t)(b)
4692	#define stq(a,b) (uint64_t )(a) = (uint64_t)(b)
4693	#define data64 0
4694
4695	//*****************************************************************************
4696	void restore_raw_fp_state(CPUX86State env, uint8_t ptr)
4697	{
4698	int fpus, fptag, i, nb_xmm_regs;
4699	CPU86_LDouble tmp;
4700	uint8_t *addr;
4701
4702	if (env->cpuid_features & CPUID_FXSR)
4703	{
4704	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4705	fptag = 0;
4706	for(i = 0; i < 8; i++) {
4707	fptag \|= (env->fptags[i] << i);
4708	}
4709	stw(ptr, env->fpuc);
4710	stw(ptr + 2, fpus);
4711	stw(ptr + 4, fptag ^ 0xff);
4712
4713	addr = ptr + 0x20;
4714	for(i = 0;i < 8; i++) {
4715	tmp = ST(i);
4716	helper_fstt_raw(tmp, addr);
4717	addr += 16;
4718	}
4719
4720	if (env->cr[4] & CR4_OSFXSR_MASK) {
4721	/* XXX: finish it */
4722	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4723	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4724	nb_xmm_regs = 8 << data64;
4725	addr = ptr + 0xa0;
4726	for(i = 0; i < nb_xmm_regs; i++) {
4727	#if __GNUC__ < 4
4728	stq(addr, env->xmm_regs[i].XMM_Q(0));
4729	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4730	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4731	stl(addr, env->xmm_regs[i].XMM_L(0));
4732	stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4733	stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4734	stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4735	#endif
4736	addr += 16;
4737	}
4738	}
4739	}
4740	else
4741	{
4742	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4743	int fptag;
4744
4745	fp->FCW = env->fpuc;
4746	fp->FSW = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4747	fptag = 0;
4748	for (i=7; i>=0; i--) {
4749	fptag <<= 2;
4750	if (env->fptags[i]) {
4751	fptag \|= 3;
4752	} else {
4753	/* the FPU automatically computes it */
4754	}
4755	}
4756	fp->FTW = fptag;
4757
4758	for(i = 0;i < 8; i++) {
4759	tmp = ST(i);
4760	helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4761	}
4762	}
4763	}
4764
4765	//*****************************************************************************
4766	#undef lduw
4767	#undef ldl
4768	#undef ldq
4769	#define lduw(a) (uint16_t )(a)
4770	#define ldl(a) (uint32_t )(a)
4771	#define ldq(a) (uint64_t )(a)
4772	//*****************************************************************************
4773	void save_raw_fp_state(CPUX86State env, uint8_t ptr)
4774	{
4775	int i, fpus, fptag, nb_xmm_regs;
4776	CPU86_LDouble tmp;
4777	uint8_t *addr;
4778
4779	if (env->cpuid_features & CPUID_FXSR)
4780	{
4781	env->fpuc = lduw(ptr);
4782	fpus = lduw(ptr + 2);
4783	fptag = lduw(ptr + 4);
4784	env->fpstt = (fpus >> 11) & 7;
4785	env->fpus = fpus & ~0x3800;
4786	fptag ^= 0xff;
4787	for(i = 0;i < 8; i++) {
4788	env->fptags[i] = ((fptag >> i) & 1);
4789	}
4790
4791	addr = ptr + 0x20;
4792	for(i = 0;i < 8; i++) {
4793	tmp = helper_fldt_raw(addr);
4794	ST(i) = tmp;
4795	addr += 16;
4796	}
4797
4798	if (env->cr[4] & CR4_OSFXSR_MASK) {
4799	/* XXX: finish it, endianness */
4800	env->mxcsr = ldl(ptr + 0x18);
4801	//ldl(ptr + 0x1c);
4802	nb_xmm_regs = 8 << data64;
4803	addr = ptr + 0xa0;
4804	for(i = 0; i < nb_xmm_regs; i++) {
4805	#if HC_ARCH_BITS == 32
4806	/* this is a workaround for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35135 */
4807	env->xmm_regs[i].XMM_L(0) = ldl(addr);
4808	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
4809	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
4810	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
4811	#else
4812	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4813	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4814	#endif
4815	addr += 16;
4816	}
4817	}
4818	}
4819	else
4820	{
4821	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4822	int fptag, j;
4823
4824	env->fpuc = fp->FCW;
4825	env->fpstt = (fp->FSW >> 11) & 7;
4826	env->fpus = fp->FSW & ~0x3800;
4827	fptag = fp->FTW;
4828	for(i = 0;i < 8; i++) {
4829	env->fptags[i] = ((fptag & 3) == 3);
4830	fptag >>= 2;
4831	}
4832	j = env->fpstt;
4833	for(i = 0;i < 8; i++) {
4834	tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4835	ST(i) = tmp;
4836	}
4837	}
4838	}
4839	//*****************************************************************************
4840	//*****************************************************************************
4841
4842	#endif /* VBOX */
4843

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source: vbox/trunk/src/recompiler/target-i386/helper.c@ 13013

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