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source: vbox/trunk/src/recompiler/target-i386/helper.c@ 2311

Last change on this file since 2311 was 1953, checked in by vboxsync, 18 years ago

Reversed vif & if clearing
  • Property svn:eol-style set to native
File size: 119.5 KB
Line 
1/*
2 * i386 helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "exec.h"
21#ifdef VBOX
22#include <VBox/err.h>
23#endif
24
25//#define DEBUG_PCALL
26
27#if 0
28#define raise_exception_err(a, b)\
29do {\
30 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
31 (raise_exception_err)(a, b);\
32} while (0)
33#endif
34
35const uint8_t parity_table[256] = {
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
44 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
45 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
46 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
58 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
59 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
60 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
61 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
62 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
65 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
66 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
68};
69
70/* modulo 17 table */
71const uint8_t rclw_table[32] = {
72 0, 1, 2, 3, 4, 5, 6, 7,
73 8, 9,10,11,12,13,14,15,
74 16, 0, 1, 2, 3, 4, 5, 6,
75 7, 8, 9,10,11,12,13,14,
76};
77
78/* modulo 9 table */
79const uint8_t rclb_table[32] = {
80 0, 1, 2, 3, 4, 5, 6, 7,
81 8, 0, 1, 2, 3, 4, 5, 6,
82 7, 8, 0, 1, 2, 3, 4, 5,
83 6, 7, 8, 0, 1, 2, 3, 4,
84};
85
86const CPU86_LDouble f15rk[7] =
87{
88 0.00000000000000000000L,
89 1.00000000000000000000L,
90 3.14159265358979323851L, /*pi*/
91 0.30102999566398119523L, /*lg2*/
92 0.69314718055994530943L, /*ln2*/
93 1.44269504088896340739L, /*l2e*/
94 3.32192809488736234781L, /*l2t*/
95};
96
97/* thread support */
98
99spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
100
101void cpu_lock(void)
102{
103 spin_lock(&global_cpu_lock);
104}
105
106void cpu_unlock(void)
107{
108 spin_unlock(&global_cpu_lock);
109}
110
111void cpu_loop_exit(void)
112{
113 /* NOTE: the register at this point must be saved by hand because
114 longjmp restore them */
115 regs_to_env();
116 longjmp(env->jmp_env, 1);
117}
118
119/* return non zero if error */
120static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
121 int selector)
122{
123 SegmentCache *dt;
124 int index;
125 target_ulong ptr;
126
127 if (selector & 0x4)
128 dt = &env->ldt;
129 else
130 dt = &env->gdt;
131 index = selector & ~7;
132 if ((index + 7) > dt->limit)
133 return -1;
134 ptr = dt->base + index;
135 *e1_ptr = ldl_kernel(ptr);
136 *e2_ptr = ldl_kernel(ptr + 4);
137 return 0;
138}
139
140static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
141{
142 unsigned int limit;
143 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
144 if (e2 & DESC_G_MASK)
145 limit = (limit << 12) | 0xfff;
146 return limit;
147}
148
149static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
150{
151 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
152}
153
154static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
155{
156 sc->base = get_seg_base(e1, e2);
157 sc->limit = get_seg_limit(e1, e2);
158 sc->flags = e2;
159}
160
161/* init the segment cache in vm86 mode. */
162static inline void load_seg_vm(int seg, int selector)
163{
164 selector &= 0xffff;
165 cpu_x86_load_seg_cache(env, seg, selector,
166 (selector << 4), 0xffff, 0);
167}
168
169static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
170 uint32_t *esp_ptr, int dpl)
171{
172 int type, index, shift;
173
174#if 0
175 {
176 int i;
177 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
178 for(i=0;i<env->tr.limit;i++) {
179 printf("%02x ", env->tr.base[i]);
180 if ((i & 7) == 7) printf("\n");
181 }
182 printf("\n");
183 }
184#endif
185
186 if (!(env->tr.flags & DESC_P_MASK))
187 cpu_abort(env, "invalid tss");
188 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
189 if ((type & 7) != 1)
190 cpu_abort(env, "invalid tss type %d", type);
191 shift = type >> 3;
192 index = (dpl * 4 + 2) << shift;
193 if (index + (4 << shift) - 1 > env->tr.limit)
194 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
195 if (shift == 0) {
196 *esp_ptr = lduw_kernel(env->tr.base + index);
197 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
198 } else {
199 *esp_ptr = ldl_kernel(env->tr.base + index);
200 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
201 }
202}
203
204/* XXX: merge with load_seg() */
205static void tss_load_seg(int seg_reg, int selector)
206{
207 uint32_t e1, e2;
208 int rpl, dpl, cpl;
209
210 if ((selector & 0xfffc) != 0) {
211 if (load_segment(&e1, &e2, selector) != 0)
212 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
213 if (!(e2 & DESC_S_MASK))
214 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
215 rpl = selector & 3;
216 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
217 cpl = env->hflags & HF_CPL_MASK;
218 if (seg_reg == R_CS) {
219 if (!(e2 & DESC_CS_MASK))
220 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
221 /* XXX: is it correct ? */
222 if (dpl != rpl)
223 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
224 if ((e2 & DESC_C_MASK) && dpl > rpl)
225 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
226
227 } else if (seg_reg == R_SS) {
228 /* SS must be writable data */
229 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
230 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231 if (dpl != cpl || dpl != rpl)
232 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
233 } else {
234 /* not readable code */
235 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
236 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
237 /* if data or non conforming code, checks the rights */
238 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
239 if (dpl < cpl || dpl < rpl)
240 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
241 }
242 }
243 if (!(e2 & DESC_P_MASK))
244 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
245 cpu_x86_load_seg_cache(env, seg_reg, selector,
246 get_seg_base(e1, e2),
247 get_seg_limit(e1, e2),
248 e2);
249 } else {
250 if (seg_reg == R_SS || seg_reg == R_CS)
251 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
252 }
253}
254
255#define SWITCH_TSS_JMP 0
256#define SWITCH_TSS_IRET 1
257#define SWITCH_TSS_CALL 2
258
259/* XXX: restore CPU state in registers (PowerPC case) */
260static void switch_tss(int tss_selector,
261 uint32_t e1, uint32_t e2, int source,
262 uint32_t next_eip)
263{
264 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
265 target_ulong tss_base;
266 uint32_t new_regs[8], new_segs[6];
267 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
268 uint32_t old_eflags, eflags_mask;
269 SegmentCache *dt;
270 int index;
271 target_ulong ptr;
272
273 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
274#ifdef DEBUG_PCALL
275 if (loglevel & CPU_LOG_PCALL)
276 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
277#endif
278
279#if defined(VBOX) && defined(DEBUG)
280 printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
281#endif
282
283 /* if task gate, we read the TSS segment and we load it */
284 if (type == 5) {
285 if (!(e2 & DESC_P_MASK))
286 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
287 tss_selector = e1 >> 16;
288 if (tss_selector & 4)
289 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
290 if (load_segment(&e1, &e2, tss_selector) != 0)
291 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
292 if (e2 & DESC_S_MASK)
293 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
294 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
295 if ((type & 7) != 1)
296 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
297 }
298
299 if (!(e2 & DESC_P_MASK))
300 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
301
302 if (type & 8)
303 tss_limit_max = 103;
304 else
305 tss_limit_max = 43;
306 tss_limit = get_seg_limit(e1, e2);
307 tss_base = get_seg_base(e1, e2);
308 if ((tss_selector & 4) != 0 ||
309 tss_limit < tss_limit_max)
310 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
311 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
312 if (old_type & 8)
313 old_tss_limit_max = 103;
314 else
315 old_tss_limit_max = 43;
316
317 /* read all the registers from the new TSS */
318 if (type & 8) {
319 /* 32 bit */
320 new_cr3 = ldl_kernel(tss_base + 0x1c);
321 new_eip = ldl_kernel(tss_base + 0x20);
322 new_eflags = ldl_kernel(tss_base + 0x24);
323 for(i = 0; i < 8; i++)
324 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
325 for(i = 0; i < 6; i++)
326 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
327 new_ldt = lduw_kernel(tss_base + 0x60);
328 new_trap = ldl_kernel(tss_base + 0x64);
329 } else {
330 /* 16 bit */
331 new_cr3 = 0;
332 new_eip = lduw_kernel(tss_base + 0x0e);
333 new_eflags = lduw_kernel(tss_base + 0x10);
334 for(i = 0; i < 8; i++)
335 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
336 for(i = 0; i < 4; i++)
337 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
338 new_ldt = lduw_kernel(tss_base + 0x2a);
339 new_segs[R_FS] = 0;
340 new_segs[R_GS] = 0;
341 new_trap = 0;
342 }
343
344 /* NOTE: we must avoid memory exceptions during the task switch,
345 so we make dummy accesses before */
346 /* XXX: it can still fail in some cases, so a bigger hack is
347 necessary to valid the TLB after having done the accesses */
348
349 v1 = ldub_kernel(env->tr.base);
350 v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
351 stb_kernel(env->tr.base, v1);
352 stb_kernel(env->tr.base + old_tss_limit_max, v2);
353
354 /* clear busy bit (it is restartable) */
355 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
356 target_ulong ptr;
357 uint32_t e2;
358 ptr = env->gdt.base + (env->tr.selector & ~7);
359 e2 = ldl_kernel(ptr + 4);
360 e2 &= ~DESC_TSS_BUSY_MASK;
361 stl_kernel(ptr + 4, e2);
362 }
363 old_eflags = compute_eflags();
364 if (source == SWITCH_TSS_IRET)
365 old_eflags &= ~NT_MASK;
366
367 /* save the current state in the old TSS */
368 if (type & 8) {
369 /* 32 bit */
370 stl_kernel(env->tr.base + 0x20, next_eip);
371 stl_kernel(env->tr.base + 0x24, old_eflags);
372 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
373 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
374 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
375 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
376 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
377 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
378 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
379 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
380 for(i = 0; i < 6; i++)
381 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
382
383#if defined(VBOX) && defined(DEBUG)
384 printf("TSS 32 bits switch\n");
385 printf("Saving CS=%08X\n", env->segs[R_CS].selector);
386#endif
387
388 } else {
389 /* 16 bit */
390 stw_kernel(env->tr.base + 0x0e, next_eip);
391 stw_kernel(env->tr.base + 0x10, old_eflags);
392 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
393 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
394 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
395 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
396 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
397 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
398 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
399 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
400 for(i = 0; i < 4; i++)
401 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
402 }
403
404 /* now if an exception occurs, it will occurs in the next task
405 context */
406
407 if (source == SWITCH_TSS_CALL) {
408 stw_kernel(tss_base, env->tr.selector);
409 new_eflags |= NT_MASK;
410 }
411
412 /* set busy bit */
413 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
414 target_ulong ptr;
415 uint32_t e2;
416 ptr = env->gdt.base + (tss_selector & ~7);
417 e2 = ldl_kernel(ptr + 4);
418 e2 |= DESC_TSS_BUSY_MASK;
419 stl_kernel(ptr + 4, e2);
420 }
421
422 /* set the new CPU state */
423 /* from this point, any exception which occurs can give problems */
424 env->cr[0] |= CR0_TS_MASK;
425 env->hflags |= HF_TS_MASK;
426 env->tr.selector = tss_selector;
427 env->tr.base = tss_base;
428 env->tr.limit = tss_limit;
429 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
430
431 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
432 cpu_x86_update_cr3(env, new_cr3);
433 }
434
435 /* load all registers without an exception, then reload them with
436 possible exception */
437 env->eip = new_eip;
438 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
439 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
440 if (!(type & 8))
441 eflags_mask &= 0xffff;
442 load_eflags(new_eflags, eflags_mask);
443 /* XXX: what to do in 16 bit case ? */
444 EAX = new_regs[0];
445 ECX = new_regs[1];
446 EDX = new_regs[2];
447 EBX = new_regs[3];
448 ESP = new_regs[4];
449 EBP = new_regs[5];
450 ESI = new_regs[6];
451 EDI = new_regs[7];
452 if (new_eflags & VM_MASK) {
453 for(i = 0; i < 6; i++)
454 load_seg_vm(i, new_segs[i]);
455 /* in vm86, CPL is always 3 */
456 cpu_x86_set_cpl(env, 3);
457 } else {
458 /* CPL is set the RPL of CS */
459 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
460 /* first just selectors as the rest may trigger exceptions */
461 for(i = 0; i < 6; i++)
462 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
463 }
464
465 env->ldt.selector = new_ldt & ~4;
466 env->ldt.base = 0;
467 env->ldt.limit = 0;
468 env->ldt.flags = 0;
469
470 /* load the LDT */
471 if (new_ldt & 4)
472 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
473
474 if ((new_ldt & 0xfffc) != 0) {
475 dt = &env->gdt;
476 index = new_ldt & ~7;
477 if ((index + 7) > dt->limit)
478 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
479 ptr = dt->base + index;
480 e1 = ldl_kernel(ptr);
481 e2 = ldl_kernel(ptr + 4);
482 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
483 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
484 if (!(e2 & DESC_P_MASK))
485 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486 load_seg_cache_raw_dt(&env->ldt, e1, e2);
487 }
488
489 /* load the segments */
490 if (!(new_eflags & VM_MASK)) {
491 tss_load_seg(R_CS, new_segs[R_CS]);
492 tss_load_seg(R_SS, new_segs[R_SS]);
493 tss_load_seg(R_ES, new_segs[R_ES]);
494 tss_load_seg(R_DS, new_segs[R_DS]);
495 tss_load_seg(R_FS, new_segs[R_FS]);
496 tss_load_seg(R_GS, new_segs[R_GS]);
497 }
498
499 /* check that EIP is in the CS segment limits */
500 if (new_eip > env->segs[R_CS].limit) {
501 /* XXX: different exception if CALL ? */
502 raise_exception_err(EXCP0D_GPF, 0);
503 }
504}
505
506/* check if Port I/O is allowed in TSS */
507static inline void check_io(int addr, int size)
508{
509 int io_offset, val, mask;
510
511 /* TSS must be a valid 32 bit one */
512 if (!(env->tr.flags & DESC_P_MASK) ||
513 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
514 env->tr.limit < 103)
515 goto fail;
516 io_offset = lduw_kernel(env->tr.base + 0x66);
517 io_offset += (addr >> 3);
518 /* Note: the check needs two bytes */
519 if ((io_offset + 1) > env->tr.limit)
520 goto fail;
521 val = lduw_kernel(env->tr.base + io_offset);
522 val >>= (addr & 7);
523 mask = (1 << size) - 1;
524 /* all bits must be zero to allow the I/O */
525 if ((val & mask) != 0) {
526 fail:
527 raise_exception_err(EXCP0D_GPF, 0);
528 }
529}
530
531void check_iob_T0(void)
532{
533 check_io(T0, 1);
534}
535
536void check_iow_T0(void)
537{
538 check_io(T0, 2);
539}
540
541void check_iol_T0(void)
542{
543 check_io(T0, 4);
544}
545
546void check_iob_DX(void)
547{
548 check_io(EDX & 0xffff, 1);
549}
550
551void check_iow_DX(void)
552{
553 check_io(EDX & 0xffff, 2);
554}
555
556void check_iol_DX(void)
557{
558 check_io(EDX & 0xffff, 4);
559}
560
561static inline unsigned int get_sp_mask(unsigned int e2)
562{
563 if (e2 & DESC_B_MASK)
564 return 0xffffffff;
565 else
566 return 0xffff;
567}
568
569/* XXX: add a is_user flag to have proper security support */
570#define PUSHW(ssp, sp, sp_mask, val)\
571{\
572 sp -= 2;\
573 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
574}
575
576#define PUSHL(ssp, sp, sp_mask, val)\
577{\
578 sp -= 4;\
579 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
580}
581
582#define POPW(ssp, sp, sp_mask, val)\
583{\
584 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
585 sp += 2;\
586}
587
588#define POPL(ssp, sp, sp_mask, val)\
589{\
590 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
591 sp += 4;\
592}
593
594/* protected mode interrupt */
595static void do_interrupt_protected(int intno, int is_int, int error_code,
596 unsigned int next_eip, int is_hw)
597{
598 SegmentCache *dt;
599 target_ulong ptr, ssp;
600 int type, dpl, selector, ss_dpl, cpl, sp_mask;
601 int has_error_code, new_stack, shift;
602 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
603 uint32_t old_eip;
604
605#ifdef VBOX
606 if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
607 cpu_loop_exit();
608#endif
609
610 has_error_code = 0;
611 if (!is_int && !is_hw) {
612 switch(intno) {
613 case 8:
614 case 10:
615 case 11:
616 case 12:
617 case 13:
618 case 14:
619 case 17:
620 has_error_code = 1;
621 break;
622 }
623 }
624 if (is_int)
625 old_eip = next_eip;
626 else
627 old_eip = env->eip;
628
629 dt = &env->idt;
630 if (intno * 8 + 7 > dt->limit)
631 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
632 ptr = dt->base + intno * 8;
633 e1 = ldl_kernel(ptr);
634 e2 = ldl_kernel(ptr + 4);
635 /* check gate type */
636 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
637 switch(type) {
638 case 5: /* task gate */
639 /* must do that check here to return the correct error code */
640 if (!(e2 & DESC_P_MASK))
641 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
642 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
643 if (has_error_code) {
644 int mask, type;
645 /* push the error code */
646 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
647 shift = type >> 3;
648 if (env->segs[R_SS].flags & DESC_B_MASK)
649 mask = 0xffffffff;
650 else
651 mask = 0xffff;
652 esp = (ESP - (2 << shift)) & mask;
653 ssp = env->segs[R_SS].base + esp;
654 if (shift)
655 stl_kernel(ssp, error_code);
656 else
657 stw_kernel(ssp, error_code);
658 ESP = (esp & mask) | (ESP & ~mask);
659 }
660 return;
661 case 6: /* 286 interrupt gate */
662 case 7: /* 286 trap gate */
663 case 14: /* 386 interrupt gate */
664 case 15: /* 386 trap gate */
665 break;
666 default:
667 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
668 break;
669 }
670 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
671 cpl = env->hflags & HF_CPL_MASK;
672 /* check privledge if software int */
673 if (is_int && dpl < cpl)
674 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
675 /* check valid bit */
676 if (!(e2 & DESC_P_MASK))
677 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
678 selector = e1 >> 16;
679 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
680 if ((selector & 0xfffc) == 0)
681 raise_exception_err(EXCP0D_GPF, 0);
682
683 if (load_segment(&e1, &e2, selector) != 0)
684 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
685 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
686 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
687 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
688 if (dpl > cpl)
689 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
690 if (!(e2 & DESC_P_MASK))
691 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
692 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
693 /* to inner priviledge */
694 get_ss_esp_from_tss(&ss, &esp, dpl);
695 if ((ss & 0xfffc) == 0)
696 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
697 if ((ss & 3) != dpl)
698 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
699 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
700 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
701 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
702 if (ss_dpl != dpl)
703 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
704 if (!(ss_e2 & DESC_S_MASK) ||
705 (ss_e2 & DESC_CS_MASK) ||
706 !(ss_e2 & DESC_W_MASK))
707 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
708 if (!(ss_e2 & DESC_P_MASK))
709 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
710 new_stack = 1;
711 sp_mask = get_sp_mask(ss_e2);
712 ssp = get_seg_base(ss_e1, ss_e2);
713#if defined(VBOX) && defined(DEBUG)
714 printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
715#endif
716 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
717 /* to same priviledge */
718 if (env->eflags & VM_MASK)
719 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
720 new_stack = 0;
721 sp_mask = get_sp_mask(env->segs[R_SS].flags);
722 ssp = env->segs[R_SS].base;
723 esp = ESP;
724 dpl = cpl;
725 } else {
726 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
727 new_stack = 0; /* avoid warning */
728 sp_mask = 0; /* avoid warning */
729 ssp = 0; /* avoid warning */
730 esp = 0; /* avoid warning */
731 }
732
733 shift = type >> 3;
734
735#if 0
736 /* XXX: check that enough room is available */
737 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
738 if (env->eflags & VM_MASK)
739 push_size += 8;
740 push_size <<= shift;
741#endif
742 if (shift == 1) {
743 if (new_stack) {
744 if (env->eflags & VM_MASK) {
745 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
746 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
747 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
748 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
749 }
750 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
751 PUSHL(ssp, esp, sp_mask, ESP);
752 }
753 PUSHL(ssp, esp, sp_mask, compute_eflags());
754 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
755 PUSHL(ssp, esp, sp_mask, old_eip);
756 if (has_error_code) {
757 PUSHL(ssp, esp, sp_mask, error_code);
758 }
759 } else {
760 if (new_stack) {
761 if (env->eflags & VM_MASK) {
762 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
763 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
764 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
765 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
766 }
767 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
768 PUSHW(ssp, esp, sp_mask, ESP);
769 }
770 PUSHW(ssp, esp, sp_mask, compute_eflags());
771 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
772 PUSHW(ssp, esp, sp_mask, old_eip);
773 if (has_error_code) {
774 PUSHW(ssp, esp, sp_mask, error_code);
775 }
776 }
777
778 if (new_stack) {
779 if (env->eflags & VM_MASK) {
780 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
781 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
782 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
783 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
784 }
785 ss = (ss & ~3) | dpl;
786 cpu_x86_load_seg_cache(env, R_SS, ss,
787 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
788 }
789 ESP = (ESP & ~sp_mask) | (esp & sp_mask);
790
791 selector = (selector & ~3) | dpl;
792 cpu_x86_load_seg_cache(env, R_CS, selector,
793 get_seg_base(e1, e2),
794 get_seg_limit(e1, e2),
795 e2);
796 cpu_x86_set_cpl(env, dpl);
797 env->eip = offset;
798
799 /* interrupt gate clear IF mask */
800 if ((type & 1) == 0) {
801 env->eflags &= ~IF_MASK;
802 }
803 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
804}
805
806#ifdef VBOX
807
808/* check if VME interrupt redirection is enabled in TSS */
809static inline bool is_vme_irq_redirected(int intno)
810{
811 int io_offset, intredir_offset;
812 unsigned char val, mask;
813
814 /* TSS must be a valid 32 bit one */
815 if (!(env->tr.flags & DESC_P_MASK) ||
816 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
817 env->tr.limit < 103)
818 goto fail;
819 io_offset = lduw_kernel(env->tr.base + 0x66);
820 /* the virtual interrupt redirection bitmap is located below the io bitmap */
821 intredir_offset = io_offset - 0x20;
822
823 intredir_offset += (intno >> 3);
824 if ((intredir_offset) > env->tr.limit)
825 goto fail;
826
827 val = ldub_kernel(env->tr.base + intredir_offset);
828 mask = 1 << (unsigned char)(intno & 7);
829
830 /* bit set means no redirection. */
831 if ((val & mask) != 0) {
832 return false;
833 }
834 return true;
835
836fail:
837 raise_exception_err(EXCP0D_GPF, 0);
838 return true;
839}
840
841/* V86 mode software interrupt with CR4.VME=1 */
842static void do_soft_interrupt_vme(int intno, int error_code, unsigned int next_eip)
843{
844 target_ulong ptr, ssp;
845 int selector;
846 uint32_t offset, esp;
847 uint32_t old_cs, old_eflags;
848 uint32_t iopl;
849
850 iopl = ((env->eflags >> IOPL_SHIFT) & 3);
851
852 if (!is_vme_irq_redirected(intno))
853 {
854 if (iopl == 3)
855 /* normal protected mode handler call */
856 return do_interrupt_protected(intno, 1, error_code, next_eip, 0);
857 else
858 raise_exception_err(EXCP0D_GPF, 0);
859 }
860
861 /* virtual mode idt is at linear address 0 */
862 ptr = 0 + intno * 4;
863 offset = lduw_kernel(ptr);
864 selector = lduw_kernel(ptr + 2);
865 esp = ESP;
866 ssp = env->segs[R_SS].base;
867 old_cs = env->segs[R_CS].selector;
868
869 old_eflags = compute_eflags();
870 if (iopl < 3)
871 {
872 /* copy VIF into IF and set IOPL to 3 */
873 if (env->eflags & VIF_MASK)
874 old_eflags |= IF_MASK;
875 else
876 old_eflags &= ~IF_MASK;
877
878 old_eflags |= (3 << IOPL_SHIFT);
879 }
880
881 /* XXX: use SS segment size ? */
882 PUSHW(ssp, esp, 0xffff, old_eflags);
883 PUSHW(ssp, esp, 0xffff, old_cs);
884 PUSHW(ssp, esp, 0xffff, next_eip);
885
886 /* update processor state */
887 ESP = (ESP & ~0xffff) | (esp & 0xffff);
888 env->eip = offset;
889 env->segs[R_CS].selector = selector;
890 env->segs[R_CS].base = (selector << 4);
891 env->eflags &= ~(TF_MASK | RF_MASK);
892
893 if (iopl < 3)
894 env->eflags &= ~VIF_MASK;
895 else
896 env->eflags &= ~IF_MASK;
897}
898#endif
899
900#ifdef TARGET_X86_64
901
902#define PUSHQ(sp, val)\
903{\
904 sp -= 8;\
905 stq_kernel(sp, (val));\
906}
907
908#define POPQ(sp, val)\
909{\
910 val = ldq_kernel(sp);\
911 sp += 8;\
912}
913
914static inline target_ulong get_rsp_from_tss(int level)
915{
916 int index;
917
918#if 0
919 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
920 env->tr.base, env->tr.limit);
921#endif
922
923 if (!(env->tr.flags & DESC_P_MASK))
924 cpu_abort(env, "invalid tss");
925 index = 8 * level + 4;
926 if ((index + 7) > env->tr.limit)
927 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
928 return ldq_kernel(env->tr.base + index);
929}
930
931/* 64 bit interrupt */
932static void do_interrupt64(int intno, int is_int, int error_code,
933 target_ulong next_eip, int is_hw)
934{
935 SegmentCache *dt;
936 target_ulong ptr;
937 int type, dpl, selector, cpl, ist;
938 int has_error_code, new_stack;
939 uint32_t e1, e2, e3, ss;
940 target_ulong old_eip, esp, offset;
941
942 has_error_code = 0;
943 if (!is_int && !is_hw) {
944 switch(intno) {
945 case 8:
946 case 10:
947 case 11:
948 case 12:
949 case 13:
950 case 14:
951 case 17:
952 has_error_code = 1;
953 break;
954 }
955 }
956 if (is_int)
957 old_eip = next_eip;
958 else
959 old_eip = env->eip;
960
961 dt = &env->idt;
962 if (intno * 16 + 15 > dt->limit)
963 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
964 ptr = dt->base + intno * 16;
965 e1 = ldl_kernel(ptr);
966 e2 = ldl_kernel(ptr + 4);
967 e3 = ldl_kernel(ptr + 8);
968 /* check gate type */
969 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
970 switch(type) {
971 case 14: /* 386 interrupt gate */
972 case 15: /* 386 trap gate */
973 break;
974 default:
975 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
976 break;
977 }
978 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
979 cpl = env->hflags & HF_CPL_MASK;
980 /* check privledge if software int */
981 if (is_int && dpl < cpl)
982 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
983 /* check valid bit */
984 if (!(e2 & DESC_P_MASK))
985 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
986 selector = e1 >> 16;
987 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
988 ist = e2 & 7;
989 if ((selector & 0xfffc) == 0)
990 raise_exception_err(EXCP0D_GPF, 0);
991
992 if (load_segment(&e1, &e2, selector) != 0)
993 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
994 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
995 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
996 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
997 if (dpl > cpl)
998 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
999 if (!(e2 & DESC_P_MASK))
1000 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1001 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
1002 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1003 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
1004 /* to inner priviledge */
1005 if (ist != 0)
1006 esp = get_rsp_from_tss(ist + 3);
1007 else
1008 esp = get_rsp_from_tss(dpl);
1009 esp &= ~0xfLL; /* align stack */
1010 ss = 0;
1011 new_stack = 1;
1012 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
1013 /* to same priviledge */
1014 if (env->eflags & VM_MASK)
1015 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1016 new_stack = 0;
1017 if (ist != 0)
1018 esp = get_rsp_from_tss(ist + 3);
1019 else
1020 esp = ESP;
1021 esp &= ~0xfLL; /* align stack */
1022 dpl = cpl;
1023 } else {
1024 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1025 new_stack = 0; /* avoid warning */
1026 esp = 0; /* avoid warning */
1027 }
1028
1029 PUSHQ(esp, env->segs[R_SS].selector);
1030 PUSHQ(esp, ESP);
1031 PUSHQ(esp, compute_eflags());
1032 PUSHQ(esp, env->segs[R_CS].selector);
1033 PUSHQ(esp, old_eip);
1034 if (has_error_code) {
1035 PUSHQ(esp, error_code);
1036 }
1037
1038 if (new_stack) {
1039 ss = 0 | dpl;
1040 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1041 }
1042 ESP = esp;
1043
1044 selector = (selector & ~3) | dpl;
1045 cpu_x86_load_seg_cache(env, R_CS, selector,
1046 get_seg_base(e1, e2),
1047 get_seg_limit(e1, e2),
1048 e2);
1049 cpu_x86_set_cpl(env, dpl);
1050 env->eip = offset;
1051
1052 /* interrupt gate clear IF mask */
1053 if ((type & 1) == 0) {
1054 env->eflags &= ~IF_MASK;
1055 }
1056 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
1057}
1058#endif
1059
1060void helper_syscall(int next_eip_addend)
1061{
1062 int selector;
1063
1064 if (!(env->efer & MSR_EFER_SCE)) {
1065 raise_exception_err(EXCP06_ILLOP, 0);
1066 }
1067 selector = (env->star >> 32) & 0xffff;
1068#ifdef TARGET_X86_64
1069 if (env->hflags & HF_LMA_MASK) {
1070 int code64;
1071
1072 ECX = env->eip + next_eip_addend;
1073 env->regs[11] = compute_eflags();
1074
1075 code64 = env->hflags & HF_CS64_MASK;
1076
1077 cpu_x86_set_cpl(env, 0);
1078 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1079 0, 0xffffffff,
1080 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1081 DESC_S_MASK |
1082 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
1083 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1084 0, 0xffffffff,
1085 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1086 DESC_S_MASK |
1087 DESC_W_MASK | DESC_A_MASK);
1088 env->eflags &= ~env->fmask;
1089 if (code64)
1090 env->eip = env->lstar;
1091 else
1092 env->eip = env->cstar;
1093 } else
1094#endif
1095 {
1096 ECX = (uint32_t)(env->eip + next_eip_addend);
1097
1098 cpu_x86_set_cpl(env, 0);
1099 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1100 0, 0xffffffff,
1101 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1102 DESC_S_MASK |
1103 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1104 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1105 0, 0xffffffff,
1106 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1107 DESC_S_MASK |
1108 DESC_W_MASK | DESC_A_MASK);
1109 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
1110 env->eip = (uint32_t)env->star;
1111 }
1112}
1113
1114void helper_sysret(int dflag)
1115{
1116 int cpl, selector;
1117
1118 if (!(env->efer & MSR_EFER_SCE)) {
1119 raise_exception_err(EXCP06_ILLOP, 0);
1120 }
1121 cpl = env->hflags & HF_CPL_MASK;
1122 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1123 raise_exception_err(EXCP0D_GPF, 0);
1124 }
1125 selector = (env->star >> 48) & 0xffff;
1126#ifdef TARGET_X86_64
1127 if (env->hflags & HF_LMA_MASK) {
1128 if (dflag == 2) {
1129 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1130 0, 0xffffffff,
1131 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1132 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1133 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1134 DESC_L_MASK);
1135 env->eip = ECX;
1136 } else {
1137 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1138 0, 0xffffffff,
1139 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1140 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1141 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1142 env->eip = (uint32_t)ECX;
1143 }
1144 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1145 0, 0xffffffff,
1146 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1147 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1148 DESC_W_MASK | DESC_A_MASK);
1149 load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1150 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
1151 cpu_x86_set_cpl(env, 3);
1152 } else
1153#endif
1154 {
1155 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1156 0, 0xffffffff,
1157 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1158 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1159 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1160 env->eip = (uint32_t)ECX;
1161 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1162 0, 0xffffffff,
1163 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1164 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1165 DESC_W_MASK | DESC_A_MASK);
1166 env->eflags |= IF_MASK;
1167 cpu_x86_set_cpl(env, 3);
1168 }
1169#ifdef USE_KQEMU
1170 if (kqemu_is_ok(env)) {
1171 if (env->hflags & HF_LMA_MASK)
1172 CC_OP = CC_OP_EFLAGS;
1173 env->exception_index = -1;
1174 cpu_loop_exit();
1175 }
1176#endif
1177}
1178
1179#ifdef VBOX
1180/**
1181 * Checks and processes external VMM events.
1182 * Called by op_check_external_event() when any of the flags is set and can be serviced.
1183 */
1184void helper_external_event(void)
1185{
1186 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1187 {
1188 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1189 cpu_interrupt(env, CPU_INTERRUPT_HARD);
1190 }
1191 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1192 {
1193 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1194 cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1195 }
1196 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1197 {
1198 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1199 remR3DmaRun(env);
1200 }
1201 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1202 {
1203 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1204 remR3TimersRun(env);
1205 }
1206}
1207#endif /* VBOX */
1208
1209/* real mode interrupt */
1210static void do_interrupt_real(int intno, int is_int, int error_code,
1211 unsigned int next_eip)
1212{
1213 SegmentCache *dt;
1214 target_ulong ptr, ssp;
1215 int selector;
1216 uint32_t offset, esp;
1217 uint32_t old_cs, old_eip;
1218
1219 /* real mode (simpler !) */
1220 dt = &env->idt;
1221 if (intno * 4 + 3 > dt->limit)
1222 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1223 ptr = dt->base + intno * 4;
1224 offset = lduw_kernel(ptr);
1225 selector = lduw_kernel(ptr + 2);
1226 esp = ESP;
1227 ssp = env->segs[R_SS].base;
1228 if (is_int)
1229 old_eip = next_eip;
1230 else
1231 old_eip = env->eip;
1232 old_cs = env->segs[R_CS].selector;
1233 /* XXX: use SS segment size ? */
1234 PUSHW(ssp, esp, 0xffff, compute_eflags());
1235 PUSHW(ssp, esp, 0xffff, old_cs);
1236 PUSHW(ssp, esp, 0xffff, old_eip);
1237
1238 /* update processor state */
1239 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1240 env->eip = offset;
1241 env->segs[R_CS].selector = selector;
1242 env->segs[R_CS].base = (selector << 4);
1243 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1244}
1245
1246/* fake user mode interrupt */
1247void do_interrupt_user(int intno, int is_int, int error_code,
1248 target_ulong next_eip)
1249{
1250 SegmentCache *dt;
1251 target_ulong ptr;
1252 int dpl, cpl;
1253 uint32_t e2;
1254
1255 dt = &env->idt;
1256 ptr = dt->base + (intno * 8);
1257 e2 = ldl_kernel(ptr + 4);
1258
1259 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1260 cpl = env->hflags & HF_CPL_MASK;
1261 /* check privledge if software int */
1262 if (is_int && dpl < cpl)
1263 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1264
1265 /* Since we emulate only user space, we cannot do more than
1266 exiting the emulation with the suitable exception and error
1267 code */
1268 if (is_int)
1269 EIP = next_eip;
1270}
1271
1272/*
1273 * Begin execution of an interruption. is_int is TRUE if coming from
1274 * the int instruction. next_eip is the EIP value AFTER the interrupt
1275 * instruction. It is only relevant if is_int is TRUE.
1276 */
1277void do_interrupt(int intno, int is_int, int error_code,
1278 target_ulong next_eip, int is_hw)
1279{
1280#ifdef DEBUG_PCALL
1281 if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) {
1282 if ((env->cr[0] & CR0_PE_MASK)) {
1283 static int count;
1284 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1285 count, intno, error_code, is_int,
1286 env->hflags & HF_CPL_MASK,
1287 env->segs[R_CS].selector, EIP,
1288 (int)env->segs[R_CS].base + EIP,
1289 env->segs[R_SS].selector, ESP);
1290 if (intno == 0x0e) {
1291 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1292 } else {
1293 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1294 }
1295 fprintf(logfile, "\n");
1296#if 0
1297 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1298 {
1299 int i;
1300 uint8_t *ptr;
1301 fprintf(logfile, " code=");
1302 ptr = env->segs[R_CS].base + env->eip;
1303 for(i = 0; i < 16; i++) {
1304 fprintf(logfile, " %02x", ldub(ptr + i));
1305 }
1306 fprintf(logfile, "\n");
1307 }
1308#endif
1309 count++;
1310 }
1311 }
1312#endif
1313 if (env->cr[0] & CR0_PE_MASK) {
1314#if TARGET_X86_64
1315 if (env->hflags & HF_LMA_MASK) {
1316 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1317 } else
1318#endif
1319 {
1320#ifdef VBOX
1321 /* int xx *, v86 code and VME enabled? */
1322 if ( (env->eflags & VM_MASK)
1323 && (env->cr[4] & CR4_VME_MASK)
1324 && is_int
1325 && !is_hw
1326 && env->eip + 1 != next_eip /* single byte int 3 goes straight to the protected mode handler */
1327 )
1328 do_soft_interrupt_vme(intno, error_code, next_eip);
1329 else
1330#endif
1331 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1332 }
1333 } else {
1334 do_interrupt_real(intno, is_int, error_code, next_eip);
1335 }
1336}
1337
1338/*
1339 * Signal an interruption. It is executed in the main CPU loop.
1340 * is_int is TRUE if coming from the int instruction. next_eip is the
1341 * EIP value AFTER the interrupt instruction. It is only relevant if
1342 * is_int is TRUE.
1343 */
1344void raise_interrupt(int intno, int is_int, int error_code,
1345 int next_eip_addend)
1346{
1347#if defined(VBOX) && defined(DEBUG) && !defined(DEBUG_dmik)
1348 Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend));
1349#endif
1350 env->exception_index = intno;
1351 env->error_code = error_code;
1352 env->exception_is_int = is_int;
1353 env->exception_next_eip = env->eip + next_eip_addend;
1354 cpu_loop_exit();
1355}
1356
1357/* same as raise_exception_err, but do not restore global registers */
1358static void raise_exception_err_norestore(int exception_index, int error_code)
1359{
1360 env->exception_index = exception_index;
1361 env->error_code = error_code;
1362 env->exception_is_int = 0;
1363 env->exception_next_eip = 0;
1364 longjmp(env->jmp_env, 1);
1365}
1366
1367/* shortcuts to generate exceptions */
1368
1369void (raise_exception_err)(int exception_index, int error_code)
1370{
1371 raise_interrupt(exception_index, 0, error_code, 0);
1372}
1373
1374void raise_exception(int exception_index)
1375{
1376 raise_interrupt(exception_index, 0, 0, 0);
1377}
1378
1379#ifdef BUGGY_GCC_DIV64
1380/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1381 call it from another function */
1382uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1383{
1384 *q_ptr = num / den;
1385 return num % den;
1386}
1387
1388int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1389{
1390 *q_ptr = num / den;
1391 return num % den;
1392}
1393#endif
1394
1395void helper_divl_EAX_T0(void)
1396{
1397 unsigned int den, r;
1398 uint64_t num, q;
1399
1400 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1401 den = T0;
1402 if (den == 0) {
1403 raise_exception(EXCP00_DIVZ);
1404 }
1405#ifdef BUGGY_GCC_DIV64
1406 r = div32(&q, num, den);
1407#else
1408 q = (num / den);
1409 r = (num % den);
1410#endif
1411 if (q > 0xffffffff)
1412 raise_exception(EXCP00_DIVZ);
1413 EAX = (uint32_t)q;
1414 EDX = (uint32_t)r;
1415}
1416
1417void helper_idivl_EAX_T0(void)
1418{
1419 int den, r;
1420 int64_t num, q;
1421
1422 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1423 den = T0;
1424 if (den == 0) {
1425 raise_exception(EXCP00_DIVZ);
1426 }
1427#ifdef BUGGY_GCC_DIV64
1428 r = idiv32(&q, num, den);
1429#else
1430 q = (num / den);
1431 r = (num % den);
1432#endif
1433 if (q != (int32_t)q)
1434 raise_exception(EXCP00_DIVZ);
1435 EAX = (uint32_t)q;
1436 EDX = (uint32_t)r;
1437}
1438
1439void helper_cmpxchg8b(void)
1440{
1441 uint64_t d;
1442 int eflags;
1443
1444 eflags = cc_table[CC_OP].compute_all();
1445 d = ldq(A0);
1446 if (d == (((uint64_t)EDX << 32) | EAX)) {
1447 stq(A0, ((uint64_t)ECX << 32) | EBX);
1448 eflags |= CC_Z;
1449 } else {
1450 EDX = d >> 32;
1451 EAX = d;
1452 eflags &= ~CC_Z;
1453 }
1454 CC_SRC = eflags;
1455}
1456
1457void helper_cpuid(void)
1458{
1459#ifndef VBOX
1460 switch((uint32_t)EAX) {
1461 case 0:
1462 EAX = 2; /* max EAX index supported */
1463 EBX = env->cpuid_vendor1;
1464 EDX = env->cpuid_vendor2;
1465 ECX = env->cpuid_vendor3;
1466 break;
1467 case 1:
1468 EAX = env->cpuid_version;
1469 EBX = 0;
1470 ECX = env->cpuid_ext_features;
1471 EDX = env->cpuid_features;
1472 break;
1473
1474 default:
1475 /* cache info: needed for Pentium Pro compatibility */
1476 EAX = 0x410601;
1477 EBX = 0;
1478 ECX = 0;
1479 EDX = 0;
1480 break;
1481
1482#ifdef TARGET_X86_64
1483 case 0x80000000:
1484 EAX = 0x80000008;
1485 EBX = env->cpuid_vendor1;
1486 EDX = env->cpuid_vendor2;
1487 ECX = env->cpuid_vendor3;
1488 break;
1489 case 0x80000001:
1490 EAX = env->cpuid_features;
1491 EBX = 0;
1492 ECX = 0;
1493 /* long mode + syscall/sysret features */
1494 EDX = (env->cpuid_features & 0x0183F3FF) | (1 << 29) | (1 << 11);
1495 break;
1496 case 0x80000008:
1497 /* virtual & phys address size in low 2 bytes. */
1498 EAX = 0x00003028;
1499 EBX = 0;
1500 ECX = 0;
1501 EDX = 0;
1502 break;
1503#endif
1504 }
1505#else /* VBOX */
1506 remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1507#endif /* VBOX */
1508}
1509
1510void helper_enter_level(int level, int data32)
1511{
1512 target_ulong ssp;
1513 uint32_t esp_mask, esp, ebp;
1514
1515 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1516 ssp = env->segs[R_SS].base;
1517 ebp = EBP;
1518 esp = ESP;
1519 if (data32) {
1520 /* 32 bit */
1521 esp -= 4;
1522 while (--level) {
1523 esp -= 4;
1524 ebp -= 4;
1525 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1526 }
1527 esp -= 4;
1528 stl(ssp + (esp & esp_mask), T1);
1529 } else {
1530 /* 16 bit */
1531 esp -= 2;
1532 while (--level) {
1533 esp -= 2;
1534 ebp -= 2;
1535 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1536 }
1537 esp -= 2;
1538 stw(ssp + (esp & esp_mask), T1);
1539 }
1540}
1541
1542#ifdef TARGET_X86_64
1543void helper_enter64_level(int level, int data64)
1544{
1545 target_ulong esp, ebp;
1546 ebp = EBP;
1547 esp = ESP;
1548
1549 if (data64) {
1550 /* 64 bit */
1551 esp -= 8;
1552 while (--level) {
1553 esp -= 8;
1554 ebp -= 8;
1555 stq(esp, ldq(ebp));
1556 }
1557 esp -= 8;
1558 stq(esp, T1);
1559 } else {
1560 /* 16 bit */
1561 esp -= 2;
1562 while (--level) {
1563 esp -= 2;
1564 ebp -= 2;
1565 stw(esp, lduw(ebp));
1566 }
1567 esp -= 2;
1568 stw(esp, T1);
1569 }
1570}
1571#endif
1572
1573void helper_lldt_T0(void)
1574{
1575 int selector;
1576 SegmentCache *dt;
1577 uint32_t e1, e2;
1578 int index, entry_limit;
1579 target_ulong ptr;
1580#ifdef VBOX
1581 Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1582 (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1583#endif
1584
1585 selector = T0 & 0xffff;
1586 if ((selector & 0xfffc) == 0) {
1587 /* XXX: NULL selector case: invalid LDT */
1588 env->ldt.base = 0;
1589 env->ldt.limit = 0;
1590 } else {
1591 if (selector & 0x4)
1592 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1593 dt = &env->gdt;
1594 index = selector & ~7;
1595#ifdef TARGET_X86_64
1596 if (env->hflags & HF_LMA_MASK)
1597 entry_limit = 15;
1598 else
1599#endif
1600 entry_limit = 7;
1601 if ((index + entry_limit) > dt->limit)
1602 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1603 ptr = dt->base + index;
1604 e1 = ldl_kernel(ptr);
1605 e2 = ldl_kernel(ptr + 4);
1606 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1607 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1608 if (!(e2 & DESC_P_MASK))
1609 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1610#ifdef TARGET_X86_64
1611 if (env->hflags & HF_LMA_MASK) {
1612 uint32_t e3;
1613 e3 = ldl_kernel(ptr + 8);
1614 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1615 env->ldt.base |= (target_ulong)e3 << 32;
1616 } else
1617#endif
1618 {
1619 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1620 }
1621 }
1622 env->ldt.selector = selector;
1623#ifdef VBOX
1624 Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
1625 (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
1626#endif
1627}
1628
1629void helper_ltr_T0(void)
1630{
1631 int selector;
1632 SegmentCache *dt;
1633 uint32_t e1, e2;
1634 int index, type, entry_limit;
1635 target_ulong ptr;
1636#ifdef VBOX
1637 Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
1638 (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
1639 env->tr.flags, (RTSEL)(T0 & 0xffff)));
1640#endif
1641
1642 selector = T0 & 0xffff;
1643 if ((selector & 0xfffc) == 0) {
1644 /* NULL selector case: invalid TR */
1645 env->tr.base = 0;
1646 env->tr.limit = 0;
1647 env->tr.flags = 0;
1648 } else {
1649 if (selector & 0x4)
1650 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1651 dt = &env->gdt;
1652 index = selector & ~7;
1653#ifdef TARGET_X86_64
1654 if (env->hflags & HF_LMA_MASK)
1655 entry_limit = 15;
1656 else
1657#endif
1658 entry_limit = 7;
1659 if ((index + entry_limit) > dt->limit)
1660 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1661 ptr = dt->base + index;
1662 e1 = ldl_kernel(ptr);
1663 e2 = ldl_kernel(ptr + 4);
1664 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1665 if ((e2 & DESC_S_MASK) ||
1666 (type != 1 && type != 9))
1667 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1668 if (!(e2 & DESC_P_MASK))
1669 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1670#ifdef TARGET_X86_64
1671 if (env->hflags & HF_LMA_MASK) {
1672 uint32_t e3;
1673 e3 = ldl_kernel(ptr + 8);
1674 load_seg_cache_raw_dt(&env->tr, e1, e2);
1675 env->tr.base |= (target_ulong)e3 << 32;
1676 } else
1677#endif
1678 {
1679 load_seg_cache_raw_dt(&env->tr, e1, e2);
1680 }
1681 e2 |= DESC_TSS_BUSY_MASK;
1682 stl_kernel(ptr + 4, e2);
1683 }
1684 env->tr.selector = selector;
1685#ifdef VBOX
1686 Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
1687 (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
1688 env->tr.flags, (RTSEL)(T0 & 0xffff)));
1689#endif
1690}
1691
1692/* only works if protected mode and not VM86. seg_reg must be != R_CS */
1693void load_seg(int seg_reg, int selector)
1694{
1695 uint32_t e1, e2;
1696 int cpl, dpl, rpl;
1697 SegmentCache *dt;
1698 int index;
1699 target_ulong ptr;
1700
1701 selector &= 0xffff;
1702 cpl = env->hflags & HF_CPL_MASK;
1703
1704#ifdef VBOX
1705 /* Trying to load a selector with CPL=1? */
1706 if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0))
1707 {
1708 Log(("RPL 1 -> sel %04X -> %04X\n", selector, selector & 0xfffc));
1709 selector = selector & 0xfffc;
1710 }
1711#endif
1712
1713 if ((selector & 0xfffc) == 0) {
1714 /* null selector case */
1715 if (seg_reg == R_SS
1716#ifdef TARGET_X86_64
1717 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1718#endif
1719 )
1720 raise_exception_err(EXCP0D_GPF, 0);
1721 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1722 } else {
1723
1724 if (selector & 0x4)
1725 dt = &env->ldt;
1726 else
1727 dt = &env->gdt;
1728 index = selector & ~7;
1729 if ((index + 7) > dt->limit)
1730 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1731 ptr = dt->base + index;
1732 e1 = ldl_kernel(ptr);
1733 e2 = ldl_kernel(ptr + 4);
1734
1735 if (!(e2 & DESC_S_MASK))
1736 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1737 rpl = selector & 3;
1738 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1739 if (seg_reg == R_SS) {
1740 /* must be writable segment */
1741 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
1742 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1743 if (rpl != cpl || dpl != cpl)
1744 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1745 } else {
1746 /* must be readable segment */
1747 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
1748 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1749
1750 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1751 /* if not conforming code, test rights */
1752 if (dpl < cpl || dpl < rpl)
1753 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1754 }
1755 }
1756
1757 if (!(e2 & DESC_P_MASK)) {
1758 if (seg_reg == R_SS)
1759 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1760 else
1761 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1762 }
1763
1764 /* set the access bit if not already set */
1765 if (!(e2 & DESC_A_MASK)) {
1766 e2 |= DESC_A_MASK;
1767 stl_kernel(ptr + 4, e2);
1768 }
1769
1770 cpu_x86_load_seg_cache(env, seg_reg, selector,
1771 get_seg_base(e1, e2),
1772 get_seg_limit(e1, e2),
1773 e2);
1774#if 0
1775 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1776 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1777#endif
1778 }
1779}
1780
1781/* protected mode jump */
1782void helper_ljmp_protected_T0_T1(int next_eip_addend)
1783{
1784 int new_cs, gate_cs, type;
1785 uint32_t e1, e2, cpl, dpl, rpl, limit;
1786 target_ulong new_eip, next_eip;
1787
1788 new_cs = T0;
1789 new_eip = T1;
1790 if ((new_cs & 0xfffc) == 0)
1791 raise_exception_err(EXCP0D_GPF, 0);
1792 if (load_segment(&e1, &e2, new_cs) != 0)
1793 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1794 cpl = env->hflags & HF_CPL_MASK;
1795 if (e2 & DESC_S_MASK) {
1796 if (!(e2 & DESC_CS_MASK))
1797 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1798 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1799 if (e2 & DESC_C_MASK) {
1800 /* conforming code segment */
1801 if (dpl > cpl)
1802 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1803 } else {
1804 /* non conforming code segment */
1805 rpl = new_cs & 3;
1806 if (rpl > cpl)
1807 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1808 if (dpl != cpl)
1809 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1810 }
1811 if (!(e2 & DESC_P_MASK))
1812 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1813 limit = get_seg_limit(e1, e2);
1814 if (new_eip > limit &&
1815 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
1816 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1817 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1818 get_seg_base(e1, e2), limit, e2);
1819 EIP = new_eip;
1820 } else {
1821 /* jump to call or task gate */
1822 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1823 rpl = new_cs & 3;
1824 cpl = env->hflags & HF_CPL_MASK;
1825 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1826 switch(type) {
1827 case 1: /* 286 TSS */
1828 case 9: /* 386 TSS */
1829 case 5: /* task gate */
1830 if (dpl < cpl || dpl < rpl)
1831 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1832 next_eip = env->eip + next_eip_addend;
1833 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1834 CC_OP = CC_OP_EFLAGS;
1835 break;
1836 case 4: /* 286 call gate */
1837 case 12: /* 386 call gate */
1838 if ((dpl < cpl) || (dpl < rpl))
1839 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1840 if (!(e2 & DESC_P_MASK))
1841 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1842 gate_cs = e1 >> 16;
1843 new_eip = (e1 & 0xffff);
1844 if (type == 12)
1845 new_eip |= (e2 & 0xffff0000);
1846 if (load_segment(&e1, &e2, gate_cs) != 0)
1847 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1848 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1849 /* must be code segment */
1850 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1851 (DESC_S_MASK | DESC_CS_MASK)))
1852 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1853 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1854 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
1855 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1856 if (!(e2 & DESC_P_MASK))
1857 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1858 limit = get_seg_limit(e1, e2);
1859 if (new_eip > limit)
1860 raise_exception_err(EXCP0D_GPF, 0);
1861 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1862 get_seg_base(e1, e2), limit, e2);
1863 EIP = new_eip;
1864 break;
1865 default:
1866 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1867 break;
1868 }
1869 }
1870}
1871
1872/* real mode call */
1873void helper_lcall_real_T0_T1(int shift, int next_eip)
1874{
1875 int new_cs, new_eip;
1876 uint32_t esp, esp_mask;
1877 target_ulong ssp;
1878
1879 new_cs = T0;
1880 new_eip = T1;
1881 esp = ESP;
1882 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1883 ssp = env->segs[R_SS].base;
1884 if (shift) {
1885 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1886 PUSHL(ssp, esp, esp_mask, next_eip);
1887 } else {
1888 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1889 PUSHW(ssp, esp, esp_mask, next_eip);
1890 }
1891
1892 ESP = (ESP & ~esp_mask) | (esp & esp_mask);
1893 env->eip = new_eip;
1894 env->segs[R_CS].selector = new_cs;
1895 env->segs[R_CS].base = (new_cs << 4);
1896}
1897
1898/* protected mode call */
1899void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
1900{
1901 int new_cs, new_stack, i;
1902 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1903 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
1904 uint32_t val, limit, old_sp_mask;
1905 target_ulong ssp, old_ssp, next_eip, new_eip;
1906
1907 new_cs = T0;
1908 new_eip = T1;
1909 next_eip = env->eip + next_eip_addend;
1910#ifdef DEBUG_PCALL
1911 if (loglevel & CPU_LOG_PCALL) {
1912 fprintf(logfile, "lcall %04x:%08x s=%d\n",
1913 new_cs, (uint32_t)new_eip, shift);
1914 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1915 }
1916#endif
1917 if ((new_cs & 0xfffc) == 0)
1918 raise_exception_err(EXCP0D_GPF, 0);
1919 if (load_segment(&e1, &e2, new_cs) != 0)
1920 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1921 cpl = env->hflags & HF_CPL_MASK;
1922#ifdef DEBUG_PCALL
1923 if (loglevel & CPU_LOG_PCALL) {
1924 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
1925 }
1926#endif
1927 if (e2 & DESC_S_MASK) {
1928 if (!(e2 & DESC_CS_MASK))
1929 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1930 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1931 if (e2 & DESC_C_MASK) {
1932 /* conforming code segment */
1933 if (dpl > cpl)
1934 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1935 } else {
1936 /* non conforming code segment */
1937 rpl = new_cs & 3;
1938 if (rpl > cpl)
1939 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1940 if (dpl != cpl)
1941 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1942 }
1943 if (!(e2 & DESC_P_MASK))
1944 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1945
1946#ifdef TARGET_X86_64
1947 /* XXX: check 16/32 bit cases in long mode */
1948 if (shift == 2) {
1949 target_ulong rsp;
1950 /* 64 bit case */
1951 rsp = ESP;
1952 PUSHQ(rsp, env->segs[R_CS].selector);
1953 PUSHQ(rsp, next_eip);
1954 /* from this point, not restartable */
1955 ESP = rsp;
1956 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1957 get_seg_base(e1, e2),
1958 get_seg_limit(e1, e2), e2);
1959 EIP = new_eip;
1960 } else
1961#endif
1962 {
1963 sp = ESP;
1964 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1965 ssp = env->segs[R_SS].base;
1966 if (shift) {
1967 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1968 PUSHL(ssp, sp, sp_mask, next_eip);
1969 } else {
1970 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1971 PUSHW(ssp, sp, sp_mask, next_eip);
1972 }
1973
1974 limit = get_seg_limit(e1, e2);
1975 if (new_eip > limit)
1976 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1977 /* from this point, not restartable */
1978 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1979 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1980 get_seg_base(e1, e2), limit, e2);
1981 EIP = new_eip;
1982 }
1983 } else {
1984 /* check gate type */
1985 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1986 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1987 rpl = new_cs & 3;
1988 switch(type) {
1989 case 1: /* available 286 TSS */
1990 case 9: /* available 386 TSS */
1991 case 5: /* task gate */
1992 if (dpl < cpl || dpl < rpl)
1993 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1994 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1995 CC_OP = CC_OP_EFLAGS;
1996 return;
1997 case 4: /* 286 call gate */
1998 case 12: /* 386 call gate */
1999 break;
2000 default:
2001 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2002 break;
2003 }
2004 shift = type >> 3;
2005
2006 if (dpl < cpl || dpl < rpl)
2007 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2008 /* check valid bit */
2009 if (!(e2 & DESC_P_MASK))
2010 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2011 selector = e1 >> 16;
2012 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
2013 param_count = e2 & 0x1f;
2014 if ((selector & 0xfffc) == 0)
2015 raise_exception_err(EXCP0D_GPF, 0);
2016
2017 if (load_segment(&e1, &e2, selector) != 0)
2018 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2019 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
2020 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2021 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2022 if (dpl > cpl)
2023 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2024 if (!(e2 & DESC_P_MASK))
2025 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2026
2027 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2028 /* to inner priviledge */
2029 get_ss_esp_from_tss(&ss, &sp, dpl);
2030#ifdef DEBUG_PCALL
2031 if (loglevel & CPU_LOG_PCALL)
2032 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2033 ss, sp, param_count, ESP);
2034#endif
2035 if ((ss & 0xfffc) == 0)
2036 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2037 if ((ss & 3) != dpl)
2038 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2039 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2040 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2041 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2042 if (ss_dpl != dpl)
2043 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2044 if (!(ss_e2 & DESC_S_MASK) ||
2045 (ss_e2 & DESC_CS_MASK) ||
2046 !(ss_e2 & DESC_W_MASK))
2047 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2048 if (!(ss_e2 & DESC_P_MASK))
2049 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2050
2051 // push_size = ((param_count * 2) + 8) << shift;
2052
2053 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2054 old_ssp = env->segs[R_SS].base;
2055
2056 sp_mask = get_sp_mask(ss_e2);
2057 ssp = get_seg_base(ss_e1, ss_e2);
2058 if (shift) {
2059 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2060 PUSHL(ssp, sp, sp_mask, ESP);
2061 for(i = param_count - 1; i >= 0; i--) {
2062 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2063 PUSHL(ssp, sp, sp_mask, val);
2064 }
2065 } else {
2066 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2067 PUSHW(ssp, sp, sp_mask, ESP);
2068 for(i = param_count - 1; i >= 0; i--) {
2069 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2070 PUSHW(ssp, sp, sp_mask, val);
2071 }
2072 }
2073 new_stack = 1;
2074 } else {
2075 /* to same priviledge */
2076 sp = ESP;
2077 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2078 ssp = env->segs[R_SS].base;
2079 // push_size = (4 << shift);
2080 new_stack = 0;
2081 }
2082
2083 if (shift) {
2084 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2085 PUSHL(ssp, sp, sp_mask, next_eip);
2086 } else {
2087 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2088 PUSHW(ssp, sp, sp_mask, next_eip);
2089 }
2090
2091 /* from this point, not restartable */
2092
2093 if (new_stack) {
2094 ss = (ss & ~3) | dpl;
2095 cpu_x86_load_seg_cache(env, R_SS, ss,
2096 ssp,
2097 get_seg_limit(ss_e1, ss_e2),
2098 ss_e2);
2099 }
2100
2101 selector = (selector & ~3) | dpl;
2102 cpu_x86_load_seg_cache(env, R_CS, selector,
2103 get_seg_base(e1, e2),
2104 get_seg_limit(e1, e2),
2105 e2);
2106 cpu_x86_set_cpl(env, dpl);
2107 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2108 EIP = offset;
2109 }
2110#ifdef USE_KQEMU
2111 if (kqemu_is_ok(env)) {
2112 env->exception_index = -1;
2113 cpu_loop_exit();
2114 }
2115#endif
2116}
2117
2118/* real and vm86 mode iret */
2119void helper_iret_real(int shift)
2120{
2121 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2122 target_ulong ssp;
2123 int eflags_mask;
2124
2125#ifdef VBOX
2126 bool fVME = false;
2127
2128 remR3TrapClear(env->pVM);
2129#endif
2130
2131 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2132 sp = ESP;
2133 ssp = env->segs[R_SS].base;
2134 if (shift == 1) {
2135 /* 32 bits */
2136 POPL(ssp, sp, sp_mask, new_eip);
2137 POPL(ssp, sp, sp_mask, new_cs);
2138 new_cs &= 0xffff;
2139 POPL(ssp, sp, sp_mask, new_eflags);
2140 } else {
2141 /* 16 bits */
2142 POPW(ssp, sp, sp_mask, new_eip);
2143 POPW(ssp, sp, sp_mask, new_cs);
2144 POPW(ssp, sp, sp_mask, new_eflags);
2145 }
2146#ifdef VBOX
2147 if ( (env->eflags & VM_MASK)
2148 && ((env->eflags >> IOPL_SHIFT) & 3) != 3
2149 && (env->cr[4] & CR4_VME_MASK)) /* implied or else we would fault earlier */
2150 {
2151 fVME = true;
2152 /* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
2153 /* if TF will be set -> #GP */
2154 if ( ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
2155 || (new_eflags & TF_MASK))
2156 {
2157 raise_exception(EXCP0D_GPF);
2158 }
2159 }
2160#endif
2161
2162 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2163 load_seg_vm(R_CS, new_cs);
2164 env->eip = new_eip;
2165#ifdef VBOX
2166 if (fVME)
2167 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2168 else
2169#endif
2170 if (env->eflags & VM_MASK)
2171 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
2172 else
2173 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
2174 if (shift == 0)
2175 eflags_mask &= 0xffff;
2176
2177 load_eflags(new_eflags, eflags_mask);
2178
2179#ifdef VBOX
2180 if (fVME)
2181 {
2182 if (new_eflags & IF_MASK)
2183 env->eflags |= VIF_MASK;
2184 else
2185 env->eflags &= ~VIF_MASK;
2186 }
2187#endif
2188}
2189
2190static inline void validate_seg(int seg_reg, int cpl)
2191{
2192 int dpl;
2193 uint32_t e2;
2194
2195 e2 = env->segs[seg_reg].flags;
2196 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2197 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2198 /* data or non conforming code segment */
2199 if (dpl < cpl) {
2200 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2201 }
2202 }
2203}
2204
2205/* protected mode iret */
2206static inline void helper_ret_protected(int shift, int is_iret, int addend)
2207{
2208 uint32_t new_cs, new_eflags, new_ss;
2209 uint32_t new_es, new_ds, new_fs, new_gs;
2210 uint32_t e1, e2, ss_e1, ss_e2;
2211 int cpl, dpl, rpl, eflags_mask, iopl;
2212 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2213
2214#ifdef TARGET_X86_64
2215 if (shift == 2)
2216 sp_mask = -1;
2217 else
2218#endif
2219 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2220 sp = ESP;
2221 ssp = env->segs[R_SS].base;
2222 new_eflags = 0; /* avoid warning */
2223#ifdef TARGET_X86_64
2224 if (shift == 2) {
2225 POPQ(sp, new_eip);
2226 POPQ(sp, new_cs);
2227 new_cs &= 0xffff;
2228 if (is_iret) {
2229 POPQ(sp, new_eflags);
2230 }
2231 } else
2232#endif
2233 if (shift == 1) {
2234 /* 32 bits */
2235 POPL(ssp, sp, sp_mask, new_eip);
2236 POPL(ssp, sp, sp_mask, new_cs);
2237 new_cs &= 0xffff;
2238 if (is_iret) {
2239 POPL(ssp, sp, sp_mask, new_eflags);
2240#if defined(VBOX) && defined(DEBUG)
2241 printf("iret: new CS %04X\n", new_cs);
2242 printf("iret: new EIP %08X\n", new_eip);
2243 printf("iret: new EFLAGS %08X\n", new_eflags);
2244 printf("iret: EAX=%08x\n", EAX);
2245#endif
2246
2247 if (new_eflags & VM_MASK)
2248 goto return_to_vm86;
2249 }
2250#ifdef VBOX
2251 if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
2252 {
2253#ifdef DEBUG
2254 printf("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc);
2255#endif
2256 new_cs = new_cs & 0xfffc;
2257 }
2258#endif
2259 } else {
2260 /* 16 bits */
2261 POPW(ssp, sp, sp_mask, new_eip);
2262 POPW(ssp, sp, sp_mask, new_cs);
2263 if (is_iret)
2264 POPW(ssp, sp, sp_mask, new_eflags);
2265 }
2266#ifdef DEBUG_PCALL
2267 if (loglevel & CPU_LOG_PCALL) {
2268 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2269 new_cs, new_eip, shift, addend);
2270 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2271 }
2272#endif
2273 if ((new_cs & 0xfffc) == 0)
2274 {
2275#if defined(VBOX) && defined(DEBUG)
2276 printf("new_cs & 0xfffc) == 0\n");
2277#endif
2278 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2279 }
2280 if (load_segment(&e1, &e2, new_cs) != 0)
2281 {
2282#if defined(VBOX) && defined(DEBUG)
2283 printf("load_segment failed\n");
2284#endif
2285 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2286 }
2287 if (!(e2 & DESC_S_MASK) ||
2288 !(e2 & DESC_CS_MASK))
2289 {
2290#if defined(VBOX) && defined(DEBUG)
2291 printf("e2 mask %08x\n", e2);
2292#endif
2293 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2294 }
2295 cpl = env->hflags & HF_CPL_MASK;
2296 rpl = new_cs & 3;
2297 if (rpl < cpl)
2298 {
2299#if defined(VBOX) && defined(DEBUG)
2300 printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2301#endif
2302 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2303 }
2304 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2305 if (e2 & DESC_C_MASK) {
2306 if (dpl > rpl)
2307 {
2308#if defined(VBOX) && defined(DEBUG)
2309 printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2310#endif
2311 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2312 }
2313 } else {
2314 if (dpl != rpl)
2315 {
2316#if defined(VBOX) && defined(DEBUG)
2317 printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2318#endif
2319 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2320 }
2321 }
2322 if (!(e2 & DESC_P_MASK))
2323 {
2324#if defined(VBOX) && defined(DEBUG)
2325 printf("DESC_P_MASK e2=%08x\n", e2);
2326#endif
2327 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2328 }
2329 sp += addend;
2330 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2331 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2332 /* return to same priledge level */
2333 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2334 get_seg_base(e1, e2),
2335 get_seg_limit(e1, e2),
2336 e2);
2337 } else {
2338 /* return to different priviledge level */
2339#ifdef TARGET_X86_64
2340 if (shift == 2) {
2341 POPQ(sp, new_esp);
2342 POPQ(sp, new_ss);
2343 new_ss &= 0xffff;
2344 } else
2345#endif
2346 if (shift == 1) {
2347 /* 32 bits */
2348 POPL(ssp, sp, sp_mask, new_esp);
2349 POPL(ssp, sp, sp_mask, new_ss);
2350 new_ss &= 0xffff;
2351 } else {
2352 /* 16 bits */
2353 POPW(ssp, sp, sp_mask, new_esp);
2354 POPW(ssp, sp, sp_mask, new_ss);
2355 }
2356#ifdef DEBUG_PCALL
2357 if (loglevel & CPU_LOG_PCALL) {
2358 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2359 new_ss, new_esp);
2360 }
2361#endif
2362 if ((new_ss & 0xfffc) == 0) {
2363#ifdef TARGET_X86_64
2364 /* NULL ss is allowed in long mode if cpl != 3*/
2365 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2366 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2367 0, 0xffffffff,
2368 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2369 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2370 DESC_W_MASK | DESC_A_MASK);
2371 } else
2372#endif
2373 {
2374 raise_exception_err(EXCP0D_GPF, 0);
2375 }
2376 } else {
2377 if ((new_ss & 3) != rpl)
2378 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2379 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2380 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2381 if (!(ss_e2 & DESC_S_MASK) ||
2382 (ss_e2 & DESC_CS_MASK) ||
2383 !(ss_e2 & DESC_W_MASK))
2384 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2385 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2386 if (dpl != rpl)
2387 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2388 if (!(ss_e2 & DESC_P_MASK))
2389 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2390 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2391 get_seg_base(ss_e1, ss_e2),
2392 get_seg_limit(ss_e1, ss_e2),
2393 ss_e2);
2394 }
2395
2396 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2397 get_seg_base(e1, e2),
2398 get_seg_limit(e1, e2),
2399 e2);
2400 cpu_x86_set_cpl(env, rpl);
2401 sp = new_esp;
2402#ifdef TARGET_X86_64
2403 if (env->hflags & HF_CS64_MASK)
2404 sp_mask = -1;
2405 else
2406#endif
2407 sp_mask = get_sp_mask(ss_e2);
2408
2409 /* validate data segments */
2410 validate_seg(R_ES, rpl);
2411 validate_seg(R_DS, rpl);
2412 validate_seg(R_FS, rpl);
2413 validate_seg(R_GS, rpl);
2414
2415 sp += addend;
2416 }
2417 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2418 env->eip = new_eip;
2419 if (is_iret) {
2420 /* NOTE: 'cpl' is the _old_ CPL */
2421 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2422 if (cpl == 0)
2423#ifdef VBOX
2424 eflags_mask |= IOPL_MASK | VIF_MASK | VIP_MASK;
2425#else
2426 eflags_mask |= IOPL_MASK;
2427#endif
2428
2429 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2430 if (cpl <= iopl)
2431 eflags_mask |= IF_MASK;
2432 if (shift == 0)
2433 eflags_mask &= 0xffff;
2434 load_eflags(new_eflags, eflags_mask);
2435 }
2436 return;
2437
2438 return_to_vm86:
2439
2440#if 0 // defined(VBOX) && defined(DEBUG)
2441 printf("V86: new CS %04X\n", new_cs);
2442 printf("V86: Descriptor %08X:%08X\n", e2, e1);
2443 printf("V86: new EIP %08X\n", new_eip);
2444 printf("V86: new EFLAGS %08X\n", new_eflags);
2445#endif
2446
2447 POPL(ssp, sp, sp_mask, new_esp);
2448 POPL(ssp, sp, sp_mask, new_ss);
2449 POPL(ssp, sp, sp_mask, new_es);
2450 POPL(ssp, sp, sp_mask, new_ds);
2451 POPL(ssp, sp, sp_mask, new_fs);
2452 POPL(ssp, sp, sp_mask, new_gs);
2453
2454 /* modify processor state */
2455 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
2456 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
2457 load_seg_vm(R_CS, new_cs & 0xffff);
2458 cpu_x86_set_cpl(env, 3);
2459 load_seg_vm(R_SS, new_ss & 0xffff);
2460 load_seg_vm(R_ES, new_es & 0xffff);
2461 load_seg_vm(R_DS, new_ds & 0xffff);
2462 load_seg_vm(R_FS, new_fs & 0xffff);
2463 load_seg_vm(R_GS, new_gs & 0xffff);
2464
2465 env->eip = new_eip & 0xffff;
2466 ESP = new_esp;
2467}
2468
2469void helper_iret_protected(int shift, int next_eip)
2470{
2471 int tss_selector, type;
2472 uint32_t e1, e2;
2473
2474#ifdef VBOX
2475 remR3TrapClear(env->pVM);
2476#endif
2477
2478 /* specific case for TSS */
2479 if (env->eflags & NT_MASK) {
2480#ifdef TARGET_X86_64
2481 if (env->hflags & HF_LMA_MASK)
2482 raise_exception_err(EXCP0D_GPF, 0);
2483#endif
2484 tss_selector = lduw_kernel(env->tr.base + 0);
2485 if (tss_selector & 4)
2486 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2487 if (load_segment(&e1, &e2, tss_selector) != 0)
2488 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2489 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2490 /* NOTE: we check both segment and busy TSS */
2491 if (type != 3)
2492 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2493 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2494 } else {
2495 helper_ret_protected(shift, 1, 0);
2496 }
2497}
2498
2499void helper_lret_protected(int shift, int addend)
2500{
2501 helper_ret_protected(shift, 0, addend);
2502}
2503
2504void helper_sysenter(void)
2505{
2506 if (env->sysenter_cs == 0) {
2507 raise_exception_err(EXCP0D_GPF, 0);
2508 }
2509 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2510 cpu_x86_set_cpl(env, 0);
2511 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2512 0, 0xffffffff,
2513 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2514 DESC_S_MASK |
2515 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2516 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2517 0, 0xffffffff,
2518 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2519 DESC_S_MASK |
2520 DESC_W_MASK | DESC_A_MASK);
2521 ESP = env->sysenter_esp;
2522 EIP = env->sysenter_eip;
2523}
2524
2525void helper_sysexit(void)
2526{
2527 int cpl;
2528
2529 cpl = env->hflags & HF_CPL_MASK;
2530 if (env->sysenter_cs == 0 || cpl != 0) {
2531 raise_exception_err(EXCP0D_GPF, 0);
2532 }
2533 cpu_x86_set_cpl(env, 3);
2534 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
2535 0, 0xffffffff,
2536 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2537 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2538 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2539 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
2540 0, 0xffffffff,
2541 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2542 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2543 DESC_W_MASK | DESC_A_MASK);
2544 ESP = ECX;
2545 EIP = EDX;
2546}
2547
2548void helper_movl_crN_T0(int reg)
2549{
2550#if !defined(CONFIG_USER_ONLY)
2551 switch(reg) {
2552 case 0:
2553 cpu_x86_update_cr0(env, T0);
2554 break;
2555 case 3:
2556 cpu_x86_update_cr3(env, T0);
2557 break;
2558 case 4:
2559 cpu_x86_update_cr4(env, T0);
2560 break;
2561 case 8:
2562 cpu_set_apic_tpr(env, T0);
2563 break;
2564 default:
2565 env->cr[reg] = T0;
2566 break;
2567 }
2568#endif
2569}
2570
2571/* XXX: do more */
2572void helper_movl_drN_T0(int reg)
2573{
2574 env->dr[reg] = T0;
2575}
2576
2577void helper_invlpg(unsigned int addr)
2578{
2579 cpu_x86_flush_tlb(env, addr);
2580}
2581
2582void helper_rdtsc(void)
2583{
2584 uint64_t val;
2585
2586 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2587 raise_exception(EXCP0D_GPF);
2588 }
2589 val = cpu_get_tsc(env);
2590 EAX = (uint32_t)(val);
2591 EDX = (uint32_t)(val >> 32);
2592}
2593
2594#if defined(CONFIG_USER_ONLY)
2595void helper_wrmsr(void)
2596{
2597}
2598
2599void helper_rdmsr(void)
2600{
2601}
2602#else
2603void helper_wrmsr(void)
2604{
2605 uint64_t val;
2606
2607 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2608
2609 switch((uint32_t)ECX) {
2610 case MSR_IA32_SYSENTER_CS:
2611 env->sysenter_cs = val & 0xffff;
2612 break;
2613 case MSR_IA32_SYSENTER_ESP:
2614 env->sysenter_esp = val;
2615 break;
2616 case MSR_IA32_SYSENTER_EIP:
2617 env->sysenter_eip = val;
2618 break;
2619 case MSR_IA32_APICBASE:
2620 cpu_set_apic_base(env, val);
2621 break;
2622#ifdef TARGET_X86_64
2623 case MSR_EFER:
2624#define MSR_EFER_UPDATE_MASK (MSR_EFER_SCE | MSR_EFER_LME | \
2625 MSR_EFER_NXE | MSR_EFER_FFXSR)
2626 env->efer = (env->efer & ~MSR_EFER_UPDATE_MASK) |
2627 (val & MSR_EFER_UPDATE_MASK);
2628 break;
2629 case MSR_STAR:
2630 env->star = val;
2631 break;
2632 case MSR_LSTAR:
2633 env->lstar = val;
2634 break;
2635 case MSR_CSTAR:
2636 env->cstar = val;
2637 break;
2638 case MSR_FMASK:
2639 env->fmask = val;
2640 break;
2641 case MSR_FSBASE:
2642 env->segs[R_FS].base = val;
2643 break;
2644 case MSR_GSBASE:
2645 env->segs[R_GS].base = val;
2646 break;
2647 case MSR_KERNELGSBASE:
2648 env->kernelgsbase = val;
2649 break;
2650#endif
2651 default:
2652 /* XXX: exception ? */
2653 break;
2654 }
2655}
2656
2657void helper_rdmsr(void)
2658{
2659 uint64_t val;
2660 switch((uint32_t)ECX) {
2661 case MSR_IA32_SYSENTER_CS:
2662 val = env->sysenter_cs;
2663 break;
2664 case MSR_IA32_SYSENTER_ESP:
2665 val = env->sysenter_esp;
2666 break;
2667 case MSR_IA32_SYSENTER_EIP:
2668 val = env->sysenter_eip;
2669 break;
2670 case MSR_IA32_APICBASE:
2671 val = cpu_get_apic_base(env);
2672 break;
2673#ifdef TARGET_X86_64
2674 case MSR_EFER:
2675 val = env->efer;
2676 break;
2677 case MSR_STAR:
2678 val = env->star;
2679 break;
2680 case MSR_LSTAR:
2681 val = env->lstar;
2682 break;
2683 case MSR_CSTAR:
2684 val = env->cstar;
2685 break;
2686 case MSR_FMASK:
2687 val = env->fmask;
2688 break;
2689 case MSR_FSBASE:
2690 val = env->segs[R_FS].base;
2691 break;
2692 case MSR_GSBASE:
2693 val = env->segs[R_GS].base;
2694 break;
2695 case MSR_KERNELGSBASE:
2696 val = env->kernelgsbase;
2697 break;
2698#endif
2699 default:
2700 /* XXX: exception ? */
2701 val = 0;
2702 break;
2703 }
2704 EAX = (uint32_t)(val);
2705 EDX = (uint32_t)(val >> 32);
2706}
2707#endif
2708
2709void helper_lsl(void)
2710{
2711 unsigned int selector, limit;
2712 uint32_t e1, e2, eflags;
2713 int rpl, dpl, cpl, type;
2714
2715 eflags = cc_table[CC_OP].compute_all();
2716 selector = T0 & 0xffff;
2717 if (load_segment(&e1, &e2, selector) != 0)
2718 goto fail;
2719 rpl = selector & 3;
2720 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2721 cpl = env->hflags & HF_CPL_MASK;
2722 if (e2 & DESC_S_MASK) {
2723 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2724 /* conforming */
2725 } else {
2726 if (dpl < cpl || dpl < rpl)
2727 goto fail;
2728 }
2729 } else {
2730 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2731 switch(type) {
2732 case 1:
2733 case 2:
2734 case 3:
2735 case 9:
2736 case 11:
2737 break;
2738 default:
2739 goto fail;
2740 }
2741 if (dpl < cpl || dpl < rpl) {
2742 fail:
2743 CC_SRC = eflags & ~CC_Z;
2744 return;
2745 }
2746 }
2747 limit = get_seg_limit(e1, e2);
2748 T1 = limit;
2749 CC_SRC = eflags | CC_Z;
2750}
2751
2752void helper_lar(void)
2753{
2754 unsigned int selector;
2755 uint32_t e1, e2, eflags;
2756 int rpl, dpl, cpl, type;
2757
2758 eflags = cc_table[CC_OP].compute_all();
2759 selector = T0 & 0xffff;
2760 if ((selector & 0xfffc) == 0)
2761 goto fail;
2762 if (load_segment(&e1, &e2, selector) != 0)
2763 goto fail;
2764 rpl = selector & 3;
2765 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2766 cpl = env->hflags & HF_CPL_MASK;
2767 if (e2 & DESC_S_MASK) {
2768 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2769 /* conforming */
2770 } else {
2771 if (dpl < cpl || dpl < rpl)
2772 goto fail;
2773 }
2774 } else {
2775 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2776 switch(type) {
2777 case 1:
2778 case 2:
2779 case 3:
2780 case 4:
2781 case 5:
2782 case 9:
2783 case 11:
2784 case 12:
2785 break;
2786 default:
2787 goto fail;
2788 }
2789 if (dpl < cpl || dpl < rpl) {
2790 fail:
2791 CC_SRC = eflags & ~CC_Z;
2792 return;
2793 }
2794 }
2795 T1 = e2 & 0x00f0ff00;
2796 CC_SRC = eflags | CC_Z;
2797}
2798
2799void helper_verr(void)
2800{
2801 unsigned int selector;
2802 uint32_t e1, e2, eflags;
2803 int rpl, dpl, cpl;
2804
2805 eflags = cc_table[CC_OP].compute_all();
2806 selector = T0 & 0xffff;
2807 if ((selector & 0xfffc) == 0)
2808 goto fail;
2809 if (load_segment(&e1, &e2, selector) != 0)
2810 goto fail;
2811 if (!(e2 & DESC_S_MASK))
2812 goto fail;
2813 rpl = selector & 3;
2814 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2815 cpl = env->hflags & HF_CPL_MASK;
2816 if (e2 & DESC_CS_MASK) {
2817 if (!(e2 & DESC_R_MASK))
2818 goto fail;
2819 if (!(e2 & DESC_C_MASK)) {
2820 if (dpl < cpl || dpl < rpl)
2821 goto fail;
2822 }
2823 } else {
2824 if (dpl < cpl || dpl < rpl) {
2825 fail:
2826 CC_SRC = eflags & ~CC_Z;
2827 return;
2828 }
2829 }
2830 CC_SRC = eflags | CC_Z;
2831}
2832
2833void helper_verw(void)
2834{
2835 unsigned int selector;
2836 uint32_t e1, e2, eflags;
2837 int rpl, dpl, cpl;
2838
2839 eflags = cc_table[CC_OP].compute_all();
2840 selector = T0 & 0xffff;
2841 if ((selector & 0xfffc) == 0)
2842 goto fail;
2843 if (load_segment(&e1, &e2, selector) != 0)
2844 goto fail;
2845 if (!(e2 & DESC_S_MASK))
2846 goto fail;
2847 rpl = selector & 3;
2848 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2849 cpl = env->hflags & HF_CPL_MASK;
2850 if (e2 & DESC_CS_MASK) {
2851 goto fail;
2852 } else {
2853 if (dpl < cpl || dpl < rpl)
2854 goto fail;
2855 if (!(e2 & DESC_W_MASK)) {
2856 fail:
2857 CC_SRC = eflags & ~CC_Z;
2858 return;
2859 }
2860 }
2861 CC_SRC = eflags | CC_Z;
2862}
2863
2864/* FPU helpers */
2865
2866void helper_fldt_ST0_A0(void)
2867{
2868 int new_fpstt;
2869 new_fpstt = (env->fpstt - 1) & 7;
2870 env->fpregs[new_fpstt].d = helper_fldt(A0);
2871 env->fpstt = new_fpstt;
2872 env->fptags[new_fpstt] = 0; /* validate stack entry */
2873}
2874
2875void helper_fstt_ST0_A0(void)
2876{
2877 helper_fstt(ST0, A0);
2878}
2879
2880void fpu_set_exception(int mask)
2881{
2882 env->fpus |= mask;
2883 if (env->fpus & (~env->fpuc & FPUC_EM))
2884 env->fpus |= FPUS_SE | FPUS_B;
2885}
2886
2887CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
2888{
2889 if (b == 0.0)
2890 fpu_set_exception(FPUS_ZE);
2891 return a / b;
2892}
2893
2894void fpu_raise_exception(void)
2895{
2896 if (env->cr[0] & CR0_NE_MASK) {
2897 raise_exception(EXCP10_COPR);
2898 }
2899#if !defined(CONFIG_USER_ONLY)
2900 else {
2901 cpu_set_ferr(env);
2902 }
2903#endif
2904}
2905
2906/* BCD ops */
2907
2908void helper_fbld_ST0_A0(void)
2909{
2910 CPU86_LDouble tmp;
2911 uint64_t val;
2912 unsigned int v;
2913 int i;
2914
2915 val = 0;
2916 for(i = 8; i >= 0; i--) {
2917 v = ldub(A0 + i);
2918 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
2919 }
2920 tmp = val;
2921 if (ldub(A0 + 9) & 0x80)
2922 tmp = -tmp;
2923 fpush();
2924 ST0 = tmp;
2925}
2926
2927void helper_fbst_ST0_A0(void)
2928{
2929 CPU86_LDouble tmp;
2930 int v;
2931 target_ulong mem_ref, mem_end;
2932 int64_t val;
2933
2934 tmp = rint(ST0);
2935 val = (int64_t)tmp;
2936 mem_ref = A0;
2937 mem_end = mem_ref + 9;
2938 if (val < 0) {
2939 stb(mem_end, 0x80);
2940 val = -val;
2941 } else {
2942 stb(mem_end, 0x00);
2943 }
2944 while (mem_ref < mem_end) {
2945 if (val == 0)
2946 break;
2947 v = val % 100;
2948 val = val / 100;
2949 v = ((v / 10) << 4) | (v % 10);
2950 stb(mem_ref++, v);
2951 }
2952 while (mem_ref < mem_end) {
2953 stb(mem_ref++, 0);
2954 }
2955}
2956
2957void helper_f2xm1(void)
2958{
2959 ST0 = pow(2.0,ST0) - 1.0;
2960}
2961
2962void helper_fyl2x(void)
2963{
2964 CPU86_LDouble fptemp;
2965
2966 fptemp = ST0;
2967 if (fptemp>0.0){
2968 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
2969 ST1 *= fptemp;
2970 fpop();
2971 } else {
2972 env->fpus &= (~0x4700);
2973 env->fpus |= 0x400;
2974 }
2975}
2976
2977void helper_fptan(void)
2978{
2979 CPU86_LDouble fptemp;
2980
2981 fptemp = ST0;
2982 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2983 env->fpus |= 0x400;
2984 } else {
2985 ST0 = tan(fptemp);
2986 fpush();
2987 ST0 = 1.0;
2988 env->fpus &= (~0x400); /* C2 <-- 0 */
2989 /* the above code is for |arg| < 2**52 only */
2990 }
2991}
2992
2993void helper_fpatan(void)
2994{
2995 CPU86_LDouble fptemp, fpsrcop;
2996
2997 fpsrcop = ST1;
2998 fptemp = ST0;
2999 ST1 = atan2(fpsrcop,fptemp);
3000 fpop();
3001}
3002
3003void helper_fxtract(void)
3004{
3005 CPU86_LDoubleU temp;
3006 unsigned int expdif;
3007
3008 temp.d = ST0;
3009 expdif = EXPD(temp) - EXPBIAS;
3010 /*DP exponent bias*/
3011 ST0 = expdif;
3012 fpush();
3013 BIASEXPONENT(temp);
3014 ST0 = temp.d;
3015}
3016
3017void helper_fprem1(void)
3018{
3019 CPU86_LDouble dblq, fpsrcop, fptemp;
3020 CPU86_LDoubleU fpsrcop1, fptemp1;
3021 int expdif;
3022 int q;
3023
3024 fpsrcop = ST0;
3025 fptemp = ST1;
3026 fpsrcop1.d = fpsrcop;
3027 fptemp1.d = fptemp;
3028 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3029 if (expdif < 53) {
3030 dblq = fpsrcop / fptemp;
3031 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3032 ST0 = fpsrcop - fptemp*dblq;
3033 q = (int)dblq; /* cutting off top bits is assumed here */
3034 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3035 /* (C0,C1,C3) <-- (q2,q1,q0) */
3036 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
3037 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
3038 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
3039 } else {
3040 env->fpus |= 0x400; /* C2 <-- 1 */
3041 fptemp = pow(2.0, expdif-50);
3042 fpsrcop = (ST0 / ST1) / fptemp;
3043 /* fpsrcop = integer obtained by rounding to the nearest */
3044 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3045 floor(fpsrcop): ceil(fpsrcop);
3046 ST0 -= (ST1 * fpsrcop * fptemp);
3047 }
3048}
3049
3050void helper_fprem(void)
3051{
3052 CPU86_LDouble dblq, fpsrcop, fptemp;
3053 CPU86_LDoubleU fpsrcop1, fptemp1;
3054 int expdif;
3055 int q;
3056
3057 fpsrcop = ST0;
3058 fptemp = ST1;
3059 fpsrcop1.d = fpsrcop;
3060 fptemp1.d = fptemp;
3061 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3062 if ( expdif < 53 ) {
3063 dblq = fpsrcop / fptemp;
3064 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3065 ST0 = fpsrcop - fptemp*dblq;
3066 q = (int)dblq; /* cutting off top bits is assumed here */
3067 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3068 /* (C0,C1,C3) <-- (q2,q1,q0) */
3069 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
3070 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
3071 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
3072 } else {
3073 env->fpus |= 0x400; /* C2 <-- 1 */
3074 fptemp = pow(2.0, expdif-50);
3075 fpsrcop = (ST0 / ST1) / fptemp;
3076 /* fpsrcop = integer obtained by chopping */
3077 fpsrcop = (fpsrcop < 0.0)?
3078 -(floor(fabs(fpsrcop))): floor(fpsrcop);
3079 ST0 -= (ST1 * fpsrcop * fptemp);
3080 }
3081}
3082
3083void helper_fyl2xp1(void)
3084{
3085 CPU86_LDouble fptemp;
3086
3087 fptemp = ST0;
3088 if ((fptemp+1.0)>0.0) {
3089 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3090 ST1 *= fptemp;
3091 fpop();
3092 } else {
3093 env->fpus &= (~0x4700);
3094 env->fpus |= 0x400;
3095 }
3096}
3097
3098void helper_fsqrt(void)
3099{
3100 CPU86_LDouble fptemp;
3101
3102 fptemp = ST0;
3103 if (fptemp<0.0) {
3104 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3105 env->fpus |= 0x400;
3106 }
3107 ST0 = sqrt(fptemp);
3108}
3109
3110void helper_fsincos(void)
3111{
3112 CPU86_LDouble fptemp;
3113
3114 fptemp = ST0;
3115 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3116 env->fpus |= 0x400;
3117 } else {
3118 ST0 = sin(fptemp);
3119 fpush();
3120 ST0 = cos(fptemp);
3121 env->fpus &= (~0x400); /* C2 <-- 0 */
3122 /* the above code is for |arg| < 2**63 only */
3123 }
3124}
3125
3126void helper_frndint(void)
3127{
3128 CPU86_LDouble a;
3129
3130 a = ST0;
3131#ifdef __arm__
3132 switch(env->fpuc & RC_MASK) {
3133 default:
3134 case RC_NEAR:
3135 asm("rndd %0, %1" : "=f" (a) : "f"(a));
3136 break;
3137 case RC_DOWN:
3138 asm("rnddm %0, %1" : "=f" (a) : "f"(a));
3139 break;
3140 case RC_UP:
3141 asm("rnddp %0, %1" : "=f" (a) : "f"(a));
3142 break;
3143 case RC_CHOP:
3144 asm("rnddz %0, %1" : "=f" (a) : "f"(a));
3145 break;
3146 }
3147#else
3148 a = rint(a);
3149#endif
3150 ST0 = a;
3151}
3152
3153void helper_fscale(void)
3154{
3155 CPU86_LDouble fpsrcop, fptemp;
3156
3157 fpsrcop = 2.0;
3158 fptemp = pow(fpsrcop,ST1);
3159 ST0 *= fptemp;
3160}
3161
3162void helper_fsin(void)
3163{
3164 CPU86_LDouble fptemp;
3165
3166 fptemp = ST0;
3167 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3168 env->fpus |= 0x400;
3169 } else {
3170 ST0 = sin(fptemp);
3171 env->fpus &= (~0x400); /* C2 <-- 0 */
3172 /* the above code is for |arg| < 2**53 only */
3173 }
3174}
3175
3176void helper_fcos(void)
3177{
3178 CPU86_LDouble fptemp;
3179
3180 fptemp = ST0;
3181 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3182 env->fpus |= 0x400;
3183 } else {
3184 ST0 = cos(fptemp);
3185 env->fpus &= (~0x400); /* C2 <-- 0 */
3186 /* the above code is for |arg5 < 2**63 only */
3187 }
3188}
3189
3190void helper_fxam_ST0(void)
3191{
3192 CPU86_LDoubleU temp;
3193 int expdif;
3194
3195 temp.d = ST0;
3196
3197 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3198 if (SIGND(temp))
3199 env->fpus |= 0x200; /* C1 <-- 1 */
3200
3201 /* XXX: test fptags too */
3202 expdif = EXPD(temp);
3203 if (expdif == MAXEXPD) {
3204#ifdef USE_X86LDOUBLE
3205 if (MANTD(temp) == 0x8000000000000000ULL)
3206#else
3207 if (MANTD(temp) == 0)
3208#endif
3209 env->fpus |= 0x500 /*Infinity*/;
3210 else
3211 env->fpus |= 0x100 /*NaN*/;
3212 } else if (expdif == 0) {
3213 if (MANTD(temp) == 0)
3214 env->fpus |= 0x4000 /*Zero*/;
3215 else
3216 env->fpus |= 0x4400 /*Denormal*/;
3217 } else {
3218 env->fpus |= 0x400;
3219 }
3220}
3221
3222void helper_fstenv(target_ulong ptr, int data32)
3223{
3224 int fpus, fptag, exp, i;
3225 uint64_t mant;
3226 CPU86_LDoubleU tmp;
3227
3228 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3229 fptag = 0;
3230 for (i=7; i>=0; i--) {
3231 fptag <<= 2;
3232 if (env->fptags[i]) {
3233 fptag |= 3;
3234 } else {
3235 tmp.d = env->fpregs[i].d;
3236 exp = EXPD(tmp);
3237 mant = MANTD(tmp);
3238 if (exp == 0 && mant == 0) {
3239 /* zero */
3240 fptag |= 1;
3241 } else if (exp == 0 || exp == MAXEXPD
3242#ifdef USE_X86LDOUBLE
3243 || (mant & (1LL << 63)) == 0
3244#endif
3245 ) {
3246 /* NaNs, infinity, denormal */
3247 fptag |= 2;
3248 }
3249 }
3250 }
3251 if (data32) {
3252 /* 32 bit */
3253 stl(ptr, env->fpuc);
3254 stl(ptr + 4, fpus);
3255 stl(ptr + 8, fptag);
3256 stl(ptr + 12, 0); /* fpip */
3257 stl(ptr + 16, 0); /* fpcs */
3258 stl(ptr + 20, 0); /* fpoo */
3259 stl(ptr + 24, 0); /* fpos */
3260 } else {
3261 /* 16 bit */
3262 stw(ptr, env->fpuc);
3263 stw(ptr + 2, fpus);
3264 stw(ptr + 4, fptag);
3265 stw(ptr + 6, 0);
3266 stw(ptr + 8, 0);
3267 stw(ptr + 10, 0);
3268 stw(ptr + 12, 0);
3269 }
3270}
3271
3272void helper_fldenv(target_ulong ptr, int data32)
3273{
3274 int i, fpus, fptag;
3275
3276 if (data32) {
3277 env->fpuc = lduw(ptr);
3278 fpus = lduw(ptr + 4);
3279 fptag = lduw(ptr + 8);
3280 }
3281 else {
3282 env->fpuc = lduw(ptr);
3283 fpus = lduw(ptr + 2);
3284 fptag = lduw(ptr + 4);
3285 }
3286 env->fpstt = (fpus >> 11) & 7;
3287 env->fpus = fpus & ~0x3800;
3288 for(i = 0;i < 8; i++) {
3289 env->fptags[i] = ((fptag & 3) == 3);
3290 fptag >>= 2;
3291 }
3292}
3293
3294void helper_fsave(target_ulong ptr, int data32)
3295{
3296 CPU86_LDouble tmp;
3297 int i;
3298
3299 helper_fstenv(ptr, data32);
3300
3301 ptr += (14 << data32);
3302 for(i = 0;i < 8; i++) {
3303 tmp = ST(i);
3304 helper_fstt(tmp, ptr);
3305 ptr += 10;
3306 }
3307
3308 /* fninit */
3309 env->fpus = 0;
3310 env->fpstt = 0;
3311 env->fpuc = 0x37f;
3312 env->fptags[0] = 1;
3313 env->fptags[1] = 1;
3314 env->fptags[2] = 1;
3315 env->fptags[3] = 1;
3316 env->fptags[4] = 1;
3317 env->fptags[5] = 1;
3318 env->fptags[6] = 1;
3319 env->fptags[7] = 1;
3320}
3321
3322void helper_frstor(target_ulong ptr, int data32)
3323{
3324 CPU86_LDouble tmp;
3325 int i;
3326
3327 helper_fldenv(ptr, data32);
3328 ptr += (14 << data32);
3329
3330 for(i = 0;i < 8; i++) {
3331 tmp = helper_fldt(ptr);
3332 ST(i) = tmp;
3333 ptr += 10;
3334 }
3335}
3336
3337void helper_fxsave(target_ulong ptr, int data64)
3338{
3339 int fpus, fptag, i, nb_xmm_regs;
3340 CPU86_LDouble tmp;
3341 target_ulong addr;
3342
3343 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3344 fptag = 0;
3345 for(i = 0; i < 8; i++) {
3346 fptag |= (env->fptags[i] << i);
3347 }
3348 stw(ptr, env->fpuc);
3349 stw(ptr + 2, fpus);
3350 stw(ptr + 4, fptag ^ 0xff);
3351
3352 addr = ptr + 0x20;
3353 for(i = 0;i < 8; i++) {
3354 tmp = ST(i);
3355 helper_fstt(tmp, addr);
3356 addr += 16;
3357 }
3358
3359 if (env->cr[4] & CR4_OSFXSR_MASK) {
3360 /* XXX: finish it */
3361 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3362 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3363 nb_xmm_regs = 8 << data64;
3364 addr = ptr + 0xa0;
3365 for(i = 0; i < nb_xmm_regs; i++) {
3366 stq(addr, env->xmm_regs[i].XMM_Q(0));
3367 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3368 addr += 16;
3369 }
3370 }
3371}
3372
3373void helper_fxrstor(target_ulong ptr, int data64)
3374{
3375 int i, fpus, fptag, nb_xmm_regs;
3376 CPU86_LDouble tmp;
3377 target_ulong addr;
3378
3379 env->fpuc = lduw(ptr);
3380 fpus = lduw(ptr + 2);
3381 fptag = lduw(ptr + 4);
3382 env->fpstt = (fpus >> 11) & 7;
3383 env->fpus = fpus & ~0x3800;
3384 fptag ^= 0xff;
3385 for(i = 0;i < 8; i++) {
3386 env->fptags[i] = ((fptag >> i) & 1);
3387 }
3388
3389 addr = ptr + 0x20;
3390 for(i = 0;i < 8; i++) {
3391 tmp = helper_fldt(addr);
3392 ST(i) = tmp;
3393 addr += 16;
3394 }
3395
3396 if (env->cr[4] & CR4_OSFXSR_MASK) {
3397 /* XXX: finish it, endianness */
3398 env->mxcsr = ldl(ptr + 0x18);
3399 //ldl(ptr + 0x1c);
3400 nb_xmm_regs = 8 << data64;
3401 addr = ptr + 0xa0;
3402 for(i = 0; i < nb_xmm_regs; i++) {
3403#if !defined(VBOX) || __GNUC__ < 4
3404 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3405 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3406#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3407# if 1
3408 env->xmm_regs[i].XMM_L(0) = ldl(addr);
3409 env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3410 env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3411 env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3412# else
3413 /* this works fine on Mac OS X, gcc 4.0.1 */
3414 uint64_t u64 = ldq(addr);
3415 env->xmm_regs[i].XMM_Q(0);
3416 u64 = ldq(addr + 4);
3417 env->xmm_regs[i].XMM_Q(1) = u64;
3418# endif
3419#endif
3420 addr += 16;
3421 }
3422 }
3423}
3424
3425#ifndef USE_X86LDOUBLE
3426
3427void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3428{
3429 CPU86_LDoubleU temp;
3430 int e;
3431
3432 temp.d = f;
3433 /* mantissa */
3434 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3435 /* exponent + sign */
3436 e = EXPD(temp) - EXPBIAS + 16383;
3437 e |= SIGND(temp) >> 16;
3438 *pexp = e;
3439}
3440
3441CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3442{
3443 CPU86_LDoubleU temp;
3444 int e;
3445 uint64_t ll;
3446
3447 /* XXX: handle overflow ? */
3448 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3449 e |= (upper >> 4) & 0x800; /* sign */
3450 ll = (mant >> 11) & ((1LL << 52) - 1);
3451#ifdef __arm__
3452 temp.l.upper = (e << 20) | (ll >> 32);
3453 temp.l.lower = ll;
3454#else
3455 temp.ll = ll | ((uint64_t)e << 52);
3456#endif
3457 return temp.d;
3458}
3459
3460#else
3461
3462void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3463{
3464 CPU86_LDoubleU temp;
3465
3466 temp.d = f;
3467 *pmant = temp.l.lower;
3468 *pexp = temp.l.upper;
3469}
3470
3471CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3472{
3473 CPU86_LDoubleU temp;
3474
3475 temp.l.upper = upper;
3476 temp.l.lower = mant;
3477 return temp.d;
3478}
3479#endif
3480
3481#ifdef TARGET_X86_64
3482
3483//#define DEBUG_MULDIV
3484
3485static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3486{
3487 *plow += a;
3488 /* carry test */
3489 if (*plow < a)
3490 (*phigh)++;
3491 *phigh += b;
3492}
3493
3494static void neg128(uint64_t *plow, uint64_t *phigh)
3495{
3496 *plow = ~ *plow;
3497 *phigh = ~ *phigh;
3498 add128(plow, phigh, 1, 0);
3499}
3500
3501static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3502{
3503 uint32_t a0, a1, b0, b1;
3504 uint64_t v;
3505
3506 a0 = a;
3507 a1 = a >> 32;
3508
3509 b0 = b;
3510 b1 = b >> 32;
3511
3512 v = (uint64_t)a0 * (uint64_t)b0;
3513 *plow = v;
3514 *phigh = 0;
3515
3516 v = (uint64_t)a0 * (uint64_t)b1;
3517 add128(plow, phigh, v << 32, v >> 32);
3518
3519 v = (uint64_t)a1 * (uint64_t)b0;
3520 add128(plow, phigh, v << 32, v >> 32);
3521
3522 v = (uint64_t)a1 * (uint64_t)b1;
3523 *phigh += v;
3524#ifdef DEBUG_MULDIV
3525 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
3526 a, b, *phigh, *plow);
3527#endif
3528}
3529
3530static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3531{
3532 int sa, sb;
3533 sa = (a < 0);
3534 if (sa)
3535 a = -a;
3536 sb = (b < 0);
3537 if (sb)
3538 b = -b;
3539 mul64(plow, phigh, a, b);
3540 if (sa ^ sb) {
3541 neg128(plow, phigh);
3542 }
3543}
3544
3545/* return TRUE if overflow */
3546static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3547{
3548 uint64_t q, r, a1, a0;
3549 int i, qb, ab;
3550
3551 a0 = *plow;
3552 a1 = *phigh;
3553 if (a1 == 0) {
3554 q = a0 / b;
3555 r = a0 % b;
3556 *plow = q;
3557 *phigh = r;
3558 } else {
3559 if (a1 >= b)
3560 return 1;
3561 /* XXX: use a better algorithm */
3562 for(i = 0; i < 64; i++) {
3563 ab = a1 >> 63;
3564 a1 = (a1 << 1) | (a0 >> 63);
3565 if (ab || a1 >= b) {
3566 a1 -= b;
3567 qb = 1;
3568 } else {
3569 qb = 0;
3570 }
3571 a0 = (a0 << 1) | qb;
3572 }
3573#if defined(DEBUG_MULDIV)
3574 printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n",
3575 *phigh, *plow, b, a0, a1);
3576#endif
3577 *plow = a0;
3578 *phigh = a1;
3579 }
3580 return 0;
3581}
3582
3583/* return TRUE if overflow */
3584static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
3585{
3586 int sa, sb;
3587 sa = ((int64_t)*phigh < 0);
3588 if (sa)
3589 neg128(plow, phigh);
3590 sb = (b < 0);
3591 if (sb)
3592 b = -b;
3593 if (div64(plow, phigh, b) != 0)
3594 return 1;
3595 if (sa ^ sb) {
3596 if (*plow > (1ULL << 63))
3597 return 1;
3598 *plow = - *plow;
3599 } else {
3600 if (*plow >= (1ULL << 63))
3601 return 1;
3602 }
3603 if (sa)
3604 *phigh = - *phigh;
3605 return 0;
3606}
3607
3608void helper_mulq_EAX_T0(void)
3609{
3610 uint64_t r0, r1;
3611
3612 mul64(&r0, &r1, EAX, T0);
3613 EAX = r0;
3614 EDX = r1;
3615 CC_DST = r0;
3616 CC_SRC = r1;
3617}
3618
3619void helper_imulq_EAX_T0(void)
3620{
3621 uint64_t r0, r1;
3622
3623 imul64(&r0, &r1, EAX, T0);
3624 EAX = r0;
3625 EDX = r1;
3626 CC_DST = r0;
3627 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3628}
3629
3630void helper_imulq_T0_T1(void)
3631{
3632 uint64_t r0, r1;
3633
3634 imul64(&r0, &r1, T0, T1);
3635 T0 = r0;
3636 CC_DST = r0;
3637 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3638}
3639
3640void helper_divq_EAX_T0(void)
3641{
3642 uint64_t r0, r1;
3643 if (T0 == 0) {
3644 raise_exception(EXCP00_DIVZ);
3645 }
3646 r0 = EAX;
3647 r1 = EDX;
3648 if (div64(&r0, &r1, T0))
3649 raise_exception(EXCP00_DIVZ);
3650 EAX = r0;
3651 EDX = r1;
3652}
3653
3654void helper_idivq_EAX_T0(void)
3655{
3656 uint64_t r0, r1;
3657 if (T0 == 0) {
3658 raise_exception(EXCP00_DIVZ);
3659 }
3660 r0 = EAX;
3661 r1 = EDX;
3662 if (idiv64(&r0, &r1, T0))
3663 raise_exception(EXCP00_DIVZ);
3664 EAX = r0;
3665 EDX = r1;
3666}
3667
3668#endif
3669
3670/* XXX: do it */
3671int fpu_isnan(double a)
3672{
3673 return 0;
3674}
3675
3676void helper_hlt(void)
3677{
3678 env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
3679 env->exception_index = EXCP_HLT;
3680 cpu_loop_exit();
3681}
3682
3683void helper_monitor(void)
3684{
3685 if (ECX != 0)
3686 raise_exception(EXCP0D_GPF);
3687 /* XXX: store address ? */
3688}
3689
3690void helper_mwait(void)
3691{
3692 if (ECX != 0)
3693 raise_exception(EXCP0D_GPF);
3694#ifdef VBOX
3695 helper_hlt();
3696#else
3697 /* XXX: not complete but not completely erroneous */
3698 if (env->cpu_index != 0 || env->next_cpu != NULL) {
3699 /* more than one CPU: do not sleep because another CPU may
3700 wake this one */
3701 } else {
3702 helper_hlt();
3703 }
3704#endif
3705}
3706
3707float approx_rsqrt(float a)
3708{
3709 return 1.0 / sqrt(a);
3710}
3711
3712float approx_rcp(float a)
3713{
3714 return 1.0 / a;
3715}
3716
3717/* XXX: find a better solution */
3718double helper_sqrt(double a)
3719{
3720 return sqrt(a);
3721}
3722
3723#if !defined(CONFIG_USER_ONLY)
3724
3725#define MMUSUFFIX _mmu
3726#define GETPC() (__builtin_return_address(0))
3727
3728#define SHIFT 0
3729#include "softmmu_template.h"
3730
3731#define SHIFT 1
3732#include "softmmu_template.h"
3733
3734#define SHIFT 2
3735#include "softmmu_template.h"
3736
3737#define SHIFT 3
3738#include "softmmu_template.h"
3739
3740#endif
3741
3742/* try to fill the TLB and return an exception if error. If retaddr is
3743 NULL, it means that the function was called in C code (i.e. not
3744 from generated code or from helper.c) */
3745/* XXX: fix it to restore all registers */
3746void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
3747{
3748 TranslationBlock *tb;
3749 int ret;
3750 unsigned long pc;
3751 CPUX86State *saved_env;
3752
3753 /* XXX: hack to restore env in all cases, even if not called from
3754 generated code */
3755 saved_env = env;
3756 env = cpu_single_env;
3757
3758 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
3759 if (ret) {
3760 if (retaddr) {
3761 /* now we have a real cpu fault */
3762 pc = (unsigned long)retaddr;
3763 tb = tb_find_pc(pc);
3764 if (tb) {
3765 /* the PC is inside the translated code. It means that we have
3766 a virtual CPU fault */
3767 cpu_restore_state(tb, env, pc, NULL);
3768 }
3769 }
3770 if (retaddr)
3771 raise_exception_err(EXCP0E_PAGE, env->error_code);
3772 else {
3773 raise_exception_err_norestore(EXCP0E_PAGE, env->error_code);
3774 }
3775 }
3776 env = saved_env;
3777}
3778
3779#if defined(VBOX)
3780
3781/**
3782 * Correctly computes the eflags.
3783 * @returns eflags.
3784 * @param env1 CPU environment.
3785 */
3786uint32_t raw_compute_eflags(CPUX86State *env1)
3787{
3788 CPUX86State *savedenv = env;
3789 env = env1;
3790 uint32_t efl = compute_eflags();
3791 env = savedenv;
3792 return efl;
3793}
3794
3795/**
3796 * Reads byte from virtual address in guest memory area.
3797 * XXX: is it working for any addresses? swapped out pages?
3798 * @returns readed data byte.
3799 * @param env1 CPU environment.
3800 * @param pvAddr GC Virtual address.
3801 */
3802uint8_t read_byte(CPUX86State *env1, target_ulong addr)
3803{
3804 CPUX86State *savedenv = env;
3805 env = env1;
3806 uint8_t u8 = ldub_kernel(addr);
3807 env = savedenv;
3808 return u8;
3809}
3810
3811/**
3812 * Reads byte from virtual address in guest memory area.
3813 * XXX: is it working for any addresses? swapped out pages?
3814 * @returns readed data byte.
3815 * @param env1 CPU environment.
3816 * @param pvAddr GC Virtual address.
3817 */
3818uint16_t read_word(CPUX86State *env1, target_ulong addr)
3819{
3820 CPUX86State *savedenv = env;
3821 env = env1;
3822 uint16_t u16 = lduw_kernel(addr);
3823 env = savedenv;
3824 return u16;
3825}
3826
3827/**
3828 * Reads byte from virtual address in guest memory area.
3829 * XXX: is it working for any addresses? swapped out pages?
3830 * @returns readed data byte.
3831 * @param env1 CPU environment.
3832 * @param pvAddr GC Virtual address.
3833 */
3834uint32_t read_dword(CPUX86State *env1, target_ulong addr)
3835{
3836 CPUX86State *savedenv = env;
3837 env = env1;
3838 uint32_t u32 = ldl_kernel(addr);
3839 env = savedenv;
3840 return u32;
3841}
3842
3843/**
3844 * Writes byte to virtual address in guest memory area.
3845 * XXX: is it working for any addresses? swapped out pages?
3846 * @returns readed data byte.
3847 * @param env1 CPU environment.
3848 * @param pvAddr GC Virtual address.
3849 * @param val byte value
3850 */
3851void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
3852{
3853 CPUX86State *savedenv = env;
3854 env = env1;
3855 stb(addr, val);
3856 env = savedenv;
3857}
3858
3859void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
3860{
3861 CPUX86State *savedenv = env;
3862 env = env1;
3863 stw(addr, val);
3864 env = savedenv;
3865}
3866
3867void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
3868{
3869 CPUX86State *savedenv = env;
3870 env = env1;
3871 stl(addr, val);
3872 env = savedenv;
3873}
3874
3875/**
3876 * Correctly loads selector into segment register with updating internal
3877 * qemu data/caches.
3878 * @param env1 CPU environment.
3879 * @param seg_reg Segment register.
3880 * @param selector Selector to load.
3881 */
3882void sync_seg(CPUX86State *env1, int seg_reg, int selector)
3883{
3884 CPUX86State *savedenv = env;
3885 env = env1;
3886
3887 if (env->eflags & X86_EFL_VM)
3888 {
3889 load_seg_vm(seg_reg, selector);
3890
3891 env = savedenv;
3892
3893 /* Successful sync. */
3894 env1->segs[seg_reg].newselector = 0;
3895 }
3896 else
3897 {
3898 if (setjmp(env1->jmp_env) == 0)
3899 {
3900 if (seg_reg == R_CS)
3901 {
3902 uint32_t e1, e2;
3903 load_segment(&e1, &e2, selector);
3904 cpu_x86_load_seg_cache(env, R_CS, selector,
3905 get_seg_base(e1, e2),
3906 get_seg_limit(e1, e2),
3907 e2);
3908 }
3909 else
3910 load_seg(seg_reg, selector);
3911 env = savedenv;
3912
3913 /* Successful sync. */
3914 env1->segs[seg_reg].newselector = 0;
3915 }
3916 else
3917 {
3918 env = savedenv;
3919
3920 /* Postpone sync until the guest uses the selector. */
3921 env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
3922 env1->segs[seg_reg].newselector = selector;
3923 Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
3924 }
3925 }
3926
3927}
3928
3929
3930/**
3931 * Correctly loads a new ldtr selector.
3932 *
3933 * @param env1 CPU environment.
3934 * @param selector Selector to load.
3935 */
3936void sync_ldtr(CPUX86State *env1, int selector)
3937{
3938 CPUX86State *saved_env = env;
3939 target_ulong saved_T0 = T0;
3940 if (setjmp(env1->jmp_env) == 0)
3941 {
3942 env = env1;
3943 T0 = selector;
3944 helper_lldt_T0();
3945 T0 = saved_T0;
3946 env = saved_env;
3947 }
3948 else
3949 {
3950 T0 = saved_T0;
3951 env = saved_env;
3952#ifdef VBOX_STRICT
3953 cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
3954#endif
3955 }
3956}
3957
3958/**
3959 * Correctly loads a new tr selector.
3960 *
3961 * @param env1 CPU environment.
3962 * @param selector Selector to load.
3963 */
3964int sync_tr(CPUX86State *env1, int selector)
3965{
3966 /* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
3967 SegmentCache *dt;
3968 uint32_t e1, e2;
3969 int index, type, entry_limit;
3970 target_ulong ptr;
3971 CPUX86State *saved_env = env;
3972 env = env1;
3973
3974 selector &= 0xffff;
3975 if ((selector & 0xfffc) == 0) {
3976 /* NULL selector case: invalid TR */
3977 env->tr.base = 0;
3978 env->tr.limit = 0;
3979 env->tr.flags = 0;
3980 } else {
3981 if (selector & 0x4)
3982 goto l_failure;
3983 dt = &env->gdt;
3984 index = selector & ~7;
3985#ifdef TARGET_X86_64
3986 if (env->hflags & HF_LMA_MASK)
3987 entry_limit = 15;
3988 else
3989#endif
3990 entry_limit = 7;
3991 if ((index + entry_limit) > dt->limit)
3992 goto l_failure;
3993 ptr = dt->base + index;
3994 e1 = ldl_kernel(ptr);
3995 e2 = ldl_kernel(ptr + 4);
3996 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3997 if ((e2 & DESC_S_MASK) /*||
3998 (type != 1 && type != 9)*/)
3999 goto l_failure;
4000 if (!(e2 & DESC_P_MASK))
4001 goto l_failure;
4002#ifdef TARGET_X86_64
4003 if (env->hflags & HF_LMA_MASK) {
4004 uint32_t e3;
4005 e3 = ldl_kernel(ptr + 8);
4006 load_seg_cache_raw_dt(&env->tr, e1, e2);
4007 env->tr.base |= (target_ulong)e3 << 32;
4008 } else
4009#endif
4010 {
4011 load_seg_cache_raw_dt(&env->tr, e1, e2);
4012 }
4013 e2 |= DESC_TSS_BUSY_MASK;
4014 stl_kernel(ptr + 4, e2);
4015 }
4016 env->tr.selector = selector;
4017
4018 env = saved_env;
4019 return 0;
4020l_failure:
4021 AssertMsgFailed(("selector=%d\n", selector));
4022 return -1;
4023}
4024
4025int emulate_single_instr(CPUX86State *env1)
4026{
4027 TranslationBlock *current;
4028 TranslationBlock tb_temp;
4029 int csize;
4030 void (*gen_func)(void);
4031 uint8_t *pvCode;
4032 uint32_t old_eip;
4033
4034 /* ensures env is loaded in ebp! */
4035 CPUX86State *savedenv = env;
4036 env = env1;
4037
4038 RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
4039
4040 pvCode = env->pvCodeBuffer;
4041
4042 // Setup temporary translation block
4043 tb_temp.hash_next = 0;
4044 tb_temp.jmp_first = 0;
4045 tb_temp.jmp_next[0] = 0;
4046 tb_temp.jmp_next[1] = 0;
4047 tb_temp.page_addr[0] = 0;
4048 tb_temp.page_addr[1] = 0;
4049 tb_temp.page_next[0] = 0;
4050 tb_temp.page_next[1] = 0;
4051 tb_temp.hash_next = 0;
4052
4053 tb_temp.tb_next_offset[0] = 0xffff;
4054 tb_temp.tb_next_offset[1] = 0xffff;
4055
4056 tb_temp.cs_base = (unsigned long)env->segs[R_CS].base;
4057 tb_temp.pc = tb_temp.cs_base + env->eip;
4058 tb_temp.cflags = 0;
4059 tb_temp.flags = env->hflags;
4060 tb_temp.flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
4061 tb_temp.tc_ptr = pvCode;
4062
4063 current = env->current_tb;
4064 env->current_tb = NULL;
4065
4066 // Translate only one instruction
4067 ASMAtomicOrS32(&env->state, CPU_EMULATE_SINGLE_INSTR);
4068 if (cpu_gen_code(env, &tb_temp, env->cbCodeBuffer, &csize) < 0)
4069 {
4070 AssertFailed();
4071 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4072 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4073 env = savedenv;
4074 return -1;
4075 }
4076#ifdef DEBUG
4077 if(csize > env->cbCodeBuffer)
4078 {
4079 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4080 AssertFailed();
4081 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4082 env = savedenv;
4083 return -1;
4084 }
4085 if (tb_temp.tc_ptr != pvCode)
4086 {
4087 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4088 AssertFailed();
4089 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4090 env = savedenv;
4091 return -1;
4092 }
4093#endif
4094 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4095
4096 tb_link(&tb_temp);
4097
4098 old_eip = env->eip;
4099 // Execute it using emulation
4100 gen_func = (void *)tb_temp.tc_ptr;
4101 env->current_tb = &tb_temp;
4102
4103 // eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
4104 // perhaps not a very safe hack
4105 while(old_eip == env->eip)
4106 {
4107 gen_func();
4108 /*
4109 * Exit once we detect an external interrupt and interrupts are enabled
4110 */
4111 if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT|CPU_INTERRUPT_EXTERNAL_TIMER)) ||
4112 ( (env->eflags & IF_MASK) &&
4113 !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
4114 (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
4115 {
4116 break;
4117 }
4118 }
4119 env->current_tb = current;
4120
4121 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4122
4123 if (env->hflags & HF_INHIBIT_IRQ_MASK)
4124 {
4125 Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK)\n"));
4126 env->hflags &= ~HF_INHIBIT_IRQ_MASK;
4127 emulate_single_instr(env);
4128 }
4129
4130 env = savedenv;
4131 return 0;
4132}
4133
4134int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr,
4135 uint32_t *esp_ptr, int dpl)
4136{
4137 int type, index, shift;
4138
4139 CPUX86State *savedenv = env;
4140 env = env1;
4141
4142 if (!(env->tr.flags & DESC_P_MASK))
4143 cpu_abort(env, "invalid tss");
4144 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
4145 if ((type & 7) != 1)
4146 cpu_abort(env, "invalid tss type %d", type);
4147 shift = type >> 3;
4148 index = (dpl * 4 + 2) << shift;
4149 if (index + (4 << shift) - 1 > env->tr.limit)
4150 {
4151 env = savedenv;
4152 return 0;
4153 }
4154 //raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
4155
4156 if (shift == 0) {
4157 *esp_ptr = lduw_kernel(env->tr.base + index);
4158 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
4159 } else {
4160 *esp_ptr = ldl_kernel(env->tr.base + index);
4161 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
4162 }
4163
4164 env = savedenv;
4165 return 1;
4166}
4167
4168//*****************************************************************************
4169// Needs to be at the bottom of the file (overriding macros)
4170
4171static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4172{
4173 return *(CPU86_LDouble *)ptr;
4174}
4175
4176static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4177{
4178 *(CPU86_LDouble *)ptr = f;
4179}
4180
4181#undef stw
4182#undef stl
4183#undef stq
4184#define stw(a,b) *(uint16_t *)(a) = (uint16_t)(b)
4185#define stl(a,b) *(uint32_t *)(a) = (uint32_t)(b)
4186#define stq(a,b) *(uint64_t *)(a) = (uint64_t)(b)
4187#define data64 0
4188
4189//*****************************************************************************
4190void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr)
4191{
4192 int fpus, fptag, i, nb_xmm_regs;
4193 CPU86_LDouble tmp;
4194 uint8_t *addr;
4195
4196 if (env->cpuid_features & CPUID_FXSR)
4197 {
4198 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
4199 fptag = 0;
4200 for(i = 0; i < 8; i++) {
4201 fptag |= (env->fptags[i] << i);
4202 }
4203 stw(ptr, env->fpuc);
4204 stw(ptr + 2, fpus);
4205 stw(ptr + 4, fptag ^ 0xff);
4206
4207 addr = ptr + 0x20;
4208 for(i = 0;i < 8; i++) {
4209 tmp = ST(i);
4210 helper_fstt_raw(tmp, addr);
4211 addr += 16;
4212 }
4213
4214 if (env->cr[4] & CR4_OSFXSR_MASK) {
4215 /* XXX: finish it */
4216 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4217 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4218 nb_xmm_regs = 8 << data64;
4219 addr = ptr + 0xa0;
4220 for(i = 0; i < nb_xmm_regs; i++) {
4221#if __GNUC__ < 4
4222 stq(addr, env->xmm_regs[i].XMM_Q(0));
4223 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4224#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4225 stl(addr, env->xmm_regs[i].XMM_L(0));
4226 stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4227 stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4228 stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4229#endif
4230 addr += 16;
4231 }
4232 }
4233 }
4234 else
4235 {
4236 PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4237 int fptag;
4238
4239 fp->FCW = env->fpuc;
4240 fp->FSW = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
4241 fptag = 0;
4242 for (i=7; i>=0; i--) {
4243 fptag <<= 2;
4244 if (env->fptags[i]) {
4245 fptag |= 3;
4246 } else {
4247 /* the FPU automatically computes it */
4248 }
4249 }
4250 fp->FTW = fptag;
4251
4252 for(i = 0;i < 8; i++) {
4253 tmp = ST(i);
4254 helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4255 }
4256 }
4257}
4258
4259//*****************************************************************************
4260#undef lduw
4261#undef ldl
4262#undef ldq
4263#define lduw(a) *(uint16_t *)(a)
4264#define ldl(a) *(uint32_t *)(a)
4265#define ldq(a) *(uint64_t *)(a)
4266//*****************************************************************************
4267void save_raw_fp_state(CPUX86State *env, uint8_t *ptr)
4268{
4269 int i, fpus, fptag, nb_xmm_regs;
4270 CPU86_LDouble tmp;
4271 uint8_t *addr;
4272
4273 if (env->cpuid_features & CPUID_FXSR)
4274 {
4275 env->fpuc = lduw(ptr);
4276 fpus = lduw(ptr + 2);
4277 fptag = lduw(ptr + 4);
4278 env->fpstt = (fpus >> 11) & 7;
4279 env->fpus = fpus & ~0x3800;
4280 fptag ^= 0xff;
4281 for(i = 0;i < 8; i++) {
4282 env->fptags[i] = ((fptag >> i) & 1);
4283 }
4284
4285 addr = ptr + 0x20;
4286 for(i = 0;i < 8; i++) {
4287 tmp = helper_fldt_raw(addr);
4288 ST(i) = tmp;
4289 addr += 16;
4290 }
4291
4292 if (env->cr[4] & CR4_OSFXSR_MASK) {
4293 /* XXX: finish it, endianness */
4294 env->mxcsr = ldl(ptr + 0x18);
4295 //ldl(ptr + 0x1c);
4296 nb_xmm_regs = 8 << data64;
4297 addr = ptr + 0xa0;
4298 for(i = 0; i < nb_xmm_regs; i++) {
4299 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4300 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4301 addr += 16;
4302 }
4303 }
4304 }
4305 else
4306 {
4307 PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4308 int fptag, j;
4309
4310 env->fpuc = fp->FCW;
4311 env->fpstt = (fp->FSW >> 11) & 7;
4312 env->fpus = fp->FSW & ~0x3800;
4313 fptag = fp->FTW;
4314 for(i = 0;i < 8; i++) {
4315 env->fptags[i] = ((fptag & 3) == 3);
4316 fptag >>= 2;
4317 }
4318 j = env->fpstt;
4319 for(i = 0;i < 8; i++) {
4320 tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4321 ST(i) = tmp;
4322 }
4323 }
4324}
4325//*****************************************************************************
4326//*****************************************************************************
4327
4328#endif /* VBOX */
4329
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