tcg-target.c@ 33540

Last change on this file since 33540 was 33540, checked in by vboxsync, 14 years ago
*: spelling fixes, thanks Timeless!
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1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24
25	#ifndef NDEBUG
26	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27	"%eax",
28	"%ecx",
29	"%edx",
30	"%ebx",
31	"%esp",
32	"%ebp",
33	"%esi",
34	"%edi",
35	};
36	#endif
37
38	static const int tcg_target_reg_alloc_order[] = {
39	TCG_REG_EAX,
40	TCG_REG_EDX,
41	TCG_REG_ECX,
42	TCG_REG_EBX,
43	TCG_REG_ESI,
44	TCG_REG_EDI,
45	TCG_REG_EBP,
46	};
47
48	static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
49	static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
50
51	static uint8_t *tb_ret_addr;
52
53	static void patch_reloc(uint8_t *code_ptr, int type,
54	tcg_target_long value, tcg_target_long addend)
55	{
56	value += addend;
57	switch(type) {
58	case R_386_32:
59	(uint32_t )code_ptr = value;
60	break;
61	case R_386_PC32:
62	(uint32_t )code_ptr = value - (long)code_ptr;
63	break;
64	default:
65	tcg_abort();
66	}
67	}
68
69	#ifdef VBOX
70	/* emits stack alignment checks for strict builds. */
71	DECLINLINE(void) tcg_gen_stack_alignment_check(TCGContext *s)
72	{
73	# if defined(RT_STRICT) && defined(RT_OS_DARWIN) /** @todo all OSes? */
74	tcg_out8(s, 0xf7); tcg_out8(s, 0xc4); /* test %esp, 1fh */
75	tcg_out32(s, TCG_TARGET_STACK_ALIGN - 1);
76	tcg_out8(s, 0x74); /* jz imm8 */
77	tcg_out8(s, 1); /* $+3 (over int3) */
78	tcg_out8(s, 0xcc); /* int3 */
79	# else
80	NOREF(s);
81	# endif
82	}
83	#endif /* VBOX */
84
85	/* maximum number of register used for input function arguments */
86	#ifndef VBOX
87	static inline int tcg_target_get_call_iarg_regs_count(int flags)
88	#else /* VBOX */
89	DECLINLINE(int) tcg_target_get_call_iarg_regs_count(int flags)
90	#endif /* VBOX */
91	{
92	flags &= TCG_CALL_TYPE_MASK;
93	switch(flags) {
94	case TCG_CALL_TYPE_STD:
95	return 0;
96	case TCG_CALL_TYPE_REGPARM_1:
97	case TCG_CALL_TYPE_REGPARM_2:
98	case TCG_CALL_TYPE_REGPARM:
99	return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
100	default:
101	tcg_abort();
102	}
103	}
104
105	/* parse target specific constraints */
106	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
107	{
108	const char *ct_str;
109
110	ct_str = *pct_str;
111	switch(ct_str[0]) {
112	case 'a':
113	ct->ct \|= TCG_CT_REG;
114	tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
115	break;
116	case 'b':
117	ct->ct \|= TCG_CT_REG;
118	tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
119	break;
120	case 'c':
121	ct->ct \|= TCG_CT_REG;
122	tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
123	break;
124	case 'd':
125	ct->ct \|= TCG_CT_REG;
126	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
127	break;
128	case 'S':
129	ct->ct \|= TCG_CT_REG;
130	tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
131	break;
132	case 'D':
133	ct->ct \|= TCG_CT_REG;
134	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
135	break;
136	case 'q':
137	ct->ct \|= TCG_CT_REG;
138	tcg_regset_set32(ct->u.regs, 0, 0xf);
139	break;
140	case 'r':
141	ct->ct \|= TCG_CT_REG;
142	tcg_regset_set32(ct->u.regs, 0, 0xff);
143	break;
144
145	/* qemu_ld/st address constraint */
146	case 'L':
147	ct->ct \|= TCG_CT_REG;
148	tcg_regset_set32(ct->u.regs, 0, 0xff);
149	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
150	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
151	break;
152	default:
153	return -1;
154	}
155	ct_str++;
156	*pct_str = ct_str;
157	return 0;
158	}
159
160	/* test if a constant matches the constraint */
161	#ifndef VBOX
162	static inline int tcg_target_const_match(tcg_target_long val,
163	#else /* VBOX */
164	DECLINLINE(int) tcg_target_const_match(tcg_target_long val,
165	#endif /* VBOX */
166	const TCGArgConstraint *arg_ct)
167	{
168	int ct;
169	ct = arg_ct->ct;
170	if (ct & TCG_CT_CONST)
171	return 1;
172	else
173	return 0;
174	}
175
176	#define ARITH_ADD 0
177	#define ARITH_OR 1
178	#define ARITH_ADC 2
179	#define ARITH_SBB 3
180	#define ARITH_AND 4
181	#define ARITH_SUB 5
182	#define ARITH_XOR 6
183	#define ARITH_CMP 7
184
185	#define SHIFT_SHL 4
186	#define SHIFT_SHR 5
187	#define SHIFT_SAR 7
188
189	#define JCC_JMP (-1)
190	#define JCC_JO 0x0
191	#define JCC_JNO 0x1
192	#define JCC_JB 0x2
193	#define JCC_JAE 0x3
194	#define JCC_JE 0x4
195	#define JCC_JNE 0x5
196	#define JCC_JBE 0x6
197	#define JCC_JA 0x7
198	#define JCC_JS 0x8
199	#define JCC_JNS 0x9
200	#define JCC_JP 0xa
201	#define JCC_JNP 0xb
202	#define JCC_JL 0xc
203	#define JCC_JGE 0xd
204	#define JCC_JLE 0xe
205	#define JCC_JG 0xf
206
207	#define P_EXT 0x100 /* 0x0f opcode prefix */
208
209	#if !defined(VBOX) \|\| !defined(_MSC_VER)
210	static const uint8_t tcg_cond_to_jcc[10] = {
211	[TCG_COND_EQ] = JCC_JE,
212	[TCG_COND_NE] = JCC_JNE,
213	[TCG_COND_LT] = JCC_JL,
214	[TCG_COND_GE] = JCC_JGE,
215	[TCG_COND_LE] = JCC_JLE,
216	[TCG_COND_GT] = JCC_JG,
217	[TCG_COND_LTU] = JCC_JB,
218	[TCG_COND_GEU] = JCC_JAE,
219	[TCG_COND_LEU] = JCC_JBE,
220	[TCG_COND_GTU] = JCC_JA,
221	};
222	#else
223	/* Fortunately, ordering is right */
224	static const uint8_t tcg_cond_to_jcc[10] = {
225	JCC_JE,
226	JCC_JNE,
227	JCC_JL,
228	JCC_JGE,
229	JCC_JLE,
230	JCC_JG,
231	JCC_JB,
232	JCC_JAE,
233	JCC_JBE,
234	JCC_JA,
235	};
236	#endif
237
238	#ifndef VBOX
239	static inline void tcg_out_opc(TCGContext *s, int opc)
240	#else /* VBOX */
241	DECLINLINE(void) tcg_out_opc(TCGContext *s, int opc)
242	#endif /* VBOX */
243	{
244	if (opc & P_EXT)
245	tcg_out8(s, 0x0f);
246	tcg_out8(s, opc);
247	}
248
249	#ifndef VBOX
250	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
251	#else /* VBOX */
252	DECLINLINE(void) tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
253	#endif /* VBOX */
254	{
255	tcg_out_opc(s, opc);
256	tcg_out8(s, 0xc0 \| (r << 3) \| rm);
257	}
258
259	/* rm == -1 means no register index */
260	#ifndef VBOX
261	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
262	#else /* VBOX */
263	DECLINLINE(void) tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
264	#endif /* VBOX */
265	int32_t offset)
266	{
267	tcg_out_opc(s, opc);
268	if (rm == -1) {
269	tcg_out8(s, 0x05 \| (r << 3));
270	tcg_out32(s, offset);
271	} else if (offset == 0 && rm != TCG_REG_EBP) {
272	if (rm == TCG_REG_ESP) {
273	tcg_out8(s, 0x04 \| (r << 3));
274	tcg_out8(s, 0x24);
275	} else {
276	tcg_out8(s, 0x00 \| (r << 3) \| rm);
277	}
278	} else if ((int8_t)offset == offset) {
279	if (rm == TCG_REG_ESP) {
280	tcg_out8(s, 0x44 \| (r << 3));
281	tcg_out8(s, 0x24);
282	} else {
283	tcg_out8(s, 0x40 \| (r << 3) \| rm);
284	}
285	tcg_out8(s, offset);
286	} else {
287	if (rm == TCG_REG_ESP) {
288	tcg_out8(s, 0x84 \| (r << 3));
289	tcg_out8(s, 0x24);
290	} else {
291	tcg_out8(s, 0x80 \| (r << 3) \| rm);
292	}
293	tcg_out32(s, offset);
294	}
295	}
296
297	#ifndef VBOX
298	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
299	#else /* VBOX */
300	DECLINLINE(void) tcg_out_mov(TCGContext *s, int ret, int arg)
301	#endif /* VBOX */
302	{
303	if (arg != ret)
304	tcg_out_modrm(s, 0x8b, ret, arg);
305	}
306
307	#ifndef VBOX
308	static inline void tcg_out_movi(TCGContext *s, TCGType type,
309	#else /* VBOX */
310	DECLINLINE(void) tcg_out_movi(TCGContext *s, TCGType type,
311	#endif /* VBOX */
312	int ret, int32_t arg)
313	{
314	if (arg == 0) {
315	/* xor r0,r0 */
316	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret);
317	} else {
318	tcg_out8(s, 0xb8 + ret);
319	tcg_out32(s, arg);
320	}
321	}
322
323	#ifndef VBOX
324	static inline void tcg_out_push(TCGContext *s, int reg)
325	#else /* VBOX */
326	DECLINLINE(void) tcg_out_push(TCGContext *s, int reg)
327	#endif /* VBOX */
328	{
329	tcg_out_opc(s, 0x50 + reg);
330	}
331
332	#ifndef VBOX
333	static inline void tcg_out_pop(TCGContext *s, int reg)
334	#else /* VBOX */
335	DECLINLINE(void) tcg_out_pop(TCGContext *s, int reg)
336	#endif /* VBOX */
337	{
338	tcg_out_opc(s, 0x58 + reg);
339	}
340
341	#ifndef VBOX
342	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
343	#else /* VBOX */
344	DECLINLINE(void) tcg_out_ld(TCGContext *s, TCGType type, int ret,
345	#endif /* VBOX */
346	int arg1, tcg_target_long arg2)
347	{
348	/* movl */
349	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
350	}
351
352	#ifndef VBOX
353	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
354	#else /* VBOX */
355	DECLINLINE(void) tcg_out_st(TCGContext *s, TCGType type, int arg,
356	#endif /* VBOX */
357	int arg1, tcg_target_long arg2)
358	{
359	/* movl */
360	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
361	}
362
363	#ifndef VBOX
364	static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
365	#else /* VBOX */
366	DECLINLINE(void) tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
367	#endif /* VBOX */
368	{
369	if (val == (int8_t)val) {
370	tcg_out_modrm(s, 0x83, c, r0);
371	tcg_out8(s, val);
372	} else {
373	tcg_out_modrm(s, 0x81, c, r0);
374	tcg_out32(s, val);
375	}
376	}
377
378	void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
379	{
380	if (val != 0)
381	tgen_arithi(s, ARITH_ADD, reg, val);
382	}
383
384	#ifdef VBOX
385	void tcg_out_subi(TCGContext *s, int reg, tcg_target_long val)
386	{
387	if (val != 0)
388	tgen_arithi(s, ARITH_SUB, reg, val);
389	}
390	#endif
391
392	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
393	{
394	int32_t val, val1;
395	TCGLabel *l = &s->labels[label_index];
396
397	if (l->has_value) {
398	val = l->u.value - (tcg_target_long)s->code_ptr;
399	val1 = val - 2;
400	if ((int8_t)val1 == val1) {
401	if (opc == -1)
402	tcg_out8(s, 0xeb);
403	else
404	tcg_out8(s, 0x70 + opc);
405	tcg_out8(s, val1);
406	} else {
407	if (opc == -1) {
408	tcg_out8(s, 0xe9);
409	tcg_out32(s, val - 5);
410	} else {
411	tcg_out8(s, 0x0f);
412	tcg_out8(s, 0x80 + opc);
413	tcg_out32(s, val - 6);
414	}
415	}
416	} else {
417	if (opc == -1) {
418	tcg_out8(s, 0xe9);
419	} else {
420	tcg_out8(s, 0x0f);
421	tcg_out8(s, 0x80 + opc);
422	}
423	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
424	s->code_ptr += 4;
425	}
426	}
427
428	static void tcg_out_brcond(TCGContext *s, int cond,
429	TCGArg arg1, TCGArg arg2, int const_arg2,
430	int label_index)
431	{
432	if (const_arg2) {
433	if (arg2 == 0) {
434	/* test r, r */
435	tcg_out_modrm(s, 0x85, arg1, arg1);
436	} else {
437	tgen_arithi(s, ARITH_CMP, arg1, arg2);
438	}
439	} else {
440	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3), arg2, arg1);
441	}
442	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
443	}
444
445	#ifdef VBOX
446	DECLINLINE(void)
447	tcg_out_long_call(TCGContext s, void dst)
448	{
449	intptr_t disp;
450	# ifdef VBOX
451	tcg_gen_stack_alignment_check(s);
452	# endif
453	disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
454	tcg_out8(s, 0xe8); /* call disp32 */
455	tcg_out32(s, disp); /* disp32 */
456	}
457	DECLINLINE(void)
458	tcg_out_long_jmp(TCGContext s, void dst)
459	{
460	intptr_t disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
461	tcg_out8(s, 0xe9); /* jmp disp32 */
462	tcg_out32(s, disp); /* disp32 */
463	}
464	#endif /* VBOX */
465
466
467	/* XXX: we implement it at the target level to avoid having to
468	handle cross basic blocks temporaries */
469	static void tcg_out_brcond2(TCGContext *s,
470	const TCGArg args, const int const_args)
471	{
472	int label_next;
473	label_next = gen_new_label();
474	switch(args[4]) {
475	case TCG_COND_EQ:
476	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
477	tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
478	break;
479	case TCG_COND_NE:
480	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
481	tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
482	break;
483	case TCG_COND_LT:
484	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
485	tcg_out_jxx(s, JCC_JNE, label_next);
486	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
487	break;
488	case TCG_COND_LE:
489	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
490	tcg_out_jxx(s, JCC_JNE, label_next);
491	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
492	break;
493	case TCG_COND_GT:
494	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
495	tcg_out_jxx(s, JCC_JNE, label_next);
496	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
497	break;
498	case TCG_COND_GE:
499	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
500	tcg_out_jxx(s, JCC_JNE, label_next);
501	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
502	break;
503	case TCG_COND_LTU:
504	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
505	tcg_out_jxx(s, JCC_JNE, label_next);
506	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
507	break;
508	case TCG_COND_LEU:
509	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
510	tcg_out_jxx(s, JCC_JNE, label_next);
511	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
512	break;
513	case TCG_COND_GTU:
514	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
515	tcg_out_jxx(s, JCC_JNE, label_next);
516	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
517	break;
518	case TCG_COND_GEU:
519	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
520	tcg_out_jxx(s, JCC_JNE, label_next);
521	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
522	break;
523	default:
524	tcg_abort();
525	}
526	tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
527	}
528
529	#if defined(CONFIG_SOFTMMU)
530
531	#include "../../softmmu_defs.h"
532
533	static void *qemu_ld_helpers[4] = {
534	__ldb_mmu,
535	__ldw_mmu,
536	__ldl_mmu,
537	__ldq_mmu,
538	};
539
540	static void *qemu_st_helpers[4] = {
541	__stb_mmu,
542	__stw_mmu,
543	__stl_mmu,
544	__stq_mmu,
545	};
546	#endif
547
548	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
549	static void *vbox_ld_helpers[] = {
550	__ldub_vbox_phys,
551	__lduw_vbox_phys,
552	__ldul_vbox_phys,
553	__ldq_vbox_phys,
554	__ldb_vbox_phys,
555	__ldw_vbox_phys,
556	__ldl_vbox_phys,
557	__ldq_vbox_phys,
558	};
559
560	static void *vbox_st_helpers[] = {
561	__stb_vbox_phys,
562	__stw_vbox_phys,
563	__stl_vbox_phys,
564	__stq_vbox_phys
565	};
566
567	static void tcg_out_vbox_phys_read(TCGContext *s, int index,
568	int addr_reg,
569	int data_reg, int data_reg2)
570	{
571	int useReg2 = ((index & 3) == 3);
572
573	/** @todo: should we make phys address accessors fastcalls - probably not a big deal */
574	/* out parameter (address), note that phys address is always 64-bit */
575	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
576
577	#if 0
578	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
579	tcg_out_push(s, addr_reg);
580	#else
581	/* mov addr_reg, %eax */
582	tcg_out_mov(s, TCG_REG_EAX, addr_reg);
583	#endif
584
585	tcg_out_long_call(s, vbox_ld_helpers[index]);
586
587	/* mov %eax, data_reg */
588	tcg_out_mov(s, data_reg, TCG_REG_EAX);
589
590	/* returned 64-bit value */
591	if (useReg2)
592	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
593	}
594
595	static void tcg_out_vbox_phys_write(TCGContext *s, int index,
596	int addr_reg,
597	int val_reg, int val_reg2) {
598	int useReg2 = ((index & 3) == 3);
599
600	#if 0
601	/* out parameter (value2) */
602	if (useReg2)
603	tcg_out_push(s, val_reg2);
604	/* out parameter (value) */
605	tcg_out_push(s, val_reg);
606	/* out parameter (address), note that phys address is always 64-bit */
607	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
608	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
609	tcg_out_push(s, addr_reg);
610	#else
611	Assert(val_reg != TCG_REG_EAX && (!useReg2 \|\| (val_reg2 != TCG_REG_EAX)));
612	/* mov addr_reg, %eax */
613	tcg_out_mov(s, TCG_REG_EAX, addr_reg);
614	Assert(!useReg2 \|\| (val_reg2 != TCG_REG_EDX));
615	/* mov val_reg, %edx */
616	tcg_out_mov(s, TCG_REG_EDX, val_reg);
617	if (useReg2)
618	tcg_out_mov(s, TCG_REG_ECX, val_reg2);
619
620	#endif
621	/* call it */
622	tcg_out_long_call(s, vbox_st_helpers[index]);
623
624	/* clean stack after us */
625	#if 0
626	tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
627	# endif
628	}
629
630	#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
631
632	/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
633	EAX. It will be useful once fixed registers globals are less
634	common. */
635	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
636	int opc)
637	{
638	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
639	#if defined(CONFIG_SOFTMMU)
640	uint8_t label1_ptr, label2_ptr;
641	#endif
642	#if TARGET_LONG_BITS == 64
643	#if defined(CONFIG_SOFTMMU)
644	uint8_t *label3_ptr;
645	#endif
646	int addr_reg2;
647	#endif
648
649	data_reg = *args++;
650	if (opc == 3)
651	data_reg2 = *args++;
652	else
653	data_reg2 = 0;
654	addr_reg = *args++;
655	#if TARGET_LONG_BITS == 64
656	addr_reg2 = *args++;
657	#endif
658	mem_index = *args;
659	s_bits = opc & 3;
660
661	r0 = TCG_REG_EAX;
662	r1 = TCG_REG_EDX;
663
664	#if defined(CONFIG_SOFTMMU)
665	tcg_out_mov(s, r1, addr_reg);
666
667	tcg_out_mov(s, r0, addr_reg);
668
669	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
670	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
671
672	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
673	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
674
675	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
676	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
677
678	#ifndef VBOX
679	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
680	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
681	tcg_out8(s, (5 << 3) \| r1);
682	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
683	#else
684	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
685	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
686	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
687	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
688	#endif
689
690	/* cmp 0(r1), r0 */
691	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
692
693	tcg_out_mov(s, r0, addr_reg);
694
695	#if TARGET_LONG_BITS == 32
696	/* je label1 */
697	tcg_out8(s, 0x70 + JCC_JE);
698	label1_ptr = s->code_ptr;
699	s->code_ptr++;
700	#else
701	/* jne label3 */
702	tcg_out8(s, 0x70 + JCC_JNE);
703	label3_ptr = s->code_ptr;
704	s->code_ptr++;
705
706	/* cmp 4(r1), addr_reg2 */
707	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
708
709	/* je label1 */
710	tcg_out8(s, 0x70 + JCC_JE);
711	label1_ptr = s->code_ptr;
712	s->code_ptr++;
713
714	/* label3: */
715	*label3_ptr = s->code_ptr - label3_ptr - 1;
716	#endif
717
718	/* XXX: move that code at the end of the TB */
719	#if TARGET_LONG_BITS == 32
720	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
721	#else
722	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
723	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
724	#endif
725	#ifdef VBOX
726	tcg_gen_stack_alignment_check(s);
727	#endif
728	tcg_out8(s, 0xe8);
729	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
730	(tcg_target_long)s->code_ptr - 4);
731
732	switch(opc) {
733	case 0 \| 4:
734	/* movsbl */
735	tcg_out_modrm(s, 0xbe \| P_EXT, data_reg, TCG_REG_EAX);
736	break;
737	case 1 \| 4:
738	/* movswl */
739	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, TCG_REG_EAX);
740	break;
741	case 0:
742	case 1:
743	case 2:
744	default:
745	tcg_out_mov(s, data_reg, TCG_REG_EAX);
746	break;
747	case 3:
748	if (data_reg == TCG_REG_EDX) {
749	tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
750	tcg_out_mov(s, data_reg2, TCG_REG_EAX);
751	} else {
752	tcg_out_mov(s, data_reg, TCG_REG_EAX);
753	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
754	}
755	break;
756	}
757
758	/* jmp label2 */
759	tcg_out8(s, 0xeb);
760	label2_ptr = s->code_ptr;
761	s->code_ptr++;
762
763	/* label1: */
764	*label1_ptr = s->code_ptr - label1_ptr - 1;
765
766	/* add x(r1), r0 */
767	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
768	offsetof(CPUTLBEntry, addr_read));
769	#else
770	r0 = addr_reg;
771	#endif
772
773	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
774	#ifdef TARGET_WORDS_BIGENDIAN
775	bswap = 1;
776	#else
777	bswap = 0;
778	#endif
779	switch(opc) {
780	case 0:
781	/* movzbl */
782	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
783	break;
784	case 0 \| 4:
785	/* movsbl */
786	tcg_out_modrm_offset(s, 0xbe \| P_EXT, data_reg, r0, 0);
787	break;
788	case 1:
789	/* movzwl */
790	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
791	if (bswap) {
792	/* rolw $8, data_reg */
793	tcg_out8(s, 0x66);
794	tcg_out_modrm(s, 0xc1, 0, data_reg);
795	tcg_out8(s, 8);
796	}
797	break;
798	case 1 \| 4:
799	/* movswl */
800	tcg_out_modrm_offset(s, 0xbf \| P_EXT, data_reg, r0, 0);
801	if (bswap) {
802	/* rolw $8, data_reg */
803	tcg_out8(s, 0x66);
804	tcg_out_modrm(s, 0xc1, 0, data_reg);
805	tcg_out8(s, 8);
806
807	/* movswl data_reg, data_reg */
808	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, data_reg);
809	}
810	break;
811	case 2:
812	/* movl (r0), data_reg */
813	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
814	if (bswap) {
815	/* bswap */
816	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
817	}
818	break;
819	case 3:
820	/* XXX: could be nicer */
821	if (r0 == data_reg) {
822	r1 = TCG_REG_EDX;
823	if (r1 == data_reg)
824	r1 = TCG_REG_EAX;
825	tcg_out_mov(s, r1, r0);
826	r0 = r1;
827	}
828	if (!bswap) {
829	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
830	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
831	} else {
832	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
833	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
834
835	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
836	/* bswap */
837	tcg_out_opc(s, (0xc8 + data_reg2) \| P_EXT);
838	}
839	break;
840	default:
841	tcg_abort();
842	}
843	#else /* VBOX */
844	tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
845	#endif
846
847
848	#if defined(CONFIG_SOFTMMU)
849	/* label2: */
850	*label2_ptr = s->code_ptr - label2_ptr - 1;
851	# ifdef VBOX
852	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
853	# endif
854	#endif
855	}
856
857
858	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
859	int opc)
860	{
861	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
862	#if defined(CONFIG_SOFTMMU)
863	uint8_t label1_ptr, label2_ptr;
864	#endif
865	#if TARGET_LONG_BITS == 64
866	#if defined(CONFIG_SOFTMMU)
867	uint8_t *label3_ptr;
868	#endif
869	int addr_reg2;
870	#endif
871	#ifdef VBOX
872	# ifdef RT_OS_DARWIN
873	int bias1 = 12, bias3 = 4;/** @todo TCG_TARGET_STACK_ALIGN. */
874	# else
875	int bias1 = 0, bias3 = 0;
876	# endif
877	NOREF(bias3);
878	#endif
879
880	data_reg = *args++;
881	if (opc == 3)
882	data_reg2 = *args++;
883	else
884	data_reg2 = 0;
885	addr_reg = *args++;
886	#if TARGET_LONG_BITS == 64
887	addr_reg2 = *args++;
888	#endif
889	mem_index = *args;
890
891	s_bits = opc;
892
893	r0 = TCG_REG_EAX;
894	r1 = TCG_REG_EDX;
895
896	#if defined(CONFIG_SOFTMMU)
897	tcg_out_mov(s, r1, addr_reg);
898
899	tcg_out_mov(s, r0, addr_reg);
900
901	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
902	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
903
904	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
905	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
906
907	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
908	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
909
910	#ifndef VBOX
911	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
912	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
913	tcg_out8(s, (5 << 3) \| r1);
914	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
915	#else
916	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
917	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
918	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
919	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
920	#endif
921
922	/* cmp 0(r1), r0 */
923	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
924
925	tcg_out_mov(s, r0, addr_reg);
926
927	#if TARGET_LONG_BITS == 32
928	/* je label1 */
929	tcg_out8(s, 0x70 + JCC_JE);
930	label1_ptr = s->code_ptr;
931	s->code_ptr++;
932	#else
933	/* jne label3 */
934	tcg_out8(s, 0x70 + JCC_JNE);
935	label3_ptr = s->code_ptr;
936	s->code_ptr++;
937
938	/* cmp 4(r1), addr_reg2 */
939	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
940
941	/* je label1 */
942	tcg_out8(s, 0x70 + JCC_JE);
943	label1_ptr = s->code_ptr;
944	s->code_ptr++;
945
946	/* label3: */
947	*label3_ptr = s->code_ptr - label3_ptr - 1;
948	#endif
949
950	/* XXX: move that code at the end of the TB */
951	#if TARGET_LONG_BITS == 32
952	if (opc == 3) {
953	tcg_out_mov(s, TCG_REG_EDX, data_reg);
954	tcg_out_mov(s, TCG_REG_ECX, data_reg2);
955	#ifdef VBOX
956	tcg_out_subi(s, TCG_REG_ESP, bias1);
957	#endif
958	tcg_out8(s, 0x6a); /* push Ib */
959	tcg_out8(s, mem_index);
960	# ifdef VBOX
961	tcg_gen_stack_alignment_check(s);
962	# endif
963	tcg_out8(s, 0xe8);
964	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
965	(tcg_target_long)s->code_ptr - 4);
966	#ifdef VBOX
967	tcg_out_addi(s, TCG_REG_ESP, 4+bias1);
968	#else
969	tcg_out_addi(s, TCG_REG_ESP, 4);
970	#endif
971	} else {
972	switch(opc) {
973	case 0:
974	/* movzbl */
975	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_EDX, data_reg);
976	break;
977	case 1:
978	/* movzwl */
979	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_EDX, data_reg);
980	break;
981	case 2:
982	tcg_out_mov(s, TCG_REG_EDX, data_reg);
983	break;
984	}
985	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
986	# ifdef VBOX
987	tcg_gen_stack_alignment_check(s);
988	# endif
989	tcg_out8(s, 0xe8);
990	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
991	(tcg_target_long)s->code_ptr - 4);
992	}
993	#else
994	if (opc == 3) {
995	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
996	# ifdef VBOX
997	tcg_out_subi(s, TCG_REG_ESP, bias3);
998	# endif
999	tcg_out8(s, 0x6a); /* push Ib */
1000	tcg_out8(s, mem_index);
1001	tcg_out_opc(s, 0x50 + data_reg2); /* push */
1002	tcg_out_opc(s, 0x50 + data_reg); /* push */
1003	# ifdef VBOX
1004	tcg_gen_stack_alignment_check(s);
1005	# endif
1006	tcg_out8(s, 0xe8);
1007	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
1008	(tcg_target_long)s->code_ptr - 4);
1009	#ifdef VBOX
1010	tcg_out_addi(s, TCG_REG_ESP, 12+bias3);
1011	#else
1012	tcg_out_addi(s, TCG_REG_ESP, 12);
1013	#endif
1014	} else {
1015	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
1016	switch(opc) {
1017	case 0:
1018	/* movzbl */
1019	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_ECX, data_reg);
1020	break;
1021	case 1:
1022	/* movzwl */
1023	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_ECX, data_reg);
1024	break;
1025	case 2:
1026	tcg_out_mov(s, TCG_REG_ECX, data_reg);
1027	break;
1028	}
1029	# ifdef VBOX
1030	tcg_out_subi(s, TCG_REG_ESP, bias1);
1031	# endif
1032	tcg_out8(s, 0x6a); /* push Ib */
1033	tcg_out8(s, mem_index);
1034	# ifdef VBOX
1035	tcg_gen_stack_alignment_check(s);
1036	# endif
1037
1038	tcg_out8(s, 0xe8);
1039	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
1040	(tcg_target_long)s->code_ptr - 4);
1041	# if defined(VBOX)
1042	tcg_out_addi(s, TCG_REG_ESP, 4 + bias1);
1043	# else
1044	tcg_out_addi(s, TCG_REG_ESP, 4);
1045	# endif
1046	}
1047	#endif
1048
1049	/* jmp label2 */
1050	tcg_out8(s, 0xeb);
1051	label2_ptr = s->code_ptr;
1052	s->code_ptr++;
1053
1054	/* label1: */
1055	*label1_ptr = s->code_ptr - label1_ptr - 1;
1056
1057	/* add x(r1), r0 */
1058	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
1059	offsetof(CPUTLBEntry, addr_write));
1060	#else
1061	r0 = addr_reg;
1062	#endif
1063
1064	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
1065	#ifdef TARGET_WORDS_BIGENDIAN
1066	bswap = 1;
1067	#else
1068	bswap = 0;
1069	#endif
1070	switch(opc) {
1071	case 0:
1072	/* movb */
1073	tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
1074	break;
1075	case 1:
1076	if (bswap) {
1077	tcg_out_mov(s, r1, data_reg);
1078	tcg_out8(s, 0x66); /* rolw $8, %ecx */
1079	tcg_out_modrm(s, 0xc1, 0, r1);
1080	tcg_out8(s, 8);
1081	data_reg = r1;
1082	}
1083	/* movw */
1084	tcg_out8(s, 0x66);
1085	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1086	break;
1087	case 2:
1088	if (bswap) {
1089	tcg_out_mov(s, r1, data_reg);
1090	/* bswap data_reg */
1091	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1092	data_reg = r1;
1093	}
1094	/* movl */
1095	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1096	break;
1097	case 3:
1098	if (bswap) {
1099	tcg_out_mov(s, r1, data_reg2);
1100	/* bswap data_reg */
1101	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1102	tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1103	tcg_out_mov(s, r1, data_reg);
1104	/* bswap data_reg */
1105	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1106	tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1107	} else {
1108	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1109	tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1110	}
1111	break;
1112	default:
1113	tcg_abort();
1114	}
1115	#else
1116	tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1117	#endif
1118
1119	#if defined(CONFIG_SOFTMMU)
1120	/* label2: */
1121	*label2_ptr = s->code_ptr - label2_ptr - 1;
1122	# ifdef VBOX
1123	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
1124	# endif
1125	#endif
1126	}
1127
1128	#ifndef VBOX
1129	static inline void tcg_out_op(TCGContext *s, int opc,
1130	#else /* VBOX */
1131	DECLINLINE(void) tcg_out_op(TCGContext *s, int opc,
1132	#endif /* VBOX */
1133	const TCGArg args, const int const_args)
1134	{
1135	int c;
1136
1137	switch(opc) {
1138	case INDEX_op_exit_tb:
1139	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1140	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1141	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1142	break;
1143	case INDEX_op_goto_tb:
1144	if (s->tb_jmp_offset) {
1145	/* direct jump method */
1146	tcg_out8(s, 0xe9); /* jmp im */
1147	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1148	tcg_out32(s, 0);
1149	} else {
1150	/* indirect jump method */
1151	/* jmp Ev */
1152	tcg_out_modrm_offset(s, 0xff, 4, -1,
1153	(tcg_target_long)(s->tb_next + args[0]));
1154	}
1155	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1156	break;
1157	case INDEX_op_call:
1158	#ifdef VBOX
1159	tcg_gen_stack_alignment_check(s);
1160	#endif
1161	if (const_args[0]) {
1162	tcg_out8(s, 0xe8);
1163	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1164	} else {
1165	tcg_out_modrm(s, 0xff, 2, args[0]);
1166	}
1167	break;
1168	case INDEX_op_jmp:
1169	if (const_args[0]) {
1170	tcg_out8(s, 0xe9);
1171	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1172	} else {
1173	tcg_out_modrm(s, 0xff, 4, args[0]);
1174	}
1175	break;
1176	case INDEX_op_br:
1177	tcg_out_jxx(s, JCC_JMP, args[0]);
1178	break;
1179	case INDEX_op_movi_i32:
1180	tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1181	break;
1182	case INDEX_op_ld8u_i32:
1183	/* movzbl */
1184	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1185	break;
1186	case INDEX_op_ld8s_i32:
1187	/* movsbl */
1188	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1189	break;
1190	case INDEX_op_ld16u_i32:
1191	/* movzwl */
1192	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1193	break;
1194	case INDEX_op_ld16s_i32:
1195	/* movswl */
1196	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1197	break;
1198	case INDEX_op_ld_i32:
1199	/* movl */
1200	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1201	break;
1202	case INDEX_op_st8_i32:
1203	/* movb */
1204	tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1205	break;
1206	case INDEX_op_st16_i32:
1207	/* movw */
1208	tcg_out8(s, 0x66);
1209	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1210	break;
1211	case INDEX_op_st_i32:
1212	/* movl */
1213	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1214	break;
1215	case INDEX_op_sub_i32:
1216	c = ARITH_SUB;
1217	goto gen_arith;
1218	case INDEX_op_and_i32:
1219	c = ARITH_AND;
1220	goto gen_arith;
1221	case INDEX_op_or_i32:
1222	c = ARITH_OR;
1223	goto gen_arith;
1224	case INDEX_op_xor_i32:
1225	c = ARITH_XOR;
1226	goto gen_arith;
1227	case INDEX_op_add_i32:
1228	c = ARITH_ADD;
1229	gen_arith:
1230	if (const_args[2]) {
1231	tgen_arithi(s, c, args[0], args[2]);
1232	} else {
1233	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1234	}
1235	break;
1236	case INDEX_op_mul_i32:
1237	if (const_args[2]) {
1238	int32_t val;
1239	val = args[2];
1240	if (val == (int8_t)val) {
1241	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1242	tcg_out8(s, val);
1243	} else {
1244	tcg_out_modrm(s, 0x69, args[0], args[0]);
1245	tcg_out32(s, val);
1246	}
1247	} else {
1248	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1249	}
1250	break;
1251	case INDEX_op_mulu2_i32:
1252	tcg_out_modrm(s, 0xf7, 4, args[3]);
1253	break;
1254	case INDEX_op_div2_i32:
1255	tcg_out_modrm(s, 0xf7, 7, args[4]);
1256	break;
1257	case INDEX_op_divu2_i32:
1258	tcg_out_modrm(s, 0xf7, 6, args[4]);
1259	break;
1260	case INDEX_op_shl_i32:
1261	c = SHIFT_SHL;
1262	gen_shift32:
1263	if (const_args[2]) {
1264	if (args[2] == 1) {
1265	tcg_out_modrm(s, 0xd1, c, args[0]);
1266	} else {
1267	tcg_out_modrm(s, 0xc1, c, args[0]);
1268	tcg_out8(s, args[2]);
1269	}
1270	} else {
1271	tcg_out_modrm(s, 0xd3, c, args[0]);
1272	}
1273	break;
1274	case INDEX_op_shr_i32:
1275	c = SHIFT_SHR;
1276	goto gen_shift32;
1277	case INDEX_op_sar_i32:
1278	c = SHIFT_SAR;
1279	goto gen_shift32;
1280
1281	case INDEX_op_add2_i32:
1282	if (const_args[4])
1283	tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1284	else
1285	tcg_out_modrm(s, 0x01 \| (ARITH_ADD << 3), args[4], args[0]);
1286	if (const_args[5])
1287	tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1288	else
1289	tcg_out_modrm(s, 0x01 \| (ARITH_ADC << 3), args[5], args[1]);
1290	break;
1291	case INDEX_op_sub2_i32:
1292	if (const_args[4])
1293	tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1294	else
1295	tcg_out_modrm(s, 0x01 \| (ARITH_SUB << 3), args[4], args[0]);
1296	if (const_args[5])
1297	tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1298	else
1299	tcg_out_modrm(s, 0x01 \| (ARITH_SBB << 3), args[5], args[1]);
1300	break;
1301	case INDEX_op_brcond_i32:
1302	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1303	break;
1304	case INDEX_op_brcond2_i32:
1305	tcg_out_brcond2(s, args, const_args);
1306	break;
1307
1308	case INDEX_op_qemu_ld8u:
1309	tcg_out_qemu_ld(s, args, 0);
1310	break;
1311	case INDEX_op_qemu_ld8s:
1312	tcg_out_qemu_ld(s, args, 0 \| 4);
1313	break;
1314	case INDEX_op_qemu_ld16u:
1315	tcg_out_qemu_ld(s, args, 1);
1316	break;
1317	case INDEX_op_qemu_ld16s:
1318	tcg_out_qemu_ld(s, args, 1 \| 4);
1319	break;
1320	case INDEX_op_qemu_ld32u:
1321	tcg_out_qemu_ld(s, args, 2);
1322	break;
1323	case INDEX_op_qemu_ld64:
1324	tcg_out_qemu_ld(s, args, 3);
1325	break;
1326
1327	case INDEX_op_qemu_st8:
1328	tcg_out_qemu_st(s, args, 0);
1329	break;
1330	case INDEX_op_qemu_st16:
1331	tcg_out_qemu_st(s, args, 1);
1332	break;
1333	case INDEX_op_qemu_st32:
1334	tcg_out_qemu_st(s, args, 2);
1335	break;
1336	case INDEX_op_qemu_st64:
1337	tcg_out_qemu_st(s, args, 3);
1338	break;
1339
1340	default:
1341	tcg_abort();
1342	}
1343	}
1344
1345	static const TCGTargetOpDef x86_op_defs[] = {
1346	{ INDEX_op_exit_tb, {"", "" } },
1347	{ INDEX_op_goto_tb, {"", "" } },
1348	{ INDEX_op_call, { "ri", "", } },
1349	{ INDEX_op_jmp, { "ri", ""} },
1350	{ INDEX_op_br, {"", "" } },
1351	{ INDEX_op_mov_i32, { "r", "r" } },
1352	{ INDEX_op_movi_i32, { "r" } },
1353	{ INDEX_op_ld8u_i32, { "r", "r" } },
1354	{ INDEX_op_ld8s_i32, { "r", "r" } },
1355	{ INDEX_op_ld16u_i32, { "r", "r" } },
1356	{ INDEX_op_ld16s_i32, { "r", "r" } },
1357	{ INDEX_op_ld_i32, { "r", "r" } },
1358	{ INDEX_op_st8_i32, { "q", "r" } },
1359	{ INDEX_op_st16_i32, { "r", "r" } },
1360	{ INDEX_op_st_i32, { "r", "r" } },
1361
1362	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1363	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1364	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1365	{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1366	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1367	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1368	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1369	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1370	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1371
1372	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1373	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1374	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1375
1376	{ INDEX_op_brcond_i32, { "r", "ri" } },
1377
1378	{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1379	{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1380	{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1381
1382	#if TARGET_LONG_BITS == 32
1383	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1384	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1385	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1386	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1387	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1388	{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
1389
1390	{ INDEX_op_qemu_st8, { "cb", "L" } },
1391	{ INDEX_op_qemu_st16, { "L", "L" } },
1392	{ INDEX_op_qemu_st32, { "L", "L" } },
1393	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1394	#else
1395	{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1396	{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1397	{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1398	{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1399	{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1400	{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1401
1402	{ INDEX_op_qemu_st8, { "cb", "L", "L" } },
1403	{ INDEX_op_qemu_st16, { "L", "L", "L" } },
1404	{ INDEX_op_qemu_st32, { "L", "L", "L" } },
1405	{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1406	#endif
1407	#ifndef VBOX
1408	{ -1 },
1409	#else
1410	{ -1, {"", "", "", ""} },
1411	#endif
1412	};
1413
1414	static int tcg_target_callee_save_regs[] = {
1415	#ifndef VBOX
1416	/* TCG_REG_EBP, / / currently used for the global env, so no
1417	need to save */
1418	TCG_REG_EBX,
1419	TCG_REG_ESI,
1420	TCG_REG_EDI,
1421	#else
1422	TCG_REG_EBP,
1423	TCG_REG_EBX,
1424	/* TCG_REG_ESI, / / currently used for the global env, so no
1425	need to save */
1426	TCG_REG_EDI,
1427	#endif
1428	};
1429
1430	/* Generate global QEMU prologue and epilogue code */
1431	void tcg_target_qemu_prologue(TCGContext *s)
1432	{
1433	int i, frame_size, push_size, stack_addend;
1434
1435	/* TB prologue */
1436	/* save all callee saved registers */
1437	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1438	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1439	}
1440	/* reserve some stack space */
1441	push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1442	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1443	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1444	~(TCG_TARGET_STACK_ALIGN - 1);
1445	stack_addend = frame_size - push_size;
1446	tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1447	# ifdef VBOX
1448	tcg_gen_stack_alignment_check(s);
1449	# endif
1450
1451	tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp %eax /
1452
1453	/* TB epilogue */
1454	tb_ret_addr = s->code_ptr;
1455	tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1456	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1457	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1458	}
1459	tcg_out8(s, 0xc3); /* ret */
1460	}
1461
1462	void tcg_target_init(TCGContext *s)
1463	{
1464	/* fail safe */
1465	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1466	tcg_abort();
1467
1468	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1469	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1470	(1 << TCG_REG_EAX) \|
1471	(1 << TCG_REG_EDX) \|
1472	(1 << TCG_REG_ECX));
1473
1474	tcg_regset_clear(s->reserved_regs);
1475	tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1476
1477	tcg_add_target_add_op_defs(x86_op_defs);
1478	}

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source: vbox/trunk/src/recompiler/tcg/i386/tcg-target.c@ 33540

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